diff --git a/.clang-format b/.clang-format new file mode 100644 index 00000000..2f21db8e --- /dev/null +++ b/.clang-format @@ -0,0 +1,399 @@ +# Made by: Ingmar Delsink +# https://ingmar.dels.ink +# See http://clang.llvm.org/docs/ClangFormatStyleOptions.html +# Tested with: clang-format version 3.7.1 + +# General +######### + +# The style used for all options not specifically set in the configuration. +# This option is supported only in the clang-format configuration (both within -style='{...}' and the .clang-format file). +# Possible values: +# LLVM A style complying with the LLVM coding standards +# Google A style complying with Google’s C++ style guide +# Chromium A style complying with Chromium’s style guide +# Mozilla A style complying with Mozilla’s style guide +# WebKit A style complying with WebKit’s style guide +#BasedOnStyle: + +# TabWidth (unsigned) +# The number of columns used for tab stops. +TabWidth: 4 + +# IndentWidth (unsigned) +# The number of columns to use for indentation. +IndentWidth: 4 + +# UseTab (UseTabStyle) +# The way to use tab characters in the resulting file. +# Possible values: +# UT_Never (in configuration: Never) Never use tab. +# UT_ForIndentation (in configuration: ForIndentation) Use tabs only for indentation. +# UT_Always (in configuration: Always) Use tabs whenever we need to fill whitespace that spans at least from one tab stop to the next one. +UseTab: Never + +# C++ +##### + +# Language (LanguageKind) +# Language, this format style is targeted at. +# Possible values: +# LK_None (in configuration: None) Do not use. +# LK_Cpp (in configuration: Cpp) Should be used for C, C++, ObjectiveC, ObjectiveC++. +# LK_Java (in configuration: Java) Should be used for Java. +# LK_JavaScript (in configuration: JavaScript) Should be used for JavaScript. +# LK_Proto (in configuration: Proto) Should be used for Protocol Buffers (https://developers.google.com/protocol-buffers/). +# LK_TableGen (in configuration: TableGen) Should be used for TableGen code. +Language: Cpp + +# Standard (LanguageStandard) +# Format compatible with this standard, e.g. use A > instead of A> for LS_Cpp03. +# Possible values: +# LS_Cpp03 (in configuration: Cpp03) Use C++03-compatible syntax. +# LS_Cpp11 (in configuration: Cpp11) Use features of C++11 (e.g. A> instead of A >). +# LS_Auto (in configuration: Auto) Automatic detection based on the input. +Standard: Cpp11 + +# Pointer and reference alignment style. Possible values: Left, Right, Middle. +PointerAlignment: Right + +# AccessModifierOffset (int) +# The extra indent or outdent of access modifiers, e.g. public:. +AccessModifierOffset: 0 + +# AlignAfterOpenBracket (BracketAlignmentStyle) +# If true, horizontally aligns arguments after an open bracket. +# This applies to round brackets (parentheses), angle brackets and square brackets. +# Possible values: +# BAS_Align (in configuration: Align) Align parameters on the open bracket, e.g.: +# someLongFunction(argument1, +# argument2); +# BAS_DontAlign (in configuration: DontAlign) Don’t align, instead use ContinuationIndentWidth, e.g.: +# someLongFunction(argument1, +# argument2); +# BAS_AlwaysBreak (in configuration: AlwaysBreak) Always break after an open bracket, if the parameters don’t fit on a single line, e.g.: +# someLongFunction( +# argument1, argument2); +AlignAfterOpenBracket: Align + +# AlignConsecutiveAssignments (bool) +# If true, aligns consecutive assignments. +# This will align the assignment operators of consecutive lines. This will result in formattings like +# int aaaa = 12; +# int b = 23; +# int ccc = 23; +AlignConsecutiveAssignments: false + +# AlignEscapedNewlinesLeft (bool) +# If true, aligns escaped newlines as far left as possible. Otherwise puts them into the right-most column. +AlignEscapedNewlinesLeft: true + +# AlignOperands (bool) +# If true, horizontally align operands of binary and ternary expressions. +# Specifically, this aligns operands of a single expression that needs to be split over multiple lines, e.g.: +# int aaa = bbbbbbbbbbbbbbb + +# ccccccccccccccc; +AlignOperands: false + +# AlignTrailingComments (bool) +# If true, aligns trailing comments. +AlignTrailingComments: true + +# AllowAllParametersOfDeclarationOnNextLine (bool) +# Allow putting all parameters of a function declaration onto the next line even if BinPackParameters is false. +AllowAllParametersOfDeclarationOnNextLine: false + +# AllowShortBlocksOnASingleLine (bool) +# Allows contracting simple braced statements to a single line. +AllowShortBlocksOnASingleLine: false + +# AllowShortCaseLabelsOnASingleLine (bool) +# If true, short case labels will be contracted to a single line. +AllowShortCaseLabelsOnASingleLine: true + +# AllowShortFunctionsOnASingleLine (ShortFunctionStyle) +# Dependent on the value, int f() { return 0; } can be put on a single line. +# Possible values: +# SFS_None (in configuration: None) Never merge functions into a single line. +# SFS_Empty (in configuration: Empty) Only merge empty functions. +# SFS_Inline (in configuration: Inline) Only merge functions defined inside a class. Implies “empty”. +# SFS_All (in configuration: All) Merge all functions fitting on a single line. +AllowShortFunctionsOnASingleLine: false + +# AllowShortIfStatementsOnASingleLine (bool) +# If true, if (a) return; can be put on a single line. +AllowShortIfStatementsOnASingleLine: false + +# AllowShortLoopsOnASingleLine (bool) +# If true, while (true) continue; can be put on a single line. +AllowShortLoopsOnASingleLine: false + +# AlwaysBreakBeforeMultilineStrings (bool) +# If true, always break before multiline string literals. +# This flag is mean to make cases where there are multiple multiline strings in a file look more consistent. Thus, it will only take effect if wrapping the string at that point leads to it being indented ContinuationIndentWidth spaces from the start of the line. +AlwaysBreakBeforeMultilineStrings: false + +# AlwaysBreakTemplateDeclarations (bool) +# If true, always break after the template<...> of a template declaration. +AlwaysBreakTemplateDeclarations: false + +# BinPackArguments (bool) +# If false, a function call’s arguments will either be all on the same line or will have one line each. +#BinPackArguments: false + +# BinPackParameters (bool) +# If false, a function declaration’s or function definition’s parameters will either all be on the same line or will have one line each. +BinPackParameters: false + +# BraceWrapping (BraceWrappingFlags) +# Control of individual brace wrapping cases. +# If BreakBeforeBraces is set to BS_Custom, use this to specify how each individual brace case should be handled. Otherwise, this is ignored. +# Nested configuration flags: +# bool AfterClass Wrap class definitions. +# bool AfterControlStatement Wrap control statements (if/for/while/switch/..). +# bool AfterEnum Wrap enum definitions. +# bool AfterFunction Wrap function definitions. +# bool AfterNamespace Wrap namespace definitions. +# bool AfterObjCDeclaration Wrap ObjC definitions (@autoreleasepool, interfaces, ..). +# bool AfterStruct Wrap struct definitions. +# bool AfterUnion Wrap union definitions. +# bool BeforeCatch Wrap before catch. +# bool BeforeElse Wrap before else. +# bool IndentBraces Indent the wrapped braces themselves. +#BraceWrapping: + +# BreakAfterJavaFieldAnnotations (bool) +# Break after each annotation on a field in Java files. +#BreakAfterJavaFieldAnnotations: + +# BreakBeforeBinaryOperators (BinaryOperatorStyle) +# The way to wrap binary operators. +# Possible values: +# BOS_None (in configuration: None) Break after operators. +# BOS_NonAssignment (in configuration: NonAssignment) Break before operators that aren’t assignments. +# BOS_All (in configuration: All) Break before operators. +BreakBeforeBinaryOperators: false + +# BreakBeforeBraces (BraceBreakingStyle) +# The brace breaking style to use. +# Possible values: +# BS_Attach (in configuration: Attach) Always attach braces to surrounding context. +# BS_Linux (in configuration: Linux) Like Attach, but break before braces on function, namespace and class definitions. +# BS_Mozilla (in configuration: Mozilla) Like Attach, but break before braces on enum, function, and record definitions. +# BS_Stroustrup (in configuration: Stroustrup) Like Attach, but break before function definitions, catch, and else. +# BS_Allman (in configuration: Allman) Always break before braces. +# BS_GNU (in configuration: GNU) Always break before braces and add an extra level of indentation to braces of control statements, not to those of class, function or other definitions. +# BS_WebKit (in configuration: WebKit) Like Attach, but break before functions. +# BS_Custom (in configuration: Custom) Configure each individual brace in BraceWrapping. +BreakBeforeBraces: Allman + +# BreakBeforeTernaryOperators (bool) +# If true, ternary operators will be placed after line breaks. +BreakBeforeTernaryOperators: false + +# BreakConstructorInitializersBeforeComma (bool) +# Always break constructor initializers before commas and align the commas with the colon. +BreakConstructorInitializersBeforeComma: false + +# BreakStringLiterals (bool) +# Allow breaking string literals when formatting. +#BreakStringLiterals: + +# ColumnLimit (unsigned) +# The column limit. +# A column limit of 0 means that there is no column limit. In this case, clang-format will respect the input’s line breaking decisions within statements unless they contradict other rules. +ColumnLimit: 80 + +# CommentPragmas (std::string) +# A regular expression that describes comments with special meaning, which should not be split into lines or otherwise changed. +CommentPragmas: '' + +# ConstructorInitializerAllOnOneLineOrOnePerLine (bool) +# If the constructor initializers don’t fit on a line, put each initializer on its own line. +ConstructorInitializerAllOnOneLineOrOnePerLine: false + +# ConstructorInitializerIndentWidth (unsigned) +# The number of characters to use for indentation of constructor initializer lists. +ConstructorInitializerIndentWidth: 0 + +# ContinuationIndentWidth (unsigned) +# Indent width for line continuations. +ContinuationIndentWidth: 4 + +# Cpp11BracedListStyle (bool) +# If true, format braced lists as best suited for C++11 braced lists. +# Important differences: - No spaces inside the braced list. - No line break before the closing brace. - Indentation with the continuation indent, not with the block indent. +# Fundamentally, C++11 braced lists are formatted exactly like function calls would be formatted in their place. If the braced list follows a name (e.g. a type or variable name), clang-format formats as if the {} were the parentheses of a function call with that name. If there is no name, a zero-length name is assumed. +Cpp11BracedListStyle: false + +# DerivePointerAlignment (bool) +# If true, analyze the formatted file for the most common alignment of & and \*. PointerAlignment is then used only as fallback. +DerivePointerBinding: false + +# DisableFormat (bool) +# Disables formatting completely. +#DisableFormat: + +# ExperimentalAutoDetectBinPacking (bool) +# If true, clang-format detects whether function calls and definitions are formatted with one parameter per line. +# Each call can be bin-packed, one-per-line or inconclusive. If it is inconclusive, e.g. completely on one line, but a decision needs to be made, clang-format analyzes whether there are other bin-packed cases in the input file and act accordingly. +# NOTE: This is an experimental flag, that might go away or be renamed. Do not use this in config files, etc. Use at your own risk. +#ExperimentalAutoDetectBinPacking: + +# ForEachMacros (std::vector) +# A vector of macros that should be interpreted as foreach loops instead of as function calls. +# These are expected to be macros of the form: +# FOREACH(, ...) +# +# In the .clang-format configuration file, this can be configured like: +# ForEachMacros: ['RANGES_FOR', 'FOREACH'] +# For example: BOOST_FOREACH. +#ForEachMacros: + +# IncludeCategories (std::vector) +# Regular expressions denoting the different #include categories used for ordering #includes. +# These regular expressions are matched against the filename of an include (including the <> or “”) in order. The value belonging to the first matching regular expression is assigned and #includes are sorted first according to increasing category number and then alphabetically within each category. +# If none of the regular expressions match, INT_MAX is assigned as category. The main header for a source file automatically gets category 0. so that it is generally kept at the beginning of the #includes (http://llvm.org/docs/CodingStandards.html#include-style). However, you can also assign negative priorities if you have certain headers that always need to be first. +# To configure this in the .clang-format file, use: +# IncludeCategories: +# - Regex: '^"(llvm|llvm-c|clang|clang-c)/' +# Priority: 2 +# - Regex: '^(<|"(gtest|isl|json)/)' +# Priority: 3 +# - Regex: '.\*' +# Priority: 1 +#IncludeCategories: + +# IndentCaseLabels (bool) +# Indent case labels one level from the switch statement. +# When false, use the same indentation level as for the switch statement. Switch statement body is always indented one level more than case labels. +IndentCaseLabels: false + +# IndentFunctionDeclarationAfterType (bool) +# If true, indent when breaking function declarations which are not also definitions after the type. +IndentFunctionDeclarationAfterType: false + +# IndentWrappedFunctionNames (bool) +# Indent if a function definition or declaration is wrapped after the type. +#IndentWrappedFunctionNames: + +# KeepEmptyLinesAtTheStartOfBlocks (bool) +# If true, empty lines at the start of blocks are kept. +#KeepEmptyLinesAtTheStartOfBlocks: + +# MacroBlockBegin (std::string) +# A regular expression matching macros that start a block. +#MacroBlockBegin: + +# MacroBlockEnd (std::string) +# A regular expression matching macros that end a block. +#MacroBlockEnd: + +# MaxEmptyLinesToKeep (unsigned) +# The maximum number of consecutive empty lines to keep. +MaxEmptyLinesToKeep: 2 + +# NamespaceIndentation (NamespaceIndentationKind) +# The indentation used for namespaces. +# Possible values: +# NI_None (in configuration: None) Don’t indent in namespaces. +# NI_Inner (in configuration: Inner) Indent only in inner namespaces (nested in other namespaces). +# NI_All (in configuration: All) Indent in all namespaces. +NamespaceIndentation: None + +# ObjCBlockIndentWidth (unsigned) +# The number of characters to use for indentation of ObjC blocks. +#ObjCBlockIndentWidth: + +# ObjCSpaceAfterProperty (bool) +# Add a space after @property in Objective-C, i.e. use @property (readonly) instead of @property(readonly). +ObjCSpaceAfterProperty: true + +# ObjCSpaceBeforeProtocolList (bool) +# Add a space in front of an Objective-C protocol list, i.e. use Foo instead of Foo. +ObjCSpaceBeforeProtocolList: true + +# PenaltyBreakBeforeFirstCallParameter (unsigned) +# The penalty for breaking a function call after call(. +PenaltyBreakBeforeFirstCallParameter: 100 + +# PenaltyBreakComment (unsigned) +# The penalty for each line break introduced inside a comment. +PenaltyBreakComment: 100 + +# PenaltyBreakFirstLessLess (unsigned) +# The penalty for breaking before the first <<. +PenaltyBreakFirstLessLess: 0 + +# PenaltyBreakString (unsigned) +# The penalty for each line break introduced inside a string literal. +PenaltyBreakString: 100 + +# PenaltyExcessCharacter (unsigned) +# The penalty for each character outside of the column limit. +PenaltyExcessCharacter: 1 + +# PenaltyReturnTypeOnItsOwnLine (unsigned) +# Penalty for putting the return type of a function onto its own line. +PenaltyReturnTypeOnItsOwnLine: 20 + +# PointerAlignment (PointerAlignmentStyle) +# Pointer and reference alignment style. +# Possible values: +# PAS_Left (in configuration: Left) Align pointer to the left. +# PAS_Right (in configuration: Right) Align pointer to the right. +# PAS_Middle (in configuration: Middle) Align pointer in the middle. +#PointerAlignment: + +# ReflowComments (bool) +# If true, clang-format will attempt to re-flow comments. +#ReflowComments: true (from v3.9) + +# SortIncludes (bool) +# If true, clang-format will sort #includes. +#SortIncludes: false (from v3.9) + +# SpaceAfterCStyleCast (bool) +# If true, a space may be inserted after C style casts. +SpaceAfterCStyleCast: false + +# SpaceBeforeAssignmentOperators (bool) +# If false, spaces will be removed before assignment operators. +SpaceBeforeAssignmentOperators: true + +# SpaceBeforeParens (SpaceBeforeParensOptions) +# Defines in which cases to put a space before opening parentheses. +# Possible values: +# SBPO_Never (in configuration: Never) Never put a space before opening parentheses. +# SBPO_ControlStatements (in configuration: ControlStatements) Put a space before opening parentheses only after control statement keywords (for/if/while...). +# SBPO_Always (in configuration: Always) Always put a space before opening parentheses, except when it’s prohibited by the syntax rules (in function-like macro definitions) or when determined by other style rules (after unary operators, opening parentheses, etc.) +SpaceBeforeParens: ControlStatements + +# SpaceInEmptyParentheses (bool) +# If true, spaces may be inserted into (). +SpaceInEmptyParentheses: false + +# SpacesBeforeTrailingComments (unsigned) +# The number of spaces before trailing line comments (// - comments). +# This does not affect trailing block comments (/* - comments) as those commonly have different usage patterns and a number of special cases. +SpacesBeforeTrailingComments: 1 + +# SpacesInAngles (bool) +# If true, spaces will be inserted after < and before > in template argument lists. +SpacesInAngles: false + +# SpacesInCStyleCastParentheses (bool) +# If true, spaces may be inserted into C style casts. +SpacesInCStyleCastParentheses: false + +# SpacesInContainerLiterals (bool) +# If true, spaces are inserted inside container literals (e.g. ObjC and Javascript array and dict literals). +SpacesInContainerLiterals: false + +# SpacesInParentheses (bool) +# If true, spaces will be inserted after ( and before ). +SpacesInParentheses: false + +# SpacesInSquareBrackets (bool) +# If true, spaces will be inserted after [ and before ]. +SpacesInSquareBrackets: false diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index 0ee313aa..adb1b957 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -10,7 +10,7 @@ Closes # (issue) - [ ] Code has been tested on STM32 hardware. - [ ] Changes do not generate any new compiler warnings. -- [ ] Code has been formatted using `trunk fmt`. +- [ ] Code has been formatted using `make format`. - [ ] Commit messages follow the [Conventional Commits](https://www.conventionalcommits.org/en/v1.0.0/#specification) specification. ### Additional Notes diff --git a/.github/workflows/trunk-action.yaml b/.github/workflows/trunk-action.yaml new file mode 100644 index 00000000..1e3af94e --- /dev/null +++ b/.github/workflows/trunk-action.yaml @@ -0,0 +1,29 @@ +name: Trunk Code Quality +on: + push: + branches: [main] + pull_request: + +concurrency: + group: ${{ github.workflow }}-${{ github.head_ref || github.ref }} + cancel-in-progress: true + +permissions: read-all + +jobs: + trunk_check: + name: Trunk Code Quality Runner + runs-on: ubuntu-latest + permissions: + checks: write + contents: read + + steps: + - name: Checkout + uses: actions/checkout@v3 + + - name: Install cppcheck + run: sudo apt-get update && sudo apt-get install -y cppcheck + + - name: Trunk Code Quality + uses: trunk-io/trunk-action@v1 diff --git a/.gitignore b/.gitignore index 6998e262..bd6e8cd4 100644 --- a/.gitignore +++ b/.gitignore @@ -159,3 +159,6 @@ misra.txt # TraceX *.trx + +# CANoe +*.cbf diff --git a/.gitmodules b/.gitmodules index 4b5e7c7a..c9d3cf62 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,6 @@ -[submodule "src/Middlewares/SUFST/rtcan"] - path = src/Middlewares/SUFST/rtcan +[submodule "src/SUFST/Middlewares/rtcan"] + path = src/SUFST/Middlewares/rtcan url = https://github.com/sufst/rtcan -[submodule "src/Middlewares/SUFST/can-defs"] - path = src/Middlewares/SUFST/can-defs +[submodule "src/SUFST/Middlewares/can-defs"] + path = src/SUFST/Middlewares/can-defs url = https://github.com/sufst/can-defs diff --git a/.trunk/trunk.yaml b/.trunk/trunk.yaml index 8f77aef3..c52796ec 100644 --- a/.trunk/trunk.yaml +++ b/.trunk/trunk.yaml @@ -58,8 +58,10 @@ lint: - src/AZURE_RTOS/** - src/Core/** - src/Drivers/** - - src/Middlewares/ST - - scripts/* + - src/Middlewares/** + - src/FileX/** + - src/USBX/** + - scripts/** - linters: [clang-format] paths: - src/SUFST/Inc/config.h diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json index 1da2201d..05d2a48d 100644 --- a/.vscode/c_cpp_properties.json +++ b/.vscode/c_cpp_properties.json @@ -11,7 +11,7 @@ "${workspaceFolder}/src/Drivers/CMSIS/**", "${workspaceFolder}/src/Middlewares/ST/threadx/common/inc", "${workspaceFolder}/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/inc", - "${workspaceFolder}/src/SUFST/Inc/CAN", + "${workspaceFolder}/src/SUFST/Inc/", "${workspaceFolder}/src/Drivers/STM32F7xx_HAL_Driver/Inc" ], "defines": [ diff --git a/.vscode/launch.json b/.vscode/launch.json index f6eb2b89..5f46455f 100644 --- a/.vscode/launch.json +++ b/.vscode/launch.json @@ -4,7 +4,7 @@ { "cwd": "${workspaceFolder}", "name": "debug (stutil)", - "executable": "build/VCU.elf", + "executable": "build/debug/VCU.elf", "request": "launch", "type": "cortex-debug", "showDevDebugOutput": "none", @@ -16,7 +16,7 @@ // debug with openocd { "cwd": "${workspaceFolder}", - "executable": "build/VCU.elf", + "executable": "build/debug/VCU.elf", "name": "debug (openocd)", "request": "launch", "type": "cortex-debug", diff --git a/.vscode/settings.json b/.vscode/settings.json index 3f664adf..f082f1c2 100644 --- a/.vscode/settings.json +++ b/.vscode/settings.json @@ -50,10 +50,13 @@ "torque_map_funcs.h": "c", "rtds.h": "c", "pm100.h": "c", - "can_c.h": "c", + "can_t.h": "c", "ctrl.h": "c" }, + "cortex-debug.gdbPath": "gdb-multiarch", "cortex-debug.variableUseNaturalFormat": true, - "C_Cpp.errorSquiggles": "Enabled", - "mcu-debug.rtos-views.showRTOS": false + "C_Cpp.errorSquiggles": "enabled", + "C_Cpp.intelliSenseEngine": "default", + "mcu-debug.rtos-views.showRTOS": false, + "clangd.enable": false } diff --git a/Makefile b/Makefile index 17f2e383..7d80a402 100644 --- a/Makefile +++ b/Makefile @@ -17,15 +17,17 @@ ############################################################################### TARGET = VCU -BUILD_DIR = build -DEBUG = 1 +DEBUG = 0 C_STANDARD = c11 # defines ALWAYS_C_DEFS = \ -DTX_INCLUDE_USER_DEFINE_FILE \ -DUSE_HAL_DRIVER \ --DSTM32F746xx +-DSTM32F746xx \ +-DRTCAN_OSAL_THREADX \ +-DFX_INCLUDE_USER_DEFINE_FILE \ +-DUX_INCLUDE_USER_DEFINE_FILE DEBUG_C_DEFS = \ -DDEBUG \ @@ -95,8 +97,15 @@ src/SUFST/Src/vcu.c \ src/SUFST/Src/config.c \ src/SUFST/Src/Functions/clip_to_range.c \ src/SUFST/Src/Functions/torque_map.c \ +src/SUFST/Src/Functions/compressor.c \ +src/SUFST/Src/Functions/torque_limiters.c \ +src/SUFST/Src/Services/mode_switch_values.c \ +src/SUFST/Src/Interfaces/usb_mass_storage_mode.c \ +src/SUFST/Src/Interfaces/adc_scan.c \ src/SUFST/Src/Interfaces/apps.c \ src/SUFST/Src/Interfaces/bps.c \ +src/SUFST/Src/Interfaces/io.c \ +src/SUFST/Src/Interfaces/rs232.c \ src/SUFST/Src/Interfaces/rtds.c \ src/SUFST/Src/Interfaces/scs.c \ src/SUFST/Src/Interfaces/trc.c \ @@ -108,6 +117,9 @@ src/SUFST/Src/Services/pm100.c \ src/SUFST/Src/Services/tick.c \ src/SUFST/Src/Services/log.c \ src/SUFST/Src/Services/heartbeat.c \ +src/SUFST/Src/Services/wheelspeed.c \ +src/SUFST/Src/Services/fans.c \ +src/SUFST/Src/Services/sd_logging.c \ src/SUFST/Src/Test/testbench.c \ src/SUFST/Src/Test/apps_testbench_data.c \ src/Core/Src/main.c \ @@ -115,12 +127,207 @@ src/Core/Src/adc.c \ src/Core/Src/can.c \ src/Core/Src/gpio.c \ src/Core/Src/usart.c \ +src/Core/Src/i2c.c \ +src/Core/Src/spi.c \ +src/Core/Src/tim.c \ +src/Core/Src/usb_otg.c \ +src/Core/Src/sysmem.c \ +src/Core/Src/syscalls.c \ src/Core/Src/stm32f7xx_it.c \ src/Core/Src/stm32f7xx_hal_msp.c \ -src/Core/stm32f7xx_hal_timebase_tim.c \ +src/Core/Src/stm32f7xx_hal_timebase_tim.c \ src/Core/Src/system_stm32f7xx.c \ -src/Core/app_threadx.c \ +src/Core/Src/app_threadx.c \ src/AZURE_RTOS/App/app_azure_rtos.c \ +src/USBX/App/app_usbx_device.c \ +src/USBX/App/app_usbx_host.c \ +src/USBX/App/ux_device_msc.c \ +src/USBX/App/ux_device_descriptors.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_activate.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_control_request.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_csw_send.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_deactivate.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_entry.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_format.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_configuration.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_performance.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_status_notification.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_initialize.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_inquiry.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_mode_select.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_mode_sense.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_prevent_allow_media_removal.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_capacity.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_disk_information.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_dvd_structure.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_format_capacity.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_toc.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_report_key.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_request_sense.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_start_stop.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_synchronize_cache.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_test_ready.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_thread.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_uninitialize.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_verify.c \ +src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_write.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_alternate_setting_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_alternate_setting_set.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_class_register.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_class_unregister.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_clear_feature.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_configuration_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_configuration_set.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_control_request_process.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_descriptor_send.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_disconnect.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_endpoint_stall.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_get_status.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_host_wakeup.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_initialize.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_delete.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_set.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_start.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_microsoft_extension_register.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_set_feature.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_abort.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_all_request_abort.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_request.c \ +src/Middlewares/ST/usbx/common/core/src/ux_device_stack_uninitialize.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_check.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_claim.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_release.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_call.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_device_scan.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_destroy.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_verify.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_interface_scan.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_register.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_unregister.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_descriptor_parse.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_enumerate.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_instance_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_instance_delete.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_interface_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_interface_scan.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_set.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_delay_ms.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_address_set.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_activate.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_deactivate.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_reset.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_select.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_descriptor_read.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_remove.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_resources_free.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_string_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_instance_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_instance_delete.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_reset.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_transfer_abort.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_enum_thread_entry.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_register.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_thread_entry.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_transfer_request.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_unregister.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hnp_polling_thread_entry.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_initialize.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_endpoint_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_instance_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_instance_delete.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_set.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_setting_select.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interfaces_scan.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_configuration_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_device_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_device_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_endpoint_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_interface_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_change_process.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_device_extraction.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_device_insertion.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_role_swap.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_transfer_request.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_transfer_request_abort.c \ +src/Middlewares/ST/usbx/common/core/src/ux_host_stack_uninitialize.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_debug_callback_register.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_debug_log.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_delay_ms.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_descriptor_pack.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_descriptor_parse.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_error_callback_register.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_delete.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_set.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_long_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_long_get_big_endian.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_long_put.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_long_put_big_endian.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_add_safe.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_mulc_safe.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_mulv_safe.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_compare.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_copy.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_free.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_free_block_best_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_set.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_delete.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_off.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_on.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_class_scan.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_read.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_write.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_physical_address.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_delete.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_put.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_set_interrupt_handler.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_short_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_short_get_big_endian.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_short_put.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_short_put_big_endian.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_string_length_check.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_string_length_get.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_string_to_unicode.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_delete.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_identify.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_relinquish.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_resume.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_schedule_other.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_sleep.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_suspend.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_timer_create.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_unicode_to_string.c \ +src/Middlewares/ST/usbx/common/core/src/ux_utility_virtual_address.c \ +src/Middlewares/ST/usbx/common/core/src/ux_system_error_handler.c \ +src/Middlewares/ST/usbx/common/core/src/ux_system_initialize.c \ +src/Middlewares/ST/usbx/common/core/src/ux_system_uninitialize.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_callback.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_create.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_destroy.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_reset.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_stall.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_status.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_frame_number_get.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_function.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_initialize.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_initialize_complete.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_interrupt_handler.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_transfer_abort.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_transfer_request.c \ +src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_uninitialize.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c \ @@ -142,6 +349,9 @@ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c \ +src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c \ +src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c \ +src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c \ src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c \ @@ -313,28 +523,270 @@ src/Middlewares/ST/threadx/common/src/tx_trace_isr_exit_insert.c \ src/Middlewares/ST/threadx/common/src/tx_trace_object_register.c \ src/Middlewares/ST/threadx/common/src/tx_trace_object_unregister.c \ src/Middlewares/ST/threadx/common/src/tx_trace_user_event_insert.c \ -src/Middlewares/SUFST/rtcan/src/rtcan.c \ -src/Middlewares/SUFST/can-defs/out/can_c.c \ -src/Middlewares/SUFST/can-defs/out/can_s.c +src/Middlewares/ST/threadx/utility/low_power/tx_low_power.c \ +src/SUFST/Middlewares/rtcan/src/rtcan.c \ +src/SUFST/Middlewares/rtcan/src/rtcan_osal_threadx.c \ +src/SUFST/Middlewares/can-defs/out/can_t.c \ +src/SUFST/Middlewares/can-defs/out/can_s.c \ +src/Core/Src/sdmmc.c \ +src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c \ +src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c \ +src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c \ +src/Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c \ +src/FileX/Target/fx_stm32_sd_driver_glue.c \ +src/FileX/App/app_filex.c \ +src/Middlewares/ST/filex/common/src/fx_directory_attributes_read.c \ +src/Middlewares/ST/filex/common/src/fx_directory_attributes_set.c \ +src/Middlewares/ST/filex/common/src/fx_directory_create.c \ +src/Middlewares/ST/filex/common/src/fx_directory_default_get.c \ +src/Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c \ +src/Middlewares/ST/filex/common/src/fx_directory_default_set.c \ +src/Middlewares/ST/filex/common/src/fx_directory_delete.c \ +src/Middlewares/ST/filex/common/src/fx_directory_entry_read.c \ +src/Middlewares/ST/filex/common/src/fx_directory_entry_write.c \ +src/Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c \ +src/Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c \ +src/Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c \ +src/Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c \ +src/Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c \ +src/Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c \ +src/Middlewares/ST/filex/common/src/fx_directory_free_search.c \ +src/Middlewares/ST/filex/common/src/fx_directory_information_get.c \ +src/Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c \ +src/Middlewares/ST/filex/common/src/fx_directory_local_path_get.c \ +src/Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c \ +src/Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c \ +src/Middlewares/ST/filex/common/src/fx_directory_local_path_set.c \ +src/Middlewares/ST/filex/common/src/fx_directory_long_name_get.c \ +src/Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c \ +src/Middlewares/ST/filex/common/src/fx_directory_name_extract.c \ +src/Middlewares/ST/filex/common/src/fx_directory_name_test.c \ +src/Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c \ +src/Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c \ +src/Middlewares/ST/filex/common/src/fx_directory_rename.c \ +src/Middlewares/ST/filex/common/src/fx_directory_search.c \ +src/Middlewares/ST/filex/common/src/fx_directory_short_name_get.c \ +src/Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c \ +src/Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c \ +src/Middlewares/ST/filex/common/src/fx_file_allocate.c \ +src/Middlewares/ST/filex/common/src/fx_file_attributes_read.c \ +src/Middlewares/ST/filex/common/src/fx_file_attributes_set.c \ +src/Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c \ +src/Middlewares/ST/filex/common/src/fx_file_close.c \ +src/Middlewares/ST/filex/common/src/fx_file_create.c \ +src/Middlewares/ST/filex/common/src/fx_file_date_time_set.c \ +src/Middlewares/ST/filex/common/src/fx_file_delete.c \ +src/Middlewares/ST/filex/common/src/fx_file_extended_allocate.c \ +src/Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c \ +src/Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c \ +src/Middlewares/ST/filex/common/src/fx_file_extended_seek.c \ +src/Middlewares/ST/filex/common/src/fx_file_extended_truncate.c \ +src/Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c \ +src/Middlewares/ST/filex/common/src/fx_file_open.c \ +src/Middlewares/ST/filex/common/src/fx_file_read.c \ +src/Middlewares/ST/filex/common/src/fx_file_relative_seek.c \ +src/Middlewares/ST/filex/common/src/fx_file_rename.c \ +src/Middlewares/ST/filex/common/src/fx_file_seek.c \ +src/Middlewares/ST/filex/common/src/fx_file_truncate.c \ +src/Middlewares/ST/filex/common/src/fx_file_truncate_release.c \ +src/Middlewares/ST/filex/common/src/fx_file_write.c \ +src/Middlewares/ST/filex/common/src/fx_file_write_notify_set.c \ +src/Middlewares/ST/filex/common/src/fx_media_abort.c \ +src/Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c \ +src/Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c \ +src/Middlewares/ST/filex/common/src/fx_media_check.c \ +src/Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c \ +src/Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c \ +src/Middlewares/ST/filex/common/src/fx_media_close.c \ +src/Middlewares/ST/filex/common/src/fx_media_close_notify_set.c \ +src/Middlewares/ST/filex/common/src/fx_media_exFAT_format.c \ +src/Middlewares/ST/filex/common/src/fx_media_extended_space_available.c \ +src/Middlewares/ST/filex/common/src/fx_media_flush.c \ +src/Middlewares/ST/filex/common/src/fx_media_format.c \ +src/Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c \ +src/Middlewares/ST/filex/common/src/fx_media_format_type_set.c \ +src/Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c \ +src/Middlewares/ST/filex/common/src/fx_media_open.c \ +src/Middlewares/ST/filex/common/src/fx_media_open_notify_set.c \ +src/Middlewares/ST/filex/common/src/fx_media_read.c \ +src/Middlewares/ST/filex/common/src/fx_media_space_available.c \ +src/Middlewares/ST/filex/common/src/fx_media_volume_get.c \ +src/Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c \ +src/Middlewares/ST/filex/common/src/fx_media_volume_set.c \ +src/Middlewares/ST/filex/common/src/fx_media_write.c \ +src/Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c \ +src/Middlewares/ST/filex/common/src/fx_system_date_get.c \ +src/Middlewares/ST/filex/common/src/fx_system_date_set.c \ +src/Middlewares/ST/filex/common/src/fx_system_initialize.c \ +src/Middlewares/ST/filex/common/src/fx_system_time_get.c \ +src/Middlewares/ST/filex/common/src/fx_system_time_set.c \ +src/Middlewares/ST/filex/common/src/fx_system_timer_entry.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_directory_create.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_directory_search.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_file_create.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_file_rename.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_length_get.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_name_get.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c \ +src/Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c \ +src/Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c \ +src/Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c \ +src/Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c \ +src/Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c \ +src/Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c \ +src/Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c \ +src/Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c \ +src/Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c \ +src/Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c \ +src/Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c \ +src/Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c \ +src/Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c \ +src/Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c \ +src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c \ +src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c \ +src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c \ +src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c \ +src/Middlewares/ST/filex/common/src/fx_utility_memory_copy.c \ +src/Middlewares/ST/filex/common/src/fx_utility_memory_set.c \ +src/Middlewares/ST/filex/common/src/fx_utility_string_length_get.c \ +src/Middlewares/ST/filex/common/src/fx_utility_token_length_get.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_create.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_default_get.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_default_set.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_delete.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_information_get.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_name_test.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_rename.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c \ +src/Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c \ +src/Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c \ +src/Middlewares/ST/filex/common/src/fxe_file_allocate.c \ +src/Middlewares/ST/filex/common/src/fxe_file_attributes_read.c \ +src/Middlewares/ST/filex/common/src/fxe_file_attributes_set.c \ +src/Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c \ +src/Middlewares/ST/filex/common/src/fxe_file_close.c \ +src/Middlewares/ST/filex/common/src/fxe_file_create.c \ +src/Middlewares/ST/filex/common/src/fxe_file_date_time_set.c \ +src/Middlewares/ST/filex/common/src/fxe_file_delete.c \ +src/Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c \ +src/Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c \ +src/Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c \ +src/Middlewares/ST/filex/common/src/fxe_file_extended_seek.c \ +src/Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c \ +src/Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c \ +src/Middlewares/ST/filex/common/src/fxe_file_open.c \ +src/Middlewares/ST/filex/common/src/fxe_file_read.c \ +src/Middlewares/ST/filex/common/src/fxe_file_relative_seek.c \ +src/Middlewares/ST/filex/common/src/fxe_file_rename.c \ +src/Middlewares/ST/filex/common/src/fxe_file_seek.c \ +src/Middlewares/ST/filex/common/src/fxe_file_truncate.c \ +src/Middlewares/ST/filex/common/src/fxe_file_truncate_release.c \ +src/Middlewares/ST/filex/common/src/fxe_file_write.c \ +src/Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c \ +src/Middlewares/ST/filex/common/src/fxe_media_abort.c \ +src/Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c \ +src/Middlewares/ST/filex/common/src/fxe_media_check.c \ +src/Middlewares/ST/filex/common/src/fxe_media_close.c \ +src/Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c \ +src/Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c \ +src/Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c \ +src/Middlewares/ST/filex/common/src/fxe_media_flush.c \ +src/Middlewares/ST/filex/common/src/fxe_media_format.c \ +src/Middlewares/ST/filex/common/src/fxe_media_open.c \ +src/Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c \ +src/Middlewares/ST/filex/common/src/fxe_media_read.c \ +src/Middlewares/ST/filex/common/src/fxe_media_space_available.c \ +src/Middlewares/ST/filex/common/src/fxe_media_volume_get.c \ +src/Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c \ +src/Middlewares/ST/filex/common/src/fxe_media_volume_set.c \ +src/Middlewares/ST/filex/common/src/fxe_media_write.c \ +src/Middlewares/ST/filex/common/src/fxe_system_date_get.c \ +src/Middlewares/ST/filex/common/src/fxe_system_date_set.c \ +src/Middlewares/ST/filex/common/src/fxe_system_time_get.c \ +src/Middlewares/ST/filex/common/src/fxe_system_time_set.c \ +src/Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c \ +src/Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c \ +src/Middlewares/ST/filex/common/src/fxe_unicode_file_create.c \ +src/Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c \ +src/Middlewares/ST/filex/common/src/fxe_unicode_name_get.c \ +src/Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c \ +src/Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c \ +src/Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c \ +src/Core/Src/dma.c ASM_SOURCES = \ src/startup_stm32f746xx.s \ src/Core/Src/tx_initialize_low_level.s \ -src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.s \ -src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.s \ -src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.s \ -src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.s \ -src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.s \ -src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.s \ -src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.s +src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.S \ +src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.S \ +src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S \ +src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S \ +src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.S \ +src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.S \ +src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.S ############################################################################### # includes ############################################################################### C_INCLUDES = \ --Isrc/Core/Inc \ -Isrc/SUFST/Inc \ +-Isrc/Core/Inc \ -Isrc/SUFST/Inc/Functions \ -Isrc/SUFST/Inc/Interfaces \ -Isrc/SUFST/Inc/Services \ @@ -345,8 +797,19 @@ C_INCLUDES = \ -Isrc/AZURE_RTOS/App \ -Isrc/Middlewares/ST/threadx/common/inc/ \ -Isrc/Middlewares/ST/threadx/ports/cortex_m7/gnu/inc/ \ --Isrc/Middlewares/SUFST/rtcan/inc/ \ --Isrc/Middlewares/SUFST/can-defs/out/ +-Isrc/Middlewares/ST/threadx/utility/low_power/ \ +-Isrc/SUFST/Middlewares/rtcan/inc/ \ +-Isrc/SUFST/Middlewares/can-defs/out/ \ +-Isrc/FileX/App \ +-Isrc/FileX/Target \ +-Isrc/Middlewares/ST/filex/common/inc \ +-Isrc/Middlewares/ST/filex/ports/generic/inc \ +-Isrc/USBX/App \ +-Isrc/USBX/Target \ +-Isrc/Middlewares/ST/usbx/common/usbx_device_classes/inc/ \ +-Isrc/Middlewares/ST/usbx/common/core/inc/ \ +-Isrc/Middlewares/ST/usbx/ports/generic/inc/ \ +-Isrc/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ ASM_INCLUDES = @@ -357,9 +820,11 @@ ASM_INCLUDES = ifeq ($(DEBUG), 1) C_DEFS = $(ALWAYS_C_DEFS) $(DEBUG_C_DEFS) ASM_DEFS = $(DEBUG_ASM_DEFS) + BUILD_DIR = build/debug else C_DEFS = $(ALWAYS_C_DEFS) $(RELEASE_C_DEFS) ASM_DEFS = $(RELEASE_ASM_DEFS) + BUILD_DIR = build/release endif ############################################################################### @@ -413,11 +878,11 @@ $(BUILD_DIR)/%.o: %.c Makefile | $(BUILD_DIR) prebuild $(CC) -c $(CFLAGS) -Wa,-a,-ad,-alms=$(BUILD_DIR)/$(notdir $(<:.c=.lst)) $< -o $@ # ASM -$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) prebuild +$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) prebuild echo "$<" $(AS) -c $(CFLAGS) $< -o $@ -$(BUILD_DIR)/%.o: %.S Makefile | $(BUILD_DIR) prebuild +$(BUILD_DIR)/%.o: %.s Makefile | $(BUILD_DIR) prebuild echo "$<" $(AS) -c $(CFLAGS) $< -o $@ @@ -445,13 +910,13 @@ $(BUILD_DIR): # clean clean: tput setaf 5; tput bold; echo "Cleaning build directory..."; tput sgr0 - -rm -fR $(BUILD_DIR) + -rm -fR build tput setaf 2; echo "Done"; tput sgr0 # flash flash: $(BUILD_DIR)/$(TARGET).bin tput setaf 5; tput bold; echo "Flashing..."; tput sgr0 - st-flash write $< 0x08000000 + st-flash --reset write $< 0x08000000 # generate compile commands database ccd: @@ -459,6 +924,13 @@ ccd: ${PYTHON} -m ccdgen --extensions .c .s .S --compiler arm-none-eabi-gcc -- ${MAKE} tput sgr0; tput setaf 2; echo "Done"; tput sgr0 +# format source code +.PHONY: format +format: + tput setaf 5; tput bold; echo "Formatting source code..."; tput sgr0 + find src/SUFST/Src src/SUFST/Inc \( -iname '*.c' -o -iname '*.h' \) -print0 | xargs -0 clang-format -i + tput setaf 2; echo "Done"; tput sgr0 + ############################################################################### # dependencies ############################################################################### diff --git a/README.md b/README.md index 892959b1..884192b2 100644 --- a/README.md +++ b/README.md @@ -3,7 +3,7 @@ # Table of Contents - [About](#about) -- [Development Environment](#development-environment) +- [Development Environment](#setup--development-environment) - [Contributing](#contributing) - [Useful Resources](#useful-resources) - [Related Projects](#related-projects) @@ -20,10 +20,10 @@ SUFST Docs Site. ## Using the setup script +Run the below command once to install dependencies, clone the repository and initialise submodules + ```sh -curl https://raw.githubusercontent.com/sufst/vcu/refs/heads/main/vcu-setup-script.sh -o vcu-setup-script.sh -chmod +x vcu-setup-script.sh -./vcu-setup-script.sh +curl -LsSf https://raw.githubusercontent.com/sufst/vcu/refs/heads/stag-12/vcu-setup-script.sh | bash ``` ## Submodules diff --git a/scripts/canoe/ProjectSettings.vtesettings b/scripts/canoe/ProjectSettings.vtesettings new file mode 100644 index 00000000..985f8784 --- /dev/null +++ b/scripts/canoe/ProjectSettings.vtesettings @@ -0,0 +1,262 @@ + + + + + + f4097ce8-e7fc-4dfe-bc1c-2a3f647af0b2 + + + + + Vector.SymbolSelection.Controls.SymbolSelectionControl + 4 + Vector.SymbolSelection, Version=3.8.12.0, Culture=neutral, PublicKeyToken=null + + <?xml version="1.0" encoding="utf-8"?> +<SymbolSelectionProperties xmlns:i="http://www.w3.org/2001/XMLSchema-instance"> +<AreDiagQualifiersShown>true</AreDiagQualifiersShown> +<CurrentViewId>None</CurrentViewId> +<SearchProperties> +<SearchTermHistory /> +</SearchProperties> +<ViewProperties> +<ViewProperties> +<ColumnsProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>0</Position> +<Sorting>Ascending</Sorting> +<Width>200</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>2</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>3</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>4</Position> +<Width>200</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>5</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +</ColumnsProperties> +<Key>Embedded/NetworkSymbols</Key> +<NodeTreeProperties /> +</ViewProperties> +</ViewProperties> +</SymbolSelectionProperties> + + + + Vector.SymbolSelection.Controls.SymbolSelectionDialog + 4 + Vector.SymbolSelection, Version=3.8.12.0, Culture=neutral, PublicKeyToken=null + + + + + + + + 73bcea0e-9abf-4359-b300-0186fd754011 + + + + + Vector.SymbolSelection.Controls.SymbolSelectionControl + 4 + Vector.SymbolSelection, Version=3.8.12.0, Culture=neutral, PublicKeyToken=null + + <?xml version="1.0" encoding="utf-8"?> +<SymbolSelectionProperties xmlns:i="http://www.w3.org/2001/XMLSchema-instance"> +<AreDiagQualifiersShown>true</AreDiagQualifiersShown> +<CurrentViewId>None</CurrentViewId> +<SearchProperties> +<SearchTermHistory /> +</SearchProperties> +<ViewProperties> +<ViewProperties> +<ColumnsProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>0</Position> +<Sorting>Ascending</Sorting> +<Width>200</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>2</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>3</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<IsVisible>true</IsVisible> +<Position>4</Position> +<Width>200</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +<ColumnProperties> +<Position>-1</Position> +<Width>100</Width> +</ColumnProperties> +</ColumnsProperties> +<Key>Embedded/NetworkSymbols</Key> +<NodeTreeProperties /> +</ViewProperties> +</ViewProperties> +</SymbolSelectionProperties> + + + + Vector.SymbolSelection.Controls.SymbolSelectionDialog + 4 + Vector.SymbolSelection, Version=3.8.12.0, Culture=neutral, PublicKeyToken=null + + + + + + + \ No newline at end of file diff --git a/scripts/canoe/Stag_12.cfg b/scripts/canoe/Stag_12.cfg new file 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You should pass it along with the cfg file +# and store it in your configuration management system. +# +# You may edit the settings directly, read the comments for a +# description. There's not necessarily any further explanation +# in the online help. +# +# The file format is a simple .ini format. That means it's a +# key=value list, with the settings grouped into [sections]. + +# General runtime settings +[Runtime] +# Enforce initialization of optional values such that they are considered unset initially as long as +# not specified differently by vCDL attribute (same keyword). When set to 0, optional elements +# are initialized to the default value of their datatype. +InitializeOptionalsAsNone=1 + +# Default value for the [EnableChangeInfo] vCDL attribute, which can be applied to distributed object +# members. It enables the calculation of change information. When set to 1, it is tracked whether the +# value has changed, how often it has changed so far, and at which time it has most recently changed. +# The calculation of change info has a performance cost. If any change handlers are listening for +# changes of the DO member in question, its change info has to be calculated regardless of this setting. +EnableChangeInfo=0 + +# Control how boundary values for linear encodings from databases are applied for conversion between +# raw and physical values. When set to 1, linear encoding rules are applied only to values which lie +# exactly within the associated min/max interval. In case the flag is set to 0, linear encoding is also +# applied to values outside all encoding ranges such that the encoding of the next lower range is used +# or if the value is below all ranges, the encoding with the lowest range is used. +StrictLinearEncodingBoundaries=1 + +# Settings pertaining to the CAPL compiler and runtime. +[CAPL] + +# Compatibility switch: an old version of the CAPL compiler +# initialized integer constants and variables in a different +# (and target dependent) way, e.g., if they were initialized by a +# floating point constant (const dword x = 3.1). +# This was fixed to a documented behavior, but if you have +# old code which relies on the old behavior, set the switch to 1. +LegacyNumericInitializations=0 + +# Compatibility switch: an old version of the CAPL compiler +# treated DWORD expressions as long (i.e., signed) in +# comparisons. That was fixed, but if you have old CAPL code +# which relies on the old behavior, set the switch to 1. +CompareDwordAsLong=0 + +# Compatibility switch: an old version of the CAPL compiler +# stored each string constant separately in the data segment, +# even if they had the same value. This was changed so the +# memory is shared for equal string constants, sometimes +# significantly reducing the amount of memory needed. +# If you have old CAPL code which relies on the old behavior +# by _changing_ a string constant, but expecting other uses +# of an equal constant to remain the same, set the switch to 0. +ShareEqualStringConstants=1 + +# Compatibility switch: older versions of CANoe used case +# sensitive search when looking for specific CAPL callbacks +# (e.g., OnXCPEvent or OnTCPReceive), even though CAPL functions +# themselves are not case sensitive. +# If you have old CAPL code which relies on the old behavior +# by having overloads (functions with the same name, but different +# parameters) of which one of them shall work as such a callback, +# set the switch to 1. +CaseSensitiveCallbackSearch=0 + +# Compatibility switch: in CANoe DE configurations normal nodes +# in the Simulation Setup are assigned to a (single) bus +# (Gateways are assigned to more buses) and every bus has one +# or more databases assigned. +# Older versions of CANoe let a node access all databases of the +# current configuration, while in newer versions, a node can only +# access (see) the database(s) assigned to its bus. +# If you have old CAPL code which relies on the old behavior +# by accessing a database which is not assigned to its bus, +# set the switch to 1 +GlobalDatabaseAccess=0 + +# Settings pertaining to the Connectifity Feature Set +[Connectivity] + +# Whether to use the new implementation of the BackendCloudConnector +# (formerly known as the BackendCloudClient) which is responsable +# for commuicating requests of the different Bindings. Setting this +# to 0 will cause the old implementation to be used. +EnableNewBCC=1 + +# Set send-queue size. +# Increase this parameter if you get the error "Overrun send queue" during measurement. +QueueCapacity=1000 + +# Settings for the C# API, as well as the related build processes and runtime configuration options +[.NET] + +# Enabling this switch will override the .NET version setting to use .NET Framework 2.0 +# .NET Framework 2.0 is no longer supported by Microsoft and the use of this switch is deprecated +# The ability to use .NET Framework 2.0 may be removed in future versions of CANoe +UseNet20=0 + +# Compatibility switch: Enabling this switch causes types library assemblies to have configuration-specific names when using .NET Framework +UseCfgSpecificAssemblyNames=0 + +# .NET 8 application layer type library: Generate separate _Types and _Objects types in addition to the .Types and .Objects subtypes +GenerateLegacyTypes=0 + +[Simulation] +# Selects the architecture used for the Ethernet RestBus Simulation (RBS). +# This setting applies to AUTOSAR PDUs and SOME/IP (including SOME/IP-SD) over Ethernet. +# Possible values: +# InteractionLayer - Uses the traditional Interaction Layer (IL) for simulation, as in previous CANoe versions. +# SOMEIPNative - Uses the new, native SOME/IP architecture for RestBus simulation with enhanced functionality. +EthernetRBSArchitecture=InteractionLayer + +[SOMEIP] +# Enforce that the values of events/fields can be set via the service signal (e.g. $-operator) even if +# Application Objects are activated for the SimSetup. +# If Application Objects are disabled for the SimSetup, this option has no impact. +ForceActiveServiceSignals=0 + +# Threshold size to determine whether generated Application Layer Objects (SOME/IP or AUTOSAR PDUs) +# should use the high-performance 'Bytes' data type instead of a normal byte array. +# The 'Bytes' data type is used for byte arrays that are >= ByteArrayThresholdSize. +ByteArrayThresholdSize=1000 + +# Settings for the Python API +[Python] +# Enforce the restart of the RT Kernel after each measurement. This might be required if dynamically loaded +# Python modules can't be unloaded correctly and therefore cause a crash or undefined behavior in the RT Kernel. +# 0: Restart is not forced. +# 1: Restart is forced. +ForceRtKernelRestart=0 + +# Enable support for system variables with the Python API. +# Support for system variables can be disabled for performance and compatibility reasons. +# 0: Support for system variables is disabled. +# 1: Support for system variables is enabled. +SystemVariableSupport=1 + +# Diagnostics settings +[Diagnostics] +# Diagnostics on FlexRay +# Disable atomic PDU group update +# the atomic PDU group update ensures correct sequence of frames +# in a diagnostic message, transferred over multiple PDUs +# this feature guarantees message data integrity, +# but may slow down transmission performance by skipping some cycles +FR_DisableAtomicPDUGroupUpdate=0 + +[Ethernet] +# Determines whether the TLS socket communication is executed on a separate thread. +# 0: Use global default from can.ini. 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Motor running + + + Xa116bffee7f24e423be9437e364469b895d8 + 24, 24 + 300, 13 + True + 9 + False + <Version>2</Version><Count>8</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Red</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Red</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Red</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Red</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Red</Color><RxValue>5</RxValue><LowerUpper>Lower</LowerUpper><TxValue>5</TxValue><Color>Orange</Color><RxValue>6</RxValue><LowerUpper>Lower</LowerUpper><TxValue>6</TxValue><Color>Green</Color> + Black + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;INV;PM100_Internal_States;PM100_VSM_State;1;CAN-T;;-1;;;Value;;;0 + + + X8b4520fde5527e4924e9f25e6179f02940c4 + 70, 15 + 277, 37 + TopCenter + VSM_Ready + + + Xbd479e4befd9de420eeb2c9e33df3398954a + 24, 24 + 240, 13 + True + 15 + False + <Version>2</Version><Count>8</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Red</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Red</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Red</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Red</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Orange</Color><RxValue>5</RxValue><LowerUpper>Lower</LowerUpper><TxValue>5</TxValue><Color>Green</Color><RxValue>6</RxValue><LowerUpper>Lower</LowerUpper><TxValue>6</TxValue><Color>Green</Color> + Black + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;INV;PM100_Internal_States;PM100_VSM_State;1;CAN-T;;-1;;;Value;;;0 + + + X6dc5d481eaf4de44f1e9cdee113427762db1 + 60, 15 + 222, 37 + TopCenter + VSM_Wait + + + Xe3a286bae8552e4673ea283e24e29f290e9f + 71, 15 + 153, 37 + TopCenter + PC complete + + + X878cba7ceff34e4310e8a8fe3861d3fb3916 + 24, 24 + 176, 13 + True + 9 + False + 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+ PC active + + + X2ce8c1a8e1978e4671eabd3e64f68227b575 + 24, 24 + 117, 13 + True + 14 + False + <Version>2</Version><Count>8</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Red</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Red</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Orange</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Green</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Green</Color><RxValue>5</RxValue><LowerUpper>Lower</LowerUpper><TxValue>5</TxValue><Color>Green</Color><RxValue>6</RxValue><LowerUpper>Lower</LowerUpper><TxValue>6</TxValue><Color>Green</Color> + Black + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;INV;PM100_Internal_States;PM100_VSM_State;1;CAN-T;;-1;;;Value;;;0 + + + Xb88a49afe25eee4c77ea0c3e0eb0df4b2c0b + 24, 24 + 69, 13 + True + 13 + False + <Version>2</Version><Count>8</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Red</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Orange</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Green</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Green</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Green</Color><RxValue>5</RxValue><LowerUpper>Lower</LowerUpper><TxValue>5</TxValue><Color>Green</Color><RxValue>6</RxValue><LowerUpper>Lower</LowerUpper><TxValue>6</TxValue><Color>Green</Color> + Black + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;INV;PM100_Internal_States;PM100_VSM_State;1;CAN-T;;-1;;;Value;;;0 + + + X8aed3db4e2ef7e49c4e883fe6b95b874d751 + 41, 15 + 61, 37 + TopCenter + PC init + + + Xc047fcb9ecb02e4784eb229e3c0f49eb822a + 62, 15 + 0, 37 + TopCenter + VSM_Start + + + Xc25b5ec9ed681e4c20ea97fe4a97506259c4 + 24, 24 + 19, 13 + True + 12 + False + <Version>2</Version><Count>8</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Orange</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Green</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Green</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Green</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Green</Color><RxValue>5</RxValue><LowerUpper>Lower</LowerUpper><TxValue>5</TxValue><Color>Green</Color><RxValue>6</RxValue><LowerUpper>Lower</LowerUpper><TxValue>6</TxValue><Color>Green</Color> + Black + Orange + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;INV;PM100_Internal_States;PM100_VSM_State;1;CAN-T;;-1;;;Value;;;0 + + X5784171eec6e6e4e65eab01eedb07f38f103 + 460, 80 + 3, 102 + Inverter VSM State + 8 + False + + + + Xfcc5d87ae489ce444eea190eb8855f5e3e0c + 60, 31 + 93, 50 + 8;2;CANT;VCU;VCU_Sensors;VCU_Torque_Request;1;CAN-T;;-1;;;Value;;;0 + 255, 247, 150, 70 + + + Xb803e187ed30ce44d4e8d7ae007db6b88606 + 40, 39 + 103, 10 + 1;2;0;100 + Salmon + Black + IndianRed + Black + FixedSingle + Top + Center + 3 + Torque + 1 + Double + RawValue + 68, 21 + 8;2;CANT;VCU;VCU_Sensors;VCU_Torque_Request;1;CAN-T;;-1;;;Value;;;0 + + + X4bb1aefce923ee4412ead8eeaf5ee3d31241 + 40, 39 + 57, 10 + 1;2;0;100 + Salmon + Black + IndianRed + Black + FixedSingle + Top + Center + 2 + BPS % + 1 + Double + RawValue + 48, 21 + 8;2;CANT;VCU;VCU_Sensors;VCU_BPS;1;CAN-T;;-1;;;Value;;;0 + + + X9ca14272e7f63e43c5e92dee72fa1fb84be6 + 48, 39 + 4, 10 + 1;2;0;100 + Salmon + Black + IndianRed + Black + FixedSingle + Top + Center + 1 + APPS % + 1 + Double + RawValue + 48, 21 + 8;2;CANT;VCU;VCU_Sensors;VCU_APPS;1;CAN-T;;-1;;;Value;;;0 + + + X8558b426edf50e4fc7ea10be0a997f81a71a + 60, 31 + 47, 50 + 8;2;CANT;VCU;VCU_Sensors;VCU_BPS;1;CAN-T;;-1;;;Value;;;0 + + + X15d94d2ae318ee4264eaf57e423d473f2093 + 47, 31 + 4, 50 + 8;2;CANT;VCU;VCU_Sensors;VCU_APPS;1;CAN-T;;-1;;;Value;;;0 + 255, 79, 129, 189 + + Xdcc00f60e6c3be4ed0eac40e8f95075f1597 + 153, 78 + 534, 18 + Driver Inputs + 7 + False + + + + Xc733384fe55ffe4132ea23ae3fc8f07e7391 + 301, 21 + 5, 73 + 1;2;0;100 + Salmon + Black + IndianRed + Black + FixedSingle + Left + 13 + VCU fault: + 0 + Text + PhysicalValue + 56, 21 + 8;16;;;;VCU_Fault_Text;4;;;-1;;;Value;;;0 + + + X50869025e8c31e49c7e9016eed73bf72c508 + 144, 21 + 162, 55 + 1;2;0;100 + Salmon + Black + IndianRed + Black + FixedSingle + Left + 12 + Current: + 0 + Symbolic + RawValue + 45, 21 + 8;2;CANT;VCU;VCU_State;VCU_CTRL_State;1;CAN-T;;-1;;;Value;;;0 + + + Xc33ad7f1e7a3fe439eeb30be8dd930e6c4fb + 155, 21 + -1, 55 + 1;2;0;100 + Salmon + Black + IndianRed + Black + FixedSingle + Left + Center + 11 + Rolling counter: + 0 + Double + RawValue + 82, 21 + 8;2;CANT;VCU;VCU_State;VCU_Rolling_Counter;1;CAN-T;;-1;;;Value;;;0 + + + Xbbf7e161e5fe7e4b06e89e3e2d1751b4af49 + 54, 15 + 242, 38 + TopCenter + DRIVING + + + X194e348de549ae4c03ea574e68f83cec22a6 + 24, 24 + 257, 17 + True + 9 + False + <Version>2</Version><Count>6</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Red</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Red</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Red</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Red</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Orange</Color> + Black + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;VCU;VCU_State;VCU_CTRL_State;1;CAN-T;;-1;;;Value;;;0 + + + Xbfebc9ede7806e4d1fe97c9eab976ef112de + 64, 15 + 182, 38 + TopCenter + R2D_WAIT + + + X7ecb8da8e2a42e4973eb0cfefb6de61ba910 + 24, 24 + 202, 17 + True + 8 + False + <Version>2</Version><Count>6</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Red</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Red</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Red</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Orange</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Green</Color> + Black + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;VCU;VCU_State;VCU_CTRL_State;1;CAN-T;;-1;;;Value;;;0 + + + X0b651e13e5ac0e485dea9b8ef62386368173 + 24, 24 + 133, 17 + True + 7 + False + <Version>2</Version><Count>6</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Red</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Red</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Orange</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Green</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Green</Color> + Black + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;VCU;VCU_State;VCU_CTRL_State;1;CAN-T;;-1;;;Value;;;0 + + + Xbe4bd8c3e2f27e46e7e8b94e69f0205a7864 + 78, 15 + 106, 39 + TopCenter + PRECHARGE + + + Xfea05f2be736de4e05e82cde8e046198b3bb + 24, 24 + 67, 17 + True + 6 + False + <Version>2</Version><Count>6</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Red</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Orange</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Green</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Green</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Green</Color> + Black + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;VCU;VCU_State;VCU_CTRL_State;1;CAN-T;;-1;;;Value;;;0 + + + Xb9dd4e42eb37fe4b14eb962e8cfff153e017 + 57, 15 + 51, 39 + TopCenter + NEG_AIR + + + X704b6970eed34e430de85adefaac2c8cc148 + 56, 15 + -1, 39 + TopCenter + TS_WAIT + + + X61d8864be3431e4307e8093e20525426b5c9 + 24, 24 + 15, 17 + True + 5 + False + <Version>2</Version><Count>6</Count><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Black</Color><RxValue>0</RxValue><LowerUpper>Lower</LowerUpper><TxValue>0</TxValue><Color>Orange</Color><RxValue>1</RxValue><LowerUpper>Lower</LowerUpper><TxValue>1</TxValue><Color>Green</Color><RxValue>2</RxValue><LowerUpper>Lower</LowerUpper><TxValue>2</TxValue><Color>Green</Color><RxValue>3</RxValue><LowerUpper>Lower</LowerUpper><TxValue>3</TxValue><Color>Green</Color><RxValue>4</RxValue><LowerUpper>Lower</LowerUpper><TxValue>4</TxValue><Color>Green</Color> + Black + Orange + <Version>2</Version><LowerUpper>Lower</LowerUpper><RxValue>0</RxValue> + 1;Lower;0 + 0 + 8;2;CANT;VCU;VCU_State;VCU_CTRL_State;1;CAN-T;;-1;;;Value;;;0 + + X9e07c1b3ecef2e49f0eb468eb62a17f9ced0 + 320, 94 + 5, 5 + VCU CTRL State + 6 + False + + Panel + 901, 522 + 0, 0 + White + + \ No newline at end of file diff --git a/scripts/canoe/pm100_fault_codes.can b/scripts/canoe/pm100_fault_codes.can new file mode 100644 index 00000000..dc5b0fba --- /dev/null +++ b/scripts/canoe/pm100_fault_codes.can @@ -0,0 +1,111 @@ +/*@!Encoding:1252*/ +variables { +} + +void AppendFault(char buffer[], long bufferSize, char faultStr[]) { + if ((strlen(buffer) + strlen(faultStr) + 3) < bufferSize) { + strncat(buffer, faultStr, bufferSize); + strncat(buffer, " | ", bufferSize); + } +} + +on message PM100_Fault_Codes { + char text[2048]; + dword postFaults; + dword runFaults; + int len; + + // Clear buffer + strncpy(text, "", elCount(text)); + + // Reassemble 16-bit CAN signals into 32-bit fault words + postFaults = ((dword)this.PM100_Post_Fault_Hi << 16) | (dword)this.PM100_Post_Fault_Lo; + runFaults = ((dword)this.PM100_Run_Fault_Hi << 16) | (dword)this.PM100_Run_Fault_Lo; + + if (postFaults == 0 && runFaults == 0) { + snprintf(text, elCount(text), "OK"); + sysSetVariableString(sysvar::PM100_Fault_Text, text); + return; + } + + // --- POST FAULTS --- + if (postFaults != 0) { + if (postFaults & 0x00000001) AppendFault(text, elCount(text), "POST: Hardware Gate/Desaturation"); + if (postFaults & 0x00000002) AppendFault(text, elCount(text), "POST: HW Over-current"); + if (postFaults & 0x00000004) AppendFault(text, elCount(text), "POST: Accelerator Shorted"); + if (postFaults & 0x00000008) AppendFault(text, elCount(text), "POST: Accelerator Open"); + if (postFaults & 0x00000010) AppendFault(text, elCount(text), "POST: Current Sensor Low"); + if (postFaults & 0x00000020) AppendFault(text, elCount(text), "POST: Current Sensor High"); + if (postFaults & 0x00000040) AppendFault(text, elCount(text), "POST: Module Temperature Low"); + if (postFaults & 0x00000080) AppendFault(text, elCount(text), "POST: Module Temperature High"); + if (postFaults & 0x00000100) AppendFault(text, elCount(text), "POST: Control PCB Temperature Low"); + if (postFaults & 0x00000200) AppendFault(text, elCount(text), "POST: Control PCB Temperature High"); + if (postFaults & 0x00000400) AppendFault(text, elCount(text), "POST: Gate Drive PCB Temperature Low"); + if (postFaults & 0x00000800) AppendFault(text, elCount(text), "POST: Gate Drive PCB Temperature High"); + if (postFaults & 0x00001000) AppendFault(text, elCount(text), "POST: 5V Sense Voltage Low"); + if (postFaults & 0x00002000) AppendFault(text, elCount(text), "POST: 5V Sense Voltage High"); + if (postFaults & 0x00004000) AppendFault(text, elCount(text), "POST: 12V Sense Voltage Low"); + if (postFaults & 0x00008000) AppendFault(text, elCount(text), "POST: 12V Sense Voltage High"); + if (postFaults & 0x00010000) AppendFault(text, elCount(text), "POST: 2.5V Sense Voltage Low"); + if (postFaults & 0x00020000) AppendFault(text, elCount(text), "POST: 2.5V Sense Voltage High"); + if (postFaults & 0x00040000) AppendFault(text, elCount(text), "POST: 1.5V Sense Voltage Low"); + if (postFaults & 0x00080000) AppendFault(text, elCount(text), "POST: 1.5V Sense Voltage High"); + if (postFaults & 0x00100000) AppendFault(text, elCount(text), "POST: DC Bus Voltage High"); + if (postFaults & 0x00200000) AppendFault(text, elCount(text), "POST: DC Bus Voltage Low"); + if (postFaults & 0x00400000) AppendFault(text, elCount(text), "POST: Pre-charge Timeout"); + if (postFaults & 0x00800000) AppendFault(text, elCount(text), "POST: Pre-charge Voltage Failure"); + if (postFaults & 0x01000000) AppendFault(text, elCount(text), "POST: EEPROM Checksum Invalid"); + if (postFaults & 0x02000000) AppendFault(text, elCount(text), "POST: EEPROM Data Out of Range"); + if (postFaults & 0x04000000) AppendFault(text, elCount(text), "POST: EEPROM Update Required"); + if (postFaults & 0x08000000) AppendFault(text, elCount(text), "POST: Hardware DC Bus Over-Voltage init"); + if (postFaults & 0x10000000) AppendFault(text, elCount(text), "POST: Gen3 Reserved / Gen5 Gate Drv Init"); + if (postFaults & 0x20000000) AppendFault(text, elCount(text), "POST: Reserved (0x20000000)"); + if (postFaults & 0x40000000) AppendFault(text, elCount(text), "POST: Brake Shorted"); + if (postFaults & 0x80000000) AppendFault(text, elCount(text), "POST: Brake Open"); + } + + // --- RUN FAULTS --- + if (runFaults != 0) { + if (runFaults & 0x00000001) AppendFault(text, elCount(text), "RUN: Motor Over-speed"); + if (runFaults & 0x00000002) AppendFault(text, elCount(text), "RUN: Over-current"); + if (runFaults & 0x00000004) AppendFault(text, elCount(text), "RUN: Over-voltage"); + if (runFaults & 0x00000008) AppendFault(text, elCount(text), "RUN: Inverter Over-temperature"); + if (runFaults & 0x00000010) AppendFault(text, elCount(text), "RUN: Accelerator Input Shorted"); + if (runFaults & 0x00000020) AppendFault(text, elCount(text), "RUN: Accelerator Input Open"); + if (runFaults & 0x00000040) AppendFault(text, elCount(text), "RUN: Direction Command"); + if (runFaults & 0x00000080) AppendFault(text, elCount(text), "RUN: Inverter Response Time-out"); + if (runFaults & 0x00000100) AppendFault(text, elCount(text), "RUN: Hardware Gate/Desaturation"); + if (runFaults & 0x00000200) AppendFault(text, elCount(text), "RUN: Hardware Over-current"); + if (runFaults & 0x00000400) AppendFault(text, elCount(text), "RUN: Under-voltage"); + if (runFaults & 0x00000800) AppendFault(text, elCount(text), "RUN: CAN Command Message Lost"); + if (runFaults & 0x00001000) AppendFault(text, elCount(text), "RUN: Motor Overtemperature"); + if (runFaults & 0x00002000) AppendFault(text, elCount(text), "RUN: Reserved (0x00002000)"); + if (runFaults & 0x00004000) AppendFault(text, elCount(text), "RUN: Reserved (0x00004000)"); + if (runFaults & 0x00008000) AppendFault(text, elCount(text), "RUN: Reserved (0x00008000)"); + if (runFaults & 0x00010000) AppendFault(text, elCount(text), "RUN: Brake Input Shorted"); + if (runFaults & 0x00020000) AppendFault(text, elCount(text), "RUN: Brake Input Open"); + if (runFaults & 0x00040000) AppendFault(text, elCount(text), "RUN: Module A Over-temperature"); + if (runFaults & 0x00080000) AppendFault(text, elCount(text), "RUN: Module B Over-temperature"); + if (runFaults & 0x00100000) AppendFault(text, elCount(text), "RUN: Module C Over-temperature"); + if (runFaults & 0x00200000) AppendFault(text, elCount(text), "RUN: PCB Over-temperature"); + if (runFaults & 0x00400000) AppendFault(text, elCount(text), "RUN: Gate Drive Board 1 Over-temp"); + if (runFaults & 0x00800000) AppendFault(text, elCount(text), "RUN: Gate Drive Board 2 Over-temp"); + if (runFaults & 0x01000000) AppendFault(text, elCount(text), "RUN: Gate Drive Board 3 Over-temp"); + if (runFaults & 0x02000000) AppendFault(text, elCount(text), "RUN: Current Sensor Fault"); + if (runFaults & 0x04000000) AppendFault(text, elCount(text), "RUN: Gen3 Rsvd / Gen5 Gate Drv Over-Volt"); + if (runFaults & 0x08000000) AppendFault(text, elCount(text), "RUN: Gen3 HW DC Bus Over-Volt / Gen5 Rsvd"); + if (runFaults & 0x10000000) AppendFault(text, elCount(text), "RUN: Gen3 Rsvd / Gen5 HW DC Bus Over-Volt"); + if (runFaults & 0x20000000) AppendFault(text, elCount(text), "RUN: Reserved (0x20000000)"); + if (runFaults & 0x40000000) AppendFault(text, elCount(text), "RUN: Resolver Not Connected"); + if (runFaults & 0x80000000) AppendFault(text, elCount(text), "RUN: Reserved (0x80000000)"); + } + + // Clean up trailing delimiter " | " + len = strlen(text); + if (len >= 3) { + text[len - 3] = '\0'; + } + + // Assign to system variable + sysSetVariableString(sysvar::PM100_Fault_Text, text); +} diff --git a/scripts/canoe/vcu_fault_codes.can b/scripts/canoe/vcu_fault_codes.can new file mode 100644 index 00000000..bae57879 --- /dev/null +++ b/scripts/canoe/vcu_fault_codes.can @@ -0,0 +1,52 @@ +/*@!Encoding:1252*/ +variables { +} + +void AppendFault(char buffer[], long bufferSize, char faultStr[]) { + if ((strlen(buffer) + strlen(faultStr) + 3) < bufferSize) { + strncat(buffer, faultStr, bufferSize); + strncat(buffer, " | ", bufferSize); + } +} + +on message VCU_Error { + char text[2048]; + dword ctrlFaults; + byte pm100Error; + byte scsError; + int len; + + // Clear buffer + strncpy(text, "", elCount(text)); + + // Extract all relevant signals from the message + ctrlFaults = (dword)this.VCU_CTRL_Error; + pm100Error = (byte)this.VCU_PM100_Error; + scsError = (byte)this.VCU_SCS_Error; + + // --- VCU CTRL FAULTS --- + if (ctrlFaults & 0x01) AppendFault(text, elCount(text), "Init"); + if (ctrlFaults & 0x02) AppendFault(text, elCount(text), "TS_Timeout"); + if (ctrlFaults & 0x04) AppendFault(text, elCount(text), "Precharge"); + if (ctrlFaults & 0x08) AppendFault(text, elCount(text), "TRC_Fault"); + if (ctrlFaults & 0x10) AppendFault(text, elCount(text), "Inv_Fault"); + + // --- ADDITIONAL ERRORS --- + if (pm100Error == 1) AppendFault(text, elCount(text), "PM100_Error"); + if (scsError == 1) AppendFault(text, elCount(text), "SCS_Error"); + + len = strlen(text); + + // Determine final output state based on whether any faults were appended + if (len == 0) { + snprintf(text, elCount(text), "OK"); + } else { + // Clean up trailing delimiter " | " + if (len >= 3) { + text[len - 3] = '\0'; + } + } + + // Assign to system variable + sysSetVariableString(sysvar::VCU_Fault_Text, text); +} diff --git a/src/AZURE_RTOS/App/app_azure_rtos.c b/src/AZURE_RTOS/App/app_azure_rtos.c index 05b6b41f..e097f268 100644 --- a/src/AZURE_RTOS/App/app_azure_rtos.c +++ b/src/AZURE_RTOS/App/app_azure_rtos.c @@ -53,6 +53,30 @@ __ALIGN_BEGIN static UCHAR tx_byte_pool_buffer[TX_APP_MEM_POOL_SIZE] __ALIGN_END; static TX_BYTE_POOL tx_app_byte_pool; +/* USER CODE BEGIN FX_Pool_Buffer */ +/* USER CODE END FX_Pool_Buffer */ +#if defined ( __ICCARM__ ) +#pragma data_alignment=4 +#endif +__ALIGN_BEGIN static UCHAR fx_byte_pool_buffer[FX_APP_MEM_POOL_SIZE] __ALIGN_END; +static TX_BYTE_POOL fx_app_byte_pool; + +/* USER CODE BEGIN UX_HOST_Pool_Buffer */ +/* USER CODE END UX_HOST_Pool_Buffer */ +#if defined ( __ICCARM__ ) +#pragma data_alignment=4 +#endif +__ALIGN_BEGIN static UCHAR ux_host_byte_pool_buffer[UX_HOST_APP_MEM_POOL_SIZE] __ALIGN_END; +static TX_BYTE_POOL ux_host_app_byte_pool; + +/* USER CODE BEGIN UX_Device_Pool_Buffer */ +/* USER CODE END UX_Device_Pool_Buffer */ +#if defined ( __ICCARM__ ) +#pragma data_alignment=4 +#endif +__ALIGN_BEGIN static UCHAR ux_device_byte_pool_buffer[UX_DEVICE_APP_MEM_POOL_SIZE] __ALIGN_END; +static TX_BYTE_POOL ux_device_app_byte_pool; + /* USER CODE BEGIN PV */ /* USER CODE END PV */ @@ -102,6 +126,83 @@ VOID tx_application_define(VOID *first_unused_memory) } + if (tx_byte_pool_create(&fx_app_byte_pool, "Fx App memory pool", fx_byte_pool_buffer, FX_APP_MEM_POOL_SIZE) != TX_SUCCESS) + { + /* USER CODE BEGIN FX_Byte_Pool_Error */ + + /* USER CODE END FX_Byte_Pool_Error */ + } + else + { + /* USER CODE BEGIN FX_Byte_Pool_Success */ + + /* USER CODE END FX_Byte_Pool_Success */ + + memory_ptr = (VOID *)&fx_app_byte_pool; + + if (MX_FileX_Init(memory_ptr) != FX_SUCCESS) + { + /* USER CODE BEGIN MX_FileX_Init_Error */ + + /* USER CODE END MX_FileX_Init_Error */ + } + + /* USER CODE BEGIN MX_FileX_Init_Success */ + + /* USER CODE END MX_FileX_Init_Success */ + } + + if (tx_byte_pool_create(&ux_host_app_byte_pool, "Ux App memory pool", ux_host_byte_pool_buffer, UX_HOST_APP_MEM_POOL_SIZE) != TX_SUCCESS) + { + /* USER CODE BEGIN TX_Byte_Pool_Error */ + + /* USER CODE END TX_Byte_Pool_Error */ + } + else + { + /* USER CODE BEGIN UX_HOST_Byte_Pool_Success */ + + /* USER CODE END UX_HOST_Byte_Pool_Success */ + + memory_ptr = (VOID *)&ux_host_app_byte_pool; + + if (MX_USBX_Host_Init(memory_ptr) != UX_SUCCESS) + { + /* USER CODE BEGIN MX_USBX_Host_Init_Error */ + + /* USER CODE END MX_USBX_Host_Init_Error */ + } + + /* USER CODE BEGIN MX_USBX_Host_Init_Success */ + + /* USER CODE END MX_USBX_Host_Init_Success */ + } + + if (tx_byte_pool_create(&ux_device_app_byte_pool, "Ux App memory pool", ux_device_byte_pool_buffer, UX_DEVICE_APP_MEM_POOL_SIZE) != TX_SUCCESS) + { + /* USER CODE BEGIN UX_Device_Byte_Pool_Error */ + + /* USER CODE END UX_Device_Byte_Pool_Error */ + } + else + { + /* USER CODE BEGIN UX_Device_Byte_Pool_Success */ + + /* USER CODE END UX_Device_Byte_Pool_Success */ + + memory_ptr = (VOID *)&ux_device_app_byte_pool; + + if (MX_USBX_Device_Init(memory_ptr) != UX_SUCCESS) + { + /* USER CODE BEGIN MX_USBX_Device_Init_Error */ + + /* USER CODE END MX_USBX_Device_Init_Error */ + } + + /* USER CODE BEGIN MX_USBX_Device_Init_Success */ + + /* USER CODE END MX_USBX_Device_Init_Success */ + } } /* USER CODE BEGIN 0 */ diff --git a/src/AZURE_RTOS/App/app_azure_rtos.h b/src/AZURE_RTOS/App/app_azure_rtos.h index 28a0ede3..6beff001 100644 --- a/src/AZURE_RTOS/App/app_azure_rtos.h +++ b/src/AZURE_RTOS/App/app_azure_rtos.h @@ -30,6 +30,12 @@ extern "C" { #include "app_azure_rtos_config.h" #include "app_threadx.h" + +#include "app_filex.h" + +#include "app_usbx_host.h" + +#include "app_usbx_device.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ diff --git a/src/AZURE_RTOS/App/app_azure_rtos_config.h b/src/AZURE_RTOS/App/app_azure_rtos_config.h index 7aa8f141..35f34616 100644 --- a/src/AZURE_RTOS/App/app_azure_rtos_config.h +++ b/src/AZURE_RTOS/App/app_azure_rtos_config.h @@ -40,7 +40,13 @@ extern "C" { /* Exported constants --------------------------------------------------------*/ /* define the size of static threadX byte memory pools */ -#define TX_APP_MEM_POOL_SIZE 16384 +#define TX_APP_MEM_POOL_SIZE 131072 + +#define FX_APP_MEM_POOL_SIZE 2048 + +#define UX_HOST_APP_MEM_POOL_SIZE 1024 + +#define UX_DEVICE_APP_MEM_POOL_SIZE 8192 /* USER CODE BEGIN EC */ diff --git a/src/Core/Inc/RTE_Components.h b/src/Core/Inc/RTE_Components.h index 412600e1..04324117 100644 --- a/src/Core/Inc/RTE_Components.h +++ b/src/Core/Inc/RTE_Components.h @@ -23,6 +23,13 @@ /* Defines ------------------------------------------------------------------*/ /* STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0 */ +#define USBXHOST_ENABLED +#define UX_HOST_CONTROLLERS_ENABLED +#define USBXDEVICE_ENABLED +#define UX_DEVICE_CONTROLLERS_ENABLED +#define UX_DEVICE_STORAGE +#define FILEX_ENABLED +#define FX_SD_INTERFACE #define THREADX_ENABLED #endif /* __RTE_COMPONENTS_H__ */ diff --git a/src/Core/Inc/adc.h b/src/Core/Inc/adc.h index 82201877..585bf396 100644 --- a/src/Core/Inc/adc.h +++ b/src/Core/Inc/adc.h @@ -36,15 +36,12 @@ extern ADC_HandleTypeDef hadc1; extern ADC_HandleTypeDef hadc2; -extern ADC_HandleTypeDef hadc3; - /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ void MX_ADC1_Init(void); void MX_ADC2_Init(void); -void MX_ADC3_Init(void); /* USER CODE BEGIN Prototypes */ diff --git a/src/Core/Inc/dma.h b/src/Core/Inc/dma.h new file mode 100644 index 00000000..cbf3957b --- /dev/null +++ b/src/Core/Inc/dma.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.h + * @brief This file contains all the function prototypes for + * the dma.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __DMA_H__ +#define __DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* DMA memory to memory transfer handles -------------------------------------*/ + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_DMA_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DMA_H__ */ + diff --git a/src/Core/Inc/i2c.h b/src/Core/Inc/i2c.h new file mode 100644 index 00000000..bba89bcf --- /dev/null +++ b/src/Core/Inc/i2c.h @@ -0,0 +1,55 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.h + * @brief This file contains all the function prototypes for + * the i2c.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern I2C_HandleTypeDef hi2c2; + +extern I2C_HandleTypeDef hi2c4; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_I2C2_Init(void); +void MX_I2C4_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2C_H__ */ + diff --git a/src/Core/Inc/main.h b/src/Core/Inc/main.h index bf98a3dd..fe66fe9c 100644 --- a/src/Core/Inc/main.h +++ b/src/Core/Inc/main.h @@ -57,55 +57,144 @@ void Error_Handler(void); /* USER CODE END EFP */ /* Private defines -----------------------------------------------------------*/ -#define VC_LEDS_Pin GPIO_PIN_3 +#define ROB_LED_Pin GPIO_PIN_2 +#define ROB_LED_GPIO_Port GPIOE +#define SD_CARD_DETECT_Pin GPIO_PIN_3 +#define SD_CARD_DETECT_GPIO_Port GPIOE +#define RS232_BAD_Pin GPIO_PIN_6 +#define RS232_BAD_GPIO_Port GPIOE +#define RS232_FORCEOFF_Pin GPIO_PIN_13 +#define RS232_FORCEOFF_GPIO_Port GPIOC +#define RS232_FORCEON_Pin GPIO_PIN_14 +#define RS232_FORCEON_GPIO_Port GPIOC +#define TOO_HOT_Pin GPIO_PIN_2 +#define TOO_HOT_GPIO_Port GPIOF +#define R2D_SIREN_Pin GPIO_PIN_6 +#define R2D_SIREN_GPIO_Port GPIOF +#define PWM_SPARE_2_Pin GPIO_PIN_7 +#define PWM_SPARE_2_GPIO_Port GPIOF +#define IMU_ADDR_Pin GPIO_PIN_10 +#define IMU_ADDR_GPIO_Port GPIOF +#define IMU_MODE_Pin GPIO_PIN_0 +#define IMU_MODE_GPIO_Port GPIOC +#define EEPROM_WC_Pin GPIO_PIN_1 +#define EEPROM_WC_GPIO_Port GPIOC +#define SPARE_ADC_Pin GPIO_PIN_3 +#define SPARE_ADC_GPIO_Port GPIOA +#define DASH_ROTARY_ADC_Pin GPIO_PIN_4 +#define DASH_ROTARY_ADC_GPIO_Port GPIOA +#define CT_ADC_Pin GPIO_PIN_5 +#define CT_ADC_GPIO_Port GPIOA +#define SAGL_ADC_Pin GPIO_PIN_6 +#define SAGL_ADC_GPIO_Port GPIOA +#define BPS_R_ADC_Pin GPIO_PIN_7 +#define BPS_R_ADC_GPIO_Port GPIOA +#define BPS_F_ADC_Pin GPIO_PIN_4 +#define BPS_F_ADC_GPIO_Port GPIOC +#define APPS_2_ADC_Pin GPIO_PIN_5 +#define APPS_2_ADC_GPIO_Port GPIOC +#define APPS_1_ADC_Pin GPIO_PIN_0 +#define APPS_1_ADC_GPIO_Port GPIOB +#define PWM_SPARE_1_Pin GPIO_PIN_1 +#define PWM_SPARE_1_GPIO_Port GPIOB +#define LS_LED_6_Pin GPIO_PIN_13 +#define LS_LED_6_GPIO_Port GPIOF +#define VC_LEDS_Pin GPIO_PIN_7 #define VC_LEDS_GPIO_Port GPIOE -#define DRS_LED_Pin GPIO_PIN_4 -#define DRS_LED_GPIO_Port GPIOE -#define TS_ON_LED_Pin GPIO_PIN_5 -#define TS_ON_LED_GPIO_Port GPIOE -#define R2D_LED_Pin GPIO_PIN_6 +#define LED_4_Pin GPIO_PIN_8 +#define LED_4_GPIO_Port GPIOE +#define R2D_LED_Pin GPIO_PIN_9 #define R2D_LED_GPIO_Port GPIOE -#define USER_BUTTON_Pin GPIO_PIN_13 -#define USER_BUTTON_GPIO_Port GPIOC -#define USER_BUTTON_EXTI_IRQn EXTI15_10_IRQn -#define TS_READY_Pin GPIO_PIN_1 -#define TS_READY_GPIO_Port GPIOF -#define R2D_BTN_Pin GPIO_PIN_2 -#define R2D_BTN_GPIO_Port GPIOF -#define SAGL_Pin GPIO_PIN_3 -#define SAGL_GPIO_Port GPIOF -#define TS_ON_BTN_Pin GPIO_PIN_5 -#define TS_ON_BTN_GPIO_Port GPIOF -#define DRS_BTN_Pin GPIO_PIN_10 -#define DRS_BTN_GPIO_Port GPIOF -#define MCO_Pin GPIO_PIN_0 -#define MCO_GPIO_Port GPIOH -#define BPS_ADC_Pin GPIO_PIN_0 -#define BPS_ADC_GPIO_Port GPIOC -#define APPS_2_ADC_Pin GPIO_PIN_3 -#define APPS_2_ADC_GPIO_Port GPIOC -#define DRS_Pin GPIO_PIN_0 -#define DRS_GPIO_Port GPIOA -#define APPS_1_ADC_Pin GPIO_PIN_3 -#define APPS_1_ADC_GPIO_Port GPIOA -#define GREEN_LED_Pin GPIO_PIN_0 -#define GREEN_LED_GPIO_Port GPIOB -#define TS_ON_Pin GPIO_PIN_14 -#define TS_ON_GPIO_Port GPIOF -#define R2D_SIREN_Pin GPIO_PIN_15 -#define R2D_SIREN_GPIO_Port GPIOF -#define STATUS_Pin GPIO_PIN_9 +#define LED_2_Pin GPIO_PIN_10 +#define LED_2_GPIO_Port GPIOE +#define TS_ON_LED_Pin GPIO_PIN_11 +#define TS_ON_LED_GPIO_Port GPIOE +#define TS_ON_Pin GPIO_PIN_13 +#define TS_ON_GPIO_Port GPIOE +#define BRAKELIGHT_EN_Pin GPIO_PIN_14 +#define BRAKELIGHT_EN_GPIO_Port GPIOE +#define STATUS_Pin GPIO_PIN_15 #define STATUS_GPIO_Port GPIOE -#define BRAKE_PRESSED_Pin GPIO_PIN_11 -#define BRAKE_PRESSED_GPIO_Port GPIOE -#define RED_LED_Pin GPIO_PIN_14 -#define RED_LED_GPIO_Port GPIOB -#define TMS_Pin GPIO_PIN_13 -#define TMS_GPIO_Port GPIOA -#define TCK_Pin GPIO_PIN_14 -#define TCK_GPIO_Port GPIOA -#define BLUE_LED_Pin GPIO_PIN_7 -#define BLUE_LED_GPIO_Port GPIOB +#define SPARE_OUT_7_Pin GPIO_PIN_10 +#define SPARE_OUT_7_GPIO_Port GPIOB +#define FAN_PWM_R_Pin GPIO_PIN_11 +#define FAN_PWM_R_GPIO_Port GPIOB +#define SPARE_OUT_6_Pin GPIO_PIN_12 +#define SPARE_OUT_6_GPIO_Port GPIOB +#define SPARE_OUT_5_Pin GPIO_PIN_13 +#define SPARE_OUT_5_GPIO_Port GPIOB +#define SPARE_OUT_4_Pin GPIO_PIN_14 +#define SPARE_OUT_4_GPIO_Port GPIOB +#define FAN_PWM_L_Pin GPIO_PIN_15 +#define FAN_PWM_L_GPIO_Port GPIOB +#define WHEELSPEED_RR_Pin GPIO_PIN_8 +#define WHEELSPEED_RR_GPIO_Port GPIOD +#define WHEELSPEED_RR_EXTI_IRQn EXTI9_5_IRQn +#define WHEELSPEED_RL_Pin GPIO_PIN_9 +#define WHEELSPEED_RL_GPIO_Port GPIOD +#define WHEELSPEED_RL_EXTI_IRQn EXTI9_5_IRQn +#define WHEELSPEED_FR_Pin GPIO_PIN_10 +#define WHEELSPEED_FR_GPIO_Port GPIOD +#define WHEELSPEED_FR_EXTI_IRQn EXTI15_10_IRQn +#define WHEELSPEED_FL_Pin GPIO_PIN_11 +#define WHEELSPEED_FL_GPIO_Port GPIOD +#define WHEELSPEED_FL_EXTI_IRQn EXTI15_10_IRQn +#define SPARE_IN_3_Pin GPIO_PIN_12 +#define SPARE_IN_3_GPIO_Port GPIOD +#define GPS_PPS_Pin GPIO_PIN_13 +#define GPS_PPS_GPIO_Port GPIOD +#define SPARE_IN_2_Pin GPIO_PIN_14 +#define SPARE_IN_2_GPIO_Port GPIOD +#define SPARE_OUT_3_Pin GPIO_PIN_15 +#define SPARE_OUT_3_GPIO_Port GPIOD +#define SPARE_OUT_2_Pin GPIO_PIN_2 +#define SPARE_OUT_2_GPIO_Port GPIOG +#define SPARE_OUT_1_Pin GPIO_PIN_3 +#define SPARE_OUT_1_GPIO_Port GPIOG +#define APPS_PWR_GOOD_Pin GPIO_PIN_4 +#define APPS_PWR_GOOD_GPIO_Port GPIOG +#define SPARE_IN_1_Pin GPIO_PIN_5 +#define SPARE_IN_1_GPIO_Port GPIOG +#define SW_BTN_2_Pin GPIO_PIN_6 +#define SW_BTN_2_GPIO_Port GPIOG +#define SW_BTN_1_Pin GPIO_PIN_7 +#define SW_BTN_1_GPIO_Port GPIOG +#define R2D_BTN_Pin GPIO_PIN_8 +#define R2D_BTN_GPIO_Port GPIOG +#define TS_ON_BTN_Pin GPIO_PIN_6 +#define TS_ON_BTN_GPIO_Port GPIOC +#define TS_READY_Pin GPIO_PIN_7 +#define TS_READY_GPIO_Port GPIOC +#define DEBUG_GPIO_1_Pin GPIO_PIN_0 +#define DEBUG_GPIO_1_GPIO_Port GPIOD +#define DEBUG_GPIO_2_Pin GPIO_PIN_1 +#define DEBUG_GPIO_2_GPIO_Port GPIOD +#define DEBUG_GPIO_3_Pin GPIO_PIN_3 +#define DEBUG_GPIO_3_GPIO_Port GPIOD +#define DEBUG_GPIO_4_Pin GPIO_PIN_4 +#define DEBUG_GPIO_4_GPIO_Port GPIOD +#define DEBUG_GPIO_5_Pin GPIO_PIN_5 +#define DEBUG_GPIO_5_GPIO_Port GPIOD +#define DEBUG_GPIO_6_Pin GPIO_PIN_6 +#define DEBUG_GPIO_6_GPIO_Port GPIOD +#define DEBUG_GPIO_7_Pin GPIO_PIN_7 +#define DEBUG_GPIO_7_GPIO_Port GPIOD +#define DEBUG_GPIO_8_Pin GPIO_PIN_9 +#define DEBUG_GPIO_8_GPIO_Port GPIOG +#define DEBUG_GPIO_9_Pin GPIO_PIN_10 +#define DEBUG_GPIO_9_GPIO_Port GPIOG +#define DEBUG_GPIO_10_Pin GPIO_PIN_11 +#define DEBUG_GPIO_10_GPIO_Port GPIOG +#define CAN_T_RX_Pin GPIO_PIN_5 +#define CAN_T_RX_GPIO_Port GPIOB +#define CAN_T_TX_Pin GPIO_PIN_6 +#define CAN_T_TX_GPIO_Port GPIOB +#define USER_BUTTON_Pin GPIO_PIN_7 +#define USER_BUTTON_GPIO_Port GPIOB +#define CAN_S_RX_Pin GPIO_PIN_8 +#define CAN_S_RX_GPIO_Port GPIOB +#define CAN_S_TX_Pin GPIO_PIN_9 +#define CAN_S_TX_GPIO_Port GPIOB /* USER CODE BEGIN Private defines */ diff --git a/src/Core/Inc/sdmmc.h b/src/Core/Inc/sdmmc.h new file mode 100644 index 00000000..7d887e18 --- /dev/null +++ b/src/Core/Inc/sdmmc.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file sdmmc.h + * @brief This file contains all the function prototypes for + * the sdmmc.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SDMMC_H__ +#define __SDMMC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern SD_HandleTypeDef hsd1; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_SDMMC1_SD_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SDMMC_H__ */ + diff --git a/src/Core/Inc/spi.h b/src/Core/Inc/spi.h new file mode 100644 index 00000000..2c01ae63 --- /dev/null +++ b/src/Core/Inc/spi.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.h + * @brief This file contains all the function prototypes for + * the spi.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern SPI_HandleTypeDef hspi6; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_SPI6_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ + diff --git a/src/Core/Inc/stm32f7xx_hal_conf.h b/src/Core/Inc/stm32f7xx_hal_conf.h index 735fb63c..f8f98dcc 100644 --- a/src/Core/Inc/stm32f7xx_hal_conf.h +++ b/src/Core/Inc/stm32f7xx_hal_conf.h @@ -60,17 +60,17 @@ /* #define HAL_RNG_MODULE_ENABLED */ /* #define HAL_RTC_MODULE_ENABLED */ /* #define HAL_SAI_MODULE_ENABLED */ -/* #define HAL_SD_MODULE_ENABLED */ +#define HAL_SD_MODULE_ENABLED /* #define HAL_MMC_MODULE_ENABLED */ /* #define HAL_SPDIFRX_MODULE_ENABLED */ -/* #define HAL_SPI_MODULE_ENABLED */ +#define HAL_SPI_MODULE_ENABLED #define HAL_TIM_MODULE_ENABLED #define HAL_UART_MODULE_ENABLED -/* #define HAL_USART_MODULE_ENABLED */ +#define HAL_USART_MODULE_ENABLED /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_SMARTCARD_MODULE_ENABLED */ /* #define HAL_WWDG_MODULE_ENABLED */ -/* #define HAL_PCD_MODULE_ENABLED */ +#define HAL_PCD_MODULE_ENABLED /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_DFSDM_MODULE_ENABLED */ /* #define HAL_DSI_MODULE_ENABLED */ @@ -94,7 +94,7 @@ * (when HSE is used as system clock source, directly or through the PLL). */ #if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ + #define HSE_VALUE ((uint32_t)25000000U) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (HSE_STARTUP_TIMEOUT) @@ -210,7 +210,7 @@ #define MAC_ADDR5 0U /* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE /* buffer size for receive */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ #define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ #define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ diff --git a/src/Core/Inc/stm32f7xx_it.h b/src/Core/Inc/stm32f7xx_it.h index 6347fa59..cac76bb0 100644 --- a/src/Core/Inc/stm32f7xx_it.h +++ b/src/Core/Inc/stm32f7xx_it.h @@ -22,7 +22,7 @@ #define __STM32F7xx_IT_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Private includes ----------------------------------------------------------*/ @@ -52,14 +52,24 @@ void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void DebugMon_Handler(void); +void ADC_IRQHandler(void); void CAN1_TX_IRQHandler(void); void CAN1_RX0_IRQHandler(void); void CAN1_RX1_IRQHandler(void); -void TIM3_IRQHandler(void); +void CAN1_SCE_IRQHandler(void); +void EXTI9_5_IRQHandler(void); void EXTI15_10_IRQHandler(void); +void SDMMC1_IRQHandler(void); +void TIM6_DAC_IRQHandler(void); +void DMA2_Stream0_IRQHandler(void); +void DMA2_Stream2_IRQHandler(void); +void DMA2_Stream3_IRQHandler(void); void CAN2_TX_IRQHandler(void); void CAN2_RX0_IRQHandler(void); void CAN2_RX1_IRQHandler(void); +void CAN2_SCE_IRQHandler(void); +void OTG_FS_IRQHandler(void); +void DMA2_Stream6_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/src/Core/Inc/tim.h b/src/Core/Inc/tim.h new file mode 100644 index 00000000..9e052149 --- /dev/null +++ b/src/Core/Inc/tim.h @@ -0,0 +1,66 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.h + * @brief This file contains all the function prototypes for + * the tim.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __TIM_H__ +#define __TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern TIM_HandleTypeDef htim2; + +extern TIM_HandleTypeDef htim3; + +extern TIM_HandleTypeDef htim10; + +extern TIM_HandleTypeDef htim11; + +extern TIM_HandleTypeDef htim12; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_TIM2_Init(void); +void MX_TIM3_Init(void); +void MX_TIM10_Init(void); +void MX_TIM11_Init(void); +void MX_TIM12_Init(void); + +void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIM_H__ */ + diff --git a/src/Core/Inc/usart.h b/src/Core/Inc/usart.h index e8c41d5b..2c98518d 100644 --- a/src/Core/Inc/usart.h +++ b/src/Core/Inc/usart.h @@ -32,13 +32,16 @@ extern "C" { /* USER CODE END Includes */ -extern UART_HandleTypeDef huart1; +extern UART_HandleTypeDef huart8; + +extern USART_HandleTypeDef husart1; /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ -void MX_USART1_UART_Init(void); +void MX_UART8_Init(void); +void MX_USART1_Init(void); /* USER CODE BEGIN Prototypes */ diff --git a/src/Core/Inc/usb_otg.h b/src/Core/Inc/usb_otg.h new file mode 100644 index 00000000..3787e76b --- /dev/null +++ b/src/Core/Inc/usb_otg.h @@ -0,0 +1,52 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usb_otg.h + * @brief This file contains all the function prototypes for + * the usb_otg.c file + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __USB_OTG_H__ +#define __USB_OTG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +extern PCD_HandleTypeDef hpcd_USB_OTG_FS; + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +void MX_USB_OTG_FS_PCD_Init(void); + +/* USER CODE BEGIN Prototypes */ + +/* USER CODE END Prototypes */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_OTG_H__ */ + diff --git a/src/Core/Src/adc.c b/src/Core/Src/adc.c index 55ed9d59..ac5d32b3 100644 --- a/src/Core/Src/adc.c +++ b/src/Core/Src/adc.c @@ -26,7 +26,8 @@ ADC_HandleTypeDef hadc1; ADC_HandleTypeDef hadc2; -ADC_HandleTypeDef hadc3; +DMA_HandleTypeDef hdma_adc1; +DMA_HandleTypeDef hdma_adc2; /* ADC1 init function */ void MX_ADC1_Init(void) @@ -45,16 +46,16 @@ void MX_ADC1_Init(void) /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc1.Instance = ADC1; - hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; hadc1.Init.Resolution = ADC_RESOLUTION_12B; - hadc1.Init.ScanConvMode = ADC_SCAN_DISABLE; - hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.ScanConvMode = ADC_SCAN_ENABLE; + hadc1.Init.ContinuousConvMode = ENABLE; hadc1.Init.DiscontinuousConvMode = DISABLE; hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc1.Init.NbrOfConversion = 1; - hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.NbrOfConversion = 5; + hadc1.Init.DMAContinuousRequests = ENABLE; hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; if (HAL_ADC_Init(&hadc1) != HAL_OK) { @@ -63,9 +64,45 @@ void MX_ADC1_Init(void) /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. */ - sConfig.Channel = ADC_CHANNEL_3; + sConfig.Channel = ADC_CHANNEL_8; sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + sConfig.SamplingTime = ADC_SAMPLETIME_144CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_7; + sConfig.Rank = ADC_REGULAR_RANK_2; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_5; + sConfig.Rank = ADC_REGULAR_RANK_3; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_6; + sConfig.Rank = ADC_REGULAR_RANK_4; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_4; + sConfig.Rank = ADC_REGULAR_RANK_5; if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) { Error_Handler(); @@ -92,16 +129,16 @@ void MX_ADC2_Init(void) /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) */ hadc2.Instance = ADC2; - hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; + hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; hadc2.Init.Resolution = ADC_RESOLUTION_12B; - hadc2.Init.ScanConvMode = ADC_SCAN_DISABLE; - hadc2.Init.ContinuousConvMode = DISABLE; + hadc2.Init.ScanConvMode = ADC_SCAN_ENABLE; + hadc2.Init.ContinuousConvMode = ENABLE; hadc2.Init.DiscontinuousConvMode = DISABLE; hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START; hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT; hadc2.Init.NbrOfConversion = 1; - hadc2.Init.DMAContinuousRequests = DISABLE; + hadc2.Init.DMAContinuousRequests = ENABLE; hadc2.Init.EOCSelection = ADC_EOC_SINGLE_CONV; if (HAL_ADC_Init(&hadc2) != HAL_OK) { @@ -110,9 +147,9 @@ void MX_ADC2_Init(void) /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. */ - sConfig.Channel = ADC_CHANNEL_13; + sConfig.Channel = ADC_CHANNEL_15; sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + sConfig.SamplingTime = ADC_SAMPLETIME_144CYCLES; if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK) { Error_Handler(); @@ -121,53 +158,6 @@ void MX_ADC2_Init(void) /* USER CODE END ADC2_Init 2 */ -} -/* ADC3 init function */ -void MX_ADC3_Init(void) -{ - - /* USER CODE BEGIN ADC3_Init 0 */ - - /* USER CODE END ADC3_Init 0 */ - - ADC_ChannelConfTypeDef sConfig = {0}; - - /* USER CODE BEGIN ADC3_Init 1 */ - - /* USER CODE END ADC3_Init 1 */ - - /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) - */ - hadc3.Instance = ADC3; - hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2; - hadc3.Init.Resolution = ADC_RESOLUTION_12B; - hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE; - hadc3.Init.ContinuousConvMode = DISABLE; - hadc3.Init.DiscontinuousConvMode = DISABLE; - hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; - hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START; - hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT; - hadc3.Init.NbrOfConversion = 1; - hadc3.Init.DMAContinuousRequests = DISABLE; - hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV; - if (HAL_ADC_Init(&hadc3) != HAL_OK) - { - Error_Handler(); - } - - /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. - */ - sConfig.Channel = ADC_CHANNEL_10; - sConfig.Rank = ADC_REGULAR_RANK_1; - sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; - if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ADC3_Init 2 */ - - /* USER CODE END ADC3_Init 2 */ - } void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) @@ -183,14 +173,53 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) __HAL_RCC_ADC1_CLK_ENABLE(); __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); /**ADC1 GPIO Configuration - PA3 ------> ADC1_IN3 + PA4 ------> ADC1_IN4 + PA5 ------> ADC1_IN5 + PA6 ------> ADC1_IN6 + PA7 ------> ADC1_IN7 + PC4 ------> ADC1_IN14 + PB0 ------> ADC1_IN8 */ + GPIO_InitStruct.Pin = DASH_ROTARY_ADC_Pin|CT_ADC_Pin|SAGL_ADC_Pin|BPS_R_ADC_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = BPS_F_ADC_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(BPS_F_ADC_GPIO_Port, &GPIO_InitStruct); + GPIO_InitStruct.Pin = APPS_1_ADC_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(APPS_1_ADC_GPIO_Port, &GPIO_InitStruct); + /* ADC1 DMA Init */ + /* ADC1 Init */ + hdma_adc1.Instance = DMA2_Stream0; + hdma_adc1.Init.Channel = DMA_CHANNEL_0; + hdma_adc1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc1.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc1.Init.Mode = DMA_CIRCULAR; + hdma_adc1.Init.Priority = DMA_PRIORITY_LOW; + hdma_adc1.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_adc1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc1); + + /* ADC1 interrupt Init */ + HAL_NVIC_SetPriority(ADC_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ADC_IRQn); /* USER CODE BEGIN ADC1_MspInit 1 */ /* USER CODE END ADC1_MspInit 1 */ @@ -203,40 +232,48 @@ void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) /* ADC2 clock enable */ __HAL_RCC_ADC2_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOC_CLK_ENABLE(); /**ADC2 GPIO Configuration - PC3 ------> ADC2_IN13 + PA3 ------> ADC2_IN3 + PC5 ------> ADC2_IN15 */ + GPIO_InitStruct.Pin = SPARE_ADC_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(SPARE_ADC_GPIO_Port, &GPIO_InitStruct); + GPIO_InitStruct.Pin = APPS_2_ADC_Pin; GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(APPS_2_ADC_GPIO_Port, &GPIO_InitStruct); + /* ADC2 DMA Init */ + /* ADC2 Init */ + hdma_adc2.Instance = DMA2_Stream2; + hdma_adc2.Init.Channel = DMA_CHANNEL_1; + hdma_adc2.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_adc2.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_adc2.Init.MemInc = DMA_MINC_ENABLE; + hdma_adc2.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_adc2.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_adc2.Init.Mode = DMA_CIRCULAR; + hdma_adc2.Init.Priority = DMA_PRIORITY_LOW; + hdma_adc2.Init.FIFOMode = DMA_FIFOMODE_DISABLE; + if (HAL_DMA_Init(&hdma_adc2) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(adcHandle,DMA_Handle,hdma_adc2); + + /* ADC2 interrupt Init */ + HAL_NVIC_SetPriority(ADC_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(ADC_IRQn); /* USER CODE BEGIN ADC2_MspInit 1 */ /* USER CODE END ADC2_MspInit 1 */ } - else if(adcHandle->Instance==ADC3) - { - /* USER CODE BEGIN ADC3_MspInit 0 */ - - /* USER CODE END ADC3_MspInit 0 */ - /* ADC3 clock enable */ - __HAL_RCC_ADC3_CLK_ENABLE(); - - __HAL_RCC_GPIOC_CLK_ENABLE(); - /**ADC3 GPIO Configuration - PC0 ------> ADC3_IN10 - */ - GPIO_InitStruct.Pin = BPS_ADC_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(BPS_ADC_GPIO_Port, &GPIO_InitStruct); - - /* USER CODE BEGIN ADC3_MspInit 1 */ - - /* USER CODE END ADC3_MspInit 1 */ - } } void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) @@ -251,10 +288,31 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) __HAL_RCC_ADC1_CLK_DISABLE(); /**ADC1 GPIO Configuration - PA3 ------> ADC1_IN3 + PA4 ------> ADC1_IN4 + PA5 ------> ADC1_IN5 + PA6 ------> ADC1_IN6 + PA7 ------> ADC1_IN7 + PC4 ------> ADC1_IN14 + PB0 ------> ADC1_IN8 */ + HAL_GPIO_DeInit(GPIOA, DASH_ROTARY_ADC_Pin|CT_ADC_Pin|SAGL_ADC_Pin|BPS_R_ADC_Pin); + + HAL_GPIO_DeInit(BPS_F_ADC_GPIO_Port, BPS_F_ADC_Pin); + HAL_GPIO_DeInit(APPS_1_ADC_GPIO_Port, APPS_1_ADC_Pin); + /* ADC1 DMA DeInit */ + HAL_DMA_DeInit(adcHandle->DMA_Handle); + + /* ADC1 interrupt Deinit */ + /* USER CODE BEGIN ADC1:ADC_IRQn disable */ + /** + * Uncomment the line below to disable the "ADC_IRQn" interrupt + * Be aware, disabling shared interrupt may affect other IPs + */ + /* HAL_NVIC_DisableIRQ(ADC_IRQn); */ + /* USER CODE END ADC1:ADC_IRQn disable */ + /* USER CODE BEGIN ADC1_MspDeInit 1 */ /* USER CODE END ADC1_MspDeInit 1 */ @@ -268,30 +326,28 @@ void HAL_ADC_MspDeInit(ADC_HandleTypeDef* adcHandle) __HAL_RCC_ADC2_CLK_DISABLE(); /**ADC2 GPIO Configuration - PC3 ------> ADC2_IN13 + PA3 ------> ADC2_IN3 + PC5 ------> ADC2_IN15 */ - HAL_GPIO_DeInit(APPS_2_ADC_GPIO_Port, APPS_2_ADC_Pin); - - /* USER CODE BEGIN ADC2_MspDeInit 1 */ + HAL_GPIO_DeInit(SPARE_ADC_GPIO_Port, SPARE_ADC_Pin); - /* USER CODE END ADC2_MspDeInit 1 */ - } - else if(adcHandle->Instance==ADC3) - { - /* USER CODE BEGIN ADC3_MspDeInit 0 */ + HAL_GPIO_DeInit(APPS_2_ADC_GPIO_Port, APPS_2_ADC_Pin); - /* USER CODE END ADC3_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ADC3_CLK_DISABLE(); + /* ADC2 DMA DeInit */ + HAL_DMA_DeInit(adcHandle->DMA_Handle); - /**ADC3 GPIO Configuration - PC0 ------> ADC3_IN10 + /* ADC2 interrupt Deinit */ + /* USER CODE BEGIN ADC2:ADC_IRQn disable */ + /** + * Uncomment the line below to disable the "ADC_IRQn" interrupt + * Be aware, disabling shared interrupt may affect other IPs */ - HAL_GPIO_DeInit(BPS_ADC_GPIO_Port, BPS_ADC_Pin); + /* HAL_NVIC_DisableIRQ(ADC_IRQn); */ + /* USER CODE END ADC2:ADC_IRQn disable */ - /* USER CODE BEGIN ADC3_MspDeInit 1 */ + /* USER CODE BEGIN ADC2_MspDeInit 1 */ - /* USER CODE END ADC3_MspDeInit 1 */ + /* USER CODE END ADC2_MspDeInit 1 */ } } diff --git a/src/Core/Src/app_threadx.c b/src/Core/Src/app_threadx.c index 8899517b..e9b6677d 100644 --- a/src/Core/Src/app_threadx.c +++ b/src/Core/Src/app_threadx.c @@ -75,7 +75,7 @@ UINT App_ThreadX_Init(VOID *memory_ptr) // initialise system if (ret == TX_SUCCESS) { - status_t status = vcu_init(&vcu, &hcan1, &hcan2, byte_pool, config_get()); + status_t status = vcu_init(&vcu, &hcan2, &hcan1, byte_pool, config_get()); if (status != STATUS_OK) { @@ -157,4 +157,9 @@ void HAL_CAN_ErrorCallback(CAN_HandleTypeDef* can_h) vcu_handle_can_err(&vcu, can_h); } +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + vcu_handle_gpio_exti(&vcu, GPIO_Pin); +} + /* USER CODE END 1 */ diff --git a/src/Core/Src/can.c b/src/Core/Src/can.c index 44aa3231..aa74cc94 100644 --- a/src/Core/Src/can.c +++ b/src/Core/Src/can.c @@ -39,15 +39,15 @@ void MX_CAN1_Init(void) /* USER CODE END CAN1_Init 1 */ hcan1.Instance = CAN1; - hcan1.Init.Prescaler = 18; + hcan1.Init.Prescaler = 3; hcan1.Init.Mode = CAN_MODE_NORMAL; - hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ; - hcan1.Init.TimeSeg1 = CAN_BS1_2TQ; - hcan1.Init.TimeSeg2 = CAN_BS2_1TQ; + hcan1.Init.SyncJumpWidth = CAN_SJW_2TQ; + hcan1.Init.TimeSeg1 = CAN_BS1_14TQ; + hcan1.Init.TimeSeg2 = CAN_BS2_3TQ; hcan1.Init.TimeTriggeredMode = DISABLE; hcan1.Init.AutoBusOff = ENABLE; hcan1.Init.AutoWakeUp = DISABLE; - hcan1.Init.AutoRetransmission = DISABLE; + hcan1.Init.AutoRetransmission = ENABLE; hcan1.Init.ReceiveFifoLocked = DISABLE; hcan1.Init.TransmitFifoPriority = DISABLE; if (HAL_CAN_Init(&hcan1) != HAL_OK) @@ -71,15 +71,15 @@ void MX_CAN2_Init(void) /* USER CODE END CAN2_Init 1 */ hcan2.Instance = CAN2; - hcan2.Init.Prescaler = 18; + hcan2.Init.Prescaler = 6; hcan2.Init.Mode = CAN_MODE_NORMAL; - hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ; - hcan2.Init.TimeSeg1 = CAN_BS1_2TQ; - hcan2.Init.TimeSeg2 = CAN_BS2_1TQ; + hcan2.Init.SyncJumpWidth = CAN_SJW_2TQ; + hcan2.Init.TimeSeg1 = CAN_BS1_14TQ; + hcan2.Init.TimeSeg2 = CAN_BS2_3TQ; hcan2.Init.TimeTriggeredMode = DISABLE; hcan2.Init.AutoBusOff = ENABLE; hcan2.Init.AutoWakeUp = DISABLE; - hcan2.Init.AutoRetransmission = DISABLE; + hcan2.Init.AutoRetransmission = ENABLE; hcan2.Init.ReceiveFifoLocked = DISABLE; hcan2.Init.TransmitFifoPriority = DISABLE; if (HAL_CAN_Init(&hcan2) != HAL_OK) @@ -108,25 +108,27 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) __HAL_RCC_CAN1_CLK_ENABLE(); } - __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); /**CAN1 GPIO Configuration - PD0 ------> CAN1_RX - PD1 ------> CAN1_TX + PB8 ------> CAN1_RX + PB9 ------> CAN1_TX */ - GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Pin = CAN_S_RX_Pin|CAN_S_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF9_CAN1; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* CAN1 interrupt Init */ - HAL_NVIC_SetPriority(CAN1_TX_IRQn, 0, 0); + HAL_NVIC_SetPriority(CAN1_TX_IRQn, 5, 0); HAL_NVIC_EnableIRQ(CAN1_TX_IRQn); - HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0); + HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 5, 0); HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn); - HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 0, 0); + HAL_NVIC_SetPriority(CAN1_RX1_IRQn, 5, 0); HAL_NVIC_EnableIRQ(CAN1_RX1_IRQn); + HAL_NVIC_SetPriority(CAN1_SCE_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN1_SCE_IRQn); /* USER CODE BEGIN CAN1_MspInit 1 */ /* USER CODE END CAN1_MspInit 1 */ @@ -145,23 +147,25 @@ void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle) __HAL_RCC_GPIOB_CLK_ENABLE(); /**CAN2 GPIO Configuration - PB12 ------> CAN2_RX + PB5 ------> CAN2_RX PB6 ------> CAN2_TX */ - GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_6; + GPIO_InitStruct.Pin = CAN_T_RX_Pin|CAN_T_TX_Pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; GPIO_InitStruct.Alternate = GPIO_AF9_CAN2; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); /* CAN2 interrupt Init */ - HAL_NVIC_SetPriority(CAN2_TX_IRQn, 0, 0); + HAL_NVIC_SetPriority(CAN2_TX_IRQn, 5, 0); HAL_NVIC_EnableIRQ(CAN2_TX_IRQn); - HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 0, 0); + HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 5, 0); HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn); - HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 0, 0); + HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 5, 0); HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn); + HAL_NVIC_SetPriority(CAN2_SCE_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(CAN2_SCE_IRQn); /* USER CODE BEGIN CAN2_MspInit 1 */ /* USER CODE END CAN2_MspInit 1 */ @@ -183,15 +187,16 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle) } /**CAN1 GPIO Configuration - PD0 ------> CAN1_RX - PD1 ------> CAN1_TX + PB8 ------> CAN1_RX + PB9 ------> CAN1_TX */ - HAL_GPIO_DeInit(GPIOD, GPIO_PIN_0|GPIO_PIN_1); + HAL_GPIO_DeInit(GPIOB, CAN_S_RX_Pin|CAN_S_TX_Pin); /* CAN1 interrupt Deinit */ HAL_NVIC_DisableIRQ(CAN1_TX_IRQn); HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn); HAL_NVIC_DisableIRQ(CAN1_RX1_IRQn); + HAL_NVIC_DisableIRQ(CAN1_SCE_IRQn); /* USER CODE BEGIN CAN1_MspDeInit 1 */ /* USER CODE END CAN1_MspDeInit 1 */ @@ -209,15 +214,16 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef* canHandle) } /**CAN2 GPIO Configuration - PB12 ------> CAN2_RX + PB5 ------> CAN2_RX PB6 ------> CAN2_TX */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_6); + HAL_GPIO_DeInit(GPIOB, CAN_T_RX_Pin|CAN_T_TX_Pin); /* CAN2 interrupt Deinit */ HAL_NVIC_DisableIRQ(CAN2_TX_IRQn); HAL_NVIC_DisableIRQ(CAN2_RX0_IRQn); HAL_NVIC_DisableIRQ(CAN2_RX1_IRQn); + HAL_NVIC_DisableIRQ(CAN2_SCE_IRQn); /* USER CODE BEGIN CAN2_MspDeInit 1 */ /* USER CODE END CAN2_MspDeInit 1 */ diff --git a/src/Core/Src/dma.c b/src/Core/Src/dma.c new file mode 100644 index 00000000..070ee2c6 --- /dev/null +++ b/src/Core/Src/dma.c @@ -0,0 +1,64 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file dma.c + * @brief This file provides code for the configuration + * of all the requested memory to memory DMA transfers. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "dma.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/*----------------------------------------------------------------------------*/ +/* Configure DMA */ +/*----------------------------------------------------------------------------*/ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + + /* DMA controller clock enable */ + __HAL_RCC_DMA2_CLK_ENABLE(); + + /* DMA interrupt init */ + /* DMA2_Stream0_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn); + /* DMA2_Stream2_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); + /* DMA2_Stream3_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 7, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); + /* DMA2_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 7, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); + +} + +/* USER CODE BEGIN 2 */ + +/* USER CODE END 2 */ + diff --git a/src/Core/Src/gpio.c b/src/Core/Src/gpio.c index b800303b..cfa8c1e9 100644 --- a/src/Core/Src/gpio.c +++ b/src/Core/Src/gpio.c @@ -7,7 +7,7 @@ ****************************************************************************** * @attention * - * Copyright (c) 2022 STMicroelectronics. + * Copyright (c) 2026 STMicroelectronics. * All rights reserved. * * This software is licensed under terms that can be found in the LICENSE file @@ -38,8 +38,6 @@ * Output * EVENT_OUT * EXTI - PB8 ------> I2C1_SCL - PB9 ------> I2C1_SDA */ void MX_GPIO_Init(void) { @@ -54,78 +52,132 @@ void MX_GPIO_Init(void) __HAL_RCC_GPIOA_CLK_ENABLE(); __HAL_RCC_GPIOB_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOE, VC_LEDS_Pin|DRS_LED_Pin|TS_ON_LED_Pin|R2D_LED_Pin - |STATUS_Pin|BRAKE_PRESSED_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOE, ROB_LED_Pin|VC_LEDS_Pin|LED_4_Pin|R2D_LED_Pin + |LED_2_Pin|TS_ON_LED_Pin|TS_ON_Pin|BRAKELIGHT_EN_Pin + |STATUS_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(DRS_GPIO_Port, DRS_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOC, RS232_FORCEOFF_Pin|RS232_FORCEON_Pin|IMU_MODE_Pin|EEPROM_WC_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOB, GREEN_LED_Pin|RED_LED_Pin|BLUE_LED_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOF, R2D_SIREN_Pin|IMU_ADDR_Pin|LS_LED_6_Pin, GPIO_PIN_RESET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOF, TS_ON_Pin|R2D_SIREN_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOB, SPARE_OUT_7_Pin|SPARE_OUT_6_Pin|SPARE_OUT_5_Pin|SPARE_OUT_4_Pin, GPIO_PIN_RESET); - /*Configure GPIO pins : PEPin PEPin PEPin PEPin - PEPin PEPin */ - GPIO_InitStruct.Pin = VC_LEDS_Pin|DRS_LED_Pin|TS_ON_LED_Pin|R2D_LED_Pin - |STATUS_Pin|BRAKE_PRESSED_Pin; + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOD, SPARE_OUT_3_Pin|DEBUG_GPIO_1_Pin|DEBUG_GPIO_2_Pin|DEBUG_GPIO_3_Pin + |DEBUG_GPIO_4_Pin|DEBUG_GPIO_5_Pin|DEBUG_GPIO_6_Pin|DEBUG_GPIO_7_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOG, DEBUG_GPIO_8_Pin|DEBUG_GPIO_9_Pin|DEBUG_GPIO_10_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pins : ROB_LED_Pin VC_LEDS_Pin LED_4_Pin R2D_LED_Pin + LED_2_Pin TS_ON_LED_Pin TS_ON_Pin BRAKELIGHT_EN_Pin + STATUS_Pin */ + GPIO_InitStruct.Pin = ROB_LED_Pin|VC_LEDS_Pin|LED_4_Pin|R2D_LED_Pin + |LED_2_Pin|TS_ON_LED_Pin|TS_ON_Pin|BRAKELIGHT_EN_Pin + |STATUS_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = USER_BUTTON_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pin : SD_CARD_DETECT_Pin */ + GPIO_InitStruct.Pin = SD_CARD_DETECT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(SD_CARD_DETECT_GPIO_Port, &GPIO_InitStruct); - /*Configure GPIO pins : PFPin PFPin PFPin PFPin */ - GPIO_InitStruct.Pin = TS_READY_Pin|R2D_BTN_Pin|TS_ON_BTN_Pin|DRS_BTN_Pin; + /*Configure GPIO pin : RS232_BAD_Pin */ + GPIO_InitStruct.Pin = RS232_BAD_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLDOWN; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(RS232_BAD_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : RS232_FORCEOFF_Pin RS232_FORCEON_Pin IMU_MODE_Pin EEPROM_WC_Pin */ + GPIO_InitStruct.Pin = RS232_FORCEOFF_Pin|RS232_FORCEON_Pin|IMU_MODE_Pin|EEPROM_WC_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = SAGL_Pin; + /*Configure GPIO pin : TOO_HOT_Pin */ + GPIO_InitStruct.Pin = TOO_HOT_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(SAGL_GPIO_Port, &GPIO_InitStruct); + HAL_GPIO_Init(TOO_HOT_GPIO_Port, &GPIO_InitStruct); - /*Configure GPIO pin : PtPin */ - GPIO_InitStruct.Pin = DRS_Pin; + /*Configure GPIO pins : R2D_SIREN_Pin IMU_ADDR_Pin LS_LED_6_Pin */ + GPIO_InitStruct.Pin = R2D_SIREN_Pin|IMU_ADDR_Pin|LS_LED_6_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(DRS_GPIO_Port, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - /*Configure GPIO pins : PBPin PBPin PBPin */ - GPIO_InitStruct.Pin = GREEN_LED_Pin|RED_LED_Pin|BLUE_LED_Pin; + /*Configure GPIO pins : SPARE_OUT_7_Pin SPARE_OUT_6_Pin SPARE_OUT_5_Pin SPARE_OUT_4_Pin */ + GPIO_InitStruct.Pin = SPARE_OUT_7_Pin|SPARE_OUT_6_Pin|SPARE_OUT_5_Pin|SPARE_OUT_4_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - /*Configure GPIO pins : PFPin PFPin */ - GPIO_InitStruct.Pin = TS_ON_Pin|R2D_SIREN_Pin; + /*Configure GPIO pins : WHEELSPEED_RR_Pin WHEELSPEED_RL_Pin WHEELSPEED_FR_Pin WHEELSPEED_FL_Pin */ + GPIO_InitStruct.Pin = WHEELSPEED_RR_Pin|WHEELSPEED_RL_Pin|WHEELSPEED_FR_Pin|WHEELSPEED_FL_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : SPARE_IN_3_Pin GPS_PPS_Pin SPARE_IN_2_Pin */ + GPIO_InitStruct.Pin = SPARE_IN_3_Pin|GPS_PPS_Pin|SPARE_IN_2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : SPARE_OUT_3_Pin DEBUG_GPIO_1_Pin DEBUG_GPIO_2_Pin DEBUG_GPIO_3_Pin + DEBUG_GPIO_4_Pin DEBUG_GPIO_5_Pin DEBUG_GPIO_6_Pin DEBUG_GPIO_7_Pin */ + GPIO_InitStruct.Pin = SPARE_OUT_3_Pin|DEBUG_GPIO_1_Pin|DEBUG_GPIO_2_Pin|DEBUG_GPIO_3_Pin + |DEBUG_GPIO_4_Pin|DEBUG_GPIO_5_Pin|DEBUG_GPIO_6_Pin|DEBUG_GPIO_7_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /*Configure GPIO pins : SPARE_OUT_2_Pin SPARE_OUT_1_Pin APPS_PWR_GOOD_Pin SPARE_IN_1_Pin + SW_BTN_2_Pin SW_BTN_1_Pin R2D_BTN_Pin */ + GPIO_InitStruct.Pin = SPARE_OUT_2_Pin|SPARE_OUT_1_Pin|APPS_PWR_GOOD_Pin|SPARE_IN_1_Pin + |SW_BTN_2_Pin|SW_BTN_1_Pin|R2D_BTN_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - /*Configure GPIO pins : PB8 PB9 */ - GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + /*Configure GPIO pins : TS_ON_BTN_Pin TS_READY_Pin */ + GPIO_InitStruct.Pin = TS_ON_BTN_Pin|TS_READY_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + /*Configure GPIO pins : DEBUG_GPIO_8_Pin DEBUG_GPIO_9_Pin DEBUG_GPIO_10_Pin */ + GPIO_InitStruct.Pin = DEBUG_GPIO_8_Pin|DEBUG_GPIO_9_Pin|DEBUG_GPIO_10_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /*Configure GPIO pin : USER_BUTTON_Pin */ + GPIO_InitStruct.Pin = USER_BUTTON_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(USER_BUTTON_GPIO_Port, &GPIO_InitStruct); /* EXTI interrupt init*/ - HAL_NVIC_SetPriority(EXTI15_10_IRQn, 0, 0); + HAL_NVIC_SetPriority(EXTI9_5_IRQn, 6, 0); + HAL_NVIC_EnableIRQ(EXTI9_5_IRQn); + + HAL_NVIC_SetPriority(EXTI15_10_IRQn, 6, 0); HAL_NVIC_EnableIRQ(EXTI15_10_IRQn); } diff --git a/src/Core/Src/i2c.c b/src/Core/Src/i2c.c new file mode 100644 index 00000000..a2d76d1e --- /dev/null +++ b/src/Core/Src/i2c.c @@ -0,0 +1,237 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file i2c.c + * @brief This file provides code for the configuration + * of the I2C instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "i2c.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +I2C_HandleTypeDef hi2c2; +I2C_HandleTypeDef hi2c4; + +/* I2C2 init function */ +void MX_I2C2_Init(void) +{ + + /* USER CODE BEGIN I2C2_Init 0 */ + + /* USER CODE END I2C2_Init 0 */ + + /* USER CODE BEGIN I2C2_Init 1 */ + + /* USER CODE END I2C2_Init 1 */ + hi2c2.Instance = I2C2; + hi2c2.Init.Timing = 0x20404768; + hi2c2.Init.OwnAddress1 = 0; + hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c2.Init.OwnAddress2 = 0; + hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c2) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C2_Init 2 */ + + /* USER CODE END I2C2_Init 2 */ + +} +/* I2C4 init function */ +void MX_I2C4_Init(void) +{ + + /* USER CODE BEGIN I2C4_Init 0 */ + + /* USER CODE END I2C4_Init 0 */ + + /* USER CODE BEGIN I2C4_Init 1 */ + + /* USER CODE END I2C4_Init 1 */ + hi2c4.Instance = I2C4; + hi2c4.Init.Timing = 0x20404768; + hi2c4.Init.OwnAddress1 = 0; + hi2c4.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hi2c4.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hi2c4.Init.OwnAddress2 = 0; + hi2c4.Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hi2c4.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hi2c4.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + if (HAL_I2C_Init(&hi2c4) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Analogue filter + */ + if (HAL_I2CEx_ConfigAnalogFilter(&hi2c4, I2C_ANALOGFILTER_ENABLE) != HAL_OK) + { + Error_Handler(); + } + + /** Configure Digital filter + */ + if (HAL_I2CEx_ConfigDigitalFilter(&hi2c4, 0) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN I2C4_Init 2 */ + + /* USER CODE END I2C4_Init 2 */ + +} + +void HAL_I2C_MspInit(I2C_HandleTypeDef* i2cHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(i2cHandle->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspInit 0 */ + + /* USER CODE END I2C2_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C2; + PeriphClkInitStruct.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**I2C2 GPIO Configuration + PF0 ------> I2C2_SDA + PF1 ------> I2C2_SCL + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* I2C2 clock enable */ + __HAL_RCC_I2C2_CLK_ENABLE(); + /* USER CODE BEGIN I2C2_MspInit 1 */ + + /* USER CODE END I2C2_MspInit 1 */ + } + else if(i2cHandle->Instance==I2C4) + { + /* USER CODE BEGIN I2C4_MspInit 0 */ + + /* USER CODE END I2C4_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_I2C4; + PeriphClkInitStruct.I2c4ClockSelection = RCC_I2C4CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**I2C4 GPIO Configuration + PF14 ------> I2C4_SCL + PF15 ------> I2C4_SDA + */ + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF4_I2C4; + HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); + + /* I2C4 clock enable */ + __HAL_RCC_I2C4_CLK_ENABLE(); + /* USER CODE BEGIN I2C4_MspInit 1 */ + + /* USER CODE END I2C4_MspInit 1 */ + } +} + +void HAL_I2C_MspDeInit(I2C_HandleTypeDef* i2cHandle) +{ + + if(i2cHandle->Instance==I2C2) + { + /* USER CODE BEGIN I2C2_MspDeInit 0 */ + + /* USER CODE END I2C2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C2_CLK_DISABLE(); + + /**I2C2 GPIO Configuration + PF0 ------> I2C2_SDA + PF1 ------> I2C2_SCL + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_1); + + /* USER CODE BEGIN I2C2_MspDeInit 1 */ + + /* USER CODE END I2C2_MspDeInit 1 */ + } + else if(i2cHandle->Instance==I2C4) + { + /* USER CODE BEGIN I2C4_MspDeInit 0 */ + + /* USER CODE END I2C4_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_I2C4_CLK_DISABLE(); + + /**I2C4 GPIO Configuration + PF14 ------> I2C4_SCL + PF15 ------> I2C4_SDA + */ + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_14); + + HAL_GPIO_DeInit(GPIOF, GPIO_PIN_15); + + /* USER CODE BEGIN I2C4_MspDeInit 1 */ + + /* USER CODE END I2C4_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/Core/Src/main.c b/src/Core/Src/main.c index 7e7c39d8..7d60d4dc 100644 --- a/src/Core/Src/main.c +++ b/src/Core/Src/main.c @@ -21,12 +21,17 @@ #include "main.h" #include "adc.h" #include "can.h" +#include "dma.h" +#include "i2c.h" +#include "spi.h" +#include "tim.h" #include "usart.h" #include "gpio.h" /* Private includes ----------------------------------------------------------*/ /* USER CODE BEGIN Includes */ - +#include "io.h" +#include "adc_scan.h" /* USER CODE END Includes */ /* Private typedef -----------------------------------------------------------*/ @@ -51,6 +56,7 @@ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); +static void MPU_Config(void); /* USER CODE BEGIN PFP */ /* USER CODE END PFP */ @@ -66,10 +72,14 @@ void SystemClock_Config(void); */ int main(void) { + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ + /* MPU Configuration--------------------------------------------------------*/ + MPU_Config(); + /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ @@ -77,11 +87,11 @@ int main(void) /* USER CODE BEGIN Init */ #ifdef DEBUG - // for some reason on STM32F7, when debugging with an interrupt on TIM3 - // the debugger creates a breakpoint in the interrupt handler. This means - // the processor stops every single TIM3 interrupt. - // this is a fix for that - __HAL_DBGMCU_FREEZE_TIM3(); + // on an STM32F7, when debugging with TIM6 running the HAL timebase + // the hardware timer keeps running (and overflowing) if the CPU is paused + // this is a fix for that by coupling TIM6 to gate the timer's clock when + // the CPU is halted + __HAL_DBGMCU_FREEZE_TIM6(); __HAL_DBGMCU_FREEZE_CAN2(); __HAL_DBGMCU_FREEZE_CAN1(); #endif @@ -91,30 +101,46 @@ int main(void) SystemClock_Config(); /* USER CODE BEGIN SysInit */ - + // wait 100ms before initialising peripherals + HAL_Delay(100); /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); - MX_ADC3_Init(); + MX_DMA_Init(); MX_ADC1_Init(); - MX_ADC2_Init(); MX_CAN1_Init(); MX_CAN2_Init(); - MX_USART1_UART_Init(); + MX_I2C2_Init(); + MX_I2C4_Init(); + MX_SPI6_Init(); + MX_TIM2_Init(); + MX_TIM12_Init(); + MX_UART8_Init(); + MX_USART1_Init(); + MX_TIM10_Init(); + MX_TIM11_Init(); + MX_ADC2_Init(); + MX_TIM3_Init(); /* USER CODE BEGIN 2 */ + if (adc_scan_init() != STATUS_OK) + { + Error_Handler(); + } + /* USER CODE END 2 */ MX_ThreadX_Init(); /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { - HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_7); - HAL_Delay(1000); + VCU_Output_Toggle(ROB_LED_GPIO_Port, ROB_LED_Pin); + HAL_Delay(200); /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ @@ -134,7 +160,7 @@ void SystemClock_Config(void) /** Configure the main internal regulator output voltage */ __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. @@ -143,25 +169,32 @@ void SystemClock_Config(void) RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = 4; - RCC_OscInitStruct.PLL.PLLN = 72; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 432; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; - RCC_OscInitStruct.PLL.PLLQ = 3; + RCC_OscInitStruct.PLL.PLLQ = 9; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } + /** Activate the Over-Drive mode + */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) { Error_Handler(); } @@ -171,9 +204,38 @@ void SystemClock_Config(void) /* USER CODE END 4 */ + /* MPU Configuration */ + +void MPU_Config(void) +{ + MPU_Region_InitTypeDef MPU_InitStruct = {0}; + + /* Disables the MPU */ + HAL_MPU_Disable(); + + /** Initializes and configures the Region and the memory to be protected + */ + MPU_InitStruct.Enable = MPU_REGION_ENABLE; + MPU_InitStruct.Number = MPU_REGION_NUMBER0; + MPU_InitStruct.BaseAddress = 0x0; + MPU_InitStruct.Size = MPU_REGION_SIZE_4GB; + MPU_InitStruct.SubRegionDisable = 0x87; + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; + MPU_InitStruct.AccessPermission = MPU_REGION_NO_ACCESS; + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; + MPU_InitStruct.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + + HAL_MPU_ConfigRegion(&MPU_InitStruct); + /* Enables the MPU */ + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); + +} + /** * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM3 interrupt took place, inside + * @note This function is called when TIM6 interrupt took place, inside * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment * a global variable "uwTick" used as application time base. * @param htim : TIM handle @@ -184,7 +246,8 @@ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) /* USER CODE BEGIN Callback 0 */ /* USER CODE END Callback 0 */ - if (htim->Instance == TIM3) { + if (htim->Instance == TIM6) + { HAL_IncTick(); } /* USER CODE BEGIN Callback 1 */ @@ -203,12 +266,13 @@ void Error_Handler(void) __disable_irq(); while (1) { - HAL_GPIO_WritePin(RED_LED_GPIO_Port, RED_LED_Pin, GPIO_PIN_SET); + VCU_Output_Toggle(ROB_LED_GPIO_Port, ROB_LED_Pin); + HAL_Delay(100); + } /* USER CODE END Error_Handler_Debug */ } - -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT /** * @brief Reports the name of the source file and the source line number * where the assert_param error has occurred. diff --git a/src/Core/Src/sdmmc.c b/src/Core/Src/sdmmc.c new file mode 100644 index 00000000..0d3b7c9b --- /dev/null +++ b/src/Core/Src/sdmmc.c @@ -0,0 +1,209 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file sdmmc.c + * @brief This file provides code for the configuration + * of the SDMMC instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "sdmmc.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +SD_HandleTypeDef hsd1; +DMA_HandleTypeDef hdma_sdmmc1_rx; +DMA_HandleTypeDef hdma_sdmmc1_tx; + +/* SDMMC1 init function */ + +void MX_SDMMC1_SD_Init(void) +{ + + /* USER CODE BEGIN SDMMC1_Init 0 */ + + /* USER CODE END SDMMC1_Init 0 */ + + /* USER CODE BEGIN SDMMC1_Init 1 */ + + /* USER CODE END SDMMC1_Init 1 */ + hsd1.Instance = SDMMC1; + hsd1.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + hsd1.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + hsd1.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_ENABLE; + hsd1.Init.BusWide = SDMMC_BUS_WIDE_1B; + hsd1.Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + hsd1.Init.ClockDiv = 0; + if (HAL_SD_Init(&hsd1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_SD_ConfigWideBusOperation(&hsd1, SDMMC_BUS_WIDE_4B) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SDMMC1_Init 2 */ + + /* USER CODE END SDMMC1_Init 2 */ + +} + +void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(sdHandle->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspInit 0 */ + + /* USER CODE END SDMMC1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SDMMC1|RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_CLK48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* SDMMC1 clock enable */ + __HAL_RCC_SDMMC1_CLK_ENABLE(); + + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); + /**SDMMC1 GPIO Configuration + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PD2 ------> SDMMC1_CMD + */ + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = GPIO_PIN_2; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF12_SDMMC1; + HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + + /* SDMMC1 DMA Init */ + /* SDMMC1_RX Init */ + hdma_sdmmc1_rx.Instance = DMA2_Stream3; + hdma_sdmmc1_rx.Init.Channel = DMA_CHANNEL_4; + hdma_sdmmc1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_sdmmc1_rx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sdmmc1_rx.Init.MemInc = DMA_MINC_ENABLE; + hdma_sdmmc1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_sdmmc1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_sdmmc1_rx.Init.Mode = DMA_PFCTRL; + hdma_sdmmc1_rx.Init.Priority = DMA_PRIORITY_LOW; + hdma_sdmmc1_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_sdmmc1_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_sdmmc1_rx.Init.MemBurst = DMA_MBURST_INC4; + hdma_sdmmc1_rx.Init.PeriphBurst = DMA_PBURST_INC4; + if (HAL_DMA_Init(&hdma_sdmmc1_rx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(sdHandle,hdmarx,hdma_sdmmc1_rx); + + /* SDMMC1_TX Init */ + hdma_sdmmc1_tx.Instance = DMA2_Stream6; + hdma_sdmmc1_tx.Init.Channel = DMA_CHANNEL_4; + hdma_sdmmc1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_sdmmc1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_sdmmc1_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_sdmmc1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_sdmmc1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_sdmmc1_tx.Init.Mode = DMA_PFCTRL; + hdma_sdmmc1_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_sdmmc1_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_sdmmc1_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_sdmmc1_tx.Init.MemBurst = DMA_MBURST_INC4; + hdma_sdmmc1_tx.Init.PeriphBurst = DMA_PBURST_INC4; + if (HAL_DMA_Init(&hdma_sdmmc1_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(sdHandle,hdmatx,hdma_sdmmc1_tx); + + /* SDMMC1 interrupt Init */ + HAL_NVIC_SetPriority(SDMMC1_IRQn, 7, 0); + HAL_NVIC_EnableIRQ(SDMMC1_IRQn); + /* USER CODE BEGIN SDMMC1_MspInit 1 */ + + /* USER CODE END SDMMC1_MspInit 1 */ + } +} + +void HAL_SD_MspDeInit(SD_HandleTypeDef* sdHandle) +{ + + if(sdHandle->Instance==SDMMC1) + { + /* USER CODE BEGIN SDMMC1_MspDeInit 0 */ + + /* USER CODE END SDMMC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SDMMC1_CLK_DISABLE(); + + /**SDMMC1 GPIO Configuration + PC8 ------> SDMMC1_D0 + PC9 ------> SDMMC1_D1 + PC10 ------> SDMMC1_D2 + PC11 ------> SDMMC1_D3 + PC12 ------> SDMMC1_CK + PD2 ------> SDMMC1_CMD + */ + HAL_GPIO_DeInit(GPIOC, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 + |GPIO_PIN_12); + + HAL_GPIO_DeInit(GPIOD, GPIO_PIN_2); + + /* SDMMC1 DMA DeInit */ + HAL_DMA_DeInit(sdHandle->hdmarx); + HAL_DMA_DeInit(sdHandle->hdmatx); + + /* SDMMC1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(SDMMC1_IRQn); + /* USER CODE BEGIN SDMMC1_MspDeInit 1 */ + + /* USER CODE END SDMMC1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/Core/Src/spi.c b/src/Core/Src/spi.c new file mode 100644 index 00000000..6ec45bf0 --- /dev/null +++ b/src/Core/Src/spi.c @@ -0,0 +1,121 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file spi.c + * @brief This file provides code for the configuration + * of the SPI instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "spi.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +SPI_HandleTypeDef hspi6; + +/* SPI6 init function */ +void MX_SPI6_Init(void) +{ + + /* USER CODE BEGIN SPI6_Init 0 */ + + /* USER CODE END SPI6_Init 0 */ + + /* USER CODE BEGIN SPI6_Init 1 */ + + /* USER CODE END SPI6_Init 1 */ + hspi6.Instance = SPI6; + hspi6.Init.Mode = SPI_MODE_MASTER; + hspi6.Init.Direction = SPI_DIRECTION_2LINES; + hspi6.Init.DataSize = SPI_DATASIZE_4BIT; + hspi6.Init.CLKPolarity = SPI_POLARITY_LOW; + hspi6.Init.CLKPhase = SPI_PHASE_1EDGE; + hspi6.Init.NSS = SPI_NSS_SOFT; + hspi6.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + hspi6.Init.FirstBit = SPI_FIRSTBIT_MSB; + hspi6.Init.TIMode = SPI_TIMODE_DISABLE; + hspi6.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + hspi6.Init.CRCPolynomial = 7; + hspi6.Init.CRCLength = SPI_CRC_LENGTH_DATASIZE; + hspi6.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; + if (HAL_SPI_Init(&hspi6) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN SPI6_Init 2 */ + + /* USER CODE END SPI6_Init 2 */ + +} + +void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(spiHandle->Instance==SPI6) + { + /* USER CODE BEGIN SPI6_MspInit 0 */ + + /* USER CODE END SPI6_MspInit 0 */ + /* SPI6 clock enable */ + __HAL_RCC_SPI6_CLK_ENABLE(); + + __HAL_RCC_GPIOG_CLK_ENABLE(); + /**SPI6 GPIO Configuration + PG12 ------> SPI6_MISO + PG13 ------> SPI6_SCK + PG14 ------> SPI6_MOSI + */ + GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF5_SPI6; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + /* USER CODE BEGIN SPI6_MspInit 1 */ + + /* USER CODE END SPI6_MspInit 1 */ + } +} + +void HAL_SPI_MspDeInit(SPI_HandleTypeDef* spiHandle) +{ + + if(spiHandle->Instance==SPI6) + { + /* USER CODE BEGIN SPI6_MspDeInit 0 */ + + /* USER CODE END SPI6_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_SPI6_CLK_DISABLE(); + + /**SPI6 GPIO Configuration + PG12 ------> SPI6_MISO + PG13 ------> SPI6_SCK + PG14 ------> SPI6_MOSI + */ + HAL_GPIO_DeInit(GPIOG, GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14); + + /* USER CODE BEGIN SPI6_MspDeInit 1 */ + + /* USER CODE END SPI6_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/Core/Src/stm32f7xx_hal_msp.c b/src/Core/Src/stm32f7xx_hal_msp.c index 192e3394..dec41f77 100644 --- a/src/Core/Src/stm32f7xx_hal_msp.c +++ b/src/Core/Src/stm32f7xx_hal_msp.c @@ -20,7 +20,6 @@ /* Includes ------------------------------------------------------------------*/ #include "main.h" - /* USER CODE BEGIN Includes */ /* USER CODE END Includes */ @@ -63,6 +62,7 @@ */ void HAL_MspInit(void) { + /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ diff --git a/src/Core/Src/stm32f7xx_hal_timebase_tim.c b/src/Core/Src/stm32f7xx_hal_timebase_tim.c index 02a91422..255d7010 100644 --- a/src/Core/Src/stm32f7xx_hal_timebase_tim.c +++ b/src/Core/Src/stm32f7xx_hal_timebase_tim.c @@ -25,12 +25,12 @@ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim6; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** - * @brief This function configures the TIM3 as a time base source. + * @brief This function configures the TIM6 as a time base source. * The time source is configured to have 1ms time base with a dedicated * Tick interrupt priority. * @note This function is called automatically at the beginning of program after @@ -45,17 +45,18 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uint32_t uwPrescalerValue = 0U; uint32_t pFLatency; + HAL_StatusTypeDef status; - /* Enable TIM3 clock */ - __HAL_RCC_TIM3_CLK_ENABLE(); + /* Enable TIM6 clock */ + __HAL_RCC_TIM6_CLK_ENABLE(); /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); /* Get APB1 prescaler */ uwAPB1Prescaler = clkconfig.APB1CLKDivider; - /* Compute TIM3 clock */ + /* Compute TIM6 clock */ if (uwAPB1Prescaler == RCC_HCLK_DIV1) { uwTimclock = HAL_RCC_GetPCLK1Freq(); @@ -65,39 +66,38 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq(); } - /* Compute the prescaler value to have TIM3 counter clock equal to 1MHz */ + /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); - /* Initialize TIM3 */ - htim3.Instance = TIM3; + /* Initialize TIM6 */ + htim6.Instance = TIM6; /* Initialize TIMx peripheral as follow: - - + Period = [(TIM3CLK/1000) - 1]. to have a (1/1000) s time base. - + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. - + ClockDivision = 0 - + Counter direction = Up - */ - htim3.Init.Period = (1000000U / 1000U) - 1U; - htim3.Init.Prescaler = uwPrescalerValue; - htim3.Init.ClockDivision = 0; - htim3.Init.CounterMode = TIM_COUNTERMODE_UP; - htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - - status = HAL_TIM_Base_Init(&htim3); + * Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. + * Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + * ClockDivision = 0 + * Counter direction = Up + */ + htim6.Init.Period = (1000000U / 1000U) - 1U; + htim6.Init.Prescaler = uwPrescalerValue; + htim6.Init.ClockDivision = 0; + htim6.Init.CounterMode = TIM_COUNTERMODE_UP; + htim6.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + + status = HAL_TIM_Base_Init(&htim6); if (status == HAL_OK) { /* Start the TIM time Base generation in interrupt mode */ - status = HAL_TIM_Base_Start_IT(&htim3); + status = HAL_TIM_Base_Start_IT(&htim6); if (status == HAL_OK) { - /* Enable the TIM3 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM3_IRQn); + /* Enable the TIM6 global Interrupt */ + HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) { /* Configure the TIM IRQ priority */ - HAL_NVIC_SetPriority(TIM3_IRQn, TickPriority, 0U); + HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0U); uwTickPrio = TickPriority; } else @@ -113,25 +113,25 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) /** * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling TIM3 update interrupt. + * @note Disable the tick increment by disabling TIM6 update interrupt. * @param None * @retval None */ void HAL_SuspendTick(void) { - /* Disable TIM3 update Interrupt */ - __HAL_TIM_DISABLE_IT(&htim3, TIM_IT_UPDATE); + /* Disable TIM6 update Interrupt */ + __HAL_TIM_DISABLE_IT(&htim6, TIM_IT_UPDATE); } /** * @brief Resume Tick increment. - * @note Enable the tick increment by Enabling TIM3 update interrupt. + * @note Enable the tick increment by Enabling TIM6 update interrupt. * @param None * @retval None */ void HAL_ResumeTick(void) { - /* Enable TIM3 Update interrupt */ - __HAL_TIM_ENABLE_IT(&htim3, TIM_IT_UPDATE); + /* Enable TIM6 Update interrupt */ + __HAL_TIM_ENABLE_IT(&htim6, TIM_IT_UPDATE); } diff --git a/src/Core/Src/stm32f7xx_it.c b/src/Core/Src/stm32f7xx_it.c index 0cf914fc..f0d47462 100644 --- a/src/Core/Src/stm32f7xx_it.c +++ b/src/Core/Src/stm32f7xx_it.c @@ -55,9 +55,17 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ +extern DMA_HandleTypeDef hdma_adc1; +extern DMA_HandleTypeDef hdma_adc2; +extern ADC_HandleTypeDef hadc1; +extern ADC_HandleTypeDef hadc2; extern CAN_HandleTypeDef hcan1; extern CAN_HandleTypeDef hcan2; -extern TIM_HandleTypeDef htim3; +extern DMA_HandleTypeDef hdma_sdmmc1_rx; +extern DMA_HandleTypeDef hdma_sdmmc1_tx; +extern SD_HandleTypeDef hsd1; +extern PCD_HandleTypeDef hpcd_USB_OTG_FS; +extern TIM_HandleTypeDef htim6; /* USER CODE BEGIN EV */ @@ -162,6 +170,21 @@ void DebugMon_Handler(void) /* please refer to the startup file (startup_stm32f7xx.s). */ /******************************************************************************/ +/** + * @brief This function handles ADC1, ADC2 and ADC3 global interrupts. + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN ADC_IRQn 0 */ + + /* USER CODE END ADC_IRQn 0 */ + HAL_ADC_IRQHandler(&hadc1); + HAL_ADC_IRQHandler(&hadc2); + /* USER CODE BEGIN ADC_IRQn 1 */ + + /* USER CODE END ADC_IRQn 1 */ +} + /** * @brief This function handles CAN1 TX interrupts. */ @@ -205,17 +228,32 @@ void CAN1_RX1_IRQHandler(void) } /** - * @brief This function handles TIM3 global interrupt. + * @brief This function handles CAN1 SCE interrupt. + */ +void CAN1_SCE_IRQHandler(void) +{ + /* USER CODE BEGIN CAN1_SCE_IRQn 0 */ + + /* USER CODE END CAN1_SCE_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan1); + /* USER CODE BEGIN CAN1_SCE_IRQn 1 */ + + /* USER CODE END CAN1_SCE_IRQn 1 */ +} + +/** + * @brief This function handles EXTI line[9:5] interrupts. */ -void TIM3_IRQHandler(void) +void EXTI9_5_IRQHandler(void) { - /* USER CODE BEGIN TIM3_IRQn 0 */ + /* USER CODE BEGIN EXTI9_5_IRQn 0 */ - /* USER CODE END TIM3_IRQn 0 */ - HAL_TIM_IRQHandler(&htim3); - /* USER CODE BEGIN TIM3_IRQn 1 */ + /* USER CODE END EXTI9_5_IRQn 0 */ + HAL_GPIO_EXTI_IRQHandler(WHEELSPEED_RR_Pin); + HAL_GPIO_EXTI_IRQHandler(WHEELSPEED_RL_Pin); + /* USER CODE BEGIN EXTI9_5_IRQn 1 */ - /* USER CODE END TIM3_IRQn 1 */ + /* USER CODE END EXTI9_5_IRQn 1 */ } /** @@ -226,12 +264,83 @@ void EXTI15_10_IRQHandler(void) /* USER CODE BEGIN EXTI15_10_IRQn 0 */ /* USER CODE END EXTI15_10_IRQn 0 */ - HAL_GPIO_EXTI_IRQHandler(USER_BUTTON_Pin); + HAL_GPIO_EXTI_IRQHandler(WHEELSPEED_FR_Pin); + HAL_GPIO_EXTI_IRQHandler(WHEELSPEED_FL_Pin); /* USER CODE BEGIN EXTI15_10_IRQn 1 */ /* USER CODE END EXTI15_10_IRQn 1 */ } +/** + * @brief This function handles SDMMC1 global interrupt. + */ +void SDMMC1_IRQHandler(void) +{ + /* USER CODE BEGIN SDMMC1_IRQn 0 */ + + /* USER CODE END SDMMC1_IRQn 0 */ + HAL_SD_IRQHandler(&hsd1); + /* USER CODE BEGIN SDMMC1_IRQn 1 */ + + /* USER CODE END SDMMC1_IRQn 1 */ +} + +/** + * @brief This function handles TIM6 global interrupt, DAC1 and DAC2 underrun error interrupts. + */ +void TIM6_DAC_IRQHandler(void) +{ + /* USER CODE BEGIN TIM6_DAC_IRQn 0 */ + + /* USER CODE END TIM6_DAC_IRQn 0 */ + HAL_TIM_IRQHandler(&htim6); + /* USER CODE BEGIN TIM6_DAC_IRQn 1 */ + + /* USER CODE END TIM6_DAC_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream0 global interrupt. + */ +void DMA2_Stream0_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */ + + /* USER CODE END DMA2_Stream0_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc1); + /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */ + + /* USER CODE END DMA2_Stream0_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream2 global interrupt. + */ +void DMA2_Stream2_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream2_IRQn 0 */ + + /* USER CODE END DMA2_Stream2_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_adc2); + /* USER CODE BEGIN DMA2_Stream2_IRQn 1 */ + + /* USER CODE END DMA2_Stream2_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream3 global interrupt. + */ +void DMA2_Stream3_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream3_IRQn 0 */ + + /* USER CODE END DMA2_Stream3_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_sdmmc1_rx); + /* USER CODE BEGIN DMA2_Stream3_IRQn 1 */ + + /* USER CODE END DMA2_Stream3_IRQn 1 */ +} + /** * @brief This function handles CAN2 TX interrupts. */ @@ -274,6 +383,48 @@ void CAN2_RX1_IRQHandler(void) /* USER CODE END CAN2_RX1_IRQn 1 */ } +/** + * @brief This function handles CAN2 SCE interrupt. + */ +void CAN2_SCE_IRQHandler(void) +{ + /* USER CODE BEGIN CAN2_SCE_IRQn 0 */ + + /* USER CODE END CAN2_SCE_IRQn 0 */ + HAL_CAN_IRQHandler(&hcan2); + /* USER CODE BEGIN CAN2_SCE_IRQn 1 */ + + /* USER CODE END CAN2_SCE_IRQn 1 */ +} + +/** + * @brief This function handles USB On The Go FS global interrupt. + */ +void OTG_FS_IRQHandler(void) +{ + /* USER CODE BEGIN OTG_FS_IRQn 0 */ + + /* USER CODE END OTG_FS_IRQn 0 */ + HAL_PCD_IRQHandler(&hpcd_USB_OTG_FS); + /* USER CODE BEGIN OTG_FS_IRQn 1 */ + + /* USER CODE END OTG_FS_IRQn 1 */ +} + +/** + * @brief This function handles DMA2 stream6 global interrupt. + */ +void DMA2_Stream6_IRQHandler(void) +{ + /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */ + + /* USER CODE END DMA2_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_sdmmc1_tx); + /* USER CODE BEGIN DMA2_Stream6_IRQn 1 */ + + /* USER CODE END DMA2_Stream6_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/src/Core/Src/syscalls.c b/src/Core/Src/syscalls.c new file mode 100644 index 00000000..e10d76fa --- /dev/null +++ b/src/Core/Src/syscalls.c @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file syscalls.c + * @author Auto-generated by STM32CubeMX + * @brief Minimal System calls file + * + * For more information about which c-functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc-manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2020-2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include +#include +#include +#include +#include +#include + + +/* Variables */ +extern int __io_putchar(int ch) __attribute__((weak)); +extern int __io_getchar(void) __attribute__((weak)); + + +char *__env[1] = { 0 }; +char **environ = __env; + + +/* Functions */ +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + return 1; +} + +int _kill(int pid, int sig) +{ + (void)pid; + (void)sig; + errno = EINVAL; + return -1; +} + +void _exit (int status) +{ + _kill(status, -1); + while (1) {} /* Make sure we hang here */ +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + + return len; +} + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} + +int _close(int file) +{ + (void)file; + return -1; +} + + +int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _isatty(int file) +{ + (void)file; + return 1; +} + +int _lseek(int file, int ptr, int dir) +{ + (void)file; + (void)ptr; + (void)dir; + return 0; +} + +int _open(char *path, int flags, ...) +{ + (void)path; + (void)flags; + /* Pretend like we always fail */ + return -1; +} + +int _wait(int *status) +{ + (void)status; + errno = ECHILD; + return -1; +} + +int _unlink(char *name) +{ + (void)name; + errno = ENOENT; + return -1; +} + +clock_t _times(struct tms *buf) +{ + (void)buf; + return -1; +} + +int _stat(const char *file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + return 0; +} + +int _link(char *old, char *new) +{ + (void)old; + (void)new; + errno = EMLINK; + return -1; +} + +int _fork(void) +{ + errno = EAGAIN; + return -1; +} + +int _execve(char *name, char **argv, char **env) +{ + (void)name; + (void)argv; + (void)env; + errno = ENOMEM; + return -1; +} + +// --- Picolibc Specific Section --- +#if defined(__PICOLIBC__) + +/** + * @brief Picolibc helper function to output a character to a FILE stream. + * This redirects the output to the low-level __io_putchar function. + * @param c Character to write. + * @param file FILE stream pointer (ignored). + * @retval int The character written. + */ +static int starm_putc(char c, FILE *file) +{ + (void) file; + __io_putchar(c); + return c; +} + +/** + * @brief Picolibc helper function to input a character from a FILE stream. + * This redirects the input from the low-level __io_getchar function. + * @param file FILE stream pointer (ignored). + * @retval int The character read, cast to an unsigned char then int. + */ +static int starm_getc(FILE *file) +{ + unsigned char c; + (void) file; + c = __io_getchar(); + return c; +} + +// Define and initialize the standard I/O streams for Picolibc. +// FDEV_SETUP_STREAM connects the starm_putc and starm_getc helper functions to a FILE structure. +// _FDEV_SETUP_RW indicates the stream is for reading and writing. +static FILE __stdio = FDEV_SETUP_STREAM(starm_putc, + starm_getc, + NULL, + _FDEV_SETUP_RW); + +// Assign the standard stream pointers (stdin, stdout, stderr) to the initialized stream. +// Picolibc uses these pointers for standard I/O operations (printf, scanf, etc.). +FILE *const stdin = &__stdio; +__strong_reference(stdin, stdout); +__strong_reference(stdin, stderr); + +// Create strong aliases mapping standard C library function names (without underscore) +// to the implemented system call stubs (with underscore). Picolibc uses these +// standard names internally, so this linking is required. +__strong_reference(_read, read); +__strong_reference(_write, write); +__strong_reference(_times, times); +__strong_reference(_execve, execve); +__strong_reference(_fork, fork); +__strong_reference(_link, link); +__strong_reference(_unlink, unlink); +__strong_reference(_stat, stat); +__strong_reference(_wait, wait); +__strong_reference(_open, open); +__strong_reference(_close, close); +__strong_reference(_lseek, lseek); +__strong_reference(_isatty, isatty); +__strong_reference(_fstat, fstat); +__strong_reference(_exit, exit); +__strong_reference(_kill, kill); +__strong_reference(_getpid, getpid); + +#endif //__PICOLIBC__ diff --git a/src/Core/Src/sysmem.c b/src/Core/Src/sysmem.c new file mode 100644 index 00000000..a875d42c --- /dev/null +++ b/src/Core/Src/sysmem.c @@ -0,0 +1,87 @@ +/** + ****************************************************************************** + * @file sysmem.c + * @author Generated by STM32CubeMX + * @brief System Memory calls file + * + * For more information about which C functions + * need which of these lowlevel functions + * please consult the Newlib or Picolibc libc manual + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes */ +#include +#include +#include + +/** + * Pointer to the current high watermark of the heap usage + */ +static uint8_t *__sbrk_heap_end = NULL; + +/** + * @brief _sbrk() allocates memory to the newlib heap and is used by malloc + * and others from the C library + * + * @verbatim + * ############################################################################ + * # .data # .bss # newlib heap # MSP stack # + * # # # # Reserved by _Min_Stack_Size # + * ############################################################################ + * ^-- RAM start ^-- _end _estack, RAM end --^ + * @endverbatim + * + * This implementation starts allocating at the '_end' linker symbol + * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack + * The implementation considers '_estack' linker symbol to be RAM end + * NOTE: If the MSP stack, at any point during execution, grows larger than the + * reserved size, please increase the '_Min_Stack_Size'. + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + const uint8_t *max_heap = (uint8_t *)stack_limit; + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + { + __sbrk_heap_end = &_end; + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + { + errno = ENOMEM; + return (void *)-1; + } + + prev_heap_end = __sbrk_heap_end; + __sbrk_heap_end += incr; + + return (void *)prev_heap_end; +} + +#if defined(__PICOLIBC__) + // Picolibc expects syscalls without the leading underscore. + // This creates a strong alias so that + // calls to `sbrk()` are resolved to our `_sbrk()` implementation. + __strong_reference(_sbrk, sbrk); +#endif diff --git a/src/Core/Src/tim.c b/src/Core/Src/tim.c new file mode 100644 index 00000000..f7631915 --- /dev/null +++ b/src/Core/Src/tim.c @@ -0,0 +1,457 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file tim.c + * @brief This file provides code for the configuration + * of the TIM instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "tim.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +TIM_HandleTypeDef htim2; +TIM_HandleTypeDef htim3; +TIM_HandleTypeDef htim10; +TIM_HandleTypeDef htim11; +TIM_HandleTypeDef htim12; + +/* TIM2 init function */ +void MX_TIM2_Init(void) +{ + + /* USER CODE BEGIN TIM2_Init 0 */ + + /* USER CODE END TIM2_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM2_Init 1 */ + + /* USER CODE END TIM2_Init 1 */ + htim2.Instance = TIM2; + htim2.Init.Prescaler = 0; + htim2.Init.CounterMode = TIM_COUNTERMODE_UP; + htim2.Init.Period = 4294967295; + htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM2_Init 2 */ + + /* USER CODE END TIM2_Init 2 */ + HAL_TIM_MspPostInit(&htim2); + +} +/* TIM3 init function */ +void MX_TIM3_Init(void) +{ + + /* USER CODE BEGIN TIM3_Init 0 */ + + /* USER CODE END TIM3_Init 0 */ + + TIM_MasterConfigTypeDef sMasterConfig = {0}; + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM3_Init 1 */ + + /* USER CODE END TIM3_Init 1 */ + htim3.Instance = TIM3; + htim3.Init.Prescaler = 0; + htim3.Init.CounterMode = TIM_COUNTERMODE_UP; + htim3.Init.Period = 65535; + htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) + { + Error_Handler(); + } + sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; + sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; + if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM3_Init 2 */ + + /* USER CODE END TIM3_Init 2 */ + HAL_TIM_MspPostInit(&htim3); + +} +/* TIM10 init function */ +void MX_TIM10_Init(void) +{ + + /* USER CODE BEGIN TIM10_Init 0 */ + + /* USER CODE END TIM10_Init 0 */ + + /* USER CODE BEGIN TIM10_Init 1 */ + + /* USER CODE END TIM10_Init 1 */ + htim10.Instance = TIM10; + htim10.Init.Prescaler = 0; + htim10.Init.CounterMode = TIM_COUNTERMODE_UP; + htim10.Init.Period = 65535; + htim10.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim10.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim10) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM10_Init 2 */ + + /* USER CODE END TIM10_Init 2 */ + +} +/* TIM11 init function */ +void MX_TIM11_Init(void) +{ + + /* USER CODE BEGIN TIM11_Init 0 */ + + /* USER CODE END TIM11_Init 0 */ + + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM11_Init 1 */ + + /* USER CODE END TIM11_Init 1 */ + htim11.Instance = TIM11; + htim11.Init.Prescaler = 0; + htim11.Init.CounterMode = TIM_COUNTERMODE_UP; + htim11.Init.Period = 65535; + htim11.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim11.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_Base_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + if (HAL_TIM_PWM_Init(&htim11) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_PWM1; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_PWM_ConfigChannel(&htim11, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM11_Init 2 */ + + /* USER CODE END TIM11_Init 2 */ + HAL_TIM_MspPostInit(&htim11); + +} +/* TIM12 init function */ +void MX_TIM12_Init(void) +{ + + /* USER CODE BEGIN TIM12_Init 0 */ + + /* USER CODE END TIM12_Init 0 */ + + TIM_OC_InitTypeDef sConfigOC = {0}; + + /* USER CODE BEGIN TIM12_Init 1 */ + + /* USER CODE END TIM12_Init 1 */ + htim12.Instance = TIM12; + htim12.Init.Prescaler = 0; + htim12.Init.CounterMode = TIM_COUNTERMODE_UP; + htim12.Init.Period = 65535; + htim12.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; + htim12.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; + if (HAL_TIM_OC_Init(&htim12) != HAL_OK) + { + Error_Handler(); + } + sConfigOC.OCMode = TIM_OCMODE_TIMING; + sConfigOC.Pulse = 0; + sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; + sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; + if (HAL_TIM_OC_ConfigChannel(&htim12, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN TIM12_Init 2 */ + + /* USER CODE END TIM12_Init 2 */ + HAL_TIM_MspPostInit(&htim12); + +} + +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) +{ + + if(tim_pwmHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspInit 0 */ + + /* USER CODE END TIM2_MspInit 0 */ + /* TIM2 clock enable */ + __HAL_RCC_TIM2_CLK_ENABLE(); + /* USER CODE BEGIN TIM2_MspInit 1 */ + + /* USER CODE END TIM2_MspInit 1 */ + } + else if(tim_pwmHandle->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspInit 0 */ + + /* USER CODE END TIM3_MspInit 0 */ + /* TIM3 clock enable */ + __HAL_RCC_TIM3_CLK_ENABLE(); + /* USER CODE BEGIN TIM3_MspInit 1 */ + + /* USER CODE END TIM3_MspInit 1 */ + } +} + +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspInit 0 */ + + /* USER CODE END TIM10_MspInit 0 */ + /* TIM10 clock enable */ + __HAL_RCC_TIM10_CLK_ENABLE(); + /* USER CODE BEGIN TIM10_MspInit 1 */ + + /* USER CODE END TIM10_MspInit 1 */ + } + else if(tim_baseHandle->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspInit 0 */ + + /* USER CODE END TIM11_MspInit 0 */ + /* TIM11 clock enable */ + __HAL_RCC_TIM11_CLK_ENABLE(); + /* USER CODE BEGIN TIM11_MspInit 1 */ + + /* USER CODE END TIM11_MspInit 1 */ + } +} + +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef* tim_ocHandle) +{ + + if(tim_ocHandle->Instance==TIM12) + { + /* USER CODE BEGIN TIM12_MspInit 0 */ + + /* USER CODE END TIM12_MspInit 0 */ + /* TIM12 clock enable */ + __HAL_RCC_TIM12_CLK_ENABLE(); + /* USER CODE BEGIN TIM12_MspInit 1 */ + + /* USER CODE END TIM12_MspInit 1 */ + } +} +void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(timHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspPostInit 0 */ + + /* USER CODE END TIM2_MspPostInit 0 */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM2 GPIO Configuration + PB11 ------> TIM2_CH4 + */ + GPIO_InitStruct.Pin = FAN_PWM_R_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2; + HAL_GPIO_Init(FAN_PWM_R_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM2_MspPostInit 1 */ + + /* USER CODE END TIM2_MspPostInit 1 */ + } + else if(timHandle->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspPostInit 0 */ + + /* USER CODE END TIM3_MspPostInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM3 GPIO Configuration + PB1 ------> TIM3_CH4 + */ + GPIO_InitStruct.Pin = PWM_SPARE_1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3; + HAL_GPIO_Init(PWM_SPARE_1_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM3_MspPostInit 1 */ + + /* USER CODE END TIM3_MspPostInit 1 */ + } + else if(timHandle->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspPostInit 0 */ + + /* USER CODE END TIM11_MspPostInit 0 */ + + __HAL_RCC_GPIOF_CLK_ENABLE(); + /**TIM11 GPIO Configuration + PF7 ------> TIM11_CH1 + */ + GPIO_InitStruct.Pin = PWM_SPARE_2_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF3_TIM11; + HAL_GPIO_Init(PWM_SPARE_2_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM11_MspPostInit 1 */ + + /* USER CODE END TIM11_MspPostInit 1 */ + } + else if(timHandle->Instance==TIM12) + { + /* USER CODE BEGIN TIM12_MspPostInit 0 */ + + /* USER CODE END TIM12_MspPostInit 0 */ + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**TIM12 GPIO Configuration + PB15 ------> TIM12_CH2 + */ + GPIO_InitStruct.Pin = FAN_PWM_L_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF9_TIM12; + HAL_GPIO_Init(FAN_PWM_L_GPIO_Port, &GPIO_InitStruct); + + /* USER CODE BEGIN TIM12_MspPostInit 1 */ + + /* USER CODE END TIM12_MspPostInit 1 */ + } + +} + +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle) +{ + + if(tim_pwmHandle->Instance==TIM2) + { + /* USER CODE BEGIN TIM2_MspDeInit 0 */ + + /* USER CODE END TIM2_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM2_CLK_DISABLE(); + /* USER CODE BEGIN TIM2_MspDeInit 1 */ + + /* USER CODE END TIM2_MspDeInit 1 */ + } + else if(tim_pwmHandle->Instance==TIM3) + { + /* USER CODE BEGIN TIM3_MspDeInit 0 */ + + /* USER CODE END TIM3_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM3_CLK_DISABLE(); + /* USER CODE BEGIN TIM3_MspDeInit 1 */ + + /* USER CODE END TIM3_MspDeInit 1 */ + } +} + +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle) +{ + + if(tim_baseHandle->Instance==TIM10) + { + /* USER CODE BEGIN TIM10_MspDeInit 0 */ + + /* USER CODE END TIM10_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM10_CLK_DISABLE(); + /* USER CODE BEGIN TIM10_MspDeInit 1 */ + + /* USER CODE END TIM10_MspDeInit 1 */ + } + else if(tim_baseHandle->Instance==TIM11) + { + /* USER CODE BEGIN TIM11_MspDeInit 0 */ + + /* USER CODE END TIM11_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM11_CLK_DISABLE(); + /* USER CODE BEGIN TIM11_MspDeInit 1 */ + + /* USER CODE END TIM11_MspDeInit 1 */ + } +} + +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef* tim_ocHandle) +{ + + if(tim_ocHandle->Instance==TIM12) + { + /* USER CODE BEGIN TIM12_MspDeInit 0 */ + + /* USER CODE END TIM12_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_TIM12_CLK_DISABLE(); + /* USER CODE BEGIN TIM12_MspDeInit 1 */ + + /* USER CODE END TIM12_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/Core/Src/tx_initialize_low_level.s b/src/Core/Src/tx_initialize_low_level.s index 43e78380..9f60a4d4 100644 --- a/src/Core/Src/tx_initialize_low_level.s +++ b/src/Core/Src/tx_initialize_low_level.s @@ -64,7 +64,7 @@ .global __Vectors @ @ -SYSTEM_CLOCK = 72000000 +SYSTEM_CLOCK = 216000000 SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) .text 32 @@ -271,7 +271,7 @@ __tx_DBGHandler: EXTERN _tx_execution_isr_exit ; ; -SYSTEM_CLOCK EQU 72000000 +SYSTEM_CLOCK EQU 216000000 SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 1000) -1) #ifdef USE_DYNAMIC_MEMORY_ALLOCATION @@ -455,7 +455,7 @@ SysTick_Handler: @ @ -SYSTEM_CLOCK = 72000000 +SYSTEM_CLOCK = 216000000 SYSTICK_CYCLES = ((SYSTEM_CLOCK / 1000) -1) .text 32 diff --git a/src/Core/Src/usart.c b/src/Core/Src/usart.c index 6cbcc021..7c72ca15 100644 --- a/src/Core/Src/usart.c +++ b/src/Core/Src/usart.c @@ -24,11 +24,42 @@ /* USER CODE END 0 */ -UART_HandleTypeDef huart1; +UART_HandleTypeDef huart8; +USART_HandleTypeDef husart1; -/* USART1 init function */ +/* UART8 init function */ +void MX_UART8_Init(void) +{ + + /* USER CODE BEGIN UART8_Init 0 */ + + /* USER CODE END UART8_Init 0 */ + + /* USER CODE BEGIN UART8_Init 1 */ + + /* USER CODE END UART8_Init 1 */ + huart8.Instance = UART8; + huart8.Init.BaudRate = 115200; + huart8.Init.WordLength = UART_WORDLENGTH_8B; + huart8.Init.StopBits = UART_STOPBITS_1; + huart8.Init.Parity = UART_PARITY_NONE; + huart8.Init.Mode = UART_MODE_TX_RX; + huart8.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart8.Init.OverSampling = UART_OVERSAMPLING_16; + huart8.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart8.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_SWAP_INIT; + huart8.AdvancedInit.Swap = UART_ADVFEATURE_SWAP_ENABLE; + if (HAL_UART_Init(&huart8) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN UART8_Init 2 */ -void MX_USART1_UART_Init(void) + /* USER CODE END UART8_Init 2 */ + +} +/* USART1 init function */ +void MX_USART1_Init(void) { /* USER CODE BEGIN USART1_Init 0 */ @@ -38,17 +69,16 @@ void MX_USART1_UART_Init(void) /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ - huart1.Instance = USART1; - huart1.Init.BaudRate = 115200; - huart1.Init.WordLength = UART_WORDLENGTH_8B; - huart1.Init.StopBits = UART_STOPBITS_1; - huart1.Init.Parity = UART_PARITY_NONE; - huart1.Init.Mode = UART_MODE_TX_RX; - huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart1.Init.OverSampling = UART_OVERSAMPLING_16; - huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart1) != HAL_OK) + husart1.Instance = USART1; + husart1.Init.BaudRate = 115200; + husart1.Init.WordLength = USART_WORDLENGTH_8B; + husart1.Init.StopBits = USART_STOPBITS_1; + husart1.Init.Parity = USART_PARITY_NONE; + husart1.Init.Mode = USART_MODE_TX_RX; + husart1.Init.CLKPolarity = USART_POLARITY_LOW; + husart1.Init.CLKPhase = USART_PHASE_1EDGE; + husart1.Init.CLKLastBit = USART_LASTBIT_DISABLE; + if (HAL_USART_Init(&husart1) != HAL_OK) { Error_Handler(); } @@ -63,7 +93,48 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) GPIO_InitTypeDef GPIO_InitStruct = {0}; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; - if(uartHandle->Instance==USART1) + if(uartHandle->Instance==UART8) + { + /* USER CODE BEGIN UART8_MspInit 0 */ + + /* USER CODE END UART8_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART8; + PeriphClkInitStruct.Uart8ClockSelection = RCC_UART8CLKSOURCE_PCLK1; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* UART8 clock enable */ + __HAL_RCC_UART8_CLK_ENABLE(); + + __HAL_RCC_GPIOE_CLK_ENABLE(); + /**UART8 GPIO Configuration + PE0 ------> UART8_RX + PE1 ------> UART8_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_UART8; + HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); + + /* USER CODE BEGIN UART8_MspInit 1 */ + + /* USER CODE END UART8_MspInit 1 */ + } +} + +void HAL_USART_MspInit(USART_HandleTypeDef* usartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(usartHandle->Instance==USART1) { /* USER CODE BEGIN USART1_MspInit 0 */ @@ -83,10 +154,11 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) __HAL_RCC_GPIOA_CLK_ENABLE(); /**USART1 GPIO Configuration + PA8 ------> USART1_CK PA9 ------> USART1_TX PA10 ------> USART1_RX */ - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10; + GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; @@ -102,7 +174,30 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) { - if(uartHandle->Instance==USART1) + if(uartHandle->Instance==UART8) + { + /* USER CODE BEGIN UART8_MspDeInit 0 */ + + /* USER CODE END UART8_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_UART8_CLK_DISABLE(); + + /**UART8 GPIO Configuration + PE0 ------> UART8_RX + PE1 ------> UART8_TX + */ + HAL_GPIO_DeInit(GPIOE, GPIO_PIN_0|GPIO_PIN_1); + + /* USER CODE BEGIN UART8_MspDeInit 1 */ + + /* USER CODE END UART8_MspDeInit 1 */ + } +} + +void HAL_USART_MspDeInit(USART_HandleTypeDef* usartHandle) +{ + + if(usartHandle->Instance==USART1) { /* USER CODE BEGIN USART1_MspDeInit 0 */ @@ -111,10 +206,11 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) __HAL_RCC_USART1_CLK_DISABLE(); /**USART1 GPIO Configuration + PA8 ------> USART1_CK PA9 ------> USART1_TX PA10 ------> USART1_RX */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10); + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10); /* USER CODE BEGIN USART1_MspDeInit 1 */ diff --git a/src/Core/Src/usb_otg.c b/src/Core/Src/usb_otg.c new file mode 100644 index 00000000..d089e9e0 --- /dev/null +++ b/src/Core/Src/usb_otg.c @@ -0,0 +1,135 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usb_otg.c + * @brief This file provides code for the configuration + * of the USB_OTG instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2026 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usb_otg.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +PCD_HandleTypeDef hpcd_USB_OTG_FS; + +/* USB_OTG_FS init function */ + +void MX_USB_OTG_FS_PCD_Init(void) +{ + + /* USER CODE BEGIN USB_OTG_FS_Init 0 */ + + /* USER CODE END USB_OTG_FS_Init 0 */ + + /* USER CODE BEGIN USB_OTG_FS_Init 1 */ + + /* USER CODE END USB_OTG_FS_Init 1 */ + hpcd_USB_OTG_FS.Instance = USB_OTG_FS; + hpcd_USB_OTG_FS.Init.dev_endpoints = 6; + hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; + hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; + hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; + hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; + hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; + hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; + hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_OTG_FS_Init 2 */ + /* HAL_PCD_Init leaves EP TX FIFOs at 0 depth, causing continuous TXFE interrupts. */ + HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80); /* RX: 128 words (512 B) */ + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40); /* EP0 TX: 64 words (256 B) */ + HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80); /* EP1 TX: 128 words (512 B) */ + /* USER CODE END USB_OTG_FS_Init 2 */ + +} + +void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(pcdHandle->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ + + /* USER CODE END USB_OTG_FS_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF10_OTG_FS; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* USB_OTG_FS clock enable */ + __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + + /* USB_OTG_FS interrupt Init */ + HAL_NVIC_SetPriority(OTG_FS_IRQn, 15, 0); + HAL_NVIC_EnableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ + + /* USER CODE END USB_OTG_FS_MspInit 1 */ + } +} + +void HAL_PCD_MspDeInit(PCD_HandleTypeDef* pcdHandle) +{ + + if(pcdHandle->Instance==USB_OTG_FS) + { + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USB_OTG_FS_CLK_DISABLE(); + + /**USB_OTG_FS GPIO Configuration + PA11 ------> USB_OTG_FS_DM + PA12 ------> USB_OTG_FS_DP + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12); + + /* USB_OTG_FS interrupt Deinit */ + HAL_NVIC_DisableIRQ(OTG_FS_IRQn); + /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ + + /* USER CODE END USB_OTG_FS_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h b/src/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h index 934ae7f7..d8c5faca 100644 --- a/src/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h +++ b/src/Drivers/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h @@ -1,17906 +1,17906 @@ -/** - ****************************************************************************** - * @file stm32f746xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral's registers hardware - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS_Device - * @{ - */ - -/** @addtogroup stm32f746xx - * @{ - */ - -#ifndef __STM32F746xx_H -#define __STM32F746xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Configuration_section_for_CMSIS - * @{ - */ - -/** - * @brief STM32F7xx Interrupt Number Definition, according to the selected device - * in @ref Library_configuration_section - */ -typedef enum -{ -/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */ - BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */ - UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */ -/****** STM32 specific Interrupt Numbers **********************************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ - TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ - RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ - FLASH_IRQn = 4, /*!< FLASH global Interrupt */ - RCC_IRQn = 5, /*!< RCC global Interrupt */ - EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ - EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ - EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ - EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ - EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ - DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ - DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ - DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ - DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ - DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ - DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ - DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ - ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ - CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ - CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ - CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ - CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ - EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ - TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ - TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ - TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ - TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ - TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ - TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ - TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ - I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ - I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ - I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ - I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ - SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ - SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ - USART1_IRQn = 37, /*!< USART1 global Interrupt */ - USART2_IRQn = 38, /*!< USART2 global Interrupt */ - USART3_IRQn = 39, /*!< USART3 global Interrupt */ - EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ - RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ - OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ - TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ - TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ - TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ - TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */ - DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ - FMC_IRQn = 48, /*!< FMC global Interrupt */ - SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */ - TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ - SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ - UART4_IRQn = 52, /*!< UART4 global Interrupt */ - UART5_IRQn = 53, /*!< UART5 global Interrupt */ - TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ - TIM7_IRQn = 55, /*!< TIM7 global interrupt */ - DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ - DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ - DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ - DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ - DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ - ETH_IRQn = 61, /*!< Ethernet global Interrupt */ - ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ - CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ - CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ - CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ - CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ - OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ - DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ - DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ - DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ - USART6_IRQn = 71, /*!< USART6 global interrupt */ - I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ - OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ - OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ - OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ - OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ - DCMI_IRQn = 78, /*!< DCMI global interrupt */ - RNG_IRQn = 80, /*!< RNG global interrupt */ - FPU_IRQn = 81, /*!< FPU global interrupt */ - UART7_IRQn = 82, /*!< UART7 global interrupt */ - UART8_IRQn = 83, /*!< UART8 global interrupt */ - SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ - SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ - SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ - SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ - LTDC_IRQn = 88, /*!< LTDC global Interrupt */ - LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ - DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ - SAI2_IRQn = 91, /*!< SAI2 global Interrupt */ - QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */ - LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */ - CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */ - I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */ - I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */ - SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */ -} IRQn_Type; - -/** - * @} - */ - -/** - * @brief Configuration of the Cortex-M7 Processor and Core Peripherals - */ -#define __CM7_REV 0x0001U /*!< Cortex-M7 revision r0p1 */ -#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */ -#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /*!< FPU present */ -#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */ -#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */ -#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */ - - -#include "system_stm32f7xx.h" -#include - -/** @addtogroup Peripheral_registers_structures - * @{ - */ - -/** - * @brief Analog to Digital Converter - */ - -typedef struct -{ - __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ - __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ - __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ - __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ - __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ - __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ - __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ - __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ - __IO uint32_t CDR; /*!< ADC common regular data register for dual - AND triple modes, Address offset: ADC1 base address + 0x308 */ -} ADC_Common_TypeDef; - - -/** - * @brief Controller Area Network TxMailBox - */ - -typedef struct -{ - __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ - __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ - __IO uint32_t TDLR; /*!< CAN mailbox data low register */ - __IO uint32_t TDHR; /*!< CAN mailbox data high register */ -} CAN_TxMailBox_TypeDef; - -/** - * @brief Controller Area Network FIFOMailBox - */ - -typedef struct -{ - __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ - __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ - __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ - __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ -} CAN_FIFOMailBox_TypeDef; - -/** - * @brief Controller Area Network FilterRegister - */ - -typedef struct -{ - __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ - __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ -} CAN_FilterRegister_TypeDef; - -/** - * @brief Controller Area Network - */ - -typedef struct -{ - __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ - __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ - __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ - __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ - __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ - __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ - __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ - __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ - uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ - CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ - CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ - uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ - __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ - __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ - uint32_t RESERVED2; /*!< Reserved, 0x208 */ - __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ - uint32_t RESERVED3; /*!< Reserved, 0x210 */ - __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ - uint32_t RESERVED4; /*!< Reserved, 0x218 */ - __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ - uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ - CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ -} CAN_TypeDef; - -/** - * @brief HDMI-CEC - */ - -typedef struct -{ - __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ - __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ - __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ - __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ - __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ - __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ -}CEC_TypeDef; - -/** - * @brief CRC calculation unit - */ - -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - uint8_t RESERVED0; /*!< Reserved, 0x05 */ - uint16_t RESERVED1; /*!< Reserved, 0x06 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ -} CRC_TypeDef; - -/** - * @brief Digital to Analog Converter - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ -} DAC_TypeDef; - - -/** - * @brief Debug MCU - */ - -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ - __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ -}DBGMCU_TypeDef; - -/** - * @brief DCMI - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA stream x configuration register */ - __IO uint32_t NDTR; /*!< DMA stream x number of data register */ - __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ - __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ - __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ - __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ -} DMA_Stream_TypeDef; - -typedef struct -{ - __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ - __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ - __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ - __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ -} DMA_TypeDef; - -/** - * @brief DMA2D Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ - __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ - __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ - __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ - __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ - __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ - __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ - __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ - __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ - __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ - __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ - __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ - __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ - __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ - __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ - __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ - __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ - __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ - __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ - __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ -} DMA2D_TypeDef; - - -/** - * @brief Ethernet MAC - */ - -typedef struct -{ - __IO uint32_t MACCR; - __IO uint32_t MACFFR; - __IO uint32_t MACHTHR; - __IO uint32_t MACHTLR; - __IO uint32_t MACMIIAR; - __IO uint32_t MACMIIDR; - __IO uint32_t MACFCR; - __IO uint32_t MACVLANTR; /* 8 */ - uint32_t RESERVED0[2]; - __IO uint32_t MACRWUFFR; /* 11 */ - __IO uint32_t MACPMTCSR; - uint32_t RESERVED1; - __IO uint32_t MACDBGR; - __IO uint32_t MACSR; /* 15 */ - __IO uint32_t MACIMR; - __IO uint32_t MACA0HR; - __IO uint32_t MACA0LR; - __IO uint32_t MACA1HR; - __IO uint32_t MACA1LR; - __IO uint32_t MACA2HR; - __IO uint32_t MACA2LR; - __IO uint32_t MACA3HR; - __IO uint32_t MACA3LR; /* 24 */ - uint32_t RESERVED2[40]; - __IO uint32_t MMCCR; /* 65 */ - __IO uint32_t MMCRIR; - __IO uint32_t MMCTIR; - __IO uint32_t MMCRIMR; - __IO uint32_t MMCTIMR; /* 69 */ - uint32_t RESERVED3[14]; - __IO uint32_t MMCTGFSCCR; /* 84 */ - __IO uint32_t MMCTGFMSCCR; - uint32_t RESERVED4[5]; - __IO uint32_t MMCTGFCR; - uint32_t RESERVED5[10]; - __IO uint32_t MMCRFCECR; - __IO uint32_t MMCRFAECR; - uint32_t RESERVED6[10]; - __IO uint32_t MMCRGUFCR; - uint32_t RESERVED7[334]; - __IO uint32_t PTPTSCR; - __IO uint32_t PTPSSIR; - __IO uint32_t PTPTSHR; - __IO uint32_t PTPTSLR; - __IO uint32_t PTPTSHUR; - __IO uint32_t PTPTSLUR; - __IO uint32_t PTPTSAR; - __IO uint32_t PTPTTHR; - __IO uint32_t PTPTTLR; - __IO uint32_t RESERVED8; - __IO uint32_t PTPTSSR; - __IO uint32_t PTPPPSCR; - uint32_t RESERVED9[564]; - __IO uint32_t DMABMR; - __IO uint32_t DMATPDR; - __IO uint32_t DMARPDR; - __IO uint32_t DMARDLAR; - __IO uint32_t DMATDLAR; - __IO uint32_t DMASR; - __IO uint32_t DMAOMR; - __IO uint32_t DMAIER; - __IO uint32_t DMAMFBOCR; - __IO uint32_t DMARSWTR; - uint32_t RESERVED10[8]; - __IO uint32_t DMACHTDR; - __IO uint32_t DMACHRDR; - __IO uint32_t DMACHTBAR; - __IO uint32_t DMACHRBAR; -} ETH_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ - __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ - __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ - __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ - __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ - __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ - -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ - __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ - __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ -} FLASH_TypeDef; - - - -/** - * @brief Flexible Memory Controller - */ - -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ - -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ - -typedef struct -{ - __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ - __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ - __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ - __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief Flexible Memory Controller Bank5_6 - */ - -typedef struct -{ - __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ - __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ - __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ - __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ - __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ -} FMC_Bank5_6_TypeDef; - - -/** - * @brief General Purpose I/O - */ - -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ -} GPIO_TypeDef; - -/** - * @brief System configuration controller - */ - -typedef struct -{ - __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ - __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ - __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ - uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ - __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ -} SYSCFG_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ -} I2C_TypeDef; - -/** - * @brief Independent WATCHDOG - */ - -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ -} IWDG_TypeDef; - - -/** - * @brief LCD-TFT Display Controller - */ - -typedef struct -{ - uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ - __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ - __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ - __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ - __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ - __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ - __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ - uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ - __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ - uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ - __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ - __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ - __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ - __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ - __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ - __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ -} LTDC_TypeDef; - -/** - * @brief LCD-TFT Display layer x Controller - */ - -typedef struct -{ - __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ - __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ - __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ - __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ - __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ - __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ - __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ - __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ - uint32_t RESERVED0[2]; /*!< Reserved */ - __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ - __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ - __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ - uint32_t RESERVED1[3]; /*!< Reserved */ - __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ - -} LTDC_Layer_TypeDef; - -/** - * @brief Power Control - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ - __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ - __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ -} PWR_TypeDef; - - -/** - * @brief Reset and Clock Control - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ - __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ - __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ - __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ - __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ - __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ - __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ - uint32_t RESERVED0; /*!< Reserved, 0x1C */ - __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ - __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ - __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ - __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ - __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ - uint32_t RESERVED2; /*!< Reserved, 0x3C */ - __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ - __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ - uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ - __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ - __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ - __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ - uint32_t RESERVED4; /*!< Reserved, 0x5C */ - __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ - __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ - uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ - __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ - __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ - uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ - __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ - __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ - __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ - __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ - __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ - -} RCC_TypeDef; - -/** - * @brief Real-Time Clock - */ - -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - uint32_t reserved; /*!< Reserved */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ - __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ - __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ - __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ - __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ - __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ - __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ - __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ - __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ - __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ - __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ - __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ - __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ - __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ - __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ - __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ - __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ - __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ - __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ - __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ - __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ - __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ - __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ - __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ - __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ - __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ - __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ - __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ - __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ - __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ - __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ - __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ - __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ - __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ - __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ -} RTC_TypeDef; - - -/** - * @brief Serial Audio Interface - */ - -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief SPDIF-RX Interface - */ - -typedef struct -{ - __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ - __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ - __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ - __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ - __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ - __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ -} SPDIFRX_TypeDef; - -/** - * @brief SD host Interface - */ - -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ - __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ - uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; - -/** - * @brief Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ - __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ - __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ - __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ - __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ - __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ - __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ - __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ -} SPI_TypeDef; - -/** - * @brief QUAD Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ - __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ - __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ - __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ - __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ - __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ - __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ - __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ - __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ - __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ -} QUADSPI_TypeDef; - -/** - * @brief TIM - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ - __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ - __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ - __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ - -} TIM_TypeDef; - -/** - * @brief LPTIMIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ -} LPTIM_TypeDef; - - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ - -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ -} USART_TypeDef; - - -/** - * @brief Window WATCHDOG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - - -/** - * @brief RNG - */ - -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ -} RNG_TypeDef; - -/** - * @} - */ - -/** - * @brief USB_OTG_Core_Registers - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ - uint32_t Reserved30[2]; /*!< Reserved 030h */ - __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ - __IO uint32_t CID; /*!< User ID Register 03Ch */ - uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ - __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ - uint32_t Reserved6; /*!< Reserved 050h */ - __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ - uint32_t Reserved7; /*!< Reserved 058h */ - __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ - uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ -} USB_OTG_GlobalTypeDef; - - -/** - * @brief USB_OTG_device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ - __IO uint32_t DCTL; /*!< dev Control Register 804h */ - __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ - uint32_t Reserved0C; /*!< Reserved 80Ch */ - __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ - uint32_t Reserved20; /*!< Reserved 820h */ - uint32_t Reserved9; /*!< Reserved 824h */ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ - __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ - uint32_t Reserved40; /*!< dedicated EP mask 840h */ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ - uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ -} USB_OTG_DeviceTypeDef; - - -/** - * @brief USB_OTG_IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ - __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ - __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ - __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ - uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ -} USB_OTG_INEndpointTypeDef; - - -/** - * @brief USB_OTG_OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ - uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ - __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ - uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ - __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ - uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ -} USB_OTG_OUTEndpointTypeDef; - - -/** - * @brief USB_OTG_Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ - __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ - __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ - uint32_t Reserved40C; /*!< Reserved 40Ch */ - __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ - __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ - __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ -} USB_OTG_HostTypeDef; - -/** - * @brief USB_OTG_Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ - __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ - __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ - __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ - __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ - __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ - uint32_t Reserved[2]; /*!< Reserved */ -} USB_OTG_HostChannelTypeDef; -/** - * @} - */ - - - - -/** @addtogroup Peripheral_memory_map - * @{ - */ -#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ -#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */ -#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ -#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 64KB system data RAM accessible over DTCM */ -#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */ -#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */ -#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */ -#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */ -#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */ -#define SRAM1_BASE 0x20010000UL /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ -#define SRAM2_BASE 0x2004C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ -#define FLASH_END 0x080FFFFFUL /*!< FLASH end address */ -#define FLASH_OTP_BASE 0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ -#define FLASH_OTP_END 0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ - -/* Legacy define */ -#define FLASH_BASE FLASHAXI_BASE - -/*!< Peripheral memory map */ -#define APB1PERIPH_BASE PERIPH_BASE -#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) -#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) -#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) - -/*!< APB1 peripherals */ -#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) -#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) -#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) -#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) -#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) -#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) -#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) -#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) -#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) -#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) -#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) -#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) -#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) -#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) -#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) -#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) -#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) -#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) -#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) -#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) -#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) -#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) -#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) -#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL) -#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) -#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) -#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) -#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) -#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) -#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) -#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) - -/*!< APB2 peripherals */ -#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) -#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) -#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) -#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) -#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) -#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) -#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) -#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL) -#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL) -#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) -#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) -#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) -#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) -#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) -#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) -#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) -#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) -#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL) -#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) -#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) -#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) -#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) -#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) -#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) -#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL) -#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL) -#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL) -/*!< AHB1 peripherals */ -#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) -#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) -#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) -#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) -#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) -#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) -#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) -#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL) -#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL) -#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) -#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) -#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) -#define UID_BASE 0x1FF0F420UL /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE 0x1FF0F442UL /*!< FLASH Size register base address */ -#define PACKAGE_BASE 0x1FF0F7E0UL /*!< Package size register base address */ -/* Legacy define */ -#define PACKAGESIZE_BASE PACKAGE_BASE - -#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) -#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) -#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) -#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) -#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) -#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) -#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) -#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) -#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) -#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) -#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) -#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) -#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) -#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) -#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) -#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) -#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) -#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) -#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) -#define ETH_MAC_BASE (ETH_BASE) -#define ETH_MMC_BASE (ETH_BASE + 0x0100UL) -#define ETH_PTP_BASE (ETH_BASE + 0x0700UL) -#define ETH_DMA_BASE (ETH_BASE + 0x1000UL) -#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL) -/*!< AHB2 peripherals */ -#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) -#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) -/*!< FMC Bankx registers base address */ -#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) -#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) -#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) -#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) - -/* Debug MCU registers base address */ -#define DBGMCU_BASE 0xE0042000UL - -/*!< USB registers base address */ -#define USB_OTG_HS_PERIPH_BASE 0x40040000UL -#define USB_OTG_FS_PERIPH_BASE 0x50000000UL - -#define USB_OTG_GLOBAL_BASE 0x0000UL -#define USB_OTG_DEVICE_BASE 0x0800UL -#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL -#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL -#define USB_OTG_EP_REG_SIZE 0x0020UL -#define USB_OTG_HOST_BASE 0x0400UL -#define USB_OTG_HOST_PORT_BASE 0x0440UL -#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL -#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL -#define USB_OTG_PCGCCTL_BASE 0x0E00UL -#define USB_OTG_FIFO_BASE 0x1000UL -#define USB_OTG_FIFO_SIZE 0x1000UL - -/** - * @} - */ - -/** @addtogroup Peripheral_declaration - * @{ - */ -#define TIM2 ((TIM_TypeDef *) TIM2_BASE) -#define TIM3 ((TIM_TypeDef *) TIM3_BASE) -#define TIM4 ((TIM_TypeDef *) TIM4_BASE) -#define TIM5 ((TIM_TypeDef *) TIM5_BASE) -#define TIM6 ((TIM_TypeDef *) TIM6_BASE) -#define TIM7 ((TIM_TypeDef *) TIM7_BASE) -#define TIM12 ((TIM_TypeDef *) TIM12_BASE) -#define TIM13 ((TIM_TypeDef *) TIM13_BASE) -#define TIM14 ((TIM_TypeDef *) TIM14_BASE) -#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) -#define RTC ((RTC_TypeDef *) RTC_BASE) -#define WWDG ((WWDG_TypeDef *) WWDG_BASE) -#define IWDG ((IWDG_TypeDef *) IWDG_BASE) -#define SPI2 ((SPI_TypeDef *) SPI2_BASE) -#define SPI3 ((SPI_TypeDef *) SPI3_BASE) -#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) -#define USART2 ((USART_TypeDef *) USART2_BASE) -#define USART3 ((USART_TypeDef *) USART3_BASE) -#define UART4 ((USART_TypeDef *) UART4_BASE) -#define UART5 ((USART_TypeDef *) UART5_BASE) -#define I2C1 ((I2C_TypeDef *) I2C1_BASE) -#define I2C2 ((I2C_TypeDef *) I2C2_BASE) -#define I2C3 ((I2C_TypeDef *) I2C3_BASE) -#define I2C4 ((I2C_TypeDef *) I2C4_BASE) -#define CAN1 ((CAN_TypeDef *) CAN1_BASE) -#define CAN2 ((CAN_TypeDef *) CAN2_BASE) -#define CEC ((CEC_TypeDef *) CEC_BASE) -#define PWR ((PWR_TypeDef *) PWR_BASE) -#define DAC1 ((DAC_TypeDef *) DAC_BASE) -#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ -#define UART7 ((USART_TypeDef *) UART7_BASE) -#define UART8 ((USART_TypeDef *) UART8_BASE) -#define TIM1 ((TIM_TypeDef *) TIM1_BASE) -#define TIM8 ((TIM_TypeDef *) TIM8_BASE) -#define USART1 ((USART_TypeDef *) USART1_BASE) -#define USART6 ((USART_TypeDef *) USART6_BASE) -#define ADC ((ADC_Common_TypeDef *) ADC_BASE) -#define ADC1 ((ADC_TypeDef *) ADC1_BASE) -#define ADC2 ((ADC_TypeDef *) ADC2_BASE) -#define ADC3 ((ADC_TypeDef *) ADC3_BASE) -#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) -#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) -#define SPI1 ((SPI_TypeDef *) SPI1_BASE) -#define SPI4 ((SPI_TypeDef *) SPI4_BASE) -#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) -#define EXTI ((EXTI_TypeDef *) EXTI_BASE) -#define TIM9 ((TIM_TypeDef *) TIM9_BASE) -#define TIM10 ((TIM_TypeDef *) TIM10_BASE) -#define TIM11 ((TIM_TypeDef *) TIM11_BASE) -#define SPI5 ((SPI_TypeDef *) SPI5_BASE) -#define SPI6 ((SPI_TypeDef *) SPI6_BASE) -#define SAI1 ((SAI_TypeDef *) SAI1_BASE) -#define SAI2 ((SAI_TypeDef *) SAI2_BASE) -#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) -#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) -#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) -#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) -#define LTDC ((LTDC_TypeDef *)LTDC_BASE) -#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) -#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) -#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) -#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) -#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) -#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) -#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) -#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) -#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) -#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) -#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) -#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) -#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) -#define CRC ((CRC_TypeDef *) CRC_BASE) -#define RCC ((RCC_TypeDef *) RCC_BASE) -#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) -#define DMA1 ((DMA_TypeDef *) DMA1_BASE) -#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) -#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) -#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) -#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) -#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) -#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) -#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) -#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) -#define DMA2 ((DMA_TypeDef *) DMA2_BASE) -#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) -#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) -#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) -#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) -#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) -#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) -#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) -#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) -#define ETH ((ETH_TypeDef *) ETH_BASE) -#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) -#define DCMI ((DCMI_TypeDef *) DCMI_BASE) -#define RNG ((RNG_TypeDef *) RNG_BASE) -#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) -#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) -#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) -#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) -#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) -#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) -#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) - -/** - * @} - */ - -/** @addtogroup Exported_constants - * @{ - */ - - /** @addtogroup Hardware_Constant_Definition - * @{ - */ -#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ - - /** - * @} - */ - - /** @addtogroup Peripheral_Registers_Bits_Definition - * @{ - */ - -/******************************************************************************/ -/* Peripheral Registers_Bits_Definition */ -/******************************************************************************/ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*! + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ + +typedef struct +{ + __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ + __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ + __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ + __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ + __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ + __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ + __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual + AND triple modes, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + + +/** + * @brief Controller Area Network TxMailBox + */ + +typedef struct +{ + __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ + __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ + __IO uint32_t TDLR; /*!< CAN mailbox data low register */ + __IO uint32_t TDHR; /*!< CAN mailbox data high register */ +} CAN_TxMailBox_TypeDef; + +/** + * @brief Controller Area Network FIFOMailBox + */ + +typedef struct +{ + __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ + __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ + __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ + __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ +} CAN_FIFOMailBox_TypeDef; + +/** + * @brief Controller Area Network FilterRegister + */ + +typedef struct +{ + __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ + __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ +} CAN_FilterRegister_TypeDef; + +/** + * @brief Controller Area Network + */ + +typedef struct +{ + __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ + __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ + __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ + __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ + __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ + __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ + __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ + __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ + uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ + CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ + uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ + __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ + __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ + uint32_t RESERVED2; /*!< Reserved, 0x208 */ + __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ + uint32_t RESERVED3; /*!< Reserved, 0x210 */ + __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ + uint32_t RESERVED4; /*!< Reserved, 0x218 */ + __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ + uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ + CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ +} CAN_TypeDef; + +/** + * @brief HDMI-CEC + */ + +typedef struct +{ + __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ + __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ + __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ + __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ + __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ + __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ +}CEC_TypeDef; + +/** + * @brief CRC calculation unit + */ + +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + uint8_t RESERVED0; /*!< Reserved, 0x05 */ + uint16_t RESERVED1; /*!< Reserved, 0x06 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Digital to Analog Converter + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ +} DAC_TypeDef; + + +/** + * @brief Debug MCU + */ + +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ + __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ +}DBGMCU_TypeDef; + +/** + * @brief DCMI + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA stream x configuration register */ + __IO uint32_t NDTR; /*!< DMA stream x number of data register */ + __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ + __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ + __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ + __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ +} DMA_Stream_TypeDef; + +typedef struct +{ + __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ + __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ + __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ + __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ +} DMA_TypeDef; + +/** + * @brief DMA2D Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ +} DMA2D_TypeDef; + + +/** + * @brief Ethernet MAC + */ + +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; /* 8 */ + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; /* 11 */ + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1; + __IO uint32_t MACDBGR; + __IO uint32_t MACSR; /* 15 */ + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; /* 24 */ + uint32_t RESERVED2[40]; + __IO uint32_t MMCCR; /* 65 */ + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; /* 69 */ + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; /* 84 */ + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + __IO uint32_t RESERVED8; + __IO uint32_t PTPTSSR; + __IO uint32_t PTPPPSCR; + uint32_t RESERVED9[564]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + __IO uint32_t DMARSWTR; + uint32_t RESERVED10[8]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + +/** + * @brief External Interrupt/Event Controller + */ + +typedef struct +{ + __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ + __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ + __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ + __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ + __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ + __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ + +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ + __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ + __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */ +} FLASH_TypeDef; + + + +/** + * @brief Flexible Memory Controller + */ + +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ + +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ + +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief Flexible Memory Controller Bank5_6 + */ + +typedef struct +{ + __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ + __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ + __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ + __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ + __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ +} FMC_Bank5_6_TypeDef; + + +/** + * @brief General Purpose I/O + */ + +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ +} GPIO_TypeDef; + +/** + * @brief System configuration controller + */ + +typedef struct +{ + __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ + __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ + __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ + uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ + +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + + +/** + * @brief LCD-TFT Display Controller + */ + +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Power Control + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */ + __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */ + __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */ +} PWR_TypeDef; + + +/** + * @brief Reset and Clock Control + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ + __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ + __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ + __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ + uint32_t RESERVED0; /*!< Reserved, 0x1C */ + __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ + __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ + uint32_t RESERVED2; /*!< Reserved, 0x3C */ + __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ + __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ + uint32_t RESERVED4; /*!< Reserved, 0x5C */ + __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ + __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ + __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ + __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ + __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ + __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ + __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */ + __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */ + +} RCC_TypeDef; + +/** + * @brief Real-Time Clock + */ + +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + uint32_t reserved; /*!< Reserved */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ + __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ + __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ + __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ + __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ + __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */ + __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */ + __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */ + __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */ + __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */ + __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */ + __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */ + __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */ + __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */ + __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */ + __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */ + __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */ +} RTC_TypeDef; + + +/** + * @brief Serial Audio Interface + */ + +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief SPDIF-RX Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */ + __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */ + __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */ + __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */ + __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */ +} SPDIFRX_TypeDef; + +/** + * @brief SD host Interface + */ + +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ + __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */ + uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief QUAD Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ + __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ + __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ + __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ + __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ + __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ + __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ + __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ + __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ + __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ +} QUADSPI_TypeDef; + +/** + * @brief TIM + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */ + __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */ + __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */ + +} TIM_TypeDef; + +/** + * @brief LPTIMIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ + +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ +} USART_TypeDef; + + +/** + * @brief Window WATCHDOG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + + +/** + * @brief RNG + */ + +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ +} RNG_TypeDef; + +/** + * @} + */ + +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + uint32_t Reserved6; /*!< Reserved 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + uint32_t Reserved7; /*!< Reserved 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */ +} USB_OTG_GlobalTypeDef; + + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} USB_OTG_OUTEndpointTypeDef; + + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved[2]; /*!< Reserved */ +} USB_OTG_HostChannelTypeDef; +/** + * @} + */ + + + + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */ +#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM */ +#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI */ +#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 64KB system data RAM accessible over DTCM */ +#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */ +#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */ +#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */ +#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */ +#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */ +#define SRAM1_BASE 0x20010000UL /*!< Base address of : 240KB RAM1 accessible over AXI/AHB */ +#define SRAM2_BASE 0x2004C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */ +#define FLASH_END 0x080FFFFFUL /*!< FLASH end address */ +#define FLASH_OTP_BASE 0x1FF0F000UL /*!< Base address of : (up to 1024 Bytes) embedded FLASH OTP Area */ +#define FLASH_OTP_END 0x1FF0F41FUL /*!< End address of : (up to 1024 Bytes) embedded FLASH OTP Area */ + +/* Legacy define */ +#define FLASH_BASE FLASHAXI_BASE + +/*!< Peripheral memory map */ +#define APB1PERIPH_BASE PERIPH_BASE +#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) +#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) +#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL) + +/*!< APB1 peripherals */ +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL) +#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL) +#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000UL) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL) +#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL) +#define I2C4_BASE (APB1PERIPH_BASE + 0x6000UL) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800UL) +#define CEC_BASE (APB1PERIPH_BASE + 0x6C00UL) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL) +#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL) +#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL) + +/*!< APB2 peripherals */ +#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL) +#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL) +#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL) +#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL) +#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL) +#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL) +#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL) +#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL) +#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL) +#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL) +#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL) +#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL) +#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL) +#define SPI6_BASE (APB2PERIPH_BASE + 0x5400UL) +#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL) +#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL) +#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL) +#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL) +#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL) +#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL) +#define LTDC_BASE (APB2PERIPH_BASE + 0x6800UL) +#define LTDC_Layer1_BASE (LTDC_BASE + 0x0084UL) +#define LTDC_Layer2_BASE (LTDC_BASE + 0x0104UL) +/*!< AHB1 peripherals */ +#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL) +#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL) +#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) +#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) +#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) +#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) +#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) +#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) +#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL) +#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400UL) +#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800UL) +#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) +#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) +#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL) +#define UID_BASE 0x1FF0F420UL /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE 0x1FF0F442UL /*!< FLASH Size register base address */ +#define PACKAGE_BASE 0x1FF0F7E0UL /*!< Package size register base address */ +/* Legacy define */ +#define PACKAGESIZE_BASE PACKAGE_BASE + +#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL) +#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL) +#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL) +#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL) +#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL) +#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL) +#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL) +#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL) +#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL) +#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL) +#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL) +#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL) +#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL) +#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL) +#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL) +#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL) +#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL) +#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL) +#define ETH_BASE (AHB1PERIPH_BASE + 0x8000UL) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100UL) +#define ETH_PTP_BASE (ETH_BASE + 0x0700UL) +#define ETH_DMA_BASE (ETH_BASE + 0x1000UL) +#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000UL) +/*!< AHB2 peripherals */ +#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000UL) +#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL) +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE 0xE0042000UL + +/*!< USB registers base address */ +#define USB_OTG_HS_PERIPH_BASE 0x40040000UL +#define USB_OTG_FS_PERIPH_BASE 0x50000000UL + +#define USB_OTG_GLOBAL_BASE 0x0000UL +#define USB_OTG_DEVICE_BASE 0x0800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL +#define USB_OTG_EP_REG_SIZE 0x0020UL +#define USB_OTG_HOST_BASE 0x0400UL +#define USB_OTG_HOST_PORT_BASE 0x0440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL +#define USB_OTG_PCGCCTL_BASE 0x0E00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define I2C4 ((I2C_TypeDef *) I2C4_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define CEC ((CEC_TypeDef *) CEC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI4 ((SPI_TypeDef *) SPI4_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define SPI5 ((SPI_TypeDef *) SPI5_BASE) +#define SPI6 ((SPI_TypeDef *) SPI6_BASE) +#define SAI1 ((SAI_TypeDef *) SAI1_BASE) +#define SAI2 ((SAI_TypeDef *) SAI2_BASE) +#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) +#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) +#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) +#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) +#define LTDC ((LTDC_TypeDef *)LTDC_BASE) +#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) +#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) +#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) +#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) +#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) +#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) +#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) +#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) +#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) +#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) +#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) +#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) +#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) +#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) +#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) +#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) +#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) +#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) +#define DCMI ((DCMI_TypeDef *) DCMI_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) +#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + + /** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ + + /** + * @} + */ + + /** @addtogroup Peripheral_Registers_Bits_Definition + * @{ + */ + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF0F44A)) /*!State = HAL_CAN_STATE_RESET) - -/** - * @brief Enable the specified CAN interrupts. - * @param __HANDLE__ CAN handle - * @param __INTERRUPT__ CAN Interrupt - * @retval None - */ -#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable the specified CAN interrupts. - * @param __HANDLE__ CAN handle - * @param __INTERRUPT__ CAN Interrupt - * @retval None - */ -#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) - -/** - * @brief Return the number of pending received messages. - * @param __HANDLE__ CAN handle - * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval The number of pending message. - */ -#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U))) - -/** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__ CAN Handle - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @arg CAN_FLAG_EWG: Error Warning Flag - * @arg CAN_FLAG_EPV: Error Passive Flag - * @arg CAN_FLAG_BOF: Bus-Off Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) - -/** @brief Clear the specified CAN pending flag. - * @param __HANDLE__ CAN Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_TSR_RQCP0: Request MailBox0 Flag - * @arg CAN_TSR_RQCP1: Request MailBox1 Flag - * @arg CAN_TSR_RQCP2: Request MailBox2 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag - * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag - * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag - * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag - * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag - * @arg CAN_FLAG_FF0: FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag - * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag - * @arg CAN_FLAG_FF1: FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKU: Wake up Flag - * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK)))) - -/** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__ CAN Handle - * @param __INTERRUPT__ specifies the CAN interrupt source to check. - * This parameter can be one of the following values: - * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable - * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable - * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** - * @brief Check the transmission status of a CAN Frame. - * @param __HANDLE__ CAN Handle - * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. - * @retval The new status of transmission (TRUE or FALSE). - */ -#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\ - ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2))) - -/** - * @brief Release the specified receive FIFO. - * @param __HANDLE__ CAN handle - * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. - * @retval None - */ -#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ -((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) - -/** - * @brief Cancel a transmit request. - * @param __HANDLE__ CAN Handle - * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission. - * @retval None - */ -#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ -(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ - ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ - ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) - -/** - * @brief Enable or disable the DBG Freeze for CAN. - * @param __HANDLE__ CAN Handle - * @param __NEWSTATE__ new state of the CAN peripheral. - * This parameter can be: ENABLE (CAN reception/transmission is frozen - * during debug. Reception FIFOs can still be accessed/controlled normally) - * or DISABLE (CAN is working during debug). - * @retval None - */ -#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ -((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions - * @{ - */ - -/** @addtogroup CAN_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); -HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); -HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); -void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); -void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ***************************************************/ -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup CAN_Private_Types CAN Private Types - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Variables CAN Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Constants CAN Private Constants - * @{ - */ -#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ -#define CAN_FLAG_MASK 0x000000FFU -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ -#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ - ((MODE) == CAN_MODE_LOOPBACK)|| \ - ((MODE) == CAN_MODE_SILENT) || \ - ((MODE) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ - ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) -#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) -#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) -#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U) -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ - ((MODE) == CAN_FILTERMODE_IDLIST)) -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ - ((SCALE) == CAN_FILTERSCALE_32BIT)) -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ - ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) - -#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) -#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) -#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) - -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ - ((IDTYPE) == CAN_ID_EXT)) -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) -#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Functions CAN Private Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CAN_LEGACY_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_eth_legacy.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_eth_legacy.h deleted file mode 100644 index a63adbc1..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/Legacy/stm32f7xx_hal_eth_legacy.h +++ /dev/null @@ -1,2212 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_eth_legacy.h - * @author MCD Application Team - * @brief Header file of ETH HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_ETH_LEGACY_H -#define __STM32F7xx_HAL_ETH_LEGACY_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (ETH) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup ETH - * @{ - */ - -/** @addtogroup ETH_Private_Macros - * @{ - */ -#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20) -#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ - ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ - ((SPEED) == ETH_SPEED_100M)) -#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ - ((MODE) == ETH_MODE_HALFDUPLEX)) -#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ - ((MODE) == ETH_RXINTERRUPT_MODE)) -#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ - ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) -#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ - ((MODE) == ETH_MEDIA_INTERFACE_RMII)) -#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ - ((CMD) == ETH_WATCHDOG_DISABLE)) -#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ - ((CMD) == ETH_JABBER_DISABLE)) -#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_40BIT)) -#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ - ((CMD) == ETH_CARRIERSENCE_DISABLE)) -#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ - ((CMD) == ETH_RECEIVEOWN_DISABLE)) -#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ - ((CMD) == ETH_LOOPBACKMODE_DISABLE)) -#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ - ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) -#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ - ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) -#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ - ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) -#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_1)) -#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ - ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) -#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ - ((CMD) == ETH_RECEIVEAll_DISABLE)) -#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) -#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) -#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ - ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) -#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ - ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) -#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ - ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) -#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) -#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) -#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF) -#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ - ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) -#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) -#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ - ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) -#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) -#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) -#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ - ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) -#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF) -#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ - ((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ - ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) -#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) -#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ - ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) -#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) -#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ - ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) -#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) -#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) -#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) -#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) -#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) -#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ - ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) -#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ - ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) -#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ - ((CMD) == ETH_FIXEDBURST_DISABLE)) -#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F) -#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ - ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) -#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ - ((FLAG) == ETH_DMATXDESC_IC) || \ - ((FLAG) == ETH_DMATXDESC_LS) || \ - ((FLAG) == ETH_DMATXDESC_FS) || \ - ((FLAG) == ETH_DMATXDESC_DC) || \ - ((FLAG) == ETH_DMATXDESC_DP) || \ - ((FLAG) == ETH_DMATXDESC_TTSE) || \ - ((FLAG) == ETH_DMATXDESC_TER) || \ - ((FLAG) == ETH_DMATXDESC_TCH) || \ - ((FLAG) == ETH_DMATXDESC_TTSS) || \ - ((FLAG) == ETH_DMATXDESC_IHE) || \ - ((FLAG) == ETH_DMATXDESC_ES) || \ - ((FLAG) == ETH_DMATXDESC_JT) || \ - ((FLAG) == ETH_DMATXDESC_FF) || \ - ((FLAG) == ETH_DMATXDESC_PCE) || \ - ((FLAG) == ETH_DMATXDESC_LCA) || \ - ((FLAG) == ETH_DMATXDESC_NC) || \ - ((FLAG) == ETH_DMATXDESC_LCO) || \ - ((FLAG) == ETH_DMATXDESC_EC) || \ - ((FLAG) == ETH_DMATXDESC_VF) || \ - ((FLAG) == ETH_DMATXDESC_CC) || \ - ((FLAG) == ETH_DMATXDESC_ED) || \ - ((FLAG) == ETH_DMATXDESC_UF) || \ - ((FLAG) == ETH_DMATXDESC_DB)) -#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ - ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) -#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) -#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF) -#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ - ((FLAG) == ETH_DMARXDESC_AFM) || \ - ((FLAG) == ETH_DMARXDESC_ES) || \ - ((FLAG) == ETH_DMARXDESC_DE) || \ - ((FLAG) == ETH_DMARXDESC_SAF) || \ - ((FLAG) == ETH_DMARXDESC_LE) || \ - ((FLAG) == ETH_DMARXDESC_OE) || \ - ((FLAG) == ETH_DMARXDESC_VLAN) || \ - ((FLAG) == ETH_DMARXDESC_FS) || \ - ((FLAG) == ETH_DMARXDESC_LS) || \ - ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ - ((FLAG) == ETH_DMARXDESC_LC) || \ - ((FLAG) == ETH_DMARXDESC_FT) || \ - ((FLAG) == ETH_DMARXDESC_RWT) || \ - ((FLAG) == ETH_DMARXDESC_RE) || \ - ((FLAG) == ETH_DMARXDESC_DBE) || \ - ((FLAG) == ETH_DMARXDESC_CE) || \ - ((FLAG) == ETH_DMARXDESC_MAMPCE)) -#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ - ((BUFFER) == ETH_DMARXDESC_BUFFER2)) -#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ - ((FLAG) == ETH_PMT_FLAG_MPR)) -#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00)) -#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ - ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ - ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ - ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ - ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ - ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ - ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ - ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ - ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ - ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ - ((FLAG) == ETH_DMA_FLAG_T)) -#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00)) -#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ - ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ - ((IT) == ETH_MAC_IT_PMT)) -#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ - ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ - ((FLAG) == ETH_MAC_FLAG_PMT)) -#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00)) -#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ - ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ - ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ - ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ - ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ - ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ - ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ - ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ - ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) -#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ - ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) -#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \ - ((IT) != 0x00)) -#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ - ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ - ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) -#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ - ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) - - -/** - * @} - */ - -/** @addtogroup ETH_Private_Defines - * @{ - */ -/* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001U) - -/* Ethernet Errors */ -#define ETH_SUCCESS ((uint32_t)0U) -#define ETH_ERROR ((uint32_t)1U) - -/* Ethernet DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3U) - -/* Ethernet DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) - -/* Ethernet DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16U) - -/* Ethernet DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16U) - -/* Ethernet DMA Rx descriptors Frame length Shift */ -#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16) - -/* Ethernet MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40U) /* Ethernet MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44U) /* Ethernet MAC address low offset */ - -/* Ethernet MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3U) - -/* Ethernet MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810FU) - -/* Ethernet MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41U) - -/* Ethernet DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23U) - -/* Ethernet Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U - -/* Ethernet Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U - /** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ETH_Exported_Types ETH Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -}HAL_ETH_StateTypeDef; - -/** - * @brief ETH Init Structure definition - */ - -typedef struct -{ - uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY - The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) - and the mode (half/full-duplex). - This parameter can be a value of @ref ETH_AutoNegotiation */ - - uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. - This parameter can be a value of @ref ETH_Speed */ - - uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode - This parameter can be a value of @ref ETH_Duplex_Mode */ - - uint16_t PhyAddress; /*!< Ethernet PHY address. - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ - - uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. - This parameter can be a value of @ref ETH_Rx_Mode */ - - uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. - This parameter can be a value of @ref ETH_Checksum_Mode */ - - uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface. - This parameter can be a value of @ref ETH_Media_Interface */ - -} ETH_InitTypeDef; - - - /** - * @brief ETH MAC Configuration Structure definition - */ - -typedef struct -{ - uint32_t Watchdog; /*!< Selects or not the Watchdog timer - When enabled, the MAC allows no more then 2048 bytes to be received. - When disabled, the MAC can receive up to 16384 bytes. - This parameter can be a value of @ref ETH_Watchdog */ - - uint32_t Jabber; /*!< Selects or not Jabber timer - When enabled, the MAC allows no more then 2048 bytes to be sent. - When disabled, the MAC can send up to 16384 bytes. - This parameter can be a value of @ref ETH_Jabber */ - - uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. - This parameter can be a value of @ref ETH_Inter_Frame_Gap */ - - uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. - This parameter can be a value of @ref ETH_Carrier_Sense */ - - uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, - ReceiveOwn allows the reception of frames when the TX_EN signal is asserted - in Half-Duplex mode. - This parameter can be a value of @ref ETH_Receive_Own */ - - uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. - This parameter can be a value of @ref ETH_Loop_Back_Mode */ - - uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. - This parameter can be a value of @ref ETH_Checksum_Offload */ - - uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, - when a collision occurs (Half-Duplex mode). - This parameter can be a value of @ref ETH_Retry_Transmission */ - - uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. - This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ - - uint32_t BackOffLimit; /*!< Selects the BackOff limit value. - This parameter can be a value of @ref ETH_Back_Off_Limit */ - - uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). - This parameter can be a value of @ref ETH_Deferral_Check */ - - uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). - This parameter can be a value of @ref ETH_Receive_All */ - - uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. - This parameter can be a value of @ref ETH_Source_Addr_Filter */ - - uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) - This parameter can be a value of @ref ETH_Pass_Control_Frames */ - - uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. - This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ - - uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. - This parameter can be a value of @ref ETH_Destination_Addr_Filter */ - - uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode - This parameter can be a value of @ref ETH_Promiscuous_Mode */ - - uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. - This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ - - uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. - This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ - - uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - - uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ - - uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. - This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ - - uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. - This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ - - uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for - automatic retransmission of PAUSE Frame. - This parameter can be a value of @ref ETH_Pause_Low_Threshold */ - - uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 - unicast address and unique multicast address). - This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ - - uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and - disable its transmitter for a specified time (Pause Time) - This parameter can be a value of @ref ETH_Receive_Flow_Control */ - - uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) - or the MAC back-pressure operation (Half-Duplex mode) - This parameter can be a value of @ref ETH_Transmit_Flow_Control */ - - uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for - comparison and filtering. - This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ - - uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ - -} ETH_MACInitTypeDef; - - -/** - * @brief ETH DMA Configuration Structure definition - */ - -typedef struct -{ - uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. - This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ - - uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. - This parameter can be a value of @ref ETH_Receive_Store_Forward */ - - uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. - This parameter can be a value of @ref ETH_Flush_Received_Frame */ - - uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. - This parameter can be a value of @ref ETH_Transmit_Store_Forward */ - - uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. - This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ - - uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. - This parameter can be a value of @ref ETH_Forward_Error_Frames */ - - uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error - and length less than 64 bytes) including pad-bytes and CRC) - This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ - - uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. - This parameter can be a value of @ref ETH_Receive_Threshold_Control */ - - uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second - frame of Transmit data even before obtaining the status for the first frame. - This parameter can be a value of @ref ETH_Second_Frame_Operate */ - - uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. - This parameter can be a value of @ref ETH_Address_Aligned_Beats */ - - uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. - This parameter can be a value of @ref ETH_Fixed_Burst */ - - uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. - This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ - - uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. - This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ - - uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. - This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ - - uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) - This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ - - uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. - This parameter can be a value of @ref ETH_DMA_Arbitration */ -} ETH_DMAInitTypeDef; - - -/** - * @brief ETH DMA Descriptors data structure definition - */ - -typedef struct -{ - __IO uint32_t Status; /*!< Status */ - - uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ - - uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ - - uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ - - /*!< Enhanced Ethernet DMA PTP Descriptors */ - uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ - - uint32_t Reserved1; /*!< Reserved */ - - uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ - - uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ - -} ETH_DMADescTypeDef; - - -/** - * @brief Received Frame Information structure definition - */ -typedef struct -{ - ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ - - ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ - - uint32_t SegCount; /*!< Segment count */ - - uint32_t length; /*!< Frame length */ - - uint32_t buffer; /*!< Frame buffer */ - -} ETH_DMARxFrameInfos; - - -/** - * @brief ETH Handle Structure definition - */ - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -typedef struct __ETH_HandleTypeDef -#else -typedef struct -#endif -{ - ETH_TypeDef *Instance; /*!< Register base address */ - - ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ - - uint32_t LinkStatus; /*!< Ethernet link status */ - - ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ - - ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ - - ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ - - __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ - - HAL_LockTypeDef Lock; /*!< ETH Lock */ - - #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - - void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ - void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ - void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */ - void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ - void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ - -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -} ETH_HandleTypeDef; - - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -/** - * @brief HAL ETH Callback ID enumeration definition - */ -typedef enum -{ - HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ - HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ - HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ - HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ - HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ - -}HAL_ETH_CallbackIDTypeDef; - -/** - * @brief HAL ETH Callback pointer definition - */ -typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ - -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ETH_Exported_Constants ETH Exported Constants - * @{ - */ - -/** @defgroup ETH_Buffers_setting ETH Buffers setting - * @{ - */ -#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ -#define ETH_EXTRA ((uint32_t)2U) /*!< Extra bytes in some cases */ -#define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ - - /* Ethernet driver receive buffers are organized in a chained linked-list, when - an Ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO - to the driver receive buffers memory. - - Depending on the size of the received Ethernet packet and the size of - each Ethernet driver receive buffer, the received packet can take one or more - Ethernet driver receive buffer. - - In below are defined the size of one Ethernet driver receive buffer ETH_RX_BUF_SIZE - and the total count of the driver receive buffers ETH_RXBUFNB. - - The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_RX_BUF_SIZE - #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ -#ifndef ETH_RXBUFNB - #define ETH_RXBUFNB ((uint32_t)5U) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ -#endif - - - /* Ethernet driver transmit buffers are organized in a chained linked-list, when - an Ethernet packet is transmitted, Tx-DMA will transfer the packet from the - driver transmit buffers memory to the TxFIFO. - - Depending on the size of the Ethernet packet to be transmitted and the size of - each Ethernet driver transmit buffer, the packet to be transmitted can take - one or more Ethernet driver transmit buffer. - - In below are defined the size of one Ethernet driver transmit buffer ETH_TX_BUF_SIZE - and the total count of the driver transmit buffers ETH_TXBUFNB. - - The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as - example, they can be reconfigured in the application layer to fit the application - needs */ - -/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet - packet */ -#ifndef ETH_TX_BUF_SIZE - #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE -#endif - -/* 5 Ethernet driver transmit buffers are used (in a chained linked list)*/ -#ifndef ETH_TXBUFNB - #define ETH_TXBUFNB ((uint32_t)5U) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ -#endif - - /** - * @} - */ - -/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor - * @{ - */ - -/* - DMA Tx Descriptor - ----------------------------------------------------------------------------------------------- - TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | - ----------------------------------------------------------------------------------------------- - TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | - ----------------------------------------------------------------------------------------------- - TDES2 | Buffer1 Address [31:0] | - ----------------------------------------------------------------------------------------------- - TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - ----------------------------------------------------------------------------------------------- -*/ - -/** - * @brief Bit definition of TDES0 register: DMA Tx descriptor status register - */ -#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMATXDESC_IC ((uint32_t)0x40000000U) /*!< Interrupt on Completion */ -#define ETH_DMATXDESC_LS ((uint32_t)0x20000000U) /*!< Last Segment */ -#define ETH_DMATXDESC_FS ((uint32_t)0x10000000U) /*!< First Segment */ -#define ETH_DMATXDESC_DC ((uint32_t)0x08000000U) /*!< Disable CRC */ -#define ETH_DMATXDESC_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ -#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000U) /*!< Transmit Time Stamp Enable */ -#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000U) /*!< Checksum Insertion Control: 4 cases */ -#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is bypassed */ -#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000U) /*!< IPV4 header Checksum Insertion */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ -#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ -#define ETH_DMATXDESC_TER ((uint32_t)0x00200000U) /*!< Transmit End of Ring */ -#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000U) /*!< Second Address Chained */ -#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000U) /*!< Tx Time Stamp Status */ -#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000U) /*!< IP Header Error */ -#define ETH_DMATXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ -#define ETH_DMATXDESC_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ -#define ETH_DMATXDESC_FF ((uint32_t)0x00002000U) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ -#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ -#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ -#define ETH_DMATXDESC_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ -#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ -#define ETH_DMATXDESC_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ -#define ETH_DMATXDESC_VF ((uint32_t)0x00000080U) /*!< VLAN Frame */ -#define ETH_DMATXDESC_CC ((uint32_t)0x00000078U) /*!< Collision Count */ -#define ETH_DMATXDESC_ED ((uint32_t)0x00000004U) /*!< Excessive Deferral */ -#define ETH_DMATXDESC_UF ((uint32_t)0x00000002U) /*!< Underflow Error: late data arrival from the memory */ -#define ETH_DMATXDESC_DB ((uint32_t)0x00000001U) /*!< Deferred Bit */ - -/** - * @brief Bit definition of TDES1 register - */ -#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000U) /*!< Transmit Buffer2 Size */ -#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFFU) /*!< Transmit Buffer1 Size */ - -/** - * @brief Bit definition of TDES2 register - */ -#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of TDES3 register - */ -#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ - - /*--------------------------------------------------------------------------------------------- - TDES6 | Transmit Time Stamp Low [31:0] | - ----------------------------------------------------------------------------------------------- - TDES7 | Transmit Time Stamp High [31:0] | - ----------------------------------------------------------------------------------------------*/ - -/* Bit definition of TDES6 register */ - #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp Low */ - -/* Bit definition of TDES7 register */ - #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFFU) /* Transmit Time Stamp High */ - -/** - * @} - */ -/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor - * @{ - */ - -/* - DMA Rx Descriptor - -------------------------------------------------------------------------------------------------------------------- - RDES0 | OWN(31) | Status [30:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES2 | Buffer1 Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | - --------------------------------------------------------------------------------------------------------------------- -*/ - -/** - * @brief Bit definition of RDES0 register: DMA Rx descriptor status register - */ -#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ -#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000U) /*!< DA Filter Fail for the rx frame */ -#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000U) /*!< Receive descriptor frame length */ -#define ETH_DMARXDESC_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ -#define ETH_DMARXDESC_DE ((uint32_t)0x00004000U) /*!< Descriptor error: no more descriptors for receive frame */ -#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000U) /*!< SA Filter Fail for the received frame */ -#define ETH_DMARXDESC_LE ((uint32_t)0x00001000U) /*!< Frame size not matching with length field */ -#define ETH_DMARXDESC_OE ((uint32_t)0x00000800U) /*!< Overflow Error: Frame was damaged due to buffer overflow */ -#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400U) /*!< VLAN Tag: received frame is a VLAN frame */ -#define ETH_DMARXDESC_FS ((uint32_t)0x00000200U) /*!< First descriptor of the frame */ -#define ETH_DMARXDESC_LS ((uint32_t)0x00000100U) /*!< Last descriptor of the frame */ -#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080U) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ -#define ETH_DMARXDESC_LC ((uint32_t)0x00000040U) /*!< Late collision occurred during reception */ -#define ETH_DMARXDESC_FT ((uint32_t)0x00000020U) /*!< Frame type - Ethernet, otherwise 802.3 */ -#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010U) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ -#define ETH_DMARXDESC_RE ((uint32_t)0x00000008U) /*!< Receive error: error reported by MII interface */ -#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004U) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ -#define ETH_DMARXDESC_CE ((uint32_t)0x00000002U) /*!< CRC error */ -#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001U) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ - -/** - * @brief Bit definition of RDES1 register - */ -#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000U) /*!< Disable Interrupt on Completion */ -#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000U) /*!< Receive Buffer2 Size */ -#define ETH_DMARXDESC_RER ((uint32_t)0x00008000U) /*!< Receive End of Ring */ -#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000U) /*!< Second Address Chained */ -#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFFU) /*!< Receive Buffer1 Size */ - -/** - * @brief Bit definition of RDES2 register - */ -#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer */ - -/** - * @brief Bit definition of RDES3 register - */ -#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ - -/*--------------------------------------------------------------------------------------------------------------------- - RDES4 | Reserved[31:15] | Extended Status [14:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES5 | Reserved[31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES6 | Receive Time Stamp Low [31:0] | - --------------------------------------------------------------------------------------------------------------------- - RDES7 | Receive Time Stamp High [31:0] | - --------------------------------------------------------------------------------------------------------------------*/ - -/* Bit definition of RDES4 register */ -#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000U) /* PTP Version */ -#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000U) /* PTP Frame Type */ -#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00U) /* PTP Message Type */ -#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100U) /* SYNC message (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200U) /* FollowUp message (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300U) /* DelayReq message (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400U) /* DelayResp message (all clock types) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500U) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600U) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700U) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ -#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080U) /* IPv6 Packet Received */ -#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040U) /* IPv4 Packet Received */ -#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020U) /* IP Checksum Bypassed */ -#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010U) /* IP Payload Error */ -#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008U) /* IP Header Error */ -#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007U) /* IP Payload Type */ -#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001U) /* UDP payload encapsulated in the IP datagram */ -#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002U) /* TCP payload encapsulated in the IP datagram */ -#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003U) /* ICMP payload encapsulated in the IP datagram */ - -/* Bit definition of RDES6 register */ -#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp Low */ - -/* Bit definition of RDES7 register */ -#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFFU) /* Receive Time Stamp High */ -/** - * @} - */ - /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation - * @{ - */ -#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001U) -#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000U) - -/** - * @} - */ -/** @defgroup ETH_Speed ETH Speed - * @{ - */ -#define ETH_SPEED_10M ((uint32_t)0x00000000U) -#define ETH_SPEED_100M ((uint32_t)0x00004000U) - -/** - * @} - */ -/** @defgroup ETH_Duplex_Mode ETH Duplex Mode - * @{ - */ -#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800U) -#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000U) -/** - * @} - */ -/** @defgroup ETH_Rx_Mode ETH Rx Mode - * @{ - */ -#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000U) -#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001U) -/** - * @} - */ - -/** @defgroup ETH_Checksum_Mode ETH Checksum Mode - * @{ - */ -#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000U) -#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001U) -/** - * @} - */ - -/** @defgroup ETH_Media_Interface ETH Media Interface - * @{ - */ -#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000U) -#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) -/** - * @} - */ - -/** @defgroup ETH_Watchdog ETH Watchdog - * @{ - */ -#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000U) -#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000U) -/** - * @} - */ - -/** @defgroup ETH_Jabber ETH Jabber - * @{ - */ -#define ETH_JABBER_ENABLE ((uint32_t)0x00000000U) -#define ETH_JABBER_DISABLE ((uint32_t)0x00400000U) -/** - * @} - */ - -/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap - * @{ - */ -#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000U) /*!< minimum IFG between frames during transmission is 96Bit */ -#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000U) /*!< minimum IFG between frames during transmission is 88Bit */ -#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000U) /*!< minimum IFG between frames during transmission is 80Bit */ -#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000U) /*!< minimum IFG between frames during transmission is 72Bit */ -#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000U) /*!< minimum IFG between frames during transmission is 64Bit */ -#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000U) /*!< minimum IFG between frames during transmission is 56Bit */ -#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000U) /*!< minimum IFG between frames during transmission is 48Bit */ -#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000U) /*!< minimum IFG between frames during transmission is 40Bit */ -/** - * @} - */ - -/** @defgroup ETH_Carrier_Sense ETH Carrier Sense - * @{ - */ -#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000U) -#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_Own ETH Receive Own - * @{ - */ -#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) -#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000U) -/** - * @} - */ - -/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode - * @{ - */ -#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000U) -#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Checksum_Offload ETH Checksum Offload - * @{ - */ -#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400U) -#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Retry_Transmission ETH Retry Transmission - * @{ - */ -#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) -#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200U) -/** - * @} - */ - -/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip - * @{ - */ -#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080U) -#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit - * @{ - */ -#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000U) -#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020U) -#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040U) -#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060U) -/** - * @} - */ - -/** @defgroup ETH_Deferral_Check ETH Deferral Check - * @{ - */ -#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010U) -#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_All ETH Receive All - * @{ - */ -#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000U) -#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter - * @{ - */ -#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200U) -#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300U) -#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames - * @{ - */ -#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040U) /*!< MAC filters all control frames from reaching the application */ -#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080U) /*!< MAC forwards all control frames to application even if they fail the Address Filter */ -#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0U) /*!< MAC forwards control frames that pass the Address Filter. */ -/** - * @} - */ - -/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception - * @{ - */ -#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000U) -#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020U) -/** - * @} - */ - -/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter - * @{ - */ -#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000U) -#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode - * @{ - */ -#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001U) -#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter - * @{ - */ -#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404U) -#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004U) -#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) -#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010U) -/** - * @} - */ - -/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter - * @{ - */ -#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402U) -#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002U) -#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause - * @{ - */ -#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000U) -#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080U) -/** - * @} - */ - -/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold - * @{ - */ -#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000U) /*!< Pause time minus 4 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010U) /*!< Pause time minus 28 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020U) /*!< Pause time minus 144 slot times */ -#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030U) /*!< Pause time minus 256 slot times */ -/** - * @} - */ - -/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect - * @{ - */ -#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008U) -#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control - * @{ - */ -#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004U) -#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control - * @{ - */ -#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002U) -#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison - * @{ - */ -#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000U) -#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses ETH MAC addresses - * @{ - */ -#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) -#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) -#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) -#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA - * @{ - */ -#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000U) -#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes - * @{ - */ -#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000U) /*!< Mask MAC Address high reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000U) /*!< Mask MAC Address high reg bits [7:0] */ -#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000U) /*!< Mask MAC Address low reg bits [31:24] */ -#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000U) /*!< Mask MAC Address low reg bits [23:16] */ -#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000U) /*!< Mask MAC Address low reg bits [15:8] */ -#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000U) /*!< Mask MAC Address low reg bits [70] */ -/** - * @} - */ - -/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame - * @{ - */ -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000U) -#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward - * @{ - */ -#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000U) -#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame - * @{ - */ -#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000U) -#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000U) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward - * @{ - */ -#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000U) -#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control - * @{ - */ -#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000U) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000U) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000U) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000U) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000U) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000U) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ -#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000U) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ -/** - * @} - */ - -/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames - * @{ - */ -#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080U) -#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames - * @{ - */ -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040U) -#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control - * @{ - */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000U) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008U) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010U) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ -#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018U) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ -/** - * @} - */ - -/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate - * @{ - */ -#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004U) -#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats - * @{ - */ -#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000U) -#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Fixed_Burst ETH Fixed Burst - * @{ - */ -#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000U) -#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length - * @{ - */ -#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ -#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ -#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ -#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000U) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ -/** - * @} - */ - -/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length - * @{ - */ -#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ -#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ -#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ -#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000U) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format - * @{ - */ -#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080U) -#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration - * @{ - */ -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000U) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000U) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000U) -#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000U) -#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment - * @{ - */ -#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000U) /*!< Last Segment */ -#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000U) /*!< First Segment */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control - * @{ - */ -#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000U) /*!< Checksum engine bypass */ -#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000U) /*!< IPv4 header checksum insertion */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000U) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ -#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000U) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers - * @{ - */ -#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000U) /*!< DMA Rx Desc Buffer1 */ -#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001U) /*!< DMA Rx Desc Buffer2 */ -/** - * @} - */ - -/** @defgroup ETH_PMT_Flags ETH PMT Flags - * @{ - */ -#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000U) /*!< Wake-Up Frame Filter Register Pointer Reset */ -#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040U) /*!< Wake-Up Frame Received */ -#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020U) /*!< Magic Packet Received */ -/** - * @} - */ - -/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts - * @{ - */ -#define ETH_MMC_IT_TGF ((uint32_t)0x00200000U) /*!< When Tx good frame counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000U) /*!< When Tx good multi col counter reaches half the maximum value */ -#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000U) /*!< When Tx good single col counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts - * @{ - */ -#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000U) /*!< When Rx good unicast frames counter reaches half the maximum value */ -#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040U) /*!< When Rx alignment error counter reaches half the maximum value */ -#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020U) /*!< When Rx crc error counter reaches half the maximum value */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Flags ETH MAC Flags - * @{ - */ -#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger flag (on MAC) */ -#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit flag */ -#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020U) /*!< MMC receive flag */ -#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010U) /*!< MMC flag (on MAC) */ -#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008U) /*!< PMT flag (on MAC) */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Flags ETH DMA Flags - * @{ - */ -#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000U) /*!< Error bits 0-Rx DMA, 1-Tx DMA */ -#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000U) /*!< Error bits 0-write transfer, 1-read transfer */ -#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000U) /*!< Error bits 0-data buffer, 1-desc. access */ -#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary flag */ -#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary flag */ -#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000U) /*!< Early receive flag */ -#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error flag */ -#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400U) /*!< Early transmit flag */ -#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout flag */ -#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped flag */ -#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable flag */ -#define ETH_DMA_FLAG_R ((uint32_t)0x00000040U) /*!< Receive flag */ -#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020U) /*!< Underflow flag */ -#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010U) /*!< Overflow flag */ -#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout flag */ -#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable flag */ -#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped flag */ -#define ETH_DMA_FLAG_T ((uint32_t)0x00000001U) /*!< Transmit flag */ -/** - * @} - */ - -/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts - * @{ - */ -#define ETH_MAC_IT_TST ((uint32_t)0x00000200U) /*!< Time stamp trigger interrupt (on MAC) */ -#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040U) /*!< MMC transmit interrupt */ -#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020U) /*!< MMC receive interrupt */ -#define ETH_MAC_IT_MMC ((uint32_t)0x00000010U) /*!< MMC interrupt (on MAC) */ -#define ETH_MAC_IT_PMT ((uint32_t)0x00000008U) /*!< PMT interrupt (on MAC) */ -/** - * @} - */ - -/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts - * @{ - */ -#define ETH_DMA_IT_TST ((uint32_t)0x20000000U) /*!< Time-stamp trigger interrupt (on DMA) */ -#define ETH_DMA_IT_PMT ((uint32_t)0x10000000U) /*!< PMT interrupt (on DMA) */ -#define ETH_DMA_IT_MMC ((uint32_t)0x08000000U) /*!< MMC interrupt (on DMA) */ -#define ETH_DMA_IT_NIS ((uint32_t)0x00010000U) /*!< Normal interrupt summary */ -#define ETH_DMA_IT_AIS ((uint32_t)0x00008000U) /*!< Abnormal interrupt summary */ -#define ETH_DMA_IT_ER ((uint32_t)0x00004000U) /*!< Early receive interrupt */ -#define ETH_DMA_IT_FBE ((uint32_t)0x00002000U) /*!< Fatal bus error interrupt */ -#define ETH_DMA_IT_ET ((uint32_t)0x00000400U) /*!< Early transmit interrupt */ -#define ETH_DMA_IT_RWT ((uint32_t)0x00000200U) /*!< Receive watchdog timeout interrupt */ -#define ETH_DMA_IT_RPS ((uint32_t)0x00000100U) /*!< Receive process stopped interrupt */ -#define ETH_DMA_IT_RBU ((uint32_t)0x00000080U) /*!< Receive buffer unavailable interrupt */ -#define ETH_DMA_IT_R ((uint32_t)0x00000040U) /*!< Receive interrupt */ -#define ETH_DMA_IT_TU ((uint32_t)0x00000020U) /*!< Underflow interrupt */ -#define ETH_DMA_IT_RO ((uint32_t)0x00000010U) /*!< Overflow interrupt */ -#define ETH_DMA_IT_TJT ((uint32_t)0x00000008U) /*!< Transmit jabber timeout interrupt */ -#define ETH_DMA_IT_TBU ((uint32_t)0x00000004U) /*!< Transmit buffer unavailable interrupt */ -#define ETH_DMA_IT_TPS ((uint32_t)0x00000002U) /*!< Transmit process stopped interrupt */ -#define ETH_DMA_IT_T ((uint32_t)0x00000001U) /*!< Transmit interrupt */ -/** - * @} - */ - -/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state - * @{ - */ -#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Tx Command issued */ -#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000U) /*!< Running - fetching the Tx descriptor */ -#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000U) /*!< Running - waiting for status */ -#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000U) /*!< Running - reading the data from host memory */ -#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000U) /*!< Suspended - Tx Descriptor unavailable */ -#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000U) /*!< Running - closing Rx descriptor */ - -/** - * @} - */ - - -/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state - * @{ - */ -#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000U) /*!< Stopped - Reset or Stop Rx Command issued */ -#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000U) /*!< Running - fetching the Rx descriptor */ -#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000U) /*!< Running - waiting for packet */ -#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000U) /*!< Suspended - Rx Descriptor unavailable */ -#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000U) /*!< Running - closing descriptor */ -#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000U) /*!< Running - queuing the receive frame into host memory */ - -/** - * @} - */ - -/** @defgroup ETH_DMA_overflow ETH DMA overflow - * @{ - */ -#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000U) /*!< Overflow bit for FIFO overflow counter */ -#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000U) /*!< Overflow bit for missed frame counter */ -/** - * @} - */ - -/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP - * @{ - */ -#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000U) /*!< External interrupt line 19 Connected to the ETH EXTI Line */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ETH_Exported_Macros ETH Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ - -/** @brief Reset ETH handle state - * @param __HANDLE__ specifies the ETH handle. - * @retval None - */ -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) -#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of TDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of RDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) - -/** - * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) - -/** - * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) - -/** - * @brief Returns the specified Ethernet DMA Tx Desc collision count. - * @param __HANDLE__ ETH Handle - * @retval The Transmit descriptor collision counter value. - */ -#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) - -/** - * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) - -/** - * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) - -/** - * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) - -/** - * @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion. - * @param __HANDLE__ ETH Handle - * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. - * This parameter can be one of the following values: - * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass - * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) - -/** - * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) - -/** - * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) - -/** - * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) - -/** - * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) - -/** - * @brief Enables the specified Ethernet MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) - -/** - * @brief Disables the specified Ethernet MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) - -/** - * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the Ethernet flow control busy bit is set or not. - * @param __HANDLE__ ETH Handle - * @retval The new state of flow control busy status bit (SET or RESET). - */ -#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) - -/** - * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the specified Ethernet MAC flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The state of Ethernet MAC flag. - */ -#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Enables the specified Ethernet DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be - * enabled @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) - -/** - * @brief Disables the specified Ethernet DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be - * disabled. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) - -/** - * @brief Clears the Ethernet DMA IT pending bit. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) - -/** - * @brief Checks whether the specified Ethernet DMA flag is set or not. -* @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Checks whether the specified Ethernet DMA flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) - -/** - * @brief Checks whether the specified Ethernet DMA overflow flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __OVERFLOW__ specifies the DMA overflow flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter - * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The state of Ethernet DMA overflow Flag (SET or RESET). - */ -#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) - -/** - * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__ ETH Handle - * @param __VALUE__ DMA Receive status watchdog timer register value - * @retval None - */ -#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) - -/** - * @brief Enables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) - -/** - * @brief Disables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) - -/** - * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) - -/** - * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) - -/** - * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) - -/** - * @brief Disables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) - -/** - * @brief Checks whether the specified Ethernet PMT flag is set or not. - * @param __HANDLE__ ETH Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of Ethernet PMT Flag (SET or RESET). - */ -#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) - -/** - * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ - (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) - -/** - * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) - -/** - * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) - -/** - * @brief Enables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) - -/** - * @brief Disables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) - -/** - * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) - -/** - * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) - -/** - * @brief Resets the MMC Counters. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) - -/** - * @brief Enables the specified Ethernet MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF) -/** - * @brief Disables the specified Ethernet MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF) -/** - * @brief Enables the specified Ethernet MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) - -/** - * @brief Disables the specified Ethernet MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) - -/** - * @brief Enables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disables the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enable event on ETH External event line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disable event on ETH External event line - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Get flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Clear flag of the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP - -/** - * @brief Disables the rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Disables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ - }while(0) - -/** - * @brief Disables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - }while(0) - -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP - -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup ETH_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ - -/** @addtogroup ETH_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* IO operation functions ****************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); -/* Communication with PHY functions*/ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); -/* Callback in non blocking modes (Interrupt) */ -void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ - -/** @addtogroup ETH_Exported_Functions_Group3 - * @{ - */ - -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ - -/** @addtogroup ETH_Exported_Functions_Group4 - * @{ - */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* ETH */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_ETH_LEGACY_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h deleted file mode 100644 index 474c9e6a..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32_assert_template.h +++ /dev/null @@ -1,56 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_assert.h - * @author MCD Application Team - * @brief STM32 assert template file. - * This file should be copied to the application folder and renamed - * to stm32_assert.h. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_ASSERT_H -#define __STM32_ASSERT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Includes ------------------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32_ASSERT_H */ - - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h index 9beac832..8606b7b3 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal.h @@ -1,275 +1,275 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_H -#define __STM32F7xx_HAL_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_conf.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Constants HAL Exported Constants - * @{ - */ - -/** @defgroup HAL_TICK_FREQ Tick Frequency - * @{ - */ -typedef enum -{ - HAL_TICK_FREQ_10HZ = 100U, - HAL_TICK_FREQ_100HZ = 10U, - HAL_TICK_FREQ_1KHZ = 1U, - HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ -} HAL_TickFreqTypeDef; -/** - * @} - */ - -/** @defgroup SYSCFG_BootMode Boot Mode - * @{ - */ -#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U) -#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup HAL_Exported_Macros HAL Exported Macros - * @{ - */ - -/** @brief Freeze/Unfreeze Peripherals in Debug mode - */ -#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) -#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) -#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) -#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) - -#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) -#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) -#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) -#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) - - -/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC)) - - -/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000 - */ -#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\ - SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\ - }while(0); -/** - * @brief Return the memory boot mapping as configured by user. - * @retval The boot mode as configured by user. The returned value can be one - * of the following values: - * @arg @ref SYSCFG_MEM_BOOT_ADD0 - * @arg @ref SYSCFG_MEM_BOOT_ADD1 - */ -#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT) - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @brief SYSCFG Break Cortex-M7 Lockup lock. - * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL) - -/** @brief SYSCFG Break PVD lock. - * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL) -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** @defgroup HAL_Private_Macros HAL Private Macros - * @{ - */ -#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ - ((FREQ) == HAL_TICK_FREQ_100HZ) || \ - ((FREQ) == HAL_TICK_FREQ_1KHZ)) -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Functions - * @{ - */ -/** @addtogroup HAL_Exported_Functions_Group1 - * @{ - */ -/* Initialization and Configuration functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); -/** - * @} - */ - - /* Exported variables ---------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Variables - * @{ - */ -extern __IO uint32_t uwTick; -extern uint32_t uwTickPrio; -extern HAL_TickFreqTypeDef uwTickFreq; -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); -HAL_TickFreqTypeDef HAL_GetTickFreq(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); -void HAL_DBGMCU_EnableDBGSleepMode(void); -void HAL_DBGMCU_DisableDBGSleepMode(void); -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); -void HAL_EnableCompensationCell(void); -void HAL_DisableCompensationCell(void); -void HAL_EnableFMCMemorySwapping(void); -void HAL_DisableFMCMemorySwapping(void); -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -void HAL_EnableMemorySwappingBank(void); -void HAL_DisableMemorySwappingBank(void); -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Variables HAL Private Variables - * @{ - */ -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Constants HAL Private Constants - * @{ - */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_H */ - - +/** + ****************************************************************************** + * @file stm32f7xx_hal.h + * @author MCD Application Team + * @brief This file contains all the functions prototypes for the HAL + * module driver. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_H +#define __STM32F7xx_HAL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_conf.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup HAL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Constants HAL Exported Constants + * @{ + */ + +/** @defgroup HAL_TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + HAL_TICK_FREQ_10HZ = 100U, + HAL_TICK_FREQ_100HZ = 10U, + HAL_TICK_FREQ_1KHZ = 1U, + HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ +} HAL_TickFreqTypeDef; +/** + * @} + */ + +/** @defgroup SYSCFG_BootMode Boot Mode + * @{ + */ +#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U) +#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ + +/** @brief Freeze/Unfreeze Peripherals in Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_FREEZE_WWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_IWDG() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_FREEZE_CAN1() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_FREEZE_CAN2() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM9() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM10() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_FREEZE_TIM11() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + +#define __HAL_DBGMCU_UNFREEZE_TIM2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM3() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM4() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM5() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM6() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM7() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM12() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM13() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM14() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) +#define __HAL_DBGMCU_UNFREEZE_LPTIM1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_RTC() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) +#define __HAL_DBGMCU_UNFREEZE_WWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_IWDG() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)) +#define __HAL_DBGMCU_UNFREEZE_CAN1() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_CAN2() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM1() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM8() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM9() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM10() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP)) +#define __HAL_DBGMCU_UNFREEZE_TIM11() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP)) + + +/** @brief FMC (NOR/RAM) mapped at 0x60000000 and SDRAM mapped at 0xC0000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC)) + + +/** @brief FMC/SDRAM mapped at 0x60000000 (NOR/RAM) mapped at 0xC0000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\ + SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\ + }while(0); +/** + * @brief Return the memory boot mapping as configured by user. + * @retval The boot mode as configured by user. The returned value can be one + * of the following values: + * @arg @ref SYSCFG_MEM_BOOT_ADD0 + * @arg @ref SYSCFG_MEM_BOOT_ADD1 + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT) + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief SYSCFG Break Cortex-M7 Lockup lock. + * Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL) + +/** @brief SYSCFG Break PVD lock. + * Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. + * @note The selected configuration is locked and can be unlocked only by system reset. + */ +#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** @defgroup HAL_Private_Macros HAL Private Macros + * @{ + */ +#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ + ((FREQ) == HAL_TICK_FREQ_100HZ) || \ + ((FREQ) == HAL_TICK_FREQ_1KHZ)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Functions + * @{ + */ +/** @addtogroup HAL_Exported_Functions_Group1 + * @{ + */ +/* Initialization and Configuration functions ******************************/ +HAL_StatusTypeDef HAL_Init(void); +HAL_StatusTypeDef HAL_DeInit(void); +void HAL_MspInit(void); +void HAL_MspDeInit(void); +HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); +/** + * @} + */ + + /* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +extern __IO uint32_t uwTick; +extern uint32_t uwTickPrio; +extern HAL_TickFreqTypeDef uwTickFreq; +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_IncTick(void); +void HAL_Delay(uint32_t Delay); +uint32_t HAL_GetTick(void); +uint32_t HAL_GetTickPrio(void); +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); +HAL_TickFreqTypeDef HAL_GetTickFreq(void); +void HAL_SuspendTick(void); +void HAL_ResumeTick(void); +uint32_t HAL_GetHalVersion(void); +uint32_t HAL_GetREVID(void); +uint32_t HAL_GetDEVID(void); +uint32_t HAL_GetUIDw0(void); +uint32_t HAL_GetUIDw1(void); +uint32_t HAL_GetUIDw2(void); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_EnableCompensationCell(void); +void HAL_DisableCompensationCell(void); +void HAL_EnableFMCMemorySwapping(void); +void HAL_DisableFMCMemorySwapping(void); +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +void HAL_EnableMemorySwappingBank(void); +void HAL_DisableMemorySwappingBank(void); +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Variables HAL Private Variables + * @{ + */ +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup HAL_Private_Constants HAL Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_H */ + + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h index d2279172..ff8d3519 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc.h @@ -1,957 +1,957 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_adc.h - * @author MCD Application Team - * @brief Header file of ADC HAL extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_ADC_H -#define STM32F7xx_ADC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADC_Exported_Types ADC Exported Types - * @{ - */ - -/** - * @brief Structure definition of ADC and regular group initialization - * @note Parameters of this structure are shared within 2 scopes: - * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. - * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. - * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled - * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. - * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). - */ -typedef struct -{ - uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for - all the ADCs. - This parameter can be a value of @ref ADC_ClockPrescaler */ - uint32_t Resolution; /*!< Configures the ADC resolution. - This parameter can be a value of @ref ADC_Resolution */ - uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) - or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). - This parameter can be a value of @ref ADC_Data_Align */ - uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. - This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. - If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). - Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). - If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). - Scan direction is upward: from rank1 to rank 'n'. - This parameter can be a value of @ref ADC_Scan_mode. - This parameter can be set to ENABLE or DISABLE */ - uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. - This parameter can be a value of @ref ADC_EOCSelection. - Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. - Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) - or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. - Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). - If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ - uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, - after the selected trigger occurred (software start or external trigger). - This parameter can be set to ENABLE or DISABLE. */ - uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. - To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ - FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. */ - uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. - If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. - This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ - uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. - If set to ADC_SOFTWARE_START, external triggers are disabled. - If set to external trigger source, triggering is on event rising edge by default. - This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ - uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. - If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. - This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ - FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) - or in Continuous mode (DMA transfer unlimited, whatever number of conversions). - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). - This parameter can be set to ENABLE or DISABLE. */ -}ADC_InitTypeDef; - - - -/** - * @brief Structure definition of ADC channel for regular group - * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. - * ADC can be either disabled or enabled without conversion on going on regular group. - */ -typedef struct -{ - uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. - This parameter can be a value of @ref ADC_channels */ - uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 - This parameter can be a value of @ref ADC_regular_rank */ - uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times - Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. - If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ - uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ -}ADC_ChannelConfTypeDef; - -/** - * @brief ADC Configuration multi-mode structure definition - */ -typedef struct -{ - uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. - This parameter can be a value of @ref ADC_analog_watchdog_selection */ - uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. - This parameter must be a 12-bit value. */ - uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. - This parameter must be a 12-bit value. */ - uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. - This parameter has an effect only if watchdog mode is configured on single channel - This parameter can be a value of @ref ADC_channels */ - FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured - is interrupt mode or in polling mode. - This parameter can be set to ENABLE or DISABLE */ - uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ -}ADC_AnalogWDGConfTypeDef; - -/** - * @brief HAL ADC state machine: ADC states definition (bitfields) - */ -/* States of ADC global scope */ -#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ -#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */ - -/* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */ - -/* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */ - -/* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, - external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ -#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */ - -/* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */ - -/* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */ - - -/** - * @brief ADC handle Structure definition - */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -typedef struct __ADC_HandleTypeDef -#else -typedef struct -#endif -{ - ADC_TypeDef *Instance; /*!< Register base address */ - - ADC_InitTypeDef Init; /*!< ADC required parameters */ - - __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ - - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - - HAL_LockTypeDef Lock; /*!< ADC locking object */ - - __IO uint32_t State; /*!< ADC communication state */ - - __IO uint32_t ErrorCode; /*!< ADC Error code */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ - void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ - void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ - void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ - void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ - void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ - void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -}ADC_HandleTypeDef; - - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL ADC Callback ID enumeration definition - */ -typedef enum -{ - HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ - HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ - HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ - HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ - HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ - HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ - HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ -} HAL_ADC_CallbackIDTypeDef; - -/** - * @brief HAL ADC Callback pointer definition - */ -typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ - -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ADC_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_Error_Code ADC Error Code - * @{ - */ -#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking, - enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -/** - * @} - */ - - -/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler - * @{ - */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U) -#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) -#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) -#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) -/** - * @} - */ - -/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases - * @{ - */ -#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U) -#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) -#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) -#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) -#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) -#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) -#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) -#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) -#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) -#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) -#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) -#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) -#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) -#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) -#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) -#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) -/** - * @} - */ - -/** @defgroup ADC_Resolution ADC Resolution - * @{ - */ -#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) -#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) -#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) -#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) -/** - * @} - */ - -/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular - * @{ - */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) -#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) -#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) -/** - * @} - */ - -/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular - * @{ - */ -/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ -/* compatibility with other STM32 devices. */ - - -#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U) -#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) -#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) -#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2) -#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) -#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3) -#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) -#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) -#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) -#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) - -#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL) -#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1) - -/** - * @} - */ - -/** @defgroup ADC_Data_Align ADC Data Align - * @{ - */ -#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) -#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) -/** - * @} - */ - -/** @defgroup ADC_Scan_mode ADC sequencer scan mode - * @{ - */ -#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */ -#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */ -/** - * @} - */ - -/** @defgroup ADC_regular_rank ADC group regular sequencer rank - * @{ - */ -#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */ -#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */ -#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */ -#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */ -#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */ -#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */ -#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */ -#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */ -#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */ -#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */ -#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */ -#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */ -#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */ -#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */ -#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */ -#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */ -/** - * @} - */ - -/** @defgroup ADC_channels ADC Common Channels - * @{ - */ -#define ADC_CHANNEL_0 ((uint32_t)0x00000000U) -#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) -#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) -#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) -#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) -#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) -#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) -#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) -#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) -#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) -#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) -#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) -#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) -#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) -#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) -#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) -#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) -#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) - -#define ADC_INTERNAL_NONE 0x80000000U -#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) -#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) -#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U)) -/** - * @} - */ - -/** @defgroup ADC_sampling_times ADC Sampling Times - * @{ - */ -#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U) -#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) -#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) -#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) -#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) -#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) -#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) -#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) -/** - * @} - */ - - /** @defgroup ADC_EOCSelection ADC EOC Selection - * @{ - */ -#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U) -#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U) -#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */ -/** - * @} - */ - -/** @defgroup ADC_Event_type ADC Event Type - * @{ - */ -#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) -#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection - * @{ - */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) -#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) -#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) -#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) -#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U) -/** - * @} - */ - -/** @defgroup ADC_interrupts_definition ADC Interrupts Definition - * @{ - */ -#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) -#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) -#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) -#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) -/** - * @} - */ - -/** @defgroup ADC_flags_definition ADC Flags Definition - * @{ - */ -#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) -#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) -#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) -#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) -#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) -#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) -/** - * @} - */ - -/** @defgroup ADC_channels_type ADC Channels Type - * @{ - */ -#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U) -#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */ -#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ADC_Exported_Macros ADC Exported Macros - * @{ - */ - -/** @brief Reset ADC handle state - * @param __HANDLE__ ADC handle - * @retval None - */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - do{ \ - (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - ((__HANDLE__)->State = HAL_ADC_STATE_RESET) -#endif - -/** - * @brief Enable the ADC peripheral. - * @param __HANDLE__ ADC handle - * @retval None - */ -#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) - -/** - * @brief Disable the ADC peripheral. - * @param __HANDLE__ ADC handle - * @retval None - */ -#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) - -/** - * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__ specifies the ADC Handle. - * @param __INTERRUPT__ ADC Interrupt. - * @retval None - */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) - -/** - * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__ specifies the ADC Handle. - * @param __INTERRUPT__ ADC interrupt. - * @retval None - */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) - -/** @brief Check if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__ specifies the ADC Handle. - * @param __INTERRUPT__ specifies the ADC interrupt source to check. - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Clear the ADC's pending flags. - * @param __HANDLE__ specifies the ADC Handle. - * @param __FLAG__ ADC flag. - * @retval None - */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) - -/** - * @brief Get the selected ADC's flag status. - * @param __HANDLE__ specifies the ADC Handle. - * @param __FLAG__ ADC flag. - * @retval None - */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** - * @} - */ - -/* Include ADC HAL Extension module */ -#include "stm32f7xx_hal_adc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup ADC_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); - -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); - -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); - -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); - -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); - -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); - -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); -/** - * @} - */ - -/** @addtogroup ADC_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); -/** - * @} - */ - -/** @addtogroup ADC_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State functions ***************************************************/ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup ADC_Private_Constants ADC Private Constants - * @{ - */ -/* Delay for ADC stabilization time. */ -/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ -/* Unit: us */ -#define ADC_STAB_DELAY_US ((uint32_t) 3U) -/* Delay for temperature sensor stabilization time. */ -/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ -/* Unit: us */ -#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in - code of final user */ - -/** - * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__ ADC handle - * @retval SET (ADC enabled) or RESET (ADC disabled) - */ -#define ADC_IS_ENABLE(__HANDLE__) \ - ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ - ) ? SET : RESET) - -/** - * @brief Test if conversion trigger of regular group is software start - * or external trigger. - * @param __HANDLE__ ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - -/** - * @brief Test if conversion trigger of injected group is software start - * or external trigger. - * @param __HANDLE__ ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ - (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) - -/** - * @brief Simultaneously clears and sets specific bits of the handle State - * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), - * the first parameter is the ADC handle State, the second parameter is the - * bit field to clear, the third and last parameter is the bit field to set. - * @retval None - */ -#define ADC_STATE_CLR_SET MODIFY_REG - -/** - * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__ ADC handle - * @retval None - */ -#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ - ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ - ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ - ((CHANNEL) == ADC_INTERNAL_NONE)) -#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ - ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8)) -#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ - ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES)) -#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ - ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ - ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ - ((__RESOLUTION__) == ADC_RESOLUTION_6B)) -#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ - ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) -#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ - ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ - ((__REGTRIG__) == ADC_SOFTWARE_START)) -#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ - ((__ALIGN__) == ADC_DATAALIGN_LEFT)) - - -#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \ - ((__TIME__) == ADC_SAMPLETIME_480CYCLES)) -#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \ - ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \ - ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV)) -#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \ - ((__EVENT__) == ADC_OVR_EVENT)) -#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ - ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE)) -#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ - ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ - ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) - -#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_2 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_3 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_4 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_5 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_6 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_7 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_8 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_9 ) || \ - ((__RANK__) == ADC_REGULAR_RANK_10) || \ - ((__RANK__) == ADC_REGULAR_RANK_11) || \ - ((__RANK__) == ADC_REGULAR_RANK_12) || \ - ((__RANK__) == ADC_REGULAR_RANK_13) || \ - ((__RANK__) == ADC_REGULAR_RANK_14) || \ - ((__RANK__) == ADC_REGULAR_RANK_15) || \ - ((__RANK__) == ADC_REGULAR_RANK_16)) - -#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ - ((__SCAN_MODE__) == ADC_SCAN_ENABLE)) - -#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF)) -#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) -#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8))) -#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ - ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \ - (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))) - -/** - * @brief Set ADC Regular channel sequence length. - * @param _NbrOfConversion_ Regular channel sequence length. - * @retval None - */ -#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) - -/** - * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_ Sample time parameter. - * @param _CHANNELNB_ Channel number. - * @retval None - */ -#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) - -/** - * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_ Sample time parameter. - * @param _CHANNELNB_ Channel number. - * @retval None - */ -#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_))))) - -/** - * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_ Channel number. - * @param _RANKNB_ Rank number. - * @retval None - */ -#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) - -/** - * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_ Channel number. - * @param _RANKNB_ Rank number. - * @retval None - */ -#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) - -/** - * @brief Set the selected regular channel rank for rank between 13 and 16. - * @param _CHANNELNB_ Channel number. - * @param _RANKNB_ Rank number. - * @retval None - */ -#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) - -/** - * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_ Continuous mode. - * @retval None - */ -#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) - -/** - * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. - * @retval None - */ -#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos) - -/** - * @brief Enable ADC scan mode. - * @param _SCANCONV_MODE_ Scan conversion mode. - * @retval None - */ -#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) - -/** - * @brief Enable the ADC end of conversion selection. - * @param _EOCSelection_MODE_ End of conversion selection mode. - * @retval None - */ -#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) - -/** - * @brief Enable the ADC DMA continuous request. - * @param _DMAContReq_MODE_ DMA continuous request mode. - * @retval None - */ -#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) - -/** - * @brief Return resolution bits in CR1 register. - * @param __HANDLE__ ADC handle - * @retval None - */ -#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_ADC_H */ - - +/** + ****************************************************************************** + * @file stm32f7xx_hal_adc.h + * @author MCD Application Team + * @brief Header file of ADC HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_ADC_H +#define STM32F7xx_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief Structure definition of ADC and regular group initialization + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. + * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. + * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. + * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for + all the ADCs. + This parameter can be a value of @ref ADC_ClockPrescaler */ + uint32_t Resolution; /*!< Configures the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) + or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). + This parameter can be a value of @ref ADC_Data_Align */ + uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). + Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). + Scan direction is upward: from rank1 to rank 'n'. + This parameter can be a value of @ref ADC_Scan_mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. + This parameter can be a value of @ref ADC_EOCSelection. + Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. + Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) + or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. + Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). + If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ + uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, + after the selected trigger occurred (software start or external trigger). + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. + To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ + FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. + If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ + uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. + If set to ADC_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge by default. + This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ + uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. + If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ + FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). + This parameter can be set to ENABLE or DISABLE. */ +}ADC_InitTypeDef; + + + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC can be either disabled or enabled without conversion on going on regular group. + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels */ + uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 + This parameter can be a value of @ref ADC_regular_rank */ + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ +}ADC_ChannelConfTypeDef; + +/** + * @brief ADC Configuration multi-mode structure definition + */ +typedef struct +{ + uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. + This parameter can be a value of @ref ADC_analog_watchdog_selection */ + uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a 12-bit value. */ + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a 12-bit value. */ + uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. + This parameter has an effect only if watchdog mode is configured on single channel + This parameter can be a value of @ref ADC_channels */ + FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured + is interrupt mode or in polling mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ +}ADC_AnalogWDGConfTypeDef; + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */ + + +/** + * @brief ADC handle Structure definition + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +typedef struct __ADC_HandleTypeDef +#else +typedef struct +#endif +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC required parameters */ + + __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO uint32_t State; /*!< ADC communication state */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +}ADC_HandleTypeDef; + + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + + +/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler + * @{ + */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U) +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) +#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) +#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) +/** + * @} + */ + +/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases + * @{ + */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U) +#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) +#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) +#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) +#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) +#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) +/** + * @} + */ + +/** @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) +#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) +#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) +#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) +#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular + * @{ + */ +/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ +/* compatibility with other STM32 devices. */ + + +#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U) +#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) +#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) +#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2) +#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) +#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3) +#define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) +#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) +#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) + +#define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL) +#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1) + +/** + * @} + */ + +/** @defgroup ADC_Data_Align ADC Data Align + * @{ + */ +#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) +#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) +/** + * @} + */ + +/** @defgroup ADC_Scan_mode ADC sequencer scan mode + * @{ + */ +#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */ +#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */ +/** + * @} + */ + +/** @defgroup ADC_regular_rank ADC group regular sequencer rank + * @{ + */ +#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */ +#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */ +#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */ +#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */ +#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */ +#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */ +#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */ +#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */ +#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */ +#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */ +#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */ +#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */ +#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */ +#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */ +#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */ +#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_channels ADC Common Channels + * @{ + */ +#define ADC_CHANNEL_0 ((uint32_t)0x00000000U) +#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) +#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) +#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) +#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) +#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) +#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) + +#define ADC_INTERNAL_NONE 0x80000000U +#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) +#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)(ADC_CHANNEL_18 | 0x10000000U)) +/** + * @} + */ + +/** @defgroup ADC_sampling_times ADC Sampling Times + * @{ + */ +#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U) +#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) +#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) +#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) +#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) +#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) +#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) +#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) +/** + * @} + */ + + /** @defgroup ADC_EOCSelection ADC EOC Selection + * @{ + */ +#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U) +#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U) +#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */ +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event Type + * @{ + */ +#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) +#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection + * @{ + */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) +#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U) +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition ADC Interrupts Definition + * @{ + */ +#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) +#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) +#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) +#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC Flags Definition + * @{ + */ +#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) +#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) +#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) +#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) +#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) +#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) +/** + * @} + */ + +/** @defgroup ADC_channels_type ADC Channels Type + * @{ + */ +#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U) +#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */ +#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @brief Reset ADC handle state + * @param __HANDLE__ ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif + +/** + * @brief Enable the ADC peripheral. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) + +/** + * @brief Disable the ADC peripheral. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) + +/** + * @brief Enable the ADC end of conversion interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC Interrupt. + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) + +/** + * @brief Disable the ADC end of conversion interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC interrupt. + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) + +/** @brief Check if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ specifies the ADC interrupt source to check. + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clear the ADC's pending flags. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. + * @retval None + */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) + +/** + * @brief Get the selected ADC's flag status. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. + * @retval None + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @} + */ + +/* Include ADC HAL Extension module */ +#include "stm32f7xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); + +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); + +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); + +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); + +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); + +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions ***************************************************/ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ +/* Delay for ADC stabilization time. */ +/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ +/* Unit: us */ +#define ADC_STAB_DELAY_US ((uint32_t) 3U) +/* Delay for temperature sensor stabilization time. */ +/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ +/* Unit: us */ +#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in + code of final user */ + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__ ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +#define ADC_IS_ENABLE(__HANDLE__) \ + ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + +/** + * @brief Test if conversion trigger of injected group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) + +/** + * @brief Simultaneously clears and sets specific bits of the handle State + * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Clear ADC error code (set it to error code: "no error") + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ + ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ + ((CHANNEL) == ADC_INTERNAL_NONE)) +#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8)) +#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ + ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES)) +#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ + ((__RESOLUTION__) == ADC_RESOLUTION_6B)) +#define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) +#define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \ + ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \ + ((__REGTRIG__) == ADC_SOFTWARE_START)) +#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ + ((__ALIGN__) == ADC_DATAALIGN_LEFT)) + + +#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \ + ((__TIME__) == ADC_SAMPLETIME_480CYCLES)) +#define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \ + ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \ + ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV)) +#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \ + ((__EVENT__) == ADC_OVR_EVENT)) +#define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ + ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE)) +#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ + ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ + ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) + +#define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_2 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_3 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_4 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_5 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_6 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_7 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_8 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_9 ) || \ + ((__RANK__) == ADC_REGULAR_RANK_10) || \ + ((__RANK__) == ADC_REGULAR_RANK_11) || \ + ((__RANK__) == ADC_REGULAR_RANK_12) || \ + ((__RANK__) == ADC_REGULAR_RANK_13) || \ + ((__RANK__) == ADC_REGULAR_RANK_14) || \ + ((__RANK__) == ADC_REGULAR_RANK_15) || \ + ((__RANK__) == ADC_REGULAR_RANK_16)) + +#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ + ((__SCAN_MODE__) == ADC_SCAN_ENABLE)) + +#define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF)) +#define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16))) +#define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8))) +#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ + ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \ + (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F)))) + +/** + * @brief Set ADC Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. + * @retval None + */ +#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) + +/** + * @brief Set the ADC's sample time for channel numbers between 10 and 18. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. + * @retval None + */ +#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) + +/** + * @brief Set the ADC's sample time for channel numbers between 0 and 9. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. + * @retval None + */ +#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << ((3UL * ((uint32_t)((uint16_t)(_CHANNELNB_)))) & 0x1FUL)) + +/** + * @brief Set the selected regular channel rank for rank between 1 and 6. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) + +/** + * @brief Set the selected regular channel rank for rank between 7 and 12. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) + +/** + * @brief Set the selected regular channel rank for rank between 13 and 16. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_ Continuous mode. + * @retval None + */ +#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) + +/** + * @brief Configures the number of discontinuous conversions for the regular group channels. + * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. + * @retval None + */ +#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos) + +/** + * @brief Enable ADC scan mode. + * @param _SCANCONV_MODE_ Scan conversion mode. + * @retval None + */ +#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) + +/** + * @brief Enable the ADC end of conversion selection. + * @param _EOCSelection_MODE_ End of conversion selection mode. + * @retval None + */ +#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMAContReq_MODE_ DMA continuous request mode. + * @retval None + */ +#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) + +/** + * @brief Return resolution bits in CR1 register. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_ADC_H */ + + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h index 6ac40232..ae270a56 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_adc_ex.h @@ -1,354 +1,354 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_adc.h - * @author MCD Application Team - * @brief Header file of ADC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_ADC_EX_H -#define STM32F7xx_ADC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADCEx_Exported_Types ADC Exported Types - * @{ - */ - -/** - * @brief ADC Configuration injected Channel structure definition - * @note Parameters of this structure are shared within 2 scopes: - * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset - * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, - * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. - * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled - * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. - * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. - */ -typedef struct -{ - uint32_t InjectedChannel; /*!< Selection of ADC channel to configure - This parameter can be a value of @ref ADC_channels - Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ - uint32_t InjectedRank; /*!< Rank in the injected group sequencer - This parameter must be a value of @ref ADCEx_injected_rank - Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ - uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). - This parameter can be a value of @ref ADC_sampling_times - Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. - If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), - sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ - uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). - Offset value must be a positive number. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), - this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ - uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. - To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. - This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. - Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one - This parameter can be set to ENABLE or DISABLE. - Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) - Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) - Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. - To maintain JAUTO always enabled, DMA must be configured in circular mode. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. - If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. - If set to external trigger source, triggering is on event rising edge. - This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected - Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). - If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ - uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. - This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. - If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to - configure a channel on injected group can impact the configuration of other channels previously set. */ -}ADC_InjectionConfTypeDef; - -/** - * @brief ADC Configuration multi-mode structure definition - */ -typedef struct -{ - uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. - This parameter can be a value of @ref ADCEx_Common_mode */ - uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. - This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ - uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ -}ADC_MultiModeTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ADCEx_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADCEx_Common_mode ADC Common Mode - * @{ - */ -#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U) -#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) -#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) -#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) -#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) -#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) -#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) -#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)) -#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1)) -#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) -#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) -#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) -#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) -/** - * @} - */ - -/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode - * @{ - */ -#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */ -#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ -#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ -#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ -/** - * @} - */ - -/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected - * @{ - */ -#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U) -#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) -#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) -#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) -/** - * @} - */ - -/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected - * @{ - */ -#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000U) -#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0) -#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1) -#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2) -#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) - -#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3) -#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1)) -#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) -#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) -#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) -#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1) -/** - * @} - */ - -/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank - * @{ - */ -#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U) -#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U) -#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U) -#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U) -/** - * @} - */ - -/** @defgroup ADCEx_channels ADC Specific Channels - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ADC_Exported_Macros ADC Exported Macros - * @{ - */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADCEx_Exported_Functions - * @{ - */ - -/** @addtogroup ADCEx_Exported_Functions_Group1 - * @{ - */ - -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); - -/* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup ADCEx_Private_Constants ADC Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ADCEx_Private_Macros ADC Private Macros - * @{ - */ - -#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ - ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ - ((__MODE__) == ADC_DUALMODE_INTERL) || \ - ((__MODE__) == ADC_DUALMODE_ALTERTRIG) || \ - ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \ - ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \ - ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT) || \ - ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT) || \ - ((__MODE__) == ADC_TRIPLEMODE_INTERL) || \ - ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG)) -#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ - ((__MODE__) == ADC_DMAACCESSMODE_1) || \ - ((__MODE__) == ADC_DMAACCESSMODE_2) || \ - ((__MODE__) == ADC_DMAACCESSMODE_3)) -#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \ - ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) -#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ - ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ - ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)) -#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \ - ((__RANK__) == ADC_INJECTED_RANK_2) || \ - ((__RANK__) == ADC_INJECTED_RANK_3) || \ - ((__RANK__) == ADC_INJECTED_RANK_4)) -#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) - -/** - * @brief Set the selected injected Channel rank. - * @param _CHANNELNB_ Channel number. - * @param _RANKNB_ Rank number. - * @param _JSQR_JL_ Sequence length. - * @retval None - */ -#define ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_)))) -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup ADCEx_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_ADC_EX_H */ - - +/** + ****************************************************************************** + * @file stm32f7xx_hal_adc.h + * @author MCD Application Team + * @brief Header file of ADC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_ADC_EX_H +#define STM32F7xx_ADC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief ADC Configuration injected Channel structure definition + * @note Parameters of this structure are shared within 2 scopes: + * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset + * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, + * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. + * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. + * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. + */ +typedef struct +{ + uint32_t InjectedChannel; /*!< Selection of ADC channel to configure + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ + uint32_t InjectedRank; /*!< Rank in the injected group sequencer + This parameter must be a value of @ref ADCEx_injected_rank + Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), + this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. + To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 4. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one + This parameter can be set to ENABLE or DISABLE. + Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) + Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. + To maintain JAUTO always enabled, DMA must be configured in circular mode. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. + This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected + Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. + This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. + If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ +}ADC_InjectionConfTypeDef; + +/** + * @brief ADC Configuration multi-mode structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. + This parameter can be a value of @ref ADCEx_Common_mode */ + uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. + This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ + uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ +}ADC_MultiModeTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADCEx_Common_mode ADC Common Mode + * @{ + */ +#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U) +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) +#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) +#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) +#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) +#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1)) +#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) +#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) +/** + * @} + */ + +/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode + * @{ + */ +#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */ +#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ +#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ +#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U) +#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) +#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) +#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000U) +#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0) +#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1) +#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)ADC_CR2_JEXTSEL_2) +#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) + +#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO2 ((uint32_t)ADC_CR2_JEXTSEL_3) +#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T8_TRGO2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1)) +#define ADC_EXTERNALTRIGINJECCONV_T3_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) +#define ADC_EXTERNALTRIGINJECCONV_T3_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T6_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) +#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1) +/** + * @} + */ + +/** @defgroup ADCEx_injected_rank ADC Injected Channel Rank + * @{ + */ +#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U) +#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U) +#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U) +#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U) +/** + * @} + */ + +/** @defgroup ADCEx_channels ADC Specific Channels + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ + +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); + +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Constants ADC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Macros ADC Private Macros + * @{ + */ + +#define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ + ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ + ((__MODE__) == ADC_DUALMODE_INTERL) || \ + ((__MODE__) == ADC_DUALMODE_ALTERTRIG) || \ + ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \ + ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \ + ((__MODE__) == ADC_TRIPLEMODE_INJECSIMULT) || \ + ((__MODE__) == ADC_TRIPLEMODE_REGSIMULT) || \ + ((__MODE__) == ADC_TRIPLEMODE_INTERL) || \ + ((__MODE__) == ADC_TRIPLEMODE_ALTERTRIG)) +#define IS_ADC_DMA_ACCESS_MODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ + ((__MODE__) == ADC_DMAACCESSMODE_1) || \ + ((__MODE__) == ADC_DMAACCESSMODE_2) || \ + ((__MODE__) == ADC_DMAACCESSMODE_3)) +#define IS_ADC_EXT_INJEC_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \ + ((__EDGE__) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) +#define IS_ADC_EXT_INJEC_TRIG(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T8_TRGO2) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC3) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T3_CC1) || \ + ((__INJTRIG__) == ADC_EXTERNALTRIGINJECCONV_T6_TRGO) || \ + ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)) +#define IS_ADC_INJECTED_RANK(__RANK__) (((__RANK__) == ADC_INJECTED_RANK_1) || \ + ((__RANK__) == ADC_INJECTED_RANK_2) || \ + ((__RANK__) == ADC_INJECTED_RANK_3) || \ + ((__RANK__) == ADC_INJECTED_RANK_4)) +#define IS_ADC_INJECTED_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)4))) + +/** + * @brief Set the selected injected Channel rank. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @param _JSQR_JL_ Sequence length. + * @retval None + */ +#define ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_)))) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_ADC_EX_H */ + + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h index dd233c1a..b3f5299b 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_can.h @@ -1,859 +1,859 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_can.h - * @author MCD Application Team - * @brief Header file of CAN HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_CAN_H -#define STM32F7xx_HAL_CAN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined (CAN1) -/** @addtogroup CAN - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CAN_Exported_Types CAN Exported Types - * @{ - */ -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ - HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ - HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ - HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ - HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ - HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ - -} HAL_CAN_StateTypeDef; - -/** - * @brief CAN init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the length of a time quantum. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ - - uint32_t Mode; /*!< Specifies the CAN operating mode. - This parameter can be a value of @ref CAN_operating_mode */ - - uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware - is allowed to lengthen or shorten a bit to perform resynchronization. - This parameter can be a value of @ref CAN_synchronisation_jump_width */ - - uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ - - uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. - This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ - - FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. - This parameter can be set to ENABLE or DISABLE. */ - -} CAN_InitTypeDef; - -/** - * @brief CAN filter configuration structure definition - */ -typedef struct -{ - uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit - configuration, first one for a 16-bit configuration). - This parameter must be a number between - Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit - configuration, second one for a 16-bit configuration). - This parameter must be a number between - Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, - according to the mode (MSBs for a 32-bit configuration, - first one for a 16-bit configuration). - This parameter must be a number between - Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, - according to the mode (LSBs for a 32-bit configuration, - second one for a 16-bit configuration). - This parameter must be a number between - Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. - This parameter can be a value of @ref CAN_filter_FIFO */ - - uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. - For single CAN instance(14 dedicated filter banks), - this parameter must be a number between Min_Data = 0 and Max_Data = 13. - For dual CAN instances(28 filter banks shared), - this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ - - uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. - This parameter can be a value of @ref CAN_filter_mode */ - - uint32_t FilterScale; /*!< Specifies the filter scale. - This parameter can be a value of @ref CAN_filter_scale */ - - uint32_t FilterActivation; /*!< Enable or disable the filter. - This parameter can be a value of @ref CAN_filter_activation */ - - uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. - For single CAN instances, this parameter is meaningless. - For dual CAN instances, all filter banks with lower index are assigned to master - CAN instance, whereas all filter banks with greater index are assigned to slave - CAN instance. - This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ - -} CAN_FilterTypeDef; - -/** - * @brief CAN Tx message header structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_identifier_type */ - - uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. - This parameter can be a value of @ref CAN_remote_transmission_request */ - - uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - - FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start - of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. - @note: Time Triggered Communication Mode must be enabled. - @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. - This parameter can be set to ENABLE or DISABLE. */ - -} CAN_TxHeaderTypeDef; - -/** - * @brief CAN Rx message header structure definition - */ -typedef struct -{ - uint32_t StdId; /*!< Specifies the standard identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ - - uint32_t ExtId; /*!< Specifies the extended identifier. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ - - uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. - This parameter can be a value of @ref CAN_identifier_type */ - - uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. - This parameter can be a value of @ref CAN_remote_transmission_request */ - - uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. - This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ - - uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. - @note: Time Triggered Communication Mode must be enabled. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ - - uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. - This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ - -} CAN_RxHeaderTypeDef; - -/** - * @brief CAN handle Structure definition - */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -typedef struct __CAN_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ -{ - CAN_TypeDef *Instance; /*!< Register base address */ - - CAN_InitTypeDef Init; /*!< CAN required parameters */ - - __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ - - __IO uint32_t ErrorCode; /*!< CAN Error code. - This parameter can be a value of @ref CAN_Error_Code */ - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ - void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ - void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ - void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ - void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ - void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ - void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ - void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ - void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ - void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ - void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ - void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ - void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ - - void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ - void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ - -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ -} CAN_HandleTypeDef; - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -/** - * @brief HAL CAN common Callback ID enumeration definition - */ -typedef enum -{ - HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ - HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ - HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ - HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ - HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ - HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ - HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ - HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ - HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ - HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ - HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ - HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */ - HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ - - HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ - HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ - -} HAL_CAN_CallbackIDTypeDef; - -/** - * @brief HAL CAN Callback pointer definition - */ -typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ - -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Constants CAN Exported Constants - * @{ - */ - -/** @defgroup CAN_Error_Code CAN Error Code - * @{ - */ -#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ -#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ -#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ -#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ -#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ -#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ -#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ -#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ -#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ -#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ -#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ -#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ -#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ -#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ -#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ -#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ -#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ -#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ -#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ -#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ - -/** - * @} - */ - -/** @defgroup CAN_InitStatus CAN InitStatus - * @{ - */ -#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ -#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ -/** - * @} - */ - -/** @defgroup CAN_operating_mode CAN Operating Mode - * @{ - */ -#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ -#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ -#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ -#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with - silent mode */ -/** - * @} - */ - - -/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width - * @{ - */ -#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ -#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ -#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ -#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 - * @{ - */ -#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ -#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ -#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ -#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ -#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ -#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ -#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ -#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ -#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ -#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ -#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ -#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ -#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ -#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ -#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ -#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ -/** - * @} - */ - -/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 - * @{ - */ -#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ -#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ -#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ -#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ -#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ -#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ -#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ -#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ -/** - * @} - */ - -/** @defgroup CAN_filter_mode CAN Filter Mode - * @{ - */ -#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ -#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ -/** - * @} - */ - -/** @defgroup CAN_filter_scale CAN Filter Scale - * @{ - */ -#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ -#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ -/** - * @} - */ - -/** @defgroup CAN_filter_activation CAN Filter Activation - * @{ - */ -#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ -#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ -/** - * @} - */ - -/** @defgroup CAN_filter_FIFO CAN Filter FIFO - * @{ - */ -#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ -#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ -/** - * @} - */ - -/** @defgroup CAN_identifier_type CAN Identifier Type - * @{ - */ -#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ -#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ -/** - * @} - */ - -/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request - * @{ - */ -#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ -#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ -/** - * @} - */ - -/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number - * @{ - */ -#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ -#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ -/** - * @} - */ - -/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes - * @{ - */ -#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ -#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ -#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ -/** - * @} - */ - -/** @defgroup CAN_flags CAN Flags - * @{ - */ -/* Transmit Flags */ -#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ -#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ -#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ -#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ -#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ -#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ -#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ -#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ -#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ -#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ -#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ -#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ -#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ -#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ -#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ -#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ -#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ -#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ - -/* Receive Flags */ -#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ -#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ -#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ -#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ - -/* Operating Mode Flags */ -#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ -#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ -#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ -#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ -#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ - -/* Error Flags */ -#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ -#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ -#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ -/** - * @} - */ - - -/** @defgroup CAN_Interrupts CAN Interrupts - * @{ - */ -/* Transmit Interrupt */ -#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ - -/* Receive Interrupts */ -#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ -#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ -#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ -#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ -#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ -#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ - -/* Operating Mode Interrupts */ -#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ -#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ - -/* Error Interrupts */ -#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ -#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ -#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ -#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ -#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CAN_Exported_Macros CAN Exported Macros - * @{ - */ - -/** @brief Reset CAN handle state - * @param __HANDLE__ CAN handle. - * @retval None - */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) -#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ - -/** - * @brief Enable the specified CAN interrupts. - * @param __HANDLE__ CAN handle. - * @param __INTERRUPT__ CAN Interrupt sources to enable. - * This parameter can be any combination of @arg CAN_Interrupts - * @retval None - */ -#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable the specified CAN interrupts. - * @param __HANDLE__ CAN handle. - * @param __INTERRUPT__ CAN Interrupt sources to disable. - * This parameter can be any combination of @arg CAN_Interrupts - * @retval None - */ -#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) - -/** @brief Check if the specified CAN interrupt source is enabled or disabled. - * @param __HANDLE__ specifies the CAN Handle. - * @param __INTERRUPT__ specifies the CAN interrupt source to check. - * This parameter can be a value of @arg CAN_Interrupts - * @retval The state of __IT__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) - -/** @brief Check whether the specified CAN flag is set or not. - * @param __HANDLE__ specifies the CAN Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of @arg CAN_flags - * @retval The state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) - -/** @brief Clear the specified CAN pending flag. - * @param __HANDLE__ specifies the CAN Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag - * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag - * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag - * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag - * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag - * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag - * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag - * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag - * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag - * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag - * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag - * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag - * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag - * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag - * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag - * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag - * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag - * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag - * @retval None - */ -#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ - (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); -void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); -void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -/* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, - void (* pCallback)(CAN_HandleTypeDef *_hcan)); -HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); - -#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions - * @brief Configuration functions - * @{ - */ - -/* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig); - -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * @{ - */ - -/* Control functions **********************************************************/ -HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, - const uint8_t aData[], uint32_t *pTxMailbox); -HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox); -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, - CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); -uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo); - -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * @{ - */ -/* Interrupts management ******************************************************/ -HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); -HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); -void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); - -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group5 Callback functions - * @brief Callback functions - * @{ - */ -/* Callbacks functions ********************************************************/ - -void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); -void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); - -/** - * @} - */ - -/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); - -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup CAN_Private_Types CAN Private Types - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Variables CAN Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CAN_Private_Constants CAN Private Constants - * @{ - */ -#define CAN_FLAG_MASK (0x000000FFU) -/** - * @} - */ - -/* Private Macros -----------------------------------------------------------*/ -/** @defgroup CAN_Private_Macros CAN Private Macros - * @{ - */ - -#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ - ((MODE) == CAN_MODE_LOOPBACK)|| \ - ((MODE) == CAN_MODE_SILENT) || \ - ((MODE) == CAN_MODE_SILENT_LOOPBACK)) -#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ - ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) -#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ - ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ - ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ - ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ - ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ - ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ - ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ - ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) -#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ - ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ - ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ - ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) -#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) -#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) -#if defined(CAN2) -#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) -#endif -#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) -#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ - ((MODE) == CAN_FILTERMODE_IDLIST)) -#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ - ((SCALE) == CAN_FILTERSCALE_32BIT)) -#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ - ((ACTIVATION) == CAN_FILTER_ENABLE)) -#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ - ((FIFO) == CAN_FILTER_FIFO1)) -#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ - ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ - ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) -#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \ - CAN_TX_MAILBOX2)) -#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) -#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) -#define IS_CAN_DLC(DLC) ((DLC) <= 8U) -#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ - ((IDTYPE) == CAN_ID_EXT)) -#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) -#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) -#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ - CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ - CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ - CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ - CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ - CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ - CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/** - * @} - */ - - -#endif /* CAN1 */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_CAN_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_can.h + * @author MCD Application Team + * @brief Header file of CAN HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_CAN_H +#define STM32F7xx_HAL_CAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +#if defined (CAN1) +/** @addtogroup CAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CAN_Exported_Types CAN Exported Types + * @{ + */ +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ + HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ + HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */ + HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */ + HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */ + HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */ + +} HAL_CAN_StateTypeDef; + +/** + * @brief CAN init structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the length of a time quantum. + This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */ + + uint32_t Mode; /*!< Specifies the CAN operating mode. + This parameter can be a value of @ref CAN_operating_mode */ + + uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware + is allowed to lengthen or shorten a bit to perform resynchronization. + This parameter can be a value of @ref CAN_synchronisation_jump_width */ + + uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ + + uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_InitTypeDef; + +/** + * @brief CAN filter configuration structure definition + */ +typedef struct +{ + uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized. + For single CAN instance(14 dedicated filter banks), + this parameter must be a number between Min_Data = 0 and Max_Data = 13. + For dual CAN instances(28 filter banks shared), + this parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + + uint32_t FilterMode; /*!< Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint32_t FilterScale; /*!< Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + uint32_t FilterActivation; /*!< Enable or disable the filter. + This parameter can be a value of @ref CAN_filter_activation */ + + uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance. + For single CAN instances, this parameter is meaningless. + For dual CAN instances, all filter banks with lower index are assigned to master + CAN instance, whereas all filter banks with greater index are assigned to slave + CAN instance. + This parameter must be a number between Min_Data = 0 and Max_Data = 27. */ + +} CAN_FilterTypeDef; + +/** + * @brief CAN Tx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start + of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7]. + @note: Time Triggered Communication Mode must be enabled. + @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent. + This parameter can be set to ENABLE or DISABLE. */ + +} CAN_TxHeaderTypeDef; + +/** + * @brief CAN Rx message header structure definition + */ +typedef struct +{ + uint32_t StdId; /*!< Specifies the standard identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */ + + uint32_t ExtId; /*!< Specifies the extended identifier. + This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */ + + uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. + This parameter can be a value of @ref CAN_identifier_type */ + + uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. + This parameter can be a value of @ref CAN_remote_transmission_request */ + + uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. + This parameter must be a number between Min_Data = 0 and Max_Data = 8. */ + + uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception. + @note: Time Triggered Communication Mode must be enabled. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */ + + uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */ + +} CAN_RxHeaderTypeDef; + +/** + * @brief CAN handle Structure definition + */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +typedef struct __CAN_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +{ + CAN_TypeDef *Instance; /*!< Register base address */ + + CAN_InitTypeDef Init; /*!< CAN required parameters */ + + __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ + + __IO uint32_t ErrorCode; /*!< CAN Error code. + This parameter can be a value of @ref CAN_Error_Code */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback */ + void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback */ + void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback */ + void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 0 abort callback */ + void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 1 abort callback */ + void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Tx Mailbox 2 abort callback */ + void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback */ + void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 full callback */ + void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback */ + void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 full callback */ + void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Sleep callback */ + void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Wake Up from Rx msg callback */ + void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Error callback */ + + void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp Init callback */ + void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Msp DeInit callback */ + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +} CAN_HandleTypeDef; + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief HAL CAN common Callback ID enumeration definition + */ +typedef enum +{ + HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID = 0x00U, /*!< CAN Tx Mailbox 0 complete callback ID */ + HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID = 0x01U, /*!< CAN Tx Mailbox 1 complete callback ID */ + HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID = 0x02U, /*!< CAN Tx Mailbox 2 complete callback ID */ + HAL_CAN_TX_MAILBOX0_ABORT_CB_ID = 0x03U, /*!< CAN Tx Mailbox 0 abort callback ID */ + HAL_CAN_TX_MAILBOX1_ABORT_CB_ID = 0x04U, /*!< CAN Tx Mailbox 1 abort callback ID */ + HAL_CAN_TX_MAILBOX2_ABORT_CB_ID = 0x05U, /*!< CAN Tx Mailbox 2 abort callback ID */ + HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID = 0x06U, /*!< CAN Rx FIFO 0 message pending callback ID */ + HAL_CAN_RX_FIFO0_FULL_CB_ID = 0x07U, /*!< CAN Rx FIFO 0 full callback ID */ + HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID = 0x08U, /*!< CAN Rx FIFO 1 message pending callback ID */ + HAL_CAN_RX_FIFO1_FULL_CB_ID = 0x09U, /*!< CAN Rx FIFO 1 full callback ID */ + HAL_CAN_SLEEP_CB_ID = 0x0AU, /*!< CAN Sleep callback ID */ + HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID = 0x0BU, /*!< CAN Wake Up from Rx msg callback ID */ + HAL_CAN_ERROR_CB_ID = 0x0CU, /*!< CAN Error callback ID */ + + HAL_CAN_MSPINIT_CB_ID = 0x0DU, /*!< CAN MspInit callback ID */ + HAL_CAN_MSPDEINIT_CB_ID = 0x0EU, /*!< CAN MspDeInit callback ID */ + +} HAL_CAN_CallbackIDTypeDef; + +/** + * @brief HAL CAN Callback pointer definition + */ +typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function */ + +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Constants CAN Exported Constants + * @{ + */ + +/** @defgroup CAN_Error_Code CAN Error Code + * @{ + */ +#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */ +#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */ +#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */ +#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */ +#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */ +#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */ +#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */ +#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */ +#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */ +#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ +#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ +#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ +#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ +#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ +#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */ +#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */ + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error */ +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ +#define HAL_CAN_ERROR_INTERNAL (0x00800000U) /*!< Internal error */ + +/** + * @} + */ + +/** @defgroup CAN_InitStatus CAN InitStatus + * @{ + */ +#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */ +#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */ +/** + * @} + */ + +/** @defgroup CAN_operating_mode CAN Operating Mode + * @{ + */ +#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ +#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ +#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with + silent mode */ +/** + * @} + */ + + +/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width + * @{ + */ +#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ +#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ +#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 + * @{ + */ +#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ +#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ +#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ +#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ +#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ +#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ +#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ +#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ +#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ +#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ +#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ +#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ +#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ +#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ +#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2 + * @{ + */ +#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */ +#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ +#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ +#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ +#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ +#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ +#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ +#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ +/** + * @} + */ + +/** @defgroup CAN_filter_mode CAN Filter Mode + * @{ + */ +#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */ +#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */ +/** + * @} + */ + +/** @defgroup CAN_filter_scale CAN Filter Scale + * @{ + */ +#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */ +#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_activation CAN Filter Activation + * @{ + */ +#define CAN_FILTER_DISABLE (0x00000000U) /*!< Disable filter */ +#define CAN_FILTER_ENABLE (0x00000001U) /*!< Enable filter */ +/** + * @} + */ + +/** @defgroup CAN_filter_FIFO CAN Filter FIFO + * @{ + */ +#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */ +#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */ +/** + * @} + */ + +/** @defgroup CAN_identifier_type CAN Identifier Type + * @{ + */ +#define CAN_ID_STD (0x00000000U) /*!< Standard Id */ +#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */ +/** + * @} + */ + +/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request + * @{ + */ +#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */ +#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */ +/** + * @} + */ + +/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number + * @{ + */ +#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */ +#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */ +/** + * @} + */ + +/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes + * @{ + */ +#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */ +#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */ +#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */ +/** + * @} + */ + +/** @defgroup CAN_flags CAN Flags + * @{ + */ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */ +#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */ +#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */ +#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */ +#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */ +#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */ +#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */ +#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */ +#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */ +#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */ +#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */ +#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */ +#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */ +#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */ +#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */ +#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */ +#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */ +#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */ + +/* Receive Flags */ +#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */ +#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */ +#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */ +#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */ +#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */ +#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */ +#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */ +#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */ + +/* Error Flags */ +#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */ +#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */ +#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */ +/** + * @} + */ + + +/** @defgroup CAN_Interrupts CAN Interrupts + * @{ + */ +/* Transmit Interrupt */ +#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ + +/* Receive Interrupts */ +#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ +#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ +#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ +#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ +#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ +#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ + +/* Operating Mode Interrupts */ +#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ +#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ + +/* Error Interrupts */ +#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ +#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ +#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ +#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ +#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup CAN_Exported_Macros CAN Exported Macros + * @{ + */ + +/** @brief Reset CAN handle state + * @param __HANDLE__ CAN handle. + * @retval None + */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_CAN_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) +#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @brief Enable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to enable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) + +/** + * @brief Disable the specified CAN interrupts. + * @param __HANDLE__ CAN handle. + * @param __INTERRUPT__ CAN Interrupt sources to disable. + * This parameter can be any combination of @arg CAN_Interrupts + * @retval None + */ +#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) + +/** @brief Check if the specified CAN interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the CAN Handle. + * @param __INTERRUPT__ specifies the CAN interrupt source to check. + * This parameter can be a value of @arg CAN_Interrupts + * @retval The state of __IT__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__)) + +/** @brief Check whether the specified CAN flag is set or not. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of @arg CAN_flags + * @retval The state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** @brief Clear the specified CAN pending flag. + * @param __HANDLE__ specifies the CAN Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag + * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag + * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag + * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag + * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag + * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag + * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag + * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag + * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag + * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag + * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag + * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag + * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag + * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag + * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag + * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag + * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag + * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag + * @retval None + */ +#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ + ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ + (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ + +/* Initialization and de-initialization functions *****************************/ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan); +void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); + +#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions + * @{ + */ + +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * @{ + */ + +/* Control functions **********************************************************/ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox); +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * @{ + */ +/* Interrupts management ******************************************************/ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs); +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs); +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group5 Callback functions + * @brief Callback functions + * @{ + */ +/* Callbacks functions ********************************************************/ + +void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan); +void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); + +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup CAN_Private_Types CAN Private Types + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Variables CAN Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_FLAG_MASK (0x000000FFU) +/** + * @} + */ + +/* Private Macros -----------------------------------------------------------*/ +/** @defgroup CAN_Private_Macros CAN Private Macros + * @{ + */ + +#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ + ((MODE) == CAN_MODE_LOOPBACK)|| \ + ((MODE) == CAN_MODE_SILENT) || \ + ((MODE) == CAN_MODE_SILENT_LOOPBACK)) +#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \ + ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) +#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \ + ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \ + ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \ + ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \ + ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \ + ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \ + ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \ + ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ)) +#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \ + ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \ + ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \ + ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ)) +#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) +#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU) +#if defined(CAN2) +#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U) +#endif +#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U) +#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ + ((MODE) == CAN_FILTERMODE_IDLIST)) +#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ + ((SCALE) == CAN_FILTERSCALE_32BIT)) +#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \ + ((ACTIVATION) == CAN_FILTER_ENABLE)) +#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ + ((FIFO) == CAN_FILTER_FIFO1)) +#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ + ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \ + CAN_TX_MAILBOX2)) +#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) +#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) +#define IS_CAN_DLC(DLC) ((DLC) <= 8U) +#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ + ((IDTYPE) == CAN_ID_EXT)) +#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) +#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1)) +#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \ + CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \ + CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \ + CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \ + CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \ + CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \ + CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR)) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/** + * @} + */ + + +#endif /* CAN1 */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_CAN_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h deleted file mode 100644 index a6d67a8d..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cec.h +++ /dev/null @@ -1,804 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cec.h - * @author MCD Application Team - * @brief Header file of CEC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_CEC_H -#define STM32F7xx_HAL_CEC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (CEC) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup CEC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CEC_Exported_Types CEC Exported Types - * @{ - */ - -/** - * @brief CEC Init Structure definition - */ -typedef struct -{ - uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time. - It can be one of CEC_Signal_Free_Time - and belongs to the set {0,...,7} where - 0x0 is the default configuration - else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */ - - uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms, - it can be a value of CEC_Tolerance : - it is either CEC_STANDARD_TOLERANCE or CEC_EXTENDED_TOLERANCE */ - - uint32_t BRERxStop; /*!< Set BRESTP bit CEC_BRERxStop : specifies whether or not a Bit Rising - Error stops the reception. - CEC_NO_RX_STOP_ON_BRE: reception is not stopped. - CEC_RX_STOP_ON_BRE: reception is stopped. */ - - uint32_t BREErrorBitGen; /*!< Set BREGEN bit CEC_BREErrorBitGen : specifies whether or not an - Error-Bit is generated on the - CEC line upon Bit Rising Error detection. - CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation. - CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */ - - uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit CEC_LBPEErrorBitGen : specifies whether or not an - Error-Bit is generated on the - CEC line upon Long Bit Period Error detection. - CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation. - CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */ - - uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit CEC_BroadCastMsgErrorBitGen : allows to avoid an - Error-Bit generation on the CEC line - upon an error detected on a broadcast message. - - It supersedes BREGEN and LBPEGEN bits for a broadcast message error - handling. It can take two values: - - 1) CEC_BROADCASTERROR_ERRORBIT_GENERATION. - a) BRE detection: error-bit generation on the CEC line if - BRESTP=CEC_RX_STOP_ON_BRE and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION. - b) LBPE detection: error-bit generation on the CEC line - if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION. - - 2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION. - no error-bit generation in case neither a) nor b) are satisfied. - Additionally, there is no error-bit generation in case of Short Bit - Period Error detection in a broadcast message while LSTN bit is set. */ - - uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit CEC_SFT_Option : specifies when SFT timer starts. - CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software. - CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end - of message transmission/reception. */ - - uint32_t ListenMode; /*!< Set LSTN bit CEC_Listening_Mode : specifies device listening mode. - It can take two values: - - CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed - to its own address (OAR). Messages addressed to different destination - are ignored. - Broadcast messages are always received. - - CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its - own address (OAR) with positive acknowledge. Messages addressed to - different destination are received, but without interfering with the - CEC bus: no acknowledge sent. */ - - uint16_t OwnAddress; /*!< Own addresses configuration - This parameter can be a value of CEC_OWN_ADDRESS */ - - uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ - - -} CEC_InitTypeDef; - -/** - * @brief HAL CEC State definition - * @note HAL CEC State value is a combination of 2 different substates: gState and RxState - (see CEC_State_Definition). - * - gState contains CEC state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7 (not used) - * x : Should be set to 0 - * b6 Error information - * 0 : No Error - * 1 : Error - * b5 CEC peripheral initialization status - * 0 : Reset (peripheral not initialized) - * 1 : Init done (peripheral initialized. HAL CEC Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (peripheral busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 CEC peripheral initialization status - * 0 : Reset (peripheral not initialized) - * 1 : Init done (peripheral initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef uint32_t HAL_CEC_StateTypeDef; - -/** - * @brief CEC handle Structure definition - */ -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) -typedef struct __CEC_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ -{ - CEC_TypeDef *Instance; /*!< CEC registers base address */ - - CEC_InitTypeDef Init; /*!< CEC communication parameters */ - - const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ - - uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ - - uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of HAL_CEC_StateTypeDef */ - - HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. - This parameter can be a value of HAL_CEC_StateTypeDef */ - - uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register - in case error is reported */ - -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) - void (* TxCpltCallback)(struct __CEC_HandleTypeDef - *hcec); /*!< CEC Tx Transfer completed callback */ - void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec, - uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ - void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC error callback */ - - void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp Init callback */ - void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec); /*!< CEC Msp DeInit callback */ - -#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ -} CEC_HandleTypeDef; - -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL CEC Callback ID enumeration definition - */ -typedef enum -{ - HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ - HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ - HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ - HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ - HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ -} HAL_CEC_CallbackIDTypeDef; - -/** - * @brief HAL CEC Callback pointer definition - */ -typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec); /*!< pointer to an CEC callback function */ -typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec, - uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed - callback function */ -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CEC_Exported_Constants CEC Exported Constants - * @{ - */ -/** @defgroup CEC_State_Definition CEC State Code Definition - * @{ - */ -#define HAL_CEC_STATE_RESET ((uint32_t)0x00000000) /*!< Peripheral is not yet Initialized - Value is allowed for gState and RxState */ -#define HAL_CEC_STATE_READY ((uint32_t)0x00000020) /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ -#define HAL_CEC_STATE_BUSY ((uint32_t)0x00000024) /*!< an internal process is ongoing - Value is allowed for gState only */ -#define HAL_CEC_STATE_BUSY_RX ((uint32_t)0x00000022) /*!< Data Reception process is ongoing - Value is allowed for RxState only */ -#define HAL_CEC_STATE_BUSY_TX ((uint32_t)0x00000021) /*!< Data Transmission process is ongoing - Value is allowed for gState only */ -#define HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023) /*!< an internal process is ongoing - Value is allowed for gState only */ -#define HAL_CEC_STATE_ERROR ((uint32_t)0x00000050) /*!< Error Value is allowed for gState only */ -/** - * @} - */ -/** @defgroup CEC_Error_Code CEC Error Code - * @{ - */ -#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */ -#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */ -#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */ -#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */ -#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */ -#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */ -#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */ -#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */ -#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */ -#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */ -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) -#define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error */ -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter - * @{ - */ -#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U) -#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U) -#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U) -#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U) -#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U) -#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U) -#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U) -#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U) -/** - * @} - */ - -/** @defgroup CEC_Tolerance CEC Receiver Tolerance - * @{ - */ -#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U) -#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL) -/** - * @} - */ - -/** @defgroup CEC_BRERxStop CEC Reception Stop on Error - * @{ - */ -#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U) -#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP) -/** - * @} - */ - -/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported - * @{ - */ -#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) -#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN) -/** - * @} - */ - -/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported - * @{ - */ -#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U) -#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN) -/** - * @} - */ - -/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message - * @{ - */ -#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U) -#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN) -/** - * @} - */ - -/** @defgroup CEC_SFT_Option CEC Signal Free Time start option - * @{ - */ -#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U) -#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT) -/** - * @} - */ - -/** @defgroup CEC_Listening_Mode CEC Listening mode option - * @{ - */ -#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U) -#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN) -/** - * @} - */ - -/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register - * @{ - */ -#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U) -/** - * @} - */ - -/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header - * @{ - */ -#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U) -/** - * @} - */ - -/** @defgroup CEC_OWN_ADDRESS CEC Own Address - * @{ - */ -#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */ -#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */ -#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */ -#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */ -#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */ -#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */ -#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */ -#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */ -#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */ -#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */ -#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */ -#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */ -#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */ -#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */ -#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */ -#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */ -/** - * @} - */ - -/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition - * @{ - */ -#define CEC_IT_TXACKE CEC_IER_TXACKEIE -#define CEC_IT_TXERR CEC_IER_TXERRIE -#define CEC_IT_TXUDR CEC_IER_TXUDRIE -#define CEC_IT_TXEND CEC_IER_TXENDIE -#define CEC_IT_TXBR CEC_IER_TXBRIE -#define CEC_IT_ARBLST CEC_IER_ARBLSTIE -#define CEC_IT_RXACKE CEC_IER_RXACKEIE -#define CEC_IT_LBPE CEC_IER_LBPEIE -#define CEC_IT_SBPE CEC_IER_SBPEIE -#define CEC_IT_BRE CEC_IER_BREIE -#define CEC_IT_RXOVR CEC_IER_RXOVRIE -#define CEC_IT_RXEND CEC_IER_RXENDIE -#define CEC_IT_RXBR CEC_IER_RXBRIE -/** - * @} - */ - -/** @defgroup CEC_Flags_Definitions CEC Flags definition - * @{ - */ -#define CEC_FLAG_TXACKE CEC_ISR_TXACKE -#define CEC_FLAG_TXERR CEC_ISR_TXERR -#define CEC_FLAG_TXUDR CEC_ISR_TXUDR -#define CEC_FLAG_TXEND CEC_ISR_TXEND -#define CEC_FLAG_TXBR CEC_ISR_TXBR -#define CEC_FLAG_ARBLST CEC_ISR_ARBLST -#define CEC_FLAG_RXACKE CEC_ISR_RXACKE -#define CEC_FLAG_LBPE CEC_ISR_LBPE -#define CEC_FLAG_SBPE CEC_ISR_SBPE -#define CEC_FLAG_BRE CEC_ISR_BRE -#define CEC_FLAG_RXOVR CEC_ISR_RXOVR -#define CEC_FLAG_RXEND CEC_ISR_RXEND -#define CEC_FLAG_RXBR CEC_ISR_RXBR -/** - * @} - */ - -/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags - * @{ - */ -#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\ - CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE) -/** - * @} - */ - -/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag - * @{ - */ -#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE) -/** - * @} - */ - -/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag - * @{ - */ -#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CEC_Exported_Macros CEC Exported Macros - * @{ - */ - -/** @brief Reset CEC handle gstate & RxState - * @param __HANDLE__ CEC handle. - * @retval None - */ -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) -#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ - } while(0) -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ -/** @brief Checks whether or not the specified CEC interrupt flag is set. - * @param __HANDLE__ specifies the CEC Handle. - * @param __FLAG__ specifies the flag to check. - * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error - * @arg CEC_FLAG_TXERR: Tx Error. - * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. - * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). - * @arg CEC_FLAG_TXBR: Tx-Byte Request. - * @arg CEC_FLAG_ARBLST: Arbitration Lost - * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge - * @arg CEC_FLAG_LBPE: Rx Long period Error - * @arg CEC_FLAG_SBPE: Rx Short period Error - * @arg CEC_FLAG_BRE: Rx Bit Rising Error - * @arg CEC_FLAG_RXOVR: Rx Overrun. - * @arg CEC_FLAG_RXEND: End Of Reception. - * @arg CEC_FLAG_RXBR: Rx-Byte Received. - * @retval ITStatus - */ -#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) - -/** @brief Clears the interrupt or status flag when raised (write at 1) - * @param __HANDLE__ specifies the CEC Handle. - * @param __FLAG__ specifies the interrupt/status flag to clear. - * This parameter can be one of the following values: - * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error - * @arg CEC_FLAG_TXERR: Tx Error. - * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun. - * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte). - * @arg CEC_FLAG_TXBR: Tx-Byte Request. - * @arg CEC_FLAG_ARBLST: Arbitration Lost - * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge - * @arg CEC_FLAG_LBPE: Rx Long period Error - * @arg CEC_FLAG_SBPE: Rx Short period Error - * @arg CEC_FLAG_BRE: Rx Bit Rising Error - * @arg CEC_FLAG_RXOVR: Rx Overrun. - * @arg CEC_FLAG_RXEND: End Of Reception. - * @arg CEC_FLAG_RXBR: Rx-Byte Received. - * @retval none - */ -#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__)) - -/** @brief Enables the specified CEC interrupt. - * @param __HANDLE__ specifies the CEC Handle. - * @param __INTERRUPT__ specifies the CEC interrupt to enable. - * This parameter can be one of the following values: - * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable - * @arg CEC_IT_TXERR: Tx Error IT Enable - * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable - * @arg CEC_IT_TXEND: End of transmission IT Enable - * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable - * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable - * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable - * @arg CEC_IT_LBPE: Rx Long period Error IT Enable - * @arg CEC_IT_SBPE: Rx Short period Error IT Enable - * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable - * @arg CEC_IT_RXOVR: Rx Overrun IT Enable - * @arg CEC_IT_RXEND: End Of Reception IT Enable - * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable - * @retval none - */ -#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) - -/** @brief Disables the specified CEC interrupt. - * @param __HANDLE__ specifies the CEC Handle. - * @param __INTERRUPT__ specifies the CEC interrupt to disable. - * This parameter can be one of the following values: - * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable - * @arg CEC_IT_TXERR: Tx Error IT Enable - * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable - * @arg CEC_IT_TXEND: End of transmission IT Enable - * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable - * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable - * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable - * @arg CEC_IT_LBPE: Rx Long period Error IT Enable - * @arg CEC_IT_SBPE: Rx Short period Error IT Enable - * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable - * @arg CEC_IT_RXOVR: Rx Overrun IT Enable - * @arg CEC_IT_RXEND: End Of Reception IT Enable - * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable - * @retval none - */ -#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) - -/** @brief Checks whether or not the specified CEC interrupt is enabled. - * @param __HANDLE__ specifies the CEC Handle. - * @param __INTERRUPT__ specifies the CEC interrupt to check. - * This parameter can be one of the following values: - * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable - * @arg CEC_IT_TXERR: Tx Error IT Enable - * @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable - * @arg CEC_IT_TXEND: End of transmission IT Enable - * @arg CEC_IT_TXBR: Tx-Byte Request IT Enable - * @arg CEC_IT_ARBLST: Arbitration Lost IT Enable - * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable - * @arg CEC_IT_LBPE: Rx Long period Error IT Enable - * @arg CEC_IT_SBPE: Rx Short period Error IT Enable - * @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable - * @arg CEC_IT_RXOVR: Rx Overrun IT Enable - * @arg CEC_IT_RXEND: End Of Reception IT Enable - * @arg CEC_IT_RXBR: Rx-Byte Received IT Enable - * @retval FlagStatus - */ -#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) - -/** @brief Enables the CEC device - * @param __HANDLE__ specifies the CEC Handle. - * @retval none - */ -#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN) - -/** @brief Disables the CEC device - * @param __HANDLE__ specifies the CEC Handle. - * @retval none - */ -#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN) - -/** @brief Set Transmission Start flag - * @param __HANDLE__ specifies the CEC Handle. - * @retval none - */ -#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM) - -/** @brief Set Transmission End flag - * @param __HANDLE__ specifies the CEC Handle. - * @retval none - * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. - */ -#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM) - -/** @brief Get Transmission Start flag - * @param __HANDLE__ specifies the CEC Handle. - * @retval FlagStatus - */ -#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM) - -/** @brief Get Transmission End flag - * @param __HANDLE__ specifies the CEC Handle. - * @retval FlagStatus - */ -#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM) - -/** @brief Clear OAR register - * @param __HANDLE__ specifies the CEC Handle. - * @retval none - */ -#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR) - -/** @brief Set OAR register (without resetting previously set address in case of multi-address mode) - * To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand - * @param __HANDLE__ specifies the CEC Handle. - * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position) - * @retval none - */ -#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, \ - (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CEC_Exported_Functions - * @{ - */ - -/** @addtogroup CEC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); -HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); -HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); -void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); -void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); - -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, - pCEC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup CEC_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - const uint8_t *pData, uint32_t Size); -uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); -void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); -void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); -void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); -void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); -void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); -/** - * @} - */ - -/** @addtogroup CEC_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); -uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup CEC_Private_Types CEC Private Types - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup CEC_Private_Variables CEC Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CEC_Private_Constants CEC Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CEC_Private_Macros CEC Private Macros - * @{ - */ - -#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT) - -#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \ - ((__RXTOL__) == CEC_EXTENDED_TOLERANCE)) - -#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \ - ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE)) - -#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \ - ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION)) - -#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \ - ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION)) - -#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) \ - (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \ - ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION)) - -#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \ - ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END)) - -#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \ - ((__MODE__) == CEC_FULL_LISTENING_MODE)) - -/** @brief Check CEC message size. - * The message size is the payload size: without counting the header, - * it varies from 0 byte (ping operation, one header only, no payload) to - * 15 bytes (1 opcode and up to 14 operands following the header). - * @param __SIZE__ CEC message size. - * @retval Test result (TRUE or FALSE). - */ -#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) - -/** @brief Check CEC device Own Address Register (OAR) setting. - * OAR address is written in a 15-bit field within CEC_CFGR register. - * @param __ADDRESS__ CEC own address. - * @retval Test result (TRUE or FALSE). - */ -#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU) - -/** @brief Check CEC initiator or destination logical address setting. - * Initiator and destination addresses are coded over 4 bits. - * @param __ADDRESS__ CEC initiator or logical address. - * @retval Test result (TRUE or FALSE). - */ -#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU) -/** - * @} - */ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CEC_Private_Functions CEC Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* CEC */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xxHAL_CEC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_conf_template.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_conf_template.h deleted file mode 100644 index b739c716..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_conf_template.h +++ /dev/null @@ -1,499 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_conf_template.h - * @author MCD Application Team - * @brief HAL configuration template file. - * This file should be copied to the application folder and renamed - * to stm32f7xx_hal_conf.h. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CONF_H -#define __STM32F7xx_HAL_CONF_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED -#define HAL_CAN_MODULE_ENABLED -/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ -#define HAL_CEC_MODULE_ENABLED -#define HAL_CRC_MODULE_ENABLED -#define HAL_CRYP_MODULE_ENABLED -#define HAL_DAC_MODULE_ENABLED -#define HAL_DCMI_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_DMA2D_MODULE_ENABLED -#define HAL_ETH_MODULE_ENABLED -/* #define HAL_ETH_LEGACY_MODULE_ENABLED */ -#define HAL_EXTI_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_NAND_MODULE_ENABLED -#define HAL_NOR_MODULE_ENABLED -#define HAL_SRAM_MODULE_ENABLED -#define HAL_SDRAM_MODULE_ENABLED -#define HAL_HASH_MODULE_ENABLED -#define HAL_GPIO_MODULE_ENABLED -#define HAL_I2C_MODULE_ENABLED -#define HAL_I2S_MODULE_ENABLED -#define HAL_IWDG_MODULE_ENABLED -#define HAL_LPTIM_MODULE_ENABLED -#define HAL_LTDC_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_QSPI_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_RNG_MODULE_ENABLED -#define HAL_RTC_MODULE_ENABLED -#define HAL_SAI_MODULE_ENABLED -#define HAL_SD_MODULE_ENABLED -#define HAL_SPDIFRX_MODULE_ENABLED -#define HAL_SPI_MODULE_ENABLED -#define HAL_TIM_MODULE_ENABLED -#define HAL_UART_MODULE_ENABLED -#define HAL_USART_MODULE_ENABLED -#define HAL_IRDA_MODULE_ENABLED -#define HAL_SMARTCARD_MODULE_ENABLED -#define HAL_WWDG_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED -#define HAL_PCD_MODULE_ENABLED -#define HAL_HCD_MODULE_ENABLED -#define HAL_DFSDM_MODULE_ENABLED -#define HAL_DSI_MODULE_ENABLED -#define HAL_JPEG_MODULE_ENABLED -#define HAL_MDIOS_MODULE_ENABLED -#define HAL_SMBUS_MODULE_ENABLED -#define HAL_MMC_MODULE_ENABLED - - -/* ########################## HSE/HSI Values adaptation ##################### */ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE 25000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) - #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) - #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz - The real value may vary depending on the variations - in voltage and temperature. */ -/** - * @brief External Low Speed oscillator (LSE) value. - */ -#if !defined (LSE_VALUE) - #define LSE_VALUE 32768U /*!< Value of the External Low Speed oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) - #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for I2S peripheral - * This value is used by the I2S HAL module to compute the I2S clock source - * frequency, this source is inserted directly through I2S_CKIN pad. - */ -#if !defined (EXTERNAL_CLOCK_VALUE) - #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* EXTERNAL_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300U /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U /* To enable prefetch */ -#define ART_ACCELERATOR_ENABLE 1U /* To enable ART Accelerator */ - -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ -#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1 */ - -/* ################## Ethernet peripheral configuration ##################### */ - -/* Section 1 : Ethernet peripheral configuration */ - -/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ -#define MAC_ADDR0 2U -#define MAC_ADDR1 0U -#define MAC_ADDR2 0U -#define MAC_ADDR3 0U -#define MAC_ADDR4 0U -#define MAC_ADDR5 0U - -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE 1528U /* ETH Max buffer size for receive */ -#define ETH_TX_BUF_SIZE 1528U /* ETH Max buffer size for transmit */ -#define ETH_RXBUFNB 4U /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ -#define ETH_TXBUFNB 4U /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ - -/* Section 2: PHY configuration section */ - -/* DP83848 PHY Address*/ -#define DP83848_PHY_ADDRESS 0x01U -/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ -#define PHY_RESET_DELAY 0x000000FFU -/* PHY Configuration delay */ -#define PHY_CONFIG_DELAY 0x00000FFFU - -#define PHY_READ_TO 0x0000FFFFU -#define PHY_WRITE_TO 0x0000FFFFU - -/* Section 3: Common PHY Registers */ - -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ - -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ - -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -/* Section 4: Extended PHY Registers */ - -#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ -#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ -#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ - -#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ -#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ - -#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ -#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ - -#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ -#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ - -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver -* Activated: CRC code is present inside driver -* Deactivated: CRC code cleaned from driver -*/ - -#define USE_SPI_CRC 1U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED - #include "stm32f7xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32f7xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED - #include "stm32f7xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32f7xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED - #include "stm32f7xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_CAN_MODULE_ENABLED - #include "stm32f7xx_hal_can.h" -#endif /* HAL_CAN_MODULE_ENABLED */ - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #include "stm32f7xx_hal_can_legacy.h" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_CEC_MODULE_ENABLED - #include "stm32f7xx_hal_cec.h" -#endif /* HAL_CEC_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED - #include "stm32f7xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32f7xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED - #include "stm32f7xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED - #include "stm32f7xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED - #include "stm32f7xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_ETH_MODULE_ENABLED - #include "stm32f7xx_hal_eth.h" -#endif /* HAL_ETH_MODULE_ENABLED */ - -#ifdef HAL_ETH_LEGACY_MODULE_ENABLED - #include "stm32f7xx_hal_eth_legacy.h" -#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32f7xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32f7xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED - #include "stm32f7xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED - #include "stm32f7xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - #include "stm32f7xx_hal_sdram.h" -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED - #include "stm32f7xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED - #include "stm32f7xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_I2S_MODULE_ENABLED - #include "stm32f7xx_hal_i2s.h" -#endif /* HAL_I2S_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32f7xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32f7xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED - #include "stm32f7xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED - #include "stm32f7xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_QSPI_MODULE_ENABLED - #include "stm32f7xx_hal_qspi.h" -#endif /* HAL_QSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED - #include "stm32f7xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED - #include "stm32f7xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED - #include "stm32f7xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED - #include "stm32f7xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED - #include "stm32f7xx_hal_spdifrx.h" -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED - #include "stm32f7xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED - #include "stm32f7xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED - #include "stm32f7xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED - #include "stm32f7xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32f7xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32f7xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32f7xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED - #include "stm32f7xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED - #include "stm32f7xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_DFSDM_MODULE_ENABLED - #include "stm32f7xx_hal_dfsdm.h" -#endif /* HAL_DFSDM_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED - #include "stm32f7xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_JPEG_MODULE_ENABLED - #include "stm32f7xx_hal_jpeg.h" -#endif /* HAL_JPEG_MODULE_ENABLED */ - -#ifdef HAL_MDIOS_MODULE_ENABLED - #include "stm32f7xx_hal_mdios.h" -#endif /* HAL_MDIOS_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32f7xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED - #include "stm32f7xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ - #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CONF_H */ - - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h index 61907ece..18eb0a20 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cortex.h @@ -1,406 +1,406 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CORTEX_H -#define __STM32F7xx_HAL_CORTEX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Types Cortex Exported Types - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @brief MPU Region initialization structure - * @{ - */ -typedef struct -{ - uint8_t Enable; /*!< Specifies the status of the region. - This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the number of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint8_t Size; /*!< Specifies the size of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Size */ - uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint8_t TypeExtField; /*!< Specifies the TEX field level. - This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. - This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. - This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ - uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. - This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ - uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ -}MPU_Region_InitTypeDef; -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ -#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority - 1 bits for subpriority */ -#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority - 0 bits for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) -#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) - -/** - * @} - */ - -#if (__MPU_PRESENT == 1) -/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) -#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) -#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) -#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable - * @{ - */ -#define MPU_REGION_ENABLE ((uint8_t)0x01U) -#define MPU_REGION_DISABLE ((uint8_t)0x00U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access - * @{ - */ -#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) -#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable - * @{ - */ -#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) -#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable - * @{ - */ -#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) -#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable - * @{ - */ -#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) -#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels - * @{ - */ -#define MPU_TEX_LEVEL0 ((uint8_t)0x00U) -#define MPU_TEX_LEVEL1 ((uint8_t)0x01U) -#define MPU_TEX_LEVEL2 ((uint8_t)0x02U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size - * @{ - */ -#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) -#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) -#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) -#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) -#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) -#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) -#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) -#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) -#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) -#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) -#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) -#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) -#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) -#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) -#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) -#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) -#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) -#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) -#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) -#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) -#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) -#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) -#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) -#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) -#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) -#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) -#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) -#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes - * @{ - */ -#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) -#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) -#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) -#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) -#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) -#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number - * @{ - */ -#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) -#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) -#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) -#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) -#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) -#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) -#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) -#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) -/** - * @} - */ -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - - -/* Exported Macros -----------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -#if (__MPU_PRESENT == 1) -void HAL_MPU_Enable(uint32_t MPU_Control); -void HAL_MPU_Disable(void); -void HAL_MPU_EnableRegion(uint32_t RegionNumber); -void HAL_MPU_DisableRegion(uint32_t RegionNumber); -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); -#endif /* __MPU_PRESENT */ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) - -#if (__MPU_PRESENT == 1) -#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ - ((STATE) == MPU_REGION_DISABLE)) - -#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ - ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) - -#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) - -#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ - ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) - -#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ - ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) - -#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ - ((TYPE) == MPU_TEX_LEVEL1) || \ - ((TYPE) == MPU_TEX_LEVEL2)) - -#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RW) || \ - ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ - ((TYPE) == MPU_REGION_FULL_ACCESS) || \ - ((TYPE) == MPU_REGION_PRIV_RO) || \ - ((TYPE) == MPU_REGION_PRIV_RO_URO)) - -#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ - ((NUMBER) == MPU_REGION_NUMBER1) || \ - ((NUMBER) == MPU_REGION_NUMBER2) || \ - ((NUMBER) == MPU_REGION_NUMBER3) || \ - ((NUMBER) == MPU_REGION_NUMBER4) || \ - ((NUMBER) == MPU_REGION_NUMBER5) || \ - ((NUMBER) == MPU_REGION_NUMBER6) || \ - ((NUMBER) == MPU_REGION_NUMBER7)) - -#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ - ((SIZE) == MPU_REGION_SIZE_64B) || \ - ((SIZE) == MPU_REGION_SIZE_128B) || \ - ((SIZE) == MPU_REGION_SIZE_256B) || \ - ((SIZE) == MPU_REGION_SIZE_512B) || \ - ((SIZE) == MPU_REGION_SIZE_1KB) || \ - ((SIZE) == MPU_REGION_SIZE_2KB) || \ - ((SIZE) == MPU_REGION_SIZE_4KB) || \ - ((SIZE) == MPU_REGION_SIZE_8KB) || \ - ((SIZE) == MPU_REGION_SIZE_16KB) || \ - ((SIZE) == MPU_REGION_SIZE_32KB) || \ - ((SIZE) == MPU_REGION_SIZE_64KB) || \ - ((SIZE) == MPU_REGION_SIZE_128KB) || \ - ((SIZE) == MPU_REGION_SIZE_256KB) || \ - ((SIZE) == MPU_REGION_SIZE_512KB) || \ - ((SIZE) == MPU_REGION_SIZE_1MB) || \ - ((SIZE) == MPU_REGION_SIZE_2MB) || \ - ((SIZE) == MPU_REGION_SIZE_4MB) || \ - ((SIZE) == MPU_REGION_SIZE_8MB) || \ - ((SIZE) == MPU_REGION_SIZE_16MB) || \ - ((SIZE) == MPU_REGION_SIZE_32MB) || \ - ((SIZE) == MPU_REGION_SIZE_64MB) || \ - ((SIZE) == MPU_REGION_SIZE_128MB) || \ - ((SIZE) == MPU_REGION_SIZE_256MB) || \ - ((SIZE) == MPU_REGION_SIZE_512MB) || \ - ((SIZE) == MPU_REGION_SIZE_1GB) || \ - ((SIZE) == MPU_REGION_SIZE_2GB) || \ - ((SIZE) == MPU_REGION_SIZE_4GB)) - -#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) -#endif /* __MPU_PRESENT */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CORTEX_H */ - - +/** + ****************************************************************************** + * @file stm32f7xx_hal_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CORTEX_H +#define __STM32F7xx_HAL_CORTEX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup CORTEX + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup CORTEX_Exported_Types Cortex Exported Types + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition + * @brief MPU Region initialization structure + * @{ + */ +typedef struct +{ + uint8_t Enable; /*!< Specifies the status of the region. + This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ + uint8_t Number; /*!< Specifies the number of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Number */ + uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ + uint8_t Size; /*!< Specifies the size of the region to protect. + This parameter can be a value of @ref CORTEX_MPU_Region_Size */ + uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + uint8_t TypeExtField; /*!< Specifies the TEX field level. + This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. + This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ + uint8_t DisableExec; /*!< Specifies the instruction access status. + This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ + uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ + uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. + This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ + uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. + This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ +}MPU_Region_InitTypeDef; +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group + * @{ + */ +#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ +/** + * @} + */ + +/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source + * @{ + */ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) +#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) + +/** + * @} + */ + +#if (__MPU_PRESENT == 1) +/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control + * @{ + */ +#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) +#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) +#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) +#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable + * @{ + */ +#define MPU_REGION_ENABLE ((uint8_t)0x01U) +#define MPU_REGION_DISABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access + * @{ + */ +#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) +#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable + * @{ + */ +#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable + * @{ + */ +#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable + * @{ + */ +#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) +#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels + * @{ + */ +#define MPU_TEX_LEVEL0 ((uint8_t)0x00U) +#define MPU_TEX_LEVEL1 ((uint8_t)0x01U) +#define MPU_TEX_LEVEL2 ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32B ((uint8_t)0x04U) +#define MPU_REGION_SIZE_64B ((uint8_t)0x05U) +#define MPU_REGION_SIZE_128B ((uint8_t)0x06U) +#define MPU_REGION_SIZE_256B ((uint8_t)0x07U) +#define MPU_REGION_SIZE_512B ((uint8_t)0x08U) +#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) +#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) +#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) +#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) +#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) +#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) +#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) +#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) +#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) +#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) +#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) +#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) +#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) +#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) +#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) +#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) +#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) +#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) +#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) +#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) +#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) +#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) +#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes + * @{ + */ +#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) +#define MPU_REGION_PRIV_RW ((uint8_t)0x01U) +#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) +#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) +#define MPU_REGION_PRIV_RO ((uint8_t)0x05U) +#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) +/** + * @} + */ + +/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number + * @{ + */ +#define MPU_REGION_NUMBER0 ((uint8_t)0x00U) +#define MPU_REGION_NUMBER1 ((uint8_t)0x01U) +#define MPU_REGION_NUMBER2 ((uint8_t)0x02U) +#define MPU_REGION_NUMBER3 ((uint8_t)0x03U) +#define MPU_REGION_NUMBER4 ((uint8_t)0x04U) +#define MPU_REGION_NUMBER5 ((uint8_t)0x05U) +#define MPU_REGION_NUMBER6 ((uint8_t)0x06U) +#define MPU_REGION_NUMBER7 ((uint8_t)0x07U) +/** + * @} + */ +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + + +/* Exported Macros -----------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CORTEX_Exported_Functions + * @{ + */ + +/** @addtogroup CORTEX_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); +void HAL_NVIC_SystemReset(void); +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); +/** + * @} + */ + +/** @addtogroup CORTEX_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ***********************************************/ +#if (__MPU_PRESENT == 1) +void HAL_MPU_Enable(uint32_t MPU_Control); +void HAL_MPU_Disable(void); +void HAL_MPU_EnableRegion(uint32_t RegionNumber); +void HAL_MPU_DisableRegion(uint32_t RegionNumber); +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); +#endif /* __MPU_PRESENT */ +uint32_t HAL_NVIC_GetPriorityGrouping(void); +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); +void HAL_SYSTICK_IRQHandler(void); +void HAL_SYSTICK_Callback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup CORTEX_Private_Macros CORTEX Private Macros + * @{ + */ +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ + ((GROUP) == NVIC_PRIORITYGROUP_1) || \ + ((GROUP) == NVIC_PRIORITYGROUP_2) || \ + ((GROUP) == NVIC_PRIORITYGROUP_3) || \ + ((GROUP) == NVIC_PRIORITYGROUP_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) + +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ + ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) + +#if (__MPU_PRESENT == 1) +#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ + ((STATE) == MPU_REGION_DISABLE)) + +#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ + ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) + +#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ + ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) + +#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ + ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) + +#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ + ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) + +#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ + ((TYPE) == MPU_TEX_LEVEL1) || \ + ((TYPE) == MPU_TEX_LEVEL2)) + +#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RW) || \ + ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ + ((TYPE) == MPU_REGION_FULL_ACCESS) || \ + ((TYPE) == MPU_REGION_PRIV_RO) || \ + ((TYPE) == MPU_REGION_PRIV_RO_URO)) + +#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ + ((NUMBER) == MPU_REGION_NUMBER1) || \ + ((NUMBER) == MPU_REGION_NUMBER2) || \ + ((NUMBER) == MPU_REGION_NUMBER3) || \ + ((NUMBER) == MPU_REGION_NUMBER4) || \ + ((NUMBER) == MPU_REGION_NUMBER5) || \ + ((NUMBER) == MPU_REGION_NUMBER6) || \ + ((NUMBER) == MPU_REGION_NUMBER7)) + +#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ + ((SIZE) == MPU_REGION_SIZE_64B) || \ + ((SIZE) == MPU_REGION_SIZE_128B) || \ + ((SIZE) == MPU_REGION_SIZE_256B) || \ + ((SIZE) == MPU_REGION_SIZE_512B) || \ + ((SIZE) == MPU_REGION_SIZE_1KB) || \ + ((SIZE) == MPU_REGION_SIZE_2KB) || \ + ((SIZE) == MPU_REGION_SIZE_4KB) || \ + ((SIZE) == MPU_REGION_SIZE_8KB) || \ + ((SIZE) == MPU_REGION_SIZE_16KB) || \ + ((SIZE) == MPU_REGION_SIZE_32KB) || \ + ((SIZE) == MPU_REGION_SIZE_64KB) || \ + ((SIZE) == MPU_REGION_SIZE_128KB) || \ + ((SIZE) == MPU_REGION_SIZE_256KB) || \ + ((SIZE) == MPU_REGION_SIZE_512KB) || \ + ((SIZE) == MPU_REGION_SIZE_1MB) || \ + ((SIZE) == MPU_REGION_SIZE_2MB) || \ + ((SIZE) == MPU_REGION_SIZE_4MB) || \ + ((SIZE) == MPU_REGION_SIZE_8MB) || \ + ((SIZE) == MPU_REGION_SIZE_16MB) || \ + ((SIZE) == MPU_REGION_SIZE_32MB) || \ + ((SIZE) == MPU_REGION_SIZE_64MB) || \ + ((SIZE) == MPU_REGION_SIZE_128MB) || \ + ((SIZE) == MPU_REGION_SIZE_256MB) || \ + ((SIZE) == MPU_REGION_SIZE_512MB) || \ + ((SIZE) == MPU_REGION_SIZE_1GB) || \ + ((SIZE) == MPU_REGION_SIZE_2GB) || \ + ((SIZE) == MPU_REGION_SIZE_4GB)) + +#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) +#endif /* __MPU_PRESENT */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CORTEX_H */ + + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h deleted file mode 100644 index 865e3425..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc.h +++ /dev/null @@ -1,342 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_crc.h - * @author MCD Application Team - * @brief Header file of CRC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_CRC_H -#define STM32F7xx_HAL_CRC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup CRC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CRC_Exported_Types CRC Exported Types - * @{ - */ - -/** - * @brief CRC HAL State Structure definition - */ -typedef enum -{ - HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */ - HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */ - HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */ -} HAL_CRC_StateTypeDef; - -/** - * @brief CRC Init Structure definition - */ -typedef struct -{ - uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used. - If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default - X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + - X^4 + X^2+ X +1. - In that case, there is no need to set GeneratingPolynomial field. - If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and - CRCLength fields must be set. */ - - uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used. - If set to DEFAULT_INIT_VALUE_ENABLE, resort to default - 0xFFFFFFFF value. In that case, there is no need to set InitValue field. If - otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */ - - uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree - respectively equal to 7, 8, 16 or 32. This field is written in normal, - representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 - is written 0x65. No need to specify it if DefaultPolynomialUse is set to - DEFAULT_POLYNOMIAL_ENABLE. */ - - uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. - Value can be either one of - @arg @ref CRC_POLYLENGTH_32B (32-bit CRC), - @arg @ref CRC_POLYLENGTH_16B (16-bit CRC), - @arg @ref CRC_POLYLENGTH_8B (8-bit CRC), - @arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */ - - uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse - is set to DEFAULT_INIT_VALUE_ENABLE. */ - - uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. - Can be either one of the following values - @arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion - @arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D - becomes 0x58D43CB2 - @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, - 0x1A2B3C4D becomes 0xD458B23C - @arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D - becomes 0xB23CD458 */ - - uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. - Can be either - @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, - @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted - into 0x22CC4488 */ -} CRC_InitTypeDef; - -/** - * @brief CRC Handle Structure definition - */ -typedef struct -{ - CRC_TypeDef *Instance; /*!< Register base address */ - - CRC_InitTypeDef Init; /*!< CRC configuration parameters */ - - HAL_LockTypeDef Lock; /*!< CRC Locking object */ - - __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ - - uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. - Can be either - @arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes - (8-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of - half-words (16-bit data) - @arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words - (32-bit data) - - Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization - error must occur if InputBufferFormat is not one of the three values listed - above */ -} CRC_HandleTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRC_Exported_Constants CRC Exported Constants - * @{ - */ - -/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial - * @{ - */ -#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */ -/** - * @} - */ - -/** @defgroup CRC_Default_InitValue Default CRC computation initialization value - * @{ - */ -#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */ -/** - * @} - */ - -/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used - * @{ - */ -#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */ -#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */ -/** - * @} - */ - -/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used - * @{ - */ -#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */ -#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */ -/** - * @} - */ - -/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral - * @{ - */ -#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */ -#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */ -#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */ -#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */ -/** - * @} - */ - -/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions - * @{ - */ -#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */ -#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */ -#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */ -#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */ -/** - * @} - */ - -/** @defgroup CRC_Input_Buffer_Format Input Buffer Format - * @{ - */ -/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but - * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set - * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for - * the CRC APIs to provide a correct result */ -#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */ -#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */ -#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */ -#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CRC_Exported_Macros CRC Exported Macros - * @{ - */ - -/** @brief Reset CRC handle state. - * @param __HANDLE__ CRC handle. - * @retval None - */ -#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) - -/** - * @brief Reset CRC Data Register. - * @param __HANDLE__ CRC handle - * @retval None - */ -#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) - -/** - * @brief Set CRC INIT non-default value - * @param __HANDLE__ CRC handle - * @param __INIT__ 32-bit initial value - * @retval None - */ -#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) - -/** - * @brief Store data in the Independent Data (ID) register. - * @param __HANDLE__ CRC handle - * @param __VALUE__ Value to be stored in the ID register - * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits - * @retval None - */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) - -/** - * @brief Return the data stored in the Independent Data (ID) register. - * @param __HANDLE__ CRC handle - * @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits - * @retval Value of the ID register - */ -#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) -/** - * @} - */ - - -/* Private macros --------------------------------------------------------*/ -/** @defgroup CRC_Private_Macros CRC Private Macros - * @{ - */ - -#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ - ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) - -#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ - ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) - -#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ - ((LENGTH) == CRC_POLYLENGTH_16B) || \ - ((LENGTH) == CRC_POLYLENGTH_8B) || \ - ((LENGTH) == CRC_POLYLENGTH_7B)) - -#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ - ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ - ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) - -/** - * @} - */ - -/* Include CRC HAL Extended module */ -#include "stm32f7xx_hal_crc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CRC_Exported_Functions CRC Exported Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); -HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc); -void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); -void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); -/** - * @} - */ - -/* Peripheral Control functions ***********************************************/ -/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); -/** - * @} - */ - -/* Peripheral State and Error functions ***************************************/ -/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @{ - */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_CRC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h deleted file mode 100644 index 760e7fcb..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_crc_ex.h +++ /dev/null @@ -1,150 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_crc_ex.h - * @author MCD Application Team - * @brief Header file of CRC HAL extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_CRC_EX_H -#define STM32F7xx_HAL_CRC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup CRCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants - * @{ - */ - -/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes - * @{ - */ -#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */ -#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */ -#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */ -/** - * @} - */ - -/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes - * @{ - */ -#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */ -#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros - * @{ - */ - -/** - * @brief Set CRC output reversal - * @param __HANDLE__ CRC handle - * @retval None - */ -#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) - -/** - * @brief Unset CRC output reversal - * @param __HANDLE__ CRC handle - * @retval None - */ -#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) - -/** - * @brief Set CRC non-default polynomial - * @param __HANDLE__ CRC handle - * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial - * @retval None - */ -#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros - * @{ - */ - -#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ - ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ - ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ - ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) - -#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ - ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup CRCEx_Exported_Functions - * @{ - */ - -/** @addtogroup CRCEx_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); -HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); -HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_CRC_EX_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h deleted file mode 100644 index 1dd17c93..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp.h +++ /dev/null @@ -1,671 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cryp.h - * @author MCD Application Team - * @brief Header file of CRYP HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CRYP_H -#define __STM32F7xx_HAL_CRYP_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (AES) || defined (CRYP) -/** @addtogroup CRYP - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Types CRYP Exported Types - * @{ - */ - -/** - * @brief CRYP Init Structure definition - */ - -typedef struct -{ - uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. - This parameter can be a value of @ref CRYP_Data_Type */ - uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. - 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */ - uint32_t *pKey; /*!< The key used for encryption/decryption */ - uint32_t *pInitVect; /*!< The initialization vector used also as initialization - counter in CTR mode */ - uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC - AES Algorithm ECB/CBC/CTR/GCM or CCM - This parameter can be a value of @ref CRYP_Algorithm_Mode */ - uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication, - GCM : also known as Additional Authentication Data - CCM : named B1 composed of the associated data length and Associated Data. */ - uint32_t HeaderSize; /*!< The size of header buffer in word */ - uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */ - uint32_t DataWidthUnit; /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/ - uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/ - uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization - Vector only once and to skip configuration for consecutive processings. - This parameter can be a value of @ref CRYP_Configuration_Skip */ - -} CRYP_ConfigTypeDef; - - -/** - * @brief CRYP State Structure definition - */ - -typedef enum -{ - HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */ - HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */ - HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */ -} HAL_CRYP_STATETypeDef; - - -/** - * @brief CRYP handle Structure definition - */ - -typedef struct __CRYP_HandleTypeDef -{ -#if defined (CRYP) - CRYP_TypeDef *Instance; /*!< CRYP registers base address */ -#else /* AES*/ - AES_TypeDef *Instance; /*!< AES Register base address */ -#endif /* End AES or CRYP */ - - CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */ - - FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allows to bypass or not key write-up before decryption. - This parameter can be a value of ENABLE/DISABLE */ - - uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - - uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - - __IO uint16_t CrypHeaderCount; /*!< Counter of header data */ - - __IO uint16_t CrypInCount; /*!< Counter of input data */ - - __IO uint16_t CrypOutCount; /*!< Counter of output data */ - - uint16_t Size; /*!< length of input data in word */ - - uint32_t Phase; /*!< CRYP peripheral phase */ - - DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ - - DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< CRYP locking object */ - - __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ - - __IO uint32_t ErrorCode; /*!< CRYP peripheral error code */ - - uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when - configuration can be skipped */ - - uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored - for a single signature computation after several - messages processing */ - -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */ - void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */ - void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */ - - void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */ - void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */ - -#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ -} CRYP_HandleTypeDef; - - -/** - * @} - */ - -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) -/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition - * @brief HAL CRYP Callback ID enumeration definition - * @{ - */ -typedef enum -{ - HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x01U, /*!< CRYP Input FIFO transfer completed callback ID */ - HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Output FIFO transfer completed callback ID */ - HAL_CRYP_ERROR_CB_ID = 0x03U, /*!< CRYP Error callback ID */ - - HAL_CRYP_MSPINIT_CB_ID = 0x04U, /*!< CRYP MspInit callback ID */ - HAL_CRYP_MSPDEINIT_CB_ID = 0x05U /*!< CRYP MspDeInit callback ID */ - -} HAL_CRYP_CallbackIDTypeDef; -/** - * @} - */ - -/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition - * @brief HAL CRYP Callback pointer definition - * @{ - */ - -typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */ - -/** - * @} - */ - -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRYP_Exported_Constants CRYP Exported Constants - * @{ - */ - -/** @defgroup CRYP_Error_Definition CRYP Error Definition - * @{ - */ -#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */ -#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */ -#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */ -#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */ -#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */ -#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */ -#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) -#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */ -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit - * @{ - */ - -#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */ -#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is word */ - -/** - * @} - */ - -/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit - * @{ - */ - -#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */ -#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */ - -/** - * @} - */ - -/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode - * @{ - */ -#if defined(CRYP) - -#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB -#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC -#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB -#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC -#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB -#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC -#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR - -#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM -#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM - -#else /* AES*/ -#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */ -#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */ -#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */ -#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */ -#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */ -#endif /* End AES or CRYP */ - -/** - * @} - */ - -/** @defgroup CRYP_Key_Size CRYP Key Size - * @{ - */ -#if defined(CRYP) -#define CRYP_KEYSIZE_128B 0x00000000U -#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0 -#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1 -#else /* AES*/ -#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */ -#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */ -#endif /* End AES or CRYP */ -/** - * @} - */ - -/** @defgroup CRYP_Data_Type CRYP Data Type - * @{ - */ -#if defined(CRYP) -#define CRYP_DATATYPE_32B 0x00000000U -#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0 -#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1 -#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE -#else /* AES*/ -#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */ -#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */ -#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */ -#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */ -#endif /* End AES or CRYP */ - -/** - * @} - */ - -/** @defgroup CRYP_Interrupt CRYP Interrupt - * @{ - */ -#if defined (CRYP) -#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */ -#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */ -#else /* AES*/ -#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */ -#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */ -#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */ -#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */ -#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */ -#endif /* End AES or CRYP */ - -/** - * @} - */ - -/** @defgroup CRYP_Flags CRYP Flags - * @{ - */ -#if defined (CRYP) -/* Flags in the SR register */ -#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< Input FIFO is empty */ -#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< Input FIFO is not Full */ -#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< Output FIFO is not empty */ -#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< Output FIFO is Full */ -#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP core is currently processing a block of data - or a key preparation (for AES decryption). */ -/* Flags in the RISR register */ -#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */ -#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/ -#else /* AES*/ -/* status flags */ -#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */ -#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */ -#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */ -#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */ -/* clearing flags */ -#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */ -#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */ -#endif /* End AES or CRYP */ - -/** - * @} - */ - -/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode - * @{ - */ - -#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */ -#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */ - -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CRYP_Exported_Macros CRYP Exported Macros - * @{ - */ - -/** @brief Reset CRYP handle state - * @param __HANDLE__ specifies the CRYP handle. - * @retval None - */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) -#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0) -#else -#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET) -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - -/** - * @brief Enable/Disable the CRYP peripheral. - * @param __HANDLE__: specifies the CRYP handle. - * @retval None - */ -#if defined(CRYP) -#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN) -#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN) -#else /* AES*/ -#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN) -#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN) -#endif /* End AES or CRYP */ - -/** @brief Check whether the specified CRYP status flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values for TinyAES: - * @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden - * @arg @ref CRYP_IT_WRERR Write Error - * @arg @ref CRYP_IT_RDERR Read Error - * @arg @ref CRYP_IT_CCF Computation Complete - * This parameter can be one of the following values for CRYP: - * @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data - * or a key preparation (for AES decryption). - * @arg CRYP_FLAG_IFEM: Input FIFO is empty - * @arg CRYP_FLAG_IFNF: Input FIFO is not full - * @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending - * @arg CRYP_FLAG_OFNE: Output FIFO is not empty - * @arg CRYP_FLAG_OFFU: Output FIFO is full - * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending - * @retval The state of __FLAG__ (TRUE or FALSE). - */ -#define CRYP_FLAG_MASK 0x0000001FU -#if defined(CRYP) -#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \ - ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK))) -#else /* AES*/ -#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) -#endif /* End AES or CRYP */ - -/** @brief Clear the CRYP pending status flag. - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear - * @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear - * @param __HANDLE__: specifies the CRYP handle. - * @retval None - */ - -#if defined(AES) -#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__)) - - -/** @brief Check whether the specified CRYP interrupt source is enabled or not. - * @param __INTERRUPT__: CRYP interrupt source to check - * This parameter can be one of the following values for TinyAES: - * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt - * @param __HANDLE__: specifies the CRYP handle. - * @retval State of interruption (TRUE or FALSE). - */ - -#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ - & (__INTERRUPT__)) == (__INTERRUPT__)) - -#endif /* AES */ - -/** @brief Check whether the specified CRYP interrupt is set or not. - * @param __INTERRUPT__: specifies the interrupt to check. - * This parameter can be one of the following values for TinyAES: - * @arg @ref CRYP_IT_WRERR Write Error - * @arg @ref CRYP_IT_RDERR Read Error - * @arg @ref CRYP_IT_CCF Computation Complete - * This parameter can be one of the following values for CRYP: - * @arg CRYP_IT_INI: Input FIFO service masked interrupt status - * @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status - * @param __HANDLE__: specifies the CRYP handle. - * @retval The state of __INTERRUPT__ (TRUE or FALSE). - */ -#if defined(CRYP) -#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR\ - & (__INTERRUPT__)) == (__INTERRUPT__)) -#else /* AES*/ -#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) -#endif /* End AES or CRYP */ - -/** - * @brief Enable the CRYP interrupt. - * @param __INTERRUPT__: CRYP Interrupt. - * This parameter can be one of the following values for TinyAES: - * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt - * This parameter can be one of the following values for CRYP: - * @ CRYP_IT_INI : Input FIFO service interrupt mask. - * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. - * @retval None - */ -#if defined(CRYP) -#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__)) -#else /* AES*/ -#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) -#endif /* End AES or CRYP */ - -/** - * @brief Disable the CRYP interrupt. - * @param __INTERRUPT__: CRYP Interrupt. - * This parameter can be one of the following values for TinyAES: - * @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR) - * @arg @ref CRYP_IT_CCFIE Computation Complete interrupt - * This parameter can be one of the following values for CRYP: - * @ CRYP_IT_INI : Input FIFO service interrupt mask. - * @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt. - * @param __HANDLE__: specifies the CRYP handle. - * @retval None - */ -#if defined(CRYP) -#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__)) -#else /* AES*/ -#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) -#endif /* End AES or CRYP */ - -/** - * @} - */ -/* Include CRYP HAL Extended module */ -#include "stm32f7xx_hal_cryp_ex.h" -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CRYP_Exported_Functions CRYP Exported Functions - * @{ - */ - -/** @addtogroup CRYP_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); -HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); -HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); -HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, - pCRYP_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup CRYP_Exported_Functions_Group2 - * @{ - */ - -/* encryption/decryption ***********************************/ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, - uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, - uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); -HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); -HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); -HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); - -/** - * @} - */ - - -/** @addtogroup CRYP_Exported_Functions_Group3 - * @{ - */ -/* Interrupt Handler functions **********************************************/ -void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); - -/** - * @} - */ - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup CRYP_Private_Macros CRYP Private Macros - * @{ - */ - -/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters - * @{ - */ -#if defined(CRYP) -#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \ - ((ALGORITHM) == CRYP_DES_CBC) || \ - ((ALGORITHM) == CRYP_TDES_ECB) || \ - ((ALGORITHM) == CRYP_TDES_CBC) || \ - ((ALGORITHM) == CRYP_AES_ECB) || \ - ((ALGORITHM) == CRYP_AES_CBC) || \ - ((ALGORITHM) == CRYP_AES_CTR) || \ - ((ALGORITHM) == CRYP_AES_GCM) || \ - ((ALGORITHM) == CRYP_AES_CCM)) -#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ - ((KEYSIZE) == CRYP_KEYSIZE_192B) || \ - ((KEYSIZE) == CRYP_KEYSIZE_256B)) -#else /* AES*/ -#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \ - ((ALGORITHM) == CRYP_AES_CBC) || \ - ((ALGORITHM) == CRYP_AES_CTR) || \ - ((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \ - ((ALGORITHM) == CRYP_AES_CCM)) - - -#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \ - ((KEYSIZE) == CRYP_KEYSIZE_256B)) -#endif /* End AES or CRYP */ - -#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \ - ((DATATYPE) == CRYP_DATATYPE_16B) || \ - ((DATATYPE) == CRYP_DATATYPE_8B) || \ - ((DATATYPE) == CRYP_DATATYPE_1B)) - -#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ - ((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) -/** - * @} - */ - -/** - * @} - */ - - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CRYP_Private_Constants CRYP Private Constants - * @{ - */ - -/** - * @} - */ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup CRYP_Private_Defines CRYP Private Defines - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup CRYP_Private_Variables CRYP Private Variables - * @{ - */ - -/** - * @} - */ -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CRYP_Private_Functions CRYP Private Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - - -/** - * @} - */ -#endif /* TinyAES or CRYP*/ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CRYP_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h deleted file mode 100644 index 23aee6ca..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_cryp_ex.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cryp_ex.h - * @author MCD Application Team - * @brief Header file of CRYP HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_CRYP_EX_H -#define __STM32F7xx_HAL_CRYP_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup CRYPEx - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CRYPEx_Exported_Types CRYPEx Exported types - * @{ - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRYPEx_Exported_Constants CRYPEx Exported constants - * @{ - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup CRYPEx_Private_Types CRYPEx Private Types - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions - * @{ - */ -#if defined (CRYP) || defined (AES) -/** @addtogroup CRYPEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -/** - * @} - */ -#endif /* CRYP||AES */ - -#if defined (AES) -/** @addtogroup CRYPEx_Exported_Functions_Group2 - * @{ - */ -void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp); -void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp); -/** - * @} - */ -#endif /* AES */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_CRYP_EX_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h deleted file mode 100644 index 5a5c2fa1..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac.h +++ /dev/null @@ -1,474 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dac.h - * @author MCD Application Team - * @brief Header file of DAC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_DAC_H -#define STM32F7xx_HAL_DAC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined(DAC) - -/** @addtogroup DAC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Types DAC Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ - HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ - HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ - HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ - HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ - -} HAL_DAC_StateTypeDef; - -/** - * @brief DAC handle Structure definition - */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) -typedef struct __DAC_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ -{ - DAC_TypeDef *Instance; /*!< Register base address */ - - __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ - - HAL_LockTypeDef Lock; /*!< DAC locking object */ - - DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ - - DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ - - __IO uint32_t ErrorCode; /*!< DAC Error code */ - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - - void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - - - void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - -} DAC_HandleTypeDef; - -/** - * @brief DAC Configuration regular Channel structure definition - */ -typedef struct -{ - uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. - This parameter can be a value of @ref DAC_trigger_selection */ - - uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. - This parameter can be a value of @ref DAC_output_buffer */ - -} DAC_ChannelConfTypeDef; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL DAC Callback ID enumeration definition - */ -typedef enum -{ - HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ - HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ - HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ - HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ - - HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ - HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ - HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ - HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ - - HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ - HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ - HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ -} HAL_DAC_CallbackIDTypeDef; - -/** - * @brief HAL DAC Callback pointer definition - */ -typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Constants DAC Exported Constants - * @{ - */ - -/** @defgroup DAC_Error_Code DAC Error Code - * @{ - */ -#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ -#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ -#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) -#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup DAC_trigger_selection DAC trigger selection - * @{ - */ -#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T2_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1 | DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ - -/** - * @} - */ - -/** @defgroup DAC_output_buffer DAC output buffer - * @{ - */ -#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U -#define DAC_OUTPUTBUFFER_DISABLE (DAC_CR_BOFF1) - -/** - * @} - */ - -/** @defgroup DAC_Channel_selection DAC Channel selection - * @{ - */ -#define DAC_CHANNEL_1 0x00000000U - -#define DAC_CHANNEL_2 0x00000010U - -/** - * @} - */ - -/** @defgroup DAC_data_alignment DAC data alignment - * @{ - */ -#define DAC_ALIGN_12B_R 0x00000000U -#define DAC_ALIGN_12B_L 0x00000004U -#define DAC_ALIGN_8B_R 0x00000008U - -/** - * @} - */ - -/** @defgroup DAC_flags_definition DAC flags definition - * @{ - */ -#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) - -#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) - - -/** - * @} - */ - -/** @defgroup DAC_IT_definition DAC IT definition - * @{ - */ -#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) - -#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) - - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Macros DAC Exported Macros - * @{ - */ - -/** @brief Reset DAC handle state. - * @param __HANDLE__ specifies the DAC handle. - * @retval None - */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) -#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - -/** @brief Enable the DAC channel. - * @param __HANDLE__ specifies the DAC handle. - * @param __DAC_Channel__ specifies the DAC channel - * @retval None - */ -#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ - ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) - -/** @brief Disable the DAC channel. - * @param __HANDLE__ specifies the DAC handle - * @param __DAC_Channel__ specifies the DAC channel. - * @retval None - */ -#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ - ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) - -/** @brief Set DHR12R1 alignment. - * @param __ALIGNMENT__ specifies the DAC alignment - * @retval None - */ -#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) - - -/** @brief Set DHR12R2 alignment. - * @param __ALIGNMENT__ specifies the DAC alignment - * @retval None - */ -#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) - - -/** @brief Set DHR12RD alignment. - * @param __ALIGNMENT__ specifies the DAC alignment - * @retval None - */ -#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) - -/** @brief Enable the DAC interrupt. - * @param __HANDLE__ specifies the DAC handle - * @param __INTERRUPT__ specifies the DAC interrupt. - * This parameter can be any combination of the following values: - * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt - * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt - * @retval None - */ -#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) - -/** @brief Disable the DAC interrupt. - * @param __HANDLE__ specifies the DAC handle - * @param __INTERRUPT__ specifies the DAC interrupt. - * This parameter can be any combination of the following values: - * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt - * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt - * @retval None - */ -#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) - -/** @brief Check whether the specified DAC interrupt source is enabled or not. - * @param __HANDLE__ DAC handle - * @param __INTERRUPT__ DAC interrupt source to check - * This parameter can be any combination of the following values: - * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt - * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt - * @retval State of interruption (SET or RESET) - */ -#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ - & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Get the selected DAC's flag status. - * @param __HANDLE__ specifies the DAC handle. - * @param __FLAG__ specifies the DAC flag to get. - * This parameter can be any combination of the following values: - * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag - * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag - * @retval None - */ -#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the DAC's flag. - * @param __HANDLE__ specifies the DAC handle. - * @param __FLAG__ specifies the DAC flag to clear. - * This parameter can be any combination of the following values: - * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag - * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag - * @retval None - */ -#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup DAC_Private_Macros DAC Private Macros - * @{ - */ -#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ - ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) - -#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ - ((CHANNEL) == DAC_CHANNEL_2)) - -#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ - ((ALIGN) == DAC_ALIGN_12B_L) || \ - ((ALIGN) == DAC_ALIGN_8B_R)) - -#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) - -/** - * @} - */ - -/* Include DAC HAL Extended module */ -#include "stm32f7xx_hal_dac_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup DAC_Exported_Functions - * @{ - */ - -/** @addtogroup DAC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); -void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); -void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); - -/** - * @} - */ - -/** @addtogroup DAC_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, - uint32_t Alignment); -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); -void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); - -void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); -void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); -void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); -void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) -/* DAC callback registering/unregistering */ -HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, - pDAC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup DAC_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel); -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, - const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup DAC_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac); -uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac); - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup DAC_Private_Functions DAC Private Functions - * @{ - */ -void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); -void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); -void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** - * @} - */ - -#endif /* DAC */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_DAC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h deleted file mode 100644 index bc538f22..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dac_ex.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dac_ex.h - * @author MCD Application Team - * @brief Header file of DAC HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_DAC_EX_H -#define STM32F7xx_HAL_DAC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined(DAC) - -/** @addtogroup DACEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL State structures definition - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DACEx_Exported_Constants DACEx Exported Constants - * @{ - */ - -/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude - * @{ - */ -#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ -#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ -#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ -#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */ -#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */ -#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ -#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */ -#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ -#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */ -#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ -#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */ -#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ -#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */ -#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ -#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */ - -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup DACEx_Private_Macros DACEx Private Macros - * @{ - */ -#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ - ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ - ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ - ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) - -#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ - ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ - ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/* Extended features functions ***********************************************/ - -/** @addtogroup DACEx_Exported_Functions - * @{ - */ - -/** @addtogroup DACEx_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ - -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude); - -HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac); -HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac); -HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); -uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac); - -void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac); -void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac); -void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac); -void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac); - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DACEx_Private_Functions - * @{ - */ - -/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */ -/* are called by HAL_DAC_Start_DMA */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DAC */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_DAC_EX_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h deleted file mode 100644 index 8ed970f8..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi.h +++ /dev/null @@ -1,701 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dcmi.h - * @author MCD Application Team - * @brief Header file of DCMI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_DCMI_H -#define STM32F7xx_HAL_DCMI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (DCMI) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup DCMI DCMI - * @brief DCMI HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DCMI_Exported_Types DCMI Exported Types - * @{ - */ -/** - * @brief HAL DCMI State structures definition - */ -typedef enum -{ - HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */ - HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */ - HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */ - HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */ - HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */ - HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */ -} HAL_DCMI_StateTypeDef; - -/** - * @brief DCMI Embedded Synchronisation CODE Init structure definition - */ -typedef struct -{ - uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */ - uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */ - uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */ - uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */ -} DCMI_CodesInitTypeDef; - -/** - * @brief DCMI Embedded Synchronisation UNMASK Init structure definition - */ -typedef struct -{ - uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */ - uint8_t LineStartUnmask; /*!< Specifies the line start delimiter unmask. */ - uint8_t LineEndUnmask; /*!< Specifies the line end delimiter unmask. */ - uint8_t FrameEndUnmask; /*!< Specifies the frame end delimiter unmask. */ -} DCMI_SyncUnmaskTypeDef; -/** - * @brief DCMI Init structure definition - */ -typedef struct -{ - uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded. - This parameter can be a value of @ref DCMI_Synchronization_Mode */ - - uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising. - This parameter can be a value of @ref DCMI_PIXCK_Polarity */ - - uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_VSYNC_Polarity */ - - uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low. - This parameter can be a value of @ref DCMI_HSYNC_Polarity */ - - uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4. - This parameter can be a value of @ref DCMI_Capture_Rate */ - - uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit. - This parameter can be a value of @ref DCMI_Extended_Data_Mode */ - - DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the - line/frame end delimiter */ - - uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. - This parameter can be a value of @ref DCMI_MODE_JPEG */ - -#ifdef DCMI_CR_BSM - uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface - This parameter can be a value of @ref DCMI_Byte_Select_Mode */ - - uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd - This parameter can be a value of @ref DCMI_Byte_Select_Start */ - - uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface - This parameter can be a value of @ref DCMI_Line_Select_Mode */ - - uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd - by the interface is even or odd - This parameter can be a value of @ref DCMI_Line_Select_Start */ -#endif -} DCMI_InitTypeDef; - -/** - * @brief DCMI handle Structure definition - */ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) -typedef struct __DCMI_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ -{ - DCMI_TypeDef *Instance; /*!< DCMI Register base address */ - - DCMI_InitTypeDef Init; /*!< DCMI parameters */ - - HAL_LockTypeDef Lock; /*!< DCMI locking object */ - - __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */ - - __IO uint32_t XferCount; /*!< DMA transfer counter */ - - __IO uint32_t XferSize; /*!< DMA transfer size */ - - uint32_t XferTransferNumber; /*!< DMA transfer number */ - - uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */ - - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */ - - __IO uint32_t ErrorCode; /*!< DCMI Error code */ - -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Frame Event Callback */ - void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Vsync Event Callback */ - void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Line Event Callback */ - void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Error Callback */ - void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp Init callback */ - void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi); /*!< DCMI Msp DeInit callback */ -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ -} DCMI_HandleTypeDef; - -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) -/** - * @brief HAL DCMI Callback ID enumeration definition - */ -typedef enum -{ - HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U, /*!< DCMI Frame Event Callback ID */ - HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U, /*!< DCMI Vsync Event Callback ID */ - HAL_DCMI_LINE_EVENT_CB_ID = 0x02U, /*!< DCMI Line Event Callback ID */ - HAL_DCMI_ERROR_CB_ID = 0x03U, /*!< DCMI Error Callback ID */ - HAL_DCMI_MSPINIT_CB_ID = 0x04U, /*!< DCMI MspInit callback ID */ - HAL_DCMI_MSPDEINIT_CB_ID = 0x05U /*!< DCMI MspDeInit callback ID */ - -} HAL_DCMI_CallbackIDTypeDef; - -/** - * @brief HAL DCMI Callback pointer definition - */ -typedef void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef *hdcmi); /*!< pointer to a DCMI callback function */ -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ - - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DCMI_Exported_Constants DCMI Exported Constants - * @{ - */ - -/** @defgroup DCMI_Error_Code DCMI Error Code - * @{ - */ -#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */ -#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */ -#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) -#define HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid callback error */ -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup DCMI_Capture_Mode DCMI Capture Mode - * @{ - */ -#define DCMI_MODE_CONTINUOUS (0x00000000U) /*!< The received data are transferred continuously - into the destination memory through the DMA */ -#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of - frame and then transfers a single frame - through the DMA */ -/** - * @} - */ - -/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode - * @{ - */ -#define DCMI_SYNCHRO_HARDWARE (0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop) - is synchronized with the HSYNC/VSYNC signals */ -#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized - with synchronization codes embedded in the data flow */ - -/** - * @} - */ - -/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity - * @{ - */ -#define DCMI_PCKPOLARITY_FALLING (0x00000000U) /*!< Pixel clock active on Falling edge */ -#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */ - -/** - * @} - */ - -/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity - * @{ - */ -#define DCMI_VSPOLARITY_LOW (0x00000000U) /*!< Vertical synchronization active Low */ -#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */ - -/** - * @} - */ - -/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity - * @{ - */ -#define DCMI_HSPOLARITY_LOW (0x00000000U) /*!< Horizontal synchronization active Low */ -#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */ - -/** - * @} - */ - -/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG - * @{ - */ -#define DCMI_JPEG_DISABLE (0x00000000U) /*!< Mode JPEG Disabled */ -#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */ - -/** - * @} - */ - -/** @defgroup DCMI_Capture_Rate DCMI Capture Rate - * @{ - */ -#define DCMI_CR_ALL_FRAME (0x00000000U) /*!< All frames are captured */ -#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */ -#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */ - -/** - * @} - */ - -/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode - * @{ - */ -#define DCMI_EXTEND_DATA_8B (0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */ -#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */ -#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */ -#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 |\ - DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */ - -/** - * @} - */ - -/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate - * @{ - */ -#define DCMI_WINDOW_COORDINATE (0x3FFFU) /*!< Window coordinate */ - -/** - * @} - */ - -/** @defgroup DCMI_Window_Height DCMI Window Height - * @{ - */ -#define DCMI_WINDOW_HEIGHT (0x1FFFU) /*!< Window Height */ - -/** - * @} - */ - -/** @defgroup DCMI_interrupt_sources DCMI interrupt sources - * @{ - */ -#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */ -#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */ -#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */ -#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */ -#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */ -/** - * @} - */ - -/** @defgroup DCMI_Flags DCMI Flags - * @{ - */ - -/** - * @brief DCMI SR register - */ -#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization - between lines) */ -#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization - between frames) */ -#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */ -/** - * @brief DCMI RIS register - */ -#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */ -#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */ -#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */ -#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */ -#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */ -/** - * @brief DCMI MIS register - */ -#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked - interrupt status */ -#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */ -#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */ -#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */ -#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */ -/** - * @} - */ - -/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode - * @{ - */ -#define DCMI_BSM_ALL (0x00000000U) /*!< Interface captures all received data */ -#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte - from the received data */ -#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */ -#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 |\ - DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */ - -/** - * @} - */ - -/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start - * @{ - */ -#define DCMI_OEBS_ODD (0x00000000U) /*!< Interface captures first data from the frame/line start, - second one being dropped */ -#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from - the frame/line start, first one being dropped */ - -/** - * @} - */ - -/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode - * @{ - */ -#define DCMI_LSM_ALL (0x00000000U) /*!< Interface captures all received lines */ -#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */ - -/** - * @} - */ - -/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start - * @{ - */ -#define DCMI_OELS_ODD (0x00000000U) /*!< Interface captures first line from the frame start, - second one being dropped */ -#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, - first one being dropped */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DCMI_Exported_Macros DCMI Exported Macros - * @{ - */ - -/** @brief Reset DCMI handle state - * @param __HANDLE__ specifies the DCMI handle. - * @retval None - */ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) -#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ - -/** - * @brief Enable the DCMI. - * @param __HANDLE__ DCMI handle - * @retval None - */ -#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) - -/** - * @brief Disable the DCMI. - * @param __HANDLE__ DCMI handle - * @retval None - */ -#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) - -/* Interrupt & Flag management */ -/** - * @brief Get the DCMI pending flag. - * @param __HANDLE__ DCMI handle - * @param __FLAG__ Get the specified flag. - * This parameter can be one of the following values (no combination allowed) - * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) - * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) - * @arg DCMI_FLAG_FNE: FIFO empty flag - * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask - * @arg DCMI_FLAG_OVRRI: Overrun flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask - * @arg DCMI_FLAG_LINERI: Line flag mask - * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status - * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status - * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status - * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status - * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status - * @retval The state of FLAG. - */ -#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\ - ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\ - (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) :\ - ((__HANDLE__)->Instance->SR & (__FLAG__))) - -/** - * @brief Clear the DCMI pending flags. - * @param __HANDLE__ DCMI handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask - * @arg DCMI_FLAG_OVFRI: Overflow flag mask - * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask - * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask - * @arg DCMI_FLAG_LINERI: Line flag mask - * @retval None - */ -#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** - * @brief Enable the specified DCMI interrupts. - * @param __HANDLE__ DCMI handle - * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval None - */ -#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) - -/** - * @brief Disable the specified DCMI interrupts. - * @param __HANDLE__ DCMI handle - * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval None - */ -#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified DCMI interrupt has occurred or not. - * @param __HANDLE__ DCMI handle - * @param __INTERRUPT__ specifies the DCMI interrupt source to check. - * This parameter can be one of the following values: - * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask - * @arg DCMI_IT_OVF: Overflow interrupt mask - * @arg DCMI_IT_ERR: Synchronization error interrupt mask - * @arg DCMI_IT_VSYNC: VSYNC interrupt mask - * @arg DCMI_IT_LINE: Line interrupt mask - * @retval The state of INTERRUPT. - */ -#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions - * @{ - */ - -/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, - pDCMI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions - * @{ - */ -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length); -HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); -/** - * @} - */ - -/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, - uint32_t YSize); -HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi); -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask); - -/** - * @} - */ - -/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions - * @{ - */ -/* Peripheral State functions *************************************************/ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi); -uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DCMI_Private_Constants DCMI Private Constants - * @{ - */ -/** @defgroup DCMI_MIS_INDEX DCMI Mis Index - * @{ - */ -#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */ - -/** - * @} - */ - -/** @defgroup DCMI_SR_INDEX DCMI SR Index - * @{ - */ -#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */ - -/** - * @} - */ - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup DCMI_Private_Macros DCMI Private Macros - * @{ - */ -#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \ - ((MODE) == DCMI_MODE_SNAPSHOT)) - -#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \ - ((MODE) == DCMI_SYNCHRO_EMBEDDED)) - -#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \ - ((POLARITY) == DCMI_PCKPOLARITY_RISING)) - -#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \ - ((POLARITY) == DCMI_VSPOLARITY_HIGH)) - -#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \ - ((POLARITY) == DCMI_HSPOLARITY_HIGH)) - -#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \ - ((JPEG_MODE) == DCMI_JPEG_ENABLE)) - -#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \ - ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \ - ((RATE) == DCMI_CR_ALTERNATE_4_FRAME)) - -#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \ - ((DATA) == DCMI_EXTEND_DATA_10B) || \ - ((DATA) == DCMI_EXTEND_DATA_12B) || \ - ((DATA) == DCMI_EXTEND_DATA_14B)) - -#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE) - -#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT) - -#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \ - ((MODE) == DCMI_BSM_OTHER) || \ - ((MODE) == DCMI_BSM_ALTERNATE_4) || \ - ((MODE) == DCMI_BSM_ALTERNATE_2)) - -#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \ - ((POLARITY) == DCMI_OEBS_EVEN)) - -#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \ - ((MODE) == DCMI_LSM_ALTERNATE_2)) - -#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \ - ((POLARITY) == DCMI_OELS_EVEN)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DCMI_Private_Functions DCMI Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ -/** - * @} - */ -#endif /* DCMI */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_DCMI_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi_ex.h deleted file mode 100644 index fa3b1880..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dcmi_ex.h +++ /dev/null @@ -1,35 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dcmi_ex.h - * @author MCD Application Team - * @brief Header file of DCMI Extension HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DCMI_EX_H -#define __STM32F7xx_HAL_DCMI_EX_H - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -#endif /* __STM32F7xx_HAL_DCMI_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h index d0c34b69..8bb99ea6 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_def.h @@ -1,220 +1,220 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DEF -#define __STM32F7xx_HAL_DEF - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" -#include "Legacy/stm32_hal_legacy.h" -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00U, - HAL_ERROR = 0x01U, - HAL_BUSY = 0x02U, - HAL_TIMEOUT = 0x03U -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00U, - HAL_LOCKED = 0x01U -} HAL_LockTypeDef; - -/* Exported macro ------------------------------------------------------------*/ - -#if !defined(UNUSED) -#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ -#endif /* UNUSED */ - -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0) - -/** @brief Reset the Handle's State field. - * @param __HANDLE__ specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) - -#if (USE_RTOS == 1U) - /* Reserved for future use */ - #error "USE_RTOS should be 0 in the current HAL release" -#else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0U) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0U) -#endif /* USE_RTOS */ - -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif - #ifndef __packed - #define __packed __attribute__((packed)) - #endif -#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ -#endif /* __GNUC__ */ - - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif -#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ -#else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler V5*/ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - -/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ -#if defined (__GNUC__) /* GNU Compiler */ - #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) -#elif defined (__ICCARM__) /* IAR Compiler */ - #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf -#elif defined (__CC_ARM) /* ARM Compiler */ - #define ALIGN_32BYTES(buf) __align(32) buf -#endif - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -/* ARM Compiler V4/V5 and V6 - -------------------------- - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC __attribute__((section(".RamFunc"))) - -#endif - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) -/* ARM V4/V5 and V6 & GNU Compiler - ------------------------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32F7xx_HAL_DEF */ - - +/** + ****************************************************************************** + * @file stm32f7xx_hal_def.h + * @author MCD Application Team + * @brief This file contains HAL common defines, enumeration, macros and + * structures definitions. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DEF +#define __STM32F7xx_HAL_DEF + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" +#include "Legacy/stm32_hal_legacy.h" +#include + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief HAL Status structures definition + */ +typedef enum +{ + HAL_OK = 0x00U, + HAL_ERROR = 0x01U, + HAL_BUSY = 0x02U, + HAL_TIMEOUT = 0x03U +} HAL_StatusTypeDef; + +/** + * @brief HAL Lock structures definition + */ +typedef enum +{ + HAL_UNLOCKED = 0x00U, + HAL_LOCKED = 0x01U +} HAL_LockTypeDef; + +/* Exported macro ------------------------------------------------------------*/ + +#if !defined(UNUSED) +#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +#define HAL_MAX_DELAY 0xFFFFFFFFU + +#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) +#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) + +#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) + +/** @brief Reset the Handle's State field. + * @param __HANDLE__ specifies the Peripheral Handle. + * @note This macro can be used for the following purpose: + * - When the Handle is declared as local variable; before passing it as parameter + * to HAL_PPP_Init() for the first time, it is mandatory to use this macro + * to set to 0 the Handle's "State" field. + * Otherwise, "State" field may have any random value and the first time the function + * HAL_PPP_Init() is called, the low level hardware initialization will be missed + * (i.e. HAL_PPP_MspInit() will not be executed). + * - When there is a need to reconfigure the low level hardware: instead of calling + * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). + * In this later function, when the Handle's "State" field is set to 0, it will execute the function + * HAL_PPP_MspInit() which will reconfigure the low level hardware. + * @retval None + */ +#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) + +#if (USE_RTOS == 1U) + /* Reserved for future use */ + #error "USE_RTOS should be 0 in the current HAL release" +#else + #define __HAL_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + }while (0U) + + #define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0U) +#endif /* USE_RTOS */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif + #ifndef __packed + #define __packed __attribute__((packed)) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __weak + #define __weak __attribute__((weak)) + #endif /* __weak */ + #ifndef __packed + #define __packed __attribute__((__packed__)) + #endif /* __packed */ +#endif /* __GNUC__ */ + + +/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ + #ifndef __ALIGN_END + #define __ALIGN_END __attribute__ ((aligned (4))) + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN + #endif /* __ALIGN_BEGIN */ +#else + #ifndef __ALIGN_END + #define __ALIGN_END + #endif /* __ALIGN_END */ + #ifndef __ALIGN_BEGIN + #if defined (__CC_ARM) /* ARM Compiler V5*/ + #define __ALIGN_BEGIN __align(4) + #elif defined (__ICCARM__) /* IAR Compiler */ + #define __ALIGN_BEGIN + #endif /* __CC_ARM */ + #endif /* __ALIGN_BEGIN */ +#endif /* __GNUC__ */ + +/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ +#if defined (__GNUC__) /* GNU Compiler */ + #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) +#elif defined (__ICCARM__) /* IAR Compiler */ + #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf +#elif defined (__CC_ARM) /* ARM Compiler */ + #define ALIGN_32BYTES(buf) __align(32) buf +#endif + +/** + * @brief __RAM_FUNC definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) +/* ARM Compiler V4/V5 and V6 + -------------------------- + RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. + Available memory areas are declared in the 'Target' tab of the 'Options for Target' + dialog. +*/ +#define __RAM_FUNC + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- + RAM functions are defined using a specific toolchain keyword "__ramfunc". +*/ +#define __RAM_FUNC __ramfunc + +#elif defined ( __GNUC__ ) +/* GNU Compiler + ------------ + RAM functions are defined using a specific toolchain attribute + "__attribute__((section(".RamFunc")))". +*/ +#define __RAM_FUNC __attribute__((section(".RamFunc"))) + +#endif + +/** + * @brief __NOINLINE definition + */ +#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +/* ARM V4/V5 and V6 & GNU Compiler + ------------------------------- +*/ +#define __NOINLINE __attribute__ ( (noinline) ) + +#elif defined ( __ICCARM__ ) +/* ICCARM Compiler + --------------- +*/ +#define __NOINLINE _Pragma("optimize = no_inline") + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32F7xx_HAL_DEF */ + + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dfsdm.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dfsdm.h deleted file mode 100644 index 038b1c16..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dfsdm.h +++ /dev/null @@ -1,792 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dfsdm.h - * @author MCD Application Team - * @brief Header file of DFSDM HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DFSDM_H -#define __STM32F7xx_HAL_DFSDM_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup DFSDM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DFSDM_Exported_Types DFSDM Exported Types - * @{ - */ - -/** - * @brief HAL DFSDM Channel states definition - */ -typedef enum -{ - HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ - HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ - HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ -}HAL_DFSDM_Channel_StateTypeDef; - -/** - * @brief DFSDM channel output clock structure definition - */ -typedef struct -{ - FunctionalState Activation; /*!< Output clock enable/disable */ - uint32_t Selection; /*!< Output clock is system clock or audio clock. - This parameter can be a value of @ref DFSDM_Channel_OuputClock */ - uint32_t Divider; /*!< Output clock divider. - This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ -}DFSDM_Channel_OutputClockTypeDef; - -/** - * @brief DFSDM channel input structure definition - */ -typedef struct -{ - uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. - This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ - uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. - This parameter can be a value of @ref DFSDM_Channel_DataPacking */ - uint32_t Pins; /*!< Input pins are taken from same or following channel. - This parameter can be a value of @ref DFSDM_Channel_InputPins */ -}DFSDM_Channel_InputTypeDef; - -/** - * @brief DFSDM channel serial interface structure definition - */ -typedef struct -{ - uint32_t Type; /*!< SPI or Manchester modes. - This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ - uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). - This parameter can be a value of @ref DFSDM_Channel_SpiClock */ -}DFSDM_Channel_SerialInterfaceTypeDef; - -/** - * @brief DFSDM channel analog watchdog structure definition - */ -typedef struct -{ - uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. - This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ - uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ -}DFSDM_Channel_AwdTypeDef; - -/** - * @brief DFSDM channel init structure definition - */ -typedef struct -{ - DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ - DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ - DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ - DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ - int32_t Offset; /*!< DFSDM channel offset. - This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ - uint32_t RightBitShift; /*!< DFSDM channel right bit shift. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ -}DFSDM_Channel_InitTypeDef; - -/** - * @brief DFSDM channel handle structure definition - */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -typedef struct __DFSDM_Channel_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ -{ - DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ - DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ - HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ - void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ - void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ - void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ -#endif -}DFSDM_Channel_HandleTypeDef; - -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -/** - * @brief DFSDM channel callback ID enumeration definition - */ -typedef enum -{ - HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ - HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ - HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ - HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ -}HAL_DFSDM_Channel_CallbackIDTypeDef; - -/** - * @brief DFSDM channel callback pointer definition - */ -typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -#endif -/** - * @brief HAL DFSDM Filter states definition - */ -typedef enum -{ - HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ - HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ - HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ - HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ - HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ - HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ -}HAL_DFSDM_Filter_StateTypeDef; - -/** - * @brief DFSDM filter regular conversion parameters structure definition - */ -typedef struct -{ - uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. - This parameter can be a value of @ref DFSDM_Filter_Trigger */ - FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ - FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ -}DFSDM_Filter_RegularParamTypeDef; - -/** - * @brief DFSDM filter injected conversion parameters structure definition - */ -typedef struct -{ - uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. - This parameter can be a value of @ref DFSDM_Filter_Trigger */ - FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ - FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ - uint32_t ExtTrigger; /*!< External trigger. - This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ - uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. - This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ -}DFSDM_Filter_InjectedParamTypeDef; - -/** - * @brief DFSDM filter parameters structure definition - */ -typedef struct -{ - uint32_t SincOrder; /*!< Sinc filter order. - This parameter can be a value of @ref DFSDM_Filter_SincOrder */ - uint32_t Oversampling; /*!< Filter oversampling ratio. - This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ - uint32_t IntOversampling; /*!< Integrator oversampling ratio. - This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ -}DFSDM_Filter_FilterParamTypeDef; - -/** - * @brief DFSDM filter init structure definition - */ -typedef struct -{ - DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ - DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ - DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ -}DFSDM_Filter_InitTypeDef; - -/** - * @brief DFSDM filter handle structure definition - */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -typedef struct __DFSDM_Filter_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ -{ - DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ - DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ - DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ - DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ - uint32_t RegularContMode; /*!< Regular conversion continuous mode */ - uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ - uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ - uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ - FunctionalState InjectedScanMode; /*!< Injected scanning mode */ - uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ - uint32_t InjConvRemaining; /*!< Injected conversions remaining */ - HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ - uint32_t ErrorCode; /*!< DFSDM filter error code */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ - void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ - void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ - void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ - void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ - void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ - void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ - void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ -#endif -}DFSDM_Filter_HandleTypeDef; - -/** - * @brief DFSDM filter analog watchdog parameters structure definition - */ -typedef struct -{ - uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. - This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ - uint32_t Channel; /*!< Analog watchdog channel selection. - This parameter can be a values combination of @ref DFSDM_Channel_Selection */ - int32_t HighThreshold; /*!< High threshold for the analog watchdog. - This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ - int32_t LowThreshold; /*!< Low threshold for the analog watchdog. - This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ - uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. - This parameter can be a values combination of @ref DFSDM_BreakSignals */ - uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. - This parameter can be a values combination of @ref DFSDM_BreakSignals */ -}DFSDM_Filter_AwdParamTypeDef; - -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -/** - * @brief DFSDM filter callback ID enumeration definition - */ -typedef enum -{ - HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ - HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ - HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ - HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ - HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ - HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ - HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ -}HAL_DFSDM_Filter_CallbackIDTypeDef; - -/** - * @brief DFSDM filter callback pointer definition - */ -typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); -#endif -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants - * @{ - */ - -/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection - * @{ - */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for output clock is system clock */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */ -/** - * @} - */ - -/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer - * @{ - */ -#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */ -#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ -/** - * @} - */ - -/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing - * @{ - */ -#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */ -#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ -#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ -/** - * @} - */ - -/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins - * @{ - */ -#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */ -#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ -/** - * @} - */ - -/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type - * @{ - */ -#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */ -#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ -#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ -#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ -/** - * @} - */ - -/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection - * @{ - */ -#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */ -#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ -#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ -#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ -/** - * @} - */ - -/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order - * @{ - */ -#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ -#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ -#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ -#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ -/** - * @} - */ - -/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger - * @{ - */ -#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */ -#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */ -#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */ -/** - * @} - */ - -/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger - * @{ - */ -#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ - DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ - DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ -#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ - DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */ -/** - * @} - */ - -/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge - * @{ - */ -#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ -#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ -#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ -/** - * @} - */ - -/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order - * @{ - */ -#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */ -#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ -#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ -#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ -#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ -#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ -/** - * @} - */ - -/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source - * @{ - */ -#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */ -#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ -/** - * @} - */ - -/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code - * @{ - */ -#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */ -#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */ -#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -#define DFSDM_FILTER_ERROR_INVALID_CALLBACK ((uint32_t)0x00000004U) /*!< Invalid callback error occurs */ -#endif -/** - * @} - */ - -/** @defgroup DFSDM_BreakSignals DFSDM break signals - * @{ - */ -#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */ -#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */ -#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */ -#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */ -#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */ -/** - * @} - */ - -/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection - * @{ - */ -/* DFSDM Channels ------------------------------------------------------------*/ -/* The DFSDM channels are defined as follows: - - in 16-bit LSB the channel mask is set - - in 16-bit MSB the channel number is set - e.g. for channel 5 definition: - - the channel mask is 0x00000020 (bit 5 is set) - - the channel number 5 is 0x00050000 - --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ -#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U) -#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U) -#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U) -#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U) -#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U) -#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U) -#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U) -#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U) -/** - * @} - */ - -/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode - * @{ - */ -#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */ -#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */ -/** - * @} - */ - -/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold - * @{ - */ -#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */ -#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros - * @{ - */ - -/** @brief Reset DFSDM channel handle state. - * @param __HANDLE__: DFSDM channel handle. - * @retval None - */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) -#endif - -/** @brief Reset DFSDM filter handle state. - * @param __HANDLE__: DFSDM filter handle. - * @retval None - */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) -#endif - -/** - * @} - */ -/* End of exported macros ----------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions - * @{ - */ - -/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions - * @{ - */ -/* Channel initialization and de-initialization functions *********************/ -HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); - -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -/* Channel callbacks register/unregister functions ****************************/ -HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, - pDFSDM_Channel_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); -#endif -/** - * @} - */ - -/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions - * @{ - */ -/* Channel operation functions ************************************************/ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); - -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); - -int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); - -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); - -void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function - * @{ - */ -/* Channel state function *****************************************************/ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -/** - * @} - */ - -/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions - * @{ - */ -/* Filter initialization and de-initialization functions *********************/ -HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); - -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -/* Filter callbacks register/unregister functions ****************************/ -HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, - pDFSDM_Filter_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - pDFSDM_Filter_AwdCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -#endif -/** - * @} - */ - -/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions - * @{ - */ -/* Filter control functions *********************/ -HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel, - uint32_t ContinuousMode); -HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel); -/** - * @} - */ - -/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions - * @{ - */ -/* Filter operation functions *********************/ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - const DFSDM_Filter_AwdParamTypeDef* awdParam); -HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); -HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); - -int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); - -void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); - -HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); -HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); - -void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); -void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions - * @{ - */ -/* Filter state functions *****************************************************/ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DFSDM_Private_Macros DFSDM Private Macros -* @{ -*/ -#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ - ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) -#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256)) -#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ - ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) -#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ - ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ - ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) -#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ - ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) -#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ - ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ - ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ - ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) -#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ - ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ - ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ - ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) -#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ - ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ - ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ - ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) -#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32)) -#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) -#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F) -#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF) -#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ - ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) -#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ - ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) -#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\ - ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) -#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ - ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ - ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) -#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ - ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ - ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ - ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ - ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ - ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) -#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024)) -#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256)) -#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ - ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) -#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) -#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) -#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ - ((CHANNEL) == DFSDM_CHANNEL_1) || \ - ((CHANNEL) == DFSDM_CHANNEL_2) || \ - ((CHANNEL) == DFSDM_CHANNEL_3) || \ - ((CHANNEL) == DFSDM_CHANNEL_4) || \ - ((CHANNEL) == DFSDM_CHANNEL_5) || \ - ((CHANNEL) == DFSDM_CHANNEL_6) || \ - ((CHANNEL) == DFSDM_CHANNEL_7)) -#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU)) -#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ - ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_DFSDM_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h index cca45097..de7c07ef 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma.h @@ -1,747 +1,747 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DMA_H -#define __STM32F7xx_HAL_DMA_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Types DMA Exported Types - * @brief DMA Exported Types - * @{ - */ - -/** - * @brief DMA Configuration Structure definition - */ -typedef struct -{ - uint32_t Channel; /*!< Specifies the channel used for the specified stream. - This parameter can be a value of @ref DMAEx_Channel_selection */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_Data_transfer_direction */ - - uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. - This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ - - uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. - This parameter can be a value of @ref DMA_Memory_incremented_mode */ - - uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. - This parameter can be a value of @ref DMA_Peripheral_data_size */ - - uint32_t MemDataAlignment; /*!< Specifies the Memory data width. - This parameter can be a value of @ref DMA_Memory_data_size */ - - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. - This parameter can be a value of @ref DMA_mode - @note The circular buffer mode cannot be used if the memory-to-memory - data transfer is configured on the selected Stream */ - - uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. - This parameter can be a value of @ref DMA_Priority_level */ - - uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. - This parameter can be a value of @ref DMA_FIFO_direct_mode - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected stream */ - - uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_FIFO_threshold_level */ - - uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_Memory_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ - - uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_Peripheral_burst - @note The burst mode is possible only if the address Increment mode is enabled. */ -}DMA_InitTypeDef; - -/** - * @brief HAL DMA State structures definition - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ - HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ - HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ -}HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ - HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ -}HAL_DMA_LevelCompleteTypeDef; - -/** - * @brief HAL DMA Error Code structure definition - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ - HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ - HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ - HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ - HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ - HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ -}HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Stream_TypeDef *Instance; /*!< Register base address */ - - DMA_InitTypeDef Init; /*!< DMA communication parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ - - void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ - - void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ - - void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ - - __IO uint32_t ErrorCode; /*!< DMA Error code */ - - uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ - - uint32_t StreamIndex; /*!< DMA Stream Index */ - -}DMA_HandleTypeDef; - -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @brief DMA Exported constants - * @{ - */ - -/** @defgroup DMA_Error_Code DMA Error Code - * @brief DMA Error Code - * @{ - */ -#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ -#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ -#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ -#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ -#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ -#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ -#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ -/** - * @} - */ - -/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction - * @brief DMA data transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode - * @brief DMA peripheral incremented mode - * @{ - */ -#define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */ -#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ -/** - * @} - */ - -/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode - * @brief DMA memory incremented mode - * @{ - */ -#define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */ -#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ -/** - * @} - */ - -/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size - * @brief DMA peripheral data size - * @{ - */ -#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ -#define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */ -#define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */ -/** - * @} - */ - -/** @defgroup DMA_Memory_data_size DMA Memory data size - * @brief DMA memory data size - * @{ - */ -#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ -#define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */ -#define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */ -/** - * @} - */ - -/** @defgroup DMA_mode DMA mode - * @brief DMA mode - * @{ - */ -#define DMA_NORMAL 0x00000000U /*!< Normal mode */ -#define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */ -#define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ -/** - * @} - */ - -/** @defgroup DMA_Priority_level DMA Priority level - * @brief DMA priority levels - * @{ - */ -#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ -#define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */ -#define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */ -#define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */ -/** - * @} - */ - -/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode - * @brief DMA FIFO direct mode - * @{ - */ -#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ -/** - * @} - */ - -/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level - * @brief DMA FIFO level - * @{ - */ -#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ -#define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ -#define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ -#define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ -/** - * @} - */ - -/** @defgroup DMA_Memory_burst DMA Memory burst - * @brief DMA memory burst - * @{ - */ -#define DMA_MBURST_SINGLE 0x00000000U -#define DMA_MBURST_INC4 DMA_SxCR_MBURST_0 -#define DMA_MBURST_INC8 DMA_SxCR_MBURST_1 -#define DMA_MBURST_INC16 DMA_SxCR_MBURST -/** - * @} - */ - -/** @defgroup DMA_Peripheral_burst DMA Peripheral burst - * @brief DMA peripheral burst - * @{ - */ -#define DMA_PBURST_SINGLE 0x00000000U -#define DMA_PBURST_INC4 DMA_SxCR_PBURST_0 -#define DMA_PBURST_INC8 DMA_SxCR_PBURST_1 -#define DMA_PBURST_INC16 DMA_SxCR_PBURST -/** - * @} - */ - -/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions - * @brief DMA interrupts definition - * @{ - */ -#define DMA_IT_TC DMA_SxCR_TCIE -#define DMA_IT_HT DMA_SxCR_HTIE -#define DMA_IT_TE DMA_SxCR_TEIE -#define DMA_IT_DME DMA_SxCR_DMEIE -#define DMA_IT_FE 0x00000080U -/** - * @} - */ - -/** @defgroup DMA_flag_definitions DMA flag definitions - * @brief DMA flag definitions - * @{ - */ -#define DMA_FLAG_FEIF0_4 0x00000001U -#define DMA_FLAG_DMEIF0_4 0x00000004U -#define DMA_FLAG_TEIF0_4 0x00000008U -#define DMA_FLAG_HTIF0_4 0x00000010U -#define DMA_FLAG_TCIF0_4 0x00000020U -#define DMA_FLAG_FEIF1_5 0x00000040U -#define DMA_FLAG_DMEIF1_5 0x00000100U -#define DMA_FLAG_TEIF1_5 0x00000200U -#define DMA_FLAG_HTIF1_5 0x00000400U -#define DMA_FLAG_TCIF1_5 0x00000800U -#define DMA_FLAG_FEIF2_6 0x00010000U -#define DMA_FLAG_DMEIF2_6 0x00040000U -#define DMA_FLAG_TEIF2_6 0x00080000U -#define DMA_FLAG_HTIF2_6 0x00100000U -#define DMA_FLAG_TCIF2_6 0x00200000U -#define DMA_FLAG_FEIF3_7 0x00400000U -#define DMA_FLAG_DMEIF3_7 0x01000000U -#define DMA_FLAG_TEIF3_7 0x02000000U -#define DMA_FLAG_HTIF3_7 0x04000000U -#define DMA_FLAG_TCIF3_7 0x08000000U -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @brief Reset DMA handle state - * @param __HANDLE__ specifies the DMA handle. - * @retval None - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Return the current DMA Stream FIFO filled level. - * @param __HANDLE__ DMA handle - * @retval The FIFO filling state. - * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full - * and not empty. - * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. - * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. - * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. - * - DMA_FIFOStatus_Empty: when FIFO is empty - * - DMA_FIFOStatus_Full: when FIFO is full - */ -#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) - -/** - * @brief Enable the specified DMA Stream. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) - -/** - * @brief Disable the specified DMA Stream. - * @param __HANDLE__ DMA handle - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) - -/* Interrupt & Flag management */ - -/** - * @brief Return the current DMA Stream transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer complete flag index. - */ -#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ - DMA_FLAG_TCIF3_7) - -/** - * @brief Return the current DMA Stream half transfer complete flag. - * @param __HANDLE__ DMA handle - * @retval The specified half transfer complete flag index. - */ -#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ - DMA_FLAG_HTIF3_7) - -/** - * @brief Return the current DMA Stream transfer error flag. - * @param __HANDLE__ DMA handle - * @retval The specified transfer error flag index. - */ -#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ - DMA_FLAG_TEIF3_7) - -/** - * @brief Return the current DMA Stream FIFO error flag. - * @param __HANDLE__ DMA handle - * @retval The specified FIFO error flag index. - */ -#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ - DMA_FLAG_FEIF3_7) - -/** - * @brief Return the current DMA Stream direct mode error flag. - * @param __HANDLE__ DMA handle - * @retval The specified direct mode error flag index. - */ -#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ -(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ - ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ - DMA_FLAG_DMEIF3_7) - -/** - * @brief Get the DMA Stream pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Transfer complete flag. - * @arg DMA_FLAG_HTIFx: Half transfer complete flag. - * @arg DMA_FLAG_TEIFx: Transfer error flag. - * @arg DMA_FLAG_DMEIFx: Direct mode error flag. - * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) - -/** - * @brief Clear the DMA Stream pending flags. - * @param __HANDLE__ DMA handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TCIFx: Transfer complete flag. - * @arg DMA_FLAG_HTIFx: Half transfer complete flag. - * @arg DMA_FLAG_TEIFx: Transfer error flag. - * @arg DMA_FLAG_DMEIFx: Direct mode error flag. - * @arg DMA_FLAG_FEIFx: FIFO error flag. - * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ -(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ - ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) - -/** - * @brief Enable the specified DMA Stream interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ -((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) - -/** - * @brief Disable the specified DMA Stream interrupts. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ -((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) - -/** - * @brief Check whether the specified DMA Stream interrupt is enabled or not. - * @param __HANDLE__ DMA handle - * @param __INTERRUPT__ specifies the DMA interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA_IT_TC: Transfer complete interrupt mask. - * @arg DMA_IT_HT: Half transfer complete interrupt mask. - * @arg DMA_IT_TE: Transfer error interrupt mask. - * @arg DMA_IT_FE: FIFO error interrupt mask. - * @arg DMA_IT_DME: Direct mode error interrupt. - * @retval The state of DMA_IT. - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ - ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ - ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) - -/** - * @brief Writes the number of data units to be transferred on the DMA Stream. - * @param __HANDLE__ DMA handle - * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) - * Number of data items depends only on the Peripheral data format. - * - * @note If Peripheral data format is Bytes: number of data units is equal - * to total number of bytes to be transferred. - * - * @note If Peripheral data format is Half-Word: number of data units is - * equal to total number of bytes to be transferred / 2. - * - * @note If Peripheral data format is Word: number of data units is equal - * to total number of bytes to be transferred / 4. - * - * @retval The number of remaining data units in the current DMAy Streamx transfer. - */ -#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) - -/** - * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. - * @param __HANDLE__ DMA handle - * - * @retval The number of remaining data units in the current DMA Stream transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) - - -/* Include DMA HAL Extension module */ -#include "stm32f7xx_hal_dma_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @brief DMA Exported functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions - * @brief I/O operation functions - * @{ - */ -HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); - -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); -/** - * @} - */ -/** - * @} - */ -/* Private Constants -------------------------------------------------------------*/ -/** @defgroup DMA_Private_Constants DMA Private Constants - * @brief DMA private defines and constants - * @{ - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMA_Private_Macros DMA Private Macros - * @brief DMA private macros - * @{ - */ -#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) - -#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) - -#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ - ((STATE) == DMA_PINC_DISABLE)) - -#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ - ((STATE) == DMA_MINC_DISABLE)) - -#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ - ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_PDATAALIGN_WORD)) - -#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ - ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ - ((SIZE) == DMA_MDATAALIGN_WORD )) - -#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ - ((MODE) == DMA_CIRCULAR) || \ - ((MODE) == DMA_PFCTRL)) - -#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ - ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ - ((PRIORITY) == DMA_PRIORITY_HIGH) || \ - ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) - -#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ - ((STATE) == DMA_FIFOMODE_ENABLE)) - -#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ - ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) - -#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ - ((BURST) == DMA_MBURST_INC4) || \ - ((BURST) == DMA_MBURST_INC8) || \ - ((BURST) == DMA_MBURST_INC16)) - -#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ - ((BURST) == DMA_PBURST_INC4) || \ - ((BURST) == DMA_PBURST_INC8) || \ - ((BURST) == DMA_PBURST_INC16)) -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA private functions - * @{ - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_DMA_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma.h + * @author MCD Application Team + * @brief Header file of DMA HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DMA_H +#define __STM32F7xx_HAL_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMA + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Types DMA Exported Types + * @brief DMA Exported Types + * @{ + */ + +/** + * @brief DMA Configuration Structure definition + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel used for the specified stream. + This parameter can be a value of @ref DMAEx_Channel_selection */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_Data_transfer_direction */ + + uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ + + uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + This parameter can be a value of @ref DMA_Memory_incremented_mode */ + + uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_Peripheral_data_size */ + + uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + This parameter can be a value of @ref DMA_Memory_data_size */ + + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. + This parameter can be a value of @ref DMA_mode + @note The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Stream */ + + uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. + This parameter can be a value of @ref DMA_Priority_level */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_FIFO_direct_mode + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_FIFO_threshold_level */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Memory_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_Peripheral_burst + @note The burst mode is possible only if the address Increment mode is enabled. */ +}DMA_InitTypeDef; + +/** + * @brief HAL DMA State structures definition + */ +typedef enum +{ + HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ + HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ + HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ + HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ + HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ + HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ +}HAL_DMA_StateTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ + HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */ +}HAL_DMA_LevelCompleteTypeDef; + +/** + * @brief HAL DMA Error Code structure definition + */ +typedef enum +{ + HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ + HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ + HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ + HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ + HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ + HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ + HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ +}HAL_DMA_CallbackIDTypeDef; + +/** + * @brief DMA handle Structure definition + */ +typedef struct __DMA_HandleTypeDef +{ + DMA_Stream_TypeDef *Instance; /*!< Register base address */ + + DMA_InitTypeDef Init; /*!< DMA communication parameters */ + + HAL_LockTypeDef Lock; /*!< DMA locking object */ + + __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ + + void *Parent; /*!< Parent object state */ + + void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ + + void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ + + void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ + + void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ + + void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ + + void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ + + __IO uint32_t ErrorCode; /*!< DMA Error code */ + + uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ + + uint32_t StreamIndex; /*!< DMA Stream Index */ + +}DMA_HandleTypeDef; + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMA_Error_Code DMA Error Code + * @brief DMA Error Code + * @{ + */ +#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ +#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ +#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ +#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ +#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ +#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ +#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ +/** + * @} + */ + +/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction + * @brief DMA data transfer direction + * @{ + */ +#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode + * @brief DMA peripheral incremented mode + * @{ + */ +#define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */ +#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode + * @brief DMA memory incremented mode + * @{ + */ +#define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */ +#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ +/** + * @} + */ + +/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size + * @brief DMA peripheral data size + * @{ + */ +#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ +#define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */ +#define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_Memory_data_size DMA Memory data size + * @brief DMA memory data size + * @{ + */ +#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ +#define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */ +#define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */ +/** + * @} + */ + +/** @defgroup DMA_mode DMA mode + * @brief DMA mode + * @{ + */ +#define DMA_NORMAL 0x00000000U /*!< Normal mode */ +#define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */ +#define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_Priority_level DMA Priority level + * @brief DMA priority levels + * @{ + */ +#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ +#define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */ +#define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */ +#define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode + * @brief DMA FIFO direct mode + * @{ + */ +#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level + * @brief DMA FIFO level + * @{ + */ +#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_Memory_burst DMA Memory burst + * @brief DMA memory burst + * @{ + */ +#define DMA_MBURST_SINGLE 0x00000000U +#define DMA_MBURST_INC4 DMA_SxCR_MBURST_0 +#define DMA_MBURST_INC8 DMA_SxCR_MBURST_1 +#define DMA_MBURST_INC16 DMA_SxCR_MBURST +/** + * @} + */ + +/** @defgroup DMA_Peripheral_burst DMA Peripheral burst + * @brief DMA peripheral burst + * @{ + */ +#define DMA_PBURST_SINGLE 0x00000000U +#define DMA_PBURST_INC4 DMA_SxCR_PBURST_0 +#define DMA_PBURST_INC8 DMA_SxCR_PBURST_1 +#define DMA_PBURST_INC16 DMA_SxCR_PBURST +/** + * @} + */ + +/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions + * @brief DMA interrupts definition + * @{ + */ +#define DMA_IT_TC DMA_SxCR_TCIE +#define DMA_IT_HT DMA_SxCR_HTIE +#define DMA_IT_TE DMA_SxCR_TEIE +#define DMA_IT_DME DMA_SxCR_DMEIE +#define DMA_IT_FE 0x00000080U +/** + * @} + */ + +/** @defgroup DMA_flag_definitions DMA flag definitions + * @brief DMA flag definitions + * @{ + */ +#define DMA_FLAG_FEIF0_4 0x00000001U +#define DMA_FLAG_DMEIF0_4 0x00000004U +#define DMA_FLAG_TEIF0_4 0x00000008U +#define DMA_FLAG_HTIF0_4 0x00000010U +#define DMA_FLAG_TCIF0_4 0x00000020U +#define DMA_FLAG_FEIF1_5 0x00000040U +#define DMA_FLAG_DMEIF1_5 0x00000100U +#define DMA_FLAG_TEIF1_5 0x00000200U +#define DMA_FLAG_HTIF1_5 0x00000400U +#define DMA_FLAG_TCIF1_5 0x00000800U +#define DMA_FLAG_FEIF2_6 0x00010000U +#define DMA_FLAG_DMEIF2_6 0x00040000U +#define DMA_FLAG_TEIF2_6 0x00080000U +#define DMA_FLAG_HTIF2_6 0x00100000U +#define DMA_FLAG_TCIF2_6 0x00200000U +#define DMA_FLAG_FEIF3_7 0x00400000U +#define DMA_FLAG_DMEIF3_7 0x01000000U +#define DMA_FLAG_TEIF3_7 0x02000000U +#define DMA_FLAG_HTIF3_7 0x04000000U +#define DMA_FLAG_TCIF3_7 0x08000000U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/** @brief Reset DMA handle state + * @param __HANDLE__ specifies the DMA handle. + * @retval None + */ +#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) + +/** + * @brief Return the current DMA Stream FIFO filled level. + * @param __HANDLE__ DMA handle + * @retval The FIFO filling state. + * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full + * and not empty. + * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. + * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. + * - DMA_FIFOStatus_Empty: when FIFO is empty + * - DMA_FIFOStatus_Full: when FIFO is full + */ +#define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) + +/** + * @brief Enable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) + +/** + * @brief Disable the specified DMA Stream. + * @param __HANDLE__ DMA handle + * @retval None + */ +#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) + +/* Interrupt & Flag management */ + +/** + * @brief Return the current DMA Stream transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer complete flag index. + */ +#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ + DMA_FLAG_TCIF3_7) + +/** + * @brief Return the current DMA Stream half transfer complete flag. + * @param __HANDLE__ DMA handle + * @retval The specified half transfer complete flag index. + */ +#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ + DMA_FLAG_HTIF3_7) + +/** + * @brief Return the current DMA Stream transfer error flag. + * @param __HANDLE__ DMA handle + * @retval The specified transfer error flag index. + */ +#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ + DMA_FLAG_TEIF3_7) + +/** + * @brief Return the current DMA Stream FIFO error flag. + * @param __HANDLE__ DMA handle + * @retval The specified FIFO error flag index. + */ +#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ + DMA_FLAG_FEIF3_7) + +/** + * @brief Return the current DMA Stream direct mode error flag. + * @param __HANDLE__ DMA handle + * @retval The specified direct mode error flag index. + */ +#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ +(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ + ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ + DMA_FLAG_DMEIF3_7) + +/** + * @brief Get the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ Get the specified flag. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) + +/** + * @brief Clear the DMA Stream pending flags. + * @param __HANDLE__ DMA handle + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg DMA_FLAG_TCIFx: Transfer complete flag. + * @arg DMA_FLAG_HTIFx: Half transfer complete flag. + * @arg DMA_FLAG_TEIFx: Transfer error flag. + * @arg DMA_FLAG_DMEIFx: Direct mode error flag. + * @arg DMA_FLAG_FEIFx: FIFO error flag. + * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. + * @retval None + */ +#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ +(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ + ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) + +/** + * @brief Enable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) + +/** + * @brief Disable the specified DMA Stream interrupts. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval None + */ +#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ +((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) + +/** + * @brief Check whether the specified DMA Stream interrupt is enabled or not. + * @param __HANDLE__ DMA handle + * @param __INTERRUPT__ specifies the DMA interrupt source to check. + * This parameter can be one of the following values: + * @arg DMA_IT_TC: Transfer complete interrupt mask. + * @arg DMA_IT_HT: Half transfer complete interrupt mask. + * @arg DMA_IT_TE: Transfer error interrupt mask. + * @arg DMA_IT_FE: FIFO error interrupt mask. + * @arg DMA_IT_DME: Direct mode error interrupt. + * @retval The state of DMA_IT. + */ +#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ + ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ + ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) + +/** + * @brief Writes the number of data units to be transferred on the DMA Stream. + * @param __HANDLE__ DMA handle + * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) + * Number of data items depends only on the Peripheral data format. + * + * @note If Peripheral data format is Bytes: number of data units is equal + * to total number of bytes to be transferred. + * + * @note If Peripheral data format is Half-Word: number of data units is + * equal to total number of bytes to be transferred / 2. + * + * @note If Peripheral data format is Word: number of data units is equal + * to total number of bytes to be transferred / 4. + * + * @retval The number of remaining data units in the current DMAy Streamx transfer. + */ +#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) + +/** + * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. + * @param __HANDLE__ DMA handle + * + * @retval The number of remaining data units in the current DMA Stream transfer. + */ +#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) + + +/* Include DMA HAL Extension module */ +#include "stm32f7xx_hal_dma_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @brief DMA Exported functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @brief I/O operation functions + * @{ + */ +HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); + +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/** + * @} + */ +/* Private Constants -------------------------------------------------------------*/ +/** @defgroup DMA_Private_Constants DMA Private Constants + * @brief DMA private defines and constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMA_Private_Macros DMA Private Macros + * @brief DMA private macros + * @{ + */ +#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ + ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ + ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) + +#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) + +#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ + ((STATE) == DMA_PINC_DISABLE)) + +#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ + ((STATE) == DMA_MINC_DISABLE)) + +#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ + ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_PDATAALIGN_WORD)) + +#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ + ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ + ((SIZE) == DMA_MDATAALIGN_WORD )) + +#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ + ((MODE) == DMA_CIRCULAR) || \ + ((MODE) == DMA_PFCTRL)) + +#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ + ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ + ((PRIORITY) == DMA_PRIORITY_HIGH) || \ + ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) + +#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ + ((STATE) == DMA_FIFOMODE_ENABLE)) + +#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ + ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) + +#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ + ((BURST) == DMA_MBURST_INC4) || \ + ((BURST) == DMA_MBURST_INC8) || \ + ((BURST) == DMA_MBURST_INC16)) + +#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ + ((BURST) == DMA_PBURST_INC4) || \ + ((BURST) == DMA_PBURST_INC8) || \ + ((BURST) == DMA_PBURST_INC16)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions + * @brief DMA private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_DMA_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h deleted file mode 100644 index 523fa8e2..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h +++ /dev/null @@ -1,681 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma2d.h - * @author MCD Application Team - * @brief Header file of DMA2D HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_DMA2D_H -#define STM32F7xx_HAL_DMA2D_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined (DMA2D) - -/** @addtogroup DMA2D DMA2D - * @brief DMA2D HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMA2D_Exported_Types DMA2D Exported Types - * @{ - */ -#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ - -/** - * @brief DMA2D CLUT Structure definition - */ -typedef struct -{ - uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ - - uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. - This parameter can be one value of @ref DMA2D_CLUT_CM. */ - - uint32_t Size; /*!< Configures the DMA2D CLUT size. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ -} DMA2D_CLUTCfgTypeDef; - -/** - * @brief DMA2D Init structure definition - */ -typedef struct -{ - uint32_t Mode; /*!< Configures the DMA2D transfer mode. - This parameter can be one value of @ref DMA2D_Mode. */ - - uint32_t ColorMode; /*!< Configures the color format of the output image. - This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ - - uint32_t OutputOffset; /*!< Specifies the Offset value. - This parameter must be a number between - Min_Data = 0x0000 and Max_Data = 0x3FFF. */ -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - uint32_t AlphaInverted; /*!< Select regular or inverted alpha value - for the output pixel format converter. - This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ - - uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) - for the output pixel format converter. - This parameter can be one value of @ref DMA2D_RB_Swap. */ - -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - - - -} DMA2D_InitTypeDef; - - -/** - * @brief DMA2D Layer structure definition - */ -typedef struct -{ - uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. - This parameter must be a number between - Min_Data = 0x0000 and Max_Data = 0x3FFF. */ - - uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. - This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ - - uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. - This parameter can be one value of @ref DMA2D_Alpha_Mode. */ - - uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value - in case of A8 or A4 color mode. - This parameter must be a number between Min_Data = 0x00 - and Max_Data = 0xFF except for the color modes detailed below. - @note In case of A8 or A4 color mode (ARGB), - this parameter must be a number between - Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where - - InputAlpha[24:31] is the alpha value ALPHA[0:7] - - InputAlpha[16:23] is the red value RED[0:7] - - InputAlpha[8:15] is the green value GREEN[0:7] - - InputAlpha[0:7] is the blue value BLUE[0:7]. */ -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. - This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ - - uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). - This parameter can be one value of @ref DMA2D_RB_Swap. */ -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - -} DMA2D_LayerCfgTypeDef; - -/** - * @brief HAL DMA2D State structures definition - */ -typedef enum -{ - HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ - HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ - HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ -} HAL_DMA2D_StateTypeDef; - -/** - * @brief DMA2D handle Structure definition - */ -typedef struct __DMA2D_HandleTypeDef -{ - DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ - - DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ - - void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ - - void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ - -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ - - void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ - - void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ - - void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ - -#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ - - DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ - - HAL_LockTypeDef Lock; /*!< DMA2D lock. */ - - __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ - - __IO uint32_t ErrorCode; /*!< DMA2D error code. */ -} DMA2D_HandleTypeDef; - -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -/** - * @brief HAL DMA2D Callback pointer definition - */ -typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ -#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants - * @{ - */ - -/** @defgroup DMA2D_Error_Code DMA2D Error Code - * @{ - */ -#define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ -#define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ -#define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ -#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup DMA2D_Mode DMA2D Mode - * @{ - */ -#define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ -#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ -#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ -#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ -/** - * @} - */ - -/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode - * @{ - */ -#define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ -#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ -#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ -#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ -#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ -/** - * @} - */ - -/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode - * @{ - */ -#define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ -#define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ -#define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ -#define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ -#define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ -#define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ -#define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ -#define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ -#define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ -#define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ -#define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ -/** - * @} - */ - -/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode - * @{ - */ -#define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ -#define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ -#define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value - with original alpha channel value */ -/** - * @} - */ - -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) -/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion - * @{ - */ -#define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ -#define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ -/** - * @} - */ - -/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap - * @{ - */ -#define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ -#define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ -/** - * @} - */ -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - - - - -/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode - * @{ - */ -#define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ -#define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ -/** - * @} - */ - -/** @defgroup DMA2D_Interrupts DMA2D Interrupts - * @{ - */ -#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ -#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ -#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ -#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ -#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ -#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ -/** - * @} - */ - -/** @defgroup DMA2D_Flags DMA2D Flags - * @{ - */ -#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ -#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ -#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ -#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ -#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ -#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ -/** - * @} - */ - -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -/** - * @brief HAL DMA2D common Callback ID enumeration definition - */ -typedef enum -{ - HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ - HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ - HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ - HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ - HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ - HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ -} HAL_DMA2D_CallbackIDTypeDef; -#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ - - -/** - * @} - */ -/* Exported macros ------------------------------------------------------------*/ -/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros - * @{ - */ - -/** @brief Reset DMA2D handle state - * @param __HANDLE__ specifies the DMA2D handle. - * @retval None - */ -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - }while(0) -#else -#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) -#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ - - -/** - * @brief Enable the DMA2D. - * @param __HANDLE__ DMA2D handle - * @retval None. - */ -#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) - - -/* Interrupt & Flag management */ -/** - * @brief Get the DMA2D pending flags. - * @param __HANDLE__ DMA2D handle - * @param __FLAG__ flag to check. - * This parameter can be any combination of the following values: - * @arg DMA2D_FLAG_CE: Configuration error flag - * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag - * @arg DMA2D_FLAG_CAE: CLUT access error flag - * @arg DMA2D_FLAG_TW: Transfer Watermark flag - * @arg DMA2D_FLAG_TC: Transfer complete flag - * @arg DMA2D_FLAG_TE: Transfer error flag - * @retval The state of FLAG. - */ -#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) - -/** - * @brief Clear the DMA2D pending flags. - * @param __HANDLE__ DMA2D handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA2D_FLAG_CE: Configuration error flag - * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag - * @arg DMA2D_FLAG_CAE: CLUT access error flag - * @arg DMA2D_FLAG_TW: Transfer Watermark flag - * @arg DMA2D_FLAG_TC: Transfer complete flag - * @arg DMA2D_FLAG_TE: Transfer error flag - * @retval None - */ -#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) - -/** - * @brief Enable the specified DMA2D interrupts. - * @param __HANDLE__ DMA2D handle - * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg DMA2D_IT_CE: Configuration error interrupt mask - * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask - * @arg DMA2D_IT_CAE: CLUT access error interrupt mask - * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask - * @arg DMA2D_IT_TC: Transfer complete interrupt mask - * @arg DMA2D_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified DMA2D interrupts. - * @param __HANDLE__ DMA2D handle - * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg DMA2D_IT_CE: Configuration error interrupt mask - * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask - * @arg DMA2D_IT_CAE: CLUT access error interrupt mask - * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask - * @arg DMA2D_IT_TC: Transfer complete interrupt mask - * @arg DMA2D_IT_TE: Transfer error interrupt mask - * @retval None - */ -#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified DMA2D interrupt source is enabled or not. - * @param __HANDLE__ DMA2D handle - * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. - * This parameter can be one of the following values: - * @arg DMA2D_IT_CE: Configuration error interrupt mask - * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask - * @arg DMA2D_IT_CAE: CLUT access error interrupt mask - * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask - * @arg DMA2D_IT_TC: Transfer complete interrupt mask - * @arg DMA2D_IT_TE: Transfer error interrupt mask - * @retval The state of INTERRUPT source. - */ -#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions - * @{ - */ - -/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions *******************************/ -HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); -HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); -void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); -void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, - pDMA2D_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ - -/** - * @} - */ - - -/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, - uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, - uint32_t DstAddress, uint32_t Width, uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, - uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, - uint32_t DstAddress, uint32_t Width, uint32_t Height); -HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); -HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); -HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); -HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, - uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, - uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); -void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); -void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); -void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); - -/** - * @} - */ - -/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); -HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); -HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); -HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); - -/** - * @} - */ - -/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State functions ***************************************************/ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ - -/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants - * @{ - */ - -/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark - * @{ - */ -#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ -/** - * @} - */ - -/** @defgroup DMA2D_Color_Value DMA2D Color Value - * @{ - */ -#define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ -/** - * @} - */ - -/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers - * @{ - */ -#define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ -/** - * @} - */ - -/** @defgroup DMA2D_Layers DMA2D Layers - * @{ - */ -#define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ -#define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ -/** - * @} - */ - -/** @defgroup DMA2D_Offset DMA2D Offset - * @{ - */ -#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ -/** - * @} - */ - -/** @defgroup DMA2D_Size DMA2D Size - * @{ - */ -#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ -#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ -/** - * @} - */ - -/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size - * @{ - */ -#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ -/** - * @} - */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Macros DMA2D Private Macros - * @{ - */ -#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ - || ((LAYER) == DMA2D_FOREGROUND_LAYER)) - -#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ - ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) - -#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ - ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ - ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ - ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ - ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) - -#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) -#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) -#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) -#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) - -#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ - ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ - ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ - ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ - ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ - ((INPUT_CM) == DMA2D_INPUT_L8) || \ - ((INPUT_CM) == DMA2D_INPUT_AL44) || \ - ((INPUT_CM) == DMA2D_INPUT_AL88) || \ - ((INPUT_CM) == DMA2D_INPUT_L4) || \ - ((INPUT_CM) == DMA2D_INPUT_A8) || \ - ((INPUT_CM) == DMA2D_INPUT_A4)) - -#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ - ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ - ((AlphaMode) == DMA2D_COMBINE_ALPHA)) - -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) -#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ - ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) - -#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ - ((RB_Swap) == DMA2D_RB_SWAP)) -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - - - -#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) -#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) -#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) -#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ - ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ - ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) -#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ - ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ - ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (DMA2D) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_DMA2D_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h index 286fb306..5d76e9f0 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma_ex.h @@ -1,183 +1,183 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma_ex.h - * @author MCD Application Team - * @brief Header file of DMA HAL extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_DMA_EX_H -#define __STM32F7xx_HAL_DMA_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMAEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Types DMAEx Exported Types - * @brief DMAEx Exported types - * @{ - */ - -/** - * @brief HAL DMA Memory definition - */ -typedef enum -{ - MEMORY0 = 0x00U, /*!< Memory 0 */ - MEMORY1 = 0x01U, /*!< Memory 1 */ - -}HAL_DMA_MemoryTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @brief DMA Exported constants - * @{ - */ - -/** @defgroup DMAEx_Channel_selection DMA Channel selection - * @brief DMAEx channel selection - * @{ - */ -#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ -#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ -#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ -#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ -#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ -#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ -#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ -#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) || defined (STM32F730xx) -#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ -#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ -#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/ -#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11*/ -#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12*/ -#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13*/ -#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/ -#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions - * @brief DMAEx Exported functions - * @{ - */ - -/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * @{ - */ - -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); - -/** - * @} - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Macros DMA Private Macros - * @brief DMAEx private macros - * @{ - */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) || defined (STM32F730xx) -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ - ((CHANNEL) == DMA_CHANNEL_1) || \ - ((CHANNEL) == DMA_CHANNEL_2) || \ - ((CHANNEL) == DMA_CHANNEL_3) || \ - ((CHANNEL) == DMA_CHANNEL_4) || \ - ((CHANNEL) == DMA_CHANNEL_5) || \ - ((CHANNEL) == DMA_CHANNEL_6) || \ - ((CHANNEL) == DMA_CHANNEL_7) || \ - ((CHANNEL) == DMA_CHANNEL_8) || \ - ((CHANNEL) == DMA_CHANNEL_9) || \ - ((CHANNEL) == DMA_CHANNEL_10) || \ - ((CHANNEL) == DMA_CHANNEL_11) || \ - ((CHANNEL) == DMA_CHANNEL_12) || \ - ((CHANNEL) == DMA_CHANNEL_13) || \ - ((CHANNEL) == DMA_CHANNEL_14) || \ - ((CHANNEL) == DMA_CHANNEL_15)) -#else -#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ - ((CHANNEL) == DMA_CHANNEL_1) || \ - ((CHANNEL) == DMA_CHANNEL_2) || \ - ((CHANNEL) == DMA_CHANNEL_3) || \ - ((CHANNEL) == DMA_CHANNEL_4) || \ - ((CHANNEL) == DMA_CHANNEL_5) || \ - ((CHANNEL) == DMA_CHANNEL_6) || \ - ((CHANNEL) == DMA_CHANNEL_7)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/ -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Functions DMAEx Private Functions - * @brief DMAEx Private functions - * @{ - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_DMA_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma_ex.h + * @author MCD Application Team + * @brief Header file of DMA HAL extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_DMA_EX_H +#define __STM32F7xx_HAL_DMA_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup DMAEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Types DMAEx Exported Types + * @brief DMAEx Exported types + * @{ + */ + +/** + * @brief HAL DMA Memory definition + */ +typedef enum +{ + MEMORY0 = 0x00U, /*!< Memory 0 */ + MEMORY1 = 0x01U, /*!< Memory 1 */ + +}HAL_DMA_MemoryTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup DMA_Exported_Constants DMA Exported Constants + * @brief DMA Exported constants + * @{ + */ + +/** @defgroup DMAEx_Channel_selection DMA Channel selection + * @brief DMAEx channel selection + * @{ + */ +#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ +#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ +#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ +#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ +#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ +#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ +#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ +#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ +#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ +#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/ +#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11*/ +#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12*/ +#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13*/ +#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/ +#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions + * @brief DMAEx Exported functions + * @{ + */ + +/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * @{ + */ + +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory); + +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Macros DMA Private Macros + * @brief DMAEx private macros + * @{ + */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7) || \ + ((CHANNEL) == DMA_CHANNEL_8) || \ + ((CHANNEL) == DMA_CHANNEL_9) || \ + ((CHANNEL) == DMA_CHANNEL_10) || \ + ((CHANNEL) == DMA_CHANNEL_11) || \ + ((CHANNEL) == DMA_CHANNEL_12) || \ + ((CHANNEL) == DMA_CHANNEL_13) || \ + ((CHANNEL) == DMA_CHANNEL_14) || \ + ((CHANNEL) == DMA_CHANNEL_15)) +#else +#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ + ((CHANNEL) == DMA_CHANNEL_1) || \ + ((CHANNEL) == DMA_CHANNEL_2) || \ + ((CHANNEL) == DMA_CHANNEL_3) || \ + ((CHANNEL) == DMA_CHANNEL_4) || \ + ((CHANNEL) == DMA_CHANNEL_5) || \ + ((CHANNEL) == DMA_CHANNEL_6) || \ + ((CHANNEL) == DMA_CHANNEL_7)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx*/ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup DMAEx_Private_Functions DMAEx Private Functions + * @brief DMAEx Private functions + * @{ + */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_DMA_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h deleted file mode 100644 index 9144a464..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dsi.h +++ /dev/null @@ -1,1377 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dsi.h - * @author MCD Application Team - * @brief Header file of DSI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_DSI_H -#define STM32F7xx_HAL_DSI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined(DSI) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DSI DSI - * @brief DSI HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DSI_Exported_Types DSI Exported Types - * @{ - */ -/** - * @brief DSI Init Structure definition - */ -typedef struct -{ - uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control - This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ - - uint32_t TXEscapeCkdiv; /*!< TX Escape clock division - The values 0 and 1 stop the TX_ESC clock generation */ - - uint32_t NumberOfLanes; /*!< Number of lanes - This parameter can be any value of @ref DSI_Number_Of_Lanes */ - -} DSI_InitTypeDef; - -/** - * @brief DSI PLL Clock structure definition - */ -typedef struct -{ - uint32_t PLLNDIV; /*!< PLL Loop Division Factor - This parameter must be a value between 10 and 125 */ - - uint32_t PLLIDF; /*!< PLL Input Division Factor - This parameter can be any value of @ref DSI_PLL_IDF */ - - uint32_t PLLODF; /*!< PLL Output Division Factor - This parameter can be any value of @ref DSI_PLL_ODF */ - -} DSI_PLLInitTypeDef; - -/** - * @brief DSI Video mode configuration - */ -typedef struct -{ - uint32_t VirtualChannelID; /*!< Virtual channel ID */ - - uint32_t ColorCoding; /*!< Color coding for LTDC interface - This parameter can be any value of @ref DSI_Color_Coding */ - - uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using - 18-bit configuration). - This parameter can be any value of @ref DSI_LooselyPacked */ - - uint32_t Mode; /*!< Video mode type - This parameter can be any value of @ref DSI_Video_Mode_Type */ - - uint32_t PacketSize; /*!< Video packet size */ - - uint32_t NumberOfChunks; /*!< Number of chunks */ - - uint32_t NullPacketSize; /*!< Null packet size */ - - uint32_t HSPolarity; /*!< HSYNC pin polarity - This parameter can be any value of @ref DSI_HSYNC_Polarity */ - - uint32_t VSPolarity; /*!< VSYNC pin polarity - This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ - - uint32_t DEPolarity; /*!< Data Enable pin polarity - This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ - - uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ - - uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ - - uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ - - uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ - - uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ - - uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ - - uint32_t VerticalActive; /*!< Vertical active duration */ - - uint32_t LPCommandEnable; /*!< Low-power command enable - This parameter can be any value of @ref DSI_LP_Command */ - - uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that - can fit in a line during VSA, VBP and VFP regions */ - - uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that - can fit in a line during VACT region */ - - uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable - This parameter can be any value of @ref DSI_LP_HFP */ - - uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable - This parameter can be any value of @ref DSI_LP_HBP */ - - uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable - This parameter can be any value of @ref DSI_LP_VACT */ - - uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable - This parameter can be any value of @ref DSI_LP_VFP */ - - uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable - This parameter can be any value of @ref DSI_LP_VBP */ - - uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable - This parameter can be any value of @ref DSI_LP_VSYNC */ - - uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable - This parameter can be any value of @ref DSI_FBTA_acknowledge */ - -} DSI_VidCfgTypeDef; - -/** - * @brief DSI Adapted command mode configuration - */ -typedef struct -{ - uint32_t VirtualChannelID; /*!< Virtual channel ID */ - - uint32_t ColorCoding; /*!< Color coding for LTDC interface - This parameter can be any value of @ref DSI_Color_Coding */ - - uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in - pixels. This parameter can be any value between 0x00 and 0xFFFFU */ - - uint32_t TearingEffectSource; /*!< Tearing effect source - This parameter can be any value of @ref DSI_TearingEffectSource */ - - uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity - This parameter can be any value of @ref DSI_TearingEffectPolarity */ - - uint32_t HSPolarity; /*!< HSYNC pin polarity - This parameter can be any value of @ref DSI_HSYNC_Polarity */ - - uint32_t VSPolarity; /*!< VSYNC pin polarity - This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ - - uint32_t DEPolarity; /*!< Data Enable pin polarity - This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ - - uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted - This parameter can be any value of @ref DSI_Vsync_Polarity */ - - uint32_t AutomaticRefresh; /*!< Automatic refresh mode - This parameter can be any value of @ref DSI_AutomaticRefresh */ - - uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable - This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ - -} DSI_CmdCfgTypeDef; - -/** - * @brief DSI command transmission mode configuration - */ -typedef struct -{ - uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission - This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ - - uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission - This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ - - uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission - This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ - - uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission - This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ - - uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission - This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ - - uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission - This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ - - uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission - This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ - - uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission - This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ - - uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission - This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ - - uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission - This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ - - uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission - This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ - - uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission - This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ - - uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable - This parameter can be any value of @ref DSI_AcknowledgeRequest */ - -} DSI_LPCmdTypeDef; - -/** - * @brief DSI PHY Timings definition - */ -typedef struct -{ - uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed - to low-power transmission */ - - uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power - to high-speed transmission */ - - uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed - to low-power transmission */ - - uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power - to high-speed transmission */ - - uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ - - uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the - Stop state */ - -} DSI_PHY_TimerTypeDef; - -/** - * @brief DSI HOST Timeouts definition - */ -typedef struct -{ - uint32_t TimeoutCkdiv; /*!< Time-out clock division */ - - uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ - - uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ - - uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ - - uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ - - uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ - - uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode - This parameter can be any value of @ref DSI_HS_PrespMode */ - - uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ - - uint32_t BTATimeout; /*!< BTA time-out */ - -} DSI_HOST_TimeoutTypeDef; - -/** - * @brief DSI States Structure definition - */ -typedef enum -{ - HAL_DSI_STATE_RESET = 0x00U, - HAL_DSI_STATE_READY = 0x01U, - HAL_DSI_STATE_ERROR = 0x02U, - HAL_DSI_STATE_BUSY = 0x03U, - HAL_DSI_STATE_TIMEOUT = 0x04U -} HAL_DSI_StateTypeDef; - -/** - * @brief DSI Handle Structure definition - */ -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -typedef struct __DSI_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ -{ - DSI_TypeDef *Instance; /*!< Register base address */ - DSI_InitTypeDef Init; /*!< DSI required parameters */ - HAL_LockTypeDef Lock; /*!< DSI peripheral status */ - __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ - __IO uint32_t ErrorCode; /*!< DSI Error code */ - uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ - -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) - void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ - void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ - void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ - - void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ - void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ - -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - -} DSI_HandleTypeDef; - -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -/** - * @brief HAL DSI Callback ID enumeration definition - */ -typedef enum -{ - HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ - HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ - - HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ - HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ - HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ - -} HAL_DSI_CallbackIDTypeDef; - -/** - * @brief HAL DSI Callback pointer definition - */ -typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ - -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DSI_Exported_Constants DSI Exported Constants - * @{ - */ -/** @defgroup DSI_DCS_Command DSI DCS Command - * @{ - */ -#define DSI_ENTER_IDLE_MODE 0x39U -#define DSI_ENTER_INVERT_MODE 0x21U -#define DSI_ENTER_NORMAL_MODE 0x13U -#define DSI_ENTER_PARTIAL_MODE 0x12U -#define DSI_ENTER_SLEEP_MODE 0x10U -#define DSI_EXIT_IDLE_MODE 0x38U -#define DSI_EXIT_INVERT_MODE 0x20U -#define DSI_EXIT_SLEEP_MODE 0x11U -#define DSI_GET_3D_CONTROL 0x3FU -#define DSI_GET_ADDRESS_MODE 0x0BU -#define DSI_GET_BLUE_CHANNEL 0x08U -#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU -#define DSI_GET_DISPLAY_MODE 0x0DU -#define DSI_GET_GREEN_CHANNEL 0x07U -#define DSI_GET_PIXEL_FORMAT 0x0CU -#define DSI_GET_POWER_MODE 0x0AU -#define DSI_GET_RED_CHANNEL 0x06U -#define DSI_GET_SCANLINE 0x45U -#define DSI_GET_SIGNAL_MODE 0x0EU -#define DSI_NOP 0x00U -#define DSI_READ_DDB_CONTINUE 0xA8U -#define DSI_READ_DDB_START 0xA1U -#define DSI_READ_MEMORY_CONTINUE 0x3EU -#define DSI_READ_MEMORY_START 0x2EU -#define DSI_SET_3D_CONTROL 0x3DU -#define DSI_SET_ADDRESS_MODE 0x36U -#define DSI_SET_COLUMN_ADDRESS 0x2AU -#define DSI_SET_DISPLAY_OFF 0x28U -#define DSI_SET_DISPLAY_ON 0x29U -#define DSI_SET_GAMMA_CURVE 0x26U -#define DSI_SET_PAGE_ADDRESS 0x2BU -#define DSI_SET_PARTIAL_COLUMNS 0x31U -#define DSI_SET_PARTIAL_ROWS 0x30U -#define DSI_SET_PIXEL_FORMAT 0x3AU -#define DSI_SET_SCROLL_AREA 0x33U -#define DSI_SET_SCROLL_START 0x37U -#define DSI_SET_TEAR_OFF 0x34U -#define DSI_SET_TEAR_ON 0x35U -#define DSI_SET_TEAR_SCANLINE 0x44U -#define DSI_SET_VSYNC_TIMING 0x40U -#define DSI_SOFT_RESET 0x01U -#define DSI_WRITE_LUT 0x2DU -#define DSI_WRITE_MEMORY_CONTINUE 0x3CU -#define DSI_WRITE_MEMORY_START 0x2CU -/** - * @} - */ - -/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type - * @{ - */ -#define DSI_VID_MODE_NB_PULSES 0U -#define DSI_VID_MODE_NB_EVENTS 1U -#define DSI_VID_MODE_BURST 2U -/** - * @} - */ - -/** @defgroup DSI_Color_Mode DSI Color Mode - * @{ - */ -#define DSI_COLOR_MODE_FULL 0x00000000U -#define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM -/** - * @} - */ - -/** @defgroup DSI_ShutDown DSI ShutDown - * @{ - */ -#define DSI_DISPLAY_ON 0x00000000U -#define DSI_DISPLAY_OFF DSI_WCR_SHTDN -/** - * @} - */ - -/** @defgroup DSI_LP_Command DSI LP Command - * @{ - */ -#define DSI_LP_COMMAND_DISABLE 0x00000000U -#define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE -/** - * @} - */ - -/** @defgroup DSI_LP_HFP DSI LP HFP - * @{ - */ -#define DSI_LP_HFP_DISABLE 0x00000000U -#define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE -/** - * @} - */ - -/** @defgroup DSI_LP_HBP DSI LP HBP - * @{ - */ -#define DSI_LP_HBP_DISABLE 0x00000000U -#define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE -/** - * @} - */ - -/** @defgroup DSI_LP_VACT DSI LP VACT - * @{ - */ -#define DSI_LP_VACT_DISABLE 0x00000000U -#define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE -/** - * @} - */ - -/** @defgroup DSI_LP_VFP DSI LP VFP - * @{ - */ -#define DSI_LP_VFP_DISABLE 0x00000000U -#define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE -/** - * @} - */ - -/** @defgroup DSI_LP_VBP DSI LP VBP - * @{ - */ -#define DSI_LP_VBP_DISABLE 0x00000000U -#define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE -/** - * @} - */ - -/** @defgroup DSI_LP_VSYNC DSI LP VSYNC - * @{ - */ -#define DSI_LP_VSYNC_DISABLE 0x00000000U -#define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE -/** - * @} - */ - -/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge - * @{ - */ -#define DSI_FBTAA_DISABLE 0x00000000U -#define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE -/** - * @} - */ - -/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source - * @{ - */ -#define DSI_TE_DSILINK 0x00000000U -#define DSI_TE_EXTERNAL DSI_WCFGR_TESRC -/** - * @} - */ - -/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity - * @{ - */ -#define DSI_TE_RISING_EDGE 0x00000000U -#define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL -/** - * @} - */ - -/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity - * @{ - */ -#define DSI_VSYNC_FALLING 0x00000000U -#define DSI_VSYNC_RISING DSI_WCFGR_VSPOL -/** - * @} - */ - -/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh - * @{ - */ -#define DSI_AR_DISABLE 0x00000000U -#define DSI_AR_ENABLE DSI_WCFGR_AR -/** - * @} - */ - -/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request - * @{ - */ -#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U -#define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE -/** - * @} - */ - -/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request - * @{ - */ -#define DSI_ACKNOWLEDGE_DISABLE 0x00000000U -#define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE -/** - * @} - */ - -/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP - * @{ - */ -#define DSI_LP_GSW0P_DISABLE 0x00000000U -#define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP - * @{ - */ -#define DSI_LP_GSW1P_DISABLE 0x00000000U -#define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP - * @{ - */ -#define DSI_LP_GSW2P_DISABLE 0x00000000U -#define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP - * @{ - */ -#define DSI_LP_GSR0P_DISABLE 0x00000000U -#define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP - * @{ - */ -#define DSI_LP_GSR1P_DISABLE 0x00000000U -#define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP - * @{ - */ -#define DSI_LP_GSR2P_DISABLE 0x00000000U -#define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite - * @{ - */ -#define DSI_LP_GLW_DISABLE 0x00000000U -#define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX -/** - * @} - */ - -/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP - * @{ - */ -#define DSI_LP_DSW0P_DISABLE 0x00000000U -#define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP - * @{ - */ -#define DSI_LP_DSW1P_DISABLE 0x00000000U -#define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP - * @{ - */ -#define DSI_LP_DSR0P_DISABLE 0x00000000U -#define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX -/** - * @} - */ - -/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write - * @{ - */ -#define DSI_LP_DLW_DISABLE 0x00000000U -#define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX -/** - * @} - */ - -/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet - * @{ - */ -#define DSI_LP_MRDP_DISABLE 0x00000000U -#define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS -/** - * @} - */ - -/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode - * @{ - */ -#define DSI_HS_PM_DISABLE 0x00000000U -#define DSI_HS_PM_ENABLE DSI_TCCR3_PM -/** - * @} - */ - - -/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control - * @{ - */ -#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U -#define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR -/** - * @} - */ - -/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes - * @{ - */ -#define DSI_ONE_DATA_LANE 0U -#define DSI_TWO_DATA_LANES 1U -/** - * @} - */ - -/** @defgroup DSI_FlowControl DSI Flow Control - * @{ - */ -#define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE -#define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE -#define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE -#define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE -#define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE -#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ - DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ - DSI_FLOW_CONTROL_EOTP_TX) -/** - * @} - */ - -/** @defgroup DSI_Color_Coding DSI Color Coding - * @{ - */ -#define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ -#define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ -#define DSI_RGB888 0x00000005U -/** - * @} - */ - -/** @defgroup DSI_LooselyPacked DSI Loosely Packed - * @{ - */ -#define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE -#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U -/** - * @} - */ - -/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity - * @{ - */ -#define DSI_HSYNC_ACTIVE_HIGH 0x00000000U -#define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP -/** - * @} - */ - -/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity - * @{ - */ -#define DSI_VSYNC_ACTIVE_HIGH 0x00000000U -#define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP -/** - * @} - */ - -/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity - * @{ - */ -#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U -#define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP -/** - * @} - */ - -/** @defgroup DSI_PLL_IDF DSI PLL IDF - * @{ - */ -#define DSI_PLL_IN_DIV1 0x00000001U -#define DSI_PLL_IN_DIV2 0x00000002U -#define DSI_PLL_IN_DIV3 0x00000003U -#define DSI_PLL_IN_DIV4 0x00000004U -#define DSI_PLL_IN_DIV5 0x00000005U -#define DSI_PLL_IN_DIV6 0x00000006U -#define DSI_PLL_IN_DIV7 0x00000007U -/** - * @} - */ - -/** @defgroup DSI_PLL_ODF DSI PLL ODF - * @{ - */ -#define DSI_PLL_OUT_DIV1 0x00000000U -#define DSI_PLL_OUT_DIV2 0x00000001U -#define DSI_PLL_OUT_DIV4 0x00000002U -#define DSI_PLL_OUT_DIV8 0x00000003U -/** - * @} - */ - -/** @defgroup DSI_Flags DSI Flags - * @{ - */ -#define DSI_FLAG_TE DSI_WISR_TEIF -#define DSI_FLAG_ER DSI_WISR_ERIF -#define DSI_FLAG_BUSY DSI_WISR_BUSY -#define DSI_FLAG_PLLLS DSI_WISR_PLLLS -#define DSI_FLAG_PLLL DSI_WISR_PLLLIF -#define DSI_FLAG_PLLU DSI_WISR_PLLUIF -#define DSI_FLAG_RRS DSI_WISR_RRS -#define DSI_FLAG_RR DSI_WISR_RRIF -/** - * @} - */ - -/** @defgroup DSI_Interrupts DSI Interrupts - * @{ - */ -#define DSI_IT_TE DSI_WIER_TEIE -#define DSI_IT_ER DSI_WIER_ERIE -#define DSI_IT_PLLL DSI_WIER_PLLLIE -#define DSI_IT_PLLU DSI_WIER_PLLUIE -#define DSI_IT_RR DSI_WIER_RRIE -/** - * @} - */ - -/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type - * @{ - */ -#define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ -#define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ -#define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ -#define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ -#define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ -/** - * @} - */ - -/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type - * @{ - */ -#define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ -#define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ -/** - * @} - */ - -/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type - * @{ - */ -#define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ -#define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ -#define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ -#define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ -/** - * @} - */ - -/** @defgroup DSI_Error_Data_Type DSI Error Data Type - * @{ - */ -#define HAL_DSI_ERROR_NONE 0U -#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */ -#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ -#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */ -#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */ -#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ -#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ -#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ -#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ -#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ -#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup DSI_Lane_Group DSI Lane Group - * @{ - */ -#define DSI_CLOCK_LANE 0x00000000U -#define DSI_DATA_LANES 0x00000001U -/** - * @} - */ - -/** @defgroup DSI_Communication_Delay DSI Communication Delay - * @{ - */ -#define DSI_SLEW_RATE_HSTX 0x00000000U -#define DSI_SLEW_RATE_LPTX 0x00000001U -#define DSI_HS_DELAY 0x00000002U -/** - * @} - */ - -/** @defgroup DSI_CustomLane DSI CustomLane - * @{ - */ -#define DSI_SWAP_LANE_PINS 0x00000000U -#define DSI_INVERT_HS_SIGNAL 0x00000001U -/** - * @} - */ - -/** @defgroup DSI_Lane_Select DSI Lane Select - * @{ - */ -#define DSI_CLK_LANE 0x00000000U -#define DSI_DATA_LANE0 0x00000001U -#define DSI_DATA_LANE1 0x00000002U -/** - * @} - */ - -/** @defgroup DSI_PHY_Timing DSI PHY Timing - * @{ - */ -#define DSI_TCLK_POST 0x00000000U -#define DSI_TLPX_CLK 0x00000001U -#define DSI_THS_EXIT 0x00000002U -#define DSI_TLPX_DATA 0x00000003U -#define DSI_THS_ZERO 0x00000004U -#define DSI_THS_TRAIL 0x00000005U -#define DSI_THS_PREPARE 0x00000006U -#define DSI_TCLK_ZERO 0x00000007U -#define DSI_TCLK_PREPARE 0x00000008U -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup DSI_Exported_Macros DSI Exported Macros - * @{ - */ - -/** - * @brief Reset DSI handle state. - * @param __HANDLE__ DSI handle - * @retval None - */ -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) -#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ - -/** - * @brief Enables the DSI host. - * @param __HANDLE__ DSI handle - * @retval None. - */ -#define __HAL_DSI_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - /* Delay after an DSI Host enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - UNUSED(tmpreg); \ - } while(0U) - -/** - * @brief Disables the DSI host. - * @param __HANDLE__ DSI handle - * @retval None. - */ -#define __HAL_DSI_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - /* Delay after an DSI Host disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - UNUSED(tmpreg); \ - } while(0U) - -/** - * @brief Enables the DSI wrapper. - * @param __HANDLE__ DSI handle - * @retval None. - */ -#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI wrapper enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - UNUSED(tmpreg); \ - } while(0U) - -/** - * @brief Disable the DSI wrapper. - * @param __HANDLE__ DSI handle - * @retval None. - */ -#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI wrapper disabling*/ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - UNUSED(tmpreg); \ - } while(0U) - -/** - * @brief Enables the DSI PLL. - * @param __HANDLE__ DSI handle - * @retval None. - */ -#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - /* Delay after an DSI PLL enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - UNUSED(tmpreg); \ - } while(0U) - -/** - * @brief Disables the DSI PLL. - * @param __HANDLE__ DSI handle - * @retval None. - */ -#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - /* Delay after an DSI PLL disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - UNUSED(tmpreg); \ - } while(0U) - -/** - * @brief Enables the DSI regulator. - * @param __HANDLE__ DSI handle - * @retval None. - */ -#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - /* Delay after an DSI regulator enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - UNUSED(tmpreg); \ - } while(0U) - -/** - * @brief Disables the DSI regulator. - * @param __HANDLE__ DSI handle - * @retval None. - */ -#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - /* Delay after an DSI regulator disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - UNUSED(tmpreg); \ - } while(0U) - -/** - * @brief Get the DSI pending flags. - * @param __HANDLE__ DSI handle. - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag - * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag - * @arg DSI_FLAG_BUSY : Busy Flag - * @arg DSI_FLAG_PLLLS: PLL Lock Status - * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag - * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag - * @arg DSI_FLAG_RRS : Regulator Ready Flag - * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) - -/** - * @brief Clears the DSI pending flags. - * @param __HANDLE__ DSI handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag - * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag - * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag - * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag - * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag - * @retval None - */ -#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) - -/** - * @brief Enables the specified DSI interrupts. - * @param __HANDLE__ DSI handle. - * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg DSI_IT_TE : Tearing Effect Interrupt - * @arg DSI_IT_ER : End of Refresh Interrupt - * @arg DSI_IT_PLLL: PLL Lock Interrupt - * @arg DSI_IT_PLLU: PLL Unlock Interrupt - * @arg DSI_IT_RR : Regulator Ready Interrupt - * @retval None - */ -#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) - -/** - * @brief Disables the specified DSI interrupts. - * @param __HANDLE__ DSI handle - * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg DSI_IT_TE : Tearing Effect Interrupt - * @arg DSI_IT_ER : End of Refresh Interrupt - * @arg DSI_IT_PLLL: PLL Lock Interrupt - * @arg DSI_IT_PLLU: PLL Unlock Interrupt - * @arg DSI_IT_RR : Regulator Ready Interrupt - * @retval None - */ -#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) - -/** - * @brief Checks whether the specified DSI interrupt source is enabled or not. - * @param __HANDLE__ DSI handle - * @param __INTERRUPT__ specifies the DSI interrupt source to check. - * This parameter can be one of the following values: - * @arg DSI_IT_TE : Tearing Effect Interrupt - * @arg DSI_IT_ER : End of Refresh Interrupt - * @arg DSI_IT_PLLL: PLL Lock Interrupt - * @arg DSI_IT_PLLU: PLL Unlock Interrupt - * @arg DSI_IT_RR : Regulator Ready Interrupt - * @retval The state of INTERRUPT (SET or RESET). - */ -#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DSI_Exported_Functions DSI Exported Functions - * @{ - */ -/** @defgroup DSI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * @{ - */ -HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); -HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); -void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); -void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, - pDSI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup DSI_Group2 IO operation functions - * @brief IO operation functions - * @{ - */ -void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); -void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); -void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); -void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); -/** - * @} - */ - -/** @defgroup DSI_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); -HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); -HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); -HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); -HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); -HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); -HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); -HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); -HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); -HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t Param1, - uint32_t Param2); -HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t NbParams, - uint32_t Param1, - const uint8_t *ParametersTable); -HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, - uint32_t ChannelNbr, - uint8_t *Array, - uint32_t Size, - uint32_t Mode, - uint32_t DCSCmd, - uint8_t *ParametersTable); -HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); - -HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); -HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); - -HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, - uint32_t Value); -HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); -HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); -HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, - FunctionalState State); -HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, - uint32_t Value); -HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); -HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); -HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); -HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); -HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); - -/** - * @} - */ - -/** @defgroup DSI_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * @{ - */ -uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi); -HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi); - -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DSI_Private_Constants DSI Private Constants - * @{ - */ -#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DSI_Private_Macros DSI Private Macros - * @{ - */ -#define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) -#define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ - ((IDF) == DSI_PLL_IN_DIV2) || \ - ((IDF) == DSI_PLL_IN_DIV3) || \ - ((IDF) == DSI_PLL_IN_DIV4) || \ - ((IDF) == DSI_PLL_IN_DIV5) || \ - ((IDF) == DSI_PLL_IN_DIV6) || \ - ((IDF) == DSI_PLL_IN_DIV7)) -#define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ - ((ODF) == DSI_PLL_OUT_DIV2) || \ - ((ODF) == DSI_PLL_OUT_DIV4) || \ - ((ODF) == DSI_PLL_OUT_DIV8)) -#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\ - || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) -#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\ - || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) -#define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) -#define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) -#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\ - || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) -#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ - || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) -#define IS_DSI_VSYNC_POLARITY(Vsync) (((Vsync) == DSI_VSYNC_ACTIVE_HIGH)\ - || ((Vsync) == DSI_VSYNC_ACTIVE_LOW)) -#define IS_DSI_HSYNC_POLARITY(Hsync) (((Hsync) == DSI_HSYNC_ACTIVE_HIGH)\ - || ((Hsync) == DSI_HSYNC_ACTIVE_LOW)) -#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ - ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ - ((VideoModeType) == DSI_VID_MODE_BURST)) -#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\ - || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) -#define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) -#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\ - || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) -#define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) -#define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) -#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\ - || ((LPVActive) == DSI_LP_VACT_ENABLE)) -#define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) -#define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) -#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\ - || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) -#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\ - || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) -#define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) -#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\ - || ((TEPolarity) == DSI_TE_FALLING_EDGE)) -#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\ - || ((AutomaticRefresh) == DSI_AR_ENABLE)) -#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\ - || ((VSPolarity) == DSI_VSYNC_RISING)) -#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\ - || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) -#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\ - || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) -#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\ - || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) -#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\ - || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) -#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\ - || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) -#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\ - || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) -#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\ - || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) -#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\ - || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) -#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\ - || ((LP_GLW) == DSI_LP_GLW_ENABLE)) -#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\ - || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) -#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\ - || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) -#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\ - || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) -#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\ - || ((LP_DLW) == DSI_LP_DLW_ENABLE)) -#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\ - || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) -#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ - ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ - ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ - ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ - ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) -#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ - ((MODE) == DSI_GEN_LONG_PKT_WRITE)) -#define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ - ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ - ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ - ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) -#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \ - ((CommDelay) == DSI_SLEW_RATE_LPTX) || \ - ((CommDelay) == DSI_HS_DELAY)) -#define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) -#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\ - || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) -#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \ - ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) -#define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ - ((Timing) == DSI_TLPX_CLK ) || \ - ((Timing) == DSI_THS_EXIT ) || \ - ((Timing) == DSI_TLPX_DATA ) || \ - ((Timing) == DSI_THS_ZERO ) || \ - ((Timing) == DSI_THS_TRAIL ) || \ - ((Timing) == DSI_THS_PREPARE ) || \ - ((Timing) == DSI_TCLK_ZERO ) || \ - ((Timing) == DSI_TCLK_PREPARE)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* DSI */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_DSI_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h deleted file mode 100644 index ccc28974..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_eth.h +++ /dev/null @@ -1,2017 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_eth.h - * @author MCD Application Team - * @brief Header file of ETH HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_ETH_H -#define STM32F7xx_HAL_ETH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined(ETH) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup ETH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -#ifndef ETH_TX_DESC_CNT -#define ETH_TX_DESC_CNT 4U -#endif /* ETH_TX_DESC_CNT */ - -#ifndef ETH_RX_DESC_CNT -#define ETH_RX_DESC_CNT 4U -#endif /* ETH_RX_DESC_CNT */ - - -/*********************** Descriptors struct def section ************************/ -/** @defgroup ETH_Exported_Types ETH Exported Types - * @{ - */ - -/** - * @brief ETH DMA Descriptor structure definition - */ -typedef struct -{ - __IO uint32_t DESC0; - __IO uint32_t DESC1; - __IO uint32_t DESC2; - __IO uint32_t DESC3; - __IO uint32_t DESC4; - __IO uint32_t DESC5; - __IO uint32_t DESC6; - __IO uint32_t DESC7; - uint32_t BackupAddr0; /* used to store rx buffer 1 address */ - uint32_t BackupAddr1; /* used to store rx buffer 2 address */ -} ETH_DMADescTypeDef; -/** - * - */ - -/** - * @brief ETH Buffers List structure definition - */ -typedef struct __ETH_BufferTypeDef -{ - uint8_t *buffer; /*gState = HAL_ETH_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ - } while(0) -#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @brief Enables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be - * enabled @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ - |= (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be - * disabled. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ - &= ~(__INTERRUPT__)) - -/** - * @brief Gets the ETHERNET DMA IT source enabled or disabled. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts - * @retval The ETH DMA IT Source enabled or disabled - */ -#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMAIER &\ - (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Gets the ETHERNET DMA IT pending bit. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts - * @retval The state of ETH DMA IT (SET or RESET) - */ -#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMASR &\ - (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Clears the ETHERNET DMA IT pending bit. - * @param __HANDLE__ : ETH Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR = (__INTERRUPT__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags - * @retval The state of ETH DMA FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &\ - ( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Clears the specified ETHERNET DMA flag. - * @param __HANDLE__: ETH Handle - * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags - * @retval The state of ETH DMA FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = ( __FLAG__)) - - - -/** - * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param __HANDLE__: ETH Handle - * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts - * @retval The state of ETH MAC IT (SET or RESET). - */ -#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ - ( __INTERRUPT__)) == ( __INTERRUPT__)) - -/*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */ -#define ETH_WAKEUP_EXTI_LINE 0x00080000U - -/** - * @brief Enable the ETH WAKEUP Exti Line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR |= (__EXTI_LINE__)) - -/** - * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval EXTI ETH WAKEUP Line Status. - */ -#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clear the ETH WAKEUP Exti flag. - * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief enable rising edge interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \ - (EXTI->RTSR |= (__EXTI_LINE__)) - -/** - * @brief enable falling edge interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\ - (EXTI->FTSR |= (__EXTI_LINE__)) - -/** - * @brief enable falling edge interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\ - (EXTI->FTSR |= (__EXTI_LINE__)) - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. - * @arg ETH_WAKEUP_EXTI_LINE - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) - -#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->PTPTSCR) & \ - (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__)) - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup ETH_Exported_Functions - * @{ - */ - -/** @addtogroup ETH_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de initialization functions **********************************/ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, - pETH_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup ETH_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); - -HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); -HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, - pETH_rxAllocateCallbackTypeDef rxAllocateCallback); -HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); -HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode); -HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); -HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); - -#ifdef HAL_ETH_USE_PTP -HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); -HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); -HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); -HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); -HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, - ETH_TimeTypeDef *timeoffset); -HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); -HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); -HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); -HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); -#endif /* HAL_ETH_USE_PTP */ - -HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout); -HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig); - -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, - uint32_t RegValue); -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, - uint32_t *pRegValue); - -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); -void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_RxAllocateCallback(uint8_t **buff); -void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); -void HAL_ETH_TxFreeCallback(uint32_t *buff); -void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); -/** - * @} - */ - -/** @addtogroup ETH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions **********************************************/ -/* MAC & DMA Configuration APIs **********************************************/ -HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); -HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); -void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); - -/* MAC VLAN Processing APIs ************************************************/ -void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, - uint32_t VLANIdentifier); - -/* MAC L2 Packet Filtering APIs **********************************************/ -HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); -HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig); -HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); -HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, - const uint8_t *pMACAddr); - -/* MAC Power Down APIs *****************************************************/ -void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, - const ETH_PowerDownConfigTypeDef *pPowerDownConfig); -void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); - -/** - * @} - */ - -/** @addtogroup ETH_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State functions **************************************************/ -HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth); -uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ETH */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_ETH_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h index 992d22eb..caf3ab39 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_exti.h @@ -1,317 +1,317 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_exti.h - * @author MCD Application Team - * @brief Header file of EXTI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_EXTI_H -#define STM32F7xx_HAL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup EXTI EXTI - * @brief EXTI HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Types EXTI Exported Types - * @{ - */ -typedef enum -{ - HAL_EXTI_COMMON_CB_ID = 0x00U -} EXTI_CallbackIDTypeDef; - -/** - * @brief EXTI Handle structure definition - */ -typedef struct -{ - uint32_t Line; /*!< Exti line number */ - void (* PendingCallback)(void); /*!< Exti pending callback */ -} EXTI_HandleTypeDef; - -/** - * @brief EXTI Configuration structure definition - */ -typedef struct -{ - uint32_t Line; /*!< The Exti line to be configured. This parameter - can be a value of @ref EXTI_Line */ - uint32_t Mode; /*!< The Exit Mode to be configured for a core. - This parameter can be a combination of @ref EXTI_Mode */ - uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter - can be a value of @ref EXTI_Trigger */ - uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. - This parameter is only possible for line 0 to 15. It - can be a value of @ref EXTI_GPIOSel */ -} EXTI_ConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_Line EXTI Line - * @{ - */ -#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ -#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ -#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ -#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ -#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ -#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ -#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ -#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ -#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ -#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ -#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ -#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ -#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ -#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ -#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ -#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ -#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ -#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ -#if defined(ETH) -#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ -#else -#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ -#endif /* ETH */ -#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ -#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ -#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */ -#if defined(EXTI_IMR_IM24) -#define EXTI_LINE_24 (EXTI_CONFIG | 0x18u) /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */ -#endif /* EXTI_IMR_IM24 */ -/** - * @} - */ - -/** @defgroup EXTI_Mode EXTI Mode - * @{ - */ -#define EXTI_MODE_NONE 0x00000000u -#define EXTI_MODE_INTERRUPT 0x00000001u -#define EXTI_MODE_EVENT 0x00000002u -/** - * @} - */ - -/** @defgroup EXTI_Trigger EXTI Trigger - * @{ - */ - -#define EXTI_TRIGGER_NONE 0x00000000u -#define EXTI_TRIGGER_RISING 0x00000001u -#define EXTI_TRIGGER_FALLING 0x00000002u -#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) -/** - * @} - */ - -/** @defgroup EXTI_GPIOSel EXTI GPIOSel - * @brief - * @{ - */ -#define EXTI_GPIOA 0x00000000u -#define EXTI_GPIOB 0x00000001u -#define EXTI_GPIOC 0x00000002u -#define EXTI_GPIOD 0x00000003u -#define EXTI_GPIOE 0x00000004u -#define EXTI_GPIOF 0x00000005u -#define EXTI_GPIOG 0x00000006u -#define EXTI_GPIOH 0x00000007u -#define EXTI_GPIOI 0x00000008u -#define EXTI_GPIOJ 0x00000009u -#if defined (GPIOK) -#define EXTI_GPIOK 0x0000000Au -#endif /* GPIOK */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** - * @} - */ - -/* Private constants --------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ -/** - * @brief EXTI Line property definition - */ -#define EXTI_PROPERTY_SHIFT 24u -#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) -#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) - -/** - * @brief EXTI bit usage - */ -#define EXTI_PIN_MASK 0x0000001Fu - -/** - * @brief EXTI Mask for interrupt & event mode - */ -#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) - -/** - * @brief EXTI Mask for trigger possibilities - */ -#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) - -/** - * @brief EXTI Line number - */ -#if defined(EXTI_IMR_IM24) -#define EXTI_LINE_NB 25u -#else -#define EXTI_LINE_NB 24u -#endif /* EXTI_IMR_IM24 */ - - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup EXTI_Private_Macros EXTI Private Macros - * @{ - */ -#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ - ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) - -#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ - (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) - -#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) - -#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_FALLING) || \ - ((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ - ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)) - -#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) - -#if defined (GPIOK) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH) || \ - ((__PORT__) == EXTI_GPIOI) || \ - ((__PORT__) == EXTI_GPIOJ) || \ - ((__PORT__) == EXTI_GPIOK)) -#else -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH) || \ - ((__PORT__) == EXTI_GPIOI) || \ - ((__PORT__) == EXTI_GPIOJ)) -#endif /* GPIOK */ - -#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Functions EXTI Exported Functions - * @brief EXTI Exported Functions - * @{ - */ - -/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions - * @brief Configuration functions - * @{ - */ -/* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * @{ - */ -/* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_EXTI_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_exti.h + * @author MCD Application Team + * @brief Header file of EXTI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_EXTI_H +#define STM32F7xx_HAL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup EXTI EXTI + * @brief EXTI HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Types EXTI Exported Types + * @{ + */ +typedef enum +{ + HAL_EXTI_COMMON_CB_ID = 0x00U +} EXTI_CallbackIDTypeDef; + +/** + * @brief EXTI Handle structure definition + */ +typedef struct +{ + uint32_t Line; /*!< Exti line number */ + void (* PendingCallback)(void); /*!< Exti pending callback */ +} EXTI_HandleTypeDef; + +/** + * @brief EXTI Configuration structure definition + */ +typedef struct +{ + uint32_t Line; /*!< The Exti line to be configured. This parameter + can be a value of @ref EXTI_Line */ + uint32_t Mode; /*!< The Exit Mode to be configured for a core. + This parameter can be a combination of @ref EXTI_Mode */ + uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter + can be a value of @ref EXTI_Trigger */ + uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. + This parameter is only possible for line 0 to 15. It + can be a value of @ref EXTI_GPIOSel */ +} EXTI_ConfigTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_Line EXTI Line + * @{ + */ +#define EXTI_LINE_0 (EXTI_GPIO | 0x00u) /*!< External interrupt line 0 */ +#define EXTI_LINE_1 (EXTI_GPIO | 0x01u) /*!< External interrupt line 1 */ +#define EXTI_LINE_2 (EXTI_GPIO | 0x02u) /*!< External interrupt line 2 */ +#define EXTI_LINE_3 (EXTI_GPIO | 0x03u) /*!< External interrupt line 3 */ +#define EXTI_LINE_4 (EXTI_GPIO | 0x04u) /*!< External interrupt line 4 */ +#define EXTI_LINE_5 (EXTI_GPIO | 0x05u) /*!< External interrupt line 5 */ +#define EXTI_LINE_6 (EXTI_GPIO | 0x06u) /*!< External interrupt line 6 */ +#define EXTI_LINE_7 (EXTI_GPIO | 0x07u) /*!< External interrupt line 7 */ +#define EXTI_LINE_8 (EXTI_GPIO | 0x08u) /*!< External interrupt line 8 */ +#define EXTI_LINE_9 (EXTI_GPIO | 0x09u) /*!< External interrupt line 9 */ +#define EXTI_LINE_10 (EXTI_GPIO | 0x0Au) /*!< External interrupt line 10 */ +#define EXTI_LINE_11 (EXTI_GPIO | 0x0Bu) /*!< External interrupt line 11 */ +#define EXTI_LINE_12 (EXTI_GPIO | 0x0Cu) /*!< External interrupt line 12 */ +#define EXTI_LINE_13 (EXTI_GPIO | 0x0Du) /*!< External interrupt line 13 */ +#define EXTI_LINE_14 (EXTI_GPIO | 0x0Eu) /*!< External interrupt line 14 */ +#define EXTI_LINE_15 (EXTI_GPIO | 0x0Fu) /*!< External interrupt line 15 */ +#define EXTI_LINE_16 (EXTI_CONFIG | 0x10u) /*!< External interrupt line 16 Connected to the PVD Output */ +#define EXTI_LINE_17 (EXTI_CONFIG | 0x11u) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_LINE_18 (EXTI_CONFIG | 0x12u) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */ +#if defined(ETH) +#define EXTI_LINE_19 (EXTI_CONFIG | 0x13u) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ +#else +#define EXTI_LINE_19 (EXTI_RESERVED | 0x13u) /*!< No interrupt supported in this line */ +#endif /* ETH */ +#define EXTI_LINE_20 (EXTI_CONFIG | 0x14u) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */ +#define EXTI_LINE_21 (EXTI_CONFIG | 0x15u) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define EXTI_LINE_22 (EXTI_CONFIG | 0x16u) /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +#define EXTI_LINE_23 (EXTI_CONFIG | 0x17u) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */ +#if defined(EXTI_IMR_IM24) +#define EXTI_LINE_24 (EXTI_CONFIG | 0x18u) /*!< External interrupt line 24 Connected to the MDIO Slave global Interrupt Wakeup event */ +#endif /* EXTI_IMR_IM24 */ +/** + * @} + */ + +/** @defgroup EXTI_Mode EXTI Mode + * @{ + */ +#define EXTI_MODE_NONE 0x00000000u +#define EXTI_MODE_INTERRUPT 0x00000001u +#define EXTI_MODE_EVENT 0x00000002u +/** + * @} + */ + +/** @defgroup EXTI_Trigger EXTI Trigger + * @{ + */ + +#define EXTI_TRIGGER_NONE 0x00000000u +#define EXTI_TRIGGER_RISING 0x00000001u +#define EXTI_TRIGGER_FALLING 0x00000002u +#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) +/** + * @} + */ + +/** @defgroup EXTI_GPIOSel EXTI GPIOSel + * @brief + * @{ + */ +#define EXTI_GPIOA 0x00000000u +#define EXTI_GPIOB 0x00000001u +#define EXTI_GPIOC 0x00000002u +#define EXTI_GPIOD 0x00000003u +#define EXTI_GPIOE 0x00000004u +#define EXTI_GPIOF 0x00000005u +#define EXTI_GPIOG 0x00000006u +#define EXTI_GPIOH 0x00000007u +#define EXTI_GPIOI 0x00000008u +#define EXTI_GPIOJ 0x00000009u +#if defined (GPIOK) +#define EXTI_GPIOK 0x0000000Au +#endif /* GPIOK */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Private constants --------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ +/** + * @brief EXTI Line property definition + */ +#define EXTI_PROPERTY_SHIFT 24u +#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT) +#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) +#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT) +#define EXTI_PROPERTY_MASK (EXTI_CONFIG | EXTI_GPIO) + +/** + * @brief EXTI bit usage + */ +#define EXTI_PIN_MASK 0x0000001Fu + +/** + * @brief EXTI Mask for interrupt & event mode + */ +#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) + +/** + * @brief EXTI Mask for trigger possibilities + */ +#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) + +/** + * @brief EXTI Line number + */ +#if defined(EXTI_IMR_IM24) +#define EXTI_LINE_NB 25u +#else +#define EXTI_LINE_NB 24u +#endif /* EXTI_IMR_IM24 */ + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup EXTI_Private_Macros EXTI Private Macros + * @{ + */ +#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \ + ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ + (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ + (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB)) + +#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \ + (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u)) + +#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00u) + +#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_FALLING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ + ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)) + +#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u) + +#if defined (GPIOK) +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ) || \ + ((__PORT__) == EXTI_GPIOK)) +#else +#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ + ((__PORT__) == EXTI_GPIOB) || \ + ((__PORT__) == EXTI_GPIOC) || \ + ((__PORT__) == EXTI_GPIOD) || \ + ((__PORT__) == EXTI_GPIOE) || \ + ((__PORT__) == EXTI_GPIOF) || \ + ((__PORT__) == EXTI_GPIOG) || \ + ((__PORT__) == EXTI_GPIOH) || \ + ((__PORT__) == EXTI_GPIOI) || \ + ((__PORT__) == EXTI_GPIOJ)) +#endif /* GPIOK */ + +#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_Exported_Functions EXTI Exported Functions + * @brief EXTI Exported Functions + * @{ + */ + +/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions + * @brief Configuration functions + * @{ + */ +/* Configuration functions ****************************************************/ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); +/** + * @} + */ + +/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +/* IO operation functions *****************************************************/ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_EXTI_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h index 39e859e3..1fad392c 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash.h @@ -1,415 +1,415 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of FLASH HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_FLASH_H -#define __STM32F7xx_HAL_FLASH_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Procedure structure definition - */ -typedef enum -{ - FLASH_PROC_NONE = 0U, - FLASH_PROC_SECTERASE, - FLASH_PROC_MASSERASE, - FLASH_PROC_PROGRAM -} FLASH_ProcedureTypeDef; - - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ - - __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ - - __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ - - __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ - - __IO uint32_t Address; /* Internal variable to save address selected for program */ - - HAL_LockTypeDef Lock; /* FLASH locking object */ - - __IO uint32_t ErrorCode; /* FLASH error code */ - -}FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Error_Code FLASH Error Code - * @brief FLASH Error Code - * @{ - */ -#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ -#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ -#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ -#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ -#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ -#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */ -/** - * @} - */ - -/** @defgroup FLASH_Type_Program FLASH Type Program - * @{ - */ -#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ -#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */ -/** - * @} - */ - -/** @defgroup FLASH_Flag_definition FLASH Flag definition - * @brief Flag definition - * @{ - */ -#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ -#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */ -#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ -#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ -#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ -#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ -#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ - -#if defined (FLASH_OPTCR2_PCROP) -#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */ -#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR) -#else -#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ - FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) -#endif /* FLASH_OPTCR2_PCROP */ -/** - * @} - */ - -/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition - * @brief FLASH Interrupt definition - * @{ - */ -#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */ -/** - * @} - */ - -/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism - * @{ - */ -#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) -#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0) -#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1) -#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE) -#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) -/** - * @} - */ - -/** @defgroup FLASH_Keys FLASH Keys - * @{ - */ -#define FLASH_KEY1 ((uint32_t)0x45670123U) -#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) -#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) -#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) -/** - * @} - */ - -/** @defgroup FLASH_Sectors FLASH Sectors - * @{ - */ -#if (FLASH_SECTOR_TOTAL == 2) -#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ -#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ -#elif (FLASH_SECTOR_TOTAL == 4) -#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ -#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ -#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ -#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ -#else -#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ -#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ -#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ -#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ -#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ -#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ -#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ -#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ -#endif /* FLASH_SECTOR_TOTAL */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @{ - */ -/** - * @brief Set the FLASH Latency. - * @param __LATENCY__ FLASH Latency - * The value of this parameter depend on device used within the same series - * @retval none - */ -#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * The value of this parameter depend on device used within the same series - */ -#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) - -/** - * @brief Enable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) - -/** - * @brief Enable the FLASH Adaptive Real-Time memory accelerator. - * @note The ART accelerator is available only for flash access on ITCM interface. - * @retval none - */ -#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN) - -/** - * @brief Disable the FLASH Adaptive Real-Time memory accelerator. - * @retval none - */ -#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN) - -/** - * @brief Resets the FLASH Adaptive Real-Time memory accelerator. - * @note This function must be used only when the Adaptive Real-Time memory accelerator - * is disabled. - * @retval None - */ -#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST) - -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt - * @retval none - */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_ERR: Error Interrupt - * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) - -/** - * @brief Get the specified FLASH flag status. - * @param __FLAG__ specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag - * @arg FLASH_FLAG_BSY : FLASH Busy flag - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) - -/** - * @brief Clear the specified FLASH flag. - * @param __FLAG__ specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP : FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR : FLASH operation Error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag - * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag - * @retval none - */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) -/** - * @} - */ - -/* Include FLASH HAL Extension module */ -#include "stm32f7xx_hal_flash_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -/* Program operation functions ***********************************************/ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); -/* FLASH IRQ handler method */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -/* Option bytes control */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); -/** - * @} - */ - -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -uint32_t HAL_FLASH_GetError(void); -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ - -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ - -/** - * @brief OPTCR register byte 1 (Bits[15:8]) base address - */ -#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ - -/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters - * @{ - */ -#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ - ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_FLASH_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash.h + * @author MCD Application Team + * @brief Header file of FLASH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_FLASH_H +#define __STM32F7xx_HAL_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASH + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Procedure structure definition + */ +typedef enum +{ + FLASH_PROC_NONE = 0U, + FLASH_PROC_SECTERASE, + FLASH_PROC_MASSERASE, + FLASH_PROC_PROGRAM +} FLASH_ProcedureTypeDef; + + +/** + * @brief FLASH handle Structure definition + */ +typedef struct +{ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ + + __IO uint32_t NbSectorsToErase; /* Internal variable to save the remaining sectors to erase in IT context */ + + __IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */ + + __IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */ + + __IO uint32_t Address; /* Internal variable to save address selected for program */ + + HAL_LockTypeDef Lock; /* FLASH locking object */ + + __IO uint32_t ErrorCode; /* FLASH error code */ + +}FLASH_ProcessTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASH_Error_Code FLASH Error Code + * @brief FLASH Error Code + * @{ + */ +#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ +#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */ +#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */ +#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */ +#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */ +#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */ +#define HAL_FLASH_ERROR_RD ((uint32_t)0x00000040U) /*!< Read Protection Error */ +/** + * @} + */ + +/** @defgroup FLASH_Type_Program FLASH Type Program + * @{ + */ +#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */ +#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */ +/** + * @} + */ + +/** @defgroup FLASH_Flag_definition FLASH Flag definition + * @brief Flag definition + * @{ + */ +#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Operation flag */ +#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH operation Error flag */ +#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */ +#define FLASH_FLAG_PGPERR FLASH_SR_PGPERR /*!< FLASH Programming Parallelism error flag */ +#define FLASH_FLAG_ERSERR FLASH_SR_ERSERR /*!< FLASH Erasing Sequence error flag */ +#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */ + +#if defined (FLASH_OPTCR2_PCROP) +#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH Read protection error flag */ +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR | FLASH_FLAG_RDERR) +#else +#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \ + FLASH_FLAG_PGPERR | FLASH_FLAG_ERSERR) +#endif /* FLASH_OPTCR2_PCROP */ +/** + * @} + */ + +/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition + * @brief FLASH Interrupt definition + * @{ + */ +#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */ +#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */ +/** + * @} + */ + +/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism + * @{ + */ +#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U) +#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0) +#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1) +#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE) +#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU) +/** + * @} + */ + +/** @defgroup FLASH_Keys FLASH Keys + * @{ + */ +#define FLASH_KEY1 ((uint32_t)0x45670123U) +#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU) +#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU) +#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU) +/** + * @} + */ + +/** @defgroup FLASH_Sectors FLASH Sectors + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 2) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#elif (FLASH_SECTOR_TOTAL == 4) +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#else +#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */ +#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */ +#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */ +#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */ +#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */ +#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */ +#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */ +#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */ +#endif /* FLASH_SECTOR_TOTAL */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Set the FLASH Latency. + * @param __LATENCY__ FLASH Latency + * The value of this parameter depend on device used within the same series + * @retval none + */ +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) + +/** + * @brief Get the FLASH Latency. + * @retval FLASH Latency + * The value of this parameter depend on device used within the same series + */ +#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) + +/** + * @brief Enable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) + +/** + * @brief Disable the FLASH prefetch buffer. + * @retval none + */ +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) + +/** + * @brief Enable the FLASH Adaptive Real-Time memory accelerator. + * @note The ART accelerator is available only for flash access on ITCM interface. + * @retval none + */ +#define __HAL_FLASH_ART_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN) + +/** + * @brief Disable the FLASH Adaptive Real-Time memory accelerator. + * @retval none + */ +#define __HAL_FLASH_ART_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN) + +/** + * @brief Resets the FLASH Adaptive Real-Time memory accelerator. + * @note This function must be used only when the Adaptive Real-Time memory accelerator + * is disabled. + * @retval None + */ +#define __HAL_FLASH_ART_RESET() (FLASH->ACR |= FLASH_ACR_ARTRST) + +/** + * @brief Enable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__)) + +/** + * @brief Disable the specified FLASH interrupt. + * @param __INTERRUPT__ FLASH interrupt + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt + * @arg FLASH_IT_ERR: Error Interrupt + * @retval none + */ +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(uint32_t)(__INTERRUPT__)) + +/** + * @brief Get the specified FLASH flag status. + * @param __FLAG__ specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__))) + +/** + * @brief Clear the specified FLASH flag. + * @param __FLAG__ specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_EOP : FLASH End of Operation flag + * @arg FLASH_FLAG_OPERR : FLASH operation Error flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag + * @arg FLASH_FLAG_ERSERR : FLASH Erasing Sequence error flag + * @retval none + */ +#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) +/** + * @} + */ + +/* Include FLASH HAL Extension module */ +#include "stm32f7xx_hal_flash_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASH_Exported_Functions + * @{ + */ +/** @addtogroup FLASH_Exported_Functions_Group1 + * @{ + */ +/* Program operation functions ***********************************************/ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); +/* FLASH IRQ handler method */ +void HAL_FLASH_IRQHandler(void); +/* Callbacks in non blocking modes */ +void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); +void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_FLASH_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_Lock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); +/* Option bytes control */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); +/** + * @} + */ + +/** @addtogroup FLASH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State functions ************************************************/ +uint32_t HAL_FLASH_GetError(void); +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Variables FLASH Private Variables + * @{ + */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Constants FLASH Private Constants + * @{ + */ + +/** + * @brief OPTCR register byte 1 (Bits[15:8]) base address + */ +#define OPTCR_BYTE1_ADDRESS ((uint32_t)0x40023C15) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ +#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \ + ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ + ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASH_Private_Functions FLASH Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_FLASH_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h index 6ec226a5..cdada3d6 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_flash_ex.h @@ -1,697 +1,697 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of FLASH HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_FLASH_EX_H -#define __STM32F7xx_HAL_FLASH_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< Mass erase or sector Erase. - This parameter can be a value of @ref FLASHEx_Type_Erase */ - -#if defined (FLASH_OPTCR_nDBANK) - uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. - This parameter must be a value of @ref FLASHEx_Banks */ -#endif /* FLASH_OPTCR_nDBANK */ - - uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled - This parameter must be a value of @ref FLASHEx_Sectors */ - - uint32_t NbSectors; /*!< Number of sectors to be erased. - This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ - - uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism - This parameter must be a value of @ref FLASHEx_Voltage_Range */ - -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Option Bytes Program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< Option byte to be configured. - This parameter can be a value of @ref FLASHEx_Option_Type */ - - uint32_t WRPState; /*!< Write protection activation or deactivation. - This parameter can be a value of @ref FLASHEx_WRP_State */ - - uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. - The value of this parameter depend on device used within the same series */ - - uint32_t RDPLevel; /*!< Set the read protection level. - This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ - - uint32_t BORLevel; /*!< Set the BOR Level. - This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ - - uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / - IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. - nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ - - uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. - This parameter can be a value of @ref FLASHEx_Boot_Address */ - - uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1. - This parameter can be a value of @ref FLASHEx_Boot_Address */ - -#if defined (FLASH_OPTCR2_PCROP) - uint32_t PCROPSector; /*!< Set the PCROP sector. - This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */ - - uint32_t PCROPRdp; /*!< Set the PCROP_RDP option. - This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ -#endif /* FLASH_OPTCR2_PCROP */ - -} FLASH_OBProgramInitTypeDef; - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASHEx_Type_Erase FLASH Type Erase - * @{ - */ -#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ -#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ -/** - * @} - */ - -/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range - * @{ - */ -#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ -#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ -#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ -#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ -/** - * @} - */ - -/** @defgroup FLASHEx_WRP_State FLASH WRP State - * @{ - */ -#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ -#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Type FLASH Option Type - * @{ - */ -#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ -#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ -#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ -#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ -#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ -#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ -#if defined (FLASH_OPTCR2_PCROP) -#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */ -#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */ -#endif /* FLASH_OPTCR2_PCROP */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection - * @{ - */ -#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) -#define OB_RDP_LEVEL_1 ((uint8_t)0x55U) -#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 - it s no more possible to go back to level 1 or 0 */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog - * @{ - */ -#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ -#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ -/** - * @} - */ - - -/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog - * @{ - */ -#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ -#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP - * @{ - */ -#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ -#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY - * @{ - */ -#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ -#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP - * @{ - */ -#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */ -#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */ -/** - * @} - */ - -/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY - * @{ - */ -#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */ -#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */ -/** - * @} - */ - -/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level - * @{ - */ -#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */ -#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */ -#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */ -#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */ -/** - * @} - */ - -#if defined (FLASH_OPTCR_nDBOOT) -/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT - * @{ - */ -#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ -#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash - (Dual bank Boot mode), or RAM if Boot address option in RAM */ -/** - * @} - */ -#endif /* FLASH_OPTCR_nDBOOT */ - -#if defined (FLASH_OPTCR_nDBANK) -/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank - * @{ - */ -#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */ -#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */ -/** - * @} - */ -#endif /* FLASH_OPTCR_nDBANK */ - -/** @defgroup FLASHEx_Boot_Address FLASH Boot Address - * @{ - */ -#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */ -#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */ -#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */ -#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ -#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ -#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ -#if (SRAM2_BASE == 0x2003C000U) -#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */ -#else -#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ -#endif /* SRAM2_BASE == 0x2003C000U */ -/** - * @} - */ - -/** @defgroup FLASH_Latency FLASH Latency - * @{ - */ -#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ -#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ -#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ -#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ -#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ -#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ -#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ -#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ -#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */ -#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */ -#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ -#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ -#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ -#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ -#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ -#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ -/** - * @} - */ - -#if defined (FLASH_OPTCR_nDBANK) -/** @defgroup FLASHEx_Banks FLASH Banks - * @{ - */ -#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */ -#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */ -#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ -/** - * @} - */ -#endif /* FLASH_OPTCR_nDBANK */ - -/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit - * @{ - */ -#if defined (FLASH_OPTCR_nDBANK) -#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */ -#else -#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */ -#endif /* FLASH_OPTCR_nDBANK */ -/** - * @} - */ - -/** @defgroup FLASHEx_Sectors FLASH Sectors - * @{ - */ -#if (FLASH_SECTOR_TOTAL == 24) -#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ -#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ -#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ -#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ -#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ -#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ -#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ -#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ -#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ -#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ -#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ -#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ -#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ -#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ -#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ -#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ -#endif /* FLASH_SECTOR_TOTAL == 24 */ -/** - * @} - */ - -#if (FLASH_SECTOR_TOTAL == 24) -/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection - * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, - * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. - * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, - * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and - * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). - * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. - * @{ - */ -/* Single Bank Sectors */ -#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */ -#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */ -#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */ -#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */ -#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */ -#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */ -#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */ -#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */ -#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ -#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ -#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ -#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ -#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ - -/* Dual Bank Sectors */ -#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */ -#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */ -#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */ -#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */ -#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */ -#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */ -#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */ -#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */ -#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ -#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ -#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ -#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ -#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ -#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ -#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ -#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */ -#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */ -#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */ -#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */ -#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */ -#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */ -#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */ -#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */ -#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */ -#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */ -/** - * @} - */ -#endif /* FLASH_SECTOR_TOTAL == 24 */ - -#if (FLASH_SECTOR_TOTAL == 8) -/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection - * @{ - */ -#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ -#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ -#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ -#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ -#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */ -#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */ -#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */ -#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */ -#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */ -/** - * @} - */ -#endif /* FLASH_SECTOR_TOTAL == 8 */ - -#if (FLASH_SECTOR_TOTAL == 4) -/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection - * @{ - */ -#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ -#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ -#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ -#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ -#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */ -/** - * @} - */ -#endif /* FLASH_SECTOR_TOTAL == 4 */ - -#if (FLASH_SECTOR_TOTAL == 2) -/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection - * @{ - */ -#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ -#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ -#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */ -/** - * @} - */ -#endif /* FLASH_SECTOR_TOTAL == 2 */ - -#if defined (FLASH_OPTCR2_PCROP) -#if (FLASH_SECTOR_TOTAL == 8) -/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors - * @{ - */ -#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ -#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ -#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ -#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ -#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */ -#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */ -#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */ -#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */ -#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */ -/** - * @} - */ -#endif /* FLASH_SECTOR_TOTAL == 8 */ - -#if (FLASH_SECTOR_TOTAL == 4) -/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors - * @{ - */ -#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ -#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ -#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ -#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ -#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */ -/** - * @} - */ -#endif /* FLASH_SECTOR_TOTAL == 4 */ - -/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit - * @{ - */ -#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */ -#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */ -/** - * @} - */ -#endif /* FLASH_OPTCR2_PCROP */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Macros FLASH Exported Macros - * @{ - */ -/** - * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) - * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. - * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) - * @retval The FLASH Boot Base Address - */ -#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) - /** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASHEx_Exported_Functions - * @{ - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group1 - * @{ - */ -/* Extension Program operation functions *************************************/ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Macros FLASH Private Macros - * @{ - */ - -/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters - * @{ - */ - -#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) - -#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ - ((RANGE) == FLASH_VOLTAGE_RANGE_4)) - -#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ - ((VALUE) == OB_WRPSTATE_ENABLE)) - -#if defined (FLASH_OPTCR2_PCROP) -#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ - OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\ - OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP))) -#else -#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ - OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) -#endif /* FLASH_OPTCR2_PCROP */ - -#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ - ((LEVEL) == OB_RDP_LEVEL_1) ||\ - ((LEVEL) == OB_RDP_LEVEL_2)) - -#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) - -#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) - -#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) - -#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) - -#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) - -#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) - -#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ - ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ - ((LATENCY) == FLASH_LATENCY_1) || \ - ((LATENCY) == FLASH_LATENCY_2) || \ - ((LATENCY) == FLASH_LATENCY_3) || \ - ((LATENCY) == FLASH_LATENCY_4) || \ - ((LATENCY) == FLASH_LATENCY_5) || \ - ((LATENCY) == FLASH_LATENCY_6) || \ - ((LATENCY) == FLASH_LATENCY_7) || \ - ((LATENCY) == FLASH_LATENCY_8) || \ - ((LATENCY) == FLASH_LATENCY_9) || \ - ((LATENCY) == FLASH_LATENCY_10) || \ - ((LATENCY) == FLASH_LATENCY_11) || \ - ((LATENCY) == FLASH_LATENCY_12) || \ - ((LATENCY) == FLASH_LATENCY_13) || \ - ((LATENCY) == FLASH_LATENCY_14) || \ - ((LATENCY) == FLASH_LATENCY_15)) - -#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ - (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) -#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) - -#if (FLASH_SECTOR_TOTAL == 8) -#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ - ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ - ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ - ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) - -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* FLASH_SECTOR_TOTAL == 8 */ - -#if (FLASH_SECTOR_TOTAL == 24) -#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ - ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ - ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ - ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ - ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ - ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ - ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ - ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ - ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ - ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ - ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ - ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) - -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* FLASH_SECTOR_TOTAL == 24 */ - -#if (FLASH_SECTOR_TOTAL == 4) -#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ - ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3)) - -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* FLASH_SECTOR_TOTAL == 4 */ - -#if (FLASH_SECTOR_TOTAL == 2) -#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1)) - -#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) -#endif /* FLASH_SECTOR_TOTAL == 2 */ - -#if defined (FLASH_OPTCR_nDBANK) -#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ - ((VALUE) == OB_NDBANK_DUAL_BANK)) - -#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2) || \ - ((BANK) == FLASH_BANK_BOTH)) -#endif /* FLASH_OPTCR_nDBANK */ - -#if defined (FLASH_OPTCR_nDBOOT) -#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \ - ((VALUE) == OB_DUAL_BOOT_ENABLE)) -#endif /* FLASH_OPTCR_nDBOOT */ - -#if defined (FLASH_OPTCR2_PCROP) -#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U) -#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \ - ((VALUE) == OB_PCROP_RDP_ENABLE)) -#endif /* FLASH_OPTCR2_PCROP */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASH Private Functions - * @{ - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_FLASH_EX_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash_ex.h + * @author MCD Application Team + * @brief Header file of FLASH HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_FLASH_EX_H +#define __STM32F7xx_HAL_FLASH_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup FLASHEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + +/** + * @brief FLASH Erase structure definition + */ +typedef struct +{ + uint32_t TypeErase; /*!< Mass erase or sector Erase. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + +#if defined (FLASH_OPTCR_nDBANK) + uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. + This parameter must be a value of @ref FLASHEx_Banks */ +#endif /* FLASH_OPTCR_nDBANK */ + + uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled + This parameter must be a value of @ref FLASHEx_Sectors */ + + uint32_t NbSectors; /*!< Number of sectors to be erased. + This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ + + uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism + This parameter must be a value of @ref FLASHEx_Voltage_Range */ + +} FLASH_EraseInitTypeDef; + +/** + * @brief FLASH Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ + + uint32_t WRPState; /*!< Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. + The value of this parameter depend on device used within the same series */ + + uint32_t RDPLevel; /*!< Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint32_t BORLevel; /*!< Set the BOR Level. + This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ + + uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY / + IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT. + nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */ + + uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0. + This parameter can be a value of @ref FLASHEx_Boot_Address */ + + uint32_t BootAddr1; /*!< Boot base address when Boot pin = 1. + This parameter can be a value of @ref FLASHEx_Boot_Address */ + +#if defined (FLASH_OPTCR2_PCROP) + uint32_t PCROPSector; /*!< Set the PCROP sector. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_Sectors */ + + uint32_t PCROPRdp; /*!< Set the PCROP_RDP option. + This parameter can be a value of @ref FLASHEx_Option_Bytes_PCROP_RDP */ +#endif /* FLASH_OPTCR2_PCROP */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants + * @{ + */ + +/** @defgroup FLASHEx_Type_Erase FLASH Type Erase + * @{ + */ +#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */ +#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */ +/** + * @} + */ + +/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range + * @{ + */ +#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */ +#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */ +#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */ +#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */ +/** + * @} + */ + +/** @defgroup FLASHEx_WRP_State FLASH WRP State + * @{ + */ +#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */ +#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Type FLASH Option Type + * @{ + */ +#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */ +#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */ +#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */ +#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */ +#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */ +#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */ +#if defined (FLASH_OPTCR2_PCROP) +#define OPTIONBYTE_PCROP ((uint32_t)0x40U) /*!< PCROP configuration */ +#define OPTIONBYTE_PCROP_RDP ((uint32_t)0x80U) /*!< PCROP_RDP configuration */ +#endif /* FLASH_OPTCR2_PCROP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection + * @{ + */ +#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU) +#define OB_RDP_LEVEL_1 ((uint8_t)0x55U) +#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2 + it s no more possible to go back to level 1 or 0 */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog + * @{ + */ +#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */ +#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */ +/** + * @} + */ + + +/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog + * @{ + */ +#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */ +#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP + * @{ + */ +#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY + * @{ + */ +#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP + * @{ + */ +#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY + * @{ + */ +#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */ +/** + * @} + */ + +/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level + * @{ + */ +#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */ +#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */ +#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */ +#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */ +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBOOT) +/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT + * @{ + */ +#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */ +#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash + (Dual bank Boot mode), or RAM if Boot address option in RAM */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBOOT */ + +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank + * @{ + */ +#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */ +#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ + +/** @defgroup FLASHEx_Boot_Address FLASH Boot Address + * @{ + */ +#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */ +#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */ +#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */ +#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */ +#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */ +#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */ +#if (SRAM2_BASE == 0x2003C000U) +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x800FU) /*!< Boot from SRAM2 (0x2003C000) */ +#else +#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */ +#endif /* SRAM2_BASE == 0x2003C000U */ +/** + * @} + */ + +/** @defgroup FLASH_Latency FLASH Latency + * @{ + */ +#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ +#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ +#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ +#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ +#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ +#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ +#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ +#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycles */ +#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycles */ +#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ +#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ +#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ +#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ +#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ +#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBANK) +/** @defgroup FLASHEx_Banks FLASH Banks + * @{ + */ +#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */ +#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */ +#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */ +/** + * @} + */ +#endif /* FLASH_OPTCR_nDBANK */ + +/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit + * @{ + */ +#if defined (FLASH_OPTCR_nDBANK) +#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */ +#else +#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */ +#endif /* FLASH_OPTCR_nDBANK */ +/** + * @} + */ + +/** @defgroup FLASHEx_Sectors FLASH Sectors + * @{ + */ +#if (FLASH_SECTOR_TOTAL == 24) +#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */ +#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */ +#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */ +#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */ +#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */ +#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */ +#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */ +#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */ +#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */ +#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */ +#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */ +#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */ +#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */ +#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */ +#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */ +#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ +/** + * @} + */ + +#if (FLASH_SECTOR_TOTAL == 24) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11. + * For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register, + * nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and + * a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1). + * This behavior is applicable only for STM32F76xxx / STM32F77xxx devices. + * @{ + */ +/* Single Bank Sectors */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */ +#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */ +#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */ +#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */ +#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */ + +/* Dual Bank Sectors */ +#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */ +#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */ +#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */ +#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */ +#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */ +#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */ +#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */ +#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */ +#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */ +#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */ +#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */ +#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */ +#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */ +#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */ +#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */ +#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */ +#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */ +#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */ +#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */ +#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */ +#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */ +#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */ +#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */ +#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */ +#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if (FLASH_SECTOR_TOTAL == 8) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */ +#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */ +#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */ +#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */ +#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x000F0000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection + * @{ + */ +#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */ +#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */ +#define OB_WRP_SECTOR_All ((uint32_t)0x00030000U) /*!< Write protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 2 */ + +#if defined (FLASH_OPTCR2_PCROP) +#if (FLASH_SECTOR_TOTAL == 8) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_4 ((uint32_t)0x00000010U) /*!< PC Readout protection of Sector4 */ +#define OB_PCROP_SECTOR_5 ((uint32_t)0x00000020U) /*!< PC Readout protection of Sector5 */ +#define OB_PCROP_SECTOR_6 ((uint32_t)0x00000040U) /*!< PC Readout protection of Sector6 */ +#define OB_PCROP_SECTOR_7 ((uint32_t)0x00000080U) /*!< PC Readout protection of Sector7 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x000000FFU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 4) +/** @defgroup FLASHEx_Option_Bytes_PCROP_Sectors FLASH Option Bytes PCROP Sectors + * @{ + */ +#define OB_PCROP_SECTOR_0 ((uint32_t)0x00000001U) /*!< PC Readout protection of Sector0 */ +#define OB_PCROP_SECTOR_1 ((uint32_t)0x00000002U) /*!< PC Readout protection of Sector1 */ +#define OB_PCROP_SECTOR_2 ((uint32_t)0x00000004U) /*!< PC Readout protection of Sector2 */ +#define OB_PCROP_SECTOR_3 ((uint32_t)0x00000008U) /*!< PC Readout protection of Sector3 */ +#define OB_PCROP_SECTOR_All ((uint32_t)0x0000000FU) /*!< PC Readout protection of all Sectors */ +/** + * @} + */ +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +/** @defgroup FLASHEx_Option_Bytes_PCROP_RDP FLASH Option Bytes PCROP_RDP Bit + * @{ + */ +#define OB_PCROP_RDP_ENABLE ((uint32_t)0x80000000U) /*!< PCROP_RDP Enable */ +#define OB_PCROP_RDP_DISABLE ((uint32_t)0x00000000U) /*!< PCROP_RDP Disable */ +/** + * @} + */ +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ +/** + * @brief Calculate the FLASH Boot Base Address (BOOT_ADD0 or BOOT_ADD1) + * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. + * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @retval The FLASH Boot Base Address + */ +#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14) + /** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ + +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @{ + */ +/* Extension Program operation functions *************************************/ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Macros FLASH Private Macros + * @{ + */ + +/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters + * @{ + */ + +#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \ + ((VALUE) == FLASH_TYPEERASE_MASSERASE)) + +#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ + ((RANGE) == FLASH_VOLTAGE_RANGE_4)) + +#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \ + ((VALUE) == OB_WRPSTATE_ENABLE)) + +#if defined (FLASH_OPTCR2_PCROP) +#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1 |\ + OPTIONBYTE_PCROP | OPTIONBYTE_PCROP_RDP))) +#else +#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1))) +#endif /* FLASH_OPTCR2_PCROP */ + +#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013) + +#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ + ((LEVEL) == OB_RDP_LEVEL_1) ||\ + ((LEVEL) == OB_RDP_LEVEL_2)) + +#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) + +#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) + +#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) + +#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) + +#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) + +#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) + +#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\ + ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF)) + +#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ + ((LATENCY) == FLASH_LATENCY_1) || \ + ((LATENCY) == FLASH_LATENCY_2) || \ + ((LATENCY) == FLASH_LATENCY_3) || \ + ((LATENCY) == FLASH_LATENCY_4) || \ + ((LATENCY) == FLASH_LATENCY_5) || \ + ((LATENCY) == FLASH_LATENCY_6) || \ + ((LATENCY) == FLASH_LATENCY_7) || \ + ((LATENCY) == FLASH_LATENCY_8) || \ + ((LATENCY) == FLASH_LATENCY_9) || \ + ((LATENCY) == FLASH_LATENCY_10) || \ + ((LATENCY) == FLASH_LATENCY_11) || \ + ((LATENCY) == FLASH_LATENCY_12) || \ + ((LATENCY) == FLASH_LATENCY_13) || \ + ((LATENCY) == FLASH_LATENCY_14) || \ + ((LATENCY) == FLASH_LATENCY_15)) + +#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \ + (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END))) +#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL)) + +#if (FLASH_SECTOR_TOTAL == 8) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ + ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ + ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFF00FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 8 */ + +#if (FLASH_SECTOR_TOTAL == 24) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\ + ((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\ + ((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\ + ((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\ + ((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\ + ((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\ + ((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\ + ((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\ + ((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\ + ((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\ + ((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 24 */ + +#if (FLASH_SECTOR_TOTAL == 4) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\ + ((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFF0FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 4 */ + +#if (FLASH_SECTOR_TOTAL == 2) +#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1)) + +#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFCFFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U)) +#endif /* FLASH_SECTOR_TOTAL == 2 */ + +#if defined (FLASH_OPTCR_nDBANK) +#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \ + ((VALUE) == OB_NDBANK_DUAL_BANK)) + +#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ + ((BANK) == FLASH_BANK_2) || \ + ((BANK) == FLASH_BANK_BOTH)) +#endif /* FLASH_OPTCR_nDBANK */ + +#if defined (FLASH_OPTCR_nDBOOT) +#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \ + ((VALUE) == OB_DUAL_BOOT_ENABLE)) +#endif /* FLASH_OPTCR_nDBOOT */ + +#if defined (FLASH_OPTCR2_PCROP) +#define IS_OB_PCROP_SECTOR(SECTOR) (((SECTOR) & (uint32_t)0xFFFFFF00U) == 0x00000000U) +#define IS_OB_PCROP_RDP_VALUE(VALUE) (((VALUE) == OB_PCROP_RDP_DISABLE) || \ + ((VALUE) == OB_PCROP_RDP_ENABLE)) +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FLASHEx_Private_Functions FLASH Private Functions + * @{ + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_FLASH_EX_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h index 9fc8540f..bf18ffa8 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio.h @@ -1,323 +1,323 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_GPIO_H -#define __STM32F7xx_HAL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ - -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode_define */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull_define */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed_define */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_Alternate_function_selection */ -} GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0, - GPIO_PIN_SET -} GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_pins_define GPIO pins define - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ -#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ -#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ -#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ -#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ -#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ -#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ -#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ -#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ -#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ -#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ -#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ -#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ -#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ -#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ -#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ -#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ -/** - * @} - */ - -/** @defgroup GPIO_mode_define GPIO mode define - * @brief GPIO Configuration Mode - * Elements values convention: 0x00WX00YZ - * - W : EXTI trigger detection on 3 bits - * - X : EXTI mode (IT or Event) on 2 bits - * - Y : Output type (Push Pull or Open Drain) on 1 bit - * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits - * @{ - */ -#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ - -#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup GPIO_speed_define GPIO speed define - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */ -#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */ -#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */ -#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */ -/** - * @} - */ - -/** @defgroup GPIO_pull_define GPIO pull define - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ -#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__ specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) - -/** - * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__ specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) - -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__ specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) -/** - * @} - */ - -/* Include GPIO HAL Extension module */ -#include "stm32f7xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ -#define GPIO_MODE_Pos 0U -#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) -#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) -#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) -#define MODE_AF (0x2UL << GPIO_MODE_Pos) -#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) -#define OUTPUT_TYPE_Pos 4U -#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) -#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) -#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) -#define EXTI_MODE_Pos 16U -#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) -#define EXTI_IT (0x1UL << EXTI_MODE_Pos) -#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) -#define TRIGGER_MODE_Pos 20U -#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) -#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) -#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) -#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U)) -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ - ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ - ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ - ((MODE) == GPIO_MODE_AF_PP) ||\ - ((MODE) == GPIO_MODE_AF_OD) ||\ - ((MODE) == GPIO_MODE_IT_RISING) ||\ - ((MODE) == GPIO_MODE_IT_FALLING) ||\ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING) ||\ - ((MODE) == GPIO_MODE_EVT_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_ANALOG)) -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ - ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH)) -#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ - ((PULL) == GPIO_PULLDOWN)) -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Functions GPIO Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_GPIO_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_GPIO_H +#define __STM32F7xx_HAL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_mode_define */ + + uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. + This parameter can be a value of @ref GPIO_pull_define */ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_speed_define */ + + uint32_t Alternate; /*!< Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_Alternate_function_selection */ +} GPIO_InitTypeDef; + +/** + * @brief GPIO Bit SET and Bit RESET enumeration + */ +typedef enum +{ + GPIO_PIN_RESET = 0, + GPIO_PIN_SET +} GPIO_PinState; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pins define + * @{ + */ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */ + +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */ +/** + * @} + */ + +/** @defgroup GPIO_mode_define GPIO mode define + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits + * @{ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup GPIO_speed_define GPIO speed define + * @brief GPIO Output Maximum frequency + * @{ + */ +#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */ +#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */ +#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */ +#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */ +/** + * @} + */ + +/** @defgroup GPIO_pull_define GPIO pull define + * @brief GPIO Pull-Up or Pull-Down Activation + * @{ + */ +#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */ +#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */ +#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending flags. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval The new state of __EXTI_LINE__ (SET or RESET). + */ +#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clears the EXTI's line pending bits. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__ specifies the EXTI line to check. + * This parameter can be GPIO_PIN_x where x can be(0..15) + * @retval None + */ +#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ + +/* Include GPIO HAL Extension module */ +#include "stm32f7xx_hal_gpio_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ + +/** @addtogroup GPIO_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); +void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIO_Private_Macros GPIO Private Macros + * @{ + */ +#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U)) +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ + ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ + ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ + ((MODE) == GPIO_MODE_AF_PP) ||\ + ((MODE) == GPIO_MODE_AF_OD) ||\ + ((MODE) == GPIO_MODE_IT_RISING) ||\ + ((MODE) == GPIO_MODE_IT_FALLING) ||\ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING) ||\ + ((MODE) == GPIO_MODE_EVT_FALLING) ||\ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((MODE) == GPIO_MODE_ANALOG)) +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ + ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH)) +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ + ((PULL) == GPIO_PULLDOWN)) +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIO_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_GPIO_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h index 0e2cb483..4a9989c7 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_gpio_ex.h @@ -1,656 +1,656 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_gpio_ex.h - * @author MCD Application Team - * @brief Header file of GPIO HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_GPIO_EX_H -#define __STM32F7xx_HAL_GPIO_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection - * @{ - */ -/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/ -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */ -#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ -#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ -#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ -#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ -#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */ -#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */ -#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */ -#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) -#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) -#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ -#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */ -#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ -#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */ -#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */ -#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ -#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ -#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ -#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) -#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/*----------------------------------------------------------------------------*/ - -/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ -#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ -#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ -#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ -#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ -#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ -#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ -#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ -#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ -#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ -#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ -#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ -#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ -#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ -#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ -#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ -#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ -#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ -#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ -#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ -#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ -#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ - -/** - * @brief AF 11 selection - */ -#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ -#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ -/*----------------------------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros - * @{ - */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions - * @{ - */ -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Constants GPIO Private Constants - * @{ - */ - -/** - * @brief GPIO pin available on the platform - */ -/* Defines the available pins per GPIOs */ -#define GPIOA_PIN_AVAILABLE GPIO_PIN_All -#define GPIOB_PIN_AVAILABLE GPIO_PIN_All -#define GPIOC_PIN_AVAILABLE GPIO_PIN_All -#define GPIOD_PIN_AVAILABLE GPIO_PIN_All -#define GPIOE_PIN_AVAILABLE GPIO_PIN_All -#define GPIOF_PIN_AVAILABLE GPIO_PIN_All -#define GPIOG_PIN_AVAILABLE GPIO_PIN_All -#define GPIOI_PIN_AVAILABLE GPIO_PIN_All -#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All -#define GPIOH_PIN_AVAILABLE GPIO_PIN_All -#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ - GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Macros GPIO Private Macros - * @{ - */ -/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index - * @{ - */ -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U :\ - ((__GPIOx__) == (GPIOI))? 8U :\ - ((__GPIOx__) == (GPIOJ))? 9U : 10U) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ - ((__GPIOx__) == (GPIOB))? 1U :\ - ((__GPIOx__) == (GPIOC))? 2U :\ - ((__GPIOx__) == (GPIOD))? 3U :\ - ((__GPIOx__) == (GPIOE))? 4U :\ - ((__GPIOx__) == (GPIOF))? 5U :\ - ((__GPIOx__) == (GPIOG))? 6U :\ - ((__GPIOx__) == (GPIOH))? 7U : 8U) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ -/** - * @} - */ - -#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ - ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \ - (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) -/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function - * @{ - */ -#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ - ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC)) -#elif defined(STM32F745xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT)) -#elif defined(STM32F767xx) || defined(STM32F777xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ - ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF14_LTDC)) -#elif defined(STM32F769xx) || defined(STM32F779xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ - ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI)) -#elif defined(STM32F765xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ - ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ - ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ - ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ - ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ - ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ - ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ - ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ - ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ - ((AF) == GPIO_AF10_OTG_FS)) -#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ - ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ - ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ - ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ - ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ - ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ - ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ - ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ - ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \ - ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \ - ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ - ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ - ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ - ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ - ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ - ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ - ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ - ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \ - ((AF) == GPIO_AF9_TIM13) || ((AF) == GPIO_AF9_TIM14) || \ - ((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \ - ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \ - ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ - ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ - ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ - ((AF) == GPIO_AF10_OTG_FS)) -#endif /* STM32F756xx || STM32F746xx || STM32F750xx */ -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup GPIOEx_Private_Functions GPIO Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_GPIO_EX_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio_ex.h + * @author MCD Application Team + * @brief Header file of GPIO HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_GPIO_EX_H +#define __STM32F7xx_HAL_GPIO_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIOEx GPIOEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection + * @{ + */ +/*--------------- STM32F74xxx/STM32F75xxx/STM32F76xxx/STM32F77xxx -------------*/ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) ||\ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */ +#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ +#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */ +#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ +#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */ +#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */ +#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) +#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF10_LTDC ((uint8_t)0x0AU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ +#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ +#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) || defined(STM32F750xx) +#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */ + +/** + * @brief AF 14 selection + */ +#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/*----------------------------------------------------------------------------*/ + +/*---------------------------- STM32F72xxx/STM32F73xxx -----------------------*/ +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F732xx) || defined(STM32F733xx) || defined(STM32F730xx) +/** + * @brief AF 0 selection + */ +#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */ +#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */ +#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */ +#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */ +#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */ +#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */ +#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */ +#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */ +#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */ + +/** + * @brief AF 4 selection + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */ +#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */ + +/** + * @brief AF 5 selection + */ +#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */ +#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */ + +/** + * @brief AF 6 selection + */ +#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */ +#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */ + +/** + * @brief AF 7 selection + */ +#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */ +#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */ +#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */ +#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */ +#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */ +#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */ + +/** + * @brief AF 8 selection + */ +#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */ +#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */ +#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */ +#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */ +#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */ +#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */ + +/** + * @brief AF 9 selection + */ +#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */ +#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */ +#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */ +#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */ +#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */ + +/** + * @brief AF 10 selection + */ +#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */ +#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */ +#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */ +#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */ +#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */ + +/** + * @brief AF 11 selection + */ +#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */ + +/** + * @brief AF 12 selection + */ +#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */ +#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */ + +/** + * @brief AF 13 selection + */ +#define GPIO_AF13_RNG ((uint8_t)0x0DU) /* RNG Alternate Function mapping */ + +/** + * @brief AF 15 selection + */ +#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +/*----------------------------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros + * @{ + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions + * @{ + */ +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Constants GPIO Private Constants + * @{ + */ + +/** + * @brief GPIO pin available on the platform + */ +/* Defines the available pins per GPIOs */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE GPIO_PIN_All +#define GPIOD_PIN_AVAILABLE GPIO_PIN_All +#define GPIOE_PIN_AVAILABLE GPIO_PIN_All +#define GPIOF_PIN_AVAILABLE GPIO_PIN_All +#define GPIOG_PIN_AVAILABLE GPIO_PIN_All +#define GPIOI_PIN_AVAILABLE GPIO_PIN_All +#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All +#define GPIOH_PIN_AVAILABLE GPIO_PIN_All +#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \ + GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Macros GPIO Private Macros + * @{ + */ +/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index + * @{ + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U :\ + ((__GPIOx__) == (GPIOI))? 8U :\ + ((__GPIOx__) == (GPIOJ))? 9U : 10U) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOF))? 5U :\ + ((__GPIOx__) == (GPIOG))? 6U :\ + ((__GPIOx__) == (GPIOH))? 7U : 8U) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ +/** + * @} + */ + +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) +/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function + * @{ + */ +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ + ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F745xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT)) +#elif defined(STM32F767xx) || defined(STM32F777xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F769xx) || defined(STM32F779xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM13) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI)) +#elif defined(STM32F765xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \ + ((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \ + ((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \ + ((AF) == GPIO_AF10_OTG_FS)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF5_SPI1) || \ + ((AF) == GPIO_AF5_SPI2) || ((AF) == GPIO_AF5_SPI3) || \ + ((AF) == GPIO_AF5_SPI4) || ((AF) == GPIO_AF5_SPI5) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM13) || ((AF) == GPIO_AF9_TIM14) || \ + ((AF) == GPIO_AF9_QUADSPI) || ((AF) == GPIO_AF10_OTG_HS) || \ + ((AF) == GPIO_AF10_SAI2) || ((AF) == GPIO_AF10_QUADSPI) || \ + ((AF) == GPIO_AF10_SDMMC2) || ((AF) == GPIO_AF11_SDMMC2) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ + ((AF) == GPIO_AF10_OTG_FS)) +#endif /* STM32F756xx || STM32F746xx || STM32F750xx */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup GPIOEx_Private_Functions GPIO Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_GPIO_EX_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h deleted file mode 100644 index e659e28a..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash.h +++ /dev/null @@ -1,630 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hash.h - * @author MCD Application Team - * @brief Header file of HASH HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_HASH_H -#define STM32F7xx_HAL_HASH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (HASH) -/** @addtogroup HASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup HASH_Exported_Types HASH Exported Types - * @{ - */ - -/** - * @brief HASH Configuration Structure definition - */ -typedef struct -{ - uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data. - This parameter can be a value of @ref HASH_Data_Type. */ - - uint32_t KeySize; /*!< The key size is used only in HMAC operation. */ - - uint8_t *pKey; /*!< The key is used only in HMAC operation. */ - -} HASH_InitTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_HASH_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ - HAL_HASH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_HASH_STATE_BUSY = 0x02U, /*!< Processing (hashing) is ongoing */ - HAL_HASH_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ - HAL_HASH_STATE_ERROR = 0x07U, /*!< Error state */ - HAL_HASH_STATE_SUSPENDED = 0x08U /*!< Suspended state */ -} HAL_HASH_StateTypeDef; - -/** - * @brief HAL phase structures definition - */ -typedef enum -{ - HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready to start */ - HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in HASH processing phase */ - HAL_HASH_PHASE_HMAC_STEP_1 = 0x03U, /*!< HASH peripheral is in HMAC step 1 processing phase - (step 1 consists in entering the inner hash function key) */ - HAL_HASH_PHASE_HMAC_STEP_2 = 0x04U, /*!< HASH peripheral is in HMAC step 2 processing phase - (step 2 consists in entering the message text) */ - HAL_HASH_PHASE_HMAC_STEP_3 = 0x05U /*!< HASH peripheral is in HMAC step 3 processing phase - (step 3 consists in entering the outer hash function key) */ -} HAL_HASH_PhaseTypeDef; - -/** - * @brief HAL HASH mode suspend definitions - */ -typedef enum -{ - HAL_HASH_SUSPEND_NONE = 0x00U, /*!< HASH peripheral suspension not requested */ - HAL_HASH_SUSPEND = 0x01U /*!< HASH peripheral suspension is requested */ -} HAL_HASH_SuspendTypeDef; - -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) -/** - * @brief HAL HASH common Callback ID enumeration definition - */ -typedef enum -{ - HAL_HASH_MSPINIT_CB_ID = 0x00U, /*!< HASH MspInit callback ID */ - HAL_HASH_MSPDEINIT_CB_ID = 0x01U, /*!< HASH MspDeInit callback ID */ - HAL_HASH_INPUTCPLT_CB_ID = 0x02U, /*!< HASH input completion callback ID */ - HAL_HASH_DGSTCPLT_CB_ID = 0x03U, /*!< HASH digest computation completion callback ID */ - HAL_HASH_ERROR_CB_ID = 0x04U, /*!< HASH error callback ID */ -} HAL_HASH_CallbackIDTypeDef; -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - -/** - * @brief HASH Handle Structure definition - */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) -typedef struct __HASH_HandleTypeDef -#else -typedef struct -#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ -{ - HASH_InitTypeDef Init; /*!< HASH required parameters */ - - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ - - uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ - - uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ - - uint32_t HashBuffSize; /*!< Size of buffer to be processed */ - - __IO uint32_t HashInCount; /*!< Counter of inputted data */ - - __IO uint32_t HashITCounter; /*!< Counter of issued interrupts */ - - __IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */ - - HAL_StatusTypeDef Status; /*!< HASH peripheral status */ - - HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */ - - DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */ - - HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */ - - FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */ - - __IO uint32_t NbWordsAlreadyPushed; /*!< Numbers of words already pushed in FIFO before inputting new block */ - - __IO uint32_t ErrorCode; /*!< HASH Error code */ - - __IO uint32_t Accumulation; /*!< HASH multi buffers accumulation flag */ - -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - void (* InCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH input completion callback */ - - void (* DgstCpltCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH digest computation completion callback */ - - void (* ErrorCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH error callback */ - - void (* MspInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp Init callback */ - - void (* MspDeInitCallback)(struct __HASH_HandleTypeDef *hhash); /*!< HASH Msp DeInit callback */ - -#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ -} HASH_HandleTypeDef; - -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) -/** - * @brief HAL HASH Callback pointer definition - */ -typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer to a HASH common callback functions */ -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HASH_Exported_Constants HASH Exported Constants - * @{ - */ - -/** @defgroup HASH_Algo_Selection HASH algorithm selection - * @{ - */ -#define HASH_ALGOSELECTION_SHA1 0x00000000U /*!< HASH function is SHA1 */ -#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */ -#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */ -#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */ -/** - * @} - */ - -/** @defgroup HASH_Algorithm_Mode HASH algorithm mode - * @{ - */ -#define HASH_ALGOMODE_HASH 0x00000000U /*!< Algorithm is HASH */ -#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */ -/** - * @} - */ - -/** @defgroup HASH_Data_Type HASH input data type - * @{ - */ -#define HASH_DATATYPE_32B 0x00000000U /*!< 32-bit data. No swapping */ -#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */ -#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */ -#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */ -/** - * @} - */ - -/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type - * @{ - */ -#define HASH_HMAC_KEYTYPE_SHORTKEY 0x00000000U /*!< HMAC Key size is <= 64 bytes */ -#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */ -/** - * @} - */ - -/** @defgroup HASH_flags_definition HASH flags definitions - * @{ - */ -#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */ -#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */ -#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */ -#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */ -#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */ - -/** - * @} - */ - -/** @defgroup HASH_interrupts_definition HASH interrupts definitions - * @{ - */ -#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ -#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ - -/** - * @} - */ - -/** @defgroup HASH_Error_Definition HASH Error Definition - * @{ - */ -#define HAL_HASH_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_HASH_ERROR_IT 0x00000001U /*!< IT-based process error */ -#define HAL_HASH_ERROR_DMA 0x00000002U /*!< DMA-based process error */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U) -#define HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid Callback error */ -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup HASH_Exported_Macros HASH Exported Macros - * @{ - */ - -/** @brief Check whether or not the specified HASH flag is set. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. - * @arg @ref HASH_FLAG_DCIS Digest calculation complete. - * @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing. - * @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data. - * @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \ - ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\ - ((HASH->SR & (__FLAG__)) == (__FLAG__)) ) - - -/** @brief Clear the specified HASH flag. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer. - * @arg @ref HASH_FLAG_DCIS Digest calculation complete - * @retval None - */ -#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__)) - - -/** @brief Enable the specified HASH interrupt. - * @param __INTERRUPT__ specifies the HASH interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) - * @arg @ref HASH_IT_DCI Digest calculation complete - * @retval None - */ -#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__)) - -/** @brief Disable the specified HASH interrupt. - * @param __INTERRUPT__ specifies the HASH interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN) - * @arg @ref HASH_IT_DCI Digest calculation complete - * @retval None - */ -#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__)) - -/** @brief Reset HASH handle state. - * @param __HANDLE__ HASH handle. - * @retval None - */ - -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) -#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_HASH_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - }while(0) -#else -#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET) -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - -/** @brief Reset HASH handle status. - * @param __HANDLE__ HASH handle. - * @retval None - */ -#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK) - -/** - * @brief Enable the multi-buffer DMA transfer mode. - * @note This bit is set when hashing large files when multiple DMA transfers are needed. - * @retval None - */ -#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT) - -/** - * @brief Disable the multi-buffer DMA transfer mode. - * @retval None - */ -#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT) - - -/** - * @brief Start the digest computation. - * @retval None - */ -#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL) - -/** - * @brief Set the number of valid bits in the last word written in data register DIN. - * @param __SIZE__ size in bytes of last data written in Data register. - * @retval None - */ -#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U)) - -/** - * @brief Reset the HASH core. - * @retval None - */ -#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT) - -/** - * @} - */ - - -/* Private macros --------------------------------------------------------*/ -/** @defgroup HASH_Private_Macros HASH Private Macros - * @{ - */ -/** - * @brief Return digest length in bytes. - * @retval Digest length - */ -#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20U : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28U : \ - ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32U : 16U ) ) ) -/** - * @brief Return number of words already pushed in the FIFO. - * @retval Number of words already pushed in the FIFO - */ -#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U) - -/** - * @brief Ensure that HASH input data type is valid. - * @param __DATATYPE__ HASH input data type. - * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid) - */ -#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \ - ((__DATATYPE__) == HASH_DATATYPE_16B)|| \ - ((__DATATYPE__) == HASH_DATATYPE_8B) || \ - ((__DATATYPE__) == HASH_DATATYPE_1B)) - -/** - * @brief Ensure that input data buffer size is valid for multi-buffer HASH - * processing in DMA mode. - * @note This check is valid only for multi-buffer HASH processing in DMA mode. - * @param __SIZE__ input data buffer size. - * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) - */ -#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U)) - -/** - * @brief Ensure that input data buffer size is valid for multi-buffer HMAC - * processing in DMA mode. - * @note This check is valid only for multi-buffer HMAC processing in DMA mode. - * @param __HANDLE__ HASH handle. - * @param __SIZE__ input data buffer size. - * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid) - */ -#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET)\ - || (((__SIZE__) % 4U) == 0U)) -/** - * @brief Ensure that handle phase is set to HASH processing. - * @param __HANDLE__ HASH handle. - * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing) - */ -#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS) - -/** - * @brief Ensure that handle phase is set to HMAC processing. - * @param __HANDLE__ HASH handle. - * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing) - */ -#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \ - ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \ - ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) - -/** - * @} - */ - -/* Include HASH HAL Extended module */ -#include "stm32f7xx_hal_hash_ex.h" -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup HASH_Exported_Functions HASH Exported Functions - * @{ - */ - -/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization/de-initialization methods **********************************/ -HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash); -void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash); -void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash); -void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash); -void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash); -void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, - pHASH_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - -/** - * @} - */ - -/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode - * @{ - */ - - -/* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout); - - -/** - * @} - */ - -/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode - * @{ - */ - -/* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); -/** - * @} - */ - -/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode - * @{ - */ - -/* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); - -/** - * @} - */ - -/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode - * @{ - */ - -/* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout); - -/** - * @} - */ - -/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode - * @{ - */ - -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); - -/** - * @} - */ - -/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode - * @{ - */ - -/* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -/** - * @} - */ - -/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions - * @{ - */ - - -/* Peripheral State methods **************************************************/ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); -void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -----------------------------------------------------------*/ - -/** @addtogroup HASH_Private_Functions HASH Private Functions - * @{ - */ - -/* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); - -/** - * @} - */ - -/** - * @} - */ -#endif /* HASH*/ -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_HASH_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h deleted file mode 100644 index 67f04b9e..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hash_ex.h +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hash_ex.h - * @author MCD Application Team - * @brief Header file of HASH HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_HASH_EX_H -#define STM32F7xx_HAL_HASH_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (HASH) -/** @addtogroup HASHEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ - - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions - * @{ - */ - -/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode - * @{ - */ - -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout); - -/** - * @} - */ - -/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode - * @{ - */ - -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); - -/** - * @} - */ - -/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode - * @{ - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); - -/** - * @} - */ - -/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode - * @{ - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout); -/** - * @} - */ - -/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode - * @{ - */ - -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer); - -/** - * @} - */ - -/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode - * @{ - */ - -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -/** - * @} - */ - -/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode - * @{ - */ - -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* HASH*/ -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_HASH_EX_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h deleted file mode 100644 index 2cb69b10..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_hcd.h +++ /dev/null @@ -1,328 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hcd.h - * @author MCD Application Team - * @brief Header file of HCD HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_HCD_H -#define STM32F7xx_HAL_HCD_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_usb.h" - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup HCD HCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup HCD_Exported_Types HCD Exported Types - * @{ - */ - -/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition - * @{ - */ -typedef enum -{ - HAL_HCD_STATE_RESET = 0x00, - HAL_HCD_STATE_READY = 0x01, - HAL_HCD_STATE_ERROR = 0x02, - HAL_HCD_STATE_BUSY = 0x03, - HAL_HCD_STATE_TIMEOUT = 0x04 -} HCD_StateTypeDef; - -typedef USB_OTG_GlobalTypeDef HCD_TypeDef; -typedef USB_OTG_CfgTypeDef HCD_InitTypeDef; -typedef USB_OTG_HCTypeDef HCD_HCTypeDef; -typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef; -typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef; -/** - * @} - */ - -/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition - * @{ - */ -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) -typedef struct __HCD_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ -{ - HCD_TypeDef *Instance; /*!< Register base address */ - HCD_InitTypeDef Init; /*!< HCD required parameters */ - HCD_HCTypeDef hc[16]; /*!< Host channels parameters */ - HAL_LockTypeDef Lock; /*!< HCD peripheral status */ - __IO HCD_StateTypeDef State; /*!< HCD communication state */ - __IO uint32_t ErrorCode; /*!< HCD Error code */ - void *pData; /*!< Pointer Stack Handler */ -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD SOF callback */ - void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Connect callback */ - void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Disconnect callback */ - void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Enable callback */ - void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Port Disable callback */ - void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum, - HCD_URBStateTypeDef urb_state); /*!< USB OTG HCD Host Channel Notify URB Change callback */ - - void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp Init callback */ - void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd); /*!< USB OTG HCD Msp DeInit callback */ -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ -} HCD_HandleTypeDef; -/** - * @} - */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HCD_Exported_Constants HCD Exported Constants - * @{ - */ - -/** @defgroup HCD_Speed HCD Speed - * @{ - */ -#define HCD_SPEED_HIGH USBH_HS_SPEED -#define HCD_SPEED_FULL USBH_FSLS_SPEED -#define HCD_SPEED_LOW USBH_FSLS_SPEED -/** - * @} - */ - -/** @defgroup HCD_Device_Speed HCD Device Speed - * @{ - */ -#define HCD_DEVICE_SPEED_HIGH 0U -#define HCD_DEVICE_SPEED_FULL 1U -#define HCD_DEVICE_SPEED_LOW 2U -/** - * @} - */ - -/** @defgroup HCD_PHY_Module HCD PHY Module - * @{ - */ -#define HCD_PHY_ULPI 1U -#define HCD_PHY_EMBEDDED 2U -/** - * @} - */ - -/** @defgroup HCD_Error_Code_definition HCD Error Code definition - * @brief HCD Error Code definition - * @{ - */ -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) -#define HAL_HCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup HCD_Exported_Macros HCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -#define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) - -#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ - & (__INTERRUPT__)) == (__INTERRUPT__)) - -#define __HAL_HCD_GET_CH_FLAG(__HANDLE__, __chnum__, __INTERRUPT__) \ - ((USB_ReadChInterrupts((__HANDLE__)->Instance, (__chnum__)) & (__INTERRUPT__)) == (__INTERRUPT__)) - -#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) -#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) - -#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__)) -#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) -#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) -#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM) -#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM) -#define __HAL_HCD_SET_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT) -#define __HAL_HCD_CLEAR_HC_CSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_COMPLSPLT) -#define __HAL_HCD_CLEAR_HC_SSPLT(chnum) (USBx_HC(chnum)->HCSPLT &= ~USB_OTG_HCSPLT_SPLITEN) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup HCD_Exported_Functions HCD Exported Functions - * @{ - */ - -/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, - uint8_t epnum, uint8_t dev_address, - uint8_t speed, uint8_t ep_type, uint16_t mps); - -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num); -void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd); -void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd); - -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) -/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition - * @brief HAL USB OTG HCD Callback ID enumeration definition - * @{ - */ -typedef enum -{ - HAL_HCD_SOF_CB_ID = 0x01, /*!< USB HCD SOF callback ID */ - HAL_HCD_CONNECT_CB_ID = 0x02, /*!< USB HCD Connect callback ID */ - HAL_HCD_DISCONNECT_CB_ID = 0x03, /*!< USB HCD Disconnect callback ID */ - HAL_HCD_PORT_ENABLED_CB_ID = 0x04, /*!< USB HCD Port Enable callback ID */ - HAL_HCD_PORT_DISABLED_CB_ID = 0x05, /*!< USB HCD Port Disable callback ID */ - - HAL_HCD_MSPINIT_CB_ID = 0x06, /*!< USB HCD MspInit callback ID */ - HAL_HCD_MSPDEINIT_CB_ID = 0x07 /*!< USB HCD MspDeInit callback ID */ - -} HAL_HCD_CallbackIDTypeDef; -/** - * @} - */ - -/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition - * @brief HAL USB OTG HCD Callback pointer definition - * @{ - */ - -typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd); /*!< pointer to a common USB OTG HCD callback function */ -typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd, - uint8_t epnum, - HCD_URBStateTypeDef urb_state); /*!< pointer to USB OTG HCD host channel callback */ -/** - * @} - */ - -HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, - HAL_HCD_CallbackIDTypeDef CallbackID, - pHCD_CallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, - HAL_HCD_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, - pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* I/O operation functions ***************************************************/ -/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, uint8_t ch_num, - uint8_t direction, uint8_t ep_type, - uint8_t token, uint8_t *pbuff, - uint16_t length, uint8_t do_ping); - -HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, - uint8_t addr, uint8_t PortNbr); - -HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num); - -/* Non-Blocking mode: Interrupt */ -void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd); -void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd); -void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd); -void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, - HCD_URBStateTypeDef urb_state); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd); -HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions - * @{ - */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd); -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum); -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum); -uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd); -uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); - - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup HCD_Private_Macros HCD Private Macros - * @{ - */ -/** - * @} - */ -/* Private functions prototypes ----------------------------------------------*/ - -/** - * @} - */ -/** - * @} - */ -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_HCD_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h index 6239a9f1..9e48e5d3 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c.h @@ -1,838 +1,838 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2c.h - * @author MCD Application Team - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_I2C_H -#define STM32F7xx_HAL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization section - in Reference manual */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing - mode is selected. - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ - -} I2C_InitTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap :\n - * b7-b6 Error information\n - * 00 : No Error\n - * 01 : Abort (Abort user request on going)\n - * 10 : Timeout\n - * 11 : Error\n - * b5 Peripheral initialization status\n - * 0 : Reset (peripheral not initialized)\n - * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n - * b4 (not used)\n - * x : Should be set to 0\n - * b3\n - * 0 : Ready or Busy (No Listen mode ongoing)\n - * 1 : Listen (peripheral in Address Listen Mode)\n - * b2 Intrinsic process state\n - * 0 : Ready\n - * 1 : Busy (peripheral busy with some configuration or internal operations)\n - * b1 Rx state\n - * 0 : Ready (no Rx operation ongoing)\n - * 1 : Busy (Rx operation ongoing)\n - * b0 Tx state\n - * 0 : Ready (no Tx operation ongoing)\n - * 1 : Busy (Tx operation ongoing) - * @{ - */ -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ - HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ - HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - -} HAL_I2C_StateTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_mode_structure_definition HAL mode structure definition - * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap :\n - * b7 (not used)\n - * x : Should be set to 0\n - * b6\n - * 0 : None\n - * 1 : Memory (HAL I2C communication is in Memory Mode)\n - * b5\n - * 0 : None\n - * 1 : Slave (HAL I2C communication is in Slave Mode)\n - * b4\n - * 0 : None\n - * 1 : Master (HAL I2C communication is in Master Mode)\n - * b3-b2-b1-b0 (not used)\n - * xxxx : Should be set to 0000 - * @{ - */ -typedef enum -{ - HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ - -} HAL_I2C_ModeTypeDef; - -/** - * @} - */ - -/** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition - * @{ - */ -#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ -#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ -/** - * @} - */ - -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition - * @{ - */ -typedef struct __I2C_HandleTypeDef -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can - be a value of @ref I2C_XFEROPTIONS */ - - __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); - /*!< I2C transfer IRQ handler function pointer */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - - __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ - - __IO uint32_t Devaddress; /*!< I2C Target device address */ - - __IO uint32_t Memaddress; /*!< I2C Target memory address */ - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Error callback */ - void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Abort callback */ - - void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); - /*!< I2C Slave Address Match callback */ - - void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Msp Init callback */ - void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Msp DeInit callback */ - -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -} I2C_HandleTypeDef; - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -/** - * @brief HAL I2C Callback ID enumeration definition - */ -typedef enum -{ - HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ - HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ - HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ - HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ - HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ - HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ - HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ - HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ - HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ - - HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ - HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ - -} HAL_I2C_CallbackIDTypeDef; - -/** - * @brief HAL I2C Callback pointer definition - */ -typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); -/*!< pointer to an I2C callback function */ -typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, - uint16_t AddrMatchCode); -/*!< pointer to an I2C Address Match callback function */ - -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options - * @{ - */ -#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) -#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) - -/* List of XferOptions in usage of : - * 1- Restart condition in all use cases (direction change or not) - */ -#define I2C_OTHER_FRAME (0x000000AAU) -#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) -/** - * @} - */ - -/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) -#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLE (0x00000000U) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -/** - * @} - */ - -/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks - * @{ - */ -#define I2C_OA2_NOMASK ((uint8_t)0x00U) -#define I2C_OA2_MASK01 ((uint8_t)0x01U) -#define I2C_OA2_MASK02 ((uint8_t)0x02U) -#define I2C_OA2_MASK03 ((uint8_t)0x03U) -#define I2C_OA2_MASK04 ((uint8_t)0x04U) -#define I2C_OA2_MASK05 ((uint8_t)0x05U) -#define I2C_OA2_MASK06 ((uint8_t)0x06U) -#define I2C_OA2_MASK07 ((uint8_t)0x07U) -/** - * @} - */ - -/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode - * @{ - */ -#define I2C_GENERALCALL_DISABLE (0x00000000U) -#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN -/** - * @} - */ - -/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLE (0x00000000U) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT (0x00000001U) -#define I2C_MEMADD_SIZE_16BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View - * @{ - */ -#define I2C_DIRECTION_TRANSMIT (0x00000000U) -#define I2C_DIRECTION_RECEIVE (0x00000001U) -/** - * @} - */ - -/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode - * @{ - */ -#define I2C_RELOAD_MODE I2C_CR2_RELOAD -#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE (0x00000000U) -/** - * @} - */ - -/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode - * @{ - */ -#define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) -#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition - * @brief I2C Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask - * @{ - */ -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C Flag definition - * @{ - */ -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_AF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY -#define I2C_FLAG_DIR I2C_ISR_DIR -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - -/** @brief Enable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified I2C interrupt source is enabled or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ - (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_TXIS Transmit interrupt status - * @arg @ref I2C_FLAG_RXNE Receive data register not empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_TC Transfer complete (master mode) - * @arg @ref I2C_FLAG_TCR Transfer complete reload - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * @arg @ref I2C_FLAG_BUSY Bus busy - * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define I2C_FLAG_MASK (0x0001FFFFU) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ - (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ - ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ - ((__HANDLE__)->Instance->ICR = (__FLAG__))) - -/** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) -/** - * @} - */ - -/* Include I2C HAL Extended module */ -#include "stm32f7xx_hal_i2c_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions******************************/ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, - pI2C_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* IO operation functions ****************************************************/ -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout); - -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - -/******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -/** - * @} - */ - -/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @{ - */ -/* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ - IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) - -#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ - ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) - -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ - I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ - I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ - >> 16U)) -#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ - >> 16U)) -#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ - (uint16_t)(0xFF00U))) >> 8U))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) - -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ - (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_ADD10) | (I2C_CR2_START) | \ - (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) - -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ - ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) -#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions are defined in stm32f7xx_hal_i2c.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_I2C_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c.h + * @author MCD Application Team + * @brief Header file of I2C HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_I2C_H +#define STM32F7xx_HAL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ + +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition + * @brief I2C Configuration Structure definition + * @{ + */ +typedef struct +{ + uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. + This parameter calculated by referring to I2C initialization section + in Reference manual */ + + uint32_t OwnAddress1; /*!< Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. + This parameter can be a value of @ref I2C_ADDRESSING_MODE */ + + uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. + This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ + + uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected + This parameter can be a 7-bit address. */ + + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ + + uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. + This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ + + uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ + +} I2C_InitTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @note HAL I2C State value coding follow below described bitmap :\n + * b7-b6 Error information\n + * 00 : No Error\n + * 01 : Abort (Abort user request on going)\n + * 10 : Timeout\n + * 11 : Error\n + * b5 Peripheral initialization status\n + * 0 : Reset (peripheral not initialized)\n + * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n + * b4 (not used)\n + * x : Should be set to 0\n + * b3\n + * 0 : Ready or Busy (No Listen mode ongoing)\n + * 1 : Listen (peripheral in Address Listen Mode)\n + * b2 Intrinsic process state\n + * 0 : Ready\n + * 1 : Busy (peripheral busy with some configuration or internal operations)\n + * b1 Rx state\n + * 0 : Ready (no Rx operation ongoing)\n + * 1 : Busy (Rx operation ongoing)\n + * b0 Tx state\n + * 0 : Ready (no Tx operation ongoing)\n + * 1 : Busy (Tx operation ongoing) + * @{ + */ +typedef enum +{ + HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ + HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ + HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ + HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ + HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ + HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission + process is ongoing */ + HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception + process is ongoing */ + HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ + +} HAL_I2C_StateTypeDef; + +/** + * @} + */ + +/** @defgroup HAL_mode_structure_definition HAL mode structure definition + * @brief HAL Mode structure definition + * @note HAL I2C Mode value coding follow below described bitmap :\n + * b7 (not used)\n + * x : Should be set to 0\n + * b6\n + * 0 : None\n + * 1 : Memory (HAL I2C communication is in Memory Mode)\n + * b5\n + * 0 : None\n + * 1 : Slave (HAL I2C communication is in Slave Mode)\n + * b4\n + * 0 : None\n + * 1 : Master (HAL I2C communication is in Master Mode)\n + * b3-b2-b1-b0 (not used)\n + * xxxx : Should be set to 0000 + * @{ + */ +typedef enum +{ + HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ + HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ + HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ + HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ + +} HAL_I2C_ModeTypeDef; + +/** + * @} + */ + +/** @defgroup I2C_Error_Code_definition I2C Error Code definition + * @brief I2C Error Code definition + * @{ + */ +#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ +#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ +#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ +#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ +/** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition + * @brief I2C handle Structure definition + * @{ + */ +typedef struct __I2C_HandleTypeDef +{ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can + be a value of @ref I2C_XFEROPTIONS */ + + __IO uint32_t PreviousState; /*!< I2C communication Previous state */ + + HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< I2C transfer IRQ handler function pointer */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ + + __IO uint32_t ErrorCode; /*!< I2C Error code */ + + __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ + + __IO uint32_t Devaddress; /*!< I2C Target device address */ + + __IO uint32_t Memaddress; /*!< I2C Target memory address */ + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Error callback */ + void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Abort callback */ + + void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< I2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp Init callback */ + void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); + /*!< I2C Msp DeInit callback */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} I2C_HandleTypeDef; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief HAL I2C Callback ID enumeration definition + */ +typedef enum +{ + HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ + HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ + HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ + HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ + HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ + HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ + HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ + HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ + HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ + + HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ + HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ + +} HAL_I2C_CallbackIDTypeDef; + +/** + * @brief HAL I2C Callback pointer definition + */ +typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); +/*!< pointer to an I2C callback function */ +typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an I2C Address Match callback function */ + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** + * @} + */ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options + * @{ + */ +#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) +#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) +#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) +#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) + +/* List of XferOptions in usage of : + * 1- Restart condition in all use cases (direction change or not) + */ +#define I2C_OTHER_FRAME (0x000000AAU) +#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) +/** + * @} + */ + +/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode + * @{ + */ +#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) +#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode + * @{ + */ +#define I2C_DUALADDRESS_DISABLE (0x00000000U) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN +/** + * @} + */ + +/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks + * @{ + */ +#define I2C_OA2_NOMASK ((uint8_t)0x00U) +#define I2C_OA2_MASK01 ((uint8_t)0x01U) +#define I2C_OA2_MASK02 ((uint8_t)0x02U) +#define I2C_OA2_MASK03 ((uint8_t)0x03U) +#define I2C_OA2_MASK04 ((uint8_t)0x04U) +#define I2C_OA2_MASK05 ((uint8_t)0x05U) +#define I2C_OA2_MASK06 ((uint8_t)0x06U) +#define I2C_OA2_MASK07 ((uint8_t)0x07U) +/** + * @} + */ + +/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode + * @{ + */ +#define I2C_GENERALCALL_DISABLE (0x00000000U) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN +/** + * @} + */ + +/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode + * @{ + */ +#define I2C_NOSTRETCH_DISABLE (0x00000000U) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH +/** + * @} + */ + +/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size + * @{ + */ +#define I2C_MEMADD_SIZE_8BIT (0x00000001U) +#define I2C_MEMADD_SIZE_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View + * @{ + */ +#define I2C_DIRECTION_TRANSMIT (0x00000000U) +#define I2C_DIRECTION_RECEIVE (0x00000001U) +/** + * @} + */ + +/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode + * @{ + */ +#define I2C_RELOAD_MODE I2C_CR2_RELOAD +#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND +#define I2C_SOFTEND_MODE (0x00000000U) +/** + * @} + */ + +/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode + * @{ + */ +#define I2C_NO_STARTSTOP (0x00000000U) +#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/** + * @} + */ + +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition + * @brief I2C Interrupt definition + * Elements values convention: 0xXXXXXXXX + * - XXXXXXXX : Interrupt control mask + * @{ + */ +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE +/** + * @} + */ + +/** @defgroup I2C_Flag_definition I2C Flag definition + * @{ + */ +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_AF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY +#define I2C_FLAG_DIR I2C_ISR_DIR +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @brief Reset I2C handle state. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** @brief Enable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupt. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval None + */ +#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) + +/** @brief Check whether the specified I2C interrupt source is enabled or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __INTERRUPT__ specifies the I2C interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref I2C_IT_ERRI Errors interrupt enable + * @arg @ref I2C_IT_TCI Transfer complete interrupt enable + * @arg @ref I2C_IT_STOPI STOP detection interrupt enable + * @arg @ref I2C_IT_NACKI NACK received interrupt enable + * @arg @ref I2C_IT_ADDRI Address match interrupt enable + * @arg @ref I2C_IT_RXI RX interrupt enable + * @arg @ref I2C_IT_TXI TX interrupt enable + * + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ + (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified I2C flag is set or not. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_TXIS Transmit interrupt status + * @arg @ref I2C_FLAG_RXNE Receive data register not empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_TC Transfer complete (master mode) + * @arg @ref I2C_FLAG_TCR Transfer complete reload + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * @arg @ref I2C_FLAG_BUSY Bus busy + * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) + * + * @retval The new state of __FLAG__ (SET or RESET). + */ +#define I2C_FLAG_MASK (0x0001FFFFU) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. + * @param __HANDLE__ specifies the I2C Handle. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg @ref I2C_FLAG_TXE Transmit data register empty + * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) + * @arg @ref I2C_FLAG_AF Acknowledge failure received flag + * @arg @ref I2C_FLAG_STOPF STOP detection flag + * @arg @ref I2C_FLAG_BERR Bus error + * @arg @ref I2C_FLAG_ARLO Arbitration lost + * @arg @ref I2C_FLAG_OVR Overrun/Underrun + * @arg @ref I2C_FLAG_PECERR PEC error in reception + * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag + * @arg @ref I2C_FLAG_ALERT SMBus alert + * + * @retval None + */ +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) + +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) + +/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. + * @param __HANDLE__ specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) +/** + * @} + */ + +/* Include I2C HAL Extended module */ +#include "stm32f7xx_hal_i2c_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ +/******* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout); + +/******* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); + +/******* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size); + +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions); +/** + * @} + */ + +/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ +/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); +void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @{ + */ +/* Peripheral State, Mode and Error functions *********************************/ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); + +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + +#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ + ((REQUEST) == I2C_NEXT_FRAME) || \ + ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME) || \ + ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ + IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) + +#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ + ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) + +#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ + I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ + I2C_CR2_RD_WRN))) + +#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ + >> 16U)) +#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ + >> 16U)) +#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) +#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) + +#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ + (uint16_t)(0xFF00U))) >> 8U))) +#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) + +#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ + (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ + (I2C_CR2_ADD10) | (I2C_CR2_START) | \ + (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) + +#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ + ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) +#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32f7xx_hal_i2c.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F7xx_HAL_I2C_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h index 27bdcf07..f0c572fd 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2c_ex.h @@ -1,212 +1,212 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2c_ex.h - * @author MCD Application Team - * @brief Header file of I2C HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_I2C_EX_H -#define STM32F7xx_HAL_I2C_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2CEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants - * @{ - */ - -/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter - * @{ - */ -#define I2C_ANALOGFILTER_ENABLE 0x00000000U -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -/** - * @} - */ - -/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus - * @{ - */ -#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ -#if defined(SYSCFG_PMC_I2C_PB6_FMP) -#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ -#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ -#else -#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */ -#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */ -#endif /* SYSCFG_PMC_I2C_PB6_FMP */ -#if defined(SYSCFG_PMC_I2C_PB8_FMP) -#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ -#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ -#else -#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */ -#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */ -#endif /* SYSCFG_PMC_I2C_PB8_FMP */ -#if defined(SYSCFG_PMC_I2C1_FMP) -#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ -#else -#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ -#endif /* SYSCFG_PMC_I2C1_FMP */ -#if defined(SYSCFG_PMC_I2C2_FMP) -#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ -#else -#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ -#endif /* SYSCFG_PMC_I2C2_FMP */ -#if defined(SYSCFG_PMC_I2C3_FMP) -#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ -#else -#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ -#endif /* SYSCFG_PMC_I2C3_FMP */ -#if defined(SYSCFG_PMC_I2C4_FMP) -#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ -#else -#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ -#endif /* SYSCFG_PMC_I2C4_FMP */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions - * @{ - */ -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -/** - * @} - */ -#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) - -/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions - * @{ - */ -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); -/** - * @} - */ -#endif /* Fast Mode Plus Availability */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros - * @{ - */ -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) - -#if defined(SYSCFG_PMC_I2C4_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) -#elif defined(SYSCFG_PMC_I2C3_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) -#elif defined(SYSCFG_PMC_I2C2_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) -#elif defined(SYSCFG_PMC_I2C1_FMP) -#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ - (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) -#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions - * @{ - */ -/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_I2C_EX_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c_ex.h + * @author MCD Application Team + * @brief Header file of I2C HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_I2C_EX_H +#define STM32F7xx_HAL_I2C_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup I2CEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants + * @{ + */ + +/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter + * @{ + */ +#define I2C_ANALOGFILTER_ENABLE 0x00000000U +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF +/** + * @} + */ + +/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus + * @{ + */ +#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ +#if defined(SYSCFG_PMC_I2C_PB6_FMP) +#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#else +#define I2C_FASTMODEPLUS_PB6 (uint32_t)(0x00000004U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB6 not supported */ +#define I2C_FASTMODEPLUS_PB7 (uint32_t)(0x00000008U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB7 not supported */ +#endif /* SYSCFG_PMC_I2C_PB6_FMP */ +#if defined(SYSCFG_PMC_I2C_PB8_FMP) +#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#else +#define I2C_FASTMODEPLUS_PB8 (uint32_t)(0x00000010U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB8 not supported */ +#define I2C_FASTMODEPLUS_PB9 (uint32_t)(0x00000012U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PB9 not supported */ +#endif /* SYSCFG_PMC_I2C_PB8_FMP */ +#if defined(SYSCFG_PMC_I2C1_FMP) +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#else +#define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ +#endif /* SYSCFG_PMC_I2C1_FMP */ +#if defined(SYSCFG_PMC_I2C2_FMP) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#else +#define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ +#endif /* SYSCFG_PMC_I2C2_FMP */ +#if defined(SYSCFG_PMC_I2C3_FMP) +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#else +#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */ +#endif /* SYSCFG_PMC_I2C3_FMP */ +#if defined(SYSCFG_PMC_I2C4_FMP) +#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */ +#else +#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */ +#endif /* SYSCFG_PMC_I2C4_FMP */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +/** + * @} + */ +#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) + +/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @{ + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); +/** + * @} + */ +#endif /* Fast Mode Plus Availability */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) + +#if defined(SYSCFG_PMC_I2C4_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4)) +#elif defined(SYSCFG_PMC_I2C3_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3)) +#elif defined(SYSCFG_PMC_I2C2_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2)) +#elif defined(SYSCFG_PMC_I2C1_FMP) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1)) +#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */ +/** + * @} + */ + +/* Private Functions ---------------------------------------------------------*/ +/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions + * @{ + */ +/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_I2C_EX_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h deleted file mode 100644 index 0a08ac15..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_i2s.h +++ /dev/null @@ -1,565 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2s.h - * @author MCD Application Team - * @brief Header file of I2S HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_I2S_H -#define STM32F7xx_HAL_I2S_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2S - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2S_Exported_Types I2S Exported Types - * @{ - */ - -/** - * @brief I2S Init structure definition - */ -typedef struct -{ - uint32_t Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_Mode */ - - uint32_t Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_Standard */ - - uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_Data_Format */ - - uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_MCLK_Output */ - - uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_Audio_Frequency */ - - uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_Clock_Polarity */ - - uint32_t ClockSource; /*!< Specifies the I2S Clock Source. - This parameter can be a value of @ref I2S_Clock_Source */ -} I2S_InitTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ - HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ -} HAL_I2S_StateTypeDef; - -/** - * @brief I2S handle Structure definition - */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1) -typedef struct __I2S_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -{ - SPI_TypeDef *Instance; /*!< I2S registers base address */ - - I2S_InitTypeDef Init; /*!< I2S communication parameters */ - - uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ - - __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ - - __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ - - uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ - - __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ - - __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter - (This field is initialized at the - same value as transfer size at the - beginning of the transfer and - decremented when a sample is received - NbSamplesReceived = RxBufferSize-RxBufferCount) */ - DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ - - __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ - - __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ - - __IO uint32_t ErrorCode; /*!< I2S Error code - This parameter can be a value of @ref I2S_Error */ - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ - void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ - void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ - void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ - void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ - void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ - void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ - -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} I2S_HandleTypeDef; - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -/** - * @brief HAL I2S Callback ID enumeration definition - */ -typedef enum -{ - HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ - HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ - HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ - HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ - HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ - HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ - HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ - -} HAL_I2S_CallbackIDTypeDef; - -/** - * @brief HAL I2S Callback pointer definition - */ -typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ - -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2S_Exported_Constants I2S Exported Constants - * @{ - */ -/** @defgroup I2S_Error I2S Error - * @{ - */ -#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ -#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ -#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ -#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ -#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ -/** - * @} - */ - -/** @defgroup I2S_Mode I2S Mode - * @{ - */ -#define I2S_MODE_SLAVE_TX (0x00000000U) -#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) -#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) -#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) -/** - * @} - */ - -/** @defgroup I2S_Standard I2S Standard - * @{ - */ -#define I2S_STANDARD_PHILIPS (0x00000000U) -#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) -#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) -#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) -#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) -/** - * @} - */ - -/** @defgroup I2S_Data_Format I2S Data Format - * @{ - */ -#define I2S_DATAFORMAT_16B (0x00000000U) -#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) -#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) -#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) -/** - * @} - */ - -/** @defgroup I2S_MCLK_Output I2S MCLK Output - * @{ - */ -#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) -#define I2S_MCLKOUTPUT_DISABLE (0x00000000U) -/** - * @} - */ - -/** @defgroup I2S_Audio_Frequency I2S Audio Frequency - * @{ - */ -#define I2S_AUDIOFREQ_192K (192000U) -#define I2S_AUDIOFREQ_96K (96000U) -#define I2S_AUDIOFREQ_48K (48000U) -#define I2S_AUDIOFREQ_44K (44100U) -#define I2S_AUDIOFREQ_32K (32000U) -#define I2S_AUDIOFREQ_22K (22050U) -#define I2S_AUDIOFREQ_16K (16000U) -#define I2S_AUDIOFREQ_11K (11025U) -#define I2S_AUDIOFREQ_8K (8000U) -#define I2S_AUDIOFREQ_DEFAULT (2U) -/** - * @} - */ - -/** @defgroup I2S_Clock_Polarity I2S Clock Polarity - * @{ - */ -#define I2S_CPOL_LOW (0x00000000U) -#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) -/** - * @} - */ - -/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition - * @{ - */ -#define I2S_IT_TXE SPI_CR2_TXEIE -#define I2S_IT_RXNE SPI_CR2_RXNEIE -#define I2S_IT_ERR SPI_CR2_ERRIE -/** - * @} - */ - -/** @defgroup I2S_Flags_Definition I2S Flags Definition - * @{ - */ -#define I2S_FLAG_TXE SPI_SR_TXE -#define I2S_FLAG_RXNE SPI_SR_RXNE - -#define I2S_FLAG_UDR SPI_SR_UDR -#define I2S_FLAG_OVR SPI_SR_OVR -#define I2S_FLAG_FRE SPI_SR_FRE - -#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE -#define I2S_FLAG_BSY SPI_SR_BSY - -#define I2S_FLAG_MASK (SPI_SR_RXNE\ - | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) -/** - * @} - */ - -/** @defgroup I2S_Clock_Source I2S Clock Source Definition - * @{ - */ -#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U) -#define I2S_CLOCK_PLL ((uint32_t)0x00000002U) -/** - * @} - */ -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup I2S_Exported_macros I2S Exported Macros - * @{ - */ - -/** @brief Reset I2S handle state - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - -/** @brief Enable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - -/** @brief Disable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - -/** @brief Enable the specified I2S interrupts. - * @param __HANDLE__ specifies the I2S Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) - -/** @brief Disable the specified I2S interrupts. - * @param __HANDLE__ specifies the I2S Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) - -/** @brief Checks if the specified I2S interrupt source is enabled or disabled. - * @param __HANDLE__ specifies the I2S Handle. - * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__ specifies the I2S interrupt source to check. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ - & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks whether the specified I2S flag is set or not. - * @param __HANDLE__ specifies the I2S Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2S_FLAG_RXNE: Receive buffer not empty flag - * @arg I2S_FLAG_TXE: Transmit buffer empty flag - * @arg I2S_FLAG_UDR: Underrun flag - * @arg I2S_FLAG_OVR: Overrun flag - * @arg I2S_FLAG_FRE: Frame error flag - * @arg I2S_FLAG_CHSIDE: Channel Side flag - * @arg I2S_FLAG_BSY: Busy flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clears the I2S OVR pending flag. - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ - __IO uint32_t tmpreg_ovr = 0x00U; \ - tmpreg_ovr = (__HANDLE__)->Instance->DR; \ - tmpreg_ovr = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_ovr); \ - }while(0U) -/** @brief Clears the I2S UDR pending flag. - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ - __IO uint32_t tmpreg_udr = 0x00U;\ - tmpreg_udr = ((__HANDLE__)->Instance->SR);\ - UNUSED(tmpreg_udr); \ - }while(0U) -/** @brief Flush the I2S DR Register. - * @param __HANDLE__ specifies the I2S Handle. - * @retval None - */ -#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ - __IO uint32_t tmpreg_dr = 0x00U;\ - tmpreg_dr = ((__HANDLE__)->Instance->DR);\ - UNUSED(tmpreg_dr); \ - }while(0U) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2S_Exported_Functions - * @{ - */ - -/** @addtogroup I2S_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); -void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); -void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, - pI2S_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup I2S_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ***************************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); -HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); - -/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ -void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); -void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); -/** - * @} - */ - -/** @addtogroup I2S_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2S_Private_Macros I2S Private Macros - * @{ - */ - -/** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of I2S SR register. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg I2S_FLAG_RXNE: Receive buffer not empty flag - * @arg I2S_FLAG_TXE: Transmit buffer empty flag - * @arg I2S_FLAG_UDR: Underrun error flag - * @arg I2S_FLAG_OVR: Overrun flag - * @arg I2S_FLAG_CHSIDE: Channel side flag - * @arg I2S_FLAG_BSY: Busy flag - * @retval SET or RESET. - */ -#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ - & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) - -/** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of I2S CR2 register. - * @param __INTERRUPT__ specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg I2S_IT_TXE: Tx buffer empty interrupt enable - * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable - * @arg I2S_IT_ERR: Error interrupt enable - * @retval SET or RESET. - */ -#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ - & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks if I2S Mode parameter is in allowed range. - * @param __MODE__ specifies the I2S Mode. - * This parameter can be a value of @ref I2S_Mode - * @retval None - */ -#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ - ((__MODE__) == I2S_MODE_SLAVE_RX) || \ - ((__MODE__) == I2S_MODE_MASTER_TX) || \ - ((__MODE__) == I2S_MODE_MASTER_RX)) - -#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ - ((__STANDARD__) == I2S_STANDARD_MSB) || \ - ((__STANDARD__) == I2S_STANDARD_LSB) || \ - ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ - ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) - -#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ - ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ - ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ - ((__FORMAT__) == I2S_DATAFORMAT_32B)) - -#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ - ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) - -#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ - ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ - ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) - -/** @brief Checks if I2S Serial clock steady state parameter is in allowed range. - * @param __CPOL__ specifies the I2S serial clock steady state. - * This parameter can be a value of @ref I2S_Clock_Polarity - * @retval None - */ -#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ - ((__CPOL__) == I2S_CPOL_HIGH)) - -#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \ - ((CLOCK) == I2S_CLOCK_PLL)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_I2S_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h deleted file mode 100644 index 35455e89..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda.h +++ /dev/null @@ -1,857 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_irda.h - * @author MCD Application Team - * @brief Header file of IRDA HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_IRDA_H -#define STM32F7xx_HAL_IRDA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup IRDA - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Types IRDA Exported Types - * @{ - */ - -/** - * @brief IRDA Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate. - The baud rate register is computed using the following formula: - Baud Rate Register = ((usart_ker_clk) / ((hirda->Init.BaudRate))) - where usart_ker_clk is the IRDA input clock */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref IRDAEx_Word_Length */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref IRDA_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref IRDA_Transfer_Mode */ - - uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock - to achieve low-power frequency. - @note Prescaler value 0 is forbidden */ - - uint16_t PowerMode; /*!< Specifies the IRDA power mode. - This parameter can be a value of @ref IRDA_Low_Power */ - -} IRDA_InitTypeDef; - -/** - * @brief HAL IRDA State definition - * @note HAL IRDA State value is a combination of 2 different substates: - * gState and RxState (see @ref IRDA_State_Definition). - * - gState contains IRDA state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized. HAL IRDA Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (Peripheral busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef uint32_t HAL_IRDA_StateTypeDef; - -/** - * @brief IRDA clock sources definition - */ -typedef enum -{ - IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ - IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */ -} IRDA_ClockSourceTypeDef; - -/** - * @brief IRDA handle Structure definition - */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -typedef struct __IRDA_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ -{ - USART_TypeDef *Instance; /*!< USART registers base address */ - - IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - - const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< IRDA Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */ - - uint16_t Mask; /*!< USART RX RDR register mask */ - - DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ - - __IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations. - This parameter can be a value of @ref HAL_IRDA_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< IRDA Error code */ - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */ - - void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */ - - void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */ - - void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */ - - void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */ - - void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */ - - void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */ - - void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */ - - - void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */ - - void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */ -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - -} IRDA_HandleTypeDef; - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -/** - * @brief HAL IRDA Callback ID enumeration definition - */ -typedef enum -{ - HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */ - HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */ - HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */ - HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */ - HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */ - HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */ - HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */ - HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */ - - HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */ - HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */ - -} HAL_IRDA_CallbackIDTypeDef; - -/** - * @brief HAL IRDA Callback pointer definition - */ -typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */ - -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Constants IRDA Exported Constants - * @{ - */ - -/** @defgroup IRDA_State_Definition IRDA State Code Definition - * @{ - */ -#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ -#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing - Value is allowed for gState only */ -#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ -#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing - Value is allowed for RxState only */ -#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between - gState and RxState values */ -#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ -#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ -/** - * @} - */ - -/** @defgroup IRDA_Error_Definition IRDA Error Code Definition - * @{ - */ -#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup IRDA_Parity IRDA Parity - * @{ - */ -#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */ -#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ -#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ -/** - * @} - */ - -/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode - * @{ - */ -#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */ -#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */ -#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ -/** - * @} - */ - -/** @defgroup IRDA_Low_Power IRDA Low Power - * @{ - */ -#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */ -#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */ -/** - * @} - */ - -/** @defgroup IRDA_State IRDA State - * @{ - */ -#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */ -#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */ -/** - * @} - */ - -/** @defgroup IRDA_Mode IRDA Mode - * @{ - */ -#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */ -#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */ -/** - * @} - */ - -/** @defgroup IRDA_One_Bit IRDA One Bit Sampling - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */ -#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */ -/** - * @} - */ - -/** @defgroup IRDA_DMA_Tx IRDA DMA Tx - * @{ - */ -#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */ -#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */ -/** - * @} - */ - -/** @defgroup IRDA_DMA_Rx IRDA DMA Rx - * @{ - */ -#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */ -#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */ -/** - * @} - */ - -/** @defgroup IRDA_Request_Parameters IRDA Request Parameters - * @{ - */ -#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ -#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ -#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ -/** - * @} - */ - -/** @defgroup IRDA_Flags IRDA Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#if defined(USART_ISR_REACK) -#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */ -#endif /* USART_ISR_REACK */ -#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */ -#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */ -#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */ -#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */ -#define IRDA_FLAG_TXE USART_ISR_TXE /*!< IRDA transmit data register empty */ -#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */ -#define IRDA_FLAG_RXNE USART_ISR_RXNE /*!< IRDA read data register not empty */ -#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */ -#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */ -#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */ -#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */ -/** - * @} - */ - -/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition - * Elements values convention: 0000ZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZ : Flag position in the ISR register(4bits) - * @{ - */ -#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */ -#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */ -#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */ -#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */ -#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */ - -/* Elements values convention: 000000000XXYYYYYb - - YYYYY : Interrupt source position in the XX register (5bits) - - XX : Interrupt source register (2bits) - - 01: CR1 register - - 10: CR2 register - - 11: CR3 register */ -#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */ - -/* Elements values convention: 0000ZZZZ00000000b - - ZZZZ : Flag position in the ISR register(4bits) */ -#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */ -#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */ -#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */ -/** - * @} - */ - -/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags - * @{ - */ -#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ -#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -/** - * @} - */ - -/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask - * @{ - */ -#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */ -#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */ -#define IRDA_CR_POS 5U /*!< IRDA control register position */ -#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */ -#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Macros IRDA Exported Macros - * @{ - */ - -/** @brief Reset IRDA handle state. - * @param __HANDLE__ IRDA handle. - * @retval None - */ -#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 -#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \ - } while(0U) -#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */ - -/** @brief Flush the IRDA DR register. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ - } while(0U) - -/** @brief Clear the specified IRDA pending flag. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg @ref IRDA_CLEAR_PEF - * @arg @ref IRDA_CLEAR_FEF - * @arg @ref IRDA_CLEAR_NEF - * @arg @ref IRDA_CLEAR_OREF - * @arg @ref IRDA_CLEAR_TCF - * @arg @ref IRDA_CLEAR_IDLEF - * @retval None - */ -#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** @brief Clear the IRDA PE pending flag. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF) - - -/** @brief Clear the IRDA FE pending flag. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF) - -/** @brief Clear the IRDA NE pending flag. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF) - -/** @brief Clear the IRDA ORE pending flag. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF) - -/** @brief Clear the IRDA IDLE pending flag. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF) - -/** @brief Check whether the specified IRDA flag is set or not. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: -#if defined(USART_ISR_REACK) - * @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag -#endif - * @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag - * @arg @ref IRDA_FLAG_BUSY Busy flag - * @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag - * @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag - * @arg @ref IRDA_FLAG_TXE Transmit data register empty flag - * @arg @ref IRDA_FLAG_TC Transmission Complete flag - * @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag - * @arg @ref IRDA_FLAG_ORE OverRun Error flag - * @arg @ref IRDA_FLAG_NE Noise Error flag - * @arg @ref IRDA_FLAG_FE Framing Error flag - * @arg @ref IRDA_FLAG_PE Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - - -/** @brief Enable the specified IRDA interrupt. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __INTERRUPT__ specifies the IRDA interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt - * @arg @ref IRDA_IT_TC Transmission complete interrupt - * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt - * @arg @ref IRDA_IT_IDLE Idle line detection interrupt - * @arg @ref IRDA_IT_PE Parity Error interrupt - * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ - ((__HANDLE__)->Instance->CR1 |= (1U << \ - ((__INTERRUPT__) & IRDA_IT_MASK))):\ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ - ((__HANDLE__)->Instance->CR2 |= (1U << \ - ((__INTERRUPT__) & IRDA_IT_MASK))):\ - ((__HANDLE__)->Instance->CR3 |= (1U << \ - ((__INTERRUPT__) & IRDA_IT_MASK)))) - -/** @brief Disable the specified IRDA interrupt. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __INTERRUPT__ specifies the IRDA interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt - * @arg @ref IRDA_IT_TC Transmission complete interrupt - * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt - * @arg @ref IRDA_IT_IDLE Idle line detection interrupt - * @arg @ref IRDA_IT_PE Parity Error interrupt - * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ - ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ - ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ - ((__INTERRUPT__) & IRDA_IT_MASK)))) - -/** @brief Check whether the specified IRDA interrupt has occurred or not. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __INTERRUPT__ specifies the IRDA interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt - * @arg @ref IRDA_IT_TC Transmission complete interrupt - * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt - * @arg @ref IRDA_IT_IDLE Idle line detection interrupt - * @arg @ref IRDA_IT_ORE OverRun Error interrupt - * @arg @ref IRDA_IT_NE Noise Error interrupt - * @arg @ref IRDA_IT_FE Framing Error interrupt - * @arg @ref IRDA_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (SET or RESET). - */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ - ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) - -/** @brief Check whether the specified IRDA interrupt source is enabled or not. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __INTERRUPT__ specifies the IRDA interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt - * @arg @ref IRDA_IT_TC Transmission complete interrupt - * @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt - * @arg @ref IRDA_IT_IDLE Idle line detection interrupt - * @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt - * @arg @ref IRDA_IT_PE Parity Error interrupt - * @retval The new state of __IT__ (SET or RESET). - */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ - & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ - & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) - -/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt - * This parameter can be one of the following values: - * @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag - * @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag - * @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag - * @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag - * @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag - * @retval None - */ -#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) - - -/** @brief Set a specific IRDA request flag. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __REQ__ specifies the request flag to set - * This parameter can be one of the following values: - * @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request - * @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request - * @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request - * @retval None - */ -#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) - -/** @brief Enable the IRDA one bit sample method. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disable the IRDA one bit sample method. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ - &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) - -/** @brief Enable UART/USART associated to IRDA Handle. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART/USART associated to IRDA Handle. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None - */ -#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @addtogroup IRDA_Private_Macros - * @{ - */ - -/** @brief Ensure that IRDA Baud rate is less or equal to maximum value. - * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user. - * @retval True or False - */ -#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U) - -/** @brief Ensure that IRDA prescaler value is strictly larger than 0. - * @param __PRESCALER__ specifies the IRDA prescaler value set by the user. - * @retval True or False - */ -#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U) - -/** @brief Ensure that IRDA frame parity is valid. - * @param __PARITY__ IRDA frame parity. - * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ -#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \ - ((__PARITY__) == IRDA_PARITY_EVEN) || \ - ((__PARITY__) == IRDA_PARITY_ODD)) - -/** @brief Ensure that IRDA communication mode is valid. - * @param __MODE__ IRDA communication mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\ - & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) - -/** @brief Ensure that IRDA power mode is valid. - * @param __MODE__ IRDA power mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \ - ((__MODE__) == IRDA_POWERMODE_NORMAL)) - -/** @brief Ensure that IRDA state is valid. - * @param __STATE__ IRDA state mode. - * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ -#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \ - ((__STATE__) == IRDA_STATE_ENABLE)) - -/** @brief Ensure that IRDA associated UART/USART mode is valid. - * @param __MODE__ IRDA associated UART/USART mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \ - ((__MODE__) == IRDA_MODE_ENABLE)) - -/** @brief Ensure that IRDA sampling rate is valid. - * @param __ONEBIT__ IRDA sampling rate. - * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ -#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ - ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE)) - -/** @brief Ensure that IRDA DMA TX mode is valid. - * @param __DMATX__ IRDA DMA TX mode. - * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) - */ -#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \ - ((__DMATX__) == IRDA_DMA_TX_ENABLE)) - -/** @brief Ensure that IRDA DMA RX mode is valid. - * @param __DMARX__ IRDA DMA RX mode. - * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) - */ -#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \ - ((__DMARX__) == IRDA_DMA_RX_ENABLE)) - -/** @brief Ensure that IRDA request is valid. - * @param __PARAM__ IRDA request. - * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ -#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \ - ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \ - ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST)) -/** - * @} - */ - -/* Include IRDA HAL Extended module */ -#include "stm32f7xx_hal_irda_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions - * @{ - */ - -/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -/* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, - pIRDA_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda); -HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda); - -void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda); -void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); - -/** - * @} - */ - -/* Peripheral Control functions ************************************************/ - -/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State and Error functions ***************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_IRDA_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h deleted file mode 100644 index 042c0e05..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_irda_ex.h +++ /dev/null @@ -1,320 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_irda_ex.h - * @author MCD Application Team - * @brief Header file of IRDA HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_IRDA_EX_H -#define STM32F7xx_HAL_IRDA_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup IRDAEx IRDAEx - * @brief IRDA Extended HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants - * @{ - */ - -/** @defgroup IRDAEx_Word_Length IRDAEx Word Length - * @{ - */ -#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */ -#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */ -#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros - * @{ - */ - -/** @brief Report the IRDA clock source. - * @param __HANDLE__ specifies the IRDA Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval IRDA clocking source, written in __CLOCKSOURCE__. - */ -#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ - case RCC_UART4CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART4CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART4CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART4CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART5) \ - { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ - case RCC_UART5CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART5CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART5CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART5CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ - case RCC_USART6CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART6CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART6CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART6CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART7) \ - { \ - switch(__HAL_RCC_GET_UART7_SOURCE()) \ - { \ - case RCC_UART7CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART7CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART7CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART7CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART8) \ - { \ - switch(__HAL_RCC_GET_UART8_SOURCE()) \ - { \ - case RCC_UART8CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART8CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART8CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART8CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) - -/** @brief Compute the mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @param __HANDLE__ specifies the IRDA Handle. - * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define IRDA_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ - } while(0U) - -/** @brief Ensure that IRDA frame length is valid. - * @param __LENGTH__ IRDA frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \ - ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \ - ((__LENGTH__) == IRDA_WORDLENGTH_9B)) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_IRDA_EX_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h deleted file mode 100644 index 9de6cdfb..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_iwdg.h +++ /dev/null @@ -1,237 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_iwdg.h - * @author MCD Application Team - * @brief Header file of IWDG HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_IWDG_H -#define STM32F7xx_HAL_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup IWDG IWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup IWDG_Exported_Types IWDG Exported Types - * @{ - */ - -/** - * @brief IWDG Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Select the prescaler of the IWDG. - This parameter can be a value of @ref IWDG_Prescaler */ - - uint32_t Reload; /*!< Specifies the IWDG down-counter reload value. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ - - uint32_t Window; /*!< Specifies the window value to be compared to the down-counter. - This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ - -} IWDG_InitTypeDef; - -/** - * @brief IWDG Handle Structure definition - */ -typedef struct -{ - IWDG_TypeDef *Instance; /*!< Register base address */ - - IWDG_InitTypeDef Init; /*!< IWDG required parameters */ -} IWDG_HandleTypeDef; - - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup IWDG_Exported_Constants IWDG Exported Constants - * @{ - */ - -/** @defgroup IWDG_Prescaler IWDG Prescaler - * @{ - */ -#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */ -#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */ -#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */ -#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */ -#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */ -#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */ -#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */ -/** - * @} - */ - -/** @defgroup IWDG_Window_option IWDG Window option - * @{ - */ -#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup IWDG_Exported_Macros IWDG Exported Macros - * @{ - */ - -/** - * @brief Enable the IWDG peripheral. - * @param __HANDLE__ IWDG handle - * @retval None - */ -#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) - -/** - * @brief Reload IWDG counter with value defined in the reload register - * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled). - * @param __HANDLE__ IWDG handle - * @retval None - */ -#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup IWDG_Exported_Functions IWDG Exported Functions - * @{ - */ - -/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions - * @{ - */ -/* Initialization/Start functions ********************************************/ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); -/** - * @} - */ - -/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions - * @{ - */ -/* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup IWDG_Private_Constants IWDG Private Constants - * @{ - */ - -/** - * @brief IWDG Key Register BitMask - */ -#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */ -#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */ -#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */ -#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup IWDG_Private_Macros IWDG Private Macros - * @{ - */ - -/** - * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__ IWDG handle - * @retval None - */ -#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) - -/** - * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__ IWDG handle - * @retval None - */ -#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) - -/** - * @brief Check IWDG prescaler value. - * @param __PRESCALER__ IWDG prescaler value - * @retval None - */ -#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ - ((__PRESCALER__) == IWDG_PRESCALER_8) || \ - ((__PRESCALER__) == IWDG_PRESCALER_16) || \ - ((__PRESCALER__) == IWDG_PRESCALER_32) || \ - ((__PRESCALER__) == IWDG_PRESCALER_64) || \ - ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ - ((__PRESCALER__) == IWDG_PRESCALER_256)) - -/** - * @brief Check IWDG reload value. - * @param __RELOAD__ IWDG reload value - * @retval None - */ -#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) - -/** - * @brief Check IWDG window value. - * @param __WINDOW__ IWDG window value - * @retval None - */ -#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_IWDG_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_jpeg.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_jpeg.h deleted file mode 100644 index 6eb2af70..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_jpeg.h +++ /dev/null @@ -1,653 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_jpeg.h - * @author MCD Application Team - * @brief Header file of JPEG HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_JPEG_H -#define STM32F7xx_HAL_JPEG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (JPEG) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup JPEG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup JPEG_Exported_Types JPEG Exported Types - * @{ - */ - -/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition - * @brief JPEG encoding configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK - This parameter can be a value of @ref JPEG_ColorSpace */ - - uint32_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0 - This parameter can be a value of @ref JPEG_ChromaSubsampling */ - - uint32_t ImageHeight; /*!< Image height : number of lines */ - - uint32_t ImageWidth; /*!< Image width : number of pixels per line */ - - uint32_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */ - -} JPEG_ConfTypeDef; -/** - * @} - */ - -/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition - * @brief HAL JPEG State structure definition - * @{ - */ -typedef enum -{ - HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */ - HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */ - HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */ - HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */ - HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */ - HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */ - HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */ -} HAL_JPEG_STATETypeDef; - -/** - * @} - */ - - -/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition - * @brief JPEG handle Structure definition - * @{ - */ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) -typedef struct __JPEG_HandleTypeDef -#else -typedef struct -#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */ -{ - JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */ - - JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */ - - uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */ - - uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */ - - __IO uint32_t JpegInCount; /*!< Internal Counter of input data */ - - __IO uint32_t JpegOutCount; /*!< Internal Counter of output data */ - - uint32_t InDataLength; /*!< Input Buffer Length in Bytes */ - - uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */ - - DMA_HandleTypeDef *hdmain; /*!< JPEG In DMA handle parameters */ - - DMA_HandleTypeDef *hdmaout; /*!< JPEG Out DMA handle parameters */ - - uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */ - - uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */ - - uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */ - - uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */ - - uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */ - - HAL_LockTypeDef Lock; /*!< JPEG locking object */ - - __IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */ - - __IO uint32_t ErrorCode; /*!< JPEG Error code */ - - __IO uint32_t Context; /*!< JPEG Internal context */ - -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - void (*InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, - JPEG_ConfTypeDef *pInfo); /*!< JPEG Info ready callback */ - void (*EncodeCpltCallback)(struct __JPEG_HandleTypeDef - *hjpeg); /*!< JPEG Encode complete callback */ - void (*DecodeCpltCallback)(struct __JPEG_HandleTypeDef - *hjpeg); /*!< JPEG Decode complete callback */ - void (*ErrorCallback)(struct __JPEG_HandleTypeDef - *hjpeg); /*!< JPEG Error callback */ - void (*GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg, - uint32_t NbDecodedData); /*!< JPEG Get Data callback */ - void (*DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, - uint32_t OutDataLength); /*!< JPEG Data ready callback */ - - void (* MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg); /*!< JPEG Msp Init callback */ - void (* MspDeInitCallback)(struct __JPEG_HandleTypeDef - *hjpeg); /*!< JPEG Msp DeInit callback */ - - -#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */ - - -} JPEG_HandleTypeDef; -/** - * @} - */ - - -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) -/** @defgroup HAL_JPEG_Callback_ID_enumeration_definition HAL JPEG Callback ID enumeration definition - * @brief HAL JPEG Callback ID enumeration definition - * @{ - */ -typedef enum -{ - HAL_JPEG_ENCODE_CPLT_CB_ID = 0x01U, /*!< JPEG Encode Complete callback ID */ - HAL_JPEG_DECODE_CPLT_CB_ID = 0x02U, /*!< JPEG Decode Complete callback ID */ - HAL_JPEG_ERROR_CB_ID = 0x03U, /*!< JPEG Error callback ID */ - - HAL_JPEG_MSPINIT_CB_ID = 0x04U, /*!< JPEG MspInit callback ID */ - HAL_JPEG_MSPDEINIT_CB_ID = 0x05U /*!< JPEG MspDeInit callback ID */ - -} HAL_JPEG_CallbackIDTypeDef; -/** - * @} - */ - -/** @defgroup HAL_JPEG_Callback_pointer_definition HAL JPEG Callback pointer definition - * @brief HAL JPEG Callback pointer definition - * @{ - */ -typedef void (*pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg); /*!< pointer to a common JPEG callback function */ -typedef void (*pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, - JPEG_ConfTypeDef *pInfo); /*!< pointer to an Info ready JPEG callback function */ -typedef void (*pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, - uint32_t NbDecodedData); /*!< pointer to a Get data JPEG callback function */ -typedef void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, - uint32_t OutDataLength); /*!< pointer to a Data ready JPEG callback function */ -/** - * @} - */ - -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup JPEG_Exported_Constants JPEG Exported Constants - * @{ - */ - -/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition - * @brief JPEG Error Code definition - * @{ - */ - -#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */ -#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */ -#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ -#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) -#define HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */ -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size - * @brief JPEG Quantization Table Size - * @{ - */ -#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes */ -/** - * @} - */ - - -/** @defgroup JPEG_ColorSpace JPEG ColorSpace - * @brief JPEG Color Space - * @{ - */ -#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U) -#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0 -#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE - - -/** - * @} - */ - - -/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling - * @brief JPEG Chrominance Sampling - * @{ - */ -#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */ -#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */ -#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */ - -/** - * @} - */ - -/** @defgroup JPEG_ImageQuality JPEG Image Quality - * @brief JPEG Min and Max Image Quality - * @{ - */ -#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */ -#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */ - -/** - * @} - */ - -/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition - * @brief JPEG Interrupt definition - * @{ - */ -#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */ -#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */ -#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */ -#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */ -#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */ -#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */ -/** - * @} - */ - -/** @defgroup JPEG_Flag_definition JPEG Flag definition - * @brief JPEG Flags definition - * @{ - */ -#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */ -#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */ -#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */ -#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */ -#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */ -#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */ -#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/ - -#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/ -/** - * @} - */ - -/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition - * @brief JPEG process pause, resume definition - * @{ - */ -#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/ -#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/ -#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/ -/** - * @} - */ - -/** - * @} - */ -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup JPEG_Exported_Macros JPEG Exported Macros - * @{ - */ - -/** @brief Reset JPEG handle state - * @param __HANDLE__ specifies the JPEG handle. - * @retval None - */ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) -#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_JPEG_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0) -#else -#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET) -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - -/** - * @brief Enable the JPEG peripheral. - * @param __HANDLE__ specifies the JPEG handle. - * @retval None - */ -#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN) - -/** - * @brief Disable the JPEG peripheral. - * @param __HANDLE__ specifies the JPEG handle. - * @retval None - */ -#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN) - - -/** - * @brief Check the specified JPEG status flag. - * @param __HANDLE__ specifies the JPEG handle. - * @param __FLAG__ specifies the flag to check - * This parameter can be one of the following values: - * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag - * @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written - * @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold - * @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available - * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process - * and than last data has been sent to the output FIFO - * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers - * and the internal registers have been updated - * @arg JPEG_FLAG_COF : JPEG Codec operation on going flag - * - * @retval __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE) - */ - -#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__))) - -/** - * @brief Clear the specified JPEG status flag. - * @param __HANDLE__ specifies the JPEG handle. - * @param __FLAG__ specifies the flag to clear - * This parameter can be one of the following values: - * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process - * and than last data has been sent to the output FIFO - * @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers - * @retval None - */ - -#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF)))) - - -/** - * @brief Enable Interrupt. - * @param __HANDLE__ specifies the JPEG handle. - * @param __INTERRUPT__ specifies the interrupt to enable - * This parameter can be one of the following values: - * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt - * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt - * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt - * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt - * @arg JPEG_IT_EOC : End of Conversion Interrupt - * @arg JPEG_IT_HPD : Header Parsing Done Interrupt - * - * @retval No return - */ -#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) ) - -/** - * @brief Disable Interrupt. - * @param __HANDLE__ specifies the JPEG handle. - * @param __INTERRUPT__ specifies the interrupt to disable - * This parameter can be one of the following values: - * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt - * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt - * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt - * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt - * @arg JPEG_IT_EOC : End of Conversion Interrupt - * @arg JPEG_IT_HPD : Header Parsing Done Interrupt - * - * @note To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits - * located in the same IT enable register (CR register). - * @retval No return - */ -#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL) - - -/** - * @brief Get Interrupt state. - * @param __HANDLE__ specifies the JPEG handle. - * @param __INTERRUPT__ specifies the interrupt to check - * This parameter can be one of the following values: - * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt - * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt - * @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt - * @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt - * @arg JPEG_IT_EOC : End of Conversion Interrupt - * @arg JPEG_IT_HPD : Header Parsing Done Interrupt - * - * @retval returns The new state of __INTERRUPT__ (Enabled or disabled) - */ -#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup JPEG_Exported_Functions - * @{ - */ - -/** @addtogroup JPEG_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg); -HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg); -void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg); -void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg); - -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, - pJPEG_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg, - pJPEG_InfoReadyCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg); - -HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg); - -HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg, - pJPEG_DataReadyCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg); - -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup JPEG_Exported_Functions_Group2 - * @{ - */ -/* Encoding/Decoding Configuration functions ********************************/ -HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf); -HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo); -HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg); -HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg); -HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, - uint8_t *QTable2, uint8_t *QTable3); - -/** - * @} - */ - -/** @addtogroup JPEG_Exported_Functions_Group3 - * @{ - */ -/* JPEG processing functions **************************************/ -HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, - uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout); -HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, - uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout); -HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, - uint8_t *pDataOut, uint32_t OutDataLength); -HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, - uint8_t *pDataOutMCU, uint32_t OutDataLength); -HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, - uint8_t *pDataOut, uint32_t OutDataLength); -HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, - uint8_t *pDataOutMCU, uint32_t OutDataLength); -HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection); -HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection); -void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength); -void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength); -HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg); - -/** - * @} - */ - -/** @addtogroup JPEG_Exported_Functions_Group4 - * @{ - */ -/* JPEG Decode/Encode callback functions ********************************************************/ -void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo); -void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg); -void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg); -void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg); -void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData); -void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength); - -/** - * @} - */ - -/** @addtogroup JPEG_Exported_Functions_Group5 - * @{ - */ -/* JPEG IRQ handler management ******************************************************/ -void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg); - -/** - * @} - */ - -/** @addtogroup JPEG_Exported_Functions_Group6 - * @{ - */ -/* Peripheral State and Error functions ************************************************/ -HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg); -uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg); - -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup JPEG_Private_Types JPEG Private Types - * @{ - */ - -/** - * @} - */ - -/* Private defines -----------------------------------------------------------*/ -/** @defgroup JPEG_Private_Defines JPEG Private Defines - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup JPEG_Private_Variables JPEG Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup JPEG_Private_Constants JPEG Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup JPEG_Private_Macros JPEG Private Macros - * @{ - */ - -#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \ - ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \ - ((SUBSAMPLING) == JPEG_422_SUBSAMPLING)) - -#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX)) - -#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \ - ((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \ - ((COLORSPACE) == JPEG_CMYK_COLORSPACE)) - -#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \ - ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \ - ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT)) - -/** - * @} - */ - -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup JPEG_Private_Functions JPEG Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* JPEG */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_JPEG_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h deleted file mode 100644 index 4ace1e01..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_lptim.h +++ /dev/null @@ -1,830 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_lptim.h - * @author MCD Application Team - * @brief Header file of LPTIM HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_LPTIM_H -#define STM32F7xx_HAL_LPTIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined (LPTIM1) - -/** @addtogroup LPTIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup LPTIM_Exported_Types LPTIM Exported Types - * @{ - */ -#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR23 /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */ - -/** - * @brief LPTIM Clock configuration definition - */ -typedef struct -{ - uint32_t Source; /*!< Selects the clock source. - This parameter can be a value of @ref LPTIM_Clock_Source */ - - uint32_t Prescaler; /*!< Specifies the counter clock Prescaler. - This parameter can be a value of @ref LPTIM_Clock_Prescaler */ - -} LPTIM_ClockConfigTypeDef; - -/** - * @brief LPTIM Clock configuration definition - */ -typedef struct -{ - uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit - if the ULPTIM input is selected. - Note: This parameter is used only when Ultra low power clock source is used. - Note: If the polarity is configured on 'both edges', an auxiliary clock - (one of the Low power oscillator) must be active. - This parameter can be a value of @ref LPTIM_Clock_Polarity */ - - uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter. - Note: This parameter is used only when Ultra low power clock source is used. - This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ - -} LPTIM_ULPClockConfigTypeDef; - -/** - * @brief LPTIM Trigger configuration definition - */ -typedef struct -{ - uint32_t Source; /*!< Selects the Trigger source. - This parameter can be a value of @ref LPTIM_Trigger_Source */ - - uint32_t ActiveEdge; /*!< Selects the Trigger active edge. - Note: This parameter is used only when an external trigger is used. - This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */ - - uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter. - Note: This parameter is used only when an external trigger is used. - This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ -} LPTIM_TriggerConfigTypeDef; - -/** - * @brief LPTIM Initialization Structure definition - */ -typedef struct -{ - LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ - - LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ - - LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ - - uint32_t OutputPolarity; /*!< Specifies the Output polarity. - This parameter can be a value of @ref LPTIM_Output_Polarity */ - - uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare - values is done immediately or after the end of current period. - This parameter can be a value of @ref LPTIM_Updating_Mode */ - - uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event - or each external event. - This parameter can be a value of @ref LPTIM_Counter_Source */ -} LPTIM_InitTypeDef; - -/** - * @brief HAL LPTIM State structure definition - */ -typedef enum -{ - HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ - HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */ -} HAL_LPTIM_StateTypeDef; - -/** - * @brief LPTIM handle Structure definition - */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -typedef struct __LPTIM_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -{ - LPTIM_TypeDef *Instance; /*!< Register base address */ - - LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */ - - HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */ - - HAL_LockTypeDef Lock; /*!< LPTIM locking object */ - - __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */ - -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */ - void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */ - void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */ - void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */ - void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */ - void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */ - void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */ - void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */ - void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */ -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -} LPTIM_HandleTypeDef; - -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -/** - * @brief HAL LPTIM Callback ID enumeration definition - */ -typedef enum -{ - HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */ - HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */ - HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */ - HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */ - HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */ - HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */ - HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */ - HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */ - HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */ -} HAL_LPTIM_CallbackIDTypeDef; - -/** - * @brief HAL TIM Callback pointer definition - */ -typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */ - -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants - * @{ - */ - -/** @defgroup LPTIM_Clock_Source LPTIM Clock Source - * @{ - */ -#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U -#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL -/** - * @} - */ - -/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler - * @{ - */ -#define LPTIM_PRESCALER_DIV1 0x00000000U -#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 -#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 -#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1) -#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 -#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2) -#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2) -#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC -/** - * @} - */ - -/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity - * @{ - */ - -#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U -#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL -/** - * @} - */ - -/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time - * @{ - */ -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U -#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 -#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 -#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT -/** - * @} - */ - -/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity - * @{ - */ -#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U -#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 -#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 -/** - * @} - */ - -/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source - * @{ - */ -#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU -#define LPTIM_TRIGSOURCE_0 0x00000000U -#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0 -#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 -#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) -#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 -#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) -/** - * @} - */ - -/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity - * @{ - */ -#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0 -#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1 -#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN -/** - * @} - */ - -/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time - * @{ - */ -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U -#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 -#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 -#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT -/** - * @} - */ - -/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode - * @{ - */ - -#define LPTIM_UPDATE_IMMEDIATE 0x00000000U -#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD -/** - * @} - */ - -/** @defgroup LPTIM_Counter_Source LPTIM Counter Source - * @{ - */ - -#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U -#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE -/** - * @} - */ - -/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition - * @{ - */ - -#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN -#define LPTIM_FLAG_UP LPTIM_ISR_UP -#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK -#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK -#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG -#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM -#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM -/** - * @} - */ - -/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition - * @{ - */ -#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE -#define LPTIM_IT_UP LPTIM_IER_UPIE -#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE -#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE -#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE -#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE -#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros - * @{ - */ - -/** @brief Reset LPTIM handle state. - * @param __HANDLE__ LPTIM handle - * @retval None - */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET) -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - -/** - * @brief Enable the LPTIM peripheral. - * @param __HANDLE__ LPTIM handle - * @retval None - */ -#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE)) - -/** - * @brief Disable the LPTIM peripheral. - * @param __HANDLE__ LPTIM handle - * @note The following sequence is required to solve LPTIM disable HW limitation. - * Please check Errata Sheet ES0335 for more details under "MCU may remain - * stuck in LPTIM interrupt when entering Stop mode" section. - * @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to - * check for TIMEOUT. - * @retval None - */ -#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) - -/** - * @brief Start the LPTIM peripheral in Continuous mode. - * @param __HANDLE__ LPTIM handle - * @retval None - */ -#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT) -/** - * @brief Start the LPTIM peripheral in single mode. - * @param __HANDLE__ LPTIM handle - * @retval None - */ -#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT) - -/** - * @brief Write the passed parameter in the Autoreload register. - * @param __HANDLE__ LPTIM handle - * @param __VALUE__ Autoreload value - * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. - * @retval None - * @note The ARR register can only be modified when the LPTIM instance is enabled. - */ -#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) - -/** - * @brief Write the passed parameter in the Compare register. - * @param __HANDLE__ LPTIM handle - * @param __VALUE__ Compare value - * @retval None - * @note The CMP register can only be modified when the LPTIM instance is enabled. - */ -#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) - -/** - * @brief Check whether the specified LPTIM flag is set or not. - * @param __HANDLE__ LPTIM handle - * @param __FLAG__ LPTIM flag to check - * This parameter can be a value of: - * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. - * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. - * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. - * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. - * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. - * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. - * @arg LPTIM_FLAG_CMPM : Compare match Flag. - * @retval The state of the specified flag (SET or RESET). - */ -#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the specified LPTIM flag. - * @param __HANDLE__ LPTIM handle. - * @param __FLAG__ LPTIM flag to clear. - * This parameter can be a value of: - * @arg LPTIM_FLAG_DOWN : Counter direction change up Flag. - * @arg LPTIM_FLAG_UP : Counter direction change down to up Flag. - * @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag. - * @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag. - * @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag. - * @arg LPTIM_FLAG_ARRM : Autoreload match Flag. - * @arg LPTIM_FLAG_CMPM : Compare match Flag. - * @retval None. - */ -#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** - * @brief Enable the specified LPTIM interrupt. - * @param __HANDLE__ LPTIM handle. - * @param __INTERRUPT__ LPTIM interrupt to set. - * This parameter can be a value of: - * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. - * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. - * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. - * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. - * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. - * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. - * @arg LPTIM_IT_CMPM : Compare match Interrupt. - * @retval None. - * @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled. - */ -#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) - -/** - * @brief Disable the specified LPTIM interrupt. - * @param __HANDLE__ LPTIM handle. - * @param __INTERRUPT__ LPTIM interrupt to set. - * This parameter can be a value of: - * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. - * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. - * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. - * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. - * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. - * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. - * @arg LPTIM_IT_CMPM : Compare match Interrupt. - * @retval None. - * @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled. - */ -#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) - -/** - * @brief Check whether the specified LPTIM interrupt source is enabled or not. - * @param __HANDLE__ LPTIM handle. - * @param __INTERRUPT__ LPTIM interrupt to check. - * This parameter can be a value of: - * @arg LPTIM_IT_DOWN : Counter direction change up Interrupt. - * @arg LPTIM_IT_UP : Counter direction change down to up Interrupt. - * @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt. - * @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt. - * @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt. - * @arg LPTIM_IT_ARRM : Autoreload match Interrupt. - * @arg LPTIM_IT_CMPM : Compare match Interrupt. - * @retval Interrupt status. - */ - -#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\ - & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** - * @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line. - * @retval None - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR\ - |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line. - * @retval None - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR\ - &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable event on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR\ - |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable event on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR\ - &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR\ - |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR\ - &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR\ - |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR\ - &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)) - -/** - * @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\ - }while(0) - -/** - * @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\ - }while(0) - -/** - * @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR\ - & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Clear the LPTIM Wake-up Timer associated Exti line flag. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR\ - = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line. - * @retval None. - */ -#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER\ - |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions - * @{ - */ - -/** @addtogroup LPTIM_Exported_Functions_Group1 - * @brief Initialization and Configuration functions. - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); -HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); - -/* MSP functions *************************************************************/ -void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); -void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); -/** - * @} - */ - -/** @addtogroup LPTIM_Exported_Functions_Group2 - * @brief Start-Stop operation functions. - * @{ - */ -/* Start/Stop operation functions *********************************************/ -/* ################################# PWM Mode ################################*/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); -HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); -HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim); - -/* ############################# One Pulse Mode ##############################*/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim); - -/* ############################## Set once Mode ##############################*/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim); - -/* ############################### Encoder Mode ##############################*/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period); -HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); -HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim); - -/* ############################# Time out Mode ##############################*/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout); -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout); -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim); - -/* ############################## Counter Mode ###############################*/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period); -HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); -HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); -/** - * @} - */ - -/** @addtogroup LPTIM_Exported_Functions_Group3 - * @brief Read operation functions. - * @{ - */ -/* Reading operation functions ************************************************/ -uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim); -/** - * @} - */ - -/** @addtogroup LPTIM_Exported_Functions_Group4 - * @brief LPTIM IRQ handler and callback functions. - * @{ - */ -/* LPTIM IRQ functions *******************************************************/ -void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); - -/* CallBack functions ********************************************************/ -void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim); -void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim); -void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim); -void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim); -void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); -void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); -void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, - pLPTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup LPTIM_Group5 - * @brief Peripheral State functions. - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Types LPTIM Private Types - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Variables LPTIM Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Constants LPTIM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Macros LPTIM Private Macros - * @{ - */ - -#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ - ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) - - -#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \ - ((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) - -#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) - -#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \ - ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH)) - -#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ - ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ - ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ - ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) - -#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) - -#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ - ((__TRIG__) == LPTIM_TRIGSOURCE_5)) - -#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \ - ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \ - ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) - -#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \ - ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ - ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ - ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) - -#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ - ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) - -#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ - ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) - -#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) - -#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ - ((__PERIOD__) <= 0x0000FFFFUL)) - -#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Functions LPTIM Private Functions - * @{ - */ -void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); -/** - * @} - */ - -/** - * @} - */ - -#endif /* LPTIM1 */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_LPTIM_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h deleted file mode 100644 index 79828119..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc.h +++ /dev/null @@ -1,719 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_ltdc.h - * @author MCD Application Team - * @brief Header file of LTDC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_LTDC_H -#define STM32F7xx_HAL_LTDC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (LTDC) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup LTDC LTDC - * @brief LTDC HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup LTDC_Exported_Types LTDC Exported Types - * @{ - */ -#define MAX_LAYER 2U - -/** - * @brief LTDC color structure definition - */ -typedef struct -{ - uint8_t Blue; /*!< Configures the blue value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - - uint8_t Green; /*!< Configures the green value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - - uint8_t Red; /*!< Configures the red value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ - - uint8_t Reserved; /*!< Reserved 0xFF */ -} LTDC_ColorTypeDef; - -/** - * @brief LTDC Init structure definition - */ -typedef struct -{ - uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity. - This parameter can be one value of @ref LTDC_HS_POLARITY */ - - uint32_t VSPolarity; /*!< configures the vertical synchronization polarity. - This parameter can be one value of @ref LTDC_VS_POLARITY */ - - uint32_t DEPolarity; /*!< configures the data enable polarity. - This parameter can be one of value of @ref LTDC_DE_POLARITY */ - - uint32_t PCPolarity; /*!< configures the pixel clock polarity. - This parameter can be one of value of @ref LTDC_PC_POLARITY */ - - uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. - This parameter must be a number between - Min_Data = 0x000 and Max_Data = 0xFFF. */ - - uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. - This parameter must be a number between - Min_Data = 0x000 and Max_Data = 0x7FF. */ - - uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. - This parameter must be a number between - Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ - - uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. - This parameter must be a number between - Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ - - uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. - This parameter must be a number between - Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ - - uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. - This parameter must be a number between - Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ - - uint32_t TotalWidth; /*!< configures the total width. - This parameter must be a number between - Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ - - uint32_t TotalHeigh; /*!< configures the total height. - This parameter must be a number between - Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ - - LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ -} LTDC_InitTypeDef; - -/** - * @brief LTDC Layer structure definition - */ -typedef struct -{ - uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. - This parameter must be a number between - Min_Data = 0x000 and Max_Data = 0xFFF. */ - - uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. - This parameter must be a number between - Min_Data = 0x000 and Max_Data = 0xFFF. */ - - uint32_t WindowY0; /*!< Configures the Window vertical Start Position. - This parameter must be a number between - Min_Data = 0x000 and Max_Data = 0x7FF. */ - - uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. - This parameter must be a number between - Min_Data = 0x0000 and Max_Data = 0x7FF. */ - - uint32_t PixelFormat; /*!< Specifies the pixel format. - This parameter can be one of value of @ref LTDC_Pixelformat */ - - uint32_t Alpha; /*!< Specifies the constant alpha used for blending. - This parameter must be a number between - Min_Data = 0x00 and Max_Data = 0xFF. */ - - uint32_t Alpha0; /*!< Configures the default alpha value. - This parameter must be a number between - Min_Data = 0x00 and Max_Data = 0xFF. */ - - uint32_t BlendingFactor1; /*!< Select the blending factor 1. - This parameter can be one of value of @ref LTDC_BlendingFactor1 */ - - uint32_t BlendingFactor2; /*!< Select the blending factor 2. - This parameter can be one of value of @ref LTDC_BlendingFactor2 */ - - uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ - - uint32_t ImageWidth; /*!< Configures the color frame buffer line length. - This parameter must be a number between - Min_Data = 0x0000 and Max_Data = 0x1FFF. */ - - uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. - This parameter must be a number between - Min_Data = 0x000 and Max_Data = 0x7FF. */ - - LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ -} LTDC_LayerCfgTypeDef; - -/** - * @brief HAL LTDC State structures definition - */ -typedef enum -{ - HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */ - HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */ - HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */ - HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */ - HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */ -} HAL_LTDC_StateTypeDef; - -/** - * @brief LTDC handle Structure definition - */ -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -typedef struct __LTDC_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ -{ - LTDC_TypeDef *Instance; /*!< LTDC Register base address */ - - LTDC_InitTypeDef Init; /*!< LTDC parameters */ - - LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */ - - HAL_LockTypeDef Lock; /*!< LTDC Lock */ - - __IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */ - - __IO uint32_t ErrorCode; /*!< LTDC Error code */ - -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) - void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Line Event Callback */ - void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Reload Event Callback */ - void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Error Callback */ - - void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp Init callback */ - void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc); /*!< LTDC Msp DeInit callback */ - -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - - -} LTDC_HandleTypeDef; - -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL LTDC Callback ID enumeration definition - */ -typedef enum -{ - HAL_LTDC_MSPINIT_CB_ID = 0x00U, /*!< LTDC MspInit callback ID */ - HAL_LTDC_MSPDEINIT_CB_ID = 0x01U, /*!< LTDC MspDeInit callback ID */ - - HAL_LTDC_LINE_EVENT_CB_ID = 0x02U, /*!< LTDC Line Event Callback ID */ - HAL_LTDC_RELOAD_EVENT_CB_ID = 0x03U, /*!< LTDC Reload Callback ID */ - HAL_LTDC_ERROR_CB_ID = 0x04U /*!< LTDC Error Callback ID */ - -} HAL_LTDC_CallbackIDTypeDef; - -/** - * @brief HAL LTDC Callback pointer definition - */ -typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer to an LTDC callback function */ - -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup LTDC_Exported_Constants LTDC Exported Constants - * @{ - */ - -/** @defgroup LTDC_Error_Code LTDC Error Code - * @{ - */ -#define HAL_LTDC_ERROR_NONE 0x00000000U /*!< LTDC No error */ -#define HAL_LTDC_ERROR_TE 0x00000001U /*!< LTDC Transfer error */ -#define HAL_LTDC_ERROR_FU 0x00000002U /*!< LTDC FIFO Underrun */ -#define HAL_LTDC_ERROR_TIMEOUT 0x00000020U /*!< LTDC Timeout error */ -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -#define HAL_LTDC_ERROR_INVALID_CALLBACK 0x00000040U /*!< LTDC Invalid Callback error */ -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup LTDC_Layer LTDC Layer - * @{ - */ -#define LTDC_LAYER_1 0x00000000U /*!< LTDC Layer 1 */ -#define LTDC_LAYER_2 0x00000001U /*!< LTDC Layer 2 */ -/** - * @} - */ - -/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY - * @{ - */ -#define LTDC_HSPOLARITY_AL 0x00000000U /*!< Horizontal Synchronization is active low. */ -#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */ -/** - * @} - */ - -/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY - * @{ - */ -#define LTDC_VSPOLARITY_AL 0x00000000U /*!< Vertical Synchronization is active low. */ -#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */ -/** - * @} - */ - -/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY - * @{ - */ -#define LTDC_DEPOLARITY_AL 0x00000000U /*!< Data Enable, is active low. */ -#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */ -/** - * @} - */ - -/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY - * @{ - */ -#define LTDC_PCPOLARITY_IPC 0x00000000U /*!< input pixel clock. */ -#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */ -/** - * @} - */ - -/** @defgroup LTDC_SYNC LTDC SYNC - * @{ - */ -#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16U) /*!< Horizontal synchronization width. */ -#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */ -/** - * @} - */ - -/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR - * @{ - */ -#define LTDC_COLOR 0x000000FFU /*!< Color mask */ -/** - * @} - */ - -/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1 - * @{ - */ -#define LTDC_BLENDING_FACTOR1_CA 0x00000400U /*!< Blending factor : Cte Alpha */ -#define LTDC_BLENDING_FACTOR1_PAxCA 0x00000600U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ -/** - * @} - */ - -/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2 - * @{ - */ -#define LTDC_BLENDING_FACTOR2_CA 0x00000005U /*!< Blending factor : Cte Alpha */ -#define LTDC_BLENDING_FACTOR2_PAxCA 0x00000007U /*!< Blending factor : Cte Alpha x Pixel Alpha*/ -/** - * @} - */ - -/** @defgroup LTDC_Pixelformat LTDC Pixel format - * @{ - */ -#define LTDC_PIXEL_FORMAT_ARGB8888 0x00000000U /*!< ARGB8888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB888 0x00000001U /*!< RGB888 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_RGB565 0x00000002U /*!< RGB565 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB1555 0x00000003U /*!< ARGB1555 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_ARGB4444 0x00000004U /*!< ARGB4444 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_L8 0x00000005U /*!< L8 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL44 0x00000006U /*!< AL44 LTDC pixel format */ -#define LTDC_PIXEL_FORMAT_AL88 0x00000007U /*!< AL88 LTDC pixel format */ -/** - * @} - */ - -/** @defgroup LTDC_Alpha LTDC Alpha - * @{ - */ -#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Constant Alpha mask */ -/** - * @} - */ - -/** @defgroup LTDC_LAYER_Config LTDC LAYER Config - * @{ - */ -#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position */ -#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */ - -#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */ -#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */ -/** - * @} - */ - -/** @defgroup LTDC_Interrupts LTDC Interrupts - * @{ - */ -#define LTDC_IT_LI LTDC_IER_LIE /*!< LTDC Line Interrupt */ -#define LTDC_IT_FU LTDC_IER_FUIE /*!< LTDC FIFO Underrun Interrupt */ -#define LTDC_IT_TE LTDC_IER_TERRIE /*!< LTDC Transfer Error Interrupt */ -#define LTDC_IT_RR LTDC_IER_RRIE /*!< LTDC Register Reload Interrupt */ -/** - * @} - */ - -/** @defgroup LTDC_Flags LTDC Flags - * @{ - */ -#define LTDC_FLAG_LI LTDC_ISR_LIF /*!< LTDC Line Interrupt Flag */ -#define LTDC_FLAG_FU LTDC_ISR_FUIF /*!< LTDC FIFO Underrun interrupt Flag */ -#define LTDC_FLAG_TE LTDC_ISR_TERRIF /*!< LTDC Transfer Error interrupt Flag */ -#define LTDC_FLAG_RR LTDC_ISR_RRIF /*!< LTDC Register Reload interrupt Flag */ -/** - * @} - */ - -/** @defgroup LTDC_Reload_Type LTDC Reload Type - * @{ - */ -#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */ -#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup LTDC_Exported_Macros LTDC Exported Macros - * @{ - */ - -/** @brief Reset LTDC handle state. - * @param __HANDLE__ LTDC handle - * @retval None - */ -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) -#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */ - -/** - * @brief Enable the LTDC. - * @param __HANDLE__ LTDC handle - * @retval None. - */ -#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) - -/** - * @brief Disable the LTDC. - * @param __HANDLE__ LTDC handle - * @retval None. - */ -#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) - -/** - * @brief Enable the LTDC Layer. - * @param __HANDLE__ LTDC handle - * @param __LAYER__ Specify the layer to be enabled. - * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). - * @retval None. - */ -#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ - |= (uint32_t)LTDC_LxCR_LEN) - -/** - * @brief Disable the LTDC Layer. - * @param __HANDLE__ LTDC handle - * @param __LAYER__ Specify the layer to be disabled. - * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). - * @retval None. - */ -#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ - &= ~(uint32_t)LTDC_LxCR_LEN) - -/** - * @brief Reload immediately all LTDC Layers. - * @param __HANDLE__ LTDC handle - * @retval None. - */ -#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) - -/** - * @brief Reload during vertical blanking period all LTDC Layers. - * @param __HANDLE__ LTDC handle - * @retval None. - */ -#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR) - -/* Interrupt & Flag management */ -/** - * @brief Get the LTDC pending flags. - * @param __HANDLE__ LTDC handle - * @param __FLAG__ Get the specified flag. - * This parameter can be any combination of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag - * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag - * @arg LTDC_FLAG_TE: Transfer Error interrupt flag - * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) - -/** - * @brief Clears the LTDC pending flags. - * @param __HANDLE__ LTDC handle - * @param __FLAG__ Specify the flag to clear. - * This parameter can be any combination of the following values: - * @arg LTDC_FLAG_LI: Line Interrupt flag - * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag - * @arg LTDC_FLAG_TE: Transfer Error interrupt flag - * @arg LTDC_FLAG_RR: Register Reload Interrupt Flag - * @retval None - */ -#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** - * @brief Enables the specified LTDC interrupts. - * @param __HANDLE__ LTDC handle - * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag - * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag - * @arg LTDC_IT_TE: Transfer Error interrupt flag - * @arg LTDC_IT_RR: Register Reload Interrupt Flag - * @retval None - */ -#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) - -/** - * @brief Disables the specified LTDC interrupts. - * @param __HANDLE__ LTDC handle - * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag - * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag - * @arg LTDC_IT_TE: Transfer Error interrupt flag - * @arg LTDC_IT_RR: Register Reload Interrupt Flag - * @retval None - */ -#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified LTDC interrupt has occurred or not. - * @param __HANDLE__ LTDC handle - * @param __INTERRUPT__ Specify the LTDC interrupt source to check. - * This parameter can be one of the following values: - * @arg LTDC_IT_LI: Line Interrupt flag - * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag - * @arg LTDC_IT_TE: Transfer Error interrupt flag - * @arg LTDC_IT_RR: Register Reload Interrupt Flag - * @retval The state of INTERRUPT (SET or RESET). - */ -#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) -/** - * @} - */ - -/* Include LTDC HAL Extension module */ -#include "stm32f7xx_hal_ltdc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup LTDC_Exported_Functions - * @{ - */ -/** @addtogroup LTDC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc); -HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc); -void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc); -void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc); -void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); -void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); -void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, - pLTDC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup LTDC_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc); -/** - * @} - */ - -/** @addtogroup LTDC_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line); -HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); -HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); -HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, - uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, - uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, - uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx); - -/** - * @} - */ - -/** @addtogroup LTDC_Exported_Functions_Group4 - * @{ - */ -/* Peripheral State functions *************************************************/ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc); -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup LTDC_Private_Macros LTDC Private Macros - * @{ - */ -#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\ - ((uint32_t)((__HANDLE__)->Instance))\ - + 0x84U + (0x80U*(__LAYER__))))) -#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) -#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\ - || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) -#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\ - || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) -#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\ - || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) -#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\ - || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) -#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) -#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) -#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) -#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC) -#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC) -#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC) -#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC) -#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC) -#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR) -#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR) -#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR) -#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \ - ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) -#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ - ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) -#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) -#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) -#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) -#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) -#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION) -#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION) -#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER) -#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) -#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) -#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) -#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \ - ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup LTDC_Private_Functions LTDC Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* LTDC */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_LTDC_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h deleted file mode 100644 index e366677c..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_ltdc_ex.h +++ /dev/null @@ -1,83 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_ltdc_ex.h - * @author MCD Application Team - * @brief Header file of LTDC HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_LTDC_EX_H -#define STM32F7xx_HAL_LTDC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (LTDC) && defined (DSI) - -#include "stm32f7xx_hal_dsi.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup LTDCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup LTDCEx_Exported_Functions - * @{ - */ - -/** @addtogroup LTDCEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg); -HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* LTDC && DSI */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_LTDC_EX_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h deleted file mode 100644 index 83de7645..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h +++ /dev/null @@ -1,567 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_mdios.h - * @author MCD Application Team - * @brief Header file of MDIOS HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_MDIOS_H -#define __STM32F7xx_HAL_MDIOS_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (MDIOS) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup MDIOS - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup MDIOS_Exported_Types MDIOS Exported Types - * @{ - */ - -/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition - * @{ - */ - -typedef enum -{ - HAL_MDIOS_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ - HAL_MDIOS_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_MDIOS_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -}HAL_MDIOS_StateTypeDef; - -/** - * @} - */ - -/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition - * @{ - */ - -typedef struct -{ - uint32_t PortAddress; /*!< Specifies the MDIOS port address. - This parameter can be a value from 0 to 31 */ - uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled. - This parameter can be a value of @ref MDIOS_Preamble_Check */ -}MDIOS_InitTypeDef; - -/** - * @} - */ - -/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition - * @{ - */ - -#if ( USE_HAL_MDIOS_REGISTER_CALLBACKS == 1 ) -typedef struct __MDIOS_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ -{ - MDIOS_TypeDef *Instance; /*!< Register base address */ - - MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */ - - __IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */ - - HAL_LockTypeDef Lock; /*!< MDIOS Lock */ - -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) - - void (* WriteCpltCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Write Complete Callback */ - void (* ReadCpltCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Read Complete Callback */ - void (* ErrorCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Error Callback */ - void (* WakeUpCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Wake UP Callback */ - void (* MspInitCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Msp Init callback */ - void (* MspDeInitCallback) ( struct __MDIOS_HandleTypeDef * hmdios); /*!< MDIOS Msp DeInit callback */ - -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - -}MDIOS_HandleTypeDef; - -#if ( USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) -/** - * @brief HAL MDIOS Callback ID enumeration definition - */ -typedef enum -{ - HAL_MDIOS_MSPINIT_CB_ID = 0x00U, /*!< MDIOS MspInit callback ID */ - HAL_MDIOS_MSPDEINIT_CB_ID = 0x01U, /*!< MDIOS MspDeInit callback ID */ - HAL_MDIOS_WRITE_COMPLETE_CB_ID = 0x02U, /*!< MDIOS Write Complete Callback ID */ - HAL_MDIOS_READ_COMPLETE_CB_ID = 0x03U, /*!< MDIOS Read Complete Callback ID */ - HAL_MDIOS_ERROR_CB_ID = 0x04U, /*!< MDIOS Error Callback ID */ - HAL_MDIOS_WAKEUP_CB_ID = 0x05U /*!< MDIOS Wake UP Callback ID */ -}HAL_MDIOS_CallbackIDTypeDef; - -/** - * @brief HAL MDIOS Callback pointer definition - */ -typedef void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef * hmdios); /*!< pointer to an MDIOS callback function */ - -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants - * @{ - */ - -/** @defgroup MDIOS_Preamble_Check MDIOS Preamble Check - * @{ - */ -#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U) -#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC -/** - * @} - */ - -/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions - * @{ - */ -#define MDIOS_REG0 ((uint32_t)0x00000000U) -#define MDIOS_REG1 ((uint32_t)0x00000001U) -#define MDIOS_REG2 ((uint32_t)0x00000002U) -#define MDIOS_REG3 ((uint32_t)0x00000003U) -#define MDIOS_REG4 ((uint32_t)0x00000004U) -#define MDIOS_REG5 ((uint32_t)0x00000005U) -#define MDIOS_REG6 ((uint32_t)0x00000006U) -#define MDIOS_REG7 ((uint32_t)0x00000007U) -#define MDIOS_REG8 ((uint32_t)0x00000008U) -#define MDIOS_REG9 ((uint32_t)0x00000009U) -#define MDIOS_REG10 ((uint32_t)0x0000000AU) -#define MDIOS_REG11 ((uint32_t)0x0000000BU) -#define MDIOS_REG12 ((uint32_t)0x0000000CU) -#define MDIOS_REG13 ((uint32_t)0x0000000DU) -#define MDIOS_REG14 ((uint32_t)0x0000000EU) -#define MDIOS_REG15 ((uint32_t)0x0000000FU) -#define MDIOS_REG16 ((uint32_t)0x00000010U) -#define MDIOS_REG17 ((uint32_t)0x00000011U) -#define MDIOS_REG18 ((uint32_t)0x00000012U) -#define MDIOS_REG19 ((uint32_t)0x00000013U) -#define MDIOS_REG20 ((uint32_t)0x00000014U) -#define MDIOS_REG21 ((uint32_t)0x00000015U) -#define MDIOS_REG22 ((uint32_t)0x00000016U) -#define MDIOS_REG23 ((uint32_t)0x00000017U) -#define MDIOS_REG24 ((uint32_t)0x00000018U) -#define MDIOS_REG25 ((uint32_t)0x00000019U) -#define MDIOS_REG26 ((uint32_t)0x0000001AU) -#define MDIOS_REG27 ((uint32_t)0x0000001BU) -#define MDIOS_REG28 ((uint32_t)0x0000001CU) -#define MDIOS_REG29 ((uint32_t)0x0000001DU) -#define MDIOS_REG30 ((uint32_t)0x0000001EU) -#define MDIOS_REG31 ((uint32_t)0x0000001FU) -/** - * @} - */ - -/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags - * @{ - */ -#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U) -#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U) -#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U) -#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U) -#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U) -#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U) -#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U) -#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U) -#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U) -#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U) -#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U) -#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U) -#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U) -#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U) -#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U) -#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U) -#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U) -#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U) -#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U) -#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U) -#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U) -#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U) -#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U) -#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U) -#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U) -#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U) -#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U) -#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U) -#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U) -#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U) -#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U) -#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U) -#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU) -/** - * @} - */ - -/** @defgroup MDIOS_Interrupt_sources Interrupt Sources - * @{ - */ -#define MDIOS_IT_WRITE MDIOS_CR_WRIE -#define MDIOS_IT_READ MDIOS_CR_RDIE -#define MDIOS_IT_ERROR MDIOS_CR_EIE -/** - * @} - */ - -/** @defgroup MDIOS_Interrupt_Flags MDIOS Interrupt Flags - * @{ - */ -#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF -#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF -#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF -/** - * @} - */ - - /** @defgroup MDIOS_Wakeup_Line MDIOS Wakeup Line - * @{ - */ -#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x01000000) /* !< EXTI Line 24 */ -/** - * @} - */ - -/** - * @} - */ -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros - * @{ - */ - -/** @brief Reset MDIOS handle state - * @param __HANDLE__ MDIOS handle. - * @retval None - */ -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) -#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_MDIOS_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET) -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - -/** - * @brief Enable/Disable the MDIOS peripheral. - * @param __HANDLE__ specifies the MDIOS handle. - * @retval None - */ -#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN) -#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN) - - -/** - * @brief Enable the MDIOS device interrupt. - * @param __HANDLE__ specifies the MDIOS handle. - * @param __INTERRUPT__ specifies the MDIOS interrupt sources to be enabled. - * This parameter can be one or a combination of the following values: - * @arg MDIOS_IT_WRITE: Register write interrupt - * @arg MDIOS_IT_READ: Register read interrupt - * @arg MDIOS_IT_ERROR: Error interrupt - * @retval None - */ -#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the MDIOS device interrupt. - * @param __HANDLE__ specifies the MDIOS handle. - * @param __INTERRUPT__ specifies the MDIOS interrupt sources to be disabled. - * This parameter can be one or a combination of the following values: - * @arg MDIOS_IT_WRITE: Register write interrupt - * @arg MDIOS_IT_READ: Register read interrupt - * @arg MDIOS_IT_ERROR: Error interrupt - * @retval None - */ -#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** @brief Set MDIOS slave get write register flag - * @param __HANDLE__ specifies the MDIOS handle. - * @param __FLAG__ specifies the write register flag - * @retval The state of write flag - */ -#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__)) - -/** @brief MDIOS slave get read register flag - * @param __HANDLE__ specifies the MDIOS handle. - * @param __FLAG__ specifies the read register flag - * @retval The state of read flag - */ -#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__)) - -/** @brief MDIOS slave get interrupt - * @param __HANDLE__ specifies the MDIOS handle. - * @param __FLAG__ specifies the Error flag. - * This parameter can be one or a combination of the following values: - * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt - * @arg MDIOS_START_ERROR_FLAG: Register read interrupt - * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt - * @retval The state of the error flag - */ -#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) - -/** @brief MDIOS slave clear interrupt - * @param __HANDLE__ specifies the MDIOS handle. - * @param __FLAG__ specifies the Error flag. - * This parameter can be one or a combination of the following values: - * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt - * @arg MDIOS_START_ERROR_FLAG: Register read interrupt - * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt - * @retval none - */ -#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__) - -/** - * @brief Checks whether the specified MDIOS interrupt is set or not. - * @param __HANDLE__ specifies the MDIOS handle. - * @param __INTERRUPT__ specifies the MDIOS interrupt sources - * This parameter can be one or a combination of the following values: - * @arg MDIOS_IT_WRITE: Register write interrupt - * @arg MDIOS_IT_READ: Register read interrupt - * @arg MDIOS_IT_ERROR: Error interrupt - * @retval The state of the interrupt source - */ -#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) - -/** - * @brief Enable the MDIOS WAKEUP Exti Line. - * @retval None. - */ -#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT() (EXTI->IMR |= (MDIOS_WAKEUP_EXTI_LINE)) - -/** - * @brief Disable the MDIOS WAKEUP Exti Line. - * @retval None. - */ -#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(MDIOS_WAKEUP_EXTI_LINE)) - -/** - * @brief Enable event on MDIOS WAKEUP Exti Line. - * @retval None. - */ -#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_EVENT() (EXTI->EMR |= (MDIOS_WAKEUP_EXTI_LINE)) - -/** - * @brief Disable event on MDIOS WAKEUP Exti Line. - * @retval None. - */ -#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(MDIOS_WAKEUP_EXTI_LINE)) - -/** - * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not. - * @retval EXTI MDIOS WAKEUP Line Status. - */ -#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() (EXTI->PR & (MDIOS_WAKEUP_EXTI_LINE)) - -/** - * @brief Clear the MDIOS WAKEUP Exti flag. - * @retval None. - */ -#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG() (EXTI->PR = (MDIOS_WAKEUP_EXTI_LINE)) - -/** - * @brief Enables rising edge trigger to the MDIOS External interrupt line. - * @retval None - */ -#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE - -/** - * @brief Disables the rising edge trigger to the MDIOS External interrupt line. - * @retval None - */ -#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) - -/** - * @brief Enables falling edge trigger to the MDIOS External interrupt line. - * @retval None - */ -#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (MDIOS_WAKEUP_EXTI_LINE) - -/** - * @brief Disables falling edge trigger to the MDIOS External interrupt line. - * @retval None - */ -#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) - -/** - * @brief Enables rising/falling edge trigger to the MDIOS External interrupt line. - * @retval None - */ -#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE;\ - EXTI->FTSR |= MDIOS_WAKEUP_EXTI_LINE - -/** - * @brief Disables rising/falling edge trigger to the MDIOS External interrupt line. - * @retval None - */ -#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE);\ - EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE) -/** - * @brief Generates a Software interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (MDIOS_WAKEUP_EXTI_LINE)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions - * @{ - */ - -/** @addtogroup MDIOS_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios); -HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios); -void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios); -void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios); -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup MDIOS_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data); -HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData); - -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios); -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios); -HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); -HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum); - -HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios); -void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios); -void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios); -void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios); -void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios); -void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios); -/** - * @} - */ - -/** @addtogroup MDIOS_Exported_Functions_Group3 - * @{ - */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios); -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup MDIOS_Private_Types MDIOS Private Types - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup MDIOS_Private_Variables MDIOS Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup MDIOS_Private_Constants MDIOS Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup MDIOS_Private_Macros MDIOS Private Macros - * @{ - */ - -#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32) - -#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32) - -#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \ - ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE)) - - /** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup MDIOS_Private_Functions MDIOS Private Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* MDIOS */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_MDIOS_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h index 60f769da..fc60b9e8 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h @@ -1,747 +1,747 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_mmc.h - * @author MCD Application Team - * @brief Header file of MMC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_MMC_H -#define STM32F7xx_HAL_MMC_H - -#if defined(SDMMC1) - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_sdmmc.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup MMC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup MMC_Exported_Types MMC Exported Types - * @{ - */ - -/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure - * @{ - */ -typedef enum -{ - HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */ - HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */ - HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */ - HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */ - HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */ - HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */ - HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */ - HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */ -}HAL_MMC_StateTypeDef; -/** - * @} - */ - -/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure - * @{ - */ -typedef uint32_t HAL_MMC_CardStateTypeDef; - -#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */ -#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ -#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ -#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ -#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ -#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ -#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ -#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ -#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */ -/** - * @} - */ - -/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition - * @{ - */ -#define MMC_InitTypeDef SDMMC_InitTypeDef -#define MMC_TypeDef SDMMC_TypeDef - -/** - * @brief MMC Card Information Structure definition - */ -typedef struct -{ - uint32_t CardType; /*!< Specifies the card Type */ - - uint32_t Class; /*!< Specifies the class of the card class */ - - uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ - - uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ - - uint32_t BlockSize; /*!< Specifies one block size in bytes */ - - uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ - - uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ - -}HAL_MMC_CardInfoTypeDef; - -/** - * @brief MMC handle Structure definition - */ -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -typedef struct __MMC_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ -{ - MMC_TypeDef *Instance; /*!< MMC registers base address */ - - MMC_InitTypeDef Init; /*!< MMC required parameters */ - - HAL_LockTypeDef Lock; /*!< MMC locking object */ - - uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ - - uint32_t TxXferSize; /*!< MMC Tx Transfer size */ - - uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ - - uint32_t RxXferSize; /*!< MMC Rx Transfer size */ - - __IO uint32_t Context; /*!< MMC transfer context */ - - __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ - - __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ - - DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */ - - DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ - - HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ - - uint32_t CSD[4U]; /*!< MMC card specific data table */ - - uint32_t CID[4U]; /*!< MMC card identification number table */ - - uint32_t Ext_CSD[128]; - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc); - - void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc); - void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc); -#endif -}MMC_HandleTypeDef; - -/** - * @} - */ - -/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register - * @{ - */ -typedef struct -{ - __IO uint8_t CSDStruct; /*!< CSD structure */ - __IO uint8_t SysSpecVersion; /*!< System specification version */ - __IO uint8_t Reserved1; /*!< Reserved */ - __IO uint8_t TAAC; /*!< Data read access time 1 */ - __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ - __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - __IO uint16_t CardComdClasses; /*!< Card command classes */ - __IO uint8_t RdBlockLen; /*!< Max. read data block length */ - __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ - __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ - __IO uint8_t DSRImpl; /*!< DSR implemented */ - __IO uint8_t Reserved2; /*!< Reserved */ - __IO uint32_t DeviceSize; /*!< Device Size */ - __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ - __IO uint8_t EraseGrSize; /*!< Erase group size */ - __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ - __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ - __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - __IO uint8_t WrSpeedFact; /*!< Write speed factor */ - __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - __IO uint8_t Reserved3; /*!< Reserved */ - __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGroup; /*!< File format group */ - __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ - __IO uint8_t PermWrProtect; /*!< Permanent write protection */ - __IO uint8_t TempWrProtect; /*!< Temporary write protection */ - __IO uint8_t FileFormat; /*!< File format */ - __IO uint8_t ECC; /*!< ECC code */ - __IO uint8_t CSD_CRC; /*!< CSD CRC */ - __IO uint8_t Reserved4; /*!< Always 1 */ - -}HAL_MMC_CardCSDTypeDef; -/** - * @} - */ - -/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register - * @{ - */ -typedef struct -{ - __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ - __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ - __IO uint32_t ProdName1; /*!< Product Name part1 */ - __IO uint8_t ProdName2; /*!< Product Name part2 */ - __IO uint8_t ProdRev; /*!< Product Revision */ - __IO uint32_t ProdSN; /*!< Product Serial Number */ - __IO uint8_t Reserved1; /*!< Reserved1 */ - __IO uint16_t ManufactDate; /*!< Manufacturing Date */ - __IO uint8_t CID_CRC; /*!< CID CRC */ - __IO uint8_t Reserved2; /*!< Always 1 */ - -}HAL_MMC_CardCIDTypeDef; -/** - * @} - */ - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition - * @{ - */ -typedef enum -{ - HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */ - HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */ - HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */ - HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */ - - HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ - HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ -}HAL_MMC_CallbackIDTypeDef; -/** - * @} - */ - -/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition - * @{ - */ -typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); -/** - * @} - */ -#endif -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup MMC_Exported_Constants Exported Constants - * @{ - */ - -#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */ - -/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition - * @{ - */ -#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ -#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ -#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ -#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ -#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ -#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ -#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ -#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ -#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ -#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ -#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ -#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ -#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ -#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ -#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ -#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ -#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ -#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ -#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ -#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ -#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ -#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ -#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ -#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ -#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ -#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ -#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ -#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ -#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ -#endif -/** - * @} - */ - -/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration - * @{ - */ -#define MMC_CONTEXT_NONE 0x00000000U /*!< None */ -#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ -#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ -#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ -#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ -#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ -#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ - -/** - * @} - */ - -/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode - * @{ - */ -/** - * @brief - */ -#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ -#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ -#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ -#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ -#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ -#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ -#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U -/** - * @} - */ - -/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards - * @{ - */ -#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */ -#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup MMC_Exported_macros MMC Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -/** @brief Reset MMC handle state. - * @param __HANDLE__ : MMC handle. - * @retval None - */ -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) -#endif - -/** - * @brief Enable the MMC device. - * @retval None - */ -#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) - -/** - * @brief Disable the MMC device. - * @retval None - */ -#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) - -/** - * @brief Enable the SDMMC DMA transfer. - * @retval None - */ -#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) - -/** - * @brief Disable the SDMMC DMA transfer. - * @retval None - */ -#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) - -/** - * @brief Enable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt - * @retval None - */ -#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @brief Disable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt - * @retval None - */ -#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @brief Check whether the specified MMC flag is set or not. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_CMDACT: Command transfer in progress - * @arg SDMMC_FLAG_TXACT: Data transmit in progress - * @arg SDMMC_FLAG_RXACT: Data receive in progress - * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full - * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received - * @retval The new state of MMC FLAG (SET or RESET). - */ -#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) - -/** - * @brief Clear the MMC's pending flags. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received - * @retval None - */ -#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) - -/** - * @brief Check whether the specified MMC interrupt has occurred or not. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. - * This parameter can be one of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt - * @retval The new state of MMC IT (SET or RESET). - */ -#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @brief Clear the MMC's interrupt pending bits. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt - * @retval None - */ -#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup MMC_Exported_Functions MMC Exported Functions - * @{ - */ - -/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); -void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); -void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); - -/** - * @} - */ - -/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); -/* Non-Blocking mode: IT */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); - -void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); - -/* Callback in non blocking modes (DMA) */ -void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); -void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); -void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); -void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -/* MMC callback registering/unregistering */ -HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); -#endif -/** - * @} - */ - -/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); -/** - * @} - */ - -/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions - * @{ - */ -HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); -HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); -HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); -/** - * @} - */ - -/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions - * @{ - */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); -/** - * @} - */ - -/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management - * @{ - */ -HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup MMC_Private_Types MMC Private Types - * @{ - */ - -/** - * @} - */ - -/* Private defines -----------------------------------------------------------*/ -/** @defgroup MMC_Private_Defines MMC Private Defines - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup MMC_Private_Variables MMC Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup MMC_Private_Constants MMC Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup MMC_Private_Macros MMC Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup MMC_Private_Functions MMC Private Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* SDMMC1 */ - -#endif /* STM32F7xx_HAL_MMC_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_mmc.h + * @author MCD Application Team + * @brief Header file of MMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_MMC_H +#define STM32F7xx_HAL_MMC_H + +#if defined(SDMMC1) + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_sdmmc.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup MMC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_Types MMC Exported Types + * @{ + */ + +/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure + * @{ + */ +typedef enum +{ + HAL_MMC_STATE_RESET = 0x00000000U, /*!< MMC not yet initialized or disabled */ + HAL_MMC_STATE_READY = 0x00000001U, /*!< MMC initialized and ready for use */ + HAL_MMC_STATE_TIMEOUT = 0x00000002U, /*!< MMC Timeout state */ + HAL_MMC_STATE_BUSY = 0x00000003U, /*!< MMC process ongoing */ + HAL_MMC_STATE_PROGRAMMING = 0x00000004U, /*!< MMC Programming State */ + HAL_MMC_STATE_RECEIVING = 0x00000005U, /*!< MMC Receinving State */ + HAL_MMC_STATE_TRANSFER = 0x00000006U, /*!< MMC Transfer State */ + HAL_MMC_STATE_ERROR = 0x0000000FU /*!< MMC is in error state */ +}HAL_MMC_StateTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure + * @{ + */ +typedef uint32_t HAL_MMC_CardStateTypeDef; + +#define HAL_MMC_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_MMC_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_MMC_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_MMC_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_MMC_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_MMC_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_MMC_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_MMC_CARD_ERROR 0x000000FFU /*!< Card response Error */ +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition + * @{ + */ +#define MMC_InitTypeDef SDMMC_InitTypeDef +#define MMC_TypeDef SDMMC_TypeDef + +/** + * @brief MMC Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_MMC_CardInfoTypeDef; + +/** + * @brief MMC handle Structure definition + */ +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +typedef struct __MMC_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ +{ + MMC_TypeDef *Instance; /*!< MMC registers base address */ + + MMC_InitTypeDef Init; /*!< MMC required parameters */ + + HAL_LockTypeDef Lock; /*!< MMC locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< MMC Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< MMC Rx Transfer size */ + + __IO uint32_t Context; /*!< MMC transfer context */ + + __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */ + + __IO uint32_t ErrorCode; /*!< MMC Card Error codes */ + + DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */ + + DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */ + + HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */ + + uint32_t CSD[4U]; /*!< MMC card specific data table */ + + uint32_t CID[4U]; /*!< MMC card identification number table */ + + uint32_t Ext_CSD[128]; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* ErrorCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* AbortCpltCallback) (struct __MMC_HandleTypeDef *hmmc); + + void (* MspInitCallback) (struct __MMC_HandleTypeDef *hmmc); + void (* MspDeInitCallback) (struct __MMC_HandleTypeDef *hmmc); +#endif +}MMC_HandleTypeDef; + +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGroup; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ + +}HAL_MMC_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +}HAL_MMC_CardCIDTypeDef; +/** + * @} + */ + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_MMC_TX_CPLT_CB_ID = 0x00U, /*!< MMC Tx Complete Callback ID */ + HAL_MMC_RX_CPLT_CB_ID = 0x01U, /*!< MMC Rx Complete Callback ID */ + HAL_MMC_ERROR_CB_ID = 0x02U, /*!< MMC Error Callback ID */ + HAL_MMC_ABORT_CB_ID = 0x03U, /*!< MMC Abort Callback ID */ + + HAL_MMC_MSP_INIT_CB_ID = 0x10U, /*!< MMC MspInit Callback ID */ + HAL_MMC_MSP_DEINIT_CB_ID = 0x11U /*!< MMC MspDeInit Callback ID */ +}HAL_MMC_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition + * @{ + */ +typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); +/** + * @} + */ +#endif +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Constants Exported Constants + * @{ + */ + +#define MMC_BLOCKSIZE 512U /*!< Block size is 512 bytes */ + +/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition + * @{ + */ +#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#define HAL_MMC_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration + * @{ + */ +#define MMC_CONTEXT_NONE 0x00000000U /*!< None */ +#define MMC_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ +#define MMC_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ +#define MMC_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ +#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ +#define MMC_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ +#define MMC_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ + +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode + * @{ + */ +/** + * @brief + */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ +#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ +#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ +#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ +#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ +#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U +/** + * @} + */ + +/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards + * @{ + */ +#define MMC_LOW_CAPACITY_CARD 0x00000000U /*!< MMC Card Capacity <=2Gbytes */ +#define MMC_HIGH_CAPACITY_CARD 0x00000001U /*!< MMC Card Capacity >2Gbytes and <2Tbytes */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup MMC_Exported_macros MMC Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** @brief Reset MMC handle state. + * @param __HANDLE__ : MMC handle. + * @retval None + */ +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_MMC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MMC_STATE_RESET) +#endif + +/** + * @brief Enable the MMC device. + * @retval None + */ +#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the MMC device. + * @retval None + */ +#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the MMC device interrupt. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified MMC flag is set or not. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_CMDACT: Command transfer in progress + * @arg SDMMC_FLAG_TXACT: Data transmit in progress + * @arg SDMMC_FLAG_RXACT: Data receive in progress + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @retval The new state of MMC FLAG (SET or RESET). + */ +#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the MMC's pending flags. + * @param __HANDLE__: MMC Handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received + * @retval None + */ +#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified MMC interrupt has occurred or not. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval The new state of MMC IT (SET or RESET). + */ +#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the MMC's interrupt pending bits. + * @param __HANDLE__: MMC Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt + * @retval None + */ +#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup MMC_Exported_Functions MMC Exported Functions + * @{ + */ + +/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc); +void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc); + +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); + +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc); + +/* Callback in non blocking modes (DMA) */ +void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc); +void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc); + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/* MMC callback registering/unregistering */ +HAL_StatusTypeDef HAL_MMC_RegisterCallback (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId); +#endif +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions + * @{ + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc); +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup MMC_Private_Types MMC Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup MMC_Private_Defines MMC Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Variables MMC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Constants MMC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup MMC_Private_Macros MMC Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SDMMC1 */ + +#endif /* STM32F7xx_HAL_MMC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h deleted file mode 100644 index e8a6893b..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h +++ /dev/null @@ -1,376 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_nand.h - * @author MCD Application Team - * @brief Header file of NAND HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_NAND_H -#define STM32F7xx_HAL_NAND_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_fmc.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup NAND - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup NAND_Exported_Types NAND Exported Types - * @{ - */ - -/** - * @brief HAL NAND State structures definition - */ -typedef enum -{ - HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ - HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ - HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ - HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ -} HAL_NAND_StateTypeDef; - -/** - * @brief NAND Memory electronic signature Structure definition - */ -typedef struct -{ - /*State = HAL_NAND_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) -#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup NAND_Exported_Functions NAND Exported Functions - * @{ - */ - -/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, - FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); -HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); - -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); - -HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); - -void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); -void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); -void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); - -/** - * @} - */ - -/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions - * @{ - */ - -/* IO operation functions ****************************************************/ -HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); - -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - const uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - const uint16_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress); - -uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); - -#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) -/* NAND callback registering/unregistering */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, - pNAND_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); -#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* NAND Control functions ****************************************************/ -HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); - -/** - * @} - */ - -/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions - * @{ - */ -/* NAND State functions *******************************************************/ -HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand); -uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup NAND_Private_Constants NAND Private Constants - * @{ - */ -#define NAND_DEVICE 0x80000000UL -#define NAND_WRITE_TIMEOUT 0x01000000UL - -#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ -#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ - -#define NAND_CMD_AREA_A ((uint8_t)0x00) -#define NAND_CMD_AREA_B ((uint8_t)0x01) -#define NAND_CMD_AREA_C ((uint8_t)0x50) -#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) - -#define NAND_CMD_WRITE0 ((uint8_t)0x80) -#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) -#define NAND_CMD_ERASE0 ((uint8_t)0x60) -#define NAND_CMD_ERASE1 ((uint8_t)0xD0) -#define NAND_CMD_READID ((uint8_t)0x90) -#define NAND_CMD_STATUS ((uint8_t)0x70) -#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) -#define NAND_CMD_RESET ((uint8_t)0xFF) - -/* NAND memory status */ -#define NAND_VALID_ADDRESS 0x00000100UL -#define NAND_INVALID_ADDRESS 0x00000200UL -#define NAND_TIMEOUT_ERROR 0x00000400UL -#define NAND_BUSY 0x00000000UL -#define NAND_ERROR 0x00000001UL -#define NAND_READY 0x00000040UL -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup NAND_Private_Macros NAND Private Macros - * @{ - */ - -/** - * @brief NAND memory address computation. - * @param __ADDRESS__ NAND memory address. - * @param __HANDLE__ NAND handle. - * @retval NAND Raw address value - */ -#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + \ - (((__ADDRESS__)->Plane) * \ - ((__HANDLE__)->Config.PlaneSize))) * \ - ((__HANDLE__)->Config.BlockSize))) - -/** - * @brief NAND memory Column address computation. - * @param __HANDLE__ NAND handle. - * @retval NAND Raw address value - */ -#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) - -/** - * @brief NAND memory address cycling. - * @param __ADDRESS__ NAND memory address. - * @retval NAND address cycling value. - */ -#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ -#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ -#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ -#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ - -/** - * @brief NAND memory Columns cycling. - * @param __ADDRESS__ NAND memory address. - * @retval NAND Column address cycling value. - */ -#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ -#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_NAND_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h deleted file mode 100644 index e30b2730..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h +++ /dev/null @@ -1,324 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_nor.h - * @author MCD Application Team - * @brief Header file of NOR HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_NOR_H -#define STM32F7xx_HAL_NOR_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_fmc.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup NOR - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ -/** @defgroup NOR_Exported_Types NOR Exported Types - * @{ - */ - -/** - * @brief HAL SRAM State structures definition - */ -typedef enum -{ - HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ - HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ - HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ - HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ - HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ -} HAL_NOR_StateTypeDef; - -/** - * @brief FMC NOR Status typedef - */ -typedef enum -{ - HAL_NOR_STATUS_SUCCESS = 0U, - HAL_NOR_STATUS_ONGOING, - HAL_NOR_STATUS_ERROR, - HAL_NOR_STATUS_TIMEOUT -} HAL_NOR_StatusTypeDef; - -/** - * @brief FMC NOR ID typedef - */ -typedef struct -{ - uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ - - uint16_t Device_Code1; - - uint16_t Device_Code2; - - uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. - These codes can be accessed by performing read operations with specific - control signals and addresses set.They can also be accessed by issuing - an Auto Select command */ -} NOR_IDTypeDef; - -/** - * @brief FMC NOR CFI typedef - */ -typedef struct -{ - /*!< Defines the information stored in the memory's Common flash interface - which contains a description of various electrical and timing parameters, - density information and functions supported by the memory */ - - uint16_t CFI_1; - - uint16_t CFI_2; - - uint16_t CFI_3; - - uint16_t CFI_4; -} NOR_CFITypeDef; - -/** - * @brief NOR handle Structure definition - */ -#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) -typedef struct __NOR_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ - -{ - FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - - FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ - - FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ - - HAL_LockTypeDef Lock; /*!< NOR locking object */ - - __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ - - uint32_t CommandSet; /*!< NOR algorithm command set and control */ - -#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ - void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ -#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ -} NOR_HandleTypeDef; - -#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) -/** - * @brief HAL NOR Callback ID enumeration definition - */ -typedef enum -{ - HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ - HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ -} HAL_NOR_CallbackIDTypeDef; - -/** - * @brief HAL NOR Callback pointer definition - */ -typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); -#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup NOR_Exported_Macros NOR Exported Macros - * @{ - */ -/** @brief Reset NOR handle state - * @param __HANDLE__ specifies the NOR handle. - * @retval None - */ -#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) -#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_NOR_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) -#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup NOR_Exported_Functions NOR Exported Functions - * @{ - */ - -/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, - FMC_NORSRAM_TimingTypeDef *ExtTiming); -HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); -void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); -void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); -void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); -/** - * @} - */ - -/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions - * @{ - */ - -/* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); -HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); -HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); -HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); - -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, - uint32_t uwBufferSize); -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, - uint32_t uwBufferSize); - -HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); -HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); -HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); - -#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) -/* NOR callback registering/unregistering */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, - pNOR_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); -#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions - * @{ - */ - -/* NOR Control functions *****************************************************/ -HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); -HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); -/** - * @} - */ - -/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions - * @{ - */ - -/* NOR State functions ********************************************************/ -HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor); -HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup NOR_Private_Constants NOR Private Constants - * @{ - */ -/* NOR device IDs addresses */ -#define MC_ADDRESS ((uint16_t)0x0000) -#define DEVICE_CODE1_ADDR ((uint16_t)0x0001) -#define DEVICE_CODE2_ADDR ((uint16_t)0x000E) -#define DEVICE_CODE3_ADDR ((uint16_t)0x000F) - -/* NOR CFI IDs addresses */ -#define CFI1_ADDRESS ((uint16_t)0x0061) -#define CFI2_ADDRESS ((uint16_t)0x0062) -#define CFI3_ADDRESS ((uint16_t)0x0063) -#define CFI4_ADDRESS ((uint16_t)0x0064) - -/* NOR operation wait timeout */ -#define NOR_TMEOUT ((uint16_t)0xFFFF) - -/* NOR memory data width */ -#define NOR_MEMORY_8B ((uint8_t)0x00) -#define NOR_MEMORY_16B ((uint8_t)0x01) - -/* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 (0x60000000U) -#define NOR_MEMORY_ADRESS2 (0x64000000U) -#define NOR_MEMORY_ADRESS3 (0x68000000U) -#define NOR_MEMORY_ADRESS4 (0x6C000000U) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup NOR_Private_Macros NOR Private Macros - * @{ - */ -/** - * @brief NOR memory address shifting. - * @param __NOR_ADDRESS NOR base address - * @param __NOR_MEMORY_WIDTH_ NOR memory width - * @param __ADDRESS__ NOR memory address - * @retval NOR shifted address value - */ -#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ - ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ - ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ - ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) - -/** - * @brief NOR memory write data to specified address. - * @param __ADDRESS__ NOR memory address - * @param __DATA__ Data to write - * @retval None - */ -#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ - (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ - __DSB(); \ - } while(0) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_NOR_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h index 7015ff81..07dacf2e 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd.h @@ -1,453 +1,453 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pcd.h - * @author MCD Application Team - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_PCD_H -#define STM32F7xx_HAL_PCD_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_usb.h" - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup PCD_Exported_Types PCD Exported Types - * @{ - */ - -/** - * @brief PCD State structure definition - */ -typedef enum -{ - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 -} PCD_StateTypeDef; - -/* Device LPM suspend state */ -typedef enum -{ - LPM_L0 = 0x00, /* on */ - LPM_L1 = 0x01, /* LPM L1 sleep */ - LPM_L2 = 0x02, /* suspend */ - LPM_L3 = 0x03, /* off */ -} PCD_LPM_StateTypeDef; - -typedef enum -{ - PCD_LPM_L0_ACTIVE = 0x00, /* on */ - PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ -} PCD_LPM_MsgTypeDef; - -typedef enum -{ - PCD_BCD_ERROR = 0xFF, - PCD_BCD_CONTACT_DETECTION = 0xFE, - PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, - PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, - PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, - PCD_BCD_DISCOVERY_COMPLETED = 0x00, - -} PCD_BCD_MsgTypeDef; - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -typedef USB_OTG_GlobalTypeDef PCD_TypeDef; -typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; -typedef USB_OTG_EPTypeDef PCD_EPTypeDef; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -/** - * @brief PCD Handle Structure definition - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -typedef struct __PCD_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - __IO uint32_t ErrorCode; /*!< PCD Error code */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ - uint32_t BESL; - uint32_t FrameNumber; /*!< Store Current Frame number */ - - - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - void *pData; /*!< Pointer to upper stack Handler */ - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ - void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ - void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ - void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ - void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ - void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ - void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ - - void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ - void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ - void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ - void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ - void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ - - void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ - void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -} PCD_HandleTypeDef; - -/** - * @} - */ - -/* Include PCD HAL Extended module */ -#include "stm32f7xx_hal_pcd_ex.h" - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ - -/** @defgroup PCD_Speed PCD Speed - * @{ - */ -#define PCD_SPEED_HIGH USBD_HS_SPEED -#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED -#define PCD_SPEED_FULL USBD_FS_SPEED -/** - * @} - */ - -/** @defgroup PCD_PHY_Module PCD PHY Module - * @{ - */ -#define PCD_PHY_ULPI 1U -#define PCD_PHY_EMBEDDED 2U -#define PCD_PHY_UTMI 3U -/** - * @} - */ - -/** @defgroup PCD_Error_Code_definition PCD Error Code definition - * @brief PCD Error Code definition - * @{ - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) - -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ - ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) - -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ - *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) - -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ - *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK - -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ - ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) - -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) - -#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ - EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ - EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ - } while(0U) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE - -#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ - do { \ - EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ - EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ - } while(0U) -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition - * @brief HAL USB OTG PCD Callback ID enumeration definition - * @{ - */ -typedef enum -{ - HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ - HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ - HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ - HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ - HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ - HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ - HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ - - HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ - HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ - -} HAL_PCD_CallbackIDTypeDef; -/** - * @} - */ - -/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition - * @brief HAL USB OTG PCD Callback pointer definition - * @{ - */ - -typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ -typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ -typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ -typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ -typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ -typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ - -/** - * @} - */ - -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, - pPCD_CallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, - pPCD_DataOutStageCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, - pPCD_DataInStageCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, - pPCD_IsoOutIncpltCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, - pPCD_IsoInIncpltCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* I/O operation functions ***************************************************/ -/* Non-Blocking mode: Interrupt */ -/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); -void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions - * @{ - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PCD_Private_Constants PCD Private Constants - * @{ - */ -/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ -#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - -/** - * @} - */ -/** - * @} - */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#ifndef USB_OTG_DOEPINT_OTEPSPR -#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ -#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ - -#ifndef USB_OTG_DOEPMSK_OTEPSPRM -#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ -#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ - -#ifndef USB_OTG_DOEPINT_NAK -#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ -#endif /* defined USB_OTG_DOEPINT_NAK */ - -#ifndef USB_OTG_DOEPMSK_NAKM -#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ -#endif /* defined USB_OTG_DOEPMSK_NAKM */ - -#ifndef USB_OTG_DOEPINT_STPKTRX -#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ -#endif /* defined USB_OTG_DOEPINT_STPKTRX */ - -#ifndef USB_OTG_DOEPMSK_NYETM -#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ -#endif /* defined USB_OTG_DOEPMSK_NYETM */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_PCD_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pcd.h + * @author MCD Application Team + * @brief Header file of PCD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_PCD_H +#define STM32F7xx_HAL_PCD_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_usb.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCD + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_Exported_Types PCD Exported Types + * @{ + */ + +/** + * @brief PCD State structure definition + */ +typedef enum +{ + HAL_PCD_STATE_RESET = 0x00, + HAL_PCD_STATE_READY = 0x01, + HAL_PCD_STATE_ERROR = 0x02, + HAL_PCD_STATE_BUSY = 0x03, + HAL_PCD_STATE_TIMEOUT = 0x04 +} PCD_StateTypeDef; + +/* Device LPM suspend state */ +typedef enum +{ + LPM_L0 = 0x00, /* on */ + LPM_L1 = 0x01, /* LPM L1 sleep */ + LPM_L2 = 0x02, /* suspend */ + LPM_L3 = 0x03, /* off */ +} PCD_LPM_StateTypeDef; + +typedef enum +{ + PCD_LPM_L0_ACTIVE = 0x00, /* on */ + PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ +} PCD_LPM_MsgTypeDef; + +typedef enum +{ + PCD_BCD_ERROR = 0xFF, + PCD_BCD_CONTACT_DETECTION = 0xFE, + PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, + PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, + PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, + PCD_BCD_DISCOVERY_COMPLETED = 0x00, + +} PCD_BCD_MsgTypeDef; + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +typedef USB_OTG_GlobalTypeDef PCD_TypeDef; +typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; +typedef USB_OTG_EPTypeDef PCD_EPTypeDef; +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @brief PCD Handle Structure definition + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +typedef struct __PCD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +{ + PCD_TypeDef *Instance; /*!< Register base address */ + PCD_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address; /*!< USB Address */ + PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + HAL_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[12]; /*!< Setup packet buffer */ + PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ + uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ + + + uint32_t lpm_active; /*!< Enable or disable the Link Power Management . + This parameter can be set to ENABLE or DISABLE */ + void *pData; /*!< Pointer to upper stack Handler */ + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ + void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ + void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ + void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ + void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ + void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ + void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ + + void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ + void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ + void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ + void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ + void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ + + void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +} PCD_HandleTypeDef; + +/** + * @} + */ + +/* Include PCD HAL Extended module */ +#include "stm32f7xx_hal_pcd_ex.h" + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Speed PCD Speed + * @{ + */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +/** @defgroup PCD_PHY_Module PCD PHY Module + * @{ + */ +#define PCD_PHY_ULPI 1U +#define PCD_PHY_EMBEDDED 2U +#define PCD_PHY_UTMI 3U +/** + * @} + */ + +/** @defgroup PCD_Error_Code_definition PCD Error Code definition + * @brief PCD Error Code definition + * @{ + */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup PCD_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) +#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) + +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) +#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) + +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) + +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK + +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) + +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE) + +#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + } while(0U) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE + +#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/* Initialization/de-initialization functions ********************************/ +/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); +void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition + * @brief HAL USB OTG PCD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ + HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ + HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ + HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ + HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ + HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ + HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ + + HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ + HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ + +} HAL_PCD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition + * @brief HAL USB OTG PCD Callback pointer definition + * @{ + */ + +typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ +typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ +typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ +typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ +typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ +typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ + +/** + * @} + */ + +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback); + +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); + +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/* Non-Blocking mode: Interrupt */ +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); +void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); + +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @} + */ +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif /* defined USB_OTG_DOEPINT_NAK */ + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NAKM */ + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NYETM */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_PCD_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h index d33c5414..33bec1e0 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pcd_ex.h @@ -1,83 +1,82 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pcd_ex.h - * @author MCD Application Team - * @brief Header file of PCD HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_PCD_EX_H -#define STM32F7xx_HAL_PCD_EX_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCDEx - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ -/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @{ - */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); - -void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); -void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - -#endif /* STM32F7xx_HAL_PCD_EX_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pcd_ex.h + * @author MCD Application Team + * @brief Header file of PCD HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_PCD_EX_H +#define STM32F7xx_HAL_PCD_EX_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PCDEx + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); + +void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); +void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32F7xx_HAL_PCD_EX_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h index 736ff6fc..7f19810d 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr.h @@ -1,402 +1,402 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_PWR_H -#define __STM32F7xx_HAL_PWR_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. - This parameter can be a value of @ref PWR_PVD_detection_level */ - - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode */ -}PWR_PVDTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_PVD_detection_level PWR PVD detection level - * @{ - */ -#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 -#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 -#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 -#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 -#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 -#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 -#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage - (Compare internally to VREFINT) */ - -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ -#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode - * @{ - */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) -#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS -/** - * @} - */ - -/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) -/** - * @} - */ - -/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry - * @{ - */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) -/** - * @} - */ - -/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale - * @{ - */ -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 -#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0 -/** - * @} - */ - -/** @defgroup PWR_Flag PWR Flag - * @{ - */ -#define PWR_FLAG_WU PWR_CSR1_WUIF -#define PWR_FLAG_SB PWR_CSR1_SBF -#define PWR_FLAG_PVDO PWR_CSR1_PVDO -#define PWR_FLAG_BRR PWR_CSR1_BRR -#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macro PWR Exported Macro - * @{ - */ - -/** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__ specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption when the device does - * not operate at the maximum frequency (refer to the datasheets for more details). - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode - * @retval None - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ - __IO uint32_t tmpreg; \ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ - UNUSED(tmpreg); \ - } while(0) - -/** @brief Check PWR flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event - * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B), - * RTC Tamper event, RTC TimeStamp event or RTC Wakeup)). - * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was - * resumed from StandBy mode. - * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode - * For this reason, this bit is equal to 0 after Standby or reset - * until the PVDE bit is set. - * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset - * when the device wakes up from Standby mode or by a system reset - * or power reset. - * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage - * scaling output selection is ready. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the PWR's pending flags. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg PWR_FLAG_SB: StandBy flag - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2) - -/** - * @brief Enable the PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable the PVD EXTI Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) - -/** - * @brief Disable event on PVD Exti Line 16. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) - -/** - * @brief Enable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) - - -/** - * @brief PVD EXTI line configuration: set rising & falling edge trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - -/** - * @brief checks whether the specified PVD Exti interrupt flag is set or not. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) - -/** - * @brief Clear the PVD Exti flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) - -/** - * @brief Generates a Software interrupt on PVD EXTI line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) - -/** - * @} - */ - -/* Include PWR HAL Extension module */ -#include "stm32f7xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ -/* Peripheral Control functions **********************************************/ -/* PVD configuration */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - -/* WakeUp pins configuration */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); - -/* Low Power modes entry */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -/* Power PVD IRQ Handler */ -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); - -/* Cortex System Control functions *******************************************/ -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PWR_Private_Constants PWR Private Constants - * @{ - */ - -/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line - * @{ - */ -#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ -/** - * @} - */ - -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PWR_Private_Macros PWR Private Macros - * @{ - */ - -/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters - * @{ - */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ - ((MODE) == PWR_PVD_MODE_NORMAL)) -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) -#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ - ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ - ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F7xx_HAL_PWR_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr.h + * @author MCD Application Team + * @brief Header file of PWR HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_PWR_H +#define __STM32F7xx_HAL_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + +/** + * @brief PWR PVD configuration structure definition + */ +typedef struct +{ + uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. + This parameter can be a value of @ref PWR_PVD_detection_level */ + + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ +}PWR_PVDTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_PVD_detection_level PWR PVD detection level + * @{ + */ +#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage + (Compare internally to VREFINT) */ + +/** + * @} + */ + +/** @defgroup PWR_PVD_Mode PWR PVD Mode + * @{ + */ +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode + * @{ + */ +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS +/** + * @} + */ + +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry + * @{ + */ +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry + * @{ + */ +#define PWR_STOPENTRY_WFI ((uint8_t)0x01U) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02U) +/** + * @} + */ + +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale + * @{ + */ +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR1_VOS_0 +/** + * @} + */ + +/** @defgroup PWR_Flag PWR Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR1_WUIF +#define PWR_FLAG_SB PWR_CSR1_SBF +#define PWR_FLAG_PVDO PWR_CSR1_PVDO +#define PWR_FLAG_BRR PWR_CSR1_BRR +#define PWR_FLAG_VOSRDY PWR_CSR1_VOSRDY +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Macro PWR Exported Macro + * @{ + */ + +/** @brief macros configure the main internal regulator output voltage. + * @param __REGULATOR__ specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption when the device does + * not operate at the maximum frequency (refer to the datasheets for more details). + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode + * @retval None + */ +#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \ + __IO uint32_t tmpreg; \ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event + * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B), + * RTC Tamper event, RTC TimeStamp event or RTC Wakeup)). + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was + * resumed from StandBy mode. + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * For this reason, this bit is equal to 0 after Standby or reset + * until the PVDE bit is set. + * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset + * when the device wakes up from Standby mode or by a system reset + * or power reset. + * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage + * scaling output selection is ready. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the PWR's pending flags. + * @param __FLAG__ specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_SB: StandBy flag + */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR1 |= (__FLAG__) << 2) + +/** + * @brief Enable the PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable the PVD EXTI Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD)) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD)) + +/** + * @brief Enable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable the PVD Extended Interrupt Rising Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief checks whether the specified PVD Exti interrupt flag is set or not. + * @retval EXTI PVD Line Status. + */ +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) + +/** + * @brief Clear the PVD Exti flag. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generates a Software interrupt on PVD EXTI line. + * @retval None + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD)) + +/** + * @} + */ + +/* Include PWR HAL Extension module */ +#include "stm32f7xx_hal_pwr_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void HAL_PWR_DeInit(void); +void HAL_PWR_EnableBkUpAccess(void); +void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ + +/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* PVD configuration */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +void HAL_PWR_EnablePVD(void); +void HAL_PWR_DisablePVD(void); + +/* WakeUp pins configuration */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity); +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); + +/* Low Power modes entry */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); +void HAL_PWR_EnterSTANDBYMode(void); + +/* Power PVD IRQ Handler */ +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); + +/* Cortex System Control functions *******************************************/ +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PWR_Private_Constants PWR Private Constants + * @{ + */ + +/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line + * @{ + */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +/** + * @} + */ + +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ + +/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) +#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ + ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F7xx_HAL_PWR_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h index e4a5995c..8178231d 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_pwr_ex.h @@ -1,260 +1,260 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pwr_ex.h - * @author MCD Application Team - * @brief Header file of PWR HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_PWR_EX_H -#define __STM32F7xx_HAL_PWR_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Constants PWREx Exported Constants - * @{ - */ -/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins - * @{ - */ -#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 -#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 -#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 -#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 -#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 -#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 -#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1 -#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2 -#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3 -#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4 -#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5 -#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6 -#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1) -#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2) -#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3) -#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4) -#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5) -#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6) - -/** - * @} - */ - -/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode - * @{ - */ -#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS -#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS)) -/** - * @} - */ - -/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag - * @{ - */ -#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY -#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY -#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY -/** - * @} - */ - -/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags - * @{ - */ -#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1 -#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2 -#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3 -#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4 -#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5 -#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6 -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Macro PWREx Exported Macro - * @{ - */ -/** @brief Macros to enable or disable the Over drive mode. - */ -#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN) -#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN)) - -/** @brief Macros to enable or disable the Over drive switching. - */ -#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN) -#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN)) - -/** @brief Macros to enable or disable the Under drive mode. - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode. - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - */ -#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN) -#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN)) - -/** @brief Check PWR flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode - * is ready - * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode - * switching is ready - * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode - * is enabled in Stop mode - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the Under-Drive Ready flag. - */ -#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= (PWR_FLAG_UDRDY | PWR_CSR1_EIWUP)) - -/** @brief Check Wake Up flag is set or not. - * @param __WUFLAG__ specifies the Wake Up flag to check. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 - * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 - * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 - * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 - * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 - * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 - */ -#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__)) - -/** @brief Clear the WakeUp pins flags. - * @param __WUFLAG__ specifies the Wake Up pin flag to clear. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 - * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 - * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 - * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 - * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 - * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 - */ -#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__)) -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 - * @{ - */ -uint32_t HAL_PWREx_GetVoltageRange(void); -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); - -void HAL_PWREx_EnableFlashPowerDown(void); -void HAL_PWREx_DisableFlashPowerDown(void); -HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); - -void HAL_PWREx_EnableMainRegulatorLowVoltage(void); -void HAL_PWREx_DisableMainRegulatorLowVoltage(void); -void HAL_PWREx_EnableLowRegulatorLowVoltage(void); -void HAL_PWREx_DisableLowRegulatorLowVoltage(void); - -HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); -HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); -HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); - -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PWREx_Private_Macros PWREx Private Macros - * @{ - */ - -/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters - * @{ - */ -#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) -#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \ - ((__PIN__) == PWR_WAKEUP_PIN2) || \ - ((__PIN__) == PWR_WAKEUP_PIN3) || \ - ((__PIN__) == PWR_WAKEUP_PIN4) || \ - ((__PIN__) == PWR_WAKEUP_PIN5) || \ - ((__PIN__) == PWR_WAKEUP_PIN6) || \ - ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \ - ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \ - ((__PIN__) == PWR_WAKEUP_PIN6_LOW)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* __STM32F7xx_HAL_PWR_EX_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr_ex.h + * @author MCD Application Team + * @brief Header file of PWR HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_PWR_EX_H +#define __STM32F7xx_HAL_PWR_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup PWREx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Constants PWREx Exported Constants + * @{ + */ +/** @defgroup PWREx_WakeUp_Pins PWREx Wake Up Pins + * @{ + */ +#define PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 +#define PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 +#define PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 +#define PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 +#define PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 +#define PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 +#define PWR_WAKEUP_PIN1_HIGH PWR_CSR2_EWUP1 +#define PWR_WAKEUP_PIN2_HIGH PWR_CSR2_EWUP2 +#define PWR_WAKEUP_PIN3_HIGH PWR_CSR2_EWUP3 +#define PWR_WAKEUP_PIN4_HIGH PWR_CSR2_EWUP4 +#define PWR_WAKEUP_PIN5_HIGH PWR_CSR2_EWUP5 +#define PWR_WAKEUP_PIN6_HIGH PWR_CSR2_EWUP6 +#define PWR_WAKEUP_PIN1_LOW (uint32_t)((PWR_CR2_WUPP1<<6) | PWR_CSR2_EWUP1) +#define PWR_WAKEUP_PIN2_LOW (uint32_t)((PWR_CR2_WUPP2<<6) | PWR_CSR2_EWUP2) +#define PWR_WAKEUP_PIN3_LOW (uint32_t)((PWR_CR2_WUPP3<<6) | PWR_CSR2_EWUP3) +#define PWR_WAKEUP_PIN4_LOW (uint32_t)((PWR_CR2_WUPP4<<6) | PWR_CSR2_EWUP4) +#define PWR_WAKEUP_PIN5_LOW (uint32_t)((PWR_CR2_WUPP5<<6) | PWR_CSR2_EWUP5) +#define PWR_WAKEUP_PIN6_LOW (uint32_t)((PWR_CR2_WUPP6<<6) | PWR_CSR2_EWUP6) + +/** + * @} + */ + +/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode + * @{ + */ +#define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR1_MRUDS +#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR1_LPDS | PWR_CR1_LPUDS)) +/** + * @} + */ + +/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag + * @{ + */ +#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY +#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY +#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY +/** + * @} + */ + +/** @defgroup PWREx_Wakeup_Pins_Flag PWREx Wake Up Pin Flags + * @{ + */ +#define PWR_WAKEUP_PIN_FLAG1 PWR_CSR2_WUPF1 +#define PWR_WAKEUP_PIN_FLAG2 PWR_CSR2_WUPF2 +#define PWR_WAKEUP_PIN_FLAG3 PWR_CSR2_WUPF3 +#define PWR_WAKEUP_PIN_FLAG4 PWR_CSR2_WUPF4 +#define PWR_WAKEUP_PIN_FLAG5 PWR_CSR2_WUPF5 +#define PWR_WAKEUP_PIN_FLAG6 PWR_CSR2_WUPF6 +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Macro PWREx Exported Macro + * @{ + */ +/** @brief Macros to enable or disable the Over drive mode. + */ +#define __HAL_PWR_OVERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODEN) +#define __HAL_PWR_OVERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODEN)) + +/** @brief Macros to enable or disable the Over drive switching. + */ +#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_ODSWEN) +#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_ODSWEN)) + +/** @brief Macros to enable or disable the Under drive mode. + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + */ +#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR1 |= (uint32_t)PWR_CR1_UDEN) +#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN)) + +/** @brief Check PWR flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode + * is ready + * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode + * switching is ready + * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode + * is enabled in Stop mode + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the Under-Drive Ready flag. + */ +#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= (PWR_FLAG_UDRDY | PWR_CSR1_EIWUP)) + +/** @brief Check Wake Up flag is set or not. + * @param __WUFLAG__ specifies the Wake Up flag to check. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 + * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 + * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 + * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 + * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 + * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 + */ +#define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__)) + +/** @brief Clear the WakeUp pins flags. + * @param __WUFLAG__ specifies the Wake Up pin flag to clear. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 + * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 + * @arg PWR_WAKEUP_PIN_FLAG3: Wakeup Pin Flag for PC1 + * @arg PWR_WAKEUP_PIN_FLAG4: Wakeup Pin Flag for PC13 + * @arg PWR_WAKEUP_PIN_FLAG5: Wakeup Pin Flag for PI8 + * @arg PWR_WAKEUP_PIN_FLAG6: Wakeup Pin Flag for PI11 + */ +#define __HAL_PWR_CLEAR_WAKEUP_FLAG(__WUFLAG__) (PWR->CR2 |= (__WUFLAG__)) +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @addtogroup PWREx_Exported_Functions_Group1 + * @{ + */ +uint32_t HAL_PWREx_GetVoltageRange(void); +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); + +void HAL_PWREx_EnableFlashPowerDown(void); +void HAL_PWREx_DisableFlashPowerDown(void); +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void); +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); + +void HAL_PWREx_EnableMainRegulatorLowVoltage(void); +void HAL_PWREx_DisableMainRegulatorLowVoltage(void); +void HAL_PWREx_EnableLowRegulatorLowVoltage(void); +void HAL_PWREx_DisableLowRegulatorLowVoltage(void); + +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void); +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PWREx_Private_Macros PWREx Private Macros + * @{ + */ + +/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters + * @{ + */ +#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON)) +#define IS_PWR_WAKEUP_PIN(__PIN__) (((__PIN__) == PWR_WAKEUP_PIN1) || \ + ((__PIN__) == PWR_WAKEUP_PIN2) || \ + ((__PIN__) == PWR_WAKEUP_PIN3) || \ + ((__PIN__) == PWR_WAKEUP_PIN4) || \ + ((__PIN__) == PWR_WAKEUP_PIN5) || \ + ((__PIN__) == PWR_WAKEUP_PIN6) || \ + ((__PIN__) == PWR_WAKEUP_PIN1_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN2_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN3_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN4_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN5_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN6_HIGH) || \ + ((__PIN__) == PWR_WAKEUP_PIN1_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN2_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN3_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN4_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN5_LOW) || \ + ((__PIN__) == PWR_WAKEUP_PIN6_LOW)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __STM32F7xx_HAL_PWR_EX_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h deleted file mode 100644 index f5fecc47..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_qspi.h +++ /dev/null @@ -1,750 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_qspi.h - * @author MCD Application Team - * @brief Header file of QSPI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_QSPI_H -#define STM32F7xx_HAL_QSPI_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined(QUADSPI) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup QSPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup QSPI_Exported_Types QSPI Exported Types - * @{ - */ - -/** - * @brief QSPI Init structure definition - */ -typedef struct -{ - uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. - This parameter can be a number between 0 and 255 */ - uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) - This parameter can be a value between 1 and 32 */ - uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to - take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) - This parameter can be a value of @ref QSPI_SampleShifting */ - uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits - required to address the flash memory. The flash capacity can be up to 4GB - (addressed using 32 bits) in indirect mode, but the addressable space in - memory-mapped mode is limited to 256MB - This parameter can be a number between 0 and 31 */ - uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number - of clock cycles which the chip select must remain high between commands. - This parameter can be a value of @ref QSPI_ChipSelectHighTime */ - uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. - This parameter can be a value of @ref QSPI_ClockMode */ - uint32_t FlashID; /* Specifies the Flash which will be used, - This parameter can be a value of @ref QSPI_Flash_Select */ - uint32_t DualFlash; /* Specifies the Dual Flash Mode State - This parameter can be a value of @ref QSPI_DualFlash_Mode */ -}QSPI_InitTypeDef; - -/** - * @brief HAL QSPI State structures definition - */ -typedef enum -{ - HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ - HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ - HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ - HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ - HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ - HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ - HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ - HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ - HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ -}HAL_QSPI_StateTypeDef; - -/** - * @brief QSPI Handle Structure definition - */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) -typedef struct __QSPI_HandleTypeDef -#else -typedef struct -#endif -{ - QUADSPI_TypeDef *Instance; /* QSPI registers base address */ - QSPI_InitTypeDef Init; /* QSPI communication parameters */ - uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ - __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ - __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ - __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ - __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ - DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ - __IO HAL_LockTypeDef Lock; /* Locking object */ - __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ - __IO uint32_t ErrorCode; /* QSPI Error code */ - uint32_t Timeout; /* Timeout for the QSPI memory access */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); - void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); - - void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); - void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); -#endif -}QSPI_HandleTypeDef; - -/** - * @brief QSPI Command structure definition - */ -typedef struct -{ - uint32_t Instruction; /* Specifies the Instruction to be sent - This parameter can be a value (8-bit) between 0x00 and 0xFF */ - uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) - This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ - uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) - This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ - uint32_t AddressSize; /* Specifies the Address Size - This parameter can be a value of @ref QSPI_AddressSize */ - uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size - This parameter can be a value of @ref QSPI_AlternateBytesSize */ - uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. - This parameter can be a number between 0 and 31 */ - uint32_t InstructionMode; /* Specifies the Instruction Mode - This parameter can be a value of @ref QSPI_InstructionMode */ - uint32_t AddressMode; /* Specifies the Address Mode - This parameter can be a value of @ref QSPI_AddressMode */ - uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode - This parameter can be a value of @ref QSPI_AlternateBytesMode */ - uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) - This parameter can be a value of @ref QSPI_DataMode */ - uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) - This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length - until end of memory)*/ - uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase - This parameter can be a value of @ref QSPI_DdrMode */ - uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data - output by one half of system clock in DDR mode. - This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ - uint32_t SIOOMode; /* Specifies the send instruction only once mode - This parameter can be a value of @ref QSPI_SIOOMode */ -}QSPI_CommandTypeDef; - -/** - * @brief QSPI Auto Polling mode configuration structure definition - */ -typedef struct -{ - uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. - This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. - This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. - This parameter can be any value between 0 and 0xFFFF */ - uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. - This parameter can be any value between 1 and 4 */ - uint32_t MatchMode; /* Specifies the method used for determining a match. - This parameter can be a value of @ref QSPI_MatchMode */ - uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. - This parameter can be a value of @ref QSPI_AutomaticStop */ -}QSPI_AutoPollingTypeDef; - -/** - * @brief QSPI Memory Mapped mode configuration structure definition - */ -typedef struct -{ - uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. - This parameter can be any value between 0 and 0xFFFF */ - uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. - This parameter can be a value of @ref QSPI_TimeOutActivation */ -}QSPI_MemoryMappedTypeDef; - -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) -/** - * @brief HAL QSPI Callback ID enumeration definition - */ -typedef enum -{ - HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ - HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ - HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ - HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ - HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ - HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ - HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ - HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ - HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ - HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ - - HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ - HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ -}HAL_QSPI_CallbackIDTypeDef; - -/** - * @brief HAL QSPI Callback pointer definition - */ -typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); -#endif -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup QSPI_Exported_Constants QSPI Exported Constants - * @{ - */ - -/** @defgroup QSPI_ErrorCode QSPI Error Code - * @{ - */ -#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ -#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ -#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ -#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ -#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) -#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ -#endif -/** - * @} - */ - -/** @defgroup QSPI_SampleShifting QSPI Sample Shifting - * @{ - */ -#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!State = HAL_QSPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) -#endif - -/** @brief Enable the QSPI peripheral. - * @param __HANDLE__ specifies the QSPI Handle. - * @retval None - */ -#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) - -/** @brief Disable the QSPI peripheral. - * @param __HANDLE__ specifies the QSPI Handle. - * @retval None - */ -#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) - -/** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. - * This parameter can be one of the following values: - * @arg QSPI_IT_TO: QSPI Timeout interrupt - * @arg QSPI_IT_SM: QSPI Status match interrupt - * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt - * @arg QSPI_IT_TC: QSPI Transfer complete interrupt - * @arg QSPI_IT_TE: QSPI Transfer error interrupt - * @retval None - */ -#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) - - -/** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. - * This parameter can be one of the following values: - * @arg QSPI_IT_TO: QSPI Timeout interrupt - * @arg QSPI_IT_SM: QSPI Status match interrupt - * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt - * @arg QSPI_IT_TC: QSPI Transfer complete interrupt - * @arg QSPI_IT_TE: QSPI Transfer error interrupt - * @retval None - */ -#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) - -/** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __INTERRUPT__ specifies the QSPI interrupt source to check. - * This parameter can be one of the following values: - * @arg QSPI_IT_TO: QSPI Timeout interrupt - * @arg QSPI_IT_SM: QSPI Status match interrupt - * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt - * @arg QSPI_IT_TC: QSPI Transfer complete interrupt - * @arg QSPI_IT_TE: QSPI Transfer error interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __FLAG__ specifies the QSPI flag to check. - * This parameter can be one of the following values: - * @arg QSPI_FLAG_BUSY: QSPI Busy flag - * @arg QSPI_FLAG_TO: QSPI Timeout flag - * @arg QSPI_FLAG_SM: QSPI Status match flag - * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag - * @arg QSPI_FLAG_TC: QSPI Transfer complete flag - * @arg QSPI_FLAG_TE: QSPI Transfer error flag - * @retval None - */ -#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) - -/** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ specifies the QSPI Handle. - * @param __FLAG__ specifies the QSPI clear register flag that needs to be set - * This parameter can be one of the following values: - * @arg QSPI_FLAG_TO: QSPI Timeout flag - * @arg QSPI_FLAG_SM: QSPI Status match flag - * @arg QSPI_FLAG_TC: QSPI Transfer complete flag - * @arg QSPI_FLAG_TE: QSPI Transfer error flag - * @retval None - */ -#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup QSPI_Exported_Functions - * @{ - */ - -/** @addtogroup QSPI_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); -HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); -/** - * @} - */ - -/** @addtogroup QSPI_Exported_Functions_Group2 - * @{ - */ -/* IO operation functions *****************************************************/ -/* QSPI IRQ handler method */ -void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); - -/* QSPI indirect mode */ -HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); -HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); -HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); -HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); -HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); -HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); - -/* QSPI status flag polling mode */ -HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); - -/* QSPI memory-mapped mode */ -HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); - -/* Callback functions in non-blocking modes ***********************************/ -void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); - -/* QSPI indirect mode */ -void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); - -/* QSPI status flag polling mode */ -void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); - -/* QSPI memory-mapped mode */ -void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); - -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) -/* QSPI callback registering/unregistering */ -HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); -#endif -/** - * @} - */ - -/** @addtogroup QSPI_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control and State functions ************************************/ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState (const QSPI_HandleTypeDef *hqspi); -uint32_t HAL_QSPI_GetError (const QSPI_HandleTypeDef *hqspi); -HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); -HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); -void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); -HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); -uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi); -HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup QSPI_Private_Macros QSPI Private Macros - * @{ - */ -#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) - -#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) - -#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ - ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) - -#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) - -#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ - ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) - -#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ - ((CLKMODE) == QSPI_CLOCK_MODE_3)) - -#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ - ((FLASH_ID) == QSPI_FLASH_ID_2)) - -#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ - ((MODE) == QSPI_DUALFLASH_DISABLE)) - -#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) - -#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ - ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) - -#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ - ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) - -#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) - -#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ - ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ - ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ - ((MODE) == QSPI_INSTRUCTION_4_LINES)) - -#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ - ((MODE) == QSPI_ADDRESS_1_LINE) || \ - ((MODE) == QSPI_ADDRESS_2_LINES) || \ - ((MODE) == QSPI_ADDRESS_4_LINES)) - -#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ - ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) - -#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ - ((MODE) == QSPI_DATA_1_LINE) || \ - ((MODE) == QSPI_DATA_2_LINES) || \ - ((MODE) == QSPI_DATA_4_LINES)) - -#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ - ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) - -#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ - ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) - -#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ - ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) - -#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) - -#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) - -#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ - ((MODE) == QSPI_MATCH_MODE_OR)) - -#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ - ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) - -#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ - ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) - -#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) -/** -* @} -*/ -/* End of private macros -----------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(QUADSPI) */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_QSPI_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h index f3309a31..50c1627f 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc.h @@ -1,1307 +1,1307 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_RCC_H -#define __STM32F7xx_HAL_RCC_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/* Include RCC HAL Extended module */ -/* (include on top of file since RCC structures are defined in extended file) */ -#include "stm32f7xx_hal_rcc_ex.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ - -}RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB buses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ - -}RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) -#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) -#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) -#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) -#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup RCC_HSE_Config RCC HSE Config - * @{ - */ -#define RCC_HSE_OFF ((uint32_t)0x00000000U) -#define RCC_HSE_ON RCC_CR_HSEON -#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) -/** - * @} - */ - -/** @defgroup RCC_LSE_Config RCC LSE Config - * @{ - */ -#define RCC_LSE_OFF ((uint32_t)0x00000000U) -#define RCC_LSE_ON RCC_BDCR_LSEON -#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) -/** - * @} - */ - -/** @defgroup RCC_HSI_Config RCC HSI Config - * @{ - */ -#define RCC_HSI_OFF ((uint32_t)0x00000000U) -#define RCC_HSI_ON RCC_CR_HSION - -#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Config RCC LSI Config - * @{ - */ -#define RCC_LSI_OFF ((uint32_t)0x00000000U) -#define RCC_LSI_ON RCC_CSR_LSION -/** - * @} - */ - -/** @defgroup RCC_PLL_Config RCC PLL Config - * @{ - */ -#define RCC_PLL_NONE ((uint32_t)0x00000000U) -#define RCC_PLL_OFF ((uint32_t)0x00000001U) -#define RCC_PLL_ON ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider - * @{ - */ -#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) -#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) -#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) -#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source PLL Clock Source - * @{ - */ -#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI -#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type RCC System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) -#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) -#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) -#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source RCC System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE -#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL -/** - * @} - */ - - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 -#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 -#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 -#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 -#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 -#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 -#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 -#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 -#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 -#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 -#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 -#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 -#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) -#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) -#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) -#define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U) -#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) -#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) -#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) -#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) -#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) -#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) -#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) -#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) -#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) -#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) -#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) -#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) -#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) -#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) -#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) -#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) -#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) -#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) -#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) -#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) -/** - * @} - */ - - - -/** @defgroup RCC_MCO_Index RCC MCO Index - * @{ - */ -#define RCC_MCO1 ((uint32_t)0x00000000U) -#define RCC_MCO2 ((uint32_t)0x00000001U) -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) -#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 -#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 -#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 -/** - * @} - */ - -/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source - * @{ - */ -#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) -#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 -#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 -#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 ((uint32_t)0x00000000U) -#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 -#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) -#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) -#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE -/** - * @} - */ - -/** @defgroup RCC_Interrupt RCC Interrupt - * @{ - */ -#define RCC_IT_LSIRDY ((uint8_t)0x01U) -#define RCC_IT_LSERDY ((uint8_t)0x02U) -#define RCC_IT_HSIRDY ((uint8_t)0x04U) -#define RCC_IT_HSERDY ((uint8_t)0x08U) -#define RCC_IT_PLLRDY ((uint8_t)0x10U) -#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) -#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) -#define RCC_IT_CSS ((uint8_t)0x80U) -/** - * @} - */ - -/** @defgroup RCC_Flag RCC Flags - * Elements values convention: 0XXYYYYYb - * - YYYYY : Flag position in the register - * - 0XX : Register index - * - 01: CR register - * - 10: BDCR register - * - 11: CSR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_HSIRDY ((uint8_t)0x21U) -#define RCC_FLAG_HSERDY ((uint8_t)0x31U) -#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) -#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) -#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint8_t)0x41U) - -/* Flags in the CSR register */ -#define RCC_FLAG_LSIRDY ((uint8_t)0x61U) -#define RCC_FLAG_BORRST ((uint8_t)0x79U) -#define RCC_FLAG_PINRST ((uint8_t)0x7AU) -#define RCC_FLAG_PORRST ((uint8_t)0x7BU) -#define RCC_FLAG_SFTRST ((uint8_t)0x7CU) -#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) -#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) -#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) -/** - * @} - */ - -/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations - * @{ - */ -#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) -#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) -#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) -#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) - -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status - * @brief EGet the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release - * @brief Force or release AHB peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) -#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) - -#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) -#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) -#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) - -#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) -#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) -#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) - -#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) -#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) - -/** - * @} - */ - -/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) - -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) -#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) - -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) -#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) - -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) -#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) - -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) -#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) - -#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) - -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) -/** - * @} - */ - -/** @defgroup RCC_HSI_Configuration HSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - */ -#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) -#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) - -/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value. - * (default is RCC_HSICALIBRATION_DEFAULT). - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ - RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos)) -/** - * @} - */ - -/** @defgroup RCC_LSI_Configuration LSI Configuration - * @{ - */ - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - */ -#define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) -#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) -/** - * @} - */ - -/** @defgroup RCC_HSE_Configuration HSE Configuration - * @{ - */ -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. - * @note This function reset the CSSON bit, so if the clock security system(CSS) - * was previously enabled you have to enable it again after calling this - * function. - * @param __STATE__ specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg RCC_HSE_ON: turn ON the HSE oscillator. - * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - if ((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if ((__STATE__) == RCC_HSE_OFF) \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - else if ((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - } \ - } while(0) -/** - * @} - */ - -/** @defgroup RCC_LSE_Configuration LSE Configuration - * @{ - */ - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. - * User should request a transition to LSE Off first and then LSE On or LSE Bypass. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__ specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg RCC_LSE_ON: turn ON the LSE oscillator. - * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if((__STATE__) == RCC_LSE_OFF) \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - } while(0) -/** - * @} - */ - -/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration - * @{ - */ - -/** @brief Macros to enable or disable the RTC clock. - * @note These macros must be used only after the RTC clock source was selected. - */ -#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) -#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) - -/** @brief Macros to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the - * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by - * a Power On Reset (POR). - * @param __RTCCLKSource__ specifies the RTC clock source. - * This parameter can be one of the following values: - @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - */ -#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ - MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) - -#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ - RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ - } while (0) - -/** @brief Macro to get the RTC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() - */ -#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) - -/** - * @brief Get the RTC and HSE clock divider (RTCPRE). - * @retval Returned value can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected - * as RTC clock, where x:[2,31] - */ -#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) - -/** @brief Macros to force or release the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - */ -#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) -#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) -/** - * @} - */ - -/** @defgroup RCC_PLL_Configuration PLL Configuration - * @{ - */ - -/** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) - -/** @brief Macro to configure the PLL clock source. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLSOURCE__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * - */ -#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) - -/** @brief Macro to configure the PLL multiplication factor. - * @note This function must be used only when the main PLL is disabled. - * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * - */ -#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) -/** - * @} - */ - -/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration - * @{ - */ - -/** @brief Macro to configure the I2S clock source (I2SCLK). - * @note This function must be called before enabling the I2S APB clock. - * @param __SOURCE__ specifies the I2S clock source. - * This parameter can be one of the following values: - * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. - * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin - * used as I2S clock source. - */ -#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ - RCC->CFGR |= (__SOURCE__); \ - }while(0) - -/** @brief Macros to enable or disable the PLLI2S. - * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) -#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) -/** - * @} - */ - -/** @defgroup RCC_Get_Clock_source Get Clock source - * @{ - */ -/** - * @brief Macro to configure the system clock source. - * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. - * This parameter can be one of the following values: - * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. - */ -#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) - -/** - * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. - * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. - * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. - * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. - * @retval None - */ -#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ - (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) - -/** @brief Macro to get the oscillator used as PLL clock source. - * @retval The oscillator used as PLL clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) -/** - * @} - */ - -/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config - * @{ - */ - -/** @brief Macro to configure the MCO1 clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - */ - -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) - -/** @brief Macro to configure the MCO2 clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - */ - -#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); -/** - * @} - */ - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts). - * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) - -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) - -/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - * @arg RCC_IT_CSS: Clock Security System interrupt - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) - -/** @brief Check the RCC's interrupt has occurred or not. - * @param __INTERRUPT__ specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg RCC_IT_LSIRDY: LSI ready interrupt. - * @arg RCC_IT_LSERDY: LSE ready interrupt. - * @arg RCC_IT_HSIRDY: HSI ready interrupt. - * @arg RCC_IT_HSERDY: HSE ready interrupt. - * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. - * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. - * @arg RCC_IT_CSS: Clock Security System interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, - * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) - -/** @brief Check RCC flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. - * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. - * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. - * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. - * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. - * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. - * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. - * @arg RCC_FLAG_PINRST: Pin reset. - * @arg RCC_FLAG_PORRST: POR/PDR reset. - * @arg RCC_FLAG_SFTRST: Software reset. - * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. - * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. - * @arg RCC_FLAG_LPWRRST: Low Power reset. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define RCC_FLAG_MASK ((uint8_t)0x1F) -#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) - -/** - * @} - */ - -/** - * @} - */ - -/* Include RCC HAL Extension module */ -#include "stm32f7xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ - /** @addtogroup RCC_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ************************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -void HAL_RCC_DisableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); - -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ -#define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ -#define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ - -/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias - * @brief RCC registers bit address alias - * @{ - */ -/* CIR register byte 2 (Bits[15:8]) base address */ -#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) - -/* CIR register byte 3 (Bits[23:16]) base address */ -#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) - -#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -/** - * @} - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters - * @{ - */ -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) - -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_BYPASS)) - -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_BYPASS)) - -#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) - -#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) - -#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) - -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) - -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) -#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) - -#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) - -#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ - ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) - -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ - ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ - ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ - ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ - ((HCLK) == RCC_SYSCLK_DIV512)) - -#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) - -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ - ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ - ((PCLK) == RCC_HCLK_DIV16)) - -#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) - - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) - -#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ - ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) - -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ - ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ - ((DIV) == RCC_MCODIV_5)) -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) - -#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) - - -#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ - ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((DRIVE) == RCC_LSEDRIVE_HIGH)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_RCC_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc.h + * @author MCD Application Team + * @brief Header file of RCC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_RCC_H +#define __STM32F7xx_HAL_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/* Include RCC HAL Extended module */ +/* (include on top of file since RCC structures are defined in extended file) */ +#include "stm32f7xx_hal_rcc_ex.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Types RCC Exported Types + * @{ + */ + +/** + * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition + */ +typedef struct +{ + uint32_t OscillatorType; /*!< The oscillators to be configured. + This parameter can be a value of @ref RCC_Oscillator_Type */ + + uint32_t HSEState; /*!< The new state of the HSE. + This parameter can be a value of @ref RCC_HSE_Config */ + + uint32_t LSEState; /*!< The new state of the LSE. + This parameter can be a value of @ref RCC_LSE_Config */ + + uint32_t HSIState; /*!< The new state of the HSI. + This parameter can be a value of @ref RCC_HSI_Config */ + + uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ + + uint32_t LSIState; /*!< The new state of the LSI. + This parameter can be a value of @ref RCC_LSI_Config */ + + RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */ + +}RCC_OscInitTypeDef; + +/** + * @brief RCC System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t ClockType; /*!< The clock to be configured. + This parameter can be a value of @ref RCC_System_Clock_Type */ + + uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. + This parameter can be a value of @ref RCC_System_Clock_Source */ + + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_AHB_Clock_Source */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ + +}RCC_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type Oscillator Type + * @{ + */ +#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U) +#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U) +#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U) +#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U) +#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_HSE_Config RCC HSE Config + * @{ + */ +#define RCC_HSE_OFF ((uint32_t)0x00000000U) +#define RCC_HSE_ON RCC_CR_HSEON +#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) +/** + * @} + */ + +/** @defgroup RCC_LSE_Config RCC LSE Config + * @{ + */ +#define RCC_LSE_OFF ((uint32_t)0x00000000U) +#define RCC_LSE_ON RCC_BDCR_LSEON +#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) +/** + * @} + */ + +/** @defgroup RCC_HSI_Config RCC HSI Config + * @{ + */ +#define RCC_HSI_OFF ((uint32_t)0x00000000U) +#define RCC_HSI_ON RCC_CR_HSION + +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */ +/** + * @} + */ + +/** @defgroup RCC_LSI_Config RCC LSI Config + * @{ + */ +#define RCC_LSI_OFF ((uint32_t)0x00000000U) +#define RCC_LSI_ON RCC_CSR_LSION +/** + * @} + */ + +/** @defgroup RCC_PLL_Config RCC PLL Config + * @{ + */ +#define RCC_PLL_NONE ((uint32_t)0x00000000U) +#define RCC_PLL_OFF ((uint32_t)0x00000001U) +#define RCC_PLL_ON ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider + * @{ + */ +#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U) +#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U) +#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U) +#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_PLL_Clock_Source PLL Clock Source + * @{ + */ +#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI +#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Type RCC System Clock Type + * @{ + */ +#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U) +#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U) +#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U) +#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U) +/** + * @} + */ + +/** @defgroup RCC_System_Clock_Source RCC System Clock Source + * @{ + */ +#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI +#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL +/** + * @} + */ + + +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source + * @{ + */ +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 +/** + * @} + */ + +/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1/APB2 Clock Source + * @{ + */ +#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 +#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 +#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 +#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 +#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 +/** + * @} + */ + +/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source + * @{ + */ +#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U) +#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U) +#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U) +#define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U) +#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U) +#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U) +#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U) +#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U) +#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U) +#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U) +#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U) +#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U) +#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U) +#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U) +#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U) +#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U) +#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U) +#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U) +#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U) +#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U) +#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U) +#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U) +#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U) +#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U) +/** + * @} + */ + + + +/** @defgroup RCC_MCO_Index RCC MCO Index + * @{ + */ +#define RCC_MCO1 ((uint32_t)0x00000000U) +#define RCC_MCO2 ((uint32_t)0x00000001U) +/** + * @} + */ + +/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source + * @{ + */ +#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U) +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0 +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1 +#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1 +/** + * @} + */ + +/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source + * @{ + */ +#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U) +#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0 +#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1 +#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2 +/** + * @} + */ + +/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler + * @{ + */ +#define RCC_MCODIV_1 ((uint32_t)0x00000000U) +#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2 +#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2) +#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE +/** + * @} + */ + +/** @defgroup RCC_Interrupt RCC Interrupt + * @{ + */ +#define RCC_IT_LSIRDY ((uint8_t)0x01U) +#define RCC_IT_LSERDY ((uint8_t)0x02U) +#define RCC_IT_HSIRDY ((uint8_t)0x04U) +#define RCC_IT_HSERDY ((uint8_t)0x08U) +#define RCC_IT_PLLRDY ((uint8_t)0x10U) +#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U) +#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U) +#define RCC_IT_CSS ((uint8_t)0x80U) +/** + * @} + */ + +/** @defgroup RCC_Flag RCC Flags + * Elements values convention: 0XXYYYYYb + * - YYYYY : Flag position in the register + * - 0XX : Register index + * - 01: CR register + * - 10: BDCR register + * - 11: CSR register + * @{ + */ +/* Flags in the CR register */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21U) +#define RCC_FLAG_HSERDY ((uint8_t)0x31U) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39U) +#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU) +#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU) + +/* Flags in the BDCR register */ +#define RCC_FLAG_LSERDY ((uint8_t)0x41U) + +/* Flags in the CSR register */ +#define RCC_FLAG_LSIRDY ((uint8_t)0x61U) +#define RCC_FLAG_BORRST ((uint8_t)0x79U) +#define RCC_FLAG_PINRST ((uint8_t)0x7AU) +#define RCC_FLAG_PORRST ((uint8_t)0x7BU) +#define RCC_FLAG_SFTRST ((uint8_t)0x7CU) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU) +/** + * @} + */ + +/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations + * @{ + */ +#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U) +#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 +#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 +#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable + * @brief Enable or disable the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN)) + +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable + * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_PWR_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable + * @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA1EN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) + +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status + * @brief EGet the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release + * @brief Force or release AHB peripheral reset. + * @{ + */ +#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST)) + +#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST)) +/** + * @} + */ + +/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset + * @brief Force or release APB1 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) + +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) +/** + * @} + */ + +/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset + * @brief Force or release APB2 peripheral reset. + * @{ + */ +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) + +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST)) + +/** + * @} + */ + +/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN)) + +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN)) + +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN)) + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN)) + +/** + * @} + */ + +/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) + +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) + +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) +/** + * @} + */ + +/** @defgroup RCC_HSI_Configuration HSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * It is used (enabled by hardware) as system clock source after startup + * from Reset, wakeup from STOP and STANDBY mode, or in case of failure + * of the HSE used directly or indirectly as system clock (if the Clock + * Security System CSS is enabled). + * @note HSI can not be stopped if it is used as system clock source. In this case, + * you have to select another source of the system clock then stop the HSI. + * @note After enabling the HSI, the application software should wait on HSIRDY + * flag to be set indicating that HSI clock is stable and can be used as + * system clock source. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + */ +#define __HAL_RCC_HSI_ENABLE() (RCC->CR |= (RCC_CR_HSION)) +#define __HAL_RCC_HSI_DISABLE() (RCC->CR &= ~(RCC_CR_HSION)) + +/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value. + * (default is RCC_HSICALIBRATION_DEFAULT). + */ +#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\ + RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos)) +/** + * @} + */ + +/** @defgroup RCC_LSI_Configuration LSI Configuration + * @{ + */ + +/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + */ +#define __HAL_RCC_LSI_ENABLE() (RCC->CSR |= (RCC_CSR_LSION)) +#define __HAL_RCC_LSI_DISABLE() (RCC->CSR &= ~(RCC_CSR_LSION)) +/** + * @} + */ + +/** @defgroup RCC_HSE_Configuration HSE Configuration + * @{ + */ +/** + * @brief Macro to configure the External High Speed oscillator (HSE). + * @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this macro. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @note This function reset the CSSON bit, so if the clock security system(CSS) + * was previously enabled you have to enable it again after calling this + * function. + * @param __STATE__ specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator. + * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_HSE_CONFIG(__STATE__) \ + do { \ + if ((__STATE__) == RCC_HSE_ON) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if ((__STATE__) == RCC_HSE_OFF) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + else if ((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) +/** + * @} + */ + +/** @defgroup RCC_LSE_Configuration LSE Configuration + * @{ + */ + +/** + * @brief Macro to configure the External Low Speed oscillator (LSE). + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. + * User should request a transition to LSE Off first and then LSE On or LSE Bypass. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param __STATE__ specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator. + * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. + */ +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) +/** + * @} + */ + +/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration + * @{ + */ + +/** @brief Macros to enable or disable the RTC clock. + * @note These macros must be used only after the RTC clock source was selected. + */ +#define __HAL_RCC_RTC_ENABLE() (RCC->BDCR |= (RCC_BDCR_RTCEN)) +#define __HAL_RCC_RTC_DISABLE() (RCC->BDCR &= ~(RCC_BDCR_RTCEN)) + +/** @brief Macros to configure the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using the Power Backup Access macro before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the + * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by + * a Power On Reset (POR). + * @param __RTCCLKSource__ specifies the RTC clock source. + * This parameter can be one of the following values: + @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock. + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as + * RTC clock source). + */ +#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) + +#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \ + RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \ + } while (0) + +/** @brief Macro to get the RTC clock source. + * @retval The clock source can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER() + */ +#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) + +/** + * @brief Get the RTC and HSE clock divider (RTCPRE). + * @retval Returned value can be one of the following values: + * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected + * as RTC clock, where x:[2,31] + */ +#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL) + +/** @brief Macros to force or release the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_CSR register. + * @note The BKPSRAM is not affected by this reset. + */ +#define __HAL_RCC_BACKUPRESET_FORCE() (RCC->BDCR |= (RCC_BDCR_BDRST)) +#define __HAL_RCC_BACKUPRESET_RELEASE() (RCC->BDCR &= ~(RCC_BDCR_BDRST)) +/** + * @} + */ + +/** @defgroup RCC_PLL_Configuration PLL Configuration + * @{ + */ + +/** @brief Macros to enable or disable the main PLL. + * @note After enabling the main PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The main PLL can not be disabled if it is used as system clock source + * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON) +#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) +/** + * @} + */ + +/** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration + * @{ + */ + +/** @brief Macro to configure the I2S clock source (I2SCLK). + * @note This function must be called before enabling the I2S APB clock. + * @param __SOURCE__ specifies the I2S clock source. + * This parameter can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin + * used as I2S clock source. + */ +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) do {RCC->CFGR &= ~(RCC_CFGR_I2SSRC); \ + RCC->CFGR |= (__SOURCE__); \ + }while(0) + +/** @brief Macros to enable or disable the PLLI2S. + * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLI2S_ENABLE() (RCC->CR |= (RCC_CR_PLLI2SON)) +#define __HAL_RCC_PLLI2S_DISABLE() (RCC->CR &= ~(RCC_CR_PLLI2SON)) +/** + * @} + */ + +/** @defgroup RCC_Get_Clock_source Get Clock source + * @{ + */ +/** + * @brief Macro to configure the system clock source. + * @param __RCC_SYSCLKSOURCE__ specifies the system clock source. + * This parameter can be one of the following values: + * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. + * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source. + */ +#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__)) + +/** @brief Macro to get the clock source used as system clock. + * @retval The clock source used as system clock. The returned value can be one + * of the following: + * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. + * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock. + */ +#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS) + +/** + * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability. + * @note As the LSE is in the Backup domain and write access is denied to + * this domain after reset, you have to enable write access using + * HAL_PWR_EnableBkUpAccess() function before to configure the LSE + * (to be done once after reset). + * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability. + * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability. + * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability. + * @retval None + */ +#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDRIVE__) \ + (MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__RCC_LSEDRIVE__) )) + +/** @brief Macro to get the oscillator used as PLL clock source. + * @retval The oscillator used as PLL clock source. The returned value can be one + * of the following: + * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. + * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. + */ +#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC)) +/** + * @} + */ + +/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config + * @{ + */ + +/** @brief Macro to configure the MCO1 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) + +/** @brief Macro to configure the MCO2 clock. + * @param __MCOCLKSOURCE__ specifies the MCO clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param __MCODIV__ specifies the MCO clock prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + */ + +#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3))); +/** + * @} + */ + +/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management + * @brief macros to manage the specified RCC Flags and interrupts. + * @{ + */ + +/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) + +/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable + * the selected interrupts). + * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + */ +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) + +/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] + * bits to clear the selected interrupt pending bits. + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + */ +#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) + +/** @brief Check the RCC's interrupt has occurred or not. + * @param __INTERRUPT__ specifies the RCC interrupt source to check. + * This parameter can be one of the following values: + * @arg RCC_IT_LSIRDY: LSI ready interrupt. + * @arg RCC_IT_LSERDY: LSE ready interrupt. + * @arg RCC_IT_HSIRDY: HSI ready interrupt. + * @arg RCC_IT_HSERDY: HSE ready interrupt. + * @arg RCC_IT_PLLRDY: Main PLL ready interrupt. + * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt. + * @arg RCC_IT_CSS: Clock Security System interrupt + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, + * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. + */ +#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) + +/** @brief Check RCC flag is set or not. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready. + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready. + * @arg RCC_FLAG_PLLRDY: Main PLL clock ready. + * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready. + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready. + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready. + * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset. + * @arg RCC_FLAG_PINRST: Pin reset. + * @arg RCC_FLAG_PORRST: POR/PDR reset. + * @arg RCC_FLAG_SFTRST: Software reset. + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset. + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset. + * @arg RCC_FLAG_LPWRRST: Low Power reset. + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define RCC_FLAG_MASK ((uint8_t)0x1F) +#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0) + +/** + * @} + */ + +/** + * @} + */ + +/* Include RCC HAL Extension module */ +#include "stm32f7xx_hal_rcc_ex.h" + +/* Exported functions --------------------------------------------------------*/ + /** @addtogroup RCC_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions ******************************/ +HAL_StatusTypeDef HAL_RCC_DeInit(void); +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/** + * @} + */ + +/** @addtogroup RCC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral Control functions ************************************************/ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); +void HAL_RCC_EnableCSS(void); +void HAL_RCC_DisableCSS(void); +uint32_t HAL_RCC_GetSysClockFreq(void); +uint32_t HAL_RCC_GetHCLKFreq(void); +uint32_t HAL_RCC_GetPCLK1Freq(void); +uint32_t HAL_RCC_GetPCLK2Freq(void); +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); + +/* CSS NMI IRQ handler */ +void HAL_RCC_NMI_IRQHandler(void); + +/* User Callbacks in non blocking mode (IT mode) */ +void HAL_RCC_CSSCallback(void); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Constants RCC Private Constants + * @{ + */ +#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */ +#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +#define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ +#define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */ + +/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias + * @brief RCC registers bit address alias + * @{ + */ +/* CIR register byte 2 (Bits[15:8]) base address */ +#define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) + +/* CIR register byte 3 (Bits[23:16]) base address */ +#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) + +#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +/** + * @} + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15) + +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_BYPASS)) + +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYPASS)) + +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)) + +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) + +#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) + +#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ + ((SOURCE) == RCC_PLLSOURCE_HSE)) + +#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ + ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_PLLM_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 63)) + +#define IS_RCC_PLLN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) + +#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == RCC_PLLP_DIV2) || ((VALUE) == RCC_PLLP_DIV4) || \ + ((VALUE) == RCC_PLLP_DIV6) || ((VALUE) == RCC_PLLP_DIV8)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) + +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ + ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ + ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ + ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ + ((HCLK) == RCC_SYSCLK_DIV512)) + +#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) + +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ + ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ + ((PCLK) == RCC_HCLK_DIV16)) + +#define IS_RCC_MCO(MCOX) (((MCOX) == RCC_MCO1) || ((MCOX) == RCC_MCO2)) + + +#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ + ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK)) + +#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \ + ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)) + +#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \ + ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \ + ((DIV) == RCC_MCODIV_5)) +#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) + +#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \ + ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31)) + + +#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || \ + ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || \ + ((DRIVE) == RCC_LSEDRIVE_HIGH)) +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_RCC_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h index 558a743e..7f749fd4 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rcc_ex.h @@ -1,3555 +1,3555 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_RCC_EX_H -#define __STM32F7xx_HAL_RCC_EX_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ - - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ - - uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). - This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ - - uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. - This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -}RCC_PLLInitTypeDef; - -/** - * @brief PLLI2S Clock structure definition - */ -typedef struct -{ - uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) - uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. - This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. - This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -}RCC_PLLI2SInitTypeDef; - -/** - * @brief PLLSAI Clock structure definition - */ -typedef struct -{ - uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432. - This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - - uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 15. - This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) - uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock - This parameter must be a number between Min_Data = 2 and Max_Data = 7. - This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - - uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. - This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider - This parameter will be used only when PLLSAI is disabled */ -}RCC_PLLSAIInitTypeDef; - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ - - RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. - This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ - - uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ - - uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 - This parameter will be used only when PLLSAI is selected as Clock Source SAI */ - - uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. - This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ - - uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - - uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. - This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ - - uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. - This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ - - uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection - This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ - - uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection - This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ - - uint32_t Usart1ClockSelection; /*!< USART1 clock source - This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - - uint32_t Usart2ClockSelection; /*!< USART2 clock source - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ - - uint32_t Usart3ClockSelection; /*!< USART3 clock source - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - - uint32_t Uart4ClockSelection; /*!< UART4 clock source - This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ - - uint32_t Uart5ClockSelection; /*!< UART5 clock source - This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ - - uint32_t Usart6ClockSelection; /*!< USART6 clock source - This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ - - uint32_t Uart7ClockSelection; /*!< UART7 clock source - This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ - - uint32_t Uart8ClockSelection; /*!< UART8 clock source - This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< I2C1 clock source - This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ - - uint32_t I2c2ClockSelection; /*!< I2C2 clock source - This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ - - uint32_t I2c3ClockSelection; /*!< I2C3 clock source - This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - - uint32_t I2c4ClockSelection; /*!< I2C4 clock source - This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ - - uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source - This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t CecClockSelection; /*!< CEC clock source - This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ - - uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC - This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ - - uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source - This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) - uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source - This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source - This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ - - uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source - This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -}RCC_PeriphCLKInitTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection - * @{ - */ -#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) -#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) -#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) -#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) -#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) -#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) -#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) -#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) -#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) -#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) -#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) -#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) -#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) -#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) -#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) -#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) -#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) -#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) -#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) -#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) -#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) -#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) -#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider - * @{ - */ -#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) -#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) -#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) -#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) -/** - * @} - */ -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider - * @{ - */ -#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) -#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) -#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) -#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) -/** - * @} - */ - -/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR - * @{ - */ -#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) -#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 -#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 -#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR -/** - * @} - */ - -/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source - * @{ - */ -#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) -#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC - -/** - * @} - */ - -/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source - * @{ - */ -#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) -#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 -#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source - * @{ - */ -#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) -#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 -#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL -#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source - * @{ - */ -#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) -#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ -/** - * @} - */ - -/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source - * @{ - */ -#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) -#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 -#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 -#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL -/** - * @} - */ - -/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source - * @{ - */ -#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 -#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 -#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL -/** - * @} - */ - -/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source - * @{ - */ -#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 -#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 -#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL -/** - * @} - */ - -/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source - * @{ - */ -#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 -#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 -#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL -/** - * @} - */ - -/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source - * @{ - */ -#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 -#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 -#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL -/** - * @} - */ - -/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source - * @{ - */ -#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) -#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 -#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 -#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL -/** - * @} - */ - -/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source - * @{ - */ -#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 -#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 -#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL -/** - * @} - */ - -/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source - * @{ - */ -#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 -#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 -#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL -/** - * @} - */ - -/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source - * @{ - */ -#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 -#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source - * @{ - */ -#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 -#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 - -/** - * @} - */ - -/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source - * @{ - */ -#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 -#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source - * @{ - */ -#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 -#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source - * @{ - */ -#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 -#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 -#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL - -/** - * @} - */ - -/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source - * @{ - */ -#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) -#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL -/** - * @} - */ - -/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection - * @{ - */ -#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) -#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE -/** - * @} - */ - -/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source - * @{ - */ -#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL -/** - * @} - */ - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source - * @{ - */ -#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) -#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL -/** - * @} - */ -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source - * @{ - */ -#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) -#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL -/** - * @} - */ - -/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source - * @{ - */ -#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) -#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL -/** - * @} - */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) -/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source - * @{ - */ -#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) -#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) -/** - * @} - */ -#endif /* STM32F769xx || STM32F779xx */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros - * @{ - */ -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable - * @brief Enables or disables the AHB/APB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -/** @brief Enables or disables the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) -#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) -#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) -#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) -#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) -#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) -#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) -#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) -#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) -#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) -#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) -#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) -#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) -#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -/** - * @brief Enable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ETH_CLK_ENABLE() do { \ - __HAL_RCC_ETHMAC_CLK_ENABLE(); \ - __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ - __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ - } while(0) -/** - * @brief Disable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) -#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) -#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) -#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) -#define __HAL_RCC_ETH_CLK_DISABLE() do { \ - __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ - __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ - __HAL_RCC_ETHMAC_CLK_DISABLE(); \ - } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ - UNUSED(tmpreg); \ - __HAL_RCC_SYSCFG_CLK_ENABLE();\ - } while(0) - -#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) - -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) -#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) -#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_AES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) -#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ - -/** @brief Enables or disables the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) -#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) - -/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_RTC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CEC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) -#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) -#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) -#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) -#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) -#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) -#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) -#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) -#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) -#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) -#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) -#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) -#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) -#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) -#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) -#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) -#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) -#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) -#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) -#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) -#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) -#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) -#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) -#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) -#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ - -/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ - -#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ - UNUSED(tmpreg); \ - } while(0) - -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F769xx || STM32F779xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ - UNUSED(tmpreg); \ - } while(0) -#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ - -#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) -#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) -#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) -#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) -#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) -#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) -#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) -#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) -#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) -#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) -#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) -#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) -#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) -#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) -#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) -#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ - -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status - * @brief Get the enable or disable status of the AHB/APB peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -/** @brief Get the enable or disable status of the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) -#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) -#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) -#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) -#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) -#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -/** - * @brief Enable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) -#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) - -/** - * @brief Disable ETHERNET clock. - */ -#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) -#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ - __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Get the enable or disable status of the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) - -#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) -#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) - -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) -#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) -#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) -#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) -#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) -#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) -#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** @brief Get the enable or disable status of the AHB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) -#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) - -#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) -#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) - -/** @brief Get the enable or disable status of the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) -#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) -#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) -#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) -#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) -#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) - -#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) -#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) -#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -/** @brief Get the enable or disable status of the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - */ -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) -#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) -#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) -#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) -#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) -#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) -#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) -#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) -#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) -#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) -#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ - -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) -#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) -#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) -#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) -#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) -#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) -#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) -#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) -#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) -#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ - -/** - * @} - */ - -/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset - * @brief Forces or releases AHB/APB peripheral reset. - * @{ - */ - -/** @brief Force or release AHB1 peripheral reset. - */ -#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) -#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) -#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) - -#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) -#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) -#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) -#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) -#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) -#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) -#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) -#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) -#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) -#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) -#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) -#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) -#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) - -#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) -#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) -#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) -#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Force or release AHB2 peripheral reset. - */ -#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) - -#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) -#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) -#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) -#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) -#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) -#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) -#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) -#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) -#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Force or release AHB3 peripheral reset - */ -#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) -#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) -#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) - -#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) -#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) -#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) - -/** @brief Force or release APB1 peripheral reset. - */ -#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) -#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) - -#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) -#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) -#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) -#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) -#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) -#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) -#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) -#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) -#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) -#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) -#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) -#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) -#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) -#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) -#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) -#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) -#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) -#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) -#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) -#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) -#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) -#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) -#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) -#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) - -#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) -#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) -#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) -#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Force or release APB2 peripheral reset. - */ -#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) -#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) -#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) -#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) -#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) -#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ - -#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) -#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) -#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) -#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) -#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) -#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) -#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) -#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) -#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) -#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) -#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) -#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) -#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) -#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) -#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) -#endif /* STM32F769xx || STM32F779xx */ - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) -#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) -#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) -#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) -#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/** - * @} - */ - -/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable - * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. - */ -#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) -#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) -#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) -#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) -#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) -#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) - -#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) -#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) -#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) -#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) -#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) -#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) -#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) -#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) -#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) -#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) - -#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) -#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) -#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) -#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) -#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) -#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) -#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) -#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) - -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) - -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) -#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) - -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) -#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) -#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) -#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ - -/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) -#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) - -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) - -/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) -#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) -#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) -#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) -#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) -#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) -#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) -#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) -#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) -#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) -#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) -#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) -#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) -#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) -#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) -#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) - -#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) -#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) -#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) -#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) -#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) -#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) -#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) -#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) -#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) -#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) -#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) -#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) -#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) -#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) -#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) -#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) -#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) -#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) -#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) -#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) -#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) -#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) -#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) -#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -/** - * @} - */ - -/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status - * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - * @{ - */ - -/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) -#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) -#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) - -#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) -#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) -#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) -#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) -#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) -#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) -#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) -#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) -#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) -#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) -#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) -#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) -#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) -#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) -#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) -#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) -#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) -#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) - -#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) -#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) -#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) -#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) -#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) -#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) -#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) -#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) -#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) -#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) - -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) - -#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) - -#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) -#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) -#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) -#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) -#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ - -/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) -#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) - -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) - -/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) -#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) -#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) -#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) -#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) -#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) -#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) -#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) - -#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) -#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) -#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) -#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) -#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) -#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) -#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) -#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) -#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) -#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ - defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ - defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || - STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) -#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) -#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) -#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) -#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) -#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) -#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) -#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) -#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) -#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) -#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) -#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) -#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) -#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) - -#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) -#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) -#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) -#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. - * @note Peripheral clock gating in SLEEP mode can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. - */ -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) -#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) -#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) -#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) -#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) -#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) -#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) -#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) -#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) -#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) -#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) -#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) -#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) -#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) -#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) -#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) -#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) -#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) -#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) -#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) -#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) -#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) -#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) -#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) -#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) -#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) -#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) -#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#if defined (STM32F769xx) || defined (STM32F779xx) -#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) -#endif /* STM32F769xx || STM32F779xx */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) -#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) -#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -/** - * @} - */ - -/*------------------------------- PLL Configuration --------------------------*/ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on - * the System clock frequency. - * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - * @param __PLLR__ specifies the division factor for DSI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ - (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ - ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ - ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ - ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) -#else -/** @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * @param __RCC_PLLSource__ specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. - * @param __PLLM__ specifies the division factor for PLL VCO input clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency - * of 2 MHz to limit PLL jitter. - * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 100 and 432 MHz. - * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) - * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on - * the System clock frequency. - * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @note If the USB OTG FS is used in your application, you have to set the - * PLLQ parameter correctly to have 48 MHz clock for the USB. However, - * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work - * correctly. - */ -#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ - (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ - ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ - ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ - ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -/*---------------------------------------------------------------------------------------------*/ - -/** @brief Macro to configure the Timers clocks prescalers - * @param __PRESC__ specifies the Timers clocks prescalers selection - * This parameter can be one of the following values: - * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1 or 2, - * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to - * division by 4 or more. - * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is - * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, - * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding - * to division by 8 or more. - */ -#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ - RCC->DCKCFGR1 |= (__PRESC__); \ - }while(0) - -/** @brief Macros to Enable or Disable the PLLISAI. - * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) -#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -/** @brief Macro to configure the PLLSAI clock multiplication and division factors. - * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks - * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. - * @param __PLLSAIQ__ specifies the division factor for SAI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ - (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ - ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ - ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)) - -/** @brief Macro to configure the PLLI2S clock multiplication and division factors. - * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API) - * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLI2SQ__ specifies the division factor for SAI clock. - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @param __PLLI2SR__ specifies the division factor for I2S clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ - ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ - ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) -#else -/** @brief Macro to configure the PLLSAI clock multiplication and division factors. - * @note This function must be used only when the PLLSAI is disabled. - * @note PLLSAI clock source is common with the main PLL (configured in - * RCC_PLLConfig function ) - * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks - * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. - * @param __PLLSAIQ__ specifies the division factor for SAI clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @param __PLLSAIR__ specifies the division factor for LTDC clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - */ -#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ - (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ - ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ - ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ - ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)) - -/** @brief Macro to configure the PLLI2S clock multiplication and division factors. - * @note This macro must be used only when the PLLI2S is disabled. - * @note PLLI2S clock source is common with the main PLL (configured in - * HAL_RCC_ClockConfig() API) - * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. - * This parameter must be a number between Min_Data = 50 and Max_Data = 432. - * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO - * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. - * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. - * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. - * @param __PLLI2SQ__ specifies the division factor for SAI clock. - * This parameter must be a number between Min_Data = 2 and Max_Data = 15. - * @param __PLLI2SR__ specifies the division factor for I2S clock - * This parameter must be a number between Min_Data = 2 and Max_Data = 7. - * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz - * on the I2S clock frequency. - */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ - (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ - ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ - ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ - ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ - -/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. - * @note This function must be called before enabling the PLLI2S. - * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . - * This parameter must be a number between 1 and 32. - * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ - */ -#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) - -/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. - * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . - * This parameter must be a number between Min_Data = 1 and Max_Data = 32. - * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ - */ -#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) - -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ - defined (STM32F750xx) -/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. - * @note This function must be called before enabling the PLLSAI. - * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . - * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. - * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ - */ -#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -/** @brief Macro to configure SAI1 clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__ specifies the SAI1 clock source. - * This parameter can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin - * used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock - * used as SAI1 clock. - * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices - */ -#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) - -/** @brief Macro to get the SAI1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin - * used as SAI1 clock. - * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock - * used as SAI1 clock. - * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices - */ -#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) - -/** @brief Macro to configure SAI2 clock source selection. - * @note This function must be called before enabling PLLSAI, PLLI2S and - * the SAI clock. - * @param __SOURCE__ specifies the SAI2 clock source. - * This parameter can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin - * used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock - * used as SAI2 clock. - * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices - */ -#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) - - -/** @brief Macro to get the SAI2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used - * as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin - * used as SAI2 clock. - * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock - * used as SAI2 clock. - * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices - */ -#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) - - -/** @brief Enable PLLSAI_RDY interrupt. - */ -#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) - -/** @brief Disable PLLSAI_RDY interrupt. - */ -#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) - -/** @brief Clear the PLLSAI RDY interrupt pending bits. - */ -#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) - -/** @brief Check the PLLSAI RDY interrupt has occurred or not. - * @retval The new state (TRUE or FALSE). - */ -#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) - -/** @brief Check PLLSAI RDY flag is set or not. - * @retval The new state (TRUE or FALSE). - */ -#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) - -/** @brief Macro to Get I2S clock source selection. - * @retval The clock source can be one of the following values: - * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. - * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source - */ -#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) - -/** @brief Macro to configure the I2C1 clock (I2C1CLK). - * - * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock - * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock - * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock - */ -#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) - -/** @brief Macro to get the I2C1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock - * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock - * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock - */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) - -/** @brief Macro to configure the I2C2 clock (I2C2CLK). - * - * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock - * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock - * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock - */ -#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) - -/** @brief Macro to get the I2C2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock - * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock - * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock - */ -#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) - -/** @brief Macro to configure the I2C3 clock (I2C3CLK). - * - * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock - * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock - * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock - */ -#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) - -/** @brief macro to get the I2C3 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock - * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock - * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock - */ -#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) - -/** @brief Macro to configure the I2C4 clock (I2C4CLK). - * - * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. - * This parameter can be one of the following values: - * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock - * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock - * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock - */ -#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) - -/** @brief macro to get the I2C4 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock - * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock - * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock - */ -#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) - -/** @brief Macro to configure the USART1 clock (USART1CLK). - * - * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. - * This parameter can be one of the following values: - * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock - */ -#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) - -/** @brief macro to get the USART1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock - * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock - */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) - -/** @brief Macro to configure the USART2 clock (USART2CLK). - * - * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. - * This parameter can be one of the following values: - * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock - */ -#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) - -/** @brief macro to get the USART2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock - * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock - */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) - -/** @brief Macro to configure the USART3 clock (USART3CLK). - * - * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. - * This parameter can be one of the following values: - * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock - */ -#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) - -/** @brief macro to get the USART3 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock - * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock - */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) - - /** @brief Macro to configure the UART4 clock (UART4CLK). - * - * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. - * This parameter can be one of the following values: - * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock - */ -#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) - -/** @brief macro to get the UART4 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock - * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock - */ -#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) - - /** @brief Macro to configure the UART5 clock (UART5CLK). - * - * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. - * This parameter can be one of the following values: - * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock - */ -#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) - -/** @brief macro to get the UART5 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock - * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock - */ -#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) - - /** @brief Macro to configure the USART6 clock (USART6CLK). - * - * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. - * This parameter can be one of the following values: - * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock - */ -#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) - -/** @brief macro to get the USART6 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock - * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock - */ -#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) - - /** @brief Macro to configure the UART7 clock (UART7CLK). - * - * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. - * This parameter can be one of the following values: - * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock - */ -#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) - -/** @brief macro to get the UART7 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock - * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock - */ -#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) - -/** @brief Macro to configure the UART8 clock (UART8CLK). - * - * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. - * This parameter can be one of the following values: - * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock - */ -#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) - -/** @brief macro to get the UART8 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock - * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock - */ -#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) - -/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). - * - * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) - -/** @brief macro to get the LPTIM1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock - * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) - -/** @brief Macro to configure the CEC clock (CECCLK). - * - * @param __CEC_CLKSOURCE__ specifies the CEC clock source. - * This parameter can be one of the following values: - * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock - * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock - */ -#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) - -/** @brief macro to get the CEC clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock - * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock - */ -#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) - -/** @brief Macro to configure the CLK48 source (CLK48CLK). - * - * @param __CLK48_SOURCE__ specifies the CLK48 clock source. - * This parameter can be one of the following values: - * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source - * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source - */ -#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) - -/** @brief macro to get the CLK48 source. - * @retval The clock source can be one of the following values: - * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source - * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source - */ -#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) - -/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). - * - * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. - * This parameter can be one of the following values: - * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock - * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock - */ -#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) - -/** @brief macro to get the SDMMC1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock - * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock - */ -#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). - * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. - * This parameter can be one of the following values: - * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock - * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock - */ -#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) - -/** @brief macro to get the SDMMC2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock - * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock - */ -#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** @brief Macro to configure the DFSDM1 clock - * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock - * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock - */ -#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) - -/** @brief Macro to get the DFSDM1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock - * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock - */ -#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) - -/** @brief Macro to configure the DFSDM1 Audio clock - * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source. - * This parameter can be one of the following values: - * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock - * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock - */ -#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) - -/** @brief Macro to get the DFSDM1 Audio clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock - * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock - */ -#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F769xx) || defined (STM32F779xx) -/** @brief Macro to configure the DSI clock. - * @param __DSI_CLKSOURCE__ specifies the DSI clock source. - * This parameter can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. - */ -#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) - -/** @brief Macro to Get the DSI clock. - * @retval The clock source can be one of the following values: - * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. - * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. - */ -#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) -#endif /* STM32F769xx || STM32F779xx */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); -HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters - * @{ - */ -#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined(STM32F745xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ - (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined (STM32F765xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ - (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ - (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ - (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -#define IS_RCC_PERIPHCLOCK(SELECTION) \ - ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ - (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ - (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ - (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ - (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ - (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ - (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ - (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ - (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ - (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ - (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ - (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ - (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ - (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ - (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) -#endif /* STM32F746xx || STM32F756xx || STM32F750xx */ -#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ - defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) -#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ - ((VALUE) == RCC_PLLI2SP_DIV4) ||\ - ((VALUE) == RCC_PLLI2SP_DIV6) ||\ - ((VALUE) == RCC_PLLI2SP_DIV8)) -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ -#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) -#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ - ((VALUE) == RCC_PLLSAIP_DIV4) ||\ - ((VALUE) == RCC_PLLSAIP_DIV6) ||\ - ((VALUE) == RCC_PLLSAIP_DIV8)) -#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) -#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) - -#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) - -#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ - ((VALUE) == RCC_PLLSAIDIVR_4) ||\ - ((VALUE) == RCC_PLLSAIDIVR_8) ||\ - ((VALUE) == RCC_PLLSAIDIVR_16)) -#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) - -#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) - -#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_CECCLKSOURCE_LSE)) -#define IS_RCC_USART1CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) - -#define IS_RCC_USART2CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) -#define IS_RCC_USART3CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) - -#define IS_RCC_UART4CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) - -#define IS_RCC_UART5CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) - -#define IS_RCC_USART6CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ - ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) - -#define IS_RCC_UART7CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) - -#define IS_RCC_UART8CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) -#define IS_RCC_I2C1CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) -#define IS_RCC_I2C2CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) - -#define IS_RCC_I2C3CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) -#define IS_RCC_I2C4CLKSOURCE(SOURCE) \ - (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) -#define IS_RCC_LPTIM1CLK(SOURCE) \ - (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) -#define IS_RCC_CLK48SOURCE(SOURCE) \ - (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ - ((SOURCE) == RCC_CLK48SOURCE_PLL)) -#define IS_RCC_TIMPRES(VALUE) \ - (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ - ((VALUE) == RCC_TIMPRES_ACTIVATED)) - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ - defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx) -#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) -#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) - -#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ - ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) - -#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ - ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) - -#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ - ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) - -#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ - ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) -#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ - -#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ - ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_RCC_EX_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc_ex.h + * @author MCD Application Team + * @brief Header file of RCC HAL Extension module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_RCC_EX_H +#define __STM32F7xx_HAL_RCC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup RCCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Types RCCEx Exported Types + * @{ + */ + +/** + * @brief RCC PLL configuration structure definition + */ +typedef struct +{ + uint32_t PLLState; /*!< The new state of the PLL. + This parameter can be a value of @ref RCC_PLL_Config */ + + uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. + This parameter must be a value of @ref RCC_PLL_Clock_Source */ + + uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 63 */ + + uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 */ + + uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK). + This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ + + uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks. + This parameter must be a number between Min_Data = 2 and Max_Data = 15 */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t PLLR; /*!< PLLR: Division factor for DSI clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7 */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +}RCC_PLLInitTypeDef; + +/** + * @brief PLLI2S Clock structure definition + */ +typedef struct +{ + uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. + This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +}RCC_PLLI2SInitTypeDef; + +/** + * @brief PLLSAI Clock structure definition + */ +typedef struct +{ + uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + + uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock. + This parameter must be a number between Min_Data = 2 and Max_Data = 15. + This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock + This parameter must be a number between Min_Data = 2 and Max_Data = 7. + This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. + This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider + This parameter will be used only when PLLSAI is disabled */ +}RCC_PLLSAIInitTypeDef; + +/** + * @brief RCC extended clocks structure definition + */ +typedef struct +{ + uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. + This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ + + RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */ + + RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters. + This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */ + + uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + + uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock. + This parameter must be a number between Min_Data = 1 and Max_Data = 32 + This parameter will be used only when PLLSAI is selected as Clock Source SAI */ + + uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock. + This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */ + + uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ + + uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection. + This parameter can be a value of @ref RCCEx_I2S_Clock_Source */ + + uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection. + This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */ + + uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ + + uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection + This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ + + uint32_t Usart1ClockSelection; /*!< USART1 clock source + This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ + + uint32_t Usart2ClockSelection; /*!< USART2 clock source + This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ + + uint32_t Usart3ClockSelection; /*!< USART3 clock source + This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ + + uint32_t Uart4ClockSelection; /*!< UART4 clock source + This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ + + uint32_t Uart5ClockSelection; /*!< UART5 clock source + This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ + + uint32_t Usart6ClockSelection; /*!< USART6 clock source + This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ + + uint32_t Uart7ClockSelection; /*!< UART7 clock source + This parameter can be a value of @ref RCCEx_UART7_Clock_Source */ + + uint32_t Uart8ClockSelection; /*!< UART8 clock source + This parameter can be a value of @ref RCCEx_UART8_Clock_Source */ + + uint32_t I2c1ClockSelection; /*!< I2C1 clock source + This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ + + uint32_t I2c2ClockSelection; /*!< I2C2 clock source + This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ + + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ + + uint32_t I2c4ClockSelection; /*!< I2C4 clock source + This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ + + uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source + This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ + + uint32_t CecClockSelection; /*!< CEC clock source + This parameter can be a value of @ref RCCEx_CEC_Clock_Source */ + + uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC + This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */ + + uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source + This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) + uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source + This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */ + + uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source + This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +}RCC_PeriphCLKInitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants + * @{ + */ + +/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection + * @{ + */ +#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U) +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U) +#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U) +#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U) +#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U) +#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U) +#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U) +#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U) +#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U) +#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U) +#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U) +#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U) +#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U) +#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U) +#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U) +#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U) +#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U) +#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U) +#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U) +#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U) +#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U) +#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U) +#define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U) +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider + * @{ + */ +#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U) +/** + * @} + */ +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider + * @{ + */ +#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U) +#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U) +#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U) +/** + * @} + */ + +/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR + * @{ + */ +#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U) +#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0 +#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1 +#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR +/** + * @} + */ + +/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source + * @{ + */ +#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U) +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC + +/** + * @} + */ + +/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source + * @{ + */ +#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) +#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0 +#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1 +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source + * @{ + */ +#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U) +#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0 +#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1 +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL +#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source + * @{ + */ +#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U) +#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/ +/** + * @} + */ + +/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source + * @{ + */ +#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0 +#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1 +#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source + * @{ + */ +#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0 +#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1 +#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source + * @{ + */ +#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0 +#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1 +#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source + * @{ + */ +#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0 +#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1 +#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source + * @{ + */ +#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0 +#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1 +#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL +/** + * @} + */ + +/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source + * @{ + */ +#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0 +#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1 +#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source + * @{ + */ +#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0 +#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1 +#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL +/** + * @} + */ + +/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source + * @{ + */ +#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0 +#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1 +#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL +/** + * @} + */ + +/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source + * @{ + */ +#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0 +#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source + * @{ + */ +#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0 +#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1 + +/** + * @} + */ + +/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0 +#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source + * @{ + */ +#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0 +#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1 +/** + * @} + */ + +/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source + * @{ + */ +#define RCC_LPTIM1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) +#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 +#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 +#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL + +/** + * @} + */ + +/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source + * @{ + */ +#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U) +#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL +/** + * @} + */ + +/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection + * @{ + */ +#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U) +#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE +/** + * @} + */ + +/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source + * @{ + */ +#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL +/** + * @} + */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +/** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source + * @{ + */ +#define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U) +#define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL +/** + * @} + */ +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source + * @{ + */ +#define RCC_DFSDM1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U) +#define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL +/** + * @} + */ + +/** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source + * @{ + */ +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U) +#define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL +/** + * @} + */ +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source + * @{ + */ +#define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U) +#define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL) +/** + * @} + */ +#endif /* STM32F769xx || STM32F779xx */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros + * @{ + */ +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable + * @brief Enables or disables the AHB/APB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +/** @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN)) +#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN)) +#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN)) +#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN)) +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN)) +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN)) +#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN)) +#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN)) +#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN)) +#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN)) +#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ETH_CLK_ENABLE() do { \ + __HAL_RCC_ETHMAC_CLK_ENABLE(); \ + __HAL_RCC_ETHMACTX_CLK_ENABLE(); \ + __HAL_RCC_ETHMACRX_CLK_ENABLE(); \ + } while(0) +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN)) +#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN)) +#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN)) +#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN)) +#define __HAL_RCC_ETH_CLK_DISABLE() do { \ + __HAL_RCC_ETHMACTX_CLK_DISABLE(); \ + __HAL_RCC_ETHMACRX_CLK_DISABLE(); \ + __HAL_RCC_ETHMAC_CLK_DISABLE(); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\ + UNUSED(tmpreg); \ + } while(0) +#define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\ + UNUSED(tmpreg); \ + __HAL_RCC_SYSCFG_CLK_ENABLE();\ + } while(0) + +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN)) +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_HASH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN)) +#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN)) +#endif /* STM32F756x || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_FMC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_QSPI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN)) +#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN)) + +/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM12_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM13_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM14_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_DAC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART7_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_UART8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CAN2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CEC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN)) +#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN)) +#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN)) +#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN)) +#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN)) +#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN)) +#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN)) +#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN)) +#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN)) +#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN)) +#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F750xx */ + +/** @brief Enable or disable the High Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_USART6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || || STM32F730xx */ + +#define __HAL_RCC_ADC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_ADC3_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI4_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM9_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM10_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_TIM11_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SPI5_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\ + UNUSED(tmpreg); \ + } while(0) + +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MDIO_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_OTGPHYCEN);\ + UNUSED(tmpreg); \ + } while(0) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) +#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) +#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN)) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN)) +#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN)) +#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN)) +#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN)) +#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN)) +#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN)) +#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) +#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN)) +#define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_OTGPHYCEN)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status + * @brief Get the enable or disable status of the AHB/APB peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @{ + */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET) +#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET) +#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET) +#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET) +#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** + * @brief Enable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET) +#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) + +/** + * @brief Disable ETHERNET clock. + */ +#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET) +#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \ + __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET) + +#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) +#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) +#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) + +#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET) +#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET) + +/** @brief Get the enable or disable status of the APB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET) + +#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET) +#define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +/** @brief Get the enable or disable status of the APB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) != RESET) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_OTGPHYCEN)) == RESET) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +/** + * @} + */ + +/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset + * @brief Forces or releases AHB/APB peripheral reset. + * @{ + */ + +/** @brief Force or release AHB1 peripheral reset. + */ +#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST)) + +#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST)) +#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST)) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST)) +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST)) +#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST)) +#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST)) +#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST)) + +#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST)) +#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST)) +#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST)) +#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release AHB2 peripheral reset. + */ +#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST)) + +#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST)) +#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST)) + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST)) +#define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST)) +#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST)) +#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST)) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST)) +#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release AHB3 peripheral reset + */ +#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU) +#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST)) + +#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) +#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST)) +#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST)) + +/** @brief Force or release APB1 peripheral reset. + */ +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST)) +#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST)) +#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST)) +#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST)) +#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST)) +#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST)) +#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST)) +#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST)) +#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST)) + +#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST)) +#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST)) +#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST)) +#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Force or release APB2 peripheral reset. + */ +#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_OTGPHYCRST)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) +#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST)) +#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST)) +#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST)) +#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST)) +#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST)) +#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST)) +#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) +#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F723xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_OTGPHYC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_OTGPHYCRST)) +#endif /* STM32F723xx || STM32F733xx || STM32F730xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST)) +#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST)) +#endif /* STM32F769xx || STM32F779xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST)) +#define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST)) +#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST)) +#define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/** + * @} + */ + +/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable + * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode. + */ +#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN)) + +#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN)) +#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN)) +#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN)) +#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN)) +#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN)) +#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN)) +#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN)) +#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN)) +#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN)) +#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN)) +#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN)) +#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN)) + +#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN)) +#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN)) +#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN)) +#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN)) +#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN)) +#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN)) +#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN)) +#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN)) +#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN)) + +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN)) +#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN)) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN)) + +#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN)) +#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN)) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN)) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN)) +#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN)) + +#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN)) +#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN)) + +/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN)) +#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN)) +#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN)) +#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN)) +#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN)) +#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN)) +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN)) +#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN)) +#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN)) +#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN)) +#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN)) +#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN)) +#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN)) +#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN)) +#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN)) + +#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN)) +#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN)) +#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN)) +#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) +#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN)) +#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN)) +#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN)) +#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN)) +#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN)) +#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN)) +#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN)) +#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN)) +#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN)) +#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN)) +#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) +#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)|| defined (STM32F750xx) +#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN)) +#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN)) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN)) +#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN)) +#define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN)) +#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) +#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @} + */ + +/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status + * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @{ + */ + +/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET) +#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET) +#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET) + +#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET) +#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET) +#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET) +#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET) +#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET) +#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET) +#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) +#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) +#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) +#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) +#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET) +#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET) +#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET) +#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET) +#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET) +#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET) + +#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET) +#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET) +#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) +#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) +#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) +#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET) +#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET) +#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET) +#define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET) +#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET) + +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET) +#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET) + +#if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET) + +#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET) +#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET) +#endif /* STM32F756xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined(STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) != RESET) +#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AESLPEN)) == RESET) +#endif /* STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET) +#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET) + +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET) +#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET) + +/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET) + +#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET) +#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET) +#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET) +#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET) +#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET) +#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET) +#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET) +#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET) +#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET) +#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET) +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\ + defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\ + defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || + STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET) +#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET) +#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET) +#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET) +#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET) +#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET) +#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET) +#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET) +#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET) +#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET) +#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET) +#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET) +#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET) + +#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET) +#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET) +#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET) +#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET) +#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) +#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) +#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET) +#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET) +#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET) +#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET) +#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET) +#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET) +#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET) +#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET) +#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET) +#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET) +#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET) +#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET) +#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) +#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) +#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#if defined (STM32F769xx) || defined (STM32F779xx) +#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET) +#endif /* STM32F769xx || STM32F779xx */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET) +#define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) +#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +/** + * @} + */ + +/*------------------------------- PLL Configuration --------------------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + * @param __PLLR__ specifies the division factor for DSI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \ + (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \ + ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos))) +#else +/** @brief Macro to configure the main PLL clock source, multiplication and division factors. + * @note This function must be used only when the main PLL is disabled. + * @param __RCC_PLLSource__ specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S. + * @param __PLLM__ specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLN parameter correctly to ensure that the VCO + * output frequency is between 100 and 432 MHz. + * @param __PLLP__ specifies the division factor for main system clock (SYSCLK) + * This parameter must be a number in the range {2, 4, 6, or 8}. + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on + * the System clock frequency. + * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @note If the USB OTG FS is used in your application, you have to set the + * PLLQ parameter correctly to have 48 MHz clock for the USB. However, + * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work + * correctly. + */ +#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \ + (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \ + ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \ + ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \ + ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ +/*---------------------------------------------------------------------------------------------*/ + +/** @brief Macro to configure the Timers clocks prescalers + * @param __PRESC__ specifies the Timers clocks prescalers selection + * This parameter can be one of the following values: + * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1 or 2, + * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to + * division by 4 or more. + * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is + * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, + * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding + * to division by 8 or more. + */ +#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\ + RCC->DCKCFGR1 |= (__PRESC__); \ + }while(0) + +/** @brief Macros to Enable or Disable the PLLISAI. + * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION)) +#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)) + +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SQ__ specifies the division factor for SAI clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) +#else +/** @brief Macro to configure the PLLSAI clock multiplication and division factors. + * @note This function must be used only when the PLLSAI is disabled. + * @note PLLSAI clock source is common with the main PLL (configured in + * RCC_PLLConfig function ) + * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider. + * @param __PLLSAIQ__ specifies the division factor for SAI clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLSAIR__ specifies the division factor for LTDC clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + */ +#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \ + (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\ + ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\ + ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\ + ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)) + +/** @brief Macro to configure the PLLI2S clock multiplication and division factors. + * @note This macro must be used only when the PLLI2S is disabled. + * @note PLLI2S clock source is common with the main PLL (configured in + * HAL_RCC_ClockConfig() API) + * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock. + * This parameter must be a number between Min_Data = 50 and Max_Data = 432. + * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO + * output frequency is between Min_Data = 100 and Max_Data = 432 MHz. + * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock. + * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider. + * @param __PLLI2SQ__ specifies the division factor for SAI clock. + * This parameter must be a number between Min_Data = 2 and Max_Data = 15. + * @param __PLLI2SR__ specifies the division factor for I2S clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 7. + * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz + * on the I2S clock frequency. + */ +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \ + (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\ + ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\ + ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\ + ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + +/** @brief Macro to configure the SAI clock Divider coming from PLLI2S. + * @note This function must be called before enabling the PLLI2S. + * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock . + * This parameter must be a number between 1 and 32. + * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ + */ +#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1)) + +/** @brief Macro to configure the SAI clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock . + * This parameter must be a number between Min_Data = 1 and Max_Data = 32. + * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8)) + +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) ||\ + defined (STM32F750xx) +/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI. + * @note This function must be called before enabling the PLLSAI. + * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock . + * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR. + * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ + */ +#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +/** @brief Macro to configure SAI1 clock source selection. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__)) + +/** @brief Macro to get the SAI1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI1 clock. + * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI1 clock. + * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL))) + +/** @brief Macro to configure SAI2 clock source selection. + * @note This function must be called before enabling PLLSAI, PLLI2S and + * the SAI clock. + * @param __SOURCE__ specifies the SAI2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__)) + + +/** @brief Macro to get the SAI2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used + * as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin + * used as SAI2 clock. + * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock + * used as SAI2 clock. + * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices + */ +#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL))) + + +/** @brief Enable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Disable PLLSAI_RDY interrupt. + */ +#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE)) + +/** @brief Clear the PLLSAI RDY interrupt pending bits. + */ +#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF)) + +/** @brief Check the PLLSAI RDY interrupt has occurred or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE)) + +/** @brief Check PLLSAI RDY flag is set or not. + * @retval The new state (TRUE or FALSE). + */ +#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY)) + +/** @brief Macro to Get I2S clock source selection. + * @retval The clock source can be one of the following values: + * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. + * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source + */ +#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)) + +/** @brief Macro to configure the I2C1 clock (I2C1CLK). + * + * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock + */ +#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) + +/** @brief Macro to get the I2C1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock + * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock + */ +#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL))) + +/** @brief Macro to configure the I2C2 clock (I2C2CLK). + * + * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock + */ +#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) + +/** @brief Macro to get the I2C2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock + * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock + */ +#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL))) + +/** @brief Macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) + +/** @brief macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL))) + +/** @brief Macro to configure the I2C4 clock (I2C4CLK). + * + * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock + */ +#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) + +/** @brief macro to get the I2C4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock + * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock + */ +#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL))) + +/** @brief Macro to configure the USART1 clock (USART1CLK). + * + * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) + +/** @brief macro to get the USART1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock + * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock + */ +#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL))) + +/** @brief Macro to configure the USART2 clock (USART2CLK). + * + * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) + +/** @brief macro to get the USART2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock + * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock + */ +#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL))) + +/** @brief Macro to configure the USART3 clock (USART3CLK). + * + * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) + +/** @brief macro to get the USART3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock + * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock + */ +#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL))) + + /** @brief Macro to configure the UART4 clock (UART4CLK). + * + * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) + +/** @brief macro to get the UART4 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock + * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock + */ +#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL))) + + /** @brief Macro to configure the UART5 clock (UART5CLK). + * + * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) + +/** @brief macro to get the UART5 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock + * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock + */ +#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL))) + + /** @brief Macro to configure the USART6 clock (USART6CLK). + * + * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. + * This parameter can be one of the following values: + * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) + +/** @brief macro to get the USART6 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock + * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock + */ +#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL))) + + /** @brief Macro to configure the UART7 clock (UART7CLK). + * + * @param __UART7_CLKSOURCE__ specifies the UART7 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__)) + +/** @brief macro to get the UART7 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock + * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock + */ +#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL))) + +/** @brief Macro to configure the UART8 clock (UART8CLK). + * + * @param __UART8_CLKSOURCE__ specifies the UART8 clock source. + * This parameter can be one of the following values: + * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__)) + +/** @brief macro to get the UART8 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock + * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock + */ +#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL))) + +/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). + * + * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) + +/** @brief macro to get the LPTIM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock + * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock + */ +#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))) + +/** @brief Macro to configure the CEC clock (CECCLK). + * + * @param __CEC_CLKSOURCE__ specifies the CEC clock source. + * This parameter can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock + */ +#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__)) + +/** @brief macro to get the CEC clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock + * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock + */ +#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))) + +/** @brief Macro to configure the CLK48 source (CLK48CLK). + * + * @param __CLK48_SOURCE__ specifies the CLK48 clock source. + * This parameter can be one of the following values: + * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source + */ +#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__)) + +/** @brief macro to get the CLK48 source. + * @retval The clock source can be one of the following values: + * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source + * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source + */ +#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))) + +/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK). + * + * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock + * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock + */ +#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__)) + +/** @brief macro to get the SDMMC1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock + * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock + */ +#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL))) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK). + * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source. + * This parameter can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__)) + +/** @brief macro to get the SDMMC2 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock + * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock + */ +#define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL))) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** @brief Macro to configure the DFSDM1 clock + * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock + * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock + */ +#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM1 clock + * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock + */ +#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL))) + +/** @brief Macro to configure the DFSDM1 Audio clock + * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source. + * This parameter can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__)) + +/** @brief Macro to get the DFSDM1 Audio clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock + * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock + */ +#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL))) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F769xx) || defined (STM32F779xx) +/** @brief Macro to configure the DSI clock. + * @param __DSI_CLKSOURCE__ specifies the DSI clock source. + * This parameter can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__))) + +/** @brief Macro to Get the DSI clock. + * @retval The clock source can be one of the following values: + * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. + * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. + */ +#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL)) +#endif /* STM32F769xx || STM32F779xx */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void); +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit); +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters + * @{ + */ +#if defined(STM32F756xx) || defined(STM32F746xx) || defined(STM32F750xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32F745xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F765xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \ + (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F746xx || STM32F756xx || STM32F750xx */ +#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || defined (STM32F767xx) || \ + defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) +#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\ + ((VALUE) == RCC_PLLI2SP_DIV4) ||\ + ((VALUE) == RCC_PLLI2SP_DIV6) ||\ + ((VALUE) == RCC_PLLI2SP_DIV8)) +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ +#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432)) +#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\ + ((VALUE) == RCC_PLLSAIP_DIV4) ||\ + ((VALUE) == RCC_PLLSAIP_DIV6) ||\ + ((VALUE) == RCC_PLLSAIP_DIV8)) +#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) +#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) + +#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32)) + +#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\ + ((VALUE) == RCC_PLLSAIDIVR_4) ||\ + ((VALUE) == RCC_PLLSAIDIVR_8) ||\ + ((VALUE) == RCC_PLLSAIDIVR_16)) +#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_I2SCLKSOURCE_EXT)) + +#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48)) + +#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \ + ((SOURCE) == RCC_CECCLKSOURCE_LSE)) +#define IS_RCC_USART1CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) + +#define IS_RCC_USART2CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) +#define IS_RCC_USART3CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART3CLKSOURCE_HSI)) + +#define IS_RCC_UART4CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART4CLKSOURCE_HSI)) + +#define IS_RCC_UART5CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART5CLKSOURCE_HSI)) + +#define IS_RCC_USART6CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_USART6CLKSOURCE_HSI)) + +#define IS_RCC_UART7CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART7CLKSOURCE_HSI)) + +#define IS_RCC_UART8CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \ + ((SOURCE) == RCC_UART8CLKSOURCE_HSI)) +#define IS_RCC_I2C1CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) +#define IS_RCC_I2C2CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)) + +#define IS_RCC_I2C3CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)) +#define IS_RCC_I2C4CLKSOURCE(SOURCE) \ + (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ + ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)) +#define IS_RCC_LPTIM1CLK(SOURCE) \ + (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)) +#define IS_RCC_CLK48SOURCE(SOURCE) \ + (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \ + ((SOURCE) == RCC_CLK48SOURCE_PLL)) +#define IS_RCC_TIMPRES(VALUE) \ + (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \ + ((VALUE) == RCC_TIMPRES_ACTIVATED)) + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F745xx) ||\ + defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F730xx) || defined (STM32F750xx) +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN)) +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F745xx || STM32F746xx || STM32F756xx || STM32F750xx || STM32F730xx */ + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7)) + +#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC)) + +#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \ + ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC)) + +#define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK2) || \ + ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK)) + +#define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \ + ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F730xx) +#define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \ + ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48)) +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F730xx */ + +#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\ + ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY)) +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_RCC_EX_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h deleted file mode 100644 index 4c128035..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rng.h +++ /dev/null @@ -1,361 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rng.h - * @author MCD Application Team - * @brief Header file of RNG HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_RNG_H -#define STM32F7xx_HAL_RNG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined (RNG) - -/** @defgroup RNG RNG - * @brief RNG HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RNG_Exported_Types RNG Exported Types - * @{ - */ - -/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition - * @{ - */ - -/** - * @} - */ - -/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition - * @{ - */ -typedef enum -{ - HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */ - HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */ - HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */ - HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */ - HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */ - -} HAL_RNG_StateTypeDef; - -/** - * @} - */ - -/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition - * @{ - */ -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -typedef struct __RNG_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ -{ - RNG_TypeDef *Instance; /*!< Register base address */ - - HAL_LockTypeDef Lock; /*!< RNG locking object */ - - __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - - __IO uint32_t ErrorCode; /*!< RNG Error code */ - - uint32_t RandomNumber; /*!< Last Generated RNG Data */ - -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) - void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */ - void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */ - - void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */ - void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */ -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - -} RNG_HandleTypeDef; - -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -/** - * @brief HAL RNG Callback ID enumeration definition - */ -typedef enum -{ - HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */ - - HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */ - HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */ - -} HAL_RNG_CallbackIDTypeDef; - -/** - * @brief HAL RNG Callback pointer definition - */ -typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */ -typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */ - -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Exported_Constants RNG Exported Constants - * @{ - */ - -/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition - * @{ - */ -#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */ -#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */ -#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */ -/** - * @} - */ - -/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition - * @{ - */ -#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */ -#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */ -#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */ -/** - * @} - */ - -/** @defgroup RNG_Error_Definition RNG Error Definition - * @{ - */ -#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ -#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ -#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ -#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ -#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup RNG_Exported_Macros RNG Exported Macros - * @{ - */ - -/** @brief Reset RNG handle state - * @param __HANDLE__ RNG Handle - * @retval None - */ -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_RNG_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - -/** - * @brief Enables the RNG peripheral. - * @param __HANDLE__ RNG Handle - * @retval None - */ -#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN) - -/** - * @brief Disables the RNG peripheral. - * @param __HANDLE__ RNG Handle - * @retval None - */ -#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) - -/** - * @brief Check the selected RNG flag status. - * @param __HANDLE__ RNG Handle - * @param __FLAG__ RNG flag - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data ready - * @arg RNG_FLAG_CECS: Clock error current status - * @arg RNG_FLAG_SECS: Seed error current status - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clears the selected RNG flag status. - * @param __HANDLE__ RNG handle - * @param __FLAG__ RNG flag to clear - * @note WARNING: This is a dummy macro for HAL code alignment, - * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. - * @retval None - */ -#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ - -/** - * @brief Enables the RNG interrupts. - * @param __HANDLE__ RNG Handle - * @retval None - */ -#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE) - -/** - * @brief Disables the RNG interrupts. - * @param __HANDLE__ RNG Handle - * @retval None - */ -#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) - -/** - * @brief Checks whether the specified RNG interrupt has occurred or not. - * @param __HANDLE__ RNG Handle - * @param __INTERRUPT__ specifies the RNG interrupt status flag to check. - * This parameter can be one of the following values: - * @arg RNG_IT_DRDY: Data ready interrupt - * @arg RNG_IT_CEI: Clock error interrupt - * @arg RNG_IT_SEI: Seed error interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Clear the RNG interrupt status flags. - * @param __HANDLE__ RNG Handle - * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear. - * This parameter can be one of the following values: - * @arg RNG_IT_CEI: Clock error interrupt - * @arg RNG_IT_SEI: Seed error interrupt - * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY. - * @retval None - */ -#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Exported_Functions RNG Exported Functions - * @{ - */ - -/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions - * @{ - */ -HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); -HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng); -void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); -void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, - pRNG_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions - * @{ - */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef - *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef - *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); - -void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); -void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); -void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); - -/** - * @} - */ - -/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions - * @{ - */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Private_Macros RNG Private Macros - * @{ - */ -#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \ - ((IT) == RNG_IT_SEI)) - -#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ - ((FLAG) == RNG_FLAG_CECS) || \ - ((FLAG) == RNG_FLAG_SECS)) - -/** - * @} - */ - -/** - * @} - */ - -#endif /* RNG */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_RNG_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h deleted file mode 100644 index 73ad5363..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc.h +++ /dev/null @@ -1,921 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rtc.h - * @author MCD Application Team - * @brief Header file of RTC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_RTC_H -#define STM32F7xx_HAL_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Types RTC Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */ - HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */ - HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ - HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ - HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ -} HAL_RTCStateTypeDef; - -/** - * @brief RTC Configuration Structure definition - */ -typedef struct -{ - uint32_t HourFormat; /*!< Specifies the RTC Hour Format. - This parameter can be a value of @ref RTC_Hour_Formats */ - - uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ - - uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */ - - uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. - This parameter can be a value of @ref RTC_Output_selection_Definitions */ - - uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal. - This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ - - uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. - This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -} RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_AM_PM_Definitions */ - - uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. - This parameter corresponds to a time unit range between [0-1] Second - with [1 Sec / SecondFraction +1] granularity */ - - uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content - corresponding to Synchronous prescaler factor value (PREDIV_S) - This parameter corresponds to a time unit range between [0-1] Second - with [1 Sec / SecondFraction +1] granularity. - This field will be used only by HAL_RTC_GetTime function */ - - uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight - Saving Time, please use HAL_RTC_DST_xxx functions */ - - uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight - Saving Time, please use HAL_RTC_DST_xxx functions */ -} RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format). - This parameter can be a value of @ref RTC_Month_Date_Definitions */ - - uint8_t Date; /*!< Specifies the RTC Date. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ - - uint8_t Year; /*!< Specifies the RTC Date Year. - This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ - -} RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */ - - uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_AlarmMask_Definitions */ - - uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks. - This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ - - uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ - - uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. - If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. - If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */ - - uint32_t Alarm; /*!< Specifies the alarm . - This parameter can be a value of @ref RTC_Alarms_Definitions */ -} RTC_AlarmTypeDef; - -/** - * @brief RTC Handle Structure definition - */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -typedef struct __RTC_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ -{ - RTC_TypeDef *Instance; /*!< Register base address */ - - RTC_InitTypeDef Init; /*!< RTC required parameters */ - - HAL_LockTypeDef Lock; /*!< RTC locking object */ - - __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - void (* AlarmAEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ - - void (* AlarmBEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ - - void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */ - - void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ - - void (* Tamper1EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ - - void (* Tamper2EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ - - void (* Tamper3EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */ - - void (* MspInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ - - void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ - -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -} RTC_HandleTypeDef; - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL RTC Callback ID enumeration definition - */ -typedef enum -{ - HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */ - HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ - HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */ - HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */ - HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ - HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ - HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */ - HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ - HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ -} HAL_RTC_CallbackIDTypeDef; - -/** - * @brief HAL RTC Callback pointer definition - */ -typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Constants RTC Exported Constants - * @{ - */ - -/** @defgroup RTC_Hour_Formats RTC Hour Formats - * @{ - */ -#define RTC_HOURFORMAT_24 0x00000000U -#define RTC_HOURFORMAT_12 RTC_CR_FMT -/** - * @} - */ - -/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions - * @{ - */ -#define RTC_OUTPUT_DISABLE 0x00000000U -#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 -#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 -#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL -/** - * @} - */ - -/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions - * @{ - */ -#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U -#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL -/** - * @} - */ - -/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT - * @{ - */ -#define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U -#define RTC_OUTPUT_TYPE_PUSHPULL RTC_OR_ALARMTYPE -/** - * @} - */ - -/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions - * @{ - */ -#define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x01) -/** - * @} - */ - -/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions - * @{ - */ -#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H -#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H -#define RTC_DAYLIGHTSAVING_NONE 0x00000000U -/** - * @} - */ - -/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions - * @{ - */ -#define RTC_STOREOPERATION_RESET 0x00000000U -#define RTC_STOREOPERATION_SET RTC_CR_BKP -/** - * @} - */ - -/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions - * @{ - */ -#define RTC_FORMAT_BIN 0x00000000U -#define RTC_FORMAT_BCD 0x00000001U -/** - * @} - */ - -/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format) - * @{ - */ -#define RTC_MONTH_JANUARY ((uint8_t)0x01) -#define RTC_MONTH_FEBRUARY ((uint8_t)0x02) -#define RTC_MONTH_MARCH ((uint8_t)0x03) -#define RTC_MONTH_APRIL ((uint8_t)0x04) -#define RTC_MONTH_MAY ((uint8_t)0x05) -#define RTC_MONTH_JUNE ((uint8_t)0x06) -#define RTC_MONTH_JULY ((uint8_t)0x07) -#define RTC_MONTH_AUGUST ((uint8_t)0x08) -#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09) -#define RTC_MONTH_OCTOBER ((uint8_t)0x10) -#define RTC_MONTH_NOVEMBER ((uint8_t)0x11) -#define RTC_MONTH_DECEMBER ((uint8_t)0x12) -/** - * @} - */ - -/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions - * @{ - */ -#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) -#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02) -#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03) -#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04) -#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05) -#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) -#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) -/** - * @} - */ - -/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions - * @{ - */ -#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL -/** - * @} - */ - -/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions - * @{ - */ -#define RTC_ALARMMASK_NONE 0x00000000U -#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 -#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 -#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 -#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \ - RTC_ALARMMASK_HOURS | \ - RTC_ALARMMASK_MINUTES | \ - RTC_ALARMMASK_SECONDS) -/** - * @} - */ - -/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions - * @{ - */ -#define RTC_ALARM_A RTC_CR_ALRAE -#define RTC_ALARM_B RTC_CR_ALRBE -/** - * @} - */ - -/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions - * @{ - */ -/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ -#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U -/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 -/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 -/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) -/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 -/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) -/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) -/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) -/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 -/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) -/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) -/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) -/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) -/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) -/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) -/*!< SS[14:0] are compared and must match to activate alarm. */ -#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS -/** - * @} - */ - -/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions - * @{ - */ -#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ -#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ -#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ -#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ -/** - * @} - */ - -/** @defgroup RTC_Flags_Definitions RTC Flags Definitions - * @{ - */ -#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */ -#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Tamper 3 event flag */ -#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */ -#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */ -#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */ -#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */ -#define RTC_FLAG_ITSF RTC_ISR_ITSF /*!< Internal Timestamp event flag */ -#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */ -#define RTC_FLAG_ALRBF RTC_ISR_ALRBF /*!< Alarm B event flag */ -#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */ -#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */ -#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */ -#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */ -#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */ -#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */ -#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF /*!< ALRMBR register write allowance flag */ -#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Macros RTC Exported Macros - * @{ - */ - -/** @brief Reset RTC handle state - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_RTC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @brief Disable the write protection for RTC registers. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \ - (__HANDLE__)->Instance->WPR = 0xCAU; \ - (__HANDLE__)->Instance->WPR = 0x53U; \ - } while(0U) - -/** - * @brief Enable the write protection for RTC registers. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \ - (__HANDLE__)->Instance->WPR = 0xFFU; \ - } while(0U) - -/** - * @brief Check whether the RTC Calendar is initialized. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U) - -/** - * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) - -/** - * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) - -/** - * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) - -/** - * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) - -/** - * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) - -/** - * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm Flag to check. - * This parameter can be: - * @arg RTC_FLAG_ALRAF: Alarm A interrupt flag - * @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag - * @arg RTC_FLAG_ALRBF: Alarm B interrupt flag - * @arg RTC_FLAG_ALRBWF: Alarm B 'write allowed' flag - * @retval None - */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) - -/** - * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm flag to be cleared. - * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @retval None - */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt - * @retval None - */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) - -/** - * @brief Enable interrupt on the RTC Alarm associated EXTI line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable interrupt on the RTC Alarm associated EXTI line. - * @retval None - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Enable event on the RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable event on the RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Enable falling edge trigger on the RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Enable rising edge trigger on the RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Clear the RTC Alarm associated EXTI line flag. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) - -/** - * @brief Generate a Software interrupt on RTC Alarm associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) -/** - * @} - */ - -/* Include RTC HAL Extended module */ -#include "stm32f7xx_hal_rtc_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup RTC_Exported_Functions - * @{ - */ - -/** @addtogroup RTC_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group2 - * @{ - */ -/* RTC Time and Date functions ************************************************/ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group3 - * @{ - */ -/* RTC Alarm functions ********************************************************/ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group4 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); - -/* RTC Daylight Saving Time functions *****************************************/ -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @addtogroup RTC_Exported_Functions_Group5 - * @{ - */ -/* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Constants RTC Private Constants - * @{ - */ -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \ - RTC_TR_MNT | RTC_TR_MNU | \ - RTC_TR_ST | RTC_TR_SU | \ - RTC_TR_PM)) -#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \ - RTC_DR_MT | RTC_DR_MU | \ - RTC_DR_DT | RTC_DR_DU | \ - RTC_DR_WDU)) -#define RTC_ISR_RESERVED_MASK ((uint32_t)(RTC_FLAGS_MASK | RTC_ISR_INIT)) -#define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \ - RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRBWF | \ - RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \ - RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \ - RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ - RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK)) - -#define RTC_TIMEOUT_VALUE 1000U - -#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup RTC_Private_Macros RTC Private Macros - * @{ - */ - -/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters - * @{ - */ -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ - ((FORMAT) == RTC_HOURFORMAT_24)) - -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) - -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((POL) == RTC_OUTPUT_POLARITY_LOW)) - -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ - ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) - -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU) -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU) - -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) - -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ - ((PM) == RTC_HOURFORMAT12_PM)) - -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) - -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ - ((OPERATION) == RTC_STOREOPERATION_SET)) - -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) - -#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) -#define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) - -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) - -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ - ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) - -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U) - -#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) - -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions RTC Private Functions - * @{ - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); -uint8_t RTC_ByteToBcd2(uint8_t number); -uint8_t RTC_Bcd2ToByte(uint8_t number); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_RTC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h deleted file mode 100644 index d36b503a..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_rtc_ex.h +++ /dev/null @@ -1,1127 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rtc_ex.h - * @author MCD Application Team - * @brief Header file of RTC HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_RTC_EX_H -#define STM32F7xx_HAL_RTC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ - -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup RTCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Types RTCEx Exported Types - * @{ - */ - -/** - * @brief RTC Tamper structure definition - */ -typedef struct -{ - uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pin_Definitions */ - - uint32_t Interrupt; /*!< Specifies the Tamper Interrupt. - This parameter can be a value of @ref RTCEx_Tamper_Interrupt_Definitions */ - - uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ - - uint32_t NoErase; /*!< Specifies the Tamper no erase mode. - This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */ - - uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking. - This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions */ - - uint32_t Filter; /*!< Specifies the RTC Filter Tamper. - This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ - - uint32_t SamplingFrequency; /*!< Specifies the sampling frequency. - This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ - - uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . - This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ - - uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . - This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */ - - uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. - This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -} RTC_TamperTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants - * @{ - */ - -/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definitions - * @{ - */ -#define RTC_BKP_DR0 0x00000000U -#define RTC_BKP_DR1 0x00000001U -#define RTC_BKP_DR2 0x00000002U -#define RTC_BKP_DR3 0x00000003U -#define RTC_BKP_DR4 0x00000004U -#define RTC_BKP_DR5 0x00000005U -#define RTC_BKP_DR6 0x00000006U -#define RTC_BKP_DR7 0x00000007U -#define RTC_BKP_DR8 0x00000008U -#define RTC_BKP_DR9 0x00000009U -#define RTC_BKP_DR10 0x0000000AU -#define RTC_BKP_DR11 0x0000000BU -#define RTC_BKP_DR12 0x0000000CU -#define RTC_BKP_DR13 0x0000000DU -#define RTC_BKP_DR14 0x0000000EU -#define RTC_BKP_DR15 0x0000000FU -#define RTC_BKP_DR16 0x00000010U -#define RTC_BKP_DR17 0x00000011U -#define RTC_BKP_DR18 0x00000012U -#define RTC_BKP_DR19 0x00000013U -#define RTC_BKP_DR20 0x00000014U -#define RTC_BKP_DR21 0x00000015U -#define RTC_BKP_DR22 0x00000016U -#define RTC_BKP_DR23 0x00000017U -#define RTC_BKP_DR24 0x00000018U -#define RTC_BKP_DR25 0x00000019U -#define RTC_BKP_DR26 0x0000001AU -#define RTC_BKP_DR27 0x0000001BU -#define RTC_BKP_DR28 0x0000001CU -#define RTC_BKP_DR29 0x0000001DU -#define RTC_BKP_DR30 0x0000001EU -#define RTC_BKP_DR31 0x0000001FU -/** - * @} - */ - -/** @defgroup RTCEx_Timestamp_Edges_Definitions RTCEx Timestamp Edges Definitions - * @{ - */ -#define RTC_TIMESTAMPEDGE_RISING 0x00000000U -#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE -/** - * @} - */ - -/** @defgroup RTCEx_Timestamp_Pin_Selection RTC Timestamp Pin Selection - * @{ - */ -#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U -#define RTC_TIMESTAMPPIN_POS1 RTC_OR_TSINSEL_0 -#define RTC_TIMESTAMPPIN_POS2 RTC_OR_TSINSEL_1 -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Definitions RTCEx Tamper Pins Definitions - * @{ - */ -#define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E -#define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E -#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Selection RTC tamper Pins Selection - * @{ - */ -#define RTC_TAMPERPIN_DEFAULT 0x00000000U -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions - * @{ - */ -#define RTC_IT_TAMP RTC_TAMPCR_TAMPIE /*!< Enable global Tamper Interrupt */ -#define RTC_IT_TAMP1 RTC_TAMPCR_TAMP1IE /*!< Enable Tamper 1 Interrupt */ -#define RTC_IT_TAMP2 RTC_TAMPCR_TAMP2IE /*!< Enable Tamper 2 Interrupt */ -#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE /*!< Enable Tamper 3 Interrupt */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Triggers Definitions - * @{ - */ -#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U -#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U -#define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE -#define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTCEx Tamper EraseBackUp Definitions - * @{ - */ -#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00000000U -#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x00020000U -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTCEx Tamper MaskFlag Definitions - * @{ - */ -#define RTC_TAMPERMASK_FLAG_DISABLE 0x00000000U -#define RTC_TAMPERMASK_FLAG_ENABLE 0x00040000U -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions - * @{ - */ -#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ - -#define RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_MASK RTC_TAMPCR_TAMPFLT /*!< Masking all bits except those of - field TAMPFLT */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions - * @{ - */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAMPCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAMPCR_TAMPFREQ /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAMPCR_TAMPFREQ /*!< Masking all bits except those of - field TAMPFREQ */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions - * @{ - */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAMPCR_TAMPPRCH /*!< Masking all bits except those of - field TAMPPRCH */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pull_Up_Definitions RTCEx Tamper Pull Up Definitions - * @{ - */ -#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */ -#define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< Tamper pins are not pre-charged before sampling */ -#define RTC_TAMPER_PULLUP_MASK RTC_TAMPCR_TAMPPUDIS /*!< Masking all bits except bit TAMPPUDIS */ -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions - * @{ - */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_TAMPCR_TAMPTS /*!< Masking all bits except bit TAMPTS */ -/** - * @} - */ - -/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions - * @{ - */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth Calib Period Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, smooth calibration - period is 32s, otherwise 2^20 RTCCLK pulses */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, smooth calibration - period is 16s, otherwise 2^19 RTCCLK pulses */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, smooth calibration - period is 8s, otherwise 2^18 RTCCLK pulses */ -/** - * @} - */ - -/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth Calib Plus Pulses Definitions - * @{ - */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ -/** - * @} - */ - -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions - * @{ - */ -#define RTC_SHIFTADD1S_RESET 0x00000000U -#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S -/** - * @} - */ - -/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output Selection Definitions - * @{ - */ -#define RTC_CALIBOUTPUT_512HZ 0x00000000U -#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros - * @{ - */ - -/* ---------------------------------WAKEUPTIMER-------------------------------*/ - -/** @defgroup RTCEx_WakeUp_Timer RTCEx WakeUp Timer - * @{ - */ - -/** - * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) - -/** - * @brief Disable the RTC Wakeup Timer peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) - -/** - * @brief Enable the RTC Wakeup Timer interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: Wakeup Timer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Wakeup Timer interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_WUT: Wakeup Timer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Wakeup Timer interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt to check. - * This parameter can be: - * @arg RTC_IT_WUT: Wakeup Timer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) - -/** - * @brief Check whether the specified RTC Wakeup timer interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wakeup timer interrupt sources to check. - * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) - -/** - * @brief Get the selected RTC Wakeup Timer's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Wakeup Timer flag to check. - * This parameter can be: - * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt flag - * @arg RTC_FLAG_WUTWF: Wakeup Timer 'write allowed' flag - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) - -/** - * @brief Clear the RTC Wakeup timer's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Wakeup Timer Flag to clear. - * This parameter can be: - * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt Flag - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable interrupt on the RTC Wakeup Timer associated EXTI line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable interrupt on the RTC Wakeup Timer associated EXTI line. - * @retval None - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Enable event on the RTC Wakeup Timer associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable event on the RTC Wakeup Timer associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Enable falling edge trigger on the RTC Wakeup Timer associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Wakeup Timer associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Enable rising edge trigger on the RTC Wakeup Timer associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Wakeup Timer associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Enable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Disable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line. - * This parameter can be: - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Check whether the RTC Wakeup Timer associated EXTI line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Clear the RTC Wakeup Timer associated EXTI line flag. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @brief Generate a Software interrupt on the RTC Wakeup Timer associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) - -/** - * @} - */ - -/* ---------------------------------TIMESTAMP---------------------------------*/ - -/** @defgroup RTCEx_Timestamp RTCEx Timestamp - * @{ - */ - -/** - * @brief Enable the RTC Timestamp peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) - -/** - * @brief Disable the RTC Timestamp peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) - -/** - * @brief Enable the RTC Timestamp interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Timestamp interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Timestamp interrupt has occurred or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Timestamp interrupt to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) - -/** - * @brief Check whether the specified RTC Timestamp interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Timestamp interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) - -/** - * @brief Get the selected RTC Timestamp's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Timestamp flag to check. - * This parameter can be: - * @arg RTC_FLAG_TSF: Timestamp interrupt flag - * @arg RTC_FLAG_TSOVF: Timestamp overflow flag - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) - -/** - * @brief Clear the RTC Timestamp's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Timestamp flag to clear. - * This parameter can be: - * @arg RTC_FLAG_TSF: Timestamp interrupt flag - * @arg RTC_FLAG_TSOVF: Timestamp overflow flag - * @retval None - */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @brief Enable the RTC internal TimeStamp peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) - -/** - * @brief Disable the RTC internal TimeStamp peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) - -/** - * @brief Get the selected RTC Internal Timestamp's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Internal Timestamp flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_ITSF: Internal Timestamp interrupt flag - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) - -/** - * @brief Clear the RTC Internal Timestamp's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Internal Timestamp flag to clear. - * This parameter can be: - * @arg RTC_FLAG_ITSF: Internal Timestamp interrupt flag - * @retval None - */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0003FFFFU)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - -/** - * @} - */ - -/* ---------------------------------TAMPER------------------------------------*/ - -/** @defgroup RTCEx_Tamper RTCEx Tamper - * @{ - */ - -/** - * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) - -/** - * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) - -/** - * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) - -/** - * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) - -/** - * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) - -/** - * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) - -/** - * @brief Enable the RTC Tamper interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: Tamper global interrupt - * @arg RTC_IT_TAMP1: Tamper 1 interrupt - * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @arg RTC_IT_TAMP3: Tamper 3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) - -/** - * @brief Disable the RTC Tamper interrupt. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_TAMP: Tamper global interrupt - * @arg RTC_IT_TAMP1: Tamper 1 interrupt - * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @arg RTC_IT_TAMP3: Tamper 3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) - -/** - * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. - * This parameter can be: - * @arg RTC_IT_TAMP: Tamper global interrupt - * @arg RTC_IT_TAMP1: Tamper 1 interrupt - * @arg RTC_IT_TAMP2: Tamper 2 interrupt - * @arg RTC_IT_TAMP3: Tamper 3 interrupt - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) - -/** - * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper flag to be checked. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag - * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag - * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag - * @retval None - */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) - -/** - * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag to clear. - * This parameter can be: - * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag - * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag - * @arg RTC_FLAG_TAMP3F: Tamper 3 interrupt flag - * @retval None - */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) -/** - * @} - */ - -/* --------------------------TAMPER/TIMESTAMP---------------------------------*/ -/** @defgroup RTCEx_Tamper_Timestamp EXTI RTC Tamper Timestamp EXTI - * @{ - */ - -/** - * @brief Enable interrupt on the RTC Tamper and Timestamp associated EXTI line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable interrupt on the RTC Tamper and Timestamp associated EXTI line. - * @retval None - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Enable event on the RTC Tamper and Timestamp associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable event on the RTC Tamper and Timestamp associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. - * This parameter can be: - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0U) - -/** - * @brief Check whether the RTC Tamper and Timestamp associated EXTI line interrupt flag is set or not. - * @retval Line Status. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Clear the RTC Tamper and Timestamp associated EXTI line flag. - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) - -/** - * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated EXTI line - * @retval None. - */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) -/** - * @} - */ - -/* ------------------------------CALIBRATION----------------------------------*/ - -/** @defgroup RTCEx_Calibration RTCEx Calibration - * @{ - */ - -/** - * @brief Enable the RTC calibration output. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) - -/** - * @brief Disable the calibration output. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) - -/** - * @brief Enable the clock reference detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) - -/** - * @brief Disable the clock reference detection. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) - -/** - * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. - * This parameter can be: - * @arg RTC_FLAG_SHPF: Shift pending flag - * @retval None - */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions - * @{ - */ - -/** @addtogroup RTCEx_Exported_Functions_Group1 - * @{ - */ -/* RTC Timestamp and Tamper functions *****************************************/ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin); -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); - -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); - -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/** @addtogroup RTCEx_Exported_Functions_Group2 - * @{ - */ -/* RTC Wakeup functions ******************************************************/ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/** @addtogroup RTCEx_Exported_Functions_Group3 - * @{ - */ -/* Extended Control functions ************************************************/ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); - -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); -/** - * @} - */ - -/** @addtogroup RTCEx_Exported_Functions_Group4 - * @{ - */ -/* Extended RTC features functions *******************************************/ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ - -/** @defgroup RTCEx_Private_Constants RTCEx Private Constants - * @{ - */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_IM21 /*!< External interrupt line 21 Connected to the RTC Tamper and Timestamp event */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_IM22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */ -/** - * @} - */ - -/** @defgroup RTCEx_Private_Constants RTCEx Private Constants - * @{ - */ -/* Masks Definition */ -#define RTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | \ - RTC_TAMPER_2 | \ - RTC_TAMPER_3)) - -#define RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | \ - RTC_FLAG_TAMP2F | \ - RTC_FLAG_TAMP3F)) - -#define RTC_TAMPER_IT_ENABLE_BITS_MASK ((uint32_t) (RTC_IT_TAMP1 | \ - RTC_IT_TAMP2 | \ - RTC_IT_TAMP3 | \ - RTC_IT_TAMP)) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup RTCEx_Private_Macros RTCEx Private Macros - * @{ - */ - -/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters - * @{ - */ -#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) - -#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ - ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) - -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~RTC_TAMPER_ENABLE_BITS_MASK)) == 0x00U) && ((TAMPER) != 0U)) - -#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT) - -#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \ - ((PIN) == RTC_TIMESTAMPPIN_POS1) || \ - ((PIN) == RTC_TIMESTAMPPIN_POS2)) - -#define IS_RTC_TAMPER_INTERRUPT(INTERRUPT) ((((INTERRUPT) & ((uint32_t)~RTC_TAMPER_IT_ENABLE_BITS_MASK )) == 0x00U) && ((INTERRUPT) != 0U)) - -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) - -#define IS_RTC_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ - ((MODE) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) - -#define IS_RTC_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_TAMPERMASK_FLAG_ENABLE) || \ - ((STATE) == RTC_TAMPERMASK_FLAG_DISABLE)) - -#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) - -#define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER) \ - ( ( ((FILTER) != RTC_TAMPERFILTER_DISABLE) \ - && ( ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) \ - || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \ - || ( ((FILTER) == RTC_TAMPERFILTER_DISABLE) \ - && ( ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) \ - || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)))) - -#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) - -#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) - -#define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) - -#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) - -#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) - -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) - -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) - -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ - ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) - -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) - -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ - ((SEL) == RTC_SHIFTADD1S_SET)) - -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) - -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ - ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_RTC_EX_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h deleted file mode 100644 index 64bef82f..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai.h +++ /dev/null @@ -1,879 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sai.h - * @author MCD Application Team - * @brief Header file of SAI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_SAI_H -#define __STM32F7xx_HAL_SAI_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SAI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SAI_Exported_Types SAI Exported Types - * @{ - */ - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */ - HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */ - HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ - HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ - HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ -} HAL_SAI_StateTypeDef; - -/** - * @brief SAI Callback prototype - */ -typedef void (*SAIcallback)(void); - -/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition - * @brief SAI Init Structure definition - * @{ - */ -typedef struct -{ - uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode. - This parameter can be a value of @ref SAI_Block_Mode */ - - uint32_t Synchro; /*!< Specifies SAI Block synchronization - This parameter can be a value of @ref SAI_Block_Synchronization */ - - uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common - for BlockA and BlockB - This parameter can be a value of @ref SAI_Block_SyncExt - @note: If both audio blocks of same SAI are used, this parameter has - to be set to the same value for each audio block */ - - uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. - This parameter can be a value of @ref SAI_Block_Output_Drive - @note this value has to be set before enabling the audio block - but after the audio block configuration. */ - - uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. - This parameter can be a value of @ref SAI_Block_NoDivider - @note: If bit NODIV in the SAI_xCR1 register is cleared, the frame length - should be aligned to a number equal to a power of 2, from 8 to 256. - If bit NODIV in the SAI_xCR1 register is set, the frame length can - take any of the values without constraint since the input clock of - the audio block should be equal to the bit clock. - There is no MCLK_x clock which can be output. */ - - uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold. - This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ - - uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. - This parameter can be a value of @ref SAI_Audio_Frequency */ - - uint32_t Mckdiv; /*!< Specifies the master clock divider. - This parameter must be a number between Min_Data = 0 and Max_Data = 15. - @note This parameter is used only if AudioFrequency is set to - SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ - - uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. - This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ - - uint32_t CompandingMode; /*!< Specifies the companding mode type. - This parameter can be a value of @ref SAI_Block_Companding_Mode */ - - uint32_t TriState; /*!< Specifies the companding mode type. - This parameter can be a value of @ref SAI_TRIState_Management */ - - /* This part of the structure is automatically filled if your are using the high level initialisation - function HAL_SAI_InitProtocol */ - - uint32_t Protocol; /*!< Specifies the SAI Block protocol. - This parameter can be a value of @ref SAI_Block_Protocol */ - - uint32_t DataSize; /*!< Specifies the SAI Block data size. - This parameter can be a value of @ref SAI_Block_Data_Size */ - - uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */ - - uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. - This parameter can be a value of @ref SAI_Block_Clock_Strobing */ -} SAI_InitTypeDef; -/** - * @} - */ - -/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition - * @brief SAI Frame Init structure definition - * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). - * @{ - */ -typedef struct -{ - - uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. - This parameter must be a number between Min_Data = 8 and Max_Data = 256. - @note: If master clock MCLK_x pin is declared as an output, the frame length - should be aligned to a number equal to power of 2 in order to keep - in an audio frame, an integer number of MCLK pulses by bit Clock. */ - - uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. - This Parameter specifies the length in number of bit clock (SCK + 1) - of the active level of FS signal in audio frame. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition. - This parameter can be a value of @ref SAI_Block_FS_Definition */ - - uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity. - This parameter can be a value of @ref SAI_Block_FS_Polarity */ - - uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. - This parameter can be a value of @ref SAI_Block_FS_Offset */ - -} SAI_FrameInitTypeDef; -/** - * @} - */ - -/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition - * @brief SAI Block Slot Init Structure definition - * @note For SPDIF protocol, these parameters are not used (set by hardware). - * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). - * @{ - */ -typedef struct -{ - uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. - This parameter must be a number between Min_Data = 0 and Max_Data = 24 */ - - uint32_t SlotSize; /*!< Specifies the Slot Size. - This parameter can be a value of @ref SAI_Block_Slot_Size */ - - uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ - - uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. - This parameter can be a value of @ref SAI_Block_Slot_Active */ -} SAI_SlotInitTypeDef; -/** - * @} - */ - -/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition - * @brief SAI handle Structure definition - * @{ - */ -typedef struct __SAI_HandleTypeDef -{ - SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ - - SAI_InitTypeDef Init; /*!< SAI communication parameters */ - - SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ - - SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */ - - uint16_t XferSize; /*!< SAI transfer size */ - - uint16_t XferCount; /*!< SAI transfer counter */ - - DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ - - SAIcallback mutecallback; /*!< SAI mute callback */ - - void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */ - - HAL_LockTypeDef Lock; /*!< SAI locking object */ - - __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ - - __IO uint32_t ErrorCode; /*!< SAI Error code */ - -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */ - void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */ - void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */ - void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */ - void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */ - void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ - void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ -#endif -} SAI_HandleTypeDef; -/** - * @} - */ - -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) -/** - * @brief SAI callback ID enumeration definition - */ -typedef enum -{ - HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */ - HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */ - HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */ - HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */ - HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */ - HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */ - HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */ -} HAL_SAI_CallbackIDTypeDef; - -/** - * @brief SAI callback pointer definition - */ -typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); -#endif - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SAI_Exported_Constants SAI Exported Constants - * @{ - */ - -/** @defgroup SAI_Error_Code SAI Error Code - * @{ - */ -#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */ -#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */ -#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */ -#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */ -#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */ -#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */ -#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */ -#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) -#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ -#endif -/** - * @} - */ - -/** @defgroup SAI_Block_SyncExt SAI External synchronisation - * @{ - */ -#define SAI_SYNCEXT_DISABLE 0 -#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1 -#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2 -/** - * @} - */ - -/** @defgroup SAI_Protocol SAI Supported protocol - * @{ - */ -#define SAI_I2S_STANDARD 0 -#define SAI_I2S_MSBJUSTIFIED 1 -#define SAI_I2S_LSBJUSTIFIED 2 -#define SAI_PCM_LONG 3 -#define SAI_PCM_SHORT 4 -/** - * @} - */ - -/** @defgroup SAI_Protocol_DataSize SAI protocol data size - * @{ - */ -#define SAI_PROTOCOL_DATASIZE_16BIT 0 -#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1 -#define SAI_PROTOCOL_DATASIZE_24BIT 2 -#define SAI_PROTOCOL_DATASIZE_32BIT 3 -/** - * @} - */ - -/** @defgroup SAI_Audio_Frequency SAI Audio Frequency - * @{ - */ -#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U) -#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U) -#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U) -#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U) -#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U) -#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U) -#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U) -#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U) -#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U) -#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U) -/** - * @} - */ - -/** @defgroup SAI_Block_Mode SAI Block Mode - * @{ - */ -#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U) -#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0) -#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1) -#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)) - -/** - * @} - */ - -/** @defgroup SAI_Block_Protocol SAI Block Protocol - * @{ - */ -#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U) -#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0) -#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1) -/** - * @} - */ - -/** @defgroup SAI_Block_Data_Size SAI Block Data Size - * @{ - */ -#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1) -#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2) -#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0)) -#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1)) -#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)) -/** - * @} - */ - -/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission - * @{ - */ -#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U) -#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST) -/** - * @} - */ - -/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing - * @{ - */ -#define SAI_CLOCKSTROBING_FALLINGEDGE 0 -#define SAI_CLOCKSTROBING_RISINGEDGE 1 -/** - * @} - */ - -/** @defgroup SAI_Block_Synchronization SAI Block Synchronization - * @{ - */ -#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */ -#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */ -#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */ -#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */ -/** - * @} - */ - -/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U) -#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV) -/** - * @} - */ - -/** @defgroup SAI_Block_NoDivider SAI Block NoDivider - * @{ - */ -#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U) -#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NODIV) -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition - * @{ - */ -#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U) -#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF) -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity - * @{ - */ -#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U) -#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL) -/** - * @} - */ - -/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset - * @{ - */ -#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U) -#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF) -/** - * @} - */ - -/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size - * @{ - */ -#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U) -#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0) -#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1) -/** - * @} - */ - -/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active - * @{ - */ -#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U) -#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U) -#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U) -#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U) -#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U) -#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U) -#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U) -#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U) -#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U) -#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U) -#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U) -#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U) -#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U) -#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U) -#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U) -#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U) -#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U) -#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU) -/** - * @} - */ - -/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode - * @{ - */ -#define SAI_STEREOMODE ((uint32_t)0x00000000U) -#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO) -/** - * @} - */ - -/** @defgroup SAI_TRIState_Management SAI TRIState Management - * @{ - */ -#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U) -#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS) -/** - * @} - */ - -/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold - * @{ - */ -#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U) -#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1)) -#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)) -#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2)) -/** - * @} - */ - -/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode - * @{ - */ -#define SAI_NOCOMPANDING ((uint32_t)0x00000000U) -#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1)) -#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)) -#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL)) -#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)) -/** - * @} - */ - -/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value - * @{ - */ -#define SAI_ZERO_VALUE ((uint32_t)0x00000000U) -#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL) -/** - * @} - */ - -/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition - * @{ - */ -#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE) -#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE) -#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE) -#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE) -#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE) -#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE) -#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE) -/** - * @} - */ - -/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition - * @{ - */ -#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR) -#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET) -#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG) -#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ) -#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY) -#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET) -#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET) -/** - * @} - */ - -/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level - * @{ - */ -#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U) -#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U) -#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U) -#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U) -#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U) -#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SAI_Exported_Macros SAI Exported Macros - * @brief macros to handle interrupts and specific configurations - * @{ - */ - -/** @brief Reset SAI handle state. - * @param __HANDLE__ specifies the SAI Handle. - * @retval None - */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) -#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SAI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - -/** @brief Enable or disable the specified SAI interrupts. - * @param __HANDLE__ specifies the SAI Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable - * @arg SAI_IT_MUTEDET: Mute detection interrupt enable - * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable - * @arg SAI_IT_FREQ: FIFO request interrupt enable - * @arg SAI_IT_CNRDY: Codec not ready interrupt enable - * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable - * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable - * @retval None - */ -#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) -#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified SAI interrupt source is enabled or not. - * @param __HANDLE__ specifies the SAI Handle. - * @param __INTERRUPT__ specifies the SAI interrupt source to check. - * This parameter can be one of the following values: - * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable - * @arg SAI_IT_MUTEDET: Mute detection interrupt enable - * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable - * @arg SAI_IT_FREQ: FIFO request interrupt enable - * @arg SAI_IT_CNRDY: Codec not ready interrupt enable - * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable - * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified SAI flag is set or not. - * @param __HANDLE__ specifies the SAI Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. - * @arg SAI_FLAG_MUTEDET: Mute detection flag. - * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag. - * @arg SAI_FLAG_FREQ: FIFO request flag. - * @arg SAI_FLAG_CNRDY: Codec not ready flag. - * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag. - * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified SAI pending flag. - * @param __HANDLE__ specifies the SAI Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun - * @arg SAI_FLAG_MUTEDET: Clear Mute detection - * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration - * @arg SAI_FLAG_FREQ: Clear FIFO request - * @arg SAI_FLAG_CNRDY: Clear Codec not ready - * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection - * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection - * - * @retval None - */ -#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) - -#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) -#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SAI_Exported_Functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup SAI_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); -HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); -HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); -void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); -void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); - -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) -/* SAI callbacks register/unregister functions ********************************/ -HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, - HAL_SAI_CallbackIDTypeDef CallbackID, - pSAI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, - HAL_SAI_CallbackIDTypeDef CallbackID); -#endif -/** - * @} - */ - -/* I/O operation functions ***************************************************/ - -/** @addtogroup SAI_Exported_Functions_Group2 - * @{ - */ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai); -HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai); -HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai); - -/* Abort function */ -HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai); - -/* Mute management */ -HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val); -HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai); -HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter); -HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai); - -/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai); -void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai); -void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai); -void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai); -void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai); -void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); -/** - * @} - */ - -/** @addtogroup SAI_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); -uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup SAI_Private_Macros - * @{ - */ -#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ - ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ - ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) - -#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ - ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ - ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\ - ((PROTOCOL) == SAI_PCM_LONG) ||\ - ((PROTOCOL) == SAI_PCM_SHORT)) - -#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\ - ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\ - ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\ - ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT)) - -#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \ - ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \ - ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \ - ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ - ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) - -#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ - ((MODE) == SAI_MODEMASTER_RX) || \ - ((MODE) == SAI_MODESLAVE_TX) || \ - ((MODE) == SAI_MODESLAVE_RX)) - -#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ - ((PROTOCOL) == SAI_AC97_PROTOCOL) || \ - ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) - -#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \ - ((DATASIZE) == SAI_DATASIZE_10) || \ - ((DATASIZE) == SAI_DATASIZE_16) || \ - ((DATASIZE) == SAI_DATASIZE_20) || \ - ((DATASIZE) == SAI_DATASIZE_24) || \ - ((DATASIZE) == SAI_DATASIZE_32)) - -#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \ - ((BIT) == SAI_FIRSTBIT_LSB)) - -#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ - ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) - -#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ - ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) - -#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \ - ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE)) - -#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ - ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) - -#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63) - -#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ - ((VALUE) == SAI_LAST_SENT_VALUE)) - -#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ - ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ - ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \ - ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \ - ((MODE) == SAI_ALAW_2CPL_COMPANDING)) - -#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \ - ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ - ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ - ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ - ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) - -#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ - ((STATE) == SAI_OUTPUT_RELEASED)) - -#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\ - ((MODE) == SAI_STEREOMODE)) - -#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) - -#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16)) - -#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ - ((SIZE) == SAI_SLOTSIZE_16B) || \ - ((SIZE) == SAI_SLOTSIZE_32B)) - -#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24) - -#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ - ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) - -#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \ - ((POLARITY) == SAI_FS_ACTIVE_HIGH)) - -#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ - ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) - -#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U) - -#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256)) - -#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup SAI_Private_Functions SAI Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_HAL_SAI_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai_ex.h deleted file mode 100644 index d1187f7e..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sai_ex.h +++ /dev/null @@ -1,36 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sai_ex.h - * @author MCD Application Team - * @brief Header file of SAI Extension HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_HAL_SAI_EX_H -#define __STM32F7xx_HAL_SAI_EX_H - - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/* Extended features functions ************************************************/ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -#endif /* __STM32F7xx_HAL_SAI_EX_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h index 8604832a..30de8485 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sd.h @@ -1,758 +1,758 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sd.h - * @author MCD Application Team - * @brief Header file of SD HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SD_H -#define STM32F7xx_HAL_SD_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(SDMMC1) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_sdmmc.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SD SD - * @brief SD HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SD_Exported_Types SD Exported Types - * @{ - */ - -/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure - * @{ - */ -typedef enum -{ - HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */ - HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */ - HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */ - HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */ - HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */ - HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */ - HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */ - HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */ -}HAL_SD_StateTypeDef; -/** - * @} - */ - -/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure - * @{ - */ -typedef uint32_t HAL_SD_CardStateTypeDef; - -#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ -#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ -#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ -#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ -#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ -#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ -#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ -#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ -#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */ -/** - * @} - */ - -/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition - * @{ - */ -#define SD_InitTypeDef SDMMC_InitTypeDef -#define SD_TypeDef SDMMC_TypeDef - -/** - * @brief SD Card Information Structure definition - */ -typedef struct -{ - uint32_t CardType; /*!< Specifies the card Type */ - - uint32_t CardVersion; /*!< Specifies the card version */ - - uint32_t Class; /*!< Specifies the class of the card class */ - - uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ - - uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ - - uint32_t BlockSize; /*!< Specifies one block size in bytes */ - - uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ - - uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ - -}HAL_SD_CardInfoTypeDef; - -/** - * @brief SD handle Structure definition - */ -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) -typedef struct __SD_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ -{ - SD_TypeDef *Instance; /*!< SD registers base address */ - - SD_InitTypeDef Init; /*!< SD required parameters */ - - HAL_LockTypeDef Lock; /*!< SD locking object */ - - uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ - - uint32_t TxXferSize; /*!< SD Tx Transfer size */ - - uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ - - uint32_t RxXferSize; /*!< SD Rx Transfer size */ - - __IO uint32_t Context; /*!< SD transfer context */ - - __IO HAL_SD_StateTypeDef State; /*!< SD card State */ - - __IO uint32_t ErrorCode; /*!< SD Card Error codes */ - - DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ - - HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ - - uint32_t CSD[4]; /*!< SD card specific data table */ - - uint32_t CID[4]; /*!< SD card identification number table */ - -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); - void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); - void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd); - - void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); - void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ -}SD_HandleTypeDef; - -/** - * @} - */ - -/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register - * @{ - */ -typedef struct -{ - __IO uint8_t CSDStruct; /*!< CSD structure */ - __IO uint8_t SysSpecVersion; /*!< System specification version */ - __IO uint8_t Reserved1; /*!< Reserved */ - __IO uint8_t TAAC; /*!< Data read access time 1 */ - __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ - __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - __IO uint16_t CardComdClasses; /*!< Card command classes */ - __IO uint8_t RdBlockLen; /*!< Max. read data block length */ - __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ - __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ - __IO uint8_t DSRImpl; /*!< DSR implemented */ - __IO uint8_t Reserved2; /*!< Reserved */ - __IO uint32_t DeviceSize; /*!< Device Size */ - __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ - __IO uint8_t EraseGrSize; /*!< Erase group size */ - __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ - __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ - __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - __IO uint8_t WrSpeedFact; /*!< Write speed factor */ - __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - __IO uint8_t Reserved3; /*!< Reserved */ - __IO uint8_t ContentProtectAppli; /*!< Content protection application */ - __IO uint8_t FileFormatGroup; /*!< File format group */ - __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ - __IO uint8_t PermWrProtect; /*!< Permanent write protection */ - __IO uint8_t TempWrProtect; /*!< Temporary write protection */ - __IO uint8_t FileFormat; /*!< File format */ - __IO uint8_t ECC; /*!< ECC code */ - __IO uint8_t CSD_CRC; /*!< CSD CRC */ - __IO uint8_t Reserved4; /*!< Always 1 */ -}HAL_SD_CardCSDTypeDef; -/** - * @} - */ - -/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register - * @{ - */ -typedef struct -{ - __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ - __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ - __IO uint32_t ProdName1; /*!< Product Name part1 */ - __IO uint8_t ProdName2; /*!< Product Name part2 */ - __IO uint8_t ProdRev; /*!< Product Revision */ - __IO uint32_t ProdSN; /*!< Product Serial Number */ - __IO uint8_t Reserved1; /*!< Reserved1 */ - __IO uint16_t ManufactDate; /*!< Manufacturing Date */ - __IO uint8_t CID_CRC; /*!< CID CRC */ - __IO uint8_t Reserved2; /*!< Always 1 */ - -}HAL_SD_CardCIDTypeDef; -/** - * @} - */ - -/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 - * @{ - */ -typedef struct -{ - __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ - __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ - __IO uint16_t CardType; /*!< Carries information about card type */ - __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ - __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ - __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ - __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ - __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ - __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ - __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ - -}HAL_SD_CardStatusTypeDef; -/** - * @} - */ - -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) -/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition - * @{ - */ -typedef enum -{ - HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */ - HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */ - HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */ - HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */ - - HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ - HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ -}HAL_SD_CallbackIDTypeDef; -/** - * @} - */ - -/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition - * @{ - */ -typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); -/** - * @} - */ -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SD_Exported_Constants Exported Constants - * @{ - */ - -#define BLOCKSIZE 512U /*!< Block size is 512 bytes */ - -/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition - * @{ - */ -#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ -#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ -#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ -#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ -#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ -#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ -#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ -#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ -#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ -#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ -#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ -#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ -#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ -#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ -#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ -#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ -#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ -#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ -#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ -#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ -#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ -#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ -#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ -#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ -#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ -#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ -#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ -#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ -#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ -#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ -#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ -#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ -#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ - -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) -#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration - * @{ - */ -#define SD_CONTEXT_NONE 0x00000000U /*!< None */ -#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ -#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ -#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ -#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ -#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ -#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ - -/** - * @} - */ - -/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards - * @{ - */ -#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */ -#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ -#define CARD_SECURED 0x00000003U - -/** - * @} - */ - -/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version - * @{ - */ -#define CARD_V1_X 0x00000000U -#define CARD_V2_X 0x00000001U -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SD_Exported_macros SD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -/** @brief Reset SD handle state. - * @param __HANDLE__ : SD handle. - * @retval None - */ -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) -#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_SD_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - -/** - * @brief Enable the SD device. - * @retval None - */ -#define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) - -/** - * @brief Disable the SD device. - * @retval None - */ -#define __HAL_SD_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) - -/** - * @brief Enable the SDMMC DMA transfer. - * @retval None - */ -#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) - -/** - * @brief Disable the SDMMC DMA transfer. - * @retval None - */ -#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) - -/** - * @brief Enable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt - * @retval None - */ -#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @brief Disable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt - * @retval None - */ -#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @brief Check whether the specified SD flag is set or not. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_CMDACT: Command transfer in progress - * @arg SDMMC_FLAG_TXACT: Data transmit in progress - * @arg SDMMC_FLAG_RXACT: Data receive in progress - * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full - * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received - * @retval The new state of SD FLAG (SET or RESET). - */ -#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) - -/** - * @brief Clear the SD's pending flags. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received - * @retval None - */ -#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) - -/** - * @brief Check whether the specified SD interrupt has occurred or not. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. - * This parameter can be one of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt - * @retval The new state of SD IT (SET or RESET). - */ -#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @brief Clear the SD's interrupt pending bits. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt - * @retval None - */ -#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SD_Exported_Functions SD Exported Functions - * @{ - */ - -/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); -void HAL_SD_MspInit(SD_HandleTypeDef *hsd); -void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); -HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); -/* Non-Blocking mode: IT */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); - -void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); - -/* Callback in non blocking modes (DMA) */ -void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); -void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); -void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); -void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); - -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) -/* SD callback registering/unregistering */ -HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group4 SD card related functions - * @{ - */ -HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); -HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions - * @{ - */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); -/** - * @} - */ - -/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management - * @{ - */ -HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/** @defgroup SD_Private_Types SD Private Types - * @{ - */ - -/** - * @} - */ - -/* Private defines -----------------------------------------------------------*/ -/** @defgroup SD_Private_Defines SD Private Defines - * @{ - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @defgroup SD_Private_Variables SD Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SD_Private_Constants SD Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SD_Private_Macros SD Private Macros - * @{ - */ - -/** - * @} - */ - -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup SD_Private_Functions SD Private Functions - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* SDMMC1 */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_SD_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_sd.h + * @author MCD Application Team + * @brief Header file of SD HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_SD_H +#define STM32F7xx_HAL_SD_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(SDMMC1) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_ll_sdmmc.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup SD SD + * @brief SD HAL module driver + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SD_Exported_Types SD Exported Types + * @{ + */ + +/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure + * @{ + */ +typedef enum +{ + HAL_SD_STATE_RESET = 0x00000000U, /*!< SD not yet initialized or disabled */ + HAL_SD_STATE_READY = 0x00000001U, /*!< SD initialized and ready for use */ + HAL_SD_STATE_TIMEOUT = 0x00000002U, /*!< SD Timeout state */ + HAL_SD_STATE_BUSY = 0x00000003U, /*!< SD process ongoing */ + HAL_SD_STATE_PROGRAMMING = 0x00000004U, /*!< SD Programming State */ + HAL_SD_STATE_RECEIVING = 0x00000005U, /*!< SD Receiving State */ + HAL_SD_STATE_TRANSFER = 0x00000006U, /*!< SD Transfer State */ + HAL_SD_STATE_ERROR = 0x0000000FU /*!< SD is in error state */ +}HAL_SD_StateTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure + * @{ + */ +typedef uint32_t HAL_SD_CardStateTypeDef; + +#define HAL_SD_CARD_READY 0x00000001U /*!< Card state is ready */ +#define HAL_SD_CARD_IDENTIFICATION 0x00000002U /*!< Card is in identification state */ +#define HAL_SD_CARD_STANDBY 0x00000003U /*!< Card is in standby state */ +#define HAL_SD_CARD_TRANSFER 0x00000004U /*!< Card is in transfer state */ +#define HAL_SD_CARD_SENDING 0x00000005U /*!< Card is sending an operation */ +#define HAL_SD_CARD_RECEIVING 0x00000006U /*!< Card is receiving operation information */ +#define HAL_SD_CARD_PROGRAMMING 0x00000007U /*!< Card is in programming state */ +#define HAL_SD_CARD_DISCONNECTED 0x00000008U /*!< Card is disconnected */ +#define HAL_SD_CARD_ERROR 0x000000FFU /*!< Card response Error */ +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition + * @{ + */ +#define SD_InitTypeDef SDMMC_InitTypeDef +#define SD_TypeDef SDMMC_TypeDef + +/** + * @brief SD Card Information Structure definition + */ +typedef struct +{ + uint32_t CardType; /*!< Specifies the card Type */ + + uint32_t CardVersion; /*!< Specifies the card version */ + + uint32_t Class; /*!< Specifies the class of the card class */ + + uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */ + + uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */ + + uint32_t BlockSize; /*!< Specifies one block size in bytes */ + + uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */ + + uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */ + +}HAL_SD_CardInfoTypeDef; + +/** + * @brief SD handle Structure definition + */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +typedef struct __SD_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +{ + SD_TypeDef *Instance; /*!< SD registers base address */ + + SD_InitTypeDef Init; /*!< SD required parameters */ + + HAL_LockTypeDef Lock; /*!< SD locking object */ + + uint8_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */ + + uint32_t TxXferSize; /*!< SD Tx Transfer size */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */ + + uint32_t RxXferSize; /*!< SD Rx Transfer size */ + + __IO uint32_t Context; /*!< SD transfer context */ + + __IO HAL_SD_StateTypeDef State; /*!< SD card State */ + + __IO uint32_t ErrorCode; /*!< SD Card Error codes */ + + DMA_HandleTypeDef *hdmatx; /*!< SD Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SD Rx DMA handle parameters */ + + HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */ + + uint32_t CSD[4]; /*!< SD card specific data table */ + + uint32_t CID[4]; /*!< SD card identification number table */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* RxCpltCallback) (struct __SD_HandleTypeDef *hsd); + void (* ErrorCallback) (struct __SD_HandleTypeDef *hsd); + void (* AbortCpltCallback) (struct __SD_HandleTypeDef *hsd); + + void (* MspInitCallback) (struct __SD_HandleTypeDef *hsd); + void (* MspDeInitCallback) (struct __SD_HandleTypeDef *hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +}SD_HandleTypeDef; + +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register + * @{ + */ +typedef struct +{ + __IO uint8_t CSDStruct; /*!< CSD structure */ + __IO uint8_t SysSpecVersion; /*!< System specification version */ + __IO uint8_t Reserved1; /*!< Reserved */ + __IO uint8_t TAAC; /*!< Data read access time 1 */ + __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */ + __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ + __IO uint16_t CardComdClasses; /*!< Card command classes */ + __IO uint8_t RdBlockLen; /*!< Max. read data block length */ + __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ + __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */ + __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */ + __IO uint8_t DSRImpl; /*!< DSR implemented */ + __IO uint8_t Reserved2; /*!< Reserved */ + __IO uint32_t DeviceSize; /*!< Device Size */ + __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ + __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ + __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ + __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ + __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */ + __IO uint8_t EraseGrSize; /*!< Erase group size */ + __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */ + __IO uint8_t WrProtectGrSize; /*!< Write protect group size */ + __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */ + __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */ + __IO uint8_t WrSpeedFact; /*!< Write speed factor */ + __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */ + __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ + __IO uint8_t Reserved3; /*!< Reserved */ + __IO uint8_t ContentProtectAppli; /*!< Content protection application */ + __IO uint8_t FileFormatGroup; /*!< File format group */ + __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */ + __IO uint8_t PermWrProtect; /*!< Permanent write protection */ + __IO uint8_t TempWrProtect; /*!< Temporary write protection */ + __IO uint8_t FileFormat; /*!< File format */ + __IO uint8_t ECC; /*!< ECC code */ + __IO uint8_t CSD_CRC; /*!< CSD CRC */ + __IO uint8_t Reserved4; /*!< Always 1 */ +}HAL_SD_CardCSDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register + * @{ + */ +typedef struct +{ + __IO uint8_t ManufacturerID; /*!< Manufacturer ID */ + __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */ + __IO uint32_t ProdName1; /*!< Product Name part1 */ + __IO uint8_t ProdName2; /*!< Product Name part2 */ + __IO uint8_t ProdRev; /*!< Product Revision */ + __IO uint32_t ProdSN; /*!< Product Serial Number */ + __IO uint8_t Reserved1; /*!< Reserved1 */ + __IO uint16_t ManufactDate; /*!< Manufacturing Date */ + __IO uint8_t CID_CRC; /*!< CID CRC */ + __IO uint8_t Reserved2; /*!< Always 1 */ + +}HAL_SD_CardCIDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13 + * @{ + */ +typedef struct +{ + __IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */ + __IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */ + __IO uint16_t CardType; /*!< Carries information about card type */ + __IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */ + __IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */ + __IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */ + __IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */ + __IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */ + __IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */ + __IO uint8_t EraseOffset; /*!< Carries information about the erase offset */ + +}HAL_SD_CardStatusTypeDef; +/** + * @} + */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition + * @{ + */ +typedef enum +{ + HAL_SD_TX_CPLT_CB_ID = 0x00U, /*!< SD Tx Complete Callback ID */ + HAL_SD_RX_CPLT_CB_ID = 0x01U, /*!< SD Rx Complete Callback ID */ + HAL_SD_ERROR_CB_ID = 0x02U, /*!< SD Error Callback ID */ + HAL_SD_ABORT_CB_ID = 0x03U, /*!< SD Abort Callback ID */ + + HAL_SD_MSP_INIT_CB_ID = 0x10U, /*!< SD MspInit Callback ID */ + HAL_SD_MSP_DEINIT_CB_ID = 0x11U /*!< SD MspDeInit Callback ID */ +}HAL_SD_CallbackIDTypeDef; +/** + * @} + */ + +/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition + * @{ + */ +typedef void (*pSD_CallbackTypeDef) (SD_HandleTypeDef *hsd); +/** + * @} + */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SD_Exported_Constants Exported Constants + * @{ + */ + +#define BLOCKSIZE 512U /*!< Block size is 512 bytes */ + +/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition + * @{ + */ +#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */ +#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */ +#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */ +#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */ +#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */ +#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */ +#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */ +#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */ +#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */ +#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */ +#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */ +#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */ +#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */ +#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */ +#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */ +#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */ +#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */ +#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */ +#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */ +#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */ +#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */ +#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */ +#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */ +#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */ +#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */ +#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */ +#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */ +#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */ +#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */ +#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */ + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +#define HAL_SD_ERROR_INVALID_CALLBACK SDMMC_ERROR_INVALID_PARAMETER /*!< Invalid callback error */ +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration + * @{ + */ +#define SD_CONTEXT_NONE 0x00000000U /*!< None */ +#define SD_CONTEXT_READ_SINGLE_BLOCK 0x00000001U /*!< Read single block operation */ +#define SD_CONTEXT_READ_MULTIPLE_BLOCK 0x00000002U /*!< Read multiple blocks operation */ +#define SD_CONTEXT_WRITE_SINGLE_BLOCK 0x00000010U /*!< Write single block operation */ +#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK 0x00000020U /*!< Write multiple blocks operation */ +#define SD_CONTEXT_IT 0x00000008U /*!< Process in Interrupt mode */ +#define SD_CONTEXT_DMA 0x00000080U /*!< Process in DMA mode */ + +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards + * @{ + */ +#define CARD_SDSC 0x00000000U /*!< SD Standard Capacity <2Go */ +#define CARD_SDHC_SDXC 0x00000001U /*!< SD High Capacity <32Go, SD Extended Capacity <2To */ +#define CARD_SECURED 0x00000003U + +/** + * @} + */ + +/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version + * @{ + */ +#define CARD_V1_X 0x00000000U +#define CARD_V2_X 0x00000001U +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SD_Exported_macros SD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +/** @brief Reset SD handle state. + * @param __HANDLE__ : SD handle. + * @retval None + */ +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_SD_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SD_STATE_RESET) +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @brief Enable the SD device. + * @retval None + */ +#define __HAL_SD_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SD device. + * @retval None + */ +#define __HAL_SD_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_SD_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance) + +/** + * @brief Disable the SDMMC DMA transfer. + * @retval None + */ +#define __HAL_SD_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance) + +/** + * @brief Enable the SD device interrupt. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Disable the SD device interrupt. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Check whether the specified SD flag is set or not. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_CMDACT: Command transfer in progress + * @arg SDMMC_FLAG_TXACT: Data transmit in progress + * @arg SDMMC_FLAG_RXACT: Data receive in progress + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received + * @retval The new state of SD FLAG (SET or RESET). + */ +#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Clear the SD's pending flags. + * @param __HANDLE__: SD Handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received + * @retval None + */ +#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__)) + +/** + * @brief Check whether the specified SD interrupt has occurred or not. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @retval The new state of SD IT (SET or RESET). + */ +#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @brief Clear the SD's interrupt pending bits. + * @param __HANDLE__: SD Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__)) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SD_Exported_Functions SD Exported Functions + * @{ + */ + +/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd); +void HAL_SD_MspInit(SD_HandleTypeDef *hsd); +void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout); +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd); +/* Non-Blocking mode: IT */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks); + +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd); + +/* Callback in non blocking modes (DMA) */ +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd); +void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd); +void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd); + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/* SD callback registering/unregistering */ +HAL_StatusTypeDef HAL_SD_RegisterCallback (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId, pSD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackId); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group4 SD card related functions + * @{ + */ +HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions + * @{ + */ +HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd); +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management + * @{ + */ +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd); +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup SD_Private_Types SD Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SD_Private_Defines SD Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup SD_Private_Variables SD Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SD_Private_Constants SD Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SD_Private_Macros SD Private Macros + * @{ + */ + +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDMMC1 */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F7xx_HAL_SD_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h deleted file mode 100644 index 88ab6d84..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sdram.h +++ /dev/null @@ -1,236 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sdram.h - * @author MCD Application Team - * @brief Header file of SDRAM HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SDRAM_H -#define STM32F7xx_HAL_SDRAM_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_fmc.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SDRAM - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ - -/** @defgroup SDRAM_Exported_Types SDRAM Exported Types - * @{ - */ - -/** - * @brief HAL SDRAM State structure definition - */ -typedef enum -{ - HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ - HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ - HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ - HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ - HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ - HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ - -} HAL_SDRAM_StateTypeDef; - -/** - * @brief SDRAM handle Structure definition - */ -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) -typedef struct __SDRAM_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ -{ - FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ - - FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ - - __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ - - HAL_LockTypeDef Lock; /*!< SDRAM locking object */ - - DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ - -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ - void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ - void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ - void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Error callback */ -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ -} SDRAM_HandleTypeDef; - -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) -/** - * @brief HAL SDRAM Callback ID enumeration definition - */ -typedef enum -{ - HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */ - HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */ - HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ - HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ - HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ -} HAL_SDRAM_CallbackIDTypeDef; - -/** - * @brief HAL SDRAM Callback pointer definition - */ -typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); -typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros - * @{ - */ - -/** @brief Reset SDRAM handle state - * @param __HANDLE__ specifies the SDRAM handle. - * @retval None - */ -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) -#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions - * @{ - */ - -/** @addtogroup SDRAM_Exported_Functions_Group1 - * @{ - */ - -/* Initialization/de-initialization functions *********************************/ -HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); -HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram); -void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); -void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram); - -void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); -void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); -void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/** @addtogroup SDRAM_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, - uint32_t BufferSize); - -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, - uint32_t BufferSize); - -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) -/* SDRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, - pSDRAM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, - pSDRAM_DmaCallbackTypeDef pCallback); -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup SDRAM_Exported_Functions_Group3 - * @{ - */ -/* SDRAM Control functions *****************************************************/ -HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); -HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); -HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); -uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); - -/** - * @} - */ - -/** @addtogroup SDRAM_Exported_Functions_Group4 - * @{ - */ -/* SDRAM State functions ********************************************************/ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_SDRAM_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h deleted file mode 100644 index 364e6b9a..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard.h +++ /dev/null @@ -1,1149 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_smartcard.h - * @author MCD Application Team - * @brief Header file of SMARTCARD HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SMARTCARD_H -#define STM32F7xx_HAL_SMARTCARD_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SMARTCARD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types - * @{ - */ - -/** - * @brief SMARTCARD Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate. - The baud rate register is computed using the following formula: - Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate))) - where usart_ker_ckpres is the USART input clock divided by a prescaler */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter @ref SMARTCARD_Word_Length can only be - set to 9 (8 data + 1 parity bits). */ - - uint32_t StopBits; /*!< Specifies the number of stop bits. - This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ - - uint16_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref SMARTCARD_Parity - @note The parity is enabled by default (PCE is forced to 1). - Since the WordLength is forced to 8 bits + parity, M is - forced to 1 and the parity bit is the 9th bit. */ - - uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref SMARTCARD_Mode */ - - uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref SMARTCARD_Clock_Polarity */ - - uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SMARTCARD_Clock_Phase */ - - uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref SMARTCARD_Last_Bit */ - - uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote - is selected. Selecting the single sample method increases - the receiver tolerance to clock deviations. This parameter can be a value - of @ref SMARTCARD_OneBit_Sampling. */ - - uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is - multiplied by 2 to give the division factor of the source clock frequency */ - - uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ - - uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled - in case of parity error. - This parameter can be a value of @ref SMARTCARD_NACK_Enable */ - - uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled. - This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/ - - uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks: - it is used to implement the Character Wait Time (CWT) and - Block Wait Time (BWT). It is coded over 24 bits. */ - - uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode. - This parameter can be any value from 0x0 to 0xFF */ - - uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in - receive and transmit mode). When set to 0, retransmission is - disabled. Otherwise, its maximum value is 7 (before signalling - an error) */ - -} SMARTCARD_InitTypeDef; - -/** - * @brief SMARTCARD advanced features initialization structure definition - */ -typedef struct -{ - uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several - advanced features may be initialized at the same time. This parameter - can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */ - - uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref SMARTCARD_Tx_Inv */ - - uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref SMARTCARD_Rx_Inv */ - - uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic - vs negative/inverted logic). - This parameter can be a value of @ref SMARTCARD_Data_Inv */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. - This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. - This parameter can be a value of @ref SMARTCARD_Overrun_Disable */ - - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. - This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. - This parameter can be a value of @ref SMARTCARD_MSB_First */ - - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when - relevant flag is available) or once guard time period has elapsed. - This parameter can be a value - of @ref SMARTCARDEx_Transmission_Completion_Indication. */ -} SMARTCARD_AdvFeatureInitTypeDef; - -/** - * @brief HAL SMARTCARD State definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: - * gState and RxState (see @ref SMARTCARD_State_Definition). - * - gState contains SMARTCARD state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (Peripheral busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef uint32_t HAL_SMARTCARD_StateTypeDef; - -/** - * @brief SMARTCARD handle Structure definition - */ -typedef struct __SMARTCARD_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< USART registers base address */ - - SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ - - SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */ - - const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */ - - - void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - - DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global - Handle management and also related to Tx operations. - This parameter can be a value - of @ref HAL_SMARTCARD_StateTypeDef */ - - __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value - of @ref HAL_SMARTCARD_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< SmartCard Error code */ - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */ - - void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */ - - void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */ - - void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */ - - void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */ - - void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */ - - void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */ - - void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */ -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ - -} SMARTCARD_HandleTypeDef; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -/** - * @brief HAL SMARTCARD Callback ID enumeration definition - */ -typedef enum -{ - HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */ - HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */ - HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */ - HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */ - HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */ - HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */ - - HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */ - HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */ - -} HAL_SMARTCARD_CallbackIDTypeDef; - -/** - * @brief HAL SMARTCARD Callback pointer definition - */ -typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */ - -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ - -/** - * @brief SMARTCARD clock sources - */ -typedef enum -{ - SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */ -} SMARTCARD_ClockSourceTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants - * @{ - */ - -/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition - * @{ - */ -#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value - is allowed for gState and RxState */ -#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for - use. Value is allowed for gState - and RxState */ -#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ -#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing - Value is allowed for RxState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception - process is ongoing Not to be used for - neither gState nor RxState. - Value is result of combination (Or) - between gState and RxState values */ -#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ -#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition - * @{ - */ -#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length - * @{ - */ -#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits - * @{ - */ -#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */ -#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Parity SMARTCARD Parity - * @{ - */ -#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */ -#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode - * @{ - */ -#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */ -#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */ -#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity - * @{ - */ -#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */ -#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase - * @{ - */ -#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */ -#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit - * @{ - */ -#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */ -#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */ -/** - * @} - */ - -/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method - * @{ - */ -#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */ -#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */ -/** - * @} - */ - -/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable - * @{ - */ -#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */ -#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable - * @{ - */ -#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */ -#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion - * @{ - */ -#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ -#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion - * @{ - */ -#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ -#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion - * @{ - */ -#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ -#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap - * @{ - */ -#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ -#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable - * @{ - */ -#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ -#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ -/** - * @} - */ - -/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error - * @{ - */ -#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ -#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ -/** - * @} - */ - -/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first - * @{ - */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters - * @{ - */ -#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */ -#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */ -/** - * @} - */ - -/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask - * @{ - */ -#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */ -#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */ -#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */ -#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */ -#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros - * @{ - */ - -/** @brief Reset SMARTCARD handle states. - * @param __HANDLE__ SMARTCARD handle. - * @retval None - */ -#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 -#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \ - } while(0U) -#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ - -/** @brief Flush the Smartcard Data registers. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ - } while(0U) - -/** @brief Clear the specified SMARTCARD pending flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag - * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag - * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag - * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag - * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag - * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag - * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag - * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag - * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** @brief Clear the SMARTCARD PE pending flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF) - -/** @brief Clear the SMARTCARD FE pending flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF) - -/** @brief Clear the SMARTCARD NE pending flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF) - -/** @brief Clear the SMARTCARD ORE pending flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF) - -/** @brief Clear the SMARTCARD IDLE pending flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF) - -/** @brief Check whether the specified Smartcard flag is set or not. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available) - * @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag - * @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag - * @arg @ref SMARTCARD_FLAG_BUSY Busy flag - * @arg @ref SMARTCARD_FLAG_EOBF End of block flag - * @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag - * @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag - * @arg @ref SMARTCARD_FLAG_TC Transmission complete flag - * @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag - * @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag - * @arg @ref SMARTCARD_FLAG_ORE Overrun error flag - * @arg @ref SMARTCARD_FLAG_NE Noise error flag - * @arg @ref SMARTCARD_FLAG_FE Framing error flag - * @arg @ref SMARTCARD_FLAG_PE Parity error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - -/** @brief Enable the specified SmartCard interrupt. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable. - * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before - * guard time interrupt (when interruption available) - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ - SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1UL <<\ - ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ - SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1UL <<\ - ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1UL <<\ - ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) - -/** @brief Disable the specified SmartCard interrupt. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable. - * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard - * time interrupt (when interruption available) - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ - SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ - ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ - SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ - ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ - ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) - -/** @brief Check whether the specified SmartCard interrupt has occurred or not. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __INTERRUPT__ specifies the SMARTCARD interrupt to check. - * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time - * interrupt (when interruption available) - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ - (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ - & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ - ? SET : RESET) - -/** @brief Check whether the specified SmartCard interrupt source is enabled or not. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref SMARTCARD_IT_EOB End of block interrupt - * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt - * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt - * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time - * interrupt (when interruption available) - * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt - * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt - * @arg @ref SMARTCARD_IT_PE Parity error interrupt - * @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ - SMARTCARD_CR_POS) == 0x01U)?\ - (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ - SMARTCARD_CR_POS) == 0x02U)?\ - (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) &\ - (0x01UL << (((uint16_t)(__INTERRUPT__))\ - & SMARTCARD_IT_MASK))) != 0U)\ - ? SET : RESET) - -/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt. - * This parameter can be one of the following values: - * @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag - * @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag - * @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag - * @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag - * @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag - * @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag - * @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available) - * @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag - * @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag - * @retval None - */ -#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__)) - -/** @brief Set a specific SMARTCARD request flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __REQ__ specifies the request flag to set - * This parameter can be one of the following values: - * @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request - * @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request - * @retval None - */ -#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) - -/** @brief Enable the SMARTCARD one bit sample method. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disable the SMARTCARD one bit sample method. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ - &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) - -/** @brief Enable the USART associated to the SMARTCARD Handle. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable the USART associated to the SMARTCARD Handle - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @retval None - */ -#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** - * @} - */ - -/* Private macros -------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros - * @{ - */ - -/** @brief Report the SMARTCARD clock source. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__. - */ -#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ - case RCC_USART6CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART6CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART6CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART6CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) - -/** @brief Check the Baud rate range. - * @note The maximum Baud Rate is derived from the maximum clock on F7 (216 MHz) - * divided by the oversampling used on the SMARTCARD (i.e. 16). - * @param __BAUDRATE__ Baud rate set by the configuration function. - * @retval Test result (TRUE or FALSE) - */ -#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 13500001U) - -/** @brief Check the block length range. - * @note The maximum SMARTCARD block length is 0xFF. - * @param __LENGTH__ block length. - * @retval Test result (TRUE or FALSE) - */ -#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU) - -/** @brief Check the receiver timeout value. - * @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF. - * @param __TIMEOUTVALUE__ receiver timeout value. - * @retval Test result (TRUE or FALSE) - */ -#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) - -/** @brief Check the SMARTCARD autoretry counter value. - * @note The maximum number of retransmissions is 0x7. - * @param __COUNT__ number of retransmissions. - * @retval Test result (TRUE or FALSE) - */ -#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U) - -/** @brief Ensure that SMARTCARD frame length is valid. - * @param __LENGTH__ SMARTCARD frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B) - -/** @brief Ensure that SMARTCARD frame number of stop bits is valid. - * @param __STOPBITS__ SMARTCARD frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\ - ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5)) - -/** @brief Ensure that SMARTCARD frame parity is valid. - * @param __PARITY__ SMARTCARD frame parity. - * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ -#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \ - ((__PARITY__) == SMARTCARD_PARITY_ODD)) - -/** @brief Ensure that SMARTCARD communication mode is valid. - * @param __MODE__ SMARTCARD communication mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) - -/** @brief Ensure that SMARTCARD frame polarity is valid. - * @param __CPOL__ SMARTCARD frame polarity. - * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) - */ -#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\ - || ((__CPOL__) == SMARTCARD_POLARITY_HIGH)) - -/** @brief Ensure that SMARTCARD frame phase is valid. - * @param __CPHA__ SMARTCARD frame phase. - * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) - */ -#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE)) - -/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid. - * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting. - * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) - */ -#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \ - ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE)) - -/** @brief Ensure that SMARTCARD frame sampling is valid. - * @param __ONEBIT__ SMARTCARD frame sampling. - * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ -#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ - ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) - -/** @brief Ensure that SMARTCARD NACK transmission setting is valid. - * @param __NACK__ SMARTCARD NACK transmission setting. - * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid) - */ -#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \ - ((__NACK__) == SMARTCARD_NACK_DISABLE)) - -/** @brief Ensure that SMARTCARD receiver timeout setting is valid. - * @param __TIMEOUT__ SMARTCARD receiver timeout setting. - * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) - */ -#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE)) - -/** @brief Ensure that SMARTCARD advanced features initialization is valid. - * @param __INIT__ SMARTCARD advanced features initialization. - * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) - */ -#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \ - SMARTCARD_ADVFEATURE_TXINVERT_INIT | \ - SMARTCARD_ADVFEATURE_RXINVERT_INIT | \ - SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \ - SMARTCARD_ADVFEATURE_SWAP_INIT | \ - SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \ - SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) - -/** @brief Ensure that SMARTCARD frame TX inversion setting is valid. - * @param __TXINV__ SMARTCARD frame TX inversion setting. - * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) - */ -#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \ - ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE)) - -/** @brief Ensure that SMARTCARD frame RX inversion setting is valid. - * @param __RXINV__ SMARTCARD frame RX inversion setting. - * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) - */ -#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \ - ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE)) - -/** @brief Ensure that SMARTCARD frame data inversion setting is valid. - * @param __DATAINV__ SMARTCARD frame data inversion setting. - * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) - */ -#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \ - ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE)) - -/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid. - * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting. - * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) - */ -#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \ - ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE)) - -/** @brief Ensure that SMARTCARD frame overrun setting is valid. - * @param __OVERRUN__ SMARTCARD frame overrun setting. - * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) - */ -#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \ - ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE)) - -/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid. - * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting. - * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) - */ -#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR)) - -/** @brief Ensure that SMARTCARD frame MSB first setting is valid. - * @param __MSBFIRST__ SMARTCARD frame MSB first setting. - * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) - */ -#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE)) - -/** @brief Ensure that SMARTCARD request parameter is valid. - * @param __PARAM__ SMARTCARD request parameter. - * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ -#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \ - ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST)) - -/** - * @} - */ - -/* Include SMARTCARD HAL Extended module */ -#include "stm32f7xx_hal_smartcard_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SMARTCARD_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -/** @addtogroup SMARTCARD_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard); -HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -/* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, - pSMARTCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* IO operation functions *****************************************************/ -/** @addtogroup SMARTCARD_Exported_Functions_Group2 - * @{ - */ - -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard); -HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard); -HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard); -HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard); -HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); -HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard); - -void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); -void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard); - -/** - * @} - */ - -/* Peripheral State and Error functions ***************************************/ -/** @addtogroup SMARTCARD_Exported_Functions_Group4 - * @{ - */ - -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard); -uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_SMARTCARD_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h deleted file mode 100644 index 1e63166d..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smartcard_ex.h +++ /dev/null @@ -1,268 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_smartcard_ex.h - * @author MCD Application Team - * @brief Header file of SMARTCARD HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SMARTCARD_EX_H -#define STM32F7xx_HAL_SMARTCARD_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SMARTCARDEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants - * @{ - */ - -/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication - * @{ - */ -#if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */ -#endif /* USART_TCBGT_SUPPORT */ -#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */ -/** - * @} - */ - -/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type - * @{ - */ -#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ -#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ -#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ -#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ -#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ -#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ -#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ -#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ -#if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */ -#endif /* USART_TCBGT_SUPPORT */ -/** - * @} - */ - -/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */ -#endif /* USART_TCBGT_SUPPORT */ -#if defined(USART_ISR_REACK) -#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */ -#endif /* USART_ISR_REACK */ -#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */ -#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */ -#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */ -#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */ -#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */ -#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */ -#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */ -#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */ -#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */ -#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */ -#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */ -#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */ -/** - * @} - */ - -/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition - * Elements values convention: 000ZZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5 bits) - * - XX : Interrupt source register (2 bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZZ : Flag position in the ISR register(5 bits) - * @{ - */ -#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */ -#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */ -#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */ -#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */ -#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */ - -#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */ -#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */ -#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */ -#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */ - -#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */ -#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */ -#if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */ -#endif /* USART_TCBGT_SUPPORT */ - -/** - * @} - */ - -/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags - * @{ - */ -#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */ -#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */ -#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise error detected clear flag */ -#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */ -#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */ -#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */ -#if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */ -#endif /* USART_TCBGT_SUPPORT */ -#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */ -#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */ -/** - * @} - */ - -/** - * @} - */ -/* Exported macros -----------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros - * @{ - */ - -/** @brief Set the Transmission Completion flag - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if - * AdvancedInit.TxCompletionIndication is not already filled, the latter is forced - * to SMARTCARD_TC (transmission completion indication when guard time has elapsed). - * @retval None - */ -#if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ - do { \ - if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \ - { \ - (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ - } \ - else \ - { \ - assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \ - } \ - } while(0U) -#else -#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \ - do { \ - (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \ - } while(0U) -#endif /* USART_TCBGT_SUPPORT */ - -/** @brief Return the transmission completion flag. - * @param __HANDLE__ specifies the SMARTCARD Handle. - * @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag. - * When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is - * reported. - * @retval Transmission completion flag - */ -#if defined(USART_TCBGT_SUPPORT) -#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \ - (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT)) -#else -#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) (SMARTCARD_FLAG_TC) -#endif /* USART_TCBGT_SUPPORT */ - - -/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid. - * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag. - * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid) - */ -#if defined(USART_TCBGT_SUPPORT) -#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \ - ((__TXCOMPLETE__) == SMARTCARD_TC)) -#else -#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) ((__TXCOMPLETE__) == SMARTCARD_TC) -#endif /* USART_TCBGT_SUPPORT */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SMARTCARDEx_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -/* IO operation methods *******************************************************/ - -/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 - * @{ - */ - -/* Peripheral Control functions ***********************************************/ -void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength); -void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue); -HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); -HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard); - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SMARTCARDEx_Exported_Functions_Group2 - * @{ - */ - -/* IO operation functions *****************************************************/ - -/** - * @} - */ - - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_SMARTCARD_EX_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h deleted file mode 100644 index 6752fc66..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h +++ /dev/null @@ -1,787 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_smbus.h - * @author MCD Application Team - * @brief Header file of SMBUS HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SMBUS_H -#define STM32F7xx_HAL_SMBUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SMBUS - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SMBUS_Exported_Types SMBUS Exported Types - * @{ - */ - -/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition - * @brief SMBUS Configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. - This parameter calculated by referring to SMBUS initialization section - in Reference manual */ - uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. - This parameter can be a value of @ref SMBUS_Analog_Filter */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. - This parameter can be a value of @ref SMBUS_addressing_mode */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref SMBUS_dual_addressing_mode */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address - if dual addressing mode is selected - This parameter can be a value of @ref SMBUS_own_address2_masks. */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref SMBUS_nostretch_mode */ - - uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. - This parameter can be a value of @ref SMBUS_packet_error_check_mode */ - - uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. - This parameter can be a value of @ref SMBUS_peripheral_mode */ - - uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to SMBUS initialization section - in Reference manual */ -} SMBUS_InitTypeDef; -/** - * @} - */ - -/** @defgroup HAL_state_definition HAL state definition - * @brief HAL State definition - * @{ - */ -#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ -#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ -#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ -#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ -#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ -/** - * @} - */ - -/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition - * @brief SMBUS Error Code definition - * @{ - */ -#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ -#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ -#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ -#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ -#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ -#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ -#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ -#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ -/** - * @} - */ - -/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition - * @brief SMBUS handle Structure definition - * @{ - */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -typedef struct __SMBUS_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ -{ - I2C_TypeDef *Instance; /*!< SMBUS registers base address */ - - SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ - - uint16_t XferSize; /*!< SMBUS transfer size */ - - __IO uint16_t XferCount; /*!< SMBUS transfer counter */ - - __IO uint32_t XferOptions; /*!< SMBUS transfer options */ - - __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ - - HAL_LockTypeDef Lock; /*!< SMBUS locking object */ - - __IO uint32_t State; /*!< SMBUS communication state */ - - __IO uint32_t ErrorCode; /*!< SMBUS Error code */ - -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); - /*!< SMBUS Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); - /*!< SMBUS Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); - /*!< SMBUS Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); - /*!< SMBUS Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); - /*!< SMBUS Listen Complete callback */ - void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); - /*!< SMBUS Error callback */ - - void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); - /*!< SMBUS Slave Address Match callback */ - - void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); - /*!< SMBUS Msp Init callback */ - void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); - /*!< SMBUS Msp DeInit callback */ - -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ -} SMBUS_HandleTypeDef; - -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -/** - * @brief HAL SMBUS Callback ID enumeration definition - */ -typedef enum -{ - HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ - HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ - HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ - HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ - HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ - HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ - - HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ - HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ - -} HAL_SMBUS_CallbackIDTypeDef; - -/** - * @brief HAL SMBUS Callback pointer definition - */ -typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); -/*!< pointer to an SMBUS callback function */ -typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, - uint16_t AddrMatchCode); -/*!< pointer to an SMBUS Address Match callback function */ - -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants - * @{ - */ - -/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter - * @{ - */ -#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) -#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -/** - * @} - */ - -/** @defgroup SMBUS_addressing_mode SMBUS addressing mode - * @{ - */ -#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) -#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode - * @{ - */ - -#define SMBUS_DUALADDRESS_DISABLE (0x00000000U) -#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -/** - * @} - */ - -/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks - * @{ - */ - -#define SMBUS_OA2_NOMASK ((uint8_t)0x00U) -#define SMBUS_OA2_MASK01 ((uint8_t)0x01U) -#define SMBUS_OA2_MASK02 ((uint8_t)0x02U) -#define SMBUS_OA2_MASK03 ((uint8_t)0x03U) -#define SMBUS_OA2_MASK04 ((uint8_t)0x04U) -#define SMBUS_OA2_MASK05 ((uint8_t)0x05U) -#define SMBUS_OA2_MASK06 ((uint8_t)0x06U) -#define SMBUS_OA2_MASK07 ((uint8_t)0x07U) -/** - * @} - */ - - -/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode - * @{ - */ -#define SMBUS_GENERALCALL_DISABLE (0x00000000U) -#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN -/** - * @} - */ - -/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode - * @{ - */ -#define SMBUS_NOSTRETCH_DISABLE (0x00000000U) -#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode - * @{ - */ -#define SMBUS_PEC_DISABLE (0x00000000U) -#define SMBUS_PEC_ENABLE I2C_CR1_PECEN -/** - * @} - */ - -/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode - * @{ - */ -#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN -#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) -#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN -/** - * @} - */ - -/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition - * @{ - */ - -#define SMBUS_SOFTEND_MODE (0x00000000U) -#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD -#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND -#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE -/** - * @} - */ - -/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition - * @{ - */ - -#define SMBUS_NO_STARTSTOP (0x00000000U) -#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) -#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/** - * @} - */ - -/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition - * @{ - */ - -/* List of XferOptions in usage of : - * 1- Restart condition when direction change - * 2- No Restart condition in other use cases - */ -#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE -#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) -#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE -#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE -#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) -#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) -#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) - -/* List of XferOptions in usage of : - * 1- Restart condition in all use cases (direction change or not) - */ -#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) -#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) -#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) -#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) -/** - * @} - */ - -/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition - * @brief SMBUS Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask - * @{ - */ -#define SMBUS_IT_ERRI I2C_CR1_ERRIE -#define SMBUS_IT_TCI I2C_CR1_TCIE -#define SMBUS_IT_STOPI I2C_CR1_STOPIE -#define SMBUS_IT_NACKI I2C_CR1_NACKIE -#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE -#define SMBUS_IT_RXI I2C_CR1_RXIE -#define SMBUS_IT_TXI I2C_CR1_TXIE -#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ - SMBUS_IT_NACKI | SMBUS_IT_TXI) -#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ - SMBUS_IT_RXI) -#define SMBUS_IT_ALERT (SMBUS_IT_ERRI) -#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) -/** - * @} - */ - -/** @defgroup SMBUS_Flag_definition SMBUS Flag definition - * @brief Flag definition - * Elements values convention: 0xXXXXYYYY - * - XXXXXXXX : Flag mask - * @{ - */ - -#define SMBUS_FLAG_TXE I2C_ISR_TXE -#define SMBUS_FLAG_TXIS I2C_ISR_TXIS -#define SMBUS_FLAG_RXNE I2C_ISR_RXNE -#define SMBUS_FLAG_ADDR I2C_ISR_ADDR -#define SMBUS_FLAG_AF I2C_ISR_NACKF -#define SMBUS_FLAG_STOPF I2C_ISR_STOPF -#define SMBUS_FLAG_TC I2C_ISR_TC -#define SMBUS_FLAG_TCR I2C_ISR_TCR -#define SMBUS_FLAG_BERR I2C_ISR_BERR -#define SMBUS_FLAG_ARLO I2C_ISR_ARLO -#define SMBUS_FLAG_OVR I2C_ISR_OVR -#define SMBUS_FLAG_PECERR I2C_ISR_PECERR -#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define SMBUS_FLAG_ALERT I2C_ISR_ALERT -#define SMBUS_FLAG_BUSY I2C_ISR_BUSY -#define SMBUS_FLAG_DIR I2C_ISR_DIR -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ -/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros - * @{ - */ - -/** @brief Reset SMBUS handle state. - * @param __HANDLE__ specifies the SMBUS Handle. - * @retval None - */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - -/** @brief Enable the specified SMBUS interrupts. - * @param __HANDLE__ specifies the SMBUS Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref SMBUS_IT_ERRI Errors interrupt enable - * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable - * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable - * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable - * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable - * @arg @ref SMBUS_IT_RXI RX interrupt enable - * @arg @ref SMBUS_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified SMBUS interrupts. - * @param __HANDLE__ specifies the SMBUS Handle. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref SMBUS_IT_ERRI Errors interrupt enable - * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable - * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable - * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable - * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable - * @arg @ref SMBUS_IT_RXI RX interrupt enable - * @arg @ref SMBUS_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified SMBUS interrupt source is enabled or not. - * @param __HANDLE__ specifies the SMBUS Handle. - * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref SMBUS_IT_ERRI Errors interrupt enable - * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable - * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable - * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable - * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable - * @arg @ref SMBUS_IT_RXI RX interrupt enable - * @arg @ref SMBUS_IT_TXI TX interrupt enable - * - * @retval The new state of __IT__ (SET or RESET). - */ -#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified SMBUS flag is set or not. - * @param __HANDLE__ specifies the SMBUS Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref SMBUS_FLAG_TXE Transmit data register empty - * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status - * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty - * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag - * @arg @ref SMBUS_FLAG_STOPF STOP detection flag - * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) - * @arg @ref SMBUS_FLAG_TCR Transfer complete reload - * @arg @ref SMBUS_FLAG_BERR Bus error - * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun - * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref SMBUS_FLAG_ALERT SMBus alert - * @arg @ref SMBUS_FLAG_BUSY Bus busy - * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define SMBUS_FLAG_MASK (0x0001FFFFU) -#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ - (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ - ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) - -/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__ specifies the SMBUS Handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg @ref SMBUS_FLAG_TXE Transmit data register empty - * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) - * @arg @ref SMBUS_FLAG_AF NACK received flag - * @arg @ref SMBUS_FLAG_STOPF STOP detection flag - * @arg @ref SMBUS_FLAG_BERR Bus error - * @arg @ref SMBUS_FLAG_ARLO Arbitration lost - * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun - * @arg @ref SMBUS_FLAG_PECERR PEC error in reception - * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref SMBUS_FLAG_ALERT SMBus alert - * - * @retval None - */ -#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ - ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ - ((__HANDLE__)->Instance->ICR = (__FLAG__))) - -/** @brief Enable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. - * @retval None - */ -#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Disable the specified SMBUS peripheral. - * @param __HANDLE__ specifies the SMBUS Handle. - * @retval None - */ -#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. - * @param __HANDLE__ specifies the SMBUS Handle. - * @retval None - */ -#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) - -/** - * @} - */ - - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SMBUS_Private_Macro SMBUS Private Macros - * @{ - */ - -#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ - ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) - -#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) - -#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ - ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) - -#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) - -#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ - ((MASK) == SMBUS_OA2_MASK01) || \ - ((MASK) == SMBUS_OA2_MASK02) || \ - ((MASK) == SMBUS_OA2_MASK03) || \ - ((MASK) == SMBUS_OA2_MASK04) || \ - ((MASK) == SMBUS_OA2_MASK05) || \ - ((MASK) == SMBUS_OA2_MASK06) || \ - ((MASK) == SMBUS_OA2_MASK07)) - -#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ - ((CALL) == SMBUS_GENERALCALL_ENABLE)) - -#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ - ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) - -#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ - ((PEC) == SMBUS_PEC_ENABLE)) - -#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ - ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) - -#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ - ((MODE) == SMBUS_AUTOEND_MODE) || \ - ((MODE) == SMBUS_SOFTEND_MODE) || \ - ((MODE) == SMBUS_SENDPEC_MODE) || \ - ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ - ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ - SMBUS_RELOAD_MODE ))) - - -#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ - ((REQUEST) == SMBUS_GENERATE_START_READ) || \ - ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ - ((REQUEST) == SMBUS_NO_STARTSTOP)) - - -#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == SMBUS_FIRST_FRAME) || \ - ((REQUEST) == SMBUS_NEXT_FRAME) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) - -#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ - ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) - -#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ - (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ - I2C_CR1_PECEN))) -#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ - I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ - I2C_CR2_RD_WRN))) - -#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ - (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & \ - (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ - (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) - -#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) -#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) -#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) -#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) - -#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ - ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) -#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) - -#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) -#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions - * @{ - */ - -/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, - HAL_SMBUS_CallbackIDTypeDef CallbackID, - pSMBUS_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, - HAL_SMBUS_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, - pSMBUS_AddrCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -/** @addtogroup Blocking_mode_Polling Blocking mode Polling - * @{ - */ -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout); -/** - * @} - */ - -/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt - * @{ - */ -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); - -HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); -HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); -/** - * @} - */ - -/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ -/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ -void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); -void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); - -/** - * @} - */ - -/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ - -/* Peripheral State and Errors functions **************************************************/ -uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus); -uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus); - -/** - * @} - */ - -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup SMBUS_Private_Functions SMBUS Private Functions - * @{ - */ -/* Private functions are defined in stm32f7xx_hal_smbus.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_SMBUS_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h deleted file mode 100644 index a46c701b..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spdifrx.h +++ /dev/null @@ -1,616 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_spdifrx.h - * @author MCD Application Team - * @brief Header file of SPDIFRX HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SPDIFRX_H -#define STM32F7xx_HAL_SPDIFRX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (SPDIFRX) - -/** @addtogroup SPDIFRX - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types - * @{ - */ - -/** - * @brief SPDIFRX Init structure definition - */ -typedef struct -{ - uint32_t InputSelection; /*!< Specifies the SPDIF input selection. - This parameter can be a value of @ref SPDIFRX_Input_Selection */ - - uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase. - This parameter can be a value of @ref SPDIFRX_Max_Retries */ - - uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input. - This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */ - - uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status - from channel A or B. - This parameter can be a value of @ref SPDIFRX_Channel_Selection */ - - uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). - This parameter can be a value of @ref SPDIFRX_Data_Format */ - - uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. - This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ - - uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not - into the received frame. - This parameter can be a value of @ref SPDIFRX_PT_Mask */ - - uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not - into the received frame. - This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ - - uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_V_Mask */ - - uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not - into the received frame. - This parameter can be a value of @ref SPDIFRX_PE_Mask */ -} SPDIFRX_InitTypeDef; - -/** - * @brief SPDIFRX SetDataFormat structure definition - */ -typedef struct -{ - uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...). - This parameter can be a value of @ref SPDIFRX_Data_Format */ - - uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. - This parameter can be a value of @ref SPDIFRX_Stereo_Mode */ - - uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not - into the received frame. - This parameter can be a value of @ref SPDIFRX_PT_Mask */ - - uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not - into the received frame. - This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */ - - uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame. - This parameter can be a value of @ref SPDIFRX_V_Mask */ - - uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not - into the received frame. - This parameter can be a value of @ref SPDIFRX_PE_Mask */ - -} SPDIFRX_SetDataFormatTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */ - HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */ - HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */ - HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */ - HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */ - HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */ -} HAL_SPDIFRX_StateTypeDef; - -/** - * @brief SPDIFRX handle Structure definition - */ -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -typedef struct __SPDIFRX_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -{ - SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */ - - SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */ - - uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */ - - uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */ - - __IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */ - - __IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter - (This field is initialized at the - same value as transfer size at the - beginning of the transfer and - decremented when a sample is received. - NbSamplesReceived = RxBufferSize-RxBufferCount) */ - - __IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */ - - __IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter - (This field is initialized at the - same value as transfer size at the - beginning of the transfer and - decremented when a sample is received. - NbSamplesReceived = RxBufferSize-RxBufferCount) */ - - DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information - DMA handle parameters */ - - DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */ - - __IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */ - - __IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */ - - __IO uint32_t ErrorCode; /* SPDIFRX Error code */ - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow half completed - callback */ - void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Data flow completed callback */ - void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed - callback */ - void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */ - void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */ - void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */ - void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp DeInit callback */ -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - -} SPDIFRX_HandleTypeDef; - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -/** - * @brief HAL SPDIFRX Callback ID enumeration definition - */ -typedef enum -{ - HAL_SPDIFRX_RX_HALF_CB_ID = 0x00U, /*!< SPDIFRX Data flow half completed callback ID */ - HAL_SPDIFRX_RX_CPLT_CB_ID = 0x01U, /*!< SPDIFRX Data flow completed callback */ - HAL_SPDIFRX_CX_HALF_CB_ID = 0x02U, /*!< SPDIFRX Control flow half completed callback */ - HAL_SPDIFRX_CX_CPLT_CB_ID = 0x03U, /*!< SPDIFRX Control flow completed callback */ - HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */ - HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */ - HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */ -} HAL_SPDIFRX_CallbackIDTypeDef; - -/** - * @brief HAL SPDIFRX Callback pointer definition - */ -typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback - function */ -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants - * @{ - */ -/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code - * @{ - */ -#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ -#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */ -#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */ -#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ -#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */ -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -#define HAL_SPDIFRX_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection - * @{ - */ -#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U) -#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U) -#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U) -#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U) -/** - * @} - */ - -/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries - * @{ - */ -#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U) -#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U) -#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U) -#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U) -/** - * @} - */ - -/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity - * @{ - */ -#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U) -#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA) -/** - * @} - */ - -/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask - * @{ - */ -#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U) -#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK) -/** - * @} - */ - -/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask - * @{ - */ -#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied - into the SPDIF_DR */ -#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied - into the SPDIF_DR, zeros are written instead*/ -/** - * @} - */ - -/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask - * @{ - */ -#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) -#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) -/** - * @} - */ - -/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask - * @{ - */ -#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U) -#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK) -/** - * @} - */ - -/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection - * @{ - */ -#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U) -#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL) -/** - * @} - */ - -/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format - * @{ - */ -#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U) -#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U) -#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U) -/** - * @} - */ - -/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode - * @{ - */ -#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U) -#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO) -/** - * @} - */ - -/** @defgroup SPDIFRX_State SPDIFRX State - * @{ - */ - -#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU) -#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U) -#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN) -/** - * @} - */ - -/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition - * @{ - */ -#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE) -#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE) -#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE) -#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE) -#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE) -#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE) -#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE ) -/** - * @} - */ - -/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition - * @{ - */ -#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE) -#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE) -#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR) -#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR) -#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD) -#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD) -#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR) -#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR) -#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros - * @{ - */ - -/** @brief Reset SPDIFRX handle state - * @param __HANDLE__ SPDIFRX handle. - * @retval None - */ -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0) -#else -#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET) -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - -/** @brief Disable the specified SPDIFRX peripheral (IDLE State). - * @param __HANDLE__ specifies the SPDIFRX Handle. - * @retval None - */ -#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) - -/** @brief Enable the specified SPDIFRX peripheral (SYNC State). - * @param __HANDLE__ specifies the SPDIFRX Handle. - * @retval None - */ -#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) - - -/** @brief Enable the specified SPDIFRX peripheral (RCV State). - * @param __HANDLE__ specifies the SPDIFRX Handle. - * @retval None - */ -#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) - - -/** @brief Enable or disable the specified SPDIFRX interrupts. - * @param __HANDLE__ specifies the SPDIFRX Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg SPDIFRX_IT_RXNE - * @arg SPDIFRX_IT_CSRNE - * @arg SPDIFRX_IT_PERRIE - * @arg SPDIFRX_IT_OVRIE - * @arg SPDIFRX_IT_SBLKIE - * @arg SPDIFRX_IT_SYNCDIE - * @arg SPDIFRX_IT_IFEIE - * @retval None - */ -#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) -#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\ - &= (uint16_t)(~(__INTERRUPT__))) - -/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. - * @param __HANDLE__ specifies the SPDIFRX Handle. - * @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check. - * This parameter can be one of the following values: - * @arg SPDIFRX_IT_RXNE - * @arg SPDIFRX_IT_CSRNE - * @arg SPDIFRX_IT_PERRIE - * @arg SPDIFRX_IT_OVRIE - * @arg SPDIFRX_IT_SBLKIE - * @arg SPDIFRX_IT_SYNCDIE - * @arg SPDIFRX_IT_IFEIE - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\ - & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks whether the specified SPDIFRX flag is set or not. - * @param __HANDLE__ specifies the SPDIFRX Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg SPDIFRX_FLAG_RXNE - * @arg SPDIFRX_FLAG_CSRNE - * @arg SPDIFRX_FLAG_PERR - * @arg SPDIFRX_FLAG_OVR - * @arg SPDIFRX_FLAG_SBD - * @arg SPDIFRX_FLAG_SYNCD - * @arg SPDIFRX_FLAG_FERR - * @arg SPDIFRX_FLAG_SERR - * @arg SPDIFRX_FLAG_TERR - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ - & (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. - * @param __HANDLE__ specifies the USART Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt - * This parameter can be one of the following values: - * @arg SPDIFRX_FLAG_PERR - * @arg SPDIFRX_FLAG_OVR - * @arg SPDIFRX_SR_SBD - * @arg SPDIFRX_SR_SYNCD - * @retval None - */ -#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPDIFRX_Exported_Functions - * @{ - */ - -/** @addtogroup SPDIFRX_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif); -HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif); -void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif); -void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif); -HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, - pSPDIFRX_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, - HAL_SPDIFRX_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup SPDIFRX_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ***************************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, - uint32_t Timeout); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); -void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif); - -/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ -void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); -void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); -void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif); -void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif); -void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); -/** - * @} - */ - -/** @addtogroup SPDIFRX_Exported_Functions_Group3 - * @{ - */ -/* Peripheral Control and State functions ************************************/ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif); -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif); -/** - * @} - */ - -/** - * @} - */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros - * @{ - */ -#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \ - ((INPUT) == SPDIFRX_INPUT_IN2) || \ - ((INPUT) == SPDIFRX_INPUT_IN3) || \ - ((INPUT) == SPDIFRX_INPUT_IN0)) - -#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \ - ((RET) == SPDIFRX_MAXRETRIES_3) || \ - ((RET) == SPDIFRX_MAXRETRIES_15) || \ - ((RET) == SPDIFRX_MAXRETRIES_63)) - -#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \ - ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) - -#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \ - ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) - -#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \ - ((VAL) == SPDIFRX_VALIDITYMASK_ON)) - -#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \ - ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) - -#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \ - ((CHANNEL) == SPDIFRX_CHANNEL_B)) - -#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \ - ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ - ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) - -#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \ - ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) - -#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \ - ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions - * @{ - */ -/** - * @} - */ - -/** - * @} - */ -#endif /* SPDIFRX */ -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_SPDIFRX_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h index 4b06a66f..6d062f0f 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h @@ -1,851 +1,855 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_spi.h - * @author MCD Application Team - * @brief Header file of SPI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SPI_H -#define STM32F7xx_HAL_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SPI_Exported_Types SPI Exported Types - * @{ - */ - -/** - * @brief SPI Configuration Structure definition - */ -typedef struct -{ - uint32_t Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_Mode */ - - uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. - This parameter can be a value of @ref SPI_Direction */ - - uint32_t DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_Data_Size */ - - uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_Slave_Select_management */ - - uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_transmission */ - - uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. - This parameter can be a value of @ref SPI_TI_mode */ - - uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. - This parameter can be a value of @ref SPI_CRC_Calculation */ - - uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ - - uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. - CRC Length is only used with Data8 and Data16, not other data size - This parameter can be a value of @ref SPI_CRC_length */ - - uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . - This parameter can be a value of @ref SPI_NSSP_Mode - This mode is activated by the NSSP bit in the SPIx_CR2 register and - it takes effect only if the SPI interface is configured as Motorola SPI - master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, - CPOL setting is ignored).. */ -} SPI_InitTypeDef; - -/** - * @brief HAL SPI State structure definition - */ -typedef enum -{ - HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ - HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ - HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ - HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ - HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ - HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ -} HAL_SPI_StateTypeDef; - -/** - * @brief SPI handle Structure definition - */ -typedef struct __SPI_HandleTypeDef -{ - SPI_TypeDef *Instance; /*!< SPI registers base address */ - - SPI_InitTypeDef Init; /*!< SPI communication parameters */ - - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< SPI Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< SPI Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ - - uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ - - void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ - - void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ - - DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ - - __IO uint32_t ErrorCode; /*!< SPI Error code */ - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ - void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ - void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ - void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ - void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ - void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ - void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ - void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ - void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ - void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ - -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} SPI_HandleTypeDef; - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -/** - * @brief HAL SPI Callback ID enumeration definition - */ -typedef enum -{ - HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ - HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ - HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ - HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ - HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ - HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ - HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ - HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ - HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ - HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ - -} HAL_SPI_CallbackIDTypeDef; - -/** - * @brief HAL SPI Callback pointer definition - */ -typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ - -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SPI_Exported_Constants SPI Exported Constants - * @{ - */ - -/** @defgroup SPI_Error_Code SPI Error Code - * @{ - */ -#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ -#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ -#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ -#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ -#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ -#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup SPI_Mode SPI Mode - * @{ - */ -#define SPI_MODE_SLAVE (0x00000000U) -#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) -/** - * @} - */ - -/** @defgroup SPI_Direction SPI Direction Mode - * @{ - */ -#define SPI_DIRECTION_2LINES (0x00000000U) -#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY -#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE -/** - * @} - */ - -/** @defgroup SPI_Data_Size SPI Data Size - * @{ - */ -#define SPI_DATASIZE_4BIT (0x00000300U) -#define SPI_DATASIZE_5BIT (0x00000400U) -#define SPI_DATASIZE_6BIT (0x00000500U) -#define SPI_DATASIZE_7BIT (0x00000600U) -#define SPI_DATASIZE_8BIT (0x00000700U) -#define SPI_DATASIZE_9BIT (0x00000800U) -#define SPI_DATASIZE_10BIT (0x00000900U) -#define SPI_DATASIZE_11BIT (0x00000A00U) -#define SPI_DATASIZE_12BIT (0x00000B00U) -#define SPI_DATASIZE_13BIT (0x00000C00U) -#define SPI_DATASIZE_14BIT (0x00000D00U) -#define SPI_DATASIZE_15BIT (0x00000E00U) -#define SPI_DATASIZE_16BIT (0x00000F00U) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity SPI Clock Polarity - * @{ - */ -#define SPI_POLARITY_LOW (0x00000000U) -#define SPI_POLARITY_HIGH SPI_CR1_CPOL -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase SPI Clock Phase - * @{ - */ -#define SPI_PHASE_1EDGE (0x00000000U) -#define SPI_PHASE_2EDGE SPI_CR1_CPHA -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_management SPI Slave Select Management - * @{ - */ -#define SPI_NSS_SOFT SPI_CR1_SSM -#define SPI_NSS_HARD_INPUT (0x00000000U) -#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) -/** - * @} - */ - -/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode - * @{ - */ -#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP -#define SPI_NSS_PULSE_DISABLE (0x00000000U) -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler - * @{ - */ -#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) -#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) -#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) -#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) -#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) -#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission - * @{ - */ -#define SPI_FIRSTBIT_MSB (0x00000000U) -#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST -/** - * @} - */ - -/** @defgroup SPI_TI_mode SPI TI Mode - * @{ - */ -#define SPI_TIMODE_DISABLE (0x00000000U) -#define SPI_TIMODE_ENABLE SPI_CR2_FRF -/** - * @} - */ - -/** @defgroup SPI_CRC_Calculation SPI CRC Calculation - * @{ - */ -#define SPI_CRCCALCULATION_DISABLE (0x00000000U) -#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN -/** - * @} - */ - -/** @defgroup SPI_CRC_length SPI CRC Length - * @{ - * This parameter can be one of the following values: - * SPI_CRC_LENGTH_DATASIZE: aligned with the data size - * SPI_CRC_LENGTH_8BIT : CRC 8bit - * SPI_CRC_LENGTH_16BIT : CRC 16bit - */ -#define SPI_CRC_LENGTH_DATASIZE (0x00000000U) -#define SPI_CRC_LENGTH_8BIT (0x00000001U) -#define SPI_CRC_LENGTH_16BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold - * @{ - * This parameter can be one of the following values: - * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : - * RXNE event is generated if the FIFO - * level is greater or equal to 1/4(8-bits). - * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO - * level is greater or equal to 1/2(16 bits). */ -#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH -#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH -#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) -/** - * @} - */ - -/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition - * @{ - */ -#define SPI_IT_TXE SPI_CR2_TXEIE -#define SPI_IT_RXNE SPI_CR2_RXNEIE -#define SPI_IT_ERR SPI_CR2_ERRIE -/** - * @} - */ - -/** @defgroup SPI_Flags_definition SPI Flags Definition - * @{ - */ -#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ -#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ -#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ -#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ -#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ -#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ -#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ -#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ -#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ -#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ - | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) -/** - * @} - */ - -/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level - * @{ - */ -#define SPI_FTLVL_EMPTY (0x00000000U) -#define SPI_FTLVL_QUARTER_FULL (0x00000800U) -#define SPI_FTLVL_HALF_FULL (0x00001000U) -#define SPI_FTLVL_FULL (0x00001800U) - -/** - * @} - */ - -/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level - * @{ - */ -#define SPI_FRLVL_EMPTY (0x00000000U) -#define SPI_FRLVL_QUARTER_FULL (0x00000200U) -#define SPI_FRLVL_HALF_FULL (0x00000400U) -#define SPI_FRLVL_FULL (0x00000600U) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup SPI_Exported_Macros SPI Exported Macros - * @{ - */ - -/** @brief Reset SPI handle state. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - -/** @brief Enable the specified SPI interrupts. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg SPI_IT_TXE: Tx buffer empty interrupt enable - * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable - * @arg SPI_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) - -/** @brief Disable the specified SPI interrupts. - * @param __HANDLE__ specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg SPI_IT_TXE: Tx buffer empty interrupt enable - * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable - * @arg SPI_IT_ERR: Error interrupt enable - * @retval None - */ -#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) - -/** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__ specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_IT_TXE: Tx buffer empty interrupt enable - * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable - * @arg SPI_IT_ERR: Error interrupt enable - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ - & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg SPI_FLAG_RXNE: Receive buffer not empty flag - * @arg SPI_FLAG_TXE: Transmit buffer empty flag - * @arg SPI_FLAG_CRCERR: CRC error flag - * @arg SPI_FLAG_MODF: Mode fault flag - * @arg SPI_FLAG_OVR: Overrun flag - * @arg SPI_FLAG_BSY: Busy flag - * @arg SPI_FLAG_FRE: Frame format error flag - * @arg SPI_FLAG_FTLVL: SPI fifo transmission level - * @arg SPI_FLAG_FRLVL: SPI fifo reception level - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) - -/** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg_modf = 0x00U; \ - tmpreg_modf = (__HANDLE__)->Instance->SR; \ - CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ - UNUSED(tmpreg_modf); \ - } while(0U) - -/** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg_ovr = 0x00U; \ - tmpreg_ovr = (__HANDLE__)->Instance->DR; \ - tmpreg_ovr = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_ovr); \ - } while(0U) - -/** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ - do{ \ - __IO uint32_t tmpreg_fre = 0x00U; \ - tmpreg_fre = (__HANDLE__)->Instance->SR; \ - UNUSED(tmpreg_fre); \ - }while(0U) - -/** @brief Enable the SPI peripheral. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) - -/** @brief Disable the SPI peripheral. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SPI_Private_Macros SPI Private Macros - * @{ - */ - -/** @brief Set the SPI transmit-only mode. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) - -/** @brief Set the SPI receive-only mode. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) - -/** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__ specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) - -/** @brief Check whether the specified SPI flag is set or not. - * @param __SR__ copy of SPI SR register. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg SPI_FLAG_RXNE: Receive buffer not empty flag - * @arg SPI_FLAG_TXE: Transmit buffer empty flag - * @arg SPI_FLAG_CRCERR: CRC error flag - * @arg SPI_FLAG_MODF: Mode fault flag - * @arg SPI_FLAG_OVR: Overrun flag - * @arg SPI_FLAG_BSY: Busy flag - * @arg SPI_FLAG_FRE: Frame format error flag - * @arg SPI_FLAG_FTLVL: SPI fifo transmission level - * @arg SPI_FLAG_FRLVL: SPI fifo reception level - * @retval SET or RESET. - */ -#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) - -/** @brief Check whether the specified SPI Interrupt is set or not. - * @param __CR2__ copy of SPI CR2 register. - * @param __INTERRUPT__ specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_IT_TXE: Tx buffer empty interrupt enable - * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable - * @arg SPI_IT_ERR: Error interrupt enable - * @retval SET or RESET. - */ -#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) - -/** @brief Checks if SPI Mode parameter is in allowed range. - * @param __MODE__ specifies the SPI Mode. - * This parameter can be a value of @ref SPI_Mode - * @retval None - */ -#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ - ((__MODE__) == SPI_MODE_MASTER)) - -/** @brief Checks if SPI Direction Mode parameter is in allowed range. - * @param __MODE__ specifies the SPI Direction Mode. - * This parameter can be a value of @ref SPI_Direction - * @retval None - */ -#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ - ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((__MODE__) == SPI_DIRECTION_1LINE)) - -/** @brief Checks if SPI Direction Mode parameter is 2 lines. - * @param __MODE__ specifies the SPI Direction Mode. - * @retval None - */ -#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) - -/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. - * @param __MODE__ specifies the SPI Direction Mode. - * @retval None - */ -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ - ((__MODE__) == SPI_DIRECTION_1LINE)) - -/** @brief Checks if SPI Data Size parameter is in allowed range. - * @param __DATASIZE__ specifies the SPI Data Size. - * This parameter can be a value of @ref SPI_Data_Size - * @retval None - */ -#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ - ((__DATASIZE__) == SPI_DATASIZE_4BIT)) - -/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. - * @param __CPOL__ specifies the SPI serial clock steady state. - * This parameter can be a value of @ref SPI_Clock_Polarity - * @retval None - */ -#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ - ((__CPOL__) == SPI_POLARITY_HIGH)) - -/** @brief Checks if SPI Clock Phase parameter is in allowed range. - * @param __CPHA__ specifies the SPI Clock Phase. - * This parameter can be a value of @ref SPI_Clock_Phase - * @retval None - */ -#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ - ((__CPHA__) == SPI_PHASE_2EDGE)) - -/** @brief Checks if SPI Slave Select parameter is in allowed range. - * @param __NSS__ specifies the SPI Slave Select management parameter. - * This parameter can be a value of @ref SPI_Slave_Select_management - * @retval None - */ -#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ - ((__NSS__) == SPI_NSS_HARD_INPUT) || \ - ((__NSS__) == SPI_NSS_HARD_OUTPUT)) - -/** @brief Checks if SPI NSS Pulse parameter is in allowed range. - * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. - * This parameter can be a value of @ref SPI_NSSP_Mode - * @retval None - */ -#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ - ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) - -/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. - * @param __PRESCALER__ specifies the SPI Baudrate prescaler. - * This parameter can be a value of @ref SPI_BaudRate_Prescaler - * @retval None - */ -#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ - ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) - -/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. - * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). - * This parameter can be a value of @ref SPI_MSB_LSB_transmission - * @retval None - */ -#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ - ((__BIT__) == SPI_FIRSTBIT_LSB)) - -/** @brief Checks if SPI TI mode parameter is in allowed range. - * @param __MODE__ specifies the SPI TI mode. - * This parameter can be a value of @ref SPI_TI_mode - * @retval None - */ -#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ - ((__MODE__) == SPI_TIMODE_ENABLE)) - -/** @brief Checks if SPI CRC calculation enabled state is in allowed range. - * @param __CALCULATION__ specifies the SPI CRC calculation enable state. - * This parameter can be a value of @ref SPI_CRC_Calculation - * @retval None - */ -#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ - ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) - -/** @brief Checks if SPI CRC length is in allowed range. - * @param __LENGTH__ specifies the SPI CRC length. - * This parameter can be a value of @ref SPI_CRC_length - * @retval None - */ -#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ - ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ - ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) - -/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. - * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. - * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 - * @retval None - */ -#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ - ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) - -/** @brief Checks if DMA handle is valid. - * @param __HANDLE__ specifies a DMA Handle. - * @retval None - */ -#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) - -/** - * @} - */ - -/* Include SPI HAL Extended module */ -#include "stm32f7xx_hal_spi_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPI_Exported_Functions - * @{ - */ - -/** @addtogroup SPI_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); -void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); -void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, - pSPI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup SPI_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size); -HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); - -void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); -/** - * @} - */ - -/** @addtogroup SPI_Exported_Functions_Group3 - * @{ - */ -/* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_SPI_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_spi.h + * @author MCD Application Team + * @brief Header file of SPI HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_SPI_H +#define STM32F7xx_HAL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ + +/** + * @brief SPI Configuration Structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_Mode */ + + uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. + This parameter can be a value of @ref SPI_Direction */ + + uint32_t DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_Data_Size */ + + uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. + This parameter can be a value of @ref SPI_TI_mode */ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_CRC_Calculation */ + + uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ + + uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. + CRC Length is only used with Data8 and Data16, not other data size + This parameter can be a value of @ref SPI_CRC_length */ + + uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . + This parameter can be a value of @ref SPI_NSSP_Mode + This mode is activated by the NSSP bit in the SPIx_CR2 register and + it takes effect only if the SPI interface is configured as Motorola SPI + master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, + CPOL setting is ignored).. */ +} SPI_InitTypeDef; + +/** + * @brief HAL SPI State structure definition + */ +typedef enum +{ + HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ + HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ + HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ + HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ + HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ + HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ +} HAL_SPI_StateTypeDef; + +/** + * @brief SPI handle Structure definition + */ +typedef struct __SPI_HandleTypeDef +{ + SPI_TypeDef *Instance; /*!< SPI registers base address */ + + SPI_InitTypeDef Init; /*!< SPI communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< SPI Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< SPI Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ + + uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ + + void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ + + void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ + + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ + + __IO uint32_t ErrorCode; /*!< SPI Error code */ + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ + void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ + void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ + void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ + void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ + void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ + void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ + void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ + void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ + void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} SPI_HandleTypeDef; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief HAL SPI Callback ID enumeration definition + */ +typedef enum +{ + HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ + HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ + HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ + HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ + HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ + HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ + HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ + HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ + HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ + HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ + +} HAL_SPI_CallbackIDTypeDef; + +/** + * @brief HAL SPI Callback pointer definition + */ +typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ + +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_Error_Code SPI Error Code + * @{ + */ +#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ +#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Mode SPI Mode + * @{ + */ +#define SPI_MODE_SLAVE (0x00000000U) +#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) +/** + * @} + */ + +/** @defgroup SPI_Direction SPI Direction Mode + * @{ + */ +#define SPI_DIRECTION_2LINES (0x00000000U) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE +/** + * @} + */ + +/** @defgroup SPI_Data_Size SPI Data Size + * @{ + */ +#define SPI_DATASIZE_4BIT (0x00000300U) +#define SPI_DATASIZE_5BIT (0x00000400U) +#define SPI_DATASIZE_6BIT (0x00000500U) +#define SPI_DATASIZE_7BIT (0x00000600U) +#define SPI_DATASIZE_8BIT (0x00000700U) +#define SPI_DATASIZE_9BIT (0x00000800U) +#define SPI_DATASIZE_10BIT (0x00000900U) +#define SPI_DATASIZE_11BIT (0x00000A00U) +#define SPI_DATASIZE_12BIT (0x00000B00U) +#define SPI_DATASIZE_13BIT (0x00000C00U) +#define SPI_DATASIZE_14BIT (0x00000D00U) +#define SPI_DATASIZE_15BIT (0x00000E00U) +#define SPI_DATASIZE_16BIT (0x00000F00U) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity + * @{ + */ +#define SPI_POLARITY_LOW (0x00000000U) +#define SPI_POLARITY_HIGH SPI_CR1_CPOL +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase SPI Clock Phase + * @{ + */ +#define SPI_PHASE_1EDGE (0x00000000U) +#define SPI_PHASE_2EDGE SPI_CR1_CPHA +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management SPI Slave Select Management + * @{ + */ +#define SPI_NSS_SOFT SPI_CR1_SSM +#define SPI_NSS_HARD_INPUT (0x00000000U) +#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) +/** + * @} + */ + +/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode + * @{ + */ +#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP +#define SPI_NSS_PULSE_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler + * @{ + */ +#define SPI_BAUDRATEPRESCALER_2 (0x00000000U) +#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission + * @{ + */ +#define SPI_FIRSTBIT_MSB (0x00000000U) +#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST +/** + * @} + */ + +/** @defgroup SPI_TI_mode SPI TI Mode + * @{ + */ +#define SPI_TIMODE_DISABLE (0x00000000U) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF +/** + * @} + */ + +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation + * @{ + */ +#define SPI_CRCCALCULATION_DISABLE (0x00000000U) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN +/** + * @} + */ + +/** @defgroup SPI_CRC_length SPI CRC Length + * @{ + * This parameter can be one of the following values: + * SPI_CRC_LENGTH_DATASIZE: aligned with the data size + * SPI_CRC_LENGTH_8BIT : CRC 8bit + * SPI_CRC_LENGTH_16BIT : CRC 16bit + */ +#define SPI_CRC_LENGTH_DATASIZE (0x00000000U) +#define SPI_CRC_LENGTH_8BIT (0x00000001U) +#define SPI_CRC_LENGTH_16BIT (0x00000002U) +/** + * @} + */ + +/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold + * @{ + * This parameter can be one of the following values: + * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : + * RXNE event is generated if the FIFO + * level is greater or equal to 1/4(8-bits). + * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO + * level is greater or equal to 1/2(16 bits). */ +#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH +#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) +/** + * @} + */ + +/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition + * @{ + */ +#define SPI_IT_TXE SPI_CR2_TXEIE +#define SPI_IT_RXNE SPI_CR2_RXNEIE +#define SPI_IT_ERR SPI_CR2_ERRIE +/** + * @} + */ + +/** @defgroup SPI_Flags_definition SPI Flags Definition + * @{ + */ +#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ +#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ +#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ +#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ +#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ +#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ +#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ +#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ +#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ +#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\ + | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) +/** + * @} + */ + +/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level + * @{ + */ +#define SPI_FTLVL_EMPTY (0x00000000U) +#define SPI_FTLVL_QUARTER_FULL (0x00000800U) +#define SPI_FTLVL_HALF_FULL (0x00001000U) +#define SPI_FTLVL_FULL (0x00001800U) + +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level + * @{ + */ +#define SPI_FRLVL_EMPTY (0x00000000U) +#define SPI_FRLVL_QUARTER_FULL (0x00000200U) +#define SPI_FRLVL_HALF_FULL (0x00000400U) +#define SPI_FRLVL_FULL (0x00000600U) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @brief Reset SPI handle state. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. + * @param __HANDLE__ specifies the SPI handle. + * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Check whether the specified SPI interrupt source is enabled or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the SPI CRCERR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) + +/** @brief Clear the SPI MODF pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_modf = 0x00U; \ + tmpreg_modf = (__HANDLE__)->Instance->SR; \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ + UNUSED(tmpreg_modf); \ + } while(0U) + +/** @brief Clear the SPI OVR pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_ovr = 0x00U; \ + tmpreg_ovr = (__HANDLE__)->Instance->DR; \ + tmpreg_ovr = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_ovr); \ + } while(0U) + +/** @brief Clear the SPI FRE pending flag. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg_fre = 0x00U; \ + tmpreg_fre = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg_fre); \ + } while(0U) + +/** @brief Enable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disable the SPI peripheral. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Set the SPI transmit-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Set the SPI receive-only mode. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) + +/** @brief Reset the CRC calculation of the SPI. + * @param __HANDLE__ specifies the SPI Handle. + * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) + +/** @brief Check whether the specified SPI flag is set or not. + * @param __SR__ copy of SPI SR register. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag + * @arg SPI_FLAG_TXE: Transmit buffer empty flag + * @arg SPI_FLAG_CRCERR: CRC error flag + * @arg SPI_FLAG_MODF: Mode fault flag + * @arg SPI_FLAG_OVR: Overrun flag + * @arg SPI_FLAG_BSY: Busy flag + * @arg SPI_FLAG_FRE: Frame format error flag + * @arg SPI_FLAG_FTLVL: SPI fifo transmission level + * @arg SPI_FLAG_FRLVL: SPI fifo reception level + * @retval SET or RESET. + */ +#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + +/** @brief Check whether the specified SPI Interrupt is set or not. + * @param __CR2__ copy of SPI CR2 register. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval SET or RESET. + */ +#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ + (__INTERRUPT__)) ? SET : RESET) + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Mode. + * This parameter can be a value of @ref SPI_Mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ + ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__ specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction + * @retval None + */ +#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__ specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__ specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_Data_Size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_4BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__ specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity + * @retval None + */ +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) + +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__ specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave Select parameter is in allowed range. + * @param __NSS__ specifies the SPI Slave Select management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI NSS Pulse parameter is in allowed range. + * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. + * This parameter can be a value of @ref SPI_NSSP_Mode + * @retval None + */ +#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ + ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__ specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) + +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__ specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) + +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__ specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) + +/** @brief Checks if SPI CRC length is in allowed range. + * @param __LENGTH__ specifies the SPI CRC length. + * This parameter can be a value of @ref SPI_CRC_length + * @retval None + */ +#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ + ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) + +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ + ((__POLYNOMIAL__) <= 0xFFFFU) && \ + (((__POLYNOMIAL__)&0x1U) != 0U)) + +/** @brief Checks if DMA handle is valid. + * @param __HANDLE__ specifies a DMA Handle. + * @retval None + */ +#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) + +/** + * @} + */ + +/* Include SPI HAL Extended module */ +#include "stm32f7xx_hal_spi_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); +void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); + +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); +void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ +/* Peripheral State and Error functions ***************************************/ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_SPI_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h index 5b0a424c..b90bf770 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi_ex.h @@ -1,73 +1,73 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_spi_ex.h - * @author MCD Application Team - * @brief Header file of SPI HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SPI_EX_H -#define STM32F7xx_HAL_SPI_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SPIEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPIEx_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -/* IO operation functions *****************************************************/ -/** @addtogroup SPIEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_SPI_EX_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_spi_ex.h + * @author MCD Application Team + * @brief Header file of SPI HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_SPI_EX_H +#define STM32F7xx_HAL_SPI_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SPIEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPIEx_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +/* IO operation functions *****************************************************/ +/** @addtogroup SPIEx_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_SPI_EX_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h deleted file mode 100644 index 6a648beb..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h +++ /dev/null @@ -1,230 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sram.h - * @author MCD Application Team - * @brief Header file of SRAM HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_SRAM_H -#define STM32F7xx_HAL_SRAM_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_fmc.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -/** @addtogroup SRAM - * @{ - */ - -/* Exported typedef ----------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_Types SRAM Exported Types - * @{ - */ -/** - * @brief HAL SRAM State structures definition - */ -typedef enum -{ - HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ - HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ - HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ - HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ - HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ - -} HAL_SRAM_StateTypeDef; - -/** - * @brief SRAM handle Structure definition - */ -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) -typedef struct __SRAM_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ -{ - FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - - FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ - - FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ - - HAL_LockTypeDef Lock; /*!< SRAM locking object */ - - __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ - - DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ - -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ - void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ - void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ -} SRAM_HandleTypeDef; - -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) -/** - * @brief HAL SRAM Callback ID enumeration definition - */ -typedef enum -{ - HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */ - HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ - HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ - HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ -} HAL_SRAM_CallbackIDTypeDef; - -/** - * @brief HAL SRAM Callback pointer definition - */ -typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); -typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_Macros SRAM Exported Macros - * @{ - */ - -/** @brief Reset SRAM handle state - * @param __HANDLE__ SRAM handle - * @retval None - */ -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) -#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions - * @{ - */ - -/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, - FMC_NORSRAM_TimingTypeDef *ExtTiming); -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); - -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions - * @{ - */ - -/* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, - uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, - uint32_t BufferSize); - -void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); - -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) -/* SRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, - pSRAM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, - pSRAM_DmaCallbackTypeDef pCallback); -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group3 Control functions - * @{ - */ - -/* SRAM Control functions ****************************************************/ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); - -/** - * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @{ - */ - -/* SRAM State functions ******************************************************/ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_SRAM_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h index a088bc1f..4899e439 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim.h @@ -1,2419 +1,2422 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_TIM_H -#define STM32F7xx_HAL_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ - -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and - Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and - Max_Data = 0xFFFF. */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClockConfigTypeDef; - -/** - * @brief TIM Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, - ETR prescaler must be off */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Master configuration Structure definition - * @note Advanced timers provide TRGO2 internal line which is redirected - * to the ADC - */ -typedef struct -{ - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode - @note When the Master/slave mode is enabled, the effect of - an event on the trigger input (TRGI) is delayed to allow a - perfect synchronization between the current timer and its - slaves (through TRGO). It is not mandatory in case of timer - synchronization mode. */ -} TIM_MasterConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct -{ - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -} TIM_SlaveConfigTypeDef; - -/** - * @brief TIM Break input(s) and Dead time configuration Structure definition - * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable - * filter and polarity. - */ -typedef struct -{ - uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ - - uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - - uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ - - uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - - uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ - - uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ - -} TIM_BreakDeadTimeConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -} HAL_TIM_StateTypeDef; - -/** - * @brief TIM Channel States definition - */ -typedef enum -{ - HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ - HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ - HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ -} HAL_TIM_ChannelStateTypeDef; - -/** - * @brief DMA Burst States definition - */ -typedef enum -{ - HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ - HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ - HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ -} HAL_TIM_DMABurstStateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ - HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ -} HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -typedef struct __TIM_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ - __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ - void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ - void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ - void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ - void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ - void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ - void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ - void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ - void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ - void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ - void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ - void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ - void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ - void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ - void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ - void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ - void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ - void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ - void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ - void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ - void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ - void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ - void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ - void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ - void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ - void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ - void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ - void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} TIM_HandleTypeDef; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief HAL TIM Callback ID enumeration definition - */ -typedef enum -{ - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ - , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ -} HAL_TIM_CallbackIDTypeDef; - -/** - * @brief HAL TIM Callback pointer definition - */ -typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ - -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_ClearInput_Source TIM Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ -#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 0x00000000U -#define TIM_DMABASE_CR2 0x00000001U -#define TIM_DMABASE_SMCR 0x00000002U -#define TIM_DMABASE_DIER 0x00000003U -#define TIM_DMABASE_SR 0x00000004U -#define TIM_DMABASE_EGR 0x00000005U -#define TIM_DMABASE_CCMR1 0x00000006U -#define TIM_DMABASE_CCMR2 0x00000007U -#define TIM_DMABASE_CCER 0x00000008U -#define TIM_DMABASE_CNT 0x00000009U -#define TIM_DMABASE_PSC 0x0000000AU -#define TIM_DMABASE_ARR 0x0000000BU -#define TIM_DMABASE_RCR 0x0000000CU -#define TIM_DMABASE_CCR1 0x0000000DU -#define TIM_DMABASE_CCR2 0x0000000EU -#define TIM_DMABASE_CCR3 0x0000000FU -#define TIM_DMABASE_CCR4 0x00000010U -#define TIM_DMABASE_BDTR 0x00000011U -#define TIM_DMABASE_DCR 0x00000012U -#define TIM_DMABASE_DMAR 0x00000013U -#define TIM_DMABASE_OR 0x00000014U -#define TIM_DMABASE_CCMR3 0x00000015U -#define TIM_DMABASE_CCR5 0x00000016U -#define TIM_DMABASE_CCR6 0x00000017U -#if defined(TIM_BREAK_INPUT_SUPPORT) -#define TIM_DMABASE_AF1 0x00000018U -#define TIM_DMABASE_AF2 0x00000019U -#endif /* TIM_BREAK_INPUT_SUPPORT */ -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ -#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ -#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ -#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ -/** - * @} - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ -/** - * @} - */ - -/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap - * @{ - */ -#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ -#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ -#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ -#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM Output Compare State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ -#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ - -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ -#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State - * @{ - */ -#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ -#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ -#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity - * @{ - */ -#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ -#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State - * @{ - */ -#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ -#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State - * @{ - */ -#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ -#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity - * @{ - */ -#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ -#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ -#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ -#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ -#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ -#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ -#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ -#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ -#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ -#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ -#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ -/** - * @} - */ - -/** @defgroup TIM_Commutation_Source TIM Commutation Source - * @{ - */ -#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ -#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ -#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ -#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ -#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ -#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ -#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ -#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ -/** - * @} - */ - -/** @defgroup TIM_CC_DMA_Request CCx DMA request selection - * @{ - */ -#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ -#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ -#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ -#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ -#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ -#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ -#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ -#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ -#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ -#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ -#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ -#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ -#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ -#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ -#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ -#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ -#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ -#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ -#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ -#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ -#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ -#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ -#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ -#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ -#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ -#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state - * @{ - */ -#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ -#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state - * @{ - */ -#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ -#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ -/** - * @} - */ -/** @defgroup TIM_Lock_level TIM Lock level - * @{ - */ -#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ -#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ -#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ -#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable - * @{ - */ -#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ -#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity TIM Break Input Polarity - * @{ - */ -#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ -#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ -/** - * @} - */ - -/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable - * @{ - */ -#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ -#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity - * @{ - */ -#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ -#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable - * @{ - */ -#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ -/** - * @} - */ - -/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 - * @{ - */ -#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ -#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ -#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ -#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) - * @{ - */ -#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ -#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ -#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ -#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ -#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ -#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ -#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ -#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ -#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes - * @{ - */ -#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ -#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ -#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ -#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ -#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ -#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ -#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ -#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ -#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ -#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ -#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ -#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ -#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ -#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ -#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ -#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ -#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -/** - * @} - */ - -/** @defgroup DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ -#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ -#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ -#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Break_System TIM Break System - * @{ - */ -#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ -#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ -#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state. - * @param __HANDLE__ TIM handle. - * @retval None - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - } while(0) -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Enable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been - * disabled - */ -#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled unconditionally - */ -#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) - -/** @brief Enable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** @brief Disable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** @brief Enable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** @brief Disable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag - * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag - * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ - == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read - * in an atomic way. - * @param __HANDLE__ TIM handle. - * @retval None -mode. - */ -#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) - -/** - * @brief Disable update interrupt flag (UIF) remapping. - * @param __HANDLE__ TIM handle. - * @retval None -mode. - */ -#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) - -/** - * @brief Get update interrupt flag (UIF) copy status. - * @param __COUNTER__ Counter value. - * @retval The state of UIFCPY (TRUE or FALSE). -mode. - */ -#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode - * or Encoder mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** - * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the Prescaler new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Set the TIM Counter Register value on runtime. - * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in - * case of 32 bits counter TIM instance. - * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) - -/** - * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) - -/** - * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() - * function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) - -/** - * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) - -/** - * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @arg TIM_CHANNEL_5: get capture/compare 5 register value - * @arg TIM_CHANNEL_6: get capture/compare 6 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ - ((__HANDLE__)->Instance->CCR6)) - -/** - * @brief Set the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) - -/** - * @brief Reset the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) - -/** - * @brief Enable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @note When fast mode is enabled an active edge on the trigger input acts - * like a compare match on CCx output. Delay to sample the trigger - * input and to activate CCx output is reduced to 3 clock cycles. - * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) - -/** - * @brief Disable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @note When fast mode is disabled CCx output behaves normally depending - * on counter and CCRx values even when the trigger is ON. The minimum - * delay to activate CCx output when an active edge occurs on the - * trigger input is 5 clock cycles. - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ - ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * _ Counter overflow underflow - * _ Setting the UG bit - * _ Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) - -/** - * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** @brief Select the Capture/compare DMA request source. - * @param __HANDLE__ specifies the TIM Handle. - * @param __CCDMA__ specifies Capture/compare DMA request source - * This parameter can be one of the following values: - * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event - * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event - * @retval None - */ -#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ - MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) - -/** - * @} - */ -/* End of exported macros ----------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) -/** - * @} - */ -/* End of private constants --------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) - -#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE) -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR) || \ - ((__BASE__) == TIM_DMABASE_OR) || \ - ((__BASE__) == TIM_DMABASE_CCMR3) || \ - ((__BASE__) == TIM_DMABASE_CCR5) || \ - ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_AF1) || \ - ((__BASE__) == TIM_DMABASE_AF2)) -#else -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR) || \ - ((__BASE__) == TIM_DMABASE_OR) || \ - ((__BASE__) == TIM_DMABASE_CCMR3) || \ - ((__BASE__) == TIM_DMABASE_CCR5) || \ - ((__BASE__) == TIM_DMABASE_CCR6)) -#endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */ - -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ - ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ - ((__MODE__) == TIM_UIFREMAP_ENABLE)) - -#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ - ((__STATE__) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) - -#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCIDLESTATE_RESET)) - -#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCNIDLESTATE_RESET)) - -#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) - -#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV8)) - -#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ - ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ - ((__CHANNEL__) != (TIM_CHANNEL_6))) - -#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ - ((__MODE__) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ - ((__MODE__) == TIM_ENCODERMODE_TI2) || \ - ((__MODE__) == TIM_ENCODERMODE_TI12)) - -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4) || \ - ((__CHANNEL__) == TIM_CHANNEL_5) || \ - ((__CHANNEL__) == TIM_CHANNEL_6) || \ - ((__CHANNEL__) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2)) - -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3)) - -#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) - -#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ - ((__STATE__) == TIM_OSSR_DISABLE)) - -#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ - ((__STATE__) == TIM_OSSI_DISABLE)) - -#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_3)) - -#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - -#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ - ((__STATE__) == TIM_BREAK_DISABLE)) - -#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) - -#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ - ((__STATE__) == TIM_BREAK2_DISABLE)) - -#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) - -#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) - -#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ - ((__SOURCE__) == TIM_TRGO_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO_OC1) || \ - ((__SOURCE__) == TIM_TRGO_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO_OC4REF)) - -#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ - ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO2_OC1) || \ - ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) - -#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ - ((__MODE__) == TIM_SLAVEMODE_RESET) || \ - ((__MODE__) == TIM_SLAVEMODE_GATED) || \ - ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ - ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) - -#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2) || \ - ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ - ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) - -#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ - ((__MODE__) == TIM_OCMODE_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_TOGGLE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ - ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) - -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ETRF)) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_NONE)) - -#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ - ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) - -#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) - -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) - -#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) - -#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) - -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) - -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) - -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) - -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) - -#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ - (__HANDLE__)->ChannelState[5]) - -#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) - -#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ - (__HANDLE__)->ChannelNState[3]) - -#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/* Include TIM HAL Extended module */ -#include "stm32f7xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * @{ - */ -/* Timer Output Compare functions *********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * @{ - */ -/* Timer PWM functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * @{ - */ -/* Timer Input Capture functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * @{ - */ -/* Timer One Pulse functions **************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * @{ - */ -/* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * @{ - */ -/* Interrupt Handler functions ***********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - const TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); - -/* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -void TIM_ResetCallback(TIM_HandleTypeDef *htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_TIM_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim.h + * @author MCD Application Team + * @brief Header file of TIM HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_TIM_H +#define STM32F7xx_HAL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** + * @brief TIM Time base Configuration Structure definition + */ +typedef struct +{ + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_ClockDivision */ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ + + uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. + This parameter can be a value of @ref TIM_AutoReloadPreload */ +} TIM_Base_InitTypeDef; + +/** + * @brief TIM Output Compare Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCFastMode; /*!< Specifies the Fast mode state. + This parameter can be a value of @ref TIM_Output_Fast_State + @note This parameter is valid only in PWM1 and PWM2 mode. */ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ +} TIM_OC_InitTypeDef; + +/** + * @brief TIM One Pulse Mode Configuration Structure definition + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for timer instances supporting break feature. */ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_OnePulse_InitTypeDef; + +/** + * @brief TIM Input Capture Configuration Structure definition + */ +typedef struct +{ + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_IC_InitTypeDef; + +/** + * @brief TIM Encoder Configuration Structure definition + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Mode */ + + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC1Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ + + uint32_t IC2Selection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC2Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_Encoder_InitTypeDef; + +/** + * @brief Clock Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClockSource; /*!< TIM clock sources + This parameter can be a value of @ref TIM_Clock_Source */ + uint32_t ClockPolarity; /*!< TIM clock polarity + This parameter can be a value of @ref TIM_Clock_Polarity */ + uint32_t ClockPrescaler; /*!< TIM clock prescaler + This parameter can be a value of @ref TIM_Clock_Prescaler */ + uint32_t ClockFilter; /*!< TIM clock filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClockConfigTypeDef; + +/** + * @brief TIM Clear Input Configuration Handle Structure definition + */ +typedef struct +{ + uint32_t ClearInputState; /*!< TIM clear Input state + This parameter can be ENABLE or DISABLE */ + uint32_t ClearInputSource; /*!< TIM clear Input sources + This parameter can be a value of @ref TIM_ClearInput_Source */ + uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity + This parameter can be a value of @ref TIM_ClearInput_Polarity */ + uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ + uint32_t ClearInputFilter; /*!< TIM Clear Input filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ +} TIM_ClearInputConfigTypeDef; + +/** + * @brief TIM Master configuration Structure definition + * @note Advanced timers provide TRGO2 internal line which is redirected + * to the ADC + */ +typedef struct +{ + uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection */ + uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection + This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ + uint32_t MasterSlaveMode; /*!< Master/slave mode selection + This parameter can be a value of @ref TIM_Master_Slave_Mode + @note When the Master/slave mode is enabled, the effect of + an event on the trigger input (TRGI) is delayed to allow a + perfect synchronization between the current timer and its + slaves (through TRGO). It is not mandatory in case of timer + synchronization mode. */ +} TIM_MasterConfigTypeDef; + +/** + * @brief TIM Slave configuration Structure definition + */ +typedef struct +{ + uint32_t SlaveMode; /*!< Slave mode selection + This parameter can be a value of @ref TIM_Slave_Mode */ + uint32_t InputTrigger; /*!< Input Trigger source + This parameter can be a value of @ref TIM_Trigger_Selection */ + uint32_t TriggerPolarity; /*!< Input Trigger polarity + This parameter can be a value of @ref TIM_Trigger_Polarity */ + uint32_t TriggerPrescaler; /*!< Input trigger prescaler + This parameter can be a value of @ref TIM_Trigger_Prescaler */ + uint32_t TriggerFilter; /*!< Input trigger filter + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + +} TIM_SlaveConfigTypeDef; + +/** + * @brief TIM Break input(s) and Dead time configuration Structure definition + * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable + * filter and polarity. + */ +typedef struct +{ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ + + uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ + + uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + +} TIM_BreakDeadTimeConfigTypeDef; + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ + HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ + HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +} HAL_TIM_StateTypeDef; + +/** + * @brief TIM Channel States definition + */ +typedef enum +{ + HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ + HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ + HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ +} HAL_TIM_ChannelStateTypeDef; + +/** + * @brief DMA Burst States definition + */ +typedef enum +{ + HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ + HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ + HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ +} HAL_TIM_DMABurstStateTypeDef; + +/** + * @brief HAL Active channel structures definition + */ +typedef enum +{ + HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ + HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ + HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ + HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ + HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ + HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ + HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ +} HAL_TIM_ActiveChannel; + +/** + * @brief TIM Time Base Handle Structure definition + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +typedef struct __TIM_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +{ + TIM_TypeDef *Instance; /*!< Register base address */ + TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ + HAL_TIM_ActiveChannel Channel; /*!< Active channel */ + DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array + This array is accessed by a @ref DMA_Handle_index */ + HAL_LockTypeDef Lock; /*!< Locking object */ + __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ + __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ + __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ + void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ + void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ + void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ + void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ + void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ + void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ + void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ + void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ + void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ + void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ + void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ + void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ + void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ + void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ + void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ + void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ + void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ + void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ + void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ + void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ + void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ + void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ + void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ + void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ + void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ + void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ + void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} TIM_HandleTypeDef; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief HAL TIM Callback ID enumeration definition + */ +typedef enum +{ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ + , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ + , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ + , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ + , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ + , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ + , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ + , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ + , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ + , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ + , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ + , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ +} HAL_TIM_CallbackIDTypeDef; + +/** + * @brief HAL TIM Callback pointer definition + */ +typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ + +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_ClearInput_Source TIM Clear Input Source + * @{ + */ +#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */ +#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address TIM DMA Base Address + * @{ + */ +#define TIM_DMABASE_CR1 0x00000000U +#define TIM_DMABASE_CR2 0x00000001U +#define TIM_DMABASE_SMCR 0x00000002U +#define TIM_DMABASE_DIER 0x00000003U +#define TIM_DMABASE_SR 0x00000004U +#define TIM_DMABASE_EGR 0x00000005U +#define TIM_DMABASE_CCMR1 0x00000006U +#define TIM_DMABASE_CCMR2 0x00000007U +#define TIM_DMABASE_CCER 0x00000008U +#define TIM_DMABASE_CNT 0x00000009U +#define TIM_DMABASE_PSC 0x0000000AU +#define TIM_DMABASE_ARR 0x0000000BU +#define TIM_DMABASE_RCR 0x0000000CU +#define TIM_DMABASE_CCR1 0x0000000DU +#define TIM_DMABASE_CCR2 0x0000000EU +#define TIM_DMABASE_CCR3 0x0000000FU +#define TIM_DMABASE_CCR4 0x00000010U +#define TIM_DMABASE_BDTR 0x00000011U +#define TIM_DMABASE_DCR 0x00000012U +#define TIM_DMABASE_DMAR 0x00000013U +#define TIM_DMABASE_OR 0x00000014U +#define TIM_DMABASE_CCMR3 0x00000015U +#define TIM_DMABASE_CCR5 0x00000016U +#define TIM_DMABASE_CCR6 0x00000017U +#if defined(TIM_BREAK_INPUT_SUPPORT) +#define TIM_DMABASE_AF1 0x00000018U +#define TIM_DMABASE_AF2 0x00000019U +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ + +/** @defgroup TIM_Event_Source TIM Event Source + * @{ + */ +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ +#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ +/** + * @} + */ + +/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity + * @{ + */ +#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Polarity TIM ETR Polarity + * @{ + */ +#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ +/** + * @} + */ + +/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler + * @{ + */ +#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ +#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode TIM Counter Mode + * @{ + */ +#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ +#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +/** + * @} + */ + +/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap + * @{ + */ +#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ +#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ +/** + * @} + */ + +/** @defgroup TIM_ClockDivision TIM Clock Division + * @{ + */ +#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_State TIM Output Compare State + * @{ + */ +#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ +#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ +/** + * @} + */ + +/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload + * @{ + */ +#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ +#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ + +/** + * @} + */ + +/** @defgroup TIM_Output_Fast_State TIM Output Fast State + * @{ + */ +#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ +#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State + * @{ + */ +#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ +#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity + * @{ + */ +#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ +#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity + * @{ + */ +#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State + * @{ + */ +#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State + * @{ + */ +#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity + * @{ + */ +#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ +#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ +#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity + * @{ + */ +#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ +#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection + * @{ + */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler + * @{ + */ +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode + * @{ + */ +#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode TIM Encoder Mode + * @{ + */ +#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ +#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ +/** + * @} + */ + +/** @defgroup TIM_Interrupt_definition TIM interrupt Definition + * @{ + */ +#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ +/** + * @} + */ + +/** @defgroup TIM_Commutation_Source TIM Commutation Source + * @{ + */ +#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ +#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ +/** + * @} + */ + +/** @defgroup TIM_DMA_sources TIM DMA Sources + * @{ + */ +#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +/** + * @} + */ + +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_Flag_definition TIM Flag Definition + * @{ + */ +#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ +#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +/** + * @} + */ + +/** @defgroup TIM_Channel TIM Channel + * @{ + */ +#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ +#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ +#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ +#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ +#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ +#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ +#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Source TIM Clock Source + * @{ + */ +#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ +#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ +#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ +#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ +#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Polarity TIM Clock Polarity + * @{ + */ +#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ +#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ +#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ +/** + * @} + */ + +/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler + * @{ + */ +#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ +#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ +#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity + * @{ + */ +#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ +#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ +/** + * @} + */ + +/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler + * @{ + */ +#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ +#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state + * @{ + */ +#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state + * @{ + */ +#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +/** + * @} + */ +/** @defgroup TIM_Lock_level TIM Lock level + * @{ + */ +#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable + * @{ + */ +#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity TIM Break Input Polarity + * @{ + */ +#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable + * @{ + */ +#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ +#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity + * @{ + */ +#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ +#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable + * @{ + */ +#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection + * @{ + */ +#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ +#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode + * @{ + */ +#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ +#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode TIM Slave mode + * @{ + */ +#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ +#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes + * @{ + */ +#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ +#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ +#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ +#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Selection TIM Trigger Selection + * @{ + */ +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ +#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity + * @{ + */ +#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ +#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ +/** + * @} + */ + +/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler + * @{ + */ +#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ +#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ +#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ +#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ +/** + * @} + */ + +/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection + * @{ + */ +#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ +#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ +/** + * @} + */ + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ +#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ +/** + * @} + */ + +/** @defgroup DMA_Handle_index TIM DMA Handle Index + * @{ + */ +#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ +#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ +#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ +#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ +#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ +#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ +#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ +/** + * @} + */ + +/** @defgroup Channel_CC_State TIM Capture/Compare Channel State + * @{ + */ +#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ +#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ +#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ +#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ +/** + * @} + */ + +/** @defgroup TIM_Break_System TIM Break System + * @{ + */ +#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */ +#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */ +#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */ +/** + * @} + */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup TIM_Exported_Macros TIM Exported Macros + * @{ + */ + +/** @brief Reset TIM handle state. + * @param __HANDLE__ TIM handle. + * @retval None + */ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + (__HANDLE__)->Base_MspInitCallback = NULL; \ + (__HANDLE__)->Base_MspDeInitCallback = NULL; \ + (__HANDLE__)->IC_MspInitCallback = NULL; \ + (__HANDLE__)->IC_MspDeInitCallback = NULL; \ + (__HANDLE__)->OC_MspInitCallback = NULL; \ + (__HANDLE__)->OC_MspDeInitCallback = NULL; \ + (__HANDLE__)->PWM_MspInitCallback = NULL; \ + (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ + (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspInitCallback = NULL; \ + (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ + (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ + (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ + (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ + } while(0) +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @brief Enable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) + +/** + * @brief Enable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) + +/** + * @brief Disable the TIM peripheral. + * @param __HANDLE__ TIM handle + * @retval None + */ +#define __HAL_TIM_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled + */ +#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ + do { \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ + { \ + if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ + { \ + (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ + } \ + } \ + } while(0) + +/** + * @brief Disable the TIM main Output. + * @param __HANDLE__ TIM handle + * @retval None + * @note The Main Output Enable of a timer instance is disabled unconditionally + */ +#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) + +/** @brief Enable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to enable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) + +/** @brief Disable the specified TIM interrupt. + * @param __HANDLE__ specifies the TIM Handle. + * @param __INTERRUPT__ specifies the TIM interrupt source to disable. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) + +/** @brief Enable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to enable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) + +/** @brief Disable the specified DMA request. + * @param __HANDLE__ specifies the TIM Handle. + * @param __DMA__ specifies the TIM DMA request to disable. + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: Update DMA request + * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request + * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request + * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request + * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request + * @arg TIM_DMA_COM: Commutation DMA request + * @arg TIM_DMA_TRIGGER: Trigger DMA request + * @retval None + */ +#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) + +/** @brief Check whether the specified TIM interrupt flag is set or not. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified TIM interrupt flag. + * @param __HANDLE__ specifies the TIM Handle. + * @param __FLAG__ specifies the TIM interrupt flag to clear. + * This parameter can be one of the following values: + * @arg TIM_FLAG_UPDATE: Update interrupt flag + * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag + * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag + * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag + * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag + * @arg TIM_FLAG_CC5: Compare 5 interrupt flag + * @arg TIM_FLAG_CC6: Compare 6 interrupt flag + * @arg TIM_FLAG_COM: Commutation interrupt flag + * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag + * @arg TIM_FLAG_BREAK: Break interrupt flag + * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag + * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag + * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag + * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag + * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag + * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) + +/** + * @brief Check whether the specified TIM interrupt source is enabled or not. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval The state of TIM_IT (SET or RESET). + */ +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ + == (__INTERRUPT__)) ? SET : RESET) + +/** @brief Clear the TIM interrupt pending bits. + * @param __HANDLE__ TIM handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg TIM_IT_UPDATE: Update interrupt + * @arg TIM_IT_CC1: Capture/Compare 1 interrupt + * @arg TIM_IT_CC2: Capture/Compare 2 interrupt + * @arg TIM_IT_CC3: Capture/Compare 3 interrupt + * @arg TIM_IT_CC4: Capture/Compare 4 interrupt + * @arg TIM_IT_COM: Commutation interrupt + * @arg TIM_IT_TRIGGER: Trigger interrupt + * @arg TIM_IT_BREAK: Break interrupt + * @retval None + */ +#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @param __HANDLE__ TIM handle. + * @retval None +mode. + */ +#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) + +/** + * @brief Get update interrupt flag (UIF) copy status. + * @param __COUNTER__ Counter value. + * @retval The state of UIFCPY (TRUE or FALSE). +mode. + */ +#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) + +/** + * @brief Indicates whether or not the TIM Counter is used as downcounter. + * @param __HANDLE__ TIM handle. + * @retval False (Counter used as upcounter) or True (Counter used as downcounter) + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. + */ +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) + +/** + * @brief Set the TIM Prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __PRESC__ specifies the Prescaler new value. + * @retval None + */ +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) + +/** + * @brief Set the TIM Counter Register value on runtime. + * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in + * case of 32 bits counter TIM instance. + * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. + * @param __HANDLE__ TIM handle. + * @param __COUNTER__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) + +/** + * @brief Get the TIM Counter Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) + */ +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) + +/** + * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __AUTORELOAD__ specifies the Counter register new value. + * @retval None + */ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ + do{ \ + (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ + (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ + } while(0) + +/** + * @brief Get the TIM Autoreload Register value on runtime. + * @param __HANDLE__ TIM handle. + * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) + */ +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) + +/** + * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. + * @param __HANDLE__ TIM handle. + * @param __CKD__ specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + * @retval None + */ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ + do{ \ + (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ + (__HANDLE__)->Instance->CR1 |= (__CKD__); \ + (__HANDLE__)->Init.ClockDivision = (__CKD__); \ + } while(0) + +/** + * @brief Get the TIM Clock Division value on runtime. + * @param __HANDLE__ TIM handle. + * @retval The clock division can be one of the following values: + * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT + * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT + * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT + */ +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) + +/** + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __ICPSC__ specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ + do{ \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + } while(0) + +/** + * @brief Get the TIM Input Capture prescaler on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get input capture 1 prescaler value + * @arg TIM_CHANNEL_2: get input capture 2 prescaler value + * @arg TIM_CHANNEL_3: get input capture 3 prescaler value + * @arg TIM_CHANNEL_4: get input capture 4 prescaler value + * @retval The input capture prescaler can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + */ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ + (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) + +/** + * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param __COMPARE__ specifies the Capture Compare register new value. + * @retval None + */ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ + ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) + +/** + * @brief Get the TIM Capture Compare Register value on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channel associated with the capture compare register + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: get capture/compare 1 register value + * @arg TIM_CHANNEL_2: get capture/compare 2 register value + * @arg TIM_CHANNEL_3: get capture/compare 3 register value + * @arg TIM_CHANNEL_4: get capture/compare 4 register value + * @arg TIM_CHANNEL_5: get capture/compare 5 register value + * @arg TIM_CHANNEL_6: get capture/compare 6 register value + * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) + */ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ + ((__HANDLE__)->Instance->CCR6)) + +/** + * @brief Set the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) + +/** + * @brief Reset the TIM Output compare preload. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) + +/** + * @brief Enable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is enabled an active edge on the trigger input acts + * like a compare match on CCx output. Delay to sample the trigger + * input and to activate CCx output is reduced to 3 clock cycles. + * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. + * @retval None + */ +#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) + +/** + * @brief Disable fast mode for a given channel. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @note When fast mode is disabled CCx output behaves normally depending + * on counter and CCRx values even when the trigger is ON. The minimum + * delay to activate CCx output when an active edge occurs on the + * trigger input is 5 clock cycles. + * @retval None + */ +#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ + ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) + +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. + * @param __HANDLE__ TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * _ Counter overflow underflow + * _ Setting the UG bit + * _ Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) + +/** + * @brief Set the TIM Capture x input polarity on runtime. + * @param __HANDLE__ TIM handle. + * @param __CHANNEL__ TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__ Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + +/** + * @} + */ +/* End of exported macros ----------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_Private_Constants TIM Private Constants + * @{ + */ +/* The counter of a timer instance is disabled only if all the CCx and CCxN + channels have been disabled */ +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) +#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) +/** + * @} + */ +/* End of private constants --------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_Private_Macros TIM Private Macros + * @{ + */ +#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR)) + +#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE) +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6) || \ + ((__BASE__) == TIM_DMABASE_AF1) || \ + ((__BASE__) == TIM_DMABASE_AF2)) +#else +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_RCR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_BDTR) || \ + ((__BASE__) == TIM_DMABASE_OR) || \ + ((__BASE__) == TIM_DMABASE_CCMR3) || \ + ((__BASE__) == TIM_DMABASE_CCR5) || \ + ((__BASE__) == TIM_DMABASE_CCR6)) +#endif /* TIM_AF1_BKINE && TIM_AF1_BKINE */ + +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + +#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ + ((__MODE__) == TIM_UIFREMAP_ENABLE)) + +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) + +#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ + ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) + +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) + +#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) + +#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCIDLESTATE_RESET)) + +#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ + ((__STATE__) == TIM_OCNIDLESTATE_RESET)) + +#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) + +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) + +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) + +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_5) || \ + ((__CHANNEL__) == TIM_CHANNEL_6) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) + +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) + +#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3)) + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) + +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + +#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ + ((__STATE__) == TIM_OSSR_DISABLE)) + +#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ + ((__STATE__) == TIM_OSSI_DISABLE)) + +#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ + ((__LEVEL__) == TIM_LOCKLEVEL_3)) + +#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) + +#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ + ((__STATE__) == TIM_BREAK_DISABLE)) + +#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) + +#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ + ((__STATE__) == TIM_BREAK2_DISABLE)) + +#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) + +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ + ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) + +#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + +#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ + ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO2_OC1) || \ + ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ + ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) + +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ + ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ + ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ + ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2)) + +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) + +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) + +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) + +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS)) + +#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) + +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) + +#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) + +#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ + ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) + +#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) + +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ + ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) + +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ + ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) + +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) + +#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ + (__HANDLE__)->ChannelState[5]) + +#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = \ + (__CHANNEL_STATE__); \ + } while(0) + +#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ + (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ + (__HANDLE__)->ChannelNState[3]) + +#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ + (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ + ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) + +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) + +/** + * @} + */ +/* End of private macros -----------------------------------------------------*/ + +/* Include TIM HAL Extended module */ +#include "stm32f7xx_hal_tim_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * @{ + */ +/* Time Base functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * @{ + */ +/* Timer Output Compare functions *********************************************/ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * @{ + */ +/* Timer PWM functions ********************************************************/ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * @{ + */ +/* Timer Input Capture functions **********************************************/ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * @{ + */ +/* Timer One Pulse functions **************************************************/ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * @{ + */ +/* Timer Encoder functions ****************************************************/ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief IRQ handler management + * @{ + */ +/* Interrupt Handler functions ***********************************************/ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Control functions *********************************************************/ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel); +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * @{ + */ +/* Callback in non blocking modes (Interrupt and DMA) *************************/ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief Peripheral State functions + * @{ + */ +/* Peripheral State functions ************************************************/ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); + +/* Peripheral Channel state functions ************************************************/ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +void TIM_ResetCallback(TIM_HandleTypeDef *htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_TIM_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h index 11b372fb..b9d03484 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_tim_ex.h @@ -1,360 +1,360 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_TIM_EX_H -#define STM32F7xx_HAL_TIM_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types - * @{ - */ - -/** - * @brief TIM Hall sensor Configuration Structure definition - */ - -typedef struct -{ - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ -} TIM_HallSensor_InitTypeDef; -#if defined(TIM_BREAK_INPUT_SUPPORT) - -/** - * @brief TIM Break/Break2 input configuration - */ -typedef struct -{ - uint32_t Source; /*!< Specifies the source of the timer break input. - This parameter can be a value of @ref TIMEx_Break_Input_Source */ - uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. - This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ - uint32_t Polarity; /*!< Specifies the break input source polarity. - This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity - Not relevant when analog watchdog output of the DFSDM1 used as break input source */ -} TIMEx_BreakInputConfigTypeDef; - -#endif /* TIM_BREAK_INPUT_SUPPORT */ -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIM Extended Remapping - * @{ - */ -#define TIM_TIM2_TIM8_TRGO (0x00000000U) -#define TIM_TIM2_ETH_PTP (0x00000400U) -#define TIM_TIM2_USBFS_SOF (0x00000800U) -#define TIM_TIM2_USBHS_SOF (0x00000C00U) -#define TIM_TIM5_GPIO (0x00000000U) -#define TIM_TIM5_LSI (0x00000040U) -#define TIM_TIM5_LSE (0x00000080U) -#define TIM_TIM5_RTC (0x000000C0U) -#define TIM_TIM11_GPIO (0x00000000U) -#define TIM_TIM11_SPDIFRX (0x00000001U) -#define TIM_TIM11_HSE (0x00000002U) -#define TIM_TIM11_MCO1 (0x00000003U) -/** - * @} - */ -#if defined(TIM_BREAK_INPUT_SUPPORT) - -/** @defgroup TIMEx_Break_Input TIM Extended Break input - * @{ - */ -#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ -#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source - * @{ - */ -#define TIM_BREAKINPUTSOURCE_BKIN (0x00000001U) /*!< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_DFSDM1 (0x00000008U) /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling - * @{ - */ -#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity - * @{ - */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ -/** - * @} - */ -#endif /* TIM_BREAK_INPUT_SUPPORT */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros - * @{ - */ - -/** - * @} - */ -/* End of exported macro -----------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros - * @{ - */ -#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\ - ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP) ||\ - ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\ - ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\ - ((__TIM_REMAP__) == TIM_TIM5_GPIO) ||\ - ((__TIM_REMAP__) == TIM_TIM5_LSI) ||\ - ((__TIM_REMAP__) == TIM_TIM5_LSE) ||\ - ((__TIM_REMAP__) == TIM_TIM5_RTC) ||\ - ((__TIM_REMAP__) == TIM_TIM11_GPIO) ||\ - ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX) ||\ - ((__TIM_REMAP__) == TIM_TIM11_HSE) ||\ - ((__TIM_REMAP__) == TIM_TIM11_MCO1)) -#if defined(TIM_BREAK_INPUT_SUPPORT) - -#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ - ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) - -#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM)) - -#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ - ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) - -#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) -#endif /* TIM_BREAK_INPUT_SUPPORT */ - -/** - * @} - */ -/* End of private macro ------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ -/* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); - -void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ -/* Timer Complementary Output Compare functions *****************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ -/* Timer Complementary PWM functions ****************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ -/* Timer Complementary One Pulse functions **********************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - const TIM_MasterConfigTypeDef *sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -#if defined(TIM_BREAK_INPUT_SUPPORT) -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); -#endif /* TIM_BREAK_INPUT_SUPPORT */ -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * @{ - */ -/* Extended Callback **********************************************************/ -void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * @{ - */ -/* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions - * @{ - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); -void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32F7xx_HAL_TIM_EX_H */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim_ex.h + * @author MCD Application Team + * @brief Header file of TIM HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_TIM_EX_H +#define STM32F7xx_HAL_TIM_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup TIMEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types + * @{ + */ + +/** + * @brief TIM Hall sensor Configuration Structure definition + */ + +typedef struct +{ + uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t IC1Filter; /*!< Specifies the input capture filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ +} TIM_HallSensor_InitTypeDef; +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief TIM Break/Break2 input configuration + */ +typedef struct +{ + uint32_t Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIMEx_Break_Input_Source */ + uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ + uint32_t Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity + Not relevant when analog watchdog output of the DFSDM1 used as break input source */ +} TIMEx_BreakInputConfigTypeDef; + +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ +/* End of exported types -----------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants + * @{ + */ + +/** @defgroup TIMEx_Remap TIM Extended Remapping + * @{ + */ +#define TIM_TIM2_TIM8_TRGO (0x00000000U) +#define TIM_TIM2_ETH_PTP (0x00000400U) +#define TIM_TIM2_USBFS_SOF (0x00000800U) +#define TIM_TIM2_USBHS_SOF (0x00000C00U) +#define TIM_TIM5_GPIO (0x00000000U) +#define TIM_TIM5_LSI (0x00000040U) +#define TIM_TIM5_LSE (0x00000080U) +#define TIM_TIM5_RTC (0x000000C0U) +#define TIM_TIM11_GPIO (0x00000000U) +#define TIM_TIM11_SPDIFRX (0x00000001U) +#define TIM_TIM11_HSE (0x00000002U) +#define TIM_TIM11_MCO1 (0x00000003U) +/** + * @} + */ +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** @defgroup TIMEx_Break_Input TIM Extended Break input + * @{ + */ +#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ +#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source + * @{ + */ +#define TIM_BREAKINPUTSOURCE_BKIN (0x00000001U) /*!< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_DFSDM1 (0x00000008U) /*!< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ +/** + * @} + */ + +/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ +#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ +#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ +/** + * @} + */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** + * @} + */ +/* End of exported constants -------------------------------------------------*/ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros + * @{ + */ + +/** + * @} + */ +/* End of exported macro -----------------------------------------------------*/ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros + * @{ + */ +#define IS_TIM_REMAP(__TIM_REMAP__) (((__TIM_REMAP__) == TIM_TIM2_TIM8_TRGO)||\ + ((__TIM_REMAP__) == TIM_TIM2_ETH_PTP) ||\ + ((__TIM_REMAP__) == TIM_TIM2_USBFS_SOF)||\ + ((__TIM_REMAP__) == TIM_TIM2_USBHS_SOF)||\ + ((__TIM_REMAP__) == TIM_TIM5_GPIO) ||\ + ((__TIM_REMAP__) == TIM_TIM5_LSI) ||\ + ((__TIM_REMAP__) == TIM_TIM5_LSE) ||\ + ((__TIM_REMAP__) == TIM_TIM5_RTC) ||\ + ((__TIM_REMAP__) == TIM_TIM11_GPIO) ||\ + ((__TIM_REMAP__) == TIM_TIM11_SPDIFRX) ||\ + ((__TIM_REMAP__) == TIM_TIM11_HSE) ||\ + ((__TIM_REMAP__) == TIM_TIM11_MCO1)) +#if defined(TIM_BREAK_INPUT_SUPPORT) + +#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ + ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) + +#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ + ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM)) + +#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) + +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ + ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/** + * @} + */ +/* End of private macro ------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * @{ + */ +/* Timer Hall Sensor functions **********************************************/ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); + +void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); +void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); + +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * @{ + */ +/* Timer Complementary Output Compare functions *****************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * @{ + */ +/* Timer Complementary PWM functions ****************************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); +/* Non-Blocking mode: DMA */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * @{ + */ +/* Timer Complementary One Pulse functions **********************************/ +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); + +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource); +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig); +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); +#if defined(TIM_BREAK_INPUT_SUPPORT) +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); +#endif /* TIM_BREAK_INPUT_SUPPORT */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * @{ + */ +/* Extended Callback **********************************************************/ +void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); +void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); +/** + * @} + */ + +/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * @{ + */ +/* Extended Peripheral State functions ***************************************/ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); +/** + * @} + */ + +/** + * @} + */ +/* End of exported functions -------------------------------------------------*/ + +/* Private functions----------------------------------------------------------*/ +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* End of private functions --------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + + +#endif /* STM32F7xx_HAL_TIM_EX_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h index 94aafd39..e45f0a3c 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart.h @@ -1,1655 +1,1659 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_uart.h - * @author MCD Application Team - * @brief Header file of UART HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_UART_H -#define STM32F7xx_HAL_UART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ck) / - ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ck) / - ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck is the UART input clock */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, - to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ - - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - - -} UART_InitTypeDef; - -/** - * @brief UART Advanced Features initialization structure definition - */ -typedef struct -{ - uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several - Advanced Features may be initialized at the same time . - This parameter can be a value of - @ref UART_Advanced_Features_Initialization_Type. */ - - uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv. */ - - uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv. */ - - uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic - vs negative/inverted logic). - This parameter can be a value of @ref UART_Data_Inv. */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. - This parameter can be a value of @ref UART_Rx_Tx_Swap. */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. - This parameter can be a value of @ref UART_Overrun_Disable. */ - - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. - This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ - - uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ - - uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate - detection is carried out. - This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. - This parameter can be a value of @ref UART_MSB_First. */ -} UART_AdvFeatureInitTypeDef; - -/** - * @brief HAL UART State definition - * @note HAL UART State value is a combination of 2 different substates: - * gState and RxState (see @ref UART_State_Definition). - * - gState contains UART state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized. HAL UART Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (Peripheral busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef uint32_t HAL_UART_StateTypeDef; - -/** - * @brief UART clock sources definition - */ -typedef enum -{ - UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -} UART_ClockSourceTypeDef; - -/** - * @brief HAL UART Reception type definition - * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * This parameter can be a value of @ref UART_Reception_Type_Values : - * HAL_UART_RECEPTION_STANDARD = 0x00U, - * HAL_UART_RECEPTION_TOIDLE = 0x01U, - * HAL_UART_RECEPTION_TORTO = 0x02U, - * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, - */ -typedef uint32_t HAL_UART_RxTypeTypeDef; - -/** - * @brief HAL UART Rx Event type definition - * @note HAL UART Rx Event type value aims to identify which type of Event has occurred - * leading to call of the RxEvent callback. - * This parameter can be a value of @ref UART_RxEvent_Type_Values : - * HAL_UART_RXEVENT_TC = 0x00U, - * HAL_UART_RXEVENT_HT = 0x01U, - * HAL_UART_RXEVENT_IDLE = 0x02U, - */ -typedef uint32_t HAL_UART_RxEventTypeTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct __UART_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< UART registers base address */ - - UART_InitTypeDef Init; /*!< UART communication parameters */ - - UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - - const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< UART Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< UART Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - - uint16_t Mask; /*!< UART Rx RDR register mask */ - - __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ - - __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ - - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. This parameter - can be a value of @ref HAL_UART_StateTypeDef */ - - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This - parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< UART Error code */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ - void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ - void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ - void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ - void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ - void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ - void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ - void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ - void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ - - void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ - void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -} UART_HandleTypeDef; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief HAL UART Callback ID enumeration definition - */ -typedef enum -{ - HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ - HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ - HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ - HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ - HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ - HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ - HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ - HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ - - HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ - HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ - -} HAL_UART_CallbackIDTypeDef; - -/** - * @brief HAL UART Callback pointer definition - */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ -typedef void (*pUART_RxEventCallbackTypeDef) -(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ - -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported Constants - * @{ - */ - -/** @defgroup UART_State_Definition UART State Code Definition - * @{ - */ -#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ -#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ -#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ -#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing - Value is allowed for RxState only */ -#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState.Value is result - of combination (Or) between gState and RxState values */ -#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ -#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ -/** - * @} - */ - -/** @defgroup UART_Error_Definition UART Error Definition - * @{ - */ -#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ -#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ -#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ -#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE 0x00000000U /*!< No parity */ -#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ -#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ -#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ -#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ -#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ -#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ -/** - * @} - */ - -/** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ -#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - -/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method - * @{ - */ -#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ -#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ -/** - * @} - */ - -/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection - on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection - on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection - on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection - on 0x55 frame detection */ -/** - * @} - */ - -/** @defgroup UART_Receiver_Timeout UART Receiver Timeout - * @{ - */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ -/** - * @} - */ - -/** @defgroup UART_LIN UART Local Interconnection Network mode - * @{ - */ -#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ -#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ -#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ -/** - * @} - */ - -/** @defgroup UART_DMA_Tx UART DMA Tx - * @{ - */ -#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ -#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ -/** - * @} - */ - -/** @defgroup UART_DMA_Rx UART DMA Rx - * @{ - */ -#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ -#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ -/** - * @} - */ - -/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection - * @{ - */ -#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ -#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_Methods UART WakeUp Methods - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ -#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ -/** - * @} - */ - -/** @defgroup UART_Request_Parameters UART Request Parameters - * @{ - */ -#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ -/** - * @} - */ - -/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type - * @{ - */ -#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ -#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ -#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ -#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ -#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ -#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ -/** - * @} - */ - -/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ -#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion - * @{ - */ -#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ -#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap - * @{ - */ -#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ -#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ -/** - * @} - */ - -/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable - * @{ - */ -#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ -/** - * @} - */ - -/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ -/** - * @} - */ - -/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error - * @{ - */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ -/** - * @} - */ - -/** @defgroup UART_MSB_First UART Advanced Feature MSB First - * @{ - */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received - first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received - first enable */ -/** - * @} - */ -#if defined(USART_CR1_UESM) - -/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable - * @{ - */ -#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ -#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ -/** - * @} - */ -#endif /* USART_CR1_UESM */ - -/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable - * @{ - */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ -#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ -/** - * @} - */ - -/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register - * @{ - */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ -/** - * @} - */ -#if defined(USART_CR1_UESM) - -/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection - * @{ - */ -#if defined(USART_CR3_WUS) -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register - not empty or RXFIFO is not empty */ -#else -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register - not empty or RXFIFO is not empty */ -#endif /* USART_CR3_WUS */ -/** - * @} - */ -#endif /* USART_CR1_UESM */ - -/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity - * @{ - */ -#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ -#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB - position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB - position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask - * @{ - */ -#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ -/** - * @} - */ - -/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value - * @{ - */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ -/** - * @} - */ - -/** @defgroup UART_Flags UART Status Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#if defined(USART_ISR_REACK) -#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ -#endif /* USART_ISR_REACK */ -#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ -#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ -#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ -#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ -#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ -#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ -#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ -#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ -#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ -#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ -#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ -#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ -#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ -#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ -#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ -#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ -#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ -#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupts Definition - * Elements values convention: 000ZZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZZ : Flag position in the ISR register(5bits) - * Elements values convention: 000000000XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - * @{ - */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ - -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ - -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ -/** - * @} - */ - -/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags - * @{ - */ -#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ -#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ -#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ -#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ -/** - * @} - */ - -/** @defgroup UART_Reception_Type_Values UART Reception type values - * @{ - */ -#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ -#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ -#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ -#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ -/** - * @} - */ - -/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values - * @{ - */ -#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ -#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ -#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - -/** @brief Reset UART handle states. - * @param __HANDLE__ UART handle. - * @retval None - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0U) -#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ - -/** @brief Flush the UART Data registers. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0U) - -/** @brief Clear the specified UART pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag -#endif -#endif - * @retval None - */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** @brief Clear the UART PE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) - -/** @brief Clear the UART FE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) - -/** @brief Clear the UART NE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) - -/** @brief Clear the UART ORE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) - -/** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) - - -/** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: -#if defined(USART_ISR_REACK) - * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag -#endif - * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - * @arg @ref UART_FLAG_WUF Wake up from stop mode flag -#endif -#endif - * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) - * @arg @ref UART_FLAG_SBKF Send Break flag - * @arg @ref UART_FLAG_CMF Character match flag - * @arg @ref UART_FLAG_BUSY Busy flag - * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag - * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag - * @arg @ref UART_FLAG_CTS CTS Change flag - * @arg @ref UART_FLAG_LBDF LIN Break detection flag - * @arg @ref UART_FLAG_TXE Transmit data register empty flag - * @arg @ref UART_FLAG_TC Transmission Complete flag - * @arg @ref UART_FLAG_RXNE Receive data register not empty flag - * @arg @ref UART_FLAG_RTOF Receiver Timeout flag - * @arg @ref UART_FLAG_IDLE Idle Line detection flag - * @arg @ref UART_FLAG_ORE Overrun Error flag - * @arg @ref UART_FLAG_NE Noise Error flag - * @arg @ref UART_FLAG_FE Framing Error flag - * @arg @ref UART_FLAG_PE Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - -/** @brief Enable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to enable. - * This parameter can be one of the following values: -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt -#endif -#endif - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Disable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to disable. - * This parameter can be one of the following values: -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt -#endif -#endif - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt to check. - * This parameter can be one of the following values: -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt -#endif -#endif - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) - -/** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to check. - * This parameter can be one of the following values: -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt -#endif -#endif - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ - (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ - (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U <<\ - (((uint16_t)(__INTERRUPT__)) &\ - UART_IT_MASK))) != RESET) ? SET : RESET) - -/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt - * This parameter can be one of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag -#endif -#endif - * @retval None - */ -#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) - -/** @brief Set a specific UART request flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __REQ__ specifies the request flag to set - * This parameter can be one of the following values: - * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request - * @arg @ref UART_SENDBREAK_REQUEST Send Break Request - * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request - * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request - * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request - * @retval None - */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) - -/** @brief Enable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) - -/** @brief Enable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** @brief Enable CTS flow control. - * @note This macro allows to enable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0U) - -/** @brief Disable CTS flow control. - * @note This macro allows to disable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0U) - -/** @brief Enable RTS flow control. - * @note This macro allows to enable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0U) - -/** @brief Disable RTS flow control. - * @note This macro allows to disable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0U) -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ - - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) - - -/** @brief Check UART Baud rate. - * @param __BAUDRATE__ Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) - */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 27000001U) - -/** @brief Check UART assertion time. - * @param __TIME__ 5-bit value assertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** @brief Check UART deassertion time. - * @param __TIME__ 5-bit value deassertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** - * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__ UART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ - ((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_1_5) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - - -/** - * @brief Ensure that UART frame parity is valid. - * @param __PARITY__ UART frame parity. - * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ -#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ - ((__PARITY__) == UART_PARITY_EVEN) || \ - ((__PARITY__) == UART_PARITY_ODD)) - -/** - * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__ UART hardware flow control. - * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) - */ -#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) - -/** - * @brief Ensure that UART communication mode is valid. - * @param __MODE__ UART communication mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) - -/** - * @brief Ensure that UART state is valid. - * @param __STATE__ UART state. - * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ -#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ - ((__STATE__) == UART_STATE_ENABLE)) - -/** - * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__ UART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == UART_OVERSAMPLING_8)) - -/** - * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__ UART frame sampling. - * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ -#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ - ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) - -/** - * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__ UART auto Baud rate detection mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) - -/** - * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__ UART receiver timeout setting. - * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) - */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) - -/** @brief Check the receiver timeout value. - * @note The maximum UART receiver timeout value is 0xFFFFFF. - * @param __TIMEOUTVALUE__ receiver timeout value. - * @retval Test result (TRUE or FALSE) - */ -#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) - -/** - * @brief Ensure that UART LIN state is valid. - * @param __LIN__ UART LIN state. - * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) - */ -#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ - ((__LIN__) == UART_LIN_ENABLE)) - -/** - * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__ UART LIN break detection length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) - -/** - * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__ UART DMA TX state. - * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) - */ -#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ - ((__DMATX__) == UART_DMA_TX_ENABLE)) - -/** - * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__ UART DMA RX state. - * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) - */ -#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ - ((__DMARX__) == UART_DMA_RX_ENABLE)) - -/** - * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__ UART half-duplex state. - * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) - */ -#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ - ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) - -/** - * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__ UART wake-up method . - * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) - */ -#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) - -/** - * @brief Ensure that UART request parameter is valid. - * @param __PARAM__ UART request parameter. - * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ -#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ - ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ - ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ - ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ - ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) - -/** - * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__ UART advanced features initialization. - * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) - */ -#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ - UART_ADVFEATURE_TXINVERT_INIT | \ - UART_ADVFEATURE_RXINVERT_INIT | \ - UART_ADVFEATURE_DATAINVERT_INIT | \ - UART_ADVFEATURE_SWAP_INIT | \ - UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ - UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ - UART_ADVFEATURE_MSBFIRST_INIT)) - -/** - * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__ UART frame TX inversion setting. - * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ - ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__ UART frame RX inversion setting. - * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ - ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) - -/** - * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__ UART frame data inversion setting. - * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ - ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__ UART frame RX/TX pins swap setting. - * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) - */ -#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ - ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) - -/** - * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__ UART frame overrun setting. - * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) - */ -#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ - ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) - -/** - * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__ UART auto Baud rate state. - * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ - UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) - -/** - * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__ UART DMA enabling or disabling on error setting. - * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) - */ -#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) - -/** - * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__ UART frame MSB first setting. - * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) - */ -#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) - -#if defined(USART_CR1_UESM) -/** - * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__ UART stop mode state. - * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ - ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) - -#endif /* USART_CR1_UESM */ -/** - * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__ UART mute mode state. - * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) - */ -#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ - ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) -#if defined(USART_CR1_UESM) - -/** - * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__ UART wake-up selection. - * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) - */ -#if defined(USART_CR3_WUFIE) -#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ - ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ - ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) -#else -#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ - ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ - -/** - * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__ UART driver enable polarity. - * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) - */ -#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ - ((__POLARITY__) == UART_DE_POLARITY_LOW)) - - -/** - * @} - */ - -/* Include UART HAL Extended module */ -#include "stm32f7xx_hal_uart_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, - pUART_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); - -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); - -void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); -HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); - -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -----------------------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); - -/** - * @} - */ - -/* Private variables -----------------------------------------------------------*/ -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_UART_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_UART_H +#define STM32F7xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ck) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ck) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ck) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck is the UART input clock */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + UART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + UART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + UART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ +#if defined(USART_CR1_UESM) + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ +#endif /* USART_CR1_UESM */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ +#if defined(USART_CR1_UESM) + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#if defined(USART_CR3_WUS) +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +#else +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +#endif /* USART_CR3_WUS */ +/** + * @} + */ +#endif /* USART_CR1_UESM */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#if defined(USART_ISR_REACK) +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#endif /* USART_ISR_REACK */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE /*!< UART transmit data register empty */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE /*!< UART read data register not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif +#endif + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: +#if defined(USART_ISR_REACK) + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag +#endif + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag +#endif +#endif + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt +#endif +#endif + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag +#endif +#endif + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ + + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) + + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 27000001U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +#if defined(USART_CR1_UESM) +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +#endif /* USART_CR1_UESM */ +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) +#if defined(USART_CR1_UESM) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#if defined(USART_CR3_WUFIE) +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#else +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32f7xx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_UART_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h index 72222fdd..65ee218b 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_uart_ex.h @@ -1,430 +1,432 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_uart_ex.h - * @author MCD Application Team - * @brief Header file of UART HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_UART_EX_H -#define STM32F7xx_HAL_UART_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup UARTEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Types UARTEx Exported Types - * @{ - */ - -#if defined(USART_CR1_UESM) -/** - * @brief UART wake up from stop mode parameters - */ -typedef struct -{ - uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). - This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. - If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must - be filled up. */ - - uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. - This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ - - uint8_t Address; /*!< UART/USART node address (7-bit long max). */ -} UART_WakeUpTypeDef; - -#endif /* USART_CR1_UESM */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants - * @{ - */ - -/** @defgroup UARTEx_Word_Length UARTEx Word Length - * @{ - */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ -/** - * @} - */ - -/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length - * @{ - */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UARTEx_Exported_Functions - * @{ - */ - -/** @addtogroup UARTEx_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, - uint32_t DeassertionTime); - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group2 - * @{ - */ - -#if defined(USART_CR1_UESM) -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - -#endif /* USART_CR1_UESM */ -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral Control functions **********************************************/ -#if defined(USART_CR1_UESM) -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); - -#endif /* USART_CR1_UESM */ -#if defined(USART_CR3_UCESM) -HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); - -#endif /* USART_CR3_UCESM */ -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); - - -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, - uint32_t Timeout); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); - -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); - - -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Macros UARTEx Private Macros - * @{ - */ - -/** @brief Report the UART clock source. - * @param __HANDLE__ specifies the UART Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval UART clocking source, written in __CLOCKSOURCE__. - */ -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - switch(__HAL_RCC_GET_UART4_SOURCE()) \ - { \ - case RCC_UART4CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART4CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART4CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART4CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART5) \ - { \ - switch(__HAL_RCC_GET_UART5_SOURCE()) \ - { \ - case RCC_UART5CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART5CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART5CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART5CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ - case RCC_USART6CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART6CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART6CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART6CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART7) \ - { \ - switch(__HAL_RCC_GET_UART7_SOURCE()) \ - { \ - case RCC_UART7CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART7CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART7CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART7CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if ((__HANDLE__)->Instance == UART8) \ - { \ - switch(__HAL_RCC_GET_UART8_SOURCE()) \ - { \ - case RCC_UART8CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_UART8CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_UART8CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_UART8CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) - -/** @brief Report the UART mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @note If PCE = 1, the parity bit is not included in the data extracted - * by the reception API(). - * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__ specifies the UART Handle. - * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define UART_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ - } while(0U) - -/** - * @brief Ensure that UART frame length is valid. - * @param __LENGTH__ UART frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ - ((__LENGTH__) == UART_WORDLENGTH_8B) || \ - ((__LENGTH__) == UART_WORDLENGTH_9B)) - -/** - * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__ UART wake-up address length. - * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) - */ -#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ - ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_UART_EX_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_UART_EX_H +#define STM32F7xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +#if defined(USART_CR1_UESM) +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +#if defined(USART_CR1_UESM) +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +#endif /* USART_CR1_UESM */ +#if defined(USART_CR3_UCESM) +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); + +#endif /* USART_CR3_UCESM */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + switch(__HAL_RCC_GET_UART4_SOURCE()) \ + { \ + case RCC_UART4CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART4CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART4CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART4CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART5) \ + { \ + switch(__HAL_RCC_GET_UART5_SOURCE()) \ + { \ + case RCC_UART5CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART5CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART5CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART5CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART7) \ + { \ + switch(__HAL_RCC_GET_UART7_SOURCE()) \ + { \ + case RCC_UART7CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART7CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART7CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART7CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if ((__HANDLE__)->Instance == UART8) \ + { \ + switch(__HAL_RCC_GET_UART8_SOURCE()) \ + { \ + case RCC_UART8CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_UART8CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_UART8CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_UART8CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_UART_EX_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h index 9f7e80cf..a8b049e4 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart.h @@ -1,871 +1,870 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_usart.h - * @author MCD Application Team - * @brief Header file of USART HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_USART_H -#define STM32F7xx_HAL_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup USART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup USART_Exported_Types USART Exported Types - * @{ - */ - -/** - * @brief USART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. - The baud rate is computed using the following formula: - Baud Rate Register[15:4] = ((2 * fclk_pres) / - ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * fclk_pres) / - ((huart->Init.BaudRate)))[3:0]) >> 1 - where fclk_pres is the USART input clock frequency - @note Oversampling by 8 is systematically applied to - achieve high baud rates. */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USARTEx_Word_Length. */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_Stop_Bits. */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_Mode. */ - - uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_Clock_Polarity. */ - - uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_Clock_Phase. */ - - uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_Last_Bit. */ - -} USART_InitTypeDef; - -/** - * @brief HAL USART State structures definition - */ -typedef enum -{ - HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ - HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ - HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ - HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_USART_STATE_ERROR = 0x04U /*!< Error */ -} HAL_USART_StateTypeDef; - -/** - * @brief USART clock sources definitions - */ -typedef enum -{ - USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ - USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ - USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ - USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ - USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ - USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ -} USART_ClockSourceTypeDef; - -/** - * @brief USART handle Structure definition - */ -typedef struct __USART_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< USART registers base address */ - - USART_InitTypeDef Init; /*!< USART communication parameters */ - - const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< USART Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< USART Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ - - uint16_t Mask; /*!< USART Rx RDR register mask */ - - void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ - - DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ - - __IO uint32_t ErrorCode; /*!< USART Error code */ - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ - void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ - void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ - void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ - void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ - void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ - void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ - - void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ - void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - -} USART_HandleTypeDef; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -/** - * @brief HAL USART Callback ID enumeration definition - */ -typedef enum -{ - HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ - HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ - HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ - HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ - HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ - HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ - HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ - - HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */ - HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */ - -} HAL_USART_CallbackIDTypeDef; - -/** - * @brief HAL USART Callback pointer definition - */ -typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ - -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_Exported_Constants USART Exported Constants - * @{ - */ - -/** @defgroup USART_Error_Definition USART Error Definition - * @{ - */ -#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ -#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ -#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ -#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ -/** - * @} - */ - -/** @defgroup USART_Stop_Bits USART Number of Stop Bits - * @{ - */ -#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ -#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ -#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ -#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ -/** - * @} - */ - -/** @defgroup USART_Parity USART Parity - * @{ - */ -#define USART_PARITY_NONE 0x00000000U /*!< No parity */ -#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ -#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ -/** - * @} - */ - -/** @defgroup USART_Mode USART Mode - * @{ - */ -#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ -#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ -/** - * @} - */ - -/** @defgroup USART_Clock USART Clock - * @{ - */ -#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */ -#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */ -/** - * @} - */ - -/** @defgroup USART_Clock_Polarity USART Clock Polarity - * @{ - */ -#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */ -#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */ -/** - * @} - */ - -/** @defgroup USART_Clock_Phase USART Clock Phase - * @{ - */ -#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */ -#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */ -/** - * @} - */ - -/** @defgroup USART_Last_Bit USART Last Bit - * @{ - */ -#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */ -#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */ -/** - * @} - */ - - -/** @defgroup USART_Request_Parameters USART Request Parameters - * @{ - */ -#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ -#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ -/** - * @} - */ - -/** @defgroup USART_Flags USART Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ -#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ -#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ -#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ -#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ -#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ -#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ -#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ -#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ -#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ -#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ -#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ -/** - * @} - */ - -/** @defgroup USART_Interrupt_definition USART Interrupts Definition - * Elements values convention: 0000ZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZ : Flag position in the ISR register(4bits) - * @{ - */ - -#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ -#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ -#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ -#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ -#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ -#define USART_IT_ERR 0x0060U /*!< USART error interruption */ -#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ -#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ -#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ - -/** - * @} - */ - -/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags - * @{ - */ -#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ -#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ -/** - * @} - */ - -/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask - * @{ - */ -#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ -#define USART_CR_MASK 0x00E0U /*!< USART control register mask */ -#define USART_CR_POS 5U /*!< USART control register position */ -#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ -#define USART_ISR_POS 8U /*!< USART ISR register position */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup USART_Exported_Macros USART Exported Macros - * @{ - */ - -/** @brief Reset USART handle state. - * @param __HANDLE__ USART handle. - * @retval None - */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_USART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - -/** @brief Check whether the specified USART flag is set or not. - * @param __HANDLE__ specifies the USART Handle - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag - * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag - * @arg @ref USART_FLAG_BUSY Busy flag - * @arg @ref USART_FLAG_TXE Transmit data register empty flag - * @arg @ref USART_FLAG_TC Transmission Complete flag - * @arg @ref USART_FLAG_RXNE Receive data register not empty flag - * @arg @ref USART_FLAG_RTOF Receiver Timeout flag - * @arg @ref USART_FLAG_IDLE Idle Line detection flag - * @arg @ref USART_FLAG_ORE OverRun Error flag - * @arg @ref USART_FLAG_NE Noise Error flag - * @arg @ref USART_FLAG_FE Framing Error flag - * @arg @ref USART_FLAG_PE Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified USART pending flag. - * @param __HANDLE__ specifies the USART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag - * @retval None - */ -#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** @brief Clear the USART PE pending flag. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) - -/** @brief Clear the USART FE pending flag. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) - -/** @brief Clear the USART NE pending flag. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) - -/** @brief Clear the USART ORE pending flag. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) - -/** @brief Clear the USART IDLE pending flag. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) - - - -/** @brief Enable the specified USART interrupt. - * @param __HANDLE__ specifies the USART Handle. - * @param __INTERRUPT__ specifies the USART interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ - (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) - -/** @brief Disable the specified USART interrupt. - * @param __HANDLE__ specifies the USART Handle. - * @param __INTERRUPT__ specifies the USART interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ - (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) - -/** @brief Check whether the specified USART interrupt has occurred or not. - * @param __HANDLE__ specifies the USART Handle. - * @param __INTERRUPT__ specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_ORE OverRun Error interrupt - * @arg @ref USART_IT_NE Noise Error interrupt - * @arg @ref USART_IT_FE Framing Error interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ - USART_ISR_POS))) != 0U) ? SET : RESET) - -/** @brief Check whether the specified USART interrupt source is enabled or not. - * @param __HANDLE__ specifies the USART Handle. - * @param __INTERRUPT__ specifies the USART interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref USART_IT_TC Transmission complete interrupt - * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref USART_IT_IDLE Idle line detection interrupt - * @arg @ref USART_IT_ORE OverRun Error interrupt - * @arg @ref USART_IT_NE Noise Error interrupt - * @arg @ref USART_IT_FE Framing Error interrupt - * @arg @ref USART_IT_PE Parity Error interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ - (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ - (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U <<\ - (((uint16_t)(__INTERRUPT__)) &\ - USART_IT_MASK))) != 0U) ? SET : RESET) - -/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__ specifies the USART Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt. - * This parameter can be one of the following values: - * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag - * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag - * @retval None - */ -#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) - -/** @brief Set a specific USART request flag. - * @param __HANDLE__ specifies the USART Handle. - * @param __REQ__ specifies the request flag to set. - * This parameter can be one of the following values: - * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request - * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request - * - * @retval None - */ -#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) - -/** @brief Enable the USART one bit sample method. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disable the USART one bit sample method. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) - -/** @brief Enable USART. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable USART. - * @param __HANDLE__ specifies the USART Handle. - * @retval None - */ -#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup USART_Private_Macros USART Private Macros - * @{ - */ - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__ USART clock. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) - -/** @brief Report the USART clock source. - * @param __HANDLE__ specifies the USART Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval the USART clocking source, written in __CLOCKSOURCE__. - */ -#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ - { \ - case RCC_USART1CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART1CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART1CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART1CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - switch(__HAL_RCC_GET_USART2_SOURCE()) \ - { \ - case RCC_USART2CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART2CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART2CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART2CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - switch(__HAL_RCC_GET_USART3_SOURCE()) \ - { \ - case RCC_USART3CLKSOURCE_PCLK1: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ - break; \ - case RCC_USART3CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART3CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART3CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - switch(__HAL_RCC_GET_USART6_SOURCE()) \ - { \ - case RCC_USART6CLKSOURCE_PCLK2: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ - break; \ - case RCC_USART6CLKSOURCE_HSI: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ - break; \ - case RCC_USART6CLKSOURCE_SYSCLK: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ - break; \ - case RCC_USART6CLKSOURCE_LSE: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ - break; \ - default: \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - break; \ - } \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ - } \ - } while(0U) - -/** @brief Check USART Baud rate. - * @param __BAUDRATE__ Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ -#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U) - -/** - * @brief Ensure that USART frame number of stop bits is valid. - * @param __STOPBITS__ USART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ - ((__STOPBITS__) == USART_STOPBITS_1) || \ - ((__STOPBITS__) == USART_STOPBITS_1_5) || \ - ((__STOPBITS__) == USART_STOPBITS_2)) - -/** - * @brief Ensure that USART frame parity is valid. - * @param __PARITY__ USART frame parity. - * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ -#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ - ((__PARITY__) == USART_PARITY_EVEN) || \ - ((__PARITY__) == USART_PARITY_ODD)) - -/** - * @brief Ensure that USART communication mode is valid. - * @param __MODE__ USART communication mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) - -/** - * @brief Ensure that USART clock state is valid. - * @param __CLOCK__ USART clock state. - * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) - */ -#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ - ((__CLOCK__) == USART_CLOCK_ENABLE)) - -/** - * @brief Ensure that USART frame polarity is valid. - * @param __CPOL__ USART frame polarity. - * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) - */ -#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) - -/** - * @brief Ensure that USART frame phase is valid. - * @param __CPHA__ USART frame phase. - * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) - */ -#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) - -/** - * @brief Ensure that USART frame last bit clock pulse setting is valid. - * @param __LASTBIT__ USART frame last bit clock pulse setting. - * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) - */ -#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ - ((__LASTBIT__) == USART_LASTBIT_ENABLE)) - -/** - * @brief Ensure that USART request parameter is valid. - * @param __PARAM__ USART request parameter. - * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ -#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ - ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) - -/** - * @} - */ - -/* Include USART HAL Extended module */ -#include "stm32f7xx_hal_usart_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USART_Exported_Functions USART Exported Functions - * @{ - */ - -/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); -HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); -void HAL_USART_MspInit(USART_HandleTypeDef *husart); -void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, - pUSART_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup USART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size); -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size); -HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); -HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); -HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); -HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); - -void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); -void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); -void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); -void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); - -/** - * @} - */ - -/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State and Error functions ***************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_USART_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_usart.h + * @author MCD Application Team + * @brief Header file of USART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_USART_H +#define STM32F7xx_HAL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. + The baud rate is computed using the following formula: + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode. */ + + uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity. */ + + uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase. */ + + uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit. */ + +} USART_InitTypeDef; + +/** + * @brief HAL USART State structures definition + */ +typedef enum +{ + HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */ + HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */ + HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_USART_STATE_ERROR = 0x04U /*!< Error */ +} HAL_USART_StateTypeDef; + +/** + * @brief USART clock sources definitions + */ +typedef enum +{ + USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */ + USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */ + USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */ + USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */ + USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */ +} USART_ClockSourceTypeDef; + +/** + * @brief USART handle Structure definition + */ +typedef struct __USART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< USART registers base address */ + + USART_InitTypeDef Init; /*!< USART communication parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< USART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< USART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */ + + uint16_t Mask; /*!< USART Rx RDR register mask */ + + void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ + + DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */ + + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_USART_StateTypeDef State; /*!< USART communication state */ + + __IO uint32_t ErrorCode; /*!< USART Error code */ + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */ + void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */ + void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */ + void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */ + + void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */ + void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} USART_HandleTypeDef; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL USART Callback ID enumeration definition + */ +typedef enum +{ + HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */ + HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */ + HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */ + HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */ + HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */ + HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */ + HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */ + + HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */ + HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */ + +} HAL_USART_CallbackIDTypeDef; + +/** + * @brief HAL USART Callback pointer definition + */ +typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */ + +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_Error_Definition USART Error Definition + * @{ + */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ +/** + * @} + */ + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */ +#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_NONE 0x00000000U /*!< No parity */ +#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup USART_Mode USART Mode + * @{ + */ +#define USART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define USART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup USART_Clock USART Clock + * @{ + */ +#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */ +#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */ +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity + * @{ + */ +#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */ +#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase + * @{ + */ +#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */ +#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */ +/** + * @} + */ + +/** @defgroup USART_Last_Bit USART Last Bit + * @{ + */ +#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */ +#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */ +/** + * @} + */ + + +/** @defgroup USART_Request_Parameters USART Request Parameters + * @{ + */ +#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup USART_Flags USART Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */ +#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */ +#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */ +#define USART_FLAG_TXE USART_ISR_TXE /*!< USART transmit data register empty */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ +#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ +#define USART_FLAG_RXNE USART_ISR_RXNE /*!< USART read data register not empty */ +#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */ +#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */ +#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */ +#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */ +#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */ +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition USART Interrupts Definition + * Elements values convention: 0000ZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ + +#define USART_IT_PE 0x0028U /*!< USART parity error interruption */ +#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */ +#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */ +#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */ +#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */ +#define USART_IT_ERR 0x0060U /*!< USART error interruption */ +#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */ +#define USART_IT_NE 0x0200U /*!< USART noise error interruption */ +#define USART_IT_FE 0x0100U /*!< USART frame error interruption */ + +/** + * @} + */ + +/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags + * @{ + */ +#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define USART_CLEAR_NEF USART_ICR_NCF /*!< Noise Error detected Clear Flag */ +#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask + * @{ + */ +#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */ +#define USART_CR_MASK 0x00E0U /*!< USART control register mask */ +#define USART_CR_POS 5U /*!< USART control register position */ +#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */ +#define USART_ISR_POS 8U /*!< USART ISR register position */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup USART_Exported_Macros USART Exported Macros + * @{ + */ + +/** @brief Reset USART handle state. + * @param __HANDLE__ USART handle. + * @retval None + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_USART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** @brief Check whether the specified USART flag is set or not. + * @param __HANDLE__ specifies the USART Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref USART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref USART_FLAG_BUSY Busy flag + * @arg @ref USART_FLAG_TXE Transmit data register empty flag + * @arg @ref USART_FLAG_TC Transmission Complete flag + * @arg @ref USART_FLAG_RXNE Receive data register not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag + * @arg @ref USART_FLAG_IDLE Idle Line detection flag + * @arg @ref USART_FLAG_ORE OverRun Error flag + * @arg @ref USART_FLAG_NE Noise Error flag + * @arg @ref USART_FLAG_FE Framing Error flag + * @arg @ref USART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the specified USART pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag + * @retval None + */ +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF) + +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF) + +/** @brief Clear the USART NE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF) + +/** @brief Clear the USART ORE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF) + +/** @brief Clear the USART IDLE pending flag. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF) + + +/** @brief Enable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Disable the specified USART interrupt. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + +/** @brief Check whether the specified USART interrupt has occurred or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) + +/** @brief Check whether the specified USART interrupt source is enabled or not. + * @param __HANDLE__ specifies the USART Handle. + * @param __INTERRUPT__ specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref USART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref USART_IT_TC Transmission complete interrupt + * @arg @ref USART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref USART_IT_IDLE Idle line detection interrupt + * @arg @ref USART_IT_ORE OverRun Error interrupt + * @arg @ref USART_IT_NE Noise Error interrupt + * @arg @ref USART_IT_FE Framing Error interrupt + * @arg @ref USART_IT_PE Parity Error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) + +/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt. + * This parameter can be one of the following values: + * @arg @ref USART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref USART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @retval None + */ +#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific USART request flag. + * @param __HANDLE__ specifies the USART Handle. + * @param __REQ__ specifies the request flag to set. + * This parameter can be one of the following values: + * @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * + * @retval None + */ +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the USART one bit sample method. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable USART. + * @param __HANDLE__ specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup USART_Private_Macros USART Private Macros + * @{ + */ + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ USART clock. + * @param __BAUD__ Baud rate set by the user. + * @retval Division result + */ +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Report the USART clock source. + * @param __HANDLE__ specifies the USART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval the USART clocking source, written in __CLOCKSOURCE__. + */ +#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ + { \ + case RCC_USART1CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + switch(__HAL_RCC_GET_USART3_SOURCE()) \ + { \ + case RCC_USART3CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART3CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART3CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART3CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + switch(__HAL_RCC_GET_USART6_SOURCE()) \ + { \ + case RCC_USART6CLKSOURCE_PCLK2: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ + break; \ + case RCC_USART6CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART6CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART6CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + break; \ + } \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \ + } \ + } while(0U) + +/** @brief Check USART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */ +#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U) + +/** + * @brief Ensure that USART frame number of stop bits is valid. + * @param __STOPBITS__ USART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \ + ((__STOPBITS__) == USART_STOPBITS_1) || \ + ((__STOPBITS__) == USART_STOPBITS_1_5) || \ + ((__STOPBITS__) == USART_STOPBITS_2)) + +/** + * @brief Ensure that USART frame parity is valid. + * @param __PARITY__ USART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \ + ((__PARITY__) == USART_PARITY_EVEN) || \ + ((__PARITY__) == USART_PARITY_ODD)) + +/** + * @brief Ensure that USART communication mode is valid. + * @param __MODE__ USART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that USART clock state is valid. + * @param __CLOCK__ USART clock state. + * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid) + */ +#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \ + ((__CLOCK__) == USART_CLOCK_ENABLE)) + +/** + * @brief Ensure that USART frame polarity is valid. + * @param __CPOL__ USART frame polarity. + * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid) + */ +#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH)) + +/** + * @brief Ensure that USART frame phase is valid. + * @param __CPHA__ USART frame phase. + * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid) + */ +#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE)) + +/** + * @brief Ensure that USART frame last bit clock pulse setting is valid. + * @param __LASTBIT__ USART frame last bit clock pulse setting. + * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid) + */ +#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \ + ((__LASTBIT__) == USART_LASTBIT_ENABLE)) + +/** + * @brief Ensure that USART request parameter is valid. + * @param __PARAM__ USART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST)) + +/** + * @} + */ + +/* Include USART HAL Extended module */ +#include "stm32f7xx_hal_usart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); +void HAL_USART_MspInit(USART_HandleTypeDef *husart); +void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart); +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart); + +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart); +void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); +void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); +void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Error functions ***************************************/ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_USART_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h index 92d90c7c..cbe04a8b 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_usart_ex.h @@ -1,170 +1,170 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_usart_ex.h - * @author MCD Application Team - * @brief Header file of USART HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_USART_EX_H -#define STM32F7xx_HAL_USART_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup USARTEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants - * @{ - */ - -/** @defgroup USARTEx_Word_Length USARTEx Word Length - * @{ - */ -#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ -/** - * @} - */ - - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup USARTEx_Private_Macros USARTEx Private Macros - * @{ - */ - -/** @brief Compute the USART mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @note If PCE = 1, the parity bit is not included in the data extracted - * by the reception API(). - * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__ specifies the USART Handle. - * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define USART_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FFU; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FFU; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FFU; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007FU; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007FU; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003FU; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ - } while(0U) - -/** - * @brief Ensure that USART frame length is valid. - * @param __LENGTH__ USART frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ - ((__LENGTH__) == USART_WORDLENGTH_8B) || \ - ((__LENGTH__) == USART_WORDLENGTH_9B)) - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USARTEx_Exported_Functions - * @{ - */ - -/** @addtogroup USARTEx_Exported_Functions_Group1 - * @{ - */ - -/* IO operation functions *****************************************************/ - -/** - * @} - */ - -/** @addtogroup USARTEx_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions ***********************************************/ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_USART_EX_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_usart_ex.h + * @author MCD Application Team + * @brief Header file of USART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_HAL_USART_EX_H +#define STM32F7xx_HAL_USART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup USARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants + * @{ + */ + +/** @defgroup USARTEx_Word_Length USARTEx Word Length + * @{ + */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ +/** + * @} + */ + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup USARTEx_Private_Macros USARTEx Private Macros + * @{ + */ + +/** @brief Compute the USART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the USART Handle. + * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define USART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that USART frame length is valid. + * @param __LENGTH__ USART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \ + ((__LENGTH__) == USART_WORDLENGTH_8B) || \ + ((__LENGTH__) == USART_WORDLENGTH_9B)) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup USARTEx_Exported_Functions_Group1 + * @{ + */ + +/* IO operation functions *****************************************************/ + +/** + * @} + */ + +/** @addtogroup USARTEx_Exported_Functions_Group2 + * @{ + */ + +/* Peripheral Control functions ***********************************************/ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_HAL_USART_EX_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h deleted file mode 100644 index ca099ba9..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_wwdg.h +++ /dev/null @@ -1,298 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_wwdg.h - * @author MCD Application Team - * @brief Header file of WWDG HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_HAL_WWDG_H -#define STM32F7xx_HAL_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup WWDG - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Types WWDG Exported Types - * @{ - */ - -/** - * @brief WWDG Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG. - This parameter can be a value of @ref WWDG_Prescaler */ - - uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter. - This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */ - - uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value. - This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ - - uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not. - This parameter can be a value of @ref WWDG_EWI_Mode */ - -} WWDG_InitTypeDef; - -/** - * @brief WWDG handle Structure definition - */ -#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -typedef struct __WWDG_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ -{ - WWDG_TypeDef *Instance; /*!< Register base address */ - - WWDG_InitTypeDef Init; /*!< WWDG required parameters */ - -#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */ - - void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */ -#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ -} WWDG_HandleTypeDef; - -#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -/** - * @brief HAL WWDG common Callback ID enumeration definition - */ -typedef enum -{ - HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */ - HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */ -} HAL_WWDG_CallbackIDTypeDef; - -/** - * @brief HAL WWDG Callback pointer definition - */ -typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */ - -#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Constants WWDG Exported Constants - * @{ - */ - -/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition - * @{ - */ -#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */ -/** - * @} - */ - -/** @defgroup WWDG_Flag_definition WWDG Flag definition - * @brief WWDG Flag definition - * @{ - */ -#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */ -/** - * @} - */ - -/** @defgroup WWDG_Prescaler WWDG Prescaler - * @{ - */ -#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */ -/** - * @} - */ - -/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode - * @{ - */ -#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */ -#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Macros WWDG Private Macros - * @{ - */ -#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ - ((__PRESCALER__) == WWDG_PRESCALER_2) || \ - ((__PRESCALER__) == WWDG_PRESCALER_4) || \ - ((__PRESCALER__) == WWDG_PRESCALER_8)) - -#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W)) - -#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T)) - -#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \ - ((__MODE__) == WWDG_EWI_DISABLE)) -/** - * @} - */ - - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Macros WWDG Exported Macros - * @{ - */ - -/** - * @brief Enable the WWDG peripheral. - * @param __HANDLE__ WWDG handle - * @retval None - */ -#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) - -/** - * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__ WWDG handle - * @param __INTERRUPT__ specifies the interrupt to enable. - * This parameter can be one of the following values: - * @arg WWDG_IT_EWI: Early wakeup interrupt - * @note Once enabled this interrupt cannot be disabled except by a system reset. - * @retval None - */ -#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__)) - -/** - * @brief Check whether the selected WWDG interrupt has occurred or not. - * @param __HANDLE__ WWDG handle - * @param __INTERRUPT__ specifies the it to check. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT - * @retval The new state of WWDG_FLAG (SET or RESET). - */ -#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__)) - -/** @brief Clear the WWDG interrupt pending bits. - * bits to clear the selected interrupt pending bits. - * @param __HANDLE__ WWDG handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag - */ -#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) - -/** - * @brief Check whether the specified WWDG flag is set or not. - * @param __HANDLE__ WWDG handle - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag - * @retval The new state of WWDG_FLAG (SET or RESET). - */ -#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the WWDG's pending flags. - * @param __HANDLE__ WWDG handle - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag - * @retval None - */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** @brief Check whether the specified WWDG interrupt source is enabled or not. - * @param __HANDLE__ WWDG Handle. - * @param __INTERRUPT__ specifies the WWDG interrupt source to check. - * This parameter can be one of the following values: - * @arg WWDG_IT_EWI: Early Wakeup Interrupt - * @retval state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\ - & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup WWDG_Exported_Functions - * @{ - */ - -/** @addtogroup WWDG_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, - pWWDG_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup WWDG_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); -void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_HAL_WWDG_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h index 55a34aef..ddcbd909 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h @@ -1,4730 +1,4730 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_adc.h - * @author MCD Application Team - * @brief Header file of ADC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_ADC_H -#define __STM32F7xx_LL_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (ADC1) || defined (ADC2) || defined (ADC3) - -/** @defgroup ADC_LL ADC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Constants ADC Private Constants - * @{ - */ - -/* Internal mask for ADC group regular sequencer: */ -/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ -/* - sequencer register offset */ -/* - sequencer rank bits position into the selected register */ - -/* Internal register offset for ADC group regular sequencer configuration */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_SQR1_REGOFFSET 0x00000000U -#define ADC_SQR2_REGOFFSET 0x00000100U -#define ADC_SQR3_REGOFFSET 0x00000200U -#define ADC_SQR4_REGOFFSET 0x00000300U - -#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) -#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) - -/* Definition of ADC group regular sequencer bits information to be inserted */ -/* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ -#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ -#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ -#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ -#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ -#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ -#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ -#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ -#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ - -/* Internal mask for ADC group injected sequencer: */ -/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ -/* - data register offset */ -/* - offset register offset */ -/* - sequencer rank bits position into the selected register */ - -/* Internal register offset for ADC group injected data register */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_JDR1_REGOFFSET 0x00000000U -#define ADC_JDR2_REGOFFSET 0x00000100U -#define ADC_JDR3_REGOFFSET 0x00000200U -#define ADC_JDR4_REGOFFSET 0x00000300U - -/* Internal register offset for ADC group injected offset configuration */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_JOFR1_REGOFFSET 0x00000000U -#define ADC_JOFR2_REGOFFSET 0x00001000U -#define ADC_JOFR3_REGOFFSET 0x00002000U -#define ADC_JOFR4_REGOFFSET 0x00003000U - -#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) -#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) -#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) - -/* Internal mask for ADC group regular trigger: */ -/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ -/* - regular trigger source */ -/* - regular trigger edge */ -#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ - -/* Mask containing trigger source masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \ - ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \ - ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \ - ((ADC_CR2_EXTSEL) >> (4U * 3U))) - -/* Mask containing trigger edge masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) - -/* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ - - - -/* Internal mask for ADC group injected trigger: */ -/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ -/* - injected trigger source */ -/* - injected trigger edge */ -#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ - -/* Mask containing trigger source masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \ - ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \ - ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \ - ((ADC_CR2_JEXTSEL) >> (4U * 3U))) - -/* Mask containing trigger edge masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ - ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) - -/* Definition of ADC group injected trigger bits information. */ -#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ -#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ - -/* Internal mask for ADC channel: */ -/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ -/* - channel identifier defined by number */ -/* - channel differentiation between external channels (connected to */ -/* GPIO pins) and internal channels (connected to internal paths) */ -/* - channel sampling time defined by SMPRx register offset */ -/* and SMPx bits positions into SMPRx register */ -#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ -#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) -/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ - -/* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ -#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ -#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ -#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) - -/* Internal register offset for ADC channel sampling time configuration */ -/* (offset placed into a spare area of literal definition) */ -#define ADC_SMPR1_REGOFFSET 0x00000000U -#define ADC_SMPR2_REGOFFSET 0x02000000U -#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) - -#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U -#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ - -/* Definition of channels ID number information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER 0x00000000U -#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) -#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) -#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) -#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) -#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) -#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) -#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) -#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) -#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) -#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) - -/* Definition of channels sampling time information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ -#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ -#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ -#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ -#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ -#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ -#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ -#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ -#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ -#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ -#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ -#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ -#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ -#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ -#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ -#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ -#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ -#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ -#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ - -/* Internal mask for ADC analog watchdog: */ -/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ -/* (concatenation of multiple bits used in different analog watchdogs, */ -/* (feature of several watchdogs not available on all STM32 families)). */ -/* - analog watchdog 1: monitored channel defined by number, */ -/* selection of ADC group (ADC groups regular and-or injected). */ - -/* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET 0x00000000U - -#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) - -#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) -#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) - -/* Internal register offset for ADC analog watchdog threshold configuration */ -#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U -#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U -#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) - -/* ADC registers bits positions */ -#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ -#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ -/* ADC internal channels related definitions */ -/* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR VREFINT_CAL_ADDR_CMSIS /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ -/* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR TEMPSENSOR_CAL1_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR TEMPSENSOR_CAL2_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Macros ADC Private Macros - * @{ - */ - -/** - * @brief Driver macro reserved for internal use: isolate bits with the - * selected mask and shift them to the register LSB - * (shift mask on register position bit 0). - * @param __BITS__ Bits in register 32 bits - * @param __MASK__ Mask in register 32 bits - * @retval Bits in register 32 bits - */ -#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ - (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) - -/** - * @brief Driver macro reserved for internal use: set a pointer to - * a register from a register basis from which an offset - * is applied. - * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). - * @retval Pointer to register address - */ -#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) - -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure - * @{ - */ - -/** - * @brief Structure definition of some features of ADC common parameters - * and multimode - * (all ADC instances belonging to the same ADC common instance). - * @note The setting of these parameters by function @ref LL_ADC_CommonInit() - * is conditioned to ADC instances state (all ADC instances - * sharing the same ADC common instance): - * All ADC instances sharing the same ADC common instance must be - * disabled. - */ -typedef struct -{ - uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. - This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ - - uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). - This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ - - uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. - This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ - - uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. - This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ - -} LL_ADC_CommonInitTypeDef; - -/** - * @brief Structure definition of some features of ADC instance. - * @note These parameters have an impact on ADC scope: ADC instance. - * Affects both group regular and group injected (availability - * of ADC group injected depends on STM32 families). - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Instance . - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t Resolution; /*!< Set ADC resolution. - This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ - - uint32_t DataAlignment; /*!< Set ADC conversion data alignment. - This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ - - uint32_t SequencersScanMode; /*!< Set ADC scan selection. - This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ - -} LL_ADC_InitTypeDef; - -/** - * @brief Structure definition of some features of ADC group regular. - * @note These parameters have an impact on ADC scope: ADC group regular. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "REG"). - * @note The setting of these parameters by function @ref LL_ADC_REG_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). - This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 series, setting of external trigger edge is performed - using function @ref LL_ADC_REG_StartConversionExtTrig(). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ - - uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH - @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE - @note This parameter has an effect only if group regular sequencer is enabled - (scan length of 2 ranks or more). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ - - uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). - This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE - Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ - - uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. - This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ - -} LL_ADC_REG_InitTypeDef; - -/** - * @brief Structure definition of some features of ADC group injected. - * @note These parameters have an impact on ADC scope: ADC group injected. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "INJ"). - * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). - This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE - @note On this STM32 series, setting of external trigger edge is performed - using function @ref LL_ADC_INJ_StartConversionExtTrig(). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ - - uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. - This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH - @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. - This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE - @note This parameter has an effect only if group injected sequencer is enabled - (scan length of 2 ranks or more). - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ - - uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. - This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO - Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. - - This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ - -} LL_ADC_INJ_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_LL_EC_FLAG ADC flags - * @brief Flags defines which can be used with LL_ADC_ReadReg function - * @{ - */ -#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ -#define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ -#define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ -#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ -#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ -#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ -#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ -#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ -#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ -#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ -#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ -#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ -#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */ -#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) - * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions - * @{ - */ -#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ -#define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ -#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ -#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose - * @{ - */ -/* List of ADC registers intended to be used (most commonly) with */ -/* DMA transfer. */ -/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ -#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source - * @{ - */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels - * @{ - */ -/* Note: Other measurement paths to internal channels may be available */ -/* (connections to other peripherals). */ -/* If they are not listed below, they do not require any specific */ -/* path enable. In this case, Access to measurement path is done */ -/* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */ -#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ -#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ -#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution - * @{ - */ -#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ -#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */ -#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */ -#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment - * @{ - */ -#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection - * @{ - */ -#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ -#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups - * @{ - */ -#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ -#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ -#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number - * @{ - */ -#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ -#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ -#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ -#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ -#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ -#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ -#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. */ -#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. */ -#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source - * @{ - */ -#define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM5_TRGO (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 |ADC_CR2_EXTSEL_2| ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge - * @{ - */ -#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ -#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ -#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ -#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ -#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data - * @{ - */ -#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions) - * @{ - */ -#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */ -#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length - * @{ - */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode - * @{ - */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ -#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ -#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ -#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks - * @{ - */ -#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ -#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ -#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ -#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ -#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ -#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ -#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ -#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ -#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ -#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ -#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ -#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ -#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ -#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ -#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ -#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source - * @{ - */ -#define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ - -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge - * @{ - */ -#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ -#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ -#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode -* @{ -*/ -#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ -#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ -/** - * @} - */ - - -/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length - * @{ - */ -#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode - * @{ - */ -#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ -#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks - * @{ - */ -#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ -#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ -#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ -#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time - * @{ - */ -#define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number - * @{ - */ -#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels - * @{ - */ -#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ -#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ -#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ -#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ -#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ -#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ -#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ -#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ -#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ -#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ -#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ -#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ -#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ -#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds - * @{ - */ -#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ -#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode - * @{ - */ -#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ -#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ -#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */ -#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ -#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ -#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ -#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ -#if defined(ADC3) -#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */ -#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */ -#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */ -#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */ -#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */ -#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ -#endif -/** - * @} - */ - -/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer - * @{ - */ -#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ -#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ -#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */ -#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ -#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ -#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */ -#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases - * @{ - */ -#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/ -#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */ -#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave - * @{ - */ -#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ -#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ -#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ -/** - * @} - */ - - - -/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays - * @note Only ADC IP HW delays are defined in ADC LL driver driver, - * not timeout values. - * For details on delays values, refer to descriptions in source code - * above each literal definition. - * @{ - */ - -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ -/* not timeout values. */ -/* Timeout values for ADC operations are dependent to device clock */ -/* configuration (system clock versus ADC clock), */ -/* and therefore must be defined in user application. */ -/* Indications for estimation of ADC timeout delays, for this */ -/* STM32 series: */ -/* - ADC enable time: maximum delay is 2us */ -/* (refer to device datasheet, parameter "tSTAB") */ -/* - ADC conversion time: duration depending on ADC clock and ADC */ -/* configuration. */ -/* (refer to device reference manual, section "Timing") */ - -/* Delay for internal voltage reference stabilization time. */ -/* Delay set to maximum value (refer to device datasheet, */ -/* parameter "tSTART"). */ -/* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ - -/* Delay for temperature sensor stabilization time. */ -/* Literal set to maximum value (refer to device datasheet, */ -/* parameter "tSTART"). */ -/* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros - * @{ - */ - -/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro - * @{ - */ - -/** - * @brief Helper macro to get ADC channel number in decimal format - * from literals LL_ADC_CHANNEL_x. - * @note Example: - * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) - * will return decimal number "4". - * @note The input can be a value from functions where a channel - * number is returned, either defined with number - * or with bitfield (only one bit must be set). - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @retval Value between Min_Data=0 and Max_Data=18 - */ -#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - -/** - * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x - * from number in decimal format. - * @note Example: - * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) - * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) <= 9U) \ - ? ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - : \ - ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ - ) \ - ) - -/** - * @brief Helper macro to determine whether the selected channel - * corresponds to literal definitions of driver. - * @note The different literal definitions of ADC channels are: - * - ADC internal channel: - * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... - * - ADC external channel (channel connected to a GPIO pin): - * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... - * @note The channel parameter must be a value defined from literal - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), - * must not be a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). - * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. - */ -#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) - -/** - * @brief Helper macro to convert a channel defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * to its equivalent parameter definition of a ADC external channel - * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). - * @note The channel parameter can be, additionally to a value - * defined from parameter definition of a ADC internal channel - * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), - * a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is returned - * from ADC registers. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - */ -#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) - -/** - * @brief Helper macro to determine whether the internal channel - * selected is available on the ADC instance selected. - * @note The channel parameter must be a value defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * must not be a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __ADC_INSTANCE__ ADC instance - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1. - * (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. - * Value "1" if the internal channel selected is available on the ADC instance selected. - */ -#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - ( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ - ) -/** - * @brief Helper macro to define ADC analog watchdog parameter: - * define a single channel to monitor with analog watchdog - * from sequencer channel and groups definition. - * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). - * Example: - * LL_ADC_SetAnalogWDMonitChannels( - * ADC1, LL_ADC_AWD1, - * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * @param __GROUP__ This parameter can be one of the following values: - * @arg @ref LL_ADC_GROUP_REGULAR - * @arg @ref LL_ADC_GROUP_INJECTED - * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) - * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - */ -#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ - (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ - : \ - ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ - ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ - : \ - (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ - ) - -/** - * @brief Helper macro to set the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to set the value of - * analog watchdog threshold high (on 8 bits): - * LL_ADC_SetAnalogWDThresholds - * (< ADCx param >, - * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ - ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) - -/** - * @brief Helper macro to get the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to get the value of - * analog watchdog threshold high (on 8 bits): - * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION - * (LL_ADC_RESOLUTION_8B, - * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ - ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) - -/** - * @brief Helper macro to get the ADC multimode conversion data of ADC master - * or ADC slave from raw value with both ADC conversion data concatenated. - * @note This macro is intended to be used when multimode transfer by DMA - * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). - * In this case the transferred data need to processed with this macro - * to separate the conversion data of ADC master and ADC slave. - * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_MASTER - * @arg @ref LL_ADC_MULTI_SLAVE - * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ - (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) - -/** - * @brief Helper macro to select the ADC common instance - * to which is belonging the selected ADC instance. - * @note ADC common register instance can be used for: - * - Set parameters common to several ADC instances - * - Multimode (for devices with several ADC instances) - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @param __ADCx__ ADC instance - * @retval ADC common register instance - */ -#if defined(ADC1) && defined(ADC2) && defined(ADC3) -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - (ADC123_COMMON) -#elif defined(ADC1) && defined(ADC2) -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - (ADC12_COMMON) -#else -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - (ADC1_COMMON) -#endif - -/** - * @brief Helper macro to check if all ADC instances sharing the same - * ADC common instance are disabled. - * @note This check is required by functions with setting conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @note On devices with only 1 ADC common instance, parameter of this macro - * is useless and can be ignored (parameter kept for compatibility - * with devices featuring several ADC common instances). - * @param __ADCXY_COMMON__ ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Value "0" if all ADC instances sharing the same ADC common instance - * are disabled. - * Value "1" if at least one ADC instance sharing the same ADC common instance - * is enabled. - */ -#if defined(ADC1) && defined(ADC2) && defined(ADC3) -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (LL_ADC_IsEnabled(ADC1) | \ - LL_ADC_IsEnabled(ADC2) | \ - LL_ADC_IsEnabled(ADC3) ) -#elif defined(ADC1) && defined(ADC2) -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (LL_ADC_IsEnabled(ADC1) | \ - LL_ADC_IsEnabled(ADC2) ) -#else -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - (LL_ADC_IsEnabled(ADC1)) -#endif - -/** - * @brief Helper macro to define the ADC conversion data full-scale digital - * value corresponding to the selected ADC resolution. - * @note ADC conversion data full-scale corresponds to voltage range - * determined by analog voltage references Vref+ and Vref- - * (refer to reference manual). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) - -/** - * @brief Helper macro to convert the ADC conversion data from - * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted - * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data to the requested resolution - */ -#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ - (((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \ - ) - -/** - * @brief Helper macro to calculate the voltage (unit: mVolt) - * corresponding to a ADC conversion data (unit: digital value). - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) - * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) - * (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ - __ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - ) - -/** - * @brief Helper macro to calculate analog reference voltage (Vref+) - * (unit: mVolt) from ADC conversion data of internal voltage - * reference VrefInt. - * @note Computation is using VrefInt calibration value - * stored in system memory for each device during production. - * @note This voltage depends on user board environment: voltage level - * connected to pin Vref+. - * On devices with small package, the pin Vref+ is not present - * and internally bonded to pin Vdda. - * @note On this STM32 series, calibration data of internal voltage reference - * VrefInt corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * internal voltage reference VrefInt. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) - * of internal voltage reference VrefInt (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Analog reference voltage (unit: mV) - */ -#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - ) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor calibration values - * stored in system memory for each device during production. - * @note Calculation formula: - * Temperature = ((TS_ADC_DATA - TS_CAL1) - * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) - * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * Avg_Slope = (TS_CAL2 - TS_CAL1) - * / (TS_CAL2_TEMP - TS_CAL1_TEMP) - * TS_CAL1 = equivalent TS_ADC_DATA at temperature - * TEMP_DEGC_CAL1 (calibrated in factory) - * TS_CAL2 = equivalent TS_ADC_DATA at temperature - * TEMP_DEGC_CAL2 (calibrated in factory) - * Caution: Calculation relevancy under reserve that calibration - * parameters are correct (address and data). - * To calculate temperature using temperature sensor - * datasheet typical values (generic values less, therefore - * less accurate than calibrated values), - * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this STM32 series, calibration data of temperature sensor - * corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * temperature sensor. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal - * temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature - * sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor typical values - * (refer to device datasheet). - * @note Calculation formula: - * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) - * / Avg_Slope + CALx_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * (unit: digital value) - * Avg_Slope = temperature sensor slope - * (unit: uV/Degree Celsius) - * TS_TYP_CALx_VOLT = temperature sensor digital value at - * temperature CALx_TEMP (unit: mV) - * Caution: Calculation relevancy under reserve the temperature sensor - * of the current device has characteristics in line with - * datasheet typical values. - * If temperature sensor calibration values are available on - * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), - * temperature calculation will be more accurate using - * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note ADC measurement data must correspond to a resolution of 12bits - * (full scale digital value 4095). If not the case, the data must be - * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). - * On STM32F7, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). - * On STM32F4, refer to device datasheet parameter "V25". - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ - __TEMPSENSOR_TYP_CALX_V__,\ - __TEMPSENSOR_CALX_TEMP__,\ - __VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - ((( ( \ - (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000) \ - - \ - (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000) \ - ) \ - ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (__TEMPSENSOR_CALX_TEMP__) \ - ) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management - * @{ - */ -/* Note: LL ADC functions to set DMA transfer are located into sections of */ -/* configuration of ADC instance, groups and multimode (if available): */ -/* @ref LL_ADC_REG_SetDMATransfer(), ... */ - -/** - * @brief Function to help to configure DMA transfer from ADC: retrieve the - * ADC register address from ADC instance and a list of ADC registers - * intended to be used (most commonly) with DMA transfer. - * @note These ADC registers are data registers: - * when ADC conversion data is available in ADC data registers, - * ADC generates a DMA transfer request. - * @note This macro is intended to be used with LL DMA driver, refer to - * function "LL_DMA_ConfigAddresses()". - * Example: - * LL_DMA_ConfigAddresses(DMA1, - * LL_DMA_CHANNEL_1, - * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), - * (uint32_t)&< array or variable >, - * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); - * @note For devices with several ADC: in multimode, some devices - * use a different data register outside of ADC instance scope - * (common data register). This macro manages this register difference, - * only ADC instance has to be set as parameter. - * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n - * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n - * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr - * @param ADCx ADC instance - * @param Register This parameter can be one of the following values: - * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA - * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) - * - * (1) Available on devices with several ADC instances. - * @retval ADC register address - */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) -{ - uint32_t data_reg_addr = 0U; - - if (Register == LL_ADC_DMA_REG_REGULAR_DATA) - { - /* Retrieve address of register DR */ - data_reg_addr = (uint32_t)&(ADCx->DR); - } - else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ - { - /* Retrieve address of register CDR */ - data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); - } - - return data_reg_addr; -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances - * @{ - */ - -/** - * @brief Set parameter common to several ADC: Clock source and prescaler. - * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param CommonClock This parameter can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock); -} - -/** - * @brief Get parameter common to several ADC: Clock source and prescaler. - * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 - */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE)); -} - -/** - * @brief Set parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @note Stabilization time of measurement path to internal channel: - * After enabling internal paths, before starting ADC conversion, - * a delay is required for internal voltage reference and - * temperature sensor stabilization time. - * Refer to device datasheet. - * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. - * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. - * @note ADC internal channel sampling time constraint: - * For ADC conversion of internal channels, - * a sampling time minimum value is required. - * Refer to device datasheet. - * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n - * CCR VBATE LL_ADC_SetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @arg @ref LL_ADC_PATH_INTERNAL_VBAT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal); -} - -/** - * @brief Get parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n - * CCR VBATE LL_ADC_GetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @arg @ref LL_ADC_PATH_INTERNAL_VBAT - */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Set ADC resolution. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CR1 RES LL_ADC_SetResolution - * @param ADCx ADC instance - * @param Resolution This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution); -} - -/** - * @brief Get ADC resolution. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CR1 RES LL_ADC_GetResolution - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES)); -} - -/** - * @brief Set ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment - * @param ADCx ADC instance - * @param DataAlignment This parameter can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) -{ - MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); -} - -/** - * @brief Get ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); -} - -/** - * @brief Set ADC sequencers scan mode, for all ADC groups - * (group regular, group injected). - * @note According to sequencers scan mode : - * - If disabled: ADC conversion is performed in unitary conversion - * mode (one channel converted, that defined in rank 1). - * Configuration of sequencers of all ADC groups - * (sequencer scan length, ...) is discarded: equivalent to - * scan length of 1 rank. - * - If enabled: ADC conversions are performed in sequence conversions - * mode, according to configuration of sequencers of - * each ADC group (sequencer scan length, ...). - * Refer to function @ref LL_ADC_REG_SetSequencerLength() - * and to function @ref LL_ADC_INJ_SetSequencerLength(). - * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode - * @param ADCx ADC instance - * @param ScanMode This parameter can be one of the following values: - * @arg @ref LL_ADC_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_SEQ_SCAN_ENABLE - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); -} - -/** - * @brief Get ADC sequencers scan mode, for all ADC groups - * (group regular, group injected). - * @note According to sequencers scan mode : - * - If disabled: ADC conversion is performed in unitary conversion - * mode (one channel converted, that defined in rank 1). - * Configuration of sequencers of all ADC groups - * (sequencer scan length, ...) is discarded: equivalent to - * scan length of 1 rank. - * - If enabled: ADC conversions are performed in sequence conversions - * mode, according to configuration of sequencers of - * each ADC group (sequencer scan length, ...). - * Refer to function @ref LL_ADC_REG_SetSequencerLength() - * and to function @ref LL_ADC_INJ_SetSequencerLength(). - * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_SEQ_SCAN_ENABLE - */ -__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Set ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note On this STM32 series, setting of external trigger edge is performed - * using function @ref LL_ADC_REG_StartConversionExtTrig(). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n - * CR2 EXTEN LL_ADC_REG_SetTriggerSource - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) -{ -/* Note: On this STM32 series, ADC group regular external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_REG_StartConversionExtTrig(). */ - MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); -} - -/** - * @brief Get ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note To determine whether group regular trigger source is - * internal (SW start) or external, without detail - * of which peripheral is selected as external trigger, - * (equivalent to - * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") - * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n - * CR2 EXTEN LL_ADC_REG_GetTriggerSource - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) -{ - uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); - - /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ - /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ - uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); - - /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ - /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL) - | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN) - ); -} - -/** - * @brief Get ADC group regular conversion trigger source internal (SW start) - or external. - * @note In case of group regular trigger source set to external trigger, - * to determine which peripheral is selected as external trigger, - * use function @ref LL_ADC_REG_GetTriggerSource(). - * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart - * @param ADCx ADC instance - * @retval Value "0" if trigger source external trigger - * Value "1" if trigger source SW start. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN)); -} - -/** - * @brief Get ADC group regular conversion trigger polarity. - * @note Applicable only for trigger source set to external trigger. - * @note On this STM32 series, setting of external trigger edge is performed - * using function @ref LL_ADC_REG_StartConversionExtTrig(). - * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING - * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN)); -} - - -/** - * @brief Set ADC group regular sequencer length and scan direction. - * @note Description of ADC group regular sequencer features: - * - For devices with sequencer fully configurable - * (function "LL_ADC_REG_SetSequencerRanks()" available): - * sequencer length and each rank affectation to a channel - * are configurable. - * This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerRanks()". - * - For devices with sequencer not fully configurable - * (function "LL_ADC_REG_SetSequencerChannels()" available): - * sequencer length and each rank affectation to a channel - * are defined by channel number. - * This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence is - * defined by number of channels set in the sequence, - * rank of each channel is fixed by channel HW number. - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from lowest channel number to - * highest channel number). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerChannels()". - * @note On this STM32 series, group regular sequencer configuration - * is conditioned to ADC instance sequencer mode. - * If ADC instance sequencer mode is disabled, sequencers of - * all groups (group regular, group injected) can be configured - * but their execution is disabled (limited to rank 1). - * Refer to function @ref LL_ADC_SetSequencersScanMode(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength - * @param ADCx ADC instance - * @param SequencerNbRanks This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) -{ - MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); -} - -/** - * @brief Get ADC group regular sequencer length and scan direction. - * @note Description of ADC group regular sequencer features: - * - For devices with sequencer fully configurable - * (function "LL_ADC_REG_SetSequencerRanks()" available): - * sequencer length and each rank affectation to a channel - * are configurable. - * This function retrieves: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerRanks()". - * - For devices with sequencer not fully configurable - * (function "LL_ADC_REG_SetSequencerChannels()" available): - * sequencer length and each rank affectation to a channel - * are defined by channel number. - * This function retrieves: - * - Sequence length: Number of ranks in the scan sequence is - * defined by number of channels set in the sequence, - * rank of each channel is fixed by channel HW number. - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from lowest channel number to - * highest channel number). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerChannels()". - * @note On this STM32 series, group regular sequencer configuration - * is conditioned to ADC instance sequencer mode. - * If ADC instance sequencer mode is disabled, sequencers of - * all groups (group regular, group injected) can be configured - * but their execution is disabled (limited to rank 1). - * Refer to function @ref LL_ADC_SetSequencersScanMode(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); -} - -/** - * @brief Set ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @note It is not possible to enable both ADC auto-injected mode - * and ADC group regular sequencer discontinuous mode. - * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n - * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont - * @param ADCx ADC instance - * @param SeqDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); -} - -/** - * @brief Get ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n - * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS - * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); -} - -/** - * @brief Set ADC group regular sequence: channel on the selected - * scan sequence rank. - * @note This function performs configuration of: - * - Channels ordering into each rank of scan sequence: - * whatever channel can be placed into whatever rank. - * @note On this STM32 series, ADC group regular sequencer is - * fully configurable: sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n - * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n - * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n - * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_RANK_1 - * @arg @ref LL_ADC_REG_RANK_2 - * @arg @ref LL_ADC_REG_RANK_3 - * @arg @ref LL_ADC_REG_RANK_4 - * @arg @ref LL_ADC_REG_RANK_5 - * @arg @ref LL_ADC_REG_RANK_6 - * @arg @ref LL_ADC_REG_RANK_7 - * @arg @ref LL_ADC_REG_RANK_8 - * @arg @ref LL_ADC_REG_RANK_9 - * @arg @ref LL_ADC_REG_RANK_10 - * @arg @ref LL_ADC_REG_RANK_11 - * @arg @ref LL_ADC_REG_RANK_12 - * @arg @ref LL_ADC_REG_RANK_13 - * @arg @ref LL_ADC_REG_RANK_14 - * @arg @ref LL_ADC_REG_RANK_15 - * @arg @ref LL_ADC_REG_RANK_16 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) -{ - /* Set bits with content of parameter "Channel" with bits position */ - /* in register and register position depending on parameter "Rank". */ - /* Parameters "Rank" and "Channel" are used with masks because containing */ - /* other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); -} - -/** - * @brief Get ADC group regular sequence: channel on the selected - * scan sequence rank. - * @note On this STM32 series, ADC group regular sequencer is - * fully configurable: sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n - * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n - * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n - * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_RANK_1 - * @arg @ref LL_ADC_REG_RANK_2 - * @arg @ref LL_ADC_REG_RANK_3 - * @arg @ref LL_ADC_REG_RANK_4 - * @arg @ref LL_ADC_REG_RANK_5 - * @arg @ref LL_ADC_REG_RANK_6 - * @arg @ref LL_ADC_REG_RANK_7 - * @arg @ref LL_ADC_REG_RANK_8 - * @arg @ref LL_ADC_REG_RANK_9 - * @arg @ref LL_ADC_REG_RANK_10 - * @arg @ref LL_ADC_REG_RANK_11 - * @arg @ref LL_ADC_REG_RANK_12 - * @arg @ref LL_ADC_REG_RANK_13 - * @arg @ref LL_ADC_REG_RANK_14 - * @arg @ref LL_ADC_REG_RANK_15 - * @arg @ref LL_ADC_REG_RANK_16 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - - return (uint32_t) (READ_BIT(*preg, - ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) - ); -} - -/** - * @brief Set ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode - * @param ADCx ADC instance - * @param Continuous This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) -{ - MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); -} - -/** - * @brief Get ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); -} - -/** - * @brief Set ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note For devices with several ADC instances: ADC multimode DMA - * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n - * CR2 DDS LL_ADC_REG_SetDMATransfer - * @param ADCx ADC instance - * @param DMATransfer This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) -{ - MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer); -} - -/** - * @brief Get ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note For devices with several ADC instances: ADC multimode DMA - * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n - * CR2 DDS LL_ADC_REG_GetDMATransfer - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS)); -} - -/** - * @brief Specify which ADC flag between EOC (end of unitary conversion) - * or EOS (end of sequence conversions) is used to indicate - * the end of conversion. - * @note This feature is aimed to be set when using ADC with - * programming model by polling or interruption - * (programming model by DMA usually uses DMA interruptions - * to indicate end of conversion and data transfer). - * @note For ADC group injected, end of conversion (flag&IT) is raised - * only at the end of the sequence. - * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion - * @param ADCx ADC instance - * @param EocSelection This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV - * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection) -{ - MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection); -} - -/** - * @brief Get which ADC flag between EOC (end of unitary conversion) - * or EOS (end of sequence conversions) is used to indicate - * the end of conversion. - * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV - * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected - * @{ - */ - -/** - * @brief Set ADC group injected conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note On this STM32 series, setting of external trigger edge is performed - * using function @ref LL_ADC_INJ_StartConversionExtTrig(). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n - * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) -{ -/* Note: On this STM32 series, ADC group injected external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ - MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); -} - -/** - * @brief Get ADC group injected conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note To determine whether group injected trigger source is - * internal (SW start) or external, without detail - * of which peripheral is selected as external trigger, - * (equivalent to - * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") - * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n - * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 - * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) -{ - uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); - - /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ - /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ - uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); - - /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ - /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL) - | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN) - ); -} - -/** - * @brief Get ADC group injected conversion trigger source internal (SW start) - or external - * @note In case of group injected trigger source set to external trigger, - * to determine which peripheral is selected as external trigger, - * use function @ref LL_ADC_INJ_GetTriggerSource. - * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart - * @param ADCx ADC instance - * @retval Value "0" if trigger source external trigger - * Value "1" if trigger source SW start. - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN)); -} - -/** - * @brief Get ADC group injected conversion trigger polarity. - * Applicable only for trigger source set to external trigger. - * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING - * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN)); -} - -/** - * @brief Set ADC group injected sequencer length and scan direction. - * @note This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * @note On this STM32 series, group injected sequencer configuration - * is conditioned to ADC instance sequencer mode. - * If ADC instance sequencer mode is disabled, sequencers of - * all groups (group regular, group injected) can be configured - * but their execution is disabled (limited to rank 1). - * Refer to function @ref LL_ADC_SetSequencersScanMode(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength - * @param ADCx ADC instance - * @param SequencerNbRanks This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) -{ - MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); -} - -/** - * @brief Get ADC group injected sequencer length and scan direction. - * @note This function retrieves: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * @note On this STM32 series, group injected sequencer configuration - * is conditioned to ADC instance sequencer mode. - * If ADC instance sequencer mode is disabled, sequencers of - * all groups (group regular, group injected) can be configured - * but their execution is disabled (limited to rank 1). - * Refer to function @ref LL_ADC_SetSequencersScanMode(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); -} - -/** - * @brief Set ADC group injected sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @note It is not possible to enable both ADC group injected - * auto-injected mode and sequencer discontinuous mode. - * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont - * @param ADCx ADC instance - * @param SeqDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); -} - -/** - * @brief Get ADC group injected sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); -} - -/** - * @brief Set ADC group injected sequence: channel on the selected - * sequence rank. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) -{ - /* Set bits with content of parameter "Channel" with bits position */ - /* in register depending on parameter "Rank". */ - /* Parameters "Rank" and "Channel" are used with masks because containing */ - /* other bits reserved for other purpose. */ - uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; - - MODIFY_REG(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), - (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); -} - -/** - * @brief Get ADC group injected sequence: channel on the selected - * sequence rank. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n - * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) -{ - uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; - - return (uint32_t)(READ_BIT(ADCx->JSQR, - ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) - >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) - ); -} - -/** - * @brief Set ADC group injected conversion trigger: - * independent or from ADC group regular. - * @note This mode can be used to extend number of data registers - * updated after one ADC conversion trigger and with data - * permanently kept (not erased by successive conversions of scan of - * ADC sequencer ranks), up to 5 data registers: - * 1 data register on ADC group regular, 4 data registers - * on ADC group injected. - * @note If ADC group injected injected trigger source is set to an - * external trigger, this feature must be must be set to - * independent trigger. - * ADC group injected automatic trigger is compliant only with - * group injected trigger source set to SW start, without any - * further action on ADC group injected conversion start or stop: - * in this case, ADC group injected is controlled only - * from ADC group regular. - * @note It is not possible to enable both ADC group injected - * auto-injected mode and sequencer discontinuous mode. - * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto - * @param ADCx ADC instance - * @param TrigAuto This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT - * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) -{ - MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); -} - -/** - * @brief Get ADC group injected conversion trigger: - * independent or from ADC group regular. - * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT - * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); -} - -/** - * @brief Set ADC group injected offset. - * @note It sets: - * - ADC group injected rank to which the offset programmed - * will be applied - * - Offset level (offset to be subtracted from the raw - * converted data). - * Caution: Offset format is dependent to ADC resolution: - * offset has to be left-aligned on bit 11, the LSB (right bits) - * are set to 0. - * @note Offset cannot be enabled or disabled. - * To emulate offset disabled, set an offset value equal to 0. - * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n - * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n - * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n - * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - ADC_JOFR1_JOFFSET1, - OffsetLevel); -} - -/** - * @brief Get ADC group injected offset. - * @note It gives offset level (offset to be subtracted from the raw converted data). - * Caution: Offset format is dependent to ADC resolution: - * offset has to be left-aligned on bit 11, the LSB (right bits) - * are set to 0. - * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n - * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n - * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n - * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - ADC_JOFR1_JOFFSET1) - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels - * @{ - */ - -/** - * @brief Set sampling time of the selected ADC channel - * Unit: ADC clock cycles. - * @note On this device, sampling time is on channel scope: independently - * of channel mapped on ADC group regular or injected. - * @note In case of internal channel (VrefInt, TempSensor, ...) to be - * converted: - * sampling time constraints must be respected (sampling time can be - * adjusted in function of ADC clock frequency and sampling time - * setting). - * Refer to device datasheet for timings values (parameters TS_vrefint, - * TS_temp, ...). - * @note Conversion time is the addition of sampling time and processing time. - * Refer to reference manual for ADC processing time of - * this STM32 series. - * @note In case of ADC conversion of internal channel (VrefInt, - * temperature sensor, ...), a sampling time minimum value - * is required. - * Refer to device datasheet. - * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n - * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n - * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime - * @param ADCx ADC instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @param SamplingTime This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) -{ - /* Set bits with content of parameter "SamplingTime" with bits position */ - /* in register and register position depending on parameter "Channel". */ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - - MODIFY_REG(*preg, - ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), - SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); -} - -/** - * @brief Get sampling time of the selected ADC channel - * Unit: ADC clock cycles. - * @note On this device, sampling time is on channel scope: independently - * of channel mapped on ADC group regular or injected. - * @note Conversion time is the addition of sampling time and processing time. - * Refer to reference manual for ADC processing time of - * this STM32 series. - * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n - * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n - * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime - * @param ADCx ADC instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) - * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES - * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES - */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) - >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog - * @{ - */ - -/** - * @brief Set ADC analog watchdog monitored channels: - * a single channel or all channels, - * on ADC groups regular and-or injected. - * @note Once monitored channels are selected, analog watchdog - * is enabled. - * @note In case of need to define a single channel to monitor - * with analog watchdog from sequencer channel definition, - * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 series, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n - * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n - * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels - * @param ADCx ADC instance - * @param AWDChannelGroup This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) - * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) - * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) - * - * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n - * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) -{ - MODIFY_REG(ADCx->CR1, - (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), - AWDChannelGroup); -} - -/** - * @brief Get ADC analog watchdog monitored channel. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Applicable only when the analog watchdog is set to monitor - * one channel. - * @note On this STM32 series, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n - * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n - * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG - * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ - */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); -} - -/** - * @brief Set ADC analog watchdog threshold value of threshold - * high or low. - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 series, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC groups regular and-or injected. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n - * LTR LT LL_ADC_SetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); - - MODIFY_REG(*preg, - ADC_HTR_HT, - AWDThresholdValue); -} - -/** - * @brief Get ADC analog watchdog threshold value of threshold high or - * threshold low. - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). - * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n - * LTR LT LL_ADC_GetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF -*/ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); - - return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode - * @{ - */ - -/** - * @brief Set ADC multimode configuration to operate in independent mode - * or multimode (for devices with several ADC instances). - * @note If multimode configuration: the selected ADC instance is - * either master or slave depending on hardware. - * Refer to reference manual. - * @rmtoll CCR MULTI LL_ADC_SetMultimode - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param Multimode This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_INDEPENDENT - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL - * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM - * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM - * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT - * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT - * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT - * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL - * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode); -} - -/** - * @brief Get ADC multimode configuration to operate in independent mode - * or multimode (for devices with several ADC instances). - * @note If multimode configuration: the selected ADC instance is - * either master or slave depending on hardware. - * Refer to reference manual. - * @rmtoll CCR MULTI LL_ADC_GetMultimode - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_MULTI_INDEPENDENT - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL - * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT - * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM - * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT - * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM - * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM - * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT - * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT - * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT - * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL - * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN - */ -__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI)); -} - -/** - * @brief Set ADC multimode conversion data transfer: no transfer - * or transfer by DMA. - * @note If ADC multimode transfer by DMA is not selected: - * each ADC uses its own DMA channel, with its individual - * DMA transfer settings. - * If ADC multimode transfer by DMA is selected: - * One DMA channel is used for both ADC (DMA of ADC master) - * Specifies the DMA requests mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note How to retrieve multimode conversion data: - * Whatever multimode transfer by DMA setting: using function - * @ref LL_ADC_REG_ReadMultiConversionData32(). - * If ADC multimode transfer by DMA is selected: conversion data - * is a raw data with ADC master and slave concatenated. - * A macro is available to get the conversion data of - * ADC master or ADC slave: see helper macro - * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n - * CCR DDS LL_ADC_SetMultiDMATransfer - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param MultiDMATransfer This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer); -} - -/** - * @brief Get ADC multimode conversion data transfer: no transfer - * or transfer by DMA. - * @note If ADC multimode transfer by DMA is not selected: - * each ADC uses its own DMA channel, with its individual - * DMA transfer settings. - * If ADC multimode transfer by DMA is selected: - * One DMA channel is used for both ADC (DMA of ADC master) - * Specifies the DMA requests mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note How to retrieve multimode conversion data: - * Whatever multimode transfer by DMA setting: using function - * @ref LL_ADC_REG_ReadMultiConversionData32(). - * If ADC multimode transfer by DMA is selected: conversion data - * is a raw data with ADC master and slave concatenated. - * A macro is available to get the conversion data of - * ADC master or ADC slave: see helper macro - * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n - * CCR DDS LL_ADC_GetMultiDMATransfer - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 - * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 - * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 - */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS)); -} - -/** - * @brief Set ADC multimode delay between 2 sampling phases. - * @note The sampling delay range depends on ADC resolution: - * - ADC resolution 12 bits can have maximum delay of 12 cycles. - * - ADC resolution 10 bits can have maximum delay of 10 cycles. - * - ADC resolution 8 bits can have maximum delay of 8 cycles. - * - ADC resolution 6 bits can have maximum delay of 6 cycles. - * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param MultiTwoSamplingDelay This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); -} - -/** - * @brief Get ADC multimode delay between 2 sampling phases. - * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES - * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES - */ -__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); -} - -/** - * @} - */ -/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Enable the selected ADC instance. - * @note On this STM32 series, after ADC enable, a delay for - * ADC internal analog stabilization is required before performing a - * ADC conversion start. - * Refer to device datasheet, parameter tSTAB. - * @rmtoll CR2 ADON LL_ADC_Enable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR2, ADC_CR2_ADON); -} - -/** - * @brief Disable the selected ADC instance. - * @rmtoll CR2 ADON LL_ADC_Disable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); -} - -/** - * @brief Get the selected ADC instance enable state. - * @rmtoll CR2 ADON LL_ADC_IsEnabled - * @param ADCx ADC instance - * @retval 0: ADC is disabled, 1: ADC is enabled. - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Start ADC group regular conversion. - * @note On this STM32 series, this function is relevant only for - * internal trigger (SW start), not for external trigger: - * - If ADC trigger has been set to software start, ADC conversion - * starts immediately. - * - If ADC trigger has been set to external trigger, ADC conversion - * start must be performed using function - * @ref LL_ADC_REG_StartConversionExtTrig(). - * (if external trigger edge would have been set during ADC other - * settings, ADC conversion would start at trigger event - * as soon as ADC is enabled). - * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR2, ADC_CR2_SWSTART); -} - -/** - * @brief Start ADC group regular conversion from external trigger. - * @note ADC conversion will start at next trigger event (on the selected - * trigger edge) following the ADC start conversion command. - * @note On this STM32 series, this function is relevant for - * ADC conversion start from external trigger. - * If internal trigger (SW start) is needed, perform ADC conversion - * start using function @ref LL_ADC_REG_StartConversionSWStart(). - * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING - * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) -{ - SET_BIT(ADCx->CR2, ExternalTriggerEdge); -} - -/** - * @brief Stop ADC group regular conversion from external trigger. - * @note No more ADC conversion will start at next trigger event - * following the ADC stop conversion command. - * If a conversion is on-going, it will be completed. - * @note On this STM32 series, there is no specific command - * to stop a conversion on-going or to stop ADC converting - * in continuous mode. These actions can be performed - * using function @ref LL_ADC_Disable(). - * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 12 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 10 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0x3FF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 8 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) -{ - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 6 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0x3F - */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) -{ - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL); -} - -/** - * @brief Get ADC multimode conversion data of ADC master, ADC slave - * or raw data with ADC master and slave concatenated. - * @note If raw data with ADC master and slave concatenated is retrieved, - * a macro is available to get the conversion data of - * ADC master or ADC slave: see helper macro - * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). - * (however this macro is mainly intended for multimode - * transfer by DMA, because this function can do the same - * by getting multimode conversion data of ADC master or ADC slave - * separately). - * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n - * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ConversionData This parameter can be one of the following values: - * @arg @ref LL_ADC_MULTI_MASTER - * @arg @ref LL_ADC_MULTI_SLAVE - * @arg @ref LL_ADC_MULTI_MASTER_SLAVE - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, - ADC_DR_ADC2DATA) - >> POSITION_VAL(ConversionData) - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected - * @{ - */ - -/** - * @brief Start ADC group injected conversion. - * @note On this STM32 series, this function is relevant only for - * internal trigger (SW start), not for external trigger: - * - If ADC trigger has been set to software start, ADC conversion - * starts immediately. - * - If ADC trigger has been set to external trigger, ADC conversion - * start must be performed using function - * @ref LL_ADC_INJ_StartConversionExtTrig(). - * (if external trigger edge would have been set during ADC other - * settings, ADC conversion would start at trigger event - * as soon as ADC is enabled). - * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART); -} - -/** - * @brief Start ADC group injected conversion from external trigger. - * @note ADC conversion will start at next trigger event (on the selected - * trigger edge) following the ADC start conversion command. - * @note On this STM32 series, this function is relevant for - * ADC conversion start from external trigger. - * If internal trigger (SW start) is needed, perform ADC conversion - * start using function @ref LL_ADC_INJ_StartConversionSWStart(). - * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING - * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING - * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) -{ - SET_BIT(ADCx->CR2, ExternalTriggerEdge); -} - -/** - * @brief Stop ADC group injected conversion from external trigger. - * @note No more ADC conversion will start at next trigger event - * following the ADC stop conversion command. - * If a conversion is on-going, it will be completed. - * @note On this STM32 series, there is no specific command - * to stop a conversion on-going or to stop ADC converting - * in continuous mode. These actions can be performed - * using function @ref LL_ADC_Disable(). - * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - - return (uint32_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 12 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - - return (uint16_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 10 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x000 and Max_Data=0x3FF - */ -__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - - return (uint16_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 8 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - - return (uint8_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) & 0x000000FFUL - ); -} - -/** - * @brief Get ADC group injected conversion data, range fit for - * ADC resolution 6 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_INJ_ReadConversionData32. - * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n - * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n - * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n - * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_INJ_RANK_1 - * @arg @ref LL_ADC_INJ_RANK_2 - * @arg @ref LL_ADC_INJ_RANK_3 - * @arg @ref LL_ADC_INJ_RANK_4 - * @retval Value between Min_Data=0x00 and Max_Data=0x3F - */ -__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) -{ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - - return (uint8_t)(READ_BIT(*preg, - ADC_JDR1_JDATA) & 0x000000FFUL - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management - * @{ - */ - -/** - * @brief Get flag ADC group regular end of unitary conversion - * or end of sequence conversions, depending on - * ADC configuration. - * @note To configure flag of end of conversion, - * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). - * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); -} - -/** - * @brief Get flag ADC group regular overrun. - * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); -} - - -/** - * @brief Get flag ADC group injected end of sequence conversions. - * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 series, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); -} - -/** - * @brief Get flag ADC analog watchdog 1 flag - * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); -} - -/** - * @brief Clear flag ADC group regular end of unitary conversion - * or end of sequence conversions, depending on - * ADC configuration. - * @note To configure flag of end of conversion, - * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). - * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS); -} - -/** - * @brief Clear flag ADC group regular overrun. - * @rmtoll SR OVR LL_ADC_ClearFlag_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR); -} - - -/** - * @brief Clear flag ADC group injected end of sequence conversions. - * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 series, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); -} - -/** - * @brief Clear flag ADC analog watchdog 1. - * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); -} - -/** - * @brief Get flag multimode ADC group regular end of unitary conversion - * or end of sequence conversions, depending on - * ADC configuration, of the ADC master. - * @note To configure flag of end of conversion, - * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). - * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); -} - -/** - * @brief Get flag multimode ADC group regular end of unitary conversion - * or end of sequence conversions, depending on - * ADC configuration, of the ADC slave 1. - * @note To configure flag of end of conversion, - * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). - * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1)); -} - -/** - * @brief Get flag multimode ADC group regular end of unitary conversion - * or end of sequence conversions, depending on - * ADC configuration, of the ADC slave 2. - * @note To configure flag of end of conversion, - * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). - * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2)); -} -/** - * @brief Get flag multimode ADC group regular overrun of the ADC master. - * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); -} - -/** - * @brief Get flag multimode ADC group regular overrun of the ADC slave 1. - * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1)); -} - -/** - * @brief Get flag multimode ADC group regular overrun of the ADC slave 2. - * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2)); -} - - -/** - * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. - * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Note: on this STM32 series, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1)); -} - -/** - * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1. - * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Note: on this STM32 series, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2)); -} - -/** - * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2. - * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Note: on this STM32 series, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3)); -} - -/** - * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. - * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); -} - -/** - * @brief Get flag multimode analog watchdog 1 of the ADC slave 1. - * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1)); -} - -/** - * @brief Get flag multimode analog watchdog 1 of the ADC slave 2. - * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1 - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); -} - - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_IT_Management ADC IT management - * @{ - */ - -/** - * @brief Enable interruption ADC group regular end of unitary conversion - * or end of sequence conversions, depending on - * ADC configuration. - * @note To configure flag of end of conversion, - * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). - * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS); -} - -/** - * @brief Enable ADC group regular interruption overrun. - * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR1, LL_ADC_IT_OVR); -} - - -/** - * @brief Enable interruption ADC group injected end of sequence conversions. - * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 series, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); -} - -/** - * @brief Enable interruption ADC analog watchdog 1. - * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); -} - -/** - * @brief Disable interruption ADC group regular end of unitary conversion - * or end of sequence conversions, depending on - * ADC configuration. - * @note To configure flag of end of conversion, - * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). - * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS); -} - -/** - * @brief Disable interruption ADC group regular overrun. - * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR); -} - - -/** - * @brief Disable interruption ADC group injected end of sequence conversions. - * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 series, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); -} - -/** - * @brief Disable interruption ADC analog watchdog 1. - * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); -} - -/** - * @brief Get state of interruption ADC group regular end of unitary conversion - * or end of sequence conversions, depending on - * ADC configuration. - * @note To configure flag of end of conversion, - * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). - * (0: interrupt disabled, 1: interrupt enabled) - * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS)); -} - -/** - * @brief Get state of interruption ADC group regular overrun - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); -} - - -/** - * @brief Get state of interruption ADC group injected end of sequence conversions - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) -{ - /* Note: on this STM32 series, there is no flag ADC group injected */ - /* end of unitary conversion. */ - /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ - /* in other STM32 families). */ - return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); -} - -/** - * @brief Get state of interruption ADC analog watchdog 1 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -/* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); - -/* De-initialization of ADC instance, ADC group regular and ADC group injected */ -/* (availability of ADC group injected depends on STM32 families) */ -ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); - -/* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); - -/* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); - -/* Initialization of some features of ADC instance and ADC group injected */ -ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); -void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ADC1 || ADC2 || ADC3 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_ADC_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_adc.h + * @author MCD Application Team + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_ADC_H +#define __STM32F7xx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) || defined (ADC3) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group regular sequencer configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SQR1_REGOFFSET 0x00000000U +#define ADC_SQR2_REGOFFSET 0x00000100U +#define ADC_SQR3_REGOFFSET 0x00000200U +#define ADC_SQR4_REGOFFSET 0x00000300U + +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ + +/* Internal mask for ADC group injected sequencer: */ +/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ +/* - data register offset */ +/* - offset register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group injected data register */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JDR1_REGOFFSET 0x00000000U +#define ADC_JDR2_REGOFFSET 0x00000100U +#define ADC_JDR3_REGOFFSET 0x00000200U +#define ADC_JDR4_REGOFFSET 0x00000300U + +/* Internal register offset for ADC group injected offset configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JOFR1_REGOFFSET 0x00000000U +#define ADC_JOFR2_REGOFFSET 0x00001000U +#define ADC_JOFR3_REGOFFSET 0x00002000U +#define ADC_JOFR4_REGOFFSET 0x00003000U + +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) +#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Internal mask for ADC group regular trigger: */ +/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ +/* - regular trigger source */ +/* - regular trigger edge */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \ + ((ADC_CR2_EXTSEL) >> (4U * 1U)) | \ + ((ADC_CR2_EXTSEL) >> (4U * 2U)) | \ + ((ADC_CR2_EXTSEL) >> (4U * 3U))) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) + +/* Definition of ADC group regular trigger bits information. */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ + + + +/* Internal mask for ADC group injected trigger: */ +/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ +/* - injected trigger source */ +/* - injected trigger edge */ +#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \ + ((ADC_CR2_JEXTSEL) >> (4U * 1U)) | \ + ((ADC_CR2_JEXTSEL) >> (4U * 2U)) | \ + ((ADC_CR2_JEXTSEL) >> (4U * 3U))) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 1U)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 2U)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4U * 3U))) + +/* Definition of ADC group injected trigger bits information. */ +#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ +#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +/* - channel sampling time defined by SMPRx register offset */ +/* and SMPx bits positions into SMPRx register */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ +#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) + +/* Internal register offset for ADC channel sampling time configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SMPR1_REGOFFSET 0x00000000U +#define ADC_SMPR2_REGOFFSET 0x02000000U +#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) + +#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER 0x00000000U +#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) +#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) +#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) + +/* Definition of channels sampling time information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ +#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ +#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ +#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ +#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ +#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ +#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ +#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ +#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ +#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ +#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ +#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ +#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ +#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ +#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ +#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ +#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ +#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ +#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 families)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC groups regular and-or injected). */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET 0x00000000U + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U +#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) + +/* ADC registers bits positions */ +#define ADC_CR1_RES_BITOFFSET_POS (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ +#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_ADDR VREFINT_CAL_ADDR_CMSIS /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +/* Temperature sensor */ +#define TEMPSENSOR_CAL1_ADDR TEMPSENSOR_CAL1_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR TEMPSENSOR_CAL2_ADDR_CMSIS /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param __BITS__ Bits in register 32 bits + * @param __MASK__ Mask in register 32 bits + * @retval Bits in register 32 bits + */ +#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ + (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ + + uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). + This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ + + uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. + This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ + + uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. + This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ + +} LL_ADC_CommonInitTypeDef; + +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 families). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t Resolution; /*!< Set ADC resolution. + This parameter can be a value of @ref ADC_LL_EC_RESOLUTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ + + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + + uint32_t SequencersScanMode; /*!< Set ADC scan selection. + This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 series, setting of external trigger edge is performed + using function @ref LL_ADC_REG_StartConversionExtTrig(). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE + @note On this STM32 series, setting of external trigger edge is performed + using function @ref LL_ADC_INJ_StartConversionExtTrig(). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE + @note This parameter has an effect only if group injected sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ + + uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO + Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ + +} LL_ADC_INJ_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ +#define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ +#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ +#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ +#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ +#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ +#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ +#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ +#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */ +#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ +#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ +#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */ +#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection + * @{ + */ +#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ +#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE 0x00000000U /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_TRGO (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CR2_EXTSEL_3 |ADC_CR2_EXTSEL_2| ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode +* @{ +*/ +#define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions) + * @{ + */ +#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000U /*!< ADC flag EOC (end of unitary conversion) selected */ +#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ +#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ +#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ +#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ +#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ +#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ +#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ +#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ +#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source + * @{ + */ +#define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000U /*!< ADC group injected conversion trigger internal: SW start. */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge + * @{ + */ +#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ +#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ +#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode +* @{ +*/ +#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ +#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ +/** + * @} + */ + + +/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length + * @{ + */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @{ + */ +#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */ +#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */ +#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */ +#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000U /*!< Sampling time 3 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ +#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ +#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ +#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ +#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ +#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ +#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ +#if defined(ADC3) +#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */ +#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer + * @{ + */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000U /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases + * @{ + */ +#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000U /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/ +#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave + * @{ + */ +#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ +#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ +#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ +/** + * @} + */ + + + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC IP HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 series: */ +/* - ADC enable time: maximum delay is 2us */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for internal voltage reference stabilization time. */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) <= 9U) \ + ? ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + : \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + ) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1. + * (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ + ) +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @arg @ref LL_ADC_GROUP_INJECTED + * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + ) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC123_COMMON) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC12_COMMON) +#else +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC1_COMMON) +#endif + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) | \ + LL_ADC_IsEnabled(ADC3) ) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) +#else +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1)) +#endif + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ + (((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)) \ + ) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + ) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + ) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 series, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). + * On STM32F7, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). + * On STM32F4, refer to device datasheet parameter "V25". + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((( ( \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000) \ + - \ + (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000) \ + ) \ + ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (__TEMPSENSOR_CALX_TEMP__) \ + ) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) + * + * (1) Available on devices with several ADC instances. + * @retval ADC register address + */ +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + uint32_t data_reg_addr = 0U; + + if (Register == LL_ADC_DMA_REG_REGULAR_DATA) + { + /* Retrieve address of register DR */ + data_reg_addr = (uint32_t)&(ADCx->DR); + } + else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ + { + /* Retrieve address of register CDR */ + data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param CommonClock This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock); +} + +/** + * @brief Get parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE)); +} + +/** + * @brief Set parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n + * CCR VBATE LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n + * CCR VBATE LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR1 RES LL_ADC_SetResolution + * @param ADCx ADC instance + * @param Resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR1 RES LL_ADC_GetResolution + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES)); +} + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); +} + +/** + * @brief Set ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode + * @param ADCx ADC instance + * @param ScanMode This parameter can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); +} + +/** + * @brief Get ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 series, setting of external trigger edge is performed + * using function @ref LL_ADC_REG_StartConversionExtTrig(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n + * CR2 EXTEN LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 series, ADC group regular external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_REG_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n + * CR2 EXTEN LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +{ + uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ + uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); + + /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN)); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @note On this STM32 series, setting of external trigger edge is performed + * using function @ref LL_ADC_REG_StartConversionExtTrig(). + * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN)); +} + + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 series, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 series, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note It is not possible to enable both ADC auto-injected mode + * and ADC group regular sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register and register position depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + return (uint32_t) (READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note For devices with several ADC instances: ADC multimode DMA + * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n + * CR2 DDS LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note For devices with several ADC instances: ADC multimode DMA + * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n + * CR2 DDS LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS)); +} + +/** + * @brief Specify which ADC flag between EOC (end of unitary conversion) + * or EOS (end of sequence conversions) is used to indicate + * the end of conversion. + * @note This feature is aimed to be set when using ADC with + * programming model by polling or interruption + * (programming model by DMA usually uses DMA interruptions + * to indicate end of conversion and data transfer). + * @note For ADC group injected, end of conversion (flag&IT) is raised + * only at the end of the sequence. + * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion + * @param ADCx ADC instance + * @param EocSelection This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV + * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection); +} + +/** + * @brief Get which ADC flag between EOC (end of unitary conversion) + * or EOS (end of sequence conversions) is used to indicate + * the end of conversion. + * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV + * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Set ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 series, setting of external trigger edge is performed + * using function @ref LL_ADC_INJ_StartConversionExtTrig(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n + * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 series, ADC group injected external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); +} + +/** + * @brief Get ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group injected trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") + * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n + * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +{ + uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ + uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U)); + + /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL) + | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN) + ); +} + +/** + * @brief Get ADC group injected conversion trigger source internal (SW start) + or external + * @note In case of group injected trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_INJ_GetTriggerSource. + * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN)); +} + +/** + * @brief Get ADC group injected conversion trigger polarity. + * Applicable only for trigger source set to external trigger. + * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN)); +} + +/** + * @brief Set ADC group injected sequencer length and scan direction. + * @note This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 series, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); +} + +/** + * @brief Get ADC group injected sequencer length and scan direction. + * @note This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 series, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); +} + +/** + * @brief Set ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); +} + +/** + * @brief Set ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; + + MODIFY_REG(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))); +} + +/** + * @brief Get ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U; + + return (uint32_t)(READ_BIT(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))) + >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))) + ); +} + +/** + * @brief Set ADC group injected conversion trigger: + * independent or from ADC group regular. + * @note This mode can be used to extend number of data registers + * updated after one ADC conversion trigger and with data + * permanently kept (not erased by successive conversions of scan of + * ADC sequencer ranks), up to 5 data registers: + * 1 data register on ADC group regular, 4 data registers + * on ADC group injected. + * @note If ADC group injected injected trigger source is set to an + * external trigger, this feature must be must be set to + * independent trigger. + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only + * from ADC group regular. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto + * @param ADCx ADC instance + * @param TrigAuto This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); +} + +/** + * @brief Get ADC group injected conversion trigger: + * independent or from ADC group regular. + * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); +} + +/** + * @brief Set ADC group injected offset. + * @note It sets: + * - ADC group injected rank to which the offset programmed + * will be applied + * - Offset level (offset to be subtracted from the raw + * converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @note Offset cannot be enabled or disabled. + * To emulate offset disabled, set an offset value equal to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_JOFR1_JOFFSET1, + OffsetLevel); +} + +/** + * @brief Get ADC group injected offset. + * @note It gives offset level (offset to be subtracted from the raw converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JOFR1_JOFFSET1) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) +{ + /* Set bits with content of parameter "SamplingTime" with bits position */ + /* in register and register position depending on parameter "Channel". */ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), + SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) + >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel or all channels, + * on ADC groups regular and-or injected. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) + * + * (1) On STM32F7, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) +{ + MODIFY_REG(ADCx->CR1, + (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), + AWDChannelGroup); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n + * LTR LT LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + MODIFY_REG(*preg, + ADC_HTR_HT, + AWDThresholdValue); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high or + * threshold low. + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n + * LTR LT LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF +*/ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode + * @{ + */ + +/** + * @brief Set ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CCR MULTI LL_ADC_SetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param Multimode This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode); +} + +/** + * @brief Get ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CCR MULTI LL_ADC_GetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI)); +} + +/** + * @brief Set ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n + * CCR DDS LL_ADC_SetMultiDMATransfer + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiDMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer); +} + +/** + * @brief Get ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n + * CCR DDS LL_ADC_GetMultiDMATransfer + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS)); +} + +/** + * @brief Set ADC multimode delay between 2 sampling phases. + * @note The sampling delay range depends on ADC resolution: + * - ADC resolution 12 bits can have maximum delay of 12 cycles. + * - ADC resolution 10 bits can have maximum delay of 10 cycles. + * - ADC resolution 8 bits can have maximum delay of 8 cycles. + * - ADC resolution 6 bits can have maximum delay of 6 cycles. + * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiTwoSamplingDelay This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); +} + +/** + * @brief Get ADC multimode delay between 2 sampling phases. + * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); +} + +/** + * @} + */ +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 series, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @rmtoll CR2 ADON LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Disable the selected ADC instance. + * @rmtoll CR2 ADON LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Get the selected ADC instance enable state. + * @rmtoll CR2 ADON LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 series, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_REG_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_SWSTART); +} + +/** + * @brief Start ADC group regular conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 series, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_REG_StartConversionSWStart(). + * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group regular conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 series, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL); +} + +/** + * @brief Get ADC multimode conversion data of ADC master, ADC slave + * or raw data with ADC master and slave concatenated. + * @note If raw data with ADC master and slave concatenated is retrieved, + * a macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * (however this macro is mainly intended for multimode + * transfer by DMA, because this function can do the same + * by getting multimode conversion data of ADC master or ADC slave + * separately). + * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n + * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ConversionData This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @arg @ref LL_ADC_MULTI_MASTER_SLAVE + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, + ADC_DR_ADC2DATA) + >> POSITION_VAL(ConversionData) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Start ADC group injected conversion. + * @note On this STM32 series, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_INJ_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART); +} + +/** + * @brief Start ADC group injected conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 series, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_INJ_StartConversionSWStart(). + * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group injected conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 series, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint8_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) & 0x000000FFUL + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint8_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) & 0x000000FFUL + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); +} + + +/** + * @brief Get flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll SR OVR LL_ADC_ClearFlag_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR); +} + + +/** + * @brief Clear flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC master. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC slave 1. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1)); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC slave 2. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2)); +} +/** + * @brief Get flag multimode ADC group regular overrun of the ADC master. + * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC slave 1. + * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1)); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC slave 2. + * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2)); +} + + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. + * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1)); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1. + * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2)); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2. + * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3)); +} + +/** + * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. + * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave 1. + * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1)); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave 2. + * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); +} + + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_OVR); +} + + +/** + * @brief Enable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR); +} + + +/** + * @brief Disable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * (0: interrupt disabled, 1: interrupt enabled) + * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS)); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); +} + + +/** + * @brief Get state of interruption ADC group injected end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); + +/* De-initialization of ADC instance, ADC group regular and ADC group injected */ +/* (availability of ADC group injected depends on STM32 families) */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); + +/* Initialization of some features of ADC instance and ADC group injected */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_ADC_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h index a7af3f46..73d64048 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_bus.h @@ -1,1973 +1,1973 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_bus.h - * @author MCD Application Team - * @brief Header file of BUS LL module. - - @verbatim - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each LL_{BUS}_GRP{x}_EnableClock() function. - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_BUS_H -#define __STM32F7xx_LL_BUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup BUS_LL BUS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants - * @{ - */ - -/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH - * @{ - */ -#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN -#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN -#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN -#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN -#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN -#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN -#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN -#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN -#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN -#if defined(GPIOJ) -#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN -#endif /* GPIOJ */ -#if defined(GPIOK) -#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN -#endif /* GPIOK */ -#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN -#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN -#define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN -#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN -#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN -#if defined(DMA2D) -#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN -#endif /* DMA2D */ -#if defined(ETH) -#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN -#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN -#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN -#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN -#endif /* ETH */ -#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN -#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN -#define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN -#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN -#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN -#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN -/** - * @} - */ - -/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH - * @{ - */ -#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU -#if defined(DCMI) -#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN -#endif /* DCMI */ -#if defined(JPEG) -#define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN -#endif /* JPEG */ -#if defined(CRYP) -#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN -#endif /* CRYP */ -#if defined(AES) -#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN -#endif /* AES */ -#if defined(HASH) -#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN -#endif /* HASH */ -#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN -#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN -/** - * @} - */ - -/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH - * @{ - */ -#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN -#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH - * @{ - */ -#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN -#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN -#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN -#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN -#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN -#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN -#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN -#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN -#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN -#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN -#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN -#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN -#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN -#if defined(SPDIFRX) -#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN -#endif /* SPDIFRX */ -#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN -#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN -#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN -#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN -#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN -#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN -#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN -#if defined(I2C4) -#define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN -#endif /* I2C4 */ -#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN -#if defined(CAN2) -#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN -#endif /* CAN2 */ -#if defined(CAN3) -#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN -#endif /* CAN3 */ -#if defined(CEC) -#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN -#endif /* CEC */ -#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN -#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN -#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN -#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN -#if defined(RCC_APB1ENR_RTCEN) -#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN -#endif /* RCC_APB1ENR_RTCEN */ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH - * @{ - */ -#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN -#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN -#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN -#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN -#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN -#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN -#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN -#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN -#if defined(SDMMC2) -#define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN -#endif /* SDMMC2 */ -#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN -#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN -#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN -#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN -#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN -#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN -#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN -#if defined(SPI6) -#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN -#endif /* SPI6 */ -#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN -#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN -#if defined(LTDC) -#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN -#endif /* LTDC */ -#if defined(DSI) -#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN -#endif /* DSI */ -#if defined(DFSDM1_Channel0) -#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN -#endif /* DFSDM1_Channel0 */ -#if defined(MDIOS) -#define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN -#endif /* MDIOS */ -#if defined(USB_HS_PHYC) -#define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN -#endif /* USB_HS_PHYC */ -#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions - * @{ - */ - -/** @defgroup BUS_LL_EF_AHB1 AHB1 - * @{ - */ - -/** - * @brief Enable AHB1 peripherals clock. - * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB1ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB1 peripheral clock is enabled or not - * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB1 peripherals clock. - * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1ENR, Periphs); -} - -/** - * @brief Force AHB1 peripherals reset. - * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB1RSTR, Periphs); -} - -/** - * @brief Release AHB1 peripherals reset. - * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1RSTR, Periphs); -} - -/** - * @brief Enable AHB1 peripheral clocks in low-power mode - * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n - * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_AXI - * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB1LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable AHB1 peripheral clocks in low-power mode - * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n - * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_AXI - * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS - * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1LPENR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_AHB2 AHB2 - * @{ - */ - -/** - * @brief Enable AHB2 peripherals clock. - * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB2ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB2 peripheral clock is enabled or not - * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB2 peripherals clock. - * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2ENR, Periphs); -} - -/** - * @brief Force AHB2 peripherals reset. - * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB2RSTR, Periphs); -} - -/** - * @brief Release AHB2 peripherals reset. - * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2RSTR, Periphs); -} - -/** - * @brief Enable AHB2 peripheral clocks in low-power mode - * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n - * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB2LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable AHB2 peripheral clocks in low-power mode - * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n - * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2LPENR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_AHB3 AHB3 - * @{ - */ - -/** - * @brief Enable AHB3 peripherals clock. - * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB3ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB3 peripheral clock is enabled or not - * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); -} - -/** - * @brief Disable AHB3 peripherals clock. - * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3ENR, Periphs); -} - -/** - * @brief Force AHB3 peripherals reset. - * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB3RSTR, Periphs); -} - -/** - * @brief Release AHB3 peripherals reset. - * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3RSTR, Periphs); -} - -/** - * @brief Enable AHB3 peripheral clocks in low-power mode - * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n - * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB3LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable AHB3 peripheral clocks in low-power mode - * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n - * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) - * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3LPENR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1 APB1 - * @{ - */ - -/** - * @brief Enable APB1 peripherals clock. - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n - * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n - * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n - * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n - * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n - * APB1ENR RTCEN LL_APB1_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB1 peripherals clock. - * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n - * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n - * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n - * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n - * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n - * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n - * APB1ENR RTCEN LL_APB1_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1ENR, Periphs); -} - -/** - * @brief Force APB1 peripherals reset. - * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @brief Release APB1 peripherals reset. - * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1RSTR, Periphs); -} - -/** - * @brief Enable APB1 peripheral clocks in low-power mode - * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n - * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable APB1 peripheral clocks in low-power mode - * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n - * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 - * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 - * @arg @ref LL_APB1_GRP1_PERIPH_UART7 - * @arg @ref LL_APB1_GRP1_PERIPH_UART8 - * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1LPENR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB2 APB2 - * @{ - */ - -/** - * @brief Enable APB2 peripherals clock. - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n - * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n - * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n - * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n - * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB2 peripheral clock is enabled or not - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). -*/ -__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); -} - -/** - * @brief Disable APB2 peripherals clock. - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n - * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n - * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n - * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n - * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n - * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2ENR, Periphs); -} - -/** - * @brief Force APB2 peripherals reset. - * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n - * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Release APB2 peripherals reset. - * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) - * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Enable APB2 peripheral clocks in low-power mode - * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n - * APB2LPENR MDIOLPEN LL_APB2_GRP1_EnableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2LPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Disable APB2 peripheral clocks in low-power mode - * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n - * APB2LPENR MDIOLPEN LL_APB2_GRP1_DisableClockLowPower - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_USART6 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 - * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 - * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) - * - * (*) value not defined in all devices. - * @retval None -*/ -__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2LPENR, Periphs); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_BUS_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_bus.h + * @author MCD Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_BUS_H +#define __STM32F7xx_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN +#define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN +#define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN +#define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN +#define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN +#define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN +#define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN +#define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN +#define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN +#if defined(GPIOJ) +#define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN +#endif /* GPIOK */ +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN +#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN +#define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN +#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN +#if defined(DMA2D) +#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN +#endif /* DMA2D */ +#if defined(ETH) +#define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN +#define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN +#define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN +#endif /* ETH */ +#define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN +#define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN +#define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN +#define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN +#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN +#define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH + * @{ + */ +#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(DCMI) +#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN +#endif /* DCMI */ +#if defined(JPEG) +#define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN +#endif /* JPEG */ +#if defined(CRYP) +#define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN +#endif /* CRYP */ +#if defined(AES) +#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN +#endif /* AES */ +#if defined(HASH) +#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN +#endif /* HASH */ +#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN +#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH + * @{ + */ +#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN +#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN +#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN +#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN +#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN +#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN +#define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN +#define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN +#define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN +#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN +#if defined(SPDIFRX) +#define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN +#endif /* SPDIFRX */ +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN +#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN +#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN +#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN +#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN +#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN +#if defined(I2C4) +#define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN +#endif /* I2C4 */ +#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN +#if defined(CAN2) +#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN +#endif /* CAN2 */ +#if defined(CAN3) +#define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN +#endif /* CAN3 */ +#if defined(CEC) +#define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN +#endif /* CEC */ +#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN +#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN +#define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN +#define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN +#if defined(RCC_APB1ENR_RTCEN) +#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN +#endif /* RCC_APB1ENR_RTCEN */ +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH + * @{ + */ +#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN +#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN +#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN +#define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN +#define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN +#define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN +#define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN +#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN +#if defined(SDMMC2) +#define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN +#endif /* SDMMC2 */ +#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN +#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN +#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN +#define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN +#define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN +#define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN +#define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN +#if defined(SPI6) +#define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN +#endif /* SPI6 */ +#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN +#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN +#if defined(LTDC) +#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN +#endif /* LTDC */ +#if defined(DSI) +#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN +#endif /* DSI */ +#if defined(DFSDM1_Channel0) +#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN +#endif /* DFSDM1_Channel0 */ +#if defined(MDIOS) +#define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN +#endif /* MDIOS */ +#if defined(USB_HS_PHYC) +#define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN +#endif /* USB_HS_PHYC */ +#define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n + * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n + * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n + * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1ENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n + * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1RSTR, Periphs); +} + +/** + * @brief Enable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB1 peripheral clocks in low-power mode + * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n + * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @arg @ref LL_AHB1_GRP1_PERIPH_AXI + * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 + * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*) + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS + * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB2 AHB2 + * @{ + */ + +/** + * @brief Enable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB2 peripheral clock is enabled or not + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB2 peripherals clock. + * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n + * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2ENR, Periphs); +} + +/** + * @brief Force AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Release AHB2 peripherals reset. + * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n + * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2RSTR, Periphs); +} + +/** + * @brief Enable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB2 peripheral clocks in low-power mode + * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n + * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) + * @arg @ref LL_AHB2_GRP1_PERIPH_RNG + * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB2LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_AHB3 AHB3 + * @{ + */ + +/** + * @brief Enable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB3 peripheral clock is enabled or not + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); +} + +/** + * @brief Disable AHB3 peripherals clock. + * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n + * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3ENR, Periphs); +} + +/** + * @brief Force AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Release AHB3 peripherals reset. + * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n + * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB2_GRP1_PERIPH_ALL + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3RSTR, Periphs); +} + +/** + * @brief Enable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB3LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable AHB3 peripheral clocks in low-power mode + * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n + * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) + * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHB3LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1 APB1 + * @{ + */ + +/** + * @brief Enable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n + * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n + * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n + * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n + * APB1ENR RTCEN LL_APB1_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 peripheral clock is enabled or not + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n + * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB1 peripherals clock. + * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n + * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n + * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n + * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n + * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n + * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n + * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n + * APB1ENR RTCEN LL_APB1_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1ENR, Periphs); +} + +/** + * @brief Force APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Release APB1 peripherals reset. + * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n + * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1RSTR, Periphs); +} + +/** + * @brief Enable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n + * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB1LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB1LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB1 peripheral clocks in low-power mode + * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n + * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 + * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*) + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART3 + * @arg @ref LL_APB1_GRP1_PERIPH_UART4 + * @arg @ref LL_APB1_GRP1_PERIPH_UART5 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 + * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*) + * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 + * @arg @ref LL_APB1_GRP1_PERIPH_UART7 + * @arg @ref LL_APB1_GRP1_PERIPH_UART8 + * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB1LPENR, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB2 APB2 + * @{ + */ + +/** + * @brief Enable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n + * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n + * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB2 peripheral clock is enabled or not + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n + * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval State of Periphs (1 or 0). +*/ +__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); +} + +/** + * @brief Disable APB2 peripherals clock. + * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n + * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n + * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n + * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n + * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n + * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2ENR, Periphs); +} + +/** + * @brief Force APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n + * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n + * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Release APB2 peripherals reset. + * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n + * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_ALL + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2RSTR, Periphs); +} + +/** + * @brief Enable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n + * APB2LPENR MDIOLPEN LL_APB2_GRP1_EnableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2LPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2LPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Disable APB2 peripheral clocks in low-power mode + * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n + * APB2LPENR MDIOLPEN LL_APB2_GRP1_DisableClockLowPower + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 + * @arg @ref LL_APB2_GRP1_PERIPH_USART1 + * @arg @ref LL_APB2_GRP1_PERIPH_USART6 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 + * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 + * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 + * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG + * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 + * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 + * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 + * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) + * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) + * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*) + * + * (*) value not defined in all devices. + * @retval None +*/ +__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APB2LPENR, Periphs); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_BUS_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h index ad98cc2c..f8e5b226 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_cortex.h @@ -1,639 +1,639 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL CORTEX driver contains a set of generic APIs that can be - used by user: - (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick - functions - (+) Low power mode configuration (SCB register of Cortex-MCU) - (+) MPU API to configure and enable regions - (+) API to access to MCU info (CPUID register) - (+) API to enable fault handler (SHCSR accesses) - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_CORTEX_H -#define __STM32F7xx_LL_CORTEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -/** @defgroup CORTEX_LL CORTEX - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source - * @{ - */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type - * @{ - */ -#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ -#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ -#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ -/** - * @} - */ - -#if __MPU_PRESENT - -/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control - * @{ - */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ -#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION MPU Region Number - * @{ - */ -#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ -#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ -#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ -#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ -#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ -#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ -#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ -#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size - * @{ - */ -#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ -#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges - * @{ - */ -#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ -#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ -#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ -#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ -#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ -#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level - * @{ - */ -#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ -#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ -#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ - -/* Legacy Define */ -#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access - * @{ - */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access - * @{ - */ -#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ -#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access - * @{ - */ -#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ -#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access - * @{ - */ -#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ -#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ -/** - * @} - */ -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK - * @{ - */ - -/** - * @brief This function checks if the Systick counter flag is active or not. - * @note It can be used in timeout function on application side. - * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) -{ - return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); -} - -/** - * @brief Configures the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) -{ - if (Source == LL_SYSTICK_CLKSOURCE_HCLK) - { - SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } - else - { - CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } -} - -/** - * @brief Get the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - */ -__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) -{ - return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); -} - -/** - * @brief Enable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_EnableIT(void) -{ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Disable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_DisableIT(void) -{ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Checks if the SYSTICK interrupt is enabled or disabled. - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) -{ - return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE - * @{ - */ - -/** - * @brief Processor uses sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleep(void) -{ - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Processor uses deep sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) -{ - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. - * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an - * empty main application. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Do not sleep when returning to Thread mode. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the - * processor. - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) -{ - /* Set SEVEONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are - * excluded - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) -{ - /* Clear SEVEONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_HANDLER HANDLER - * @{ - */ - -/** - * @brief Enable a fault in System handler control register (SHCSR) - * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault - * @param Fault This parameter can be a combination of the following values: - * @arg @ref LL_HANDLER_FAULT_USG - * @arg @ref LL_HANDLER_FAULT_BUS - * @arg @ref LL_HANDLER_FAULT_MEM - * @retval None - */ -__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) -{ - /* Enable the system handler fault */ - SET_BIT(SCB->SHCSR, Fault); -} - -/** - * @brief Disable a fault in System handler control register (SHCSR) - * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault - * @param Fault This parameter can be a combination of the following values: - * @arg @ref LL_HANDLER_FAULT_USG - * @arg @ref LL_HANDLER_FAULT_BUS - * @arg @ref LL_HANDLER_FAULT_MEM - * @retval None - */ -__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) -{ - /* Disable the system handler fault */ - CLEAR_BIT(SCB->SHCSR, Fault); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO - * @{ - */ - -/** - * @brief Get Implementer code - * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer - * @retval Value should be equal to 0x41 for ARM - */ -__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); -} - -/** - * @brief Get Variant number (The r value in the rnpn product revision identifier) - * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant - * @retval Value between 0 and 255 (0x0: revision 0) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); -} - -/** - * @brief Get Constant number - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant - * @retval Value should be equal to 0xF for Cortex-M7 devices - */ -__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); -} - -/** - * @brief Get Part number - * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo - * @retval Value should be equal to 0xC27 for Cortex-M7 - */ -__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); -} - -/** - * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) - * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision - * @retval Value between 0 and 255 (0x1: patch 1) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); -} - -/** - * @} - */ - -#if __MPU_PRESENT -/** @defgroup CORTEX_LL_EF_MPU MPU - * @{ - */ - -/** - * @brief Enable MPU with input options - * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable - * @param Options This parameter can be one of the following values: - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE - * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI - * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) -{ - /* Enable the MPU*/ - WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); - /* Ensure MPU settings take effects */ - __DSB(); - /* Sequence instruction fetches using update settings */ - __ISB(); -} - -/** - * @brief Disable MPU - * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable - * @retval None - */ -__STATIC_INLINE void LL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - /* Disable MPU*/ - WRITE_REG(MPU->CTRL, 0U); -} - -/** - * @brief Check if MPU is enabled or not - * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) -{ - return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); -} - -/** - * @brief Enable a MPU region - * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Enable the MPU region */ - SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); -} - -/** - * @brief Configure and enable a region - * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n - * MPU_RBAR REGION LL_MPU_ConfigRegion\n - * MPU_RBAR ADDR LL_MPU_ConfigRegion\n - * MPU_RASR XN LL_MPU_ConfigRegion\n - * MPU_RASR AP LL_MPU_ConfigRegion\n - * MPU_RASR S LL_MPU_ConfigRegion\n - * MPU_RASR C LL_MPU_ConfigRegion\n - * MPU_RASR B LL_MPU_ConfigRegion\n - * MPU_RASR SIZE LL_MPU_ConfigRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param Address Value of region base address - * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF - * @param Attributes This parameter can be a combination of the following values: - * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B - * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB - * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB - * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB - * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB - * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB - * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS - * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO - * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 - * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE - * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE - * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE - * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Set base address */ - WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); - /* Configure MPU */ - WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); -} - -/** - * @brief Disable a region - * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n - * MPU_RASR ENABLE LL_MPU_DisableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - /* Disable the MPU region */ - CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); -} - -/** - * @} - */ - -#endif /* __MPU_PRESENT */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_CORTEX_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_cortex.h + * @author MCD Application Team + * @brief Header file of CORTEX LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL CORTEX driver contains a set of generic APIs that can be + used by user: + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick + functions + (+) Low power mode configuration (SCB register of Cortex-MCU) + (+) MPU API to configure and enable regions + (+) API to access to MCU info (CPUID register) + (+) API to enable fault handler (SHCSR accesses) + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_CORTEX_H +#define __STM32F7xx_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type + * @{ + */ +#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ +#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ +#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ +/** + * @} + */ + +#if __MPU_PRESENT + +/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control + * @{ + */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ +#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION MPU Region Number + * @{ + */ +#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ +#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ +#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ +#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ +#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ +#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ +#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ +#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size + * @{ + */ +#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ +#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges + * @{ + */ +#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ +#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ +#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ +#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ +#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ +#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level + * @{ + */ +#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ +#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ +#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ + +/* Legacy Define */ +#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access + * @{ + */ +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access + * @{ + */ +#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ +#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access + * @{ + */ +#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ +#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ +/** + * @} + */ + +/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access + * @{ + */ +#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ +#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ +/** + * @} + */ +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_HANDLER HANDLER + * @{ + */ + +/** + * @brief Enable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) +{ + /* Enable the system handler fault */ + SET_BIT(SCB->SHCSR, Fault); +} + +/** + * @brief Disable a fault in System handler control register (SHCSR) + * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault + * @param Fault This parameter can be a combination of the following values: + * @arg @ref LL_HANDLER_FAULT_USG + * @arg @ref LL_HANDLER_FAULT_BUS + * @arg @ref LL_HANDLER_FAULT_MEM + * @retval None + */ +__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) +{ + /* Disable the system handler fault */ + CLEAR_BIT(SCB->SHCSR, Fault); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Constant number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant + * @retval Value should be equal to 0xF for Cortex-M7 devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC27 for Cortex-M7 + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +#if __MPU_PRESENT +/** @defgroup CORTEX_LL_EF_MPU MPU + * @{ + */ + +/** + * @brief Enable MPU with input options + * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable + * @param Options This parameter can be one of the following values: + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE + * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI + * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT + * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF + * @retval None + */ +__STATIC_INLINE void LL_MPU_Enable(uint32_t Options) +{ + /* Enable the MPU*/ + WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); + /* Ensure MPU settings take effects */ + __DSB(); + /* Sequence instruction fetches using update settings */ + __ISB(); +} + +/** + * @brief Disable MPU + * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable + * @retval None + */ +__STATIC_INLINE void LL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + /* Disable MPU*/ + WRITE_REG(MPU->CTRL, 0U); +} + +/** + * @brief Check if MPU is enabled or not + * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) +{ + return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); +} + +/** + * @brief Enable a MPU region + * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Enable the MPU region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Configure and enable a region + * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR REGION LL_MPU_ConfigRegion\n + * MPU_RBAR ADDR LL_MPU_ConfigRegion\n + * MPU_RASR XN LL_MPU_ConfigRegion\n + * MPU_RASR AP LL_MPU_ConfigRegion\n + * MPU_RASR S LL_MPU_ConfigRegion\n + * MPU_RASR C LL_MPU_ConfigRegion\n + * MPU_RASR B LL_MPU_ConfigRegion\n + * MPU_RASR SIZE LL_MPU_ConfigRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @param Address Value of region base address + * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF + * @param Attributes This parameter can be a combination of the following values: + * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B + * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB + * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB + * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB + * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB + * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB + * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS + * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO + * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 + * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE + * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE + * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE + * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE + * @retval None + */ +__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Set base address */ + WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); + /* Configure MPU */ + WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); +} + +/** + * @brief Disable a region + * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n + * MPU_RASR ENABLE LL_MPU_DisableRegion + * @param Region This parameter can be one of the following values: + * @arg @ref LL_MPU_REGION_NUMBER0 + * @arg @ref LL_MPU_REGION_NUMBER1 + * @arg @ref LL_MPU_REGION_NUMBER2 + * @arg @ref LL_MPU_REGION_NUMBER3 + * @arg @ref LL_MPU_REGION_NUMBER4 + * @arg @ref LL_MPU_REGION_NUMBER5 + * @arg @ref LL_MPU_REGION_NUMBER6 + * @arg @ref LL_MPU_REGION_NUMBER7 + * @retval None + */ +__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) +{ + /* Set Region number */ + WRITE_REG(MPU->RNR, Region); + /* Disable the MPU region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @} + */ + +#endif /* __MPU_PRESENT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_CORTEX_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_crc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_crc.h deleted file mode 100644 index 2f421022..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_crc.h +++ /dev/null @@ -1,461 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_crc.h - * @author MCD Application Team - * @brief Header file of CRC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_CRC_H -#define STM32F7xx_LL_CRC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(CRC) - -/** @defgroup CRC_LL CRC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants - * @{ - */ - -/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length - * @{ - */ -#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */ -#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */ -#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */ -#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */ -/** - * @} - */ - -/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse - * @{ - */ -#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */ -#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */ -#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */ -#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */ -/** - * @} - */ - -/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse - * @{ - */ -#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */ -#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */ -/** - * @} - */ - -/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value - * @brief Normal representation of this polynomial value is - * X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 . - * @{ - */ -#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */ -/** - * @} - */ - -/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value - * @{ - */ -#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros - * @{ - */ - -/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in CRC register - * @param __INSTANCE__ CRC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) - -/** - * @brief Read a value in CRC register - * @param __INSTANCE__ CRC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions - * @{ - */ - -/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions - * @{ - */ - -/** - * @brief Reset the CRC calculation unit. - * @note If Programmable Initial CRC value feature - * is available, also set the Data Register to the value stored in the - * CRC_INIT register, otherwise, reset Data Register to its default value. - * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit - * @param CRCx CRC Instance - * @retval None - */ -__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) -{ - SET_BIT(CRCx->CR, CRC_CR_RESET); -} - -/** - * @brief Configure size of the polynomial. - * @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize - * @param CRCx CRC Instance - * @param PolySize This parameter can be one of the following values: - * @arg @ref LL_CRC_POLYLENGTH_32B - * @arg @ref LL_CRC_POLYLENGTH_16B - * @arg @ref LL_CRC_POLYLENGTH_8B - * @arg @ref LL_CRC_POLYLENGTH_7B - * @retval None - */ -__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize) -{ - MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize); -} - -/** - * @brief Return size of the polynomial. - * @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize - * @param CRCx CRC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRC_POLYLENGTH_32B - * @arg @ref LL_CRC_POLYLENGTH_16B - * @arg @ref LL_CRC_POLYLENGTH_8B - * @arg @ref LL_CRC_POLYLENGTH_7B - */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); -} - -/** - * @brief Configure the reversal of the bit order of the input data - * @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode - * @param CRCx CRC Instance - * @param ReverseMode This parameter can be one of the following values: - * @arg @ref LL_CRC_INDATA_REVERSE_NONE - * @arg @ref LL_CRC_INDATA_REVERSE_BYTE - * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD - * @arg @ref LL_CRC_INDATA_REVERSE_WORD - * @retval None - */ -__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) -{ - MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode); -} - -/** - * @brief Return type of reversal for input data bit order - * @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode - * @param CRCx CRC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRC_INDATA_REVERSE_NONE - * @arg @ref LL_CRC_INDATA_REVERSE_BYTE - * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD - * @arg @ref LL_CRC_INDATA_REVERSE_WORD - */ -__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); -} - -/** - * @brief Configure the reversal of the bit order of the Output data - * @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode - * @param CRCx CRC Instance - * @param ReverseMode This parameter can be one of the following values: - * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE - * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT - * @retval None - */ -__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode) -{ - MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode); -} - -/** - * @brief Return type of reversal of the bit order of the Output data - * @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode - * @param CRCx CRC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE - * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT - */ -__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); -} - -/** - * @brief Initialize the Programmable initial CRC value. - * @note If the CRC size is less than 32 bits, the least significant bits - * are used to write the correct value - * @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter. - * @rmtoll INIT INIT LL_CRC_SetInitialData - * @param CRCx CRC Instance - * @param InitCrc Value to be programmed in Programmable initial CRC value register - * @retval None - */ -__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) -{ - WRITE_REG(CRCx->INIT, InitCrc); -} - -/** - * @brief Return current Initial CRC value. - * @note If the CRC size is less than 32 bits, the least significant bits - * are used to read the correct value - * @rmtoll INIT INIT LL_CRC_GetInitialData - * @param CRCx CRC Instance - * @retval Value programmed in Programmable initial CRC value register - */ -__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_REG(CRCx->INIT)); -} - -/** - * @brief Initialize the Programmable polynomial value - * (coefficients of the polynomial to be used for CRC calculation). - * @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter. - * @note Please check Reference Manual and existing Errata Sheets, - * regarding possible limitations for Polynomial values usage. - * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 - * @rmtoll POL POL LL_CRC_SetPolynomialCoef - * @param CRCx CRC Instance - * @param PolynomCoef Value to be programmed in Programmable Polynomial value register - * @retval None - */ -__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef) -{ - WRITE_REG(CRCx->POL, PolynomCoef); -} - -/** - * @brief Return current Programmable polynomial value - * @note Please check Reference Manual and existing Errata Sheets, - * regarding possible limitations for Polynomial values usage. - * For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 - * @rmtoll POL POL LL_CRC_GetPolynomialCoef - * @param CRCx CRC Instance - * @retval Value programmed in Programmable Polynomial value register - */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_REG(CRCx->POL)); -} - -/** - * @} - */ - -/** @defgroup CRC_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Write given 32-bit data to the CRC calculator - * @rmtoll DR DR LL_CRC_FeedData32 - * @param CRCx CRC Instance - * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) -{ - WRITE_REG(CRCx->DR, InData); -} - -/** - * @brief Write given 16-bit data to the CRC calculator - * @rmtoll DR DR LL_CRC_FeedData16 - * @param CRCx CRC Instance - * @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData) -{ - __IO uint16_t *pReg; - - pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */ - *pReg = InData; -} - -/** - * @brief Write given 8-bit data to the CRC calculator - * @rmtoll DR DR LL_CRC_FeedData8 - * @param CRCx CRC Instance - * @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) -{ - *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData; -} - -/** - * @brief Return current CRC calculation result. 32 bits value is returned. - * @rmtoll DR DR LL_CRC_ReadData32 - * @param CRCx CRC Instance - * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). - */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_REG(CRCx->DR)); -} - -/** - * @brief Return current CRC calculation result. 16 bits value is returned. - * @note This function is expected to be used in a 16 bits CRC polynomial size context. - * @rmtoll DR DR LL_CRC_ReadData16 - * @param CRCx CRC Instance - * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). - */ -__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) -{ - return (uint16_t)READ_REG(CRCx->DR); -} - -/** - * @brief Return current CRC calculation result. 8 bits value is returned. - * @note This function is expected to be used in a 8 bits CRC polynomial size context. - * @rmtoll DR DR LL_CRC_ReadData8 - * @param CRCx CRC Instance - * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). - */ -__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) -{ - return (uint8_t)READ_REG(CRCx->DR); -} - -/** - * @brief Return current CRC calculation result. 7 bits value is returned. - * @note This function is expected to be used in a 7 bits CRC polynomial size context. - * @rmtoll DR DR LL_CRC_ReadData7 - * @param CRCx CRC Instance - * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). - */ -__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) -{ - return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); -} - -/** - * @brief Return data stored in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. - * @rmtoll IDR IDR LL_CRC_Read_IDR - * @param CRCx CRC Instance - * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). - */ -__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_REG(CRCx->IDR)); -} - -/** - * @brief Store data in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. - * @rmtoll IDR IDR LL_CRC_Write_IDR - * @param CRCx CRC Instance - * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) -{ - *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; -} -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(CRC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_CRC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h deleted file mode 100644 index 75ff2060..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dac.h +++ /dev/null @@ -1,1335 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_dac.h - * @author MCD Application Team - * @brief Header file of DAC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_DAC_H -#define STM32F7xx_LL_DAC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(DAC) - -/** @defgroup DAC_LL DAC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DAC_LL_Private_Constants DAC Private Constants - * @{ - */ - -/* Internal masks for DAC channels definition */ -/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ -/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ -/* - channel bits position into register SWTRIG */ -/* - channel register offset of data holding register DHRx */ -/* - channel register offset of data output register DORx */ -#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers - CR, MCR, CCR, SHHR, SHRR of channel 1 */ -#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers - CR, MCR, CCR, SHHR, SHRR of channel 2 */ -#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) - -#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ -#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ -#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) - -#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ -#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus - DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus - DHR12Rx channel 1 (shifted left of 24 bits) */ - -#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus - DHR12Rx channel 1 (shifted left of 16 bits) */ -#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus - DHR12Rx channel 1 (shifted left of 20 bits) */ -#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus - DHR12Rx channel 1 (shifted left of 24 bits) */ - -#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL -#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL -#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL -#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ - | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) - -#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ - -#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus - DORx channel 2 (shifted left of 28 bits) */ -#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) - - - -#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, - DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ -#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted - to position 0 */ -#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted - to position 0 */ - -#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx - channel 1 or 2 versus DHR12Rx channel 1 - (shifted left of 16 bits) */ -#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx - channel 1 or 2 versus DHR12Rx channel 1 - (shifted left of 20 bits) */ -#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx - channel 1 or 2 versus DHR12Rx channel 1 - (shifted left of 24 bits) */ -#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx - channel 1 or 2 versus DORx channel 1 - (shifted left of 28 bits) */ - -/* DAC registers bits positions */ -#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos -#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos -#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos - -/* Miscellaneous data */ -#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 - bits (voltage range determined by analog voltage - references Vref+ and Vref-, refer to reference manual) */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup DAC_LL_Private_Macros DAC Private Macros - * @{ - */ - -/** - * @brief Driver macro reserved for internal use: set a pointer to - * a register from a register basis from which an offset - * is applied. - * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). - * @retval Pointer to register address - */ -#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) - -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure - * @{ - */ - -/** - * @brief Structure definition of some features of DAC instance. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: - internal (SW start) or from external peripheral - (timer event, external interrupt line). - This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE - - This feature can be modified afterwards using unitary - function @ref LL_DAC_SetTriggerSource(). */ - - uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. - This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE - - This feature can be modified afterwards using unitary - function @ref LL_DAC_SetWaveAutoGeneration(). */ - - uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. - If waveform automatic generation mode is set to noise, this parameter - can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS - If waveform automatic generation mode is set to triangle, - this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE - @note If waveform automatic generation mode is disabled, - this parameter is discarded. - - This feature can be modified afterwards using unitary - function @ref LL_DAC_SetWaveNoiseLFSR(), - @ref LL_DAC_SetWaveTriangleAmplitude() - depending on the wave automatic generation selected. */ - - uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. - This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER - - This feature can be modified afterwards using unitary - function @ref LL_DAC_SetOutputBuffer(). */ -} LL_DAC_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants - * @{ - */ - -/** @defgroup DAC_LL_EC_GET_FLAG DAC flags - * @brief Flags defines which can be used with LL_DAC_ReadReg function - * @{ - */ -/* DAC channel 1 flags */ -#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ - -/* DAC channel 2 flags */ -#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ - -/** - * @} - */ - -/** @defgroup DAC_LL_EC_IT DAC interruptions - * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions - * @{ - */ -#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ - -#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ - -/** - * @} - */ - -/** @defgroup DAC_LL_EC_CHANNEL DAC channels - * @{ - */ -#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ - -#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ - -/** - * @} - */ - -/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source - * @{ - */ -#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ -#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ -#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ -#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ -/** - * @} - */ - -/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode - * @{ - */ -#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ -#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ -#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ -/** - * @} - */ - -/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits - * @{ - */ -#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ -#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ -/** - * @} - */ - -/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude - * @{ - */ -#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ -#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ -/** - * @} - */ - -/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer - * @{ - */ -#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ -#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ -/** - * @} - */ - -/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution - * @{ - */ -#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ -#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ -/** - * @} - */ - -/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose - * @{ - */ -/* List of DAC registers intended to be used (most commonly) with */ -/* DMA transfer. */ -/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ -#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ -#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ -#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ -/** - * @} - */ - -/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays - * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, - * not timeout values. - * For details on delays values, refer to descriptions in source code - * above each literal definition. - * @{ - */ - -/* Delay for DAC channel voltage settling time from DAC channel startup */ -/* (transition from disable to enable). */ -/* Note: DAC channel startup time depends on board application environment: */ -/* impedance connected to DAC channel output. */ -/* The delay below is specified under conditions: */ -/* - voltage maximum transition (lowest to highest value) */ -/* - until voltage reaches final value +-1LSB */ -/* - DAC channel output buffer enabled */ -/* - load impedance of 5kOhm (min), 50pF (max) */ -/* Literal set to maximum value (refer to device datasheet, */ -/* parameter "tWAKEUP"). */ -/* Unit: us */ -#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ - -/* Delay for DAC channel voltage settling time. */ -/* Note: DAC channel startup time depends on board application environment: */ -/* impedance connected to DAC channel output. */ -/* The delay below is specified under conditions: */ -/* - voltage maximum transition (lowest to highest value) */ -/* - until voltage reaches final value +-1LSB */ -/* - DAC channel output buffer enabled */ -/* - load impedance of 5kOhm min, 50pF max */ -/* Literal set to maximum value (refer to device datasheet, */ -/* parameter "tSETTLING"). */ -/* Unit: us */ -#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros - * @{ - */ - -/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros - * @{ - */ - -/** - * @brief Write a value in DAC register - * @param __INSTANCE__ DAC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DAC register - * @param __INSTANCE__ DAC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) - -/** - * @} - */ - -/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro - * @{ - */ - -/** - * @brief Helper macro to get DAC channel number in decimal format - * from literals LL_DAC_CHANNEL_x. - * Example: - * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) - * will return decimal number "1". - * @note The input can be a value from functions where a channel - * number is returned. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval 1...2 - */ -#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((__CHANNEL__) & DAC_SWTR_CHX_MASK) - -/** - * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x - * from number in decimal format. - * Example: - * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) - * will return a data equivalent to "LL_DAC_CHANNEL_1". - * @note If the input parameter does not correspond to a DAC channel, - * this macro returns value '0'. - * @param __DECIMAL_NB__ 1...2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - */ -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ - (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) - -/** - * @brief Helper macro to define the DAC conversion data full-scale digital - * value corresponding to the selected DAC resolution. - * @note DAC conversion data full-scale corresponds to voltage range - * determined by analog voltage references Vref+ and Vref- - * (refer to reference manual). - * @param __DAC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_DAC_RESOLUTION_12B - * @arg @ref LL_DAC_RESOLUTION_8B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) - -/** - * @brief Helper macro to calculate the DAC conversion data (unit: digital - * value) corresponding to a voltage (unit: mVolt). - * @note This helper macro is intended to provide input data in voltage - * rather than digital value, - * to be used with LL DAC functions such as - * @ref LL_DAC_ConvertData12RightAligned(). - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel - * (unit: mVolt). - * @param __DAC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_DAC_RESOLUTION_12B - * @arg @ref LL_DAC_RESOLUTION_8B - * @retval DAC conversion data (unit: digital value) - */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ - ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ - ) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions - * @{ - */ - -/** - * @brief Set the conversion trigger source for the selected DAC channel. - * @note For conversion trigger source to be effective, DAC trigger - * must be enabled using function @ref LL_DAC_EnableTrigger(). - * @note To set conversion trigger source, DAC channel must be disabled. - * Otherwise, the setting is discarded. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n - * CR TSEL2 LL_DAC_SetTriggerSource - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_DAC_TRIG_SOFTWARE - * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 - * @retval None - */ -__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) -{ - MODIFY_REG(DACx->CR, - DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Get the conversion trigger source for the selected DAC channel. - * @note For conversion trigger source to be effective, DAC trigger - * must be enabled using function @ref LL_DAC_EnableTrigger(). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n - * CR TSEL2 LL_DAC_GetTriggerSource - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DAC_TRIG_SOFTWARE - * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO - * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO - * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 - */ -__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - ); -} - -/** - * @brief Set the waveform automatic generation mode - * for the selected DAC channel. - * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n - * CR WAVE2 LL_DAC_SetWaveAutoGeneration - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param WaveAutoGeneration This parameter can be one of the following values: - * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE - * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE - * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE - * @retval None - */ -__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) -{ - MODIFY_REG(DACx->CR, - DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Get the waveform automatic generation mode - * for the selected DAC channel. - * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n - * CR WAVE2 LL_DAC_GetWaveAutoGeneration - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE - * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE - * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE - */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - ); -} - -/** - * @brief Set the noise waveform generation for the selected DAC channel: - * Noise mode and parameters LFSR (linear feedback shift register). - * @note For wave generation to be effective, DAC channel - * wave generation mode must be enabled using - * function @ref LL_DAC_SetWaveAutoGeneration(). - * @note This setting can be set when the selected DAC channel is disabled - * (otherwise, the setting operation is ignored). - * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n - * CR MAMP2 LL_DAC_SetWaveNoiseLFSR - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param NoiseLFSRMask This parameter can be one of the following values: - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 - * @retval None - */ -__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) -{ - MODIFY_REG(DACx->CR, - DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Get the noise waveform generation for the selected DAC channel: - * Noise mode and parameters LFSR (linear feedback shift register). - * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n - * CR MAMP2 LL_DAC_GetWaveNoiseLFSR - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 - * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 - */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - ); -} - -/** - * @brief Set the triangle waveform generation for the selected DAC channel: - * triangle mode and amplitude. - * @note For wave generation to be effective, DAC channel - * wave generation mode must be enabled using - * function @ref LL_DAC_SetWaveAutoGeneration(). - * @note This setting can be set when the selected DAC channel is disabled - * (otherwise, the setting operation is ignored). - * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n - * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param TriangleAmplitude This parameter can be one of the following values: - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 - * @retval None - */ -__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, - uint32_t TriangleAmplitude) -{ - MODIFY_REG(DACx->CR, - DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Get the triangle waveform generation for the selected DAC channel: - * triangle mode and amplitude. - * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n - * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 - * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 - */ -__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - ); -} - -/** - * @brief Set the output buffer for the selected DAC channel. - * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n - * CR BOFF2 LL_DAC_SetOutputBuffer - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param OutputBuffer This parameter can be one of the following values: - * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE - * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE - * @retval None - */ -__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) -{ - MODIFY_REG(DACx->CR, - DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), - OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Get the output buffer state for the selected DAC channel. - * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n - * CR BOFF2 LL_DAC_GetOutputBuffer - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE - * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE - */ -__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - ); -} - -/** - * @} - */ - -/** @defgroup DAC_LL_EF_DMA_Management DMA Management - * @{ - */ - -/** - * @brief Enable DAC DMA transfer request of the selected channel. - * @note To configure DMA source address (peripheral address), - * use function @ref LL_DAC_DMA_GetRegAddr(). - * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n - * CR DMAEN2 LL_DAC_EnableDMAReq - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval None - */ -__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - SET_BIT(DACx->CR, - DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Disable DAC DMA transfer request of the selected channel. - * @note To configure DMA source address (peripheral address), - * use function @ref LL_DAC_DMA_GetRegAddr(). - * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n - * CR DMAEN2 LL_DAC_DisableDMAReq - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval None - */ -__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - CLEAR_BIT(DACx->CR, - DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Get DAC DMA transfer request state of the selected channel. - * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) - * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n - * CR DMAEN2 LL_DAC_IsDMAReqEnabled - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return ((READ_BIT(DACx->CR, - DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); -} - -/** - * @brief Function to help to configure DMA transfer to DAC: retrieve the - * DAC register address from DAC instance and a list of DAC registers - * intended to be used (most commonly) with DMA transfer. - * @note These DAC registers are data holding registers: - * when DAC conversion is requested, DAC generates a DMA transfer - * request to have data available in DAC data holding registers. - * @note This macro is intended to be used with LL DMA driver, refer to - * function "LL_DMA_ConfigAddresses()". - * Example: - * LL_DMA_ConfigAddresses(DMA1, - * LL_DMA_CHANNEL_1, - * (uint32_t)&< array or variable >, - * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, - * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), - * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); - * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n - * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n - * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n - * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n - * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n - * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param Register This parameter can be one of the following values: - * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED - * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED - * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED - * @retval DAC register address - */ -__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) -{ - /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ - /* DAC channel selected. */ - return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) - & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); -} -/** - * @} - */ - -/** @defgroup DAC_LL_EF_Operation Operation on DAC channels - * @{ - */ - -/** - * @brief Enable DAC selected channel. - * @rmtoll CR EN1 LL_DAC_Enable\n - * CR EN2 LL_DAC_Enable - * @note After enable from off state, DAC channel requires a delay - * for output voltage to reach accuracy +/- 1 LSB. - * Refer to device datasheet, parameter "tWAKEUP". - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval None - */ -__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - SET_BIT(DACx->CR, - DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Disable DAC selected channel. - * @rmtoll CR EN1 LL_DAC_Disable\n - * CR EN2 LL_DAC_Disable - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval None - */ -__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - CLEAR_BIT(DACx->CR, - DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Get DAC enable state of the selected channel. - * (0: DAC channel is disabled, 1: DAC channel is enabled) - * @rmtoll CR EN1 LL_DAC_IsEnabled\n - * CR EN2 LL_DAC_IsEnabled - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return ((READ_BIT(DACx->CR, - DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); -} - -/** - * @brief Enable DAC trigger of the selected channel. - * @note - If DAC trigger is disabled, DAC conversion is performed - * automatically once the data holding register is updated, - * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": - * @ref LL_DAC_ConvertData12RightAligned(), ... - * - If DAC trigger is enabled, DAC conversion is performed - * only when a hardware of software trigger event is occurring. - * Select trigger source using - * function @ref LL_DAC_SetTriggerSource(). - * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n - * CR TEN2 LL_DAC_EnableTrigger - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval None - */ -__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - SET_BIT(DACx->CR, - DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Disable DAC trigger of the selected channel. - * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n - * CR TEN2 LL_DAC_DisableTrigger - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval None - */ -__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - CLEAR_BIT(DACx->CR, - DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); -} - -/** - * @brief Get DAC trigger state of the selected channel. - * (0: DAC trigger is disabled, 1: DAC trigger is enabled) - * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n - * CR TEN2 LL_DAC_IsTriggerEnabled - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - return ((READ_BIT(DACx->CR, - DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) - == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); -} - -/** - * @brief Trig DAC conversion by software for the selected DAC channel. - * @note Preliminarily, DAC trigger must be set to software trigger - * using function - * @ref LL_DAC_Init() - * @ref LL_DAC_SetTriggerSource() - * with parameter "LL_DAC_TRIGGER_SOFTWARE". - * and DAC trigger must be enabled using - * function @ref LL_DAC_EnableTrigger(). - * @note For devices featuring DAC with 2 channels: this function - * can perform a SW start of both DAC channels simultaneously. - * Two channels can be selected as parameter. - * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) - * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n - * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion - * @param DACx DAC instance - * @param DAC_Channel This parameter can a combination of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval None - */ -__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - SET_BIT(DACx->SWTRIGR, - (DAC_Channel & DAC_SWTR_CHX_MASK)); -} - -/** - * @brief Set the data to be loaded in the data holding register - * in format 12 bits left alignment (LSB aligned on bit 0), - * for the selected DAC channel. - * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n - * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) -{ - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) - & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - - MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); -} - -/** - * @brief Set the data to be loaded in the data holding register - * in format 12 bits left alignment (MSB aligned on bit 15), - * for the selected DAC channel. - * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n - * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) -{ - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) - & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - - MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); -} - -/** - * @brief Set the data to be loaded in the data holding register - * in format 8 bits left alignment (LSB aligned on bit 0), - * for the selected DAC channel. - * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n - * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param Data Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) -{ - __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) - & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); - - MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); -} - - -/** - * @brief Set the data to be loaded in the data holding register - * in format 12 bits left alignment (LSB aligned on bit 0), - * for both DAC channels. - * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n - * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned - * @param DACx DAC instance - * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF - * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, - uint32_t DataChannel2) -{ - MODIFY_REG(DACx->DHR12RD, - (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), - ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); -} - -/** - * @brief Set the data to be loaded in the data holding register - * in format 12 bits left alignment (MSB aligned on bit 15), - * for both DAC channels. - * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n - * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned - * @param DACx DAC instance - * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF - * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, - uint32_t DataChannel2) -{ - /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ - /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ - /* the 4 LSB must be taken into account for the shift value. */ - MODIFY_REG(DACx->DHR12LD, - (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), - ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); -} - -/** - * @brief Set the data to be loaded in the data holding register - * in format 8 bits left alignment (LSB aligned on bit 0), - * for both DAC channels. - * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n - * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned - * @param DACx DAC instance - * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF - * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, - uint32_t DataChannel2) -{ - MODIFY_REG(DACx->DHR8RD, - (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), - ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); -} - - -/** - * @brief Retrieve output data currently generated for the selected DAC channel. - * @note Whatever alignment and resolution settings - * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": - * @ref LL_DAC_ConvertData12RightAligned(), ...), - * output data format is 12 bits right aligned (LSB aligned on bit 0). - * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n - * DOR2 DACC2DOR LL_DAC_RetrieveOutputData - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel) -{ - __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) - & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); - - return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); -} - -/** - * @} - */ - -/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Get DAC underrun flag for DAC channel 1 - * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 - * @param DACx DAC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx) -{ - return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); -} - - -/** - * @brief Get DAC underrun flag for DAC channel 2 - * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 - * @param DACx DAC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx) -{ - return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); -} - - -/** - * @brief Clear DAC underrun flag for DAC channel 1 - * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 - * @param DACx DAC instance - * @retval None - */ -__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) -{ - WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); -} - - -/** - * @brief Clear DAC underrun flag for DAC channel 2 - * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 - * @param DACx DAC instance - * @retval None - */ -__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) -{ - WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); -} - - -/** - * @} - */ - -/** @defgroup DAC_LL_EF_IT_Management IT management - * @{ - */ - -/** - * @brief Enable DMA underrun interrupt for DAC channel 1 - * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 - * @param DACx DAC instance - * @retval None - */ -__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) -{ - SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); -} - - -/** - * @brief Enable DMA underrun interrupt for DAC channel 2 - * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 - * @param DACx DAC instance - * @retval None - */ -__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) -{ - SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); -} - - -/** - * @brief Disable DMA underrun interrupt for DAC channel 1 - * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 - * @param DACx DAC instance - * @retval None - */ -__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) -{ - CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); -} - - -/** - * @brief Disable DMA underrun interrupt for DAC channel 2 - * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 - * @param DACx DAC instance - * @retval None - */ -__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) -{ - CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); -} - - -/** - * @brief Get DMA underrun interrupt for DAC channel 1 - * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 - * @param DACx DAC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) -{ - return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); -} - - -/** - * @brief Get DMA underrun interrupt for DAC channel 2 - * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 - * @param DACx DAC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx) -{ - return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); -} - - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx); -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); -void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DAC */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_DAC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h index 07933e4c..8f86cfff 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma.h @@ -1,2891 +1,2891 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_dma.h - * @author MCD Application Team - * @brief Header file of DMA LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_DMA_H -#define __STM32F7xx_LL_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (DMA1) || defined (DMA2) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Variables DMA Private Variables - * @{ - */ -/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ -static const uint8_t STREAM_OFFSET_TAB[] = -{ - (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), - (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) -}; - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Constants DMA Private Constants - * @{ - */ -#if defined(DMA_SxCR_CHSEL_3) -#define DMA_CHANNEL_SELECTION_8_15 -#endif /* DMA_SxCR_CHSEL_3 */ -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer - or as Source base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer - or as Destination base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_LL_EC_DIRECTION - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ - - uint32_t Mode; /*!< Specifies the normal or circular operation mode. - This parameter can be a value of @ref DMA_LL_EC_MODE - @note The circular buffer mode cannot be used if the memory to memory - data transfer direction is configured on the selected Stream - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ - - uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_PERIPH - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ - - uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_MEMORY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ - - uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ - - uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ - - uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. - The data unit is equal to the source buffer configuration set in PeripheralSize - or MemorySize parameters depending in the transfer direction. - This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ - - uint32_t Channel; /*!< Specifies the peripheral channel. - This parameter can be a value of @ref DMA_LL_EC_CHANNEL - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ - - uint32_t Priority; /*!< Specifies the channel priority level. - This parameter can be a value of @ref DMA_LL_EC_PRIORITY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ - - uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. - This parameter can be a value of @ref DMA_LL_FIFOMODE - @note The Direct mode (FIFO mode disabled) cannot be used if the - memory-to-memory data transfer is configured on the selected stream - - This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ - - uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ - - uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_LL_EC_MBURST - @note The burst mode is possible only if the address Increment mode is enabled. - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ - - uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. - It specifies the amount of data to be transferred in a single non interruptible - transaction. - This parameter can be a value of @ref DMA_LL_EC_PBURST - @note The burst mode is possible only if the address Increment mode is enabled. - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ - -} LL_DMA_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_LL_EC_STREAM STREAM - * @{ - */ -#define LL_DMA_STREAM_0 0x00000000U -#define LL_DMA_STREAM_1 0x00000001U -#define LL_DMA_STREAM_2 0x00000002U -#define LL_DMA_STREAM_3 0x00000003U -#define LL_DMA_STREAM_4 0x00000004U -#define LL_DMA_STREAM_5 0x00000005U -#define LL_DMA_STREAM_6 0x00000006U -#define LL_DMA_STREAM_7 0x00000007U -#define LL_DMA_STREAM_ALL 0xFFFF0000U -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DIRECTION DIRECTION - * @{ - */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MODE MODE - * @{ - */ -#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ -#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ -#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE - * @{ - */ -#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ -#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PERIPH PERIPH - * @{ - */ -#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ -#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MEMORY MEMORY - * @{ - */ -#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ -#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN - * @{ - */ -#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ -#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ -#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN - * @{ - */ -#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ -#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ -#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE - * @{ - */ -#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ -#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PRIORITY PRIORITY - * @{ - */ -#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ -#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ -#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ -#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_CHANNEL CHANNEL - * @{ - */ -#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ -#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ -#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ -#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ -#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ -#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ -#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ -#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ -#if defined(DMA_CHANNEL_SELECTION_8_15) -#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */ -#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */ -#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */ -#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */ -#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */ -#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */ -#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */ -#define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL /* Select Channel15 of DMA Instance */ -#endif /* DMA_CHANNEL_SELECTION_8_15 */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MBURST MBURST - * @{ - */ -#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ -#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ -#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ -#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PBURST PBURST - * @{ - */ -#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ -#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ -#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ -#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ -/** - * @} - */ - -/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE - * @{ - */ -#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ -#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 - * @{ - */ -#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ -#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ -#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ -#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ -#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ -#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD - * @{ - */ -#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ -#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ -#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ -#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM - * @{ - */ -#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ -#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros - * @{ - */ -/** - * @brief Write a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy - * @{ - */ -/** - * @brief Convert DMAx_Streamy into DMAx - * @param __STREAM_INSTANCE__ DMAx_Streamy - * @retval DMAx - */ -#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ -(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) - -/** - * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y - * @param __STREAM_INSTANCE__ DMAx_Streamy - * @retval LL_DMA_CHANNEL_y - */ -#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ -(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ - ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ - LL_DMA_STREAM_7) - -/** - * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy - * @param __DMA_INSTANCE__ DMAx - * @param __STREAM__ LL_DMA_STREAM_y - * @retval DMAx_Streamy - */ -#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ - DMA2_Stream7) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable DMA stream. - * @rmtoll CR EN LL_DMA_EnableStream - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); -} - -/** - * @brief Disable DMA stream. - * @rmtoll CR EN LL_DMA_DisableStream - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); -} - -/** - * @brief Check if DMA stream is enabled or disabled. - * @rmtoll CR EN LL_DMA_IsEnabledStream - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); -} - -/** - * @brief Configure all parameters linked to DMA transfer. - * @rmtoll CR DIR LL_DMA_ConfigTransfer\n - * CR CIRC LL_DMA_ConfigTransfer\n - * CR PINC LL_DMA_ConfigTransfer\n - * CR MINC LL_DMA_ConfigTransfer\n - * CR PSIZE LL_DMA_ConfigTransfer\n - * CR MSIZE LL_DMA_ConfigTransfer\n - * CR PL LL_DMA_ConfigTransfer\n - * CR PFCTRL LL_DMA_ConfigTransfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL - * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD - * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD - * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH - *@retval None - */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) -{ - MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, - DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, - Configuration); -} - -/** - * @brief Set Data transfer direction (read from peripheral or from memory). - * @rmtoll CR DIR LL_DMA_SetDataTransferDirection - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); -} - -/** - * @brief Get Data transfer direction (read from peripheral or from memory). - * @rmtoll CR DIR LL_DMA_GetDataTransferDirection - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); -} - -/** - * @brief Set DMA mode normal, circular or peripheral flow control. - * @rmtoll CR CIRC LL_DMA_SetMode\n - * CR PFCTRL LL_DMA_SetMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - * @arg @ref LL_DMA_MODE_PFCTRL - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); -} - -/** - * @brief Get DMA mode normal, circular or peripheral flow control. - * @rmtoll CR CIRC LL_DMA_GetMode\n - * CR PFCTRL LL_DMA_GetMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - * @arg @ref LL_DMA_MODE_PFCTRL - */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); -} - -/** - * @brief Set Peripheral increment mode. - * @rmtoll CR PINC LL_DMA_SetPeriphIncMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param IncrementMode This parameter can be one of the following values: - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); -} - -/** - * @brief Get Peripheral increment mode. - * @rmtoll CR PINC LL_DMA_GetPeriphIncMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_PERIPH_INCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); -} - -/** - * @brief Set Memory increment mode. - * @rmtoll CR MINC LL_DMA_SetMemoryIncMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param IncrementMode This parameter can be one of the following values: - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); -} - -/** - * @brief Get Memory increment mode. - * @rmtoll CR MINC LL_DMA_GetMemoryIncMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); -} - -/** - * @brief Set Peripheral size. - * @rmtoll CR PSIZE LL_DMA_SetPeriphSize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Size This parameter can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); -} - -/** - * @brief Get Peripheral size. - * @rmtoll CR PSIZE LL_DMA_GetPeriphSize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); -} - -/** - * @brief Set Memory size. - * @rmtoll CR MSIZE LL_DMA_SetMemorySize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Size This parameter can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); -} - -/** - * @brief Get Memory size. - * @rmtoll CR MSIZE LL_DMA_GetMemorySize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); -} - -/** - * @brief Set Peripheral increment offset size. - * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param OffsetSize This parameter can be one of the following values: - * @arg @ref LL_DMA_OFFSETSIZE_PSIZE - * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); -} - -/** - * @brief Get Peripheral increment offset size. - * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_OFFSETSIZE_PSIZE - * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 - */ -__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); -} - -/** - * @brief Set Stream priority level. - * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Priority This parameter can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); -} - -/** - * @brief Get Stream priority level. - * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - */ -__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); -} - -/** - * @brief Set Number of data to transfer. - * @rmtoll NDTR NDT LL_DMA_SetDataLength - * @note This action has no effect if - * stream is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param NbData Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); -} - -/** - * @brief Get Number of data to transfer. - * @rmtoll NDTR NDT LL_DMA_GetDataLength - * @note Once the stream is enabled, the return value indicate the - * remaining bytes to be transmitted. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); -} - -/** - * @brief Select Channel number associated to the Stream. - * @rmtoll CR CHSEL LL_DMA_SetChannelSelection - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 (*) - * @arg @ref LL_DMA_CHANNEL_9 (*) - * @arg @ref LL_DMA_CHANNEL_10 (*) - * @arg @ref LL_DMA_CHANNEL_11 (*) - * @arg @ref LL_DMA_CHANNEL_12 (*) - * @arg @ref LL_DMA_CHANNEL_13 (*) - * @arg @ref LL_DMA_CHANNEL_14 (*) - * @arg @ref LL_DMA_CHANNEL_15 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); -} - -/** - * @brief Get the Channel number associated to the Stream. - * @rmtoll CR CHSEL LL_DMA_GetChannelSelection - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 (*) - * @arg @ref LL_DMA_CHANNEL_9 (*) - * @arg @ref LL_DMA_CHANNEL_10 (*) - * @arg @ref LL_DMA_CHANNEL_11 (*) - * @arg @ref LL_DMA_CHANNEL_12 (*) - * @arg @ref LL_DMA_CHANNEL_13 (*) - * @arg @ref LL_DMA_CHANNEL_14 (*) - * @arg @ref LL_DMA_CHANNEL_15 (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); -} - -/** - * @brief Set Memory burst transfer configuration. - * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Mburst This parameter can be one of the following values: - * @arg @ref LL_DMA_MBURST_SINGLE - * @arg @ref LL_DMA_MBURST_INC4 - * @arg @ref LL_DMA_MBURST_INC8 - * @arg @ref LL_DMA_MBURST_INC16 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); -} - -/** - * @brief Get Memory burst transfer configuration. - * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MBURST_SINGLE - * @arg @ref LL_DMA_MBURST_INC4 - * @arg @ref LL_DMA_MBURST_INC8 - * @arg @ref LL_DMA_MBURST_INC16 - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); -} - -/** - * @brief Set Peripheral burst transfer configuration. - * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Pburst This parameter can be one of the following values: - * @arg @ref LL_DMA_PBURST_SINGLE - * @arg @ref LL_DMA_PBURST_INC4 - * @arg @ref LL_DMA_PBURST_INC8 - * @arg @ref LL_DMA_PBURST_INC16 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); -} - -/** - * @brief Get Peripheral burst transfer configuration. - * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PBURST_SINGLE - * @arg @ref LL_DMA_PBURST_INC4 - * @arg @ref LL_DMA_PBURST_INC8 - * @arg @ref LL_DMA_PBURST_INC16 - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); -} - -/** - * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. - * @rmtoll CR CT LL_DMA_SetCurrentTargetMem - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param CurrentMemory This parameter can be one of the following values: - * @arg @ref LL_DMA_CURRENTTARGETMEM0 - * @arg @ref LL_DMA_CURRENTTARGETMEM1 - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); -} - -/** - * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. - * @rmtoll CR CT LL_DMA_GetCurrentTargetMem - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_CURRENTTARGETMEM0 - * @arg @ref LL_DMA_CURRENTTARGETMEM1 - */ -__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); -} - -/** - * @brief Enable the double buffer mode. - * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); -} - -/** - * @brief Disable the double buffer mode. - * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); -} - -/** - * @brief Get FIFO status. - * @rmtoll FCR FS LL_DMA_GetFIFOStatus - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_FIFOSTATUS_0_25 - * @arg @ref LL_DMA_FIFOSTATUS_25_50 - * @arg @ref LL_DMA_FIFOSTATUS_50_75 - * @arg @ref LL_DMA_FIFOSTATUS_75_100 - * @arg @ref LL_DMA_FIFOSTATUS_EMPTY - * @arg @ref LL_DMA_FIFOSTATUS_FULL - */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); -} - -/** - * @brief Disable Fifo mode. - * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); -} - -/** - * @brief Enable Fifo mode. - * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); -} - -/** - * @brief Select FIFO threshold. - * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 - * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); -} - -/** - * @brief Get FIFO threshold. - * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 - * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL - */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); -} - -/** - * @brief Configure the FIFO . - * @rmtoll FCR FTH LL_DMA_ConfigFifo\n - * FCR DMDIS LL_DMA_ConfigFifo - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param FifoMode This parameter can be one of the following values: - * @arg @ref LL_DMA_FIFOMODE_ENABLE - * @arg @ref LL_DMA_FIFOMODE_DISABLE - * @param FifoThreshold This parameter can be one of the following values: - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 - * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 - * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); -} - -/** - * @brief Configure the Source and Destination addresses. - * @note This API must not be called when the DMA stream is enabled. - * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n - * PAR PA LL_DMA_ConfigAddresses - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param SrcAddress Between 0 to 0xFFFFFFFF - * @param DstAddress Between 0 to 0xFFFFFFFF - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) -{ - /* Direction Memory to Periph */ - if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) - { - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); - } - /* Direction Periph to Memory and Memory to Memory */ - else - { - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); - } -} - -/** - * @brief Set the Memory address. - * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param MemoryAddress Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); -} - -/** - * @brief Set the Peripheral address. - * @rmtoll PAR PA LL_DMA_SetPeriphAddress - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param PeriphAddress Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) -{ - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); -} - -/** - * @brief Get the Memory address. - * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) -{ - return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); -} - -/** - * @brief Get the Peripheral address. - * @rmtoll PAR PA LL_DMA_GetPeriphAddress - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) -{ - return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); -} - -/** - * @brief Set the Memory to Memory Source address. - * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param MemoryAddress Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); -} - -/** - * @brief Set the Memory to Memory Destination address. - * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param MemoryAddress Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) - { - WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); - } - -/** - * @brief Get the Memory to Memory Source address. - * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) - { - return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); - } - -/** - * @brief Get the Memory to Memory Destination address. - * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) -{ - return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); -} - -/** - * @brief Set Memory 1 address (used in case of Double buffer mode). - * @rmtoll M1AR M1A LL_DMA_SetMemory1Address - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param Address Between 0 to 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) -{ - MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address); -} - -/** - * @brief Get Memory 1 address (used in case of Double buffer mode). - * @rmtoll M1AR M1A LL_DMA_GetMemory1Address - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Stream 0 half transfer flag. - * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); -} - -/** - * @brief Get Stream 1 half transfer flag. - * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); -} - -/** - * @brief Get Stream 2 half transfer flag. - * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); -} - -/** - * @brief Get Stream 3 half transfer flag. - * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); -} - -/** - * @brief Get Stream 4 half transfer flag. - * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); -} - -/** - * @brief Get Stream 5 half transfer flag. - * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); -} - -/** - * @brief Get Stream 6 half transfer flag. - * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); -} - -/** - * @brief Get Stream 7 half transfer flag. - * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); -} - -/** - * @brief Get Stream 0 transfer complete flag. - * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); -} - -/** - * @brief Get Stream 1 transfer complete flag. - * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); -} - -/** - * @brief Get Stream 2 transfer complete flag. - * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); -} - -/** - * @brief Get Stream 3 transfer complete flag. - * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); -} - -/** - * @brief Get Stream 4 transfer complete flag. - * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); -} - -/** - * @brief Get Stream 5 transfer complete flag. - * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); -} - -/** - * @brief Get Stream 6 transfer complete flag. - * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); -} - -/** - * @brief Get Stream 7 transfer complete flag. - * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); -} - -/** - * @brief Get Stream 0 transfer error flag. - * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); -} - -/** - * @brief Get Stream 1 transfer error flag. - * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); -} - -/** - * @brief Get Stream 2 transfer error flag. - * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); -} - -/** - * @brief Get Stream 3 transfer error flag. - * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); -} - -/** - * @brief Get Stream 4 transfer error flag. - * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); -} - -/** - * @brief Get Stream 5 transfer error flag. - * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); -} - -/** - * @brief Get Stream 6 transfer error flag. - * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); -} - -/** - * @brief Get Stream 7 transfer error flag. - * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); -} - -/** - * @brief Get Stream 0 direct mode error flag. - * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); -} - -/** - * @brief Get Stream 1 direct mode error flag. - * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); -} - -/** - * @brief Get Stream 2 direct mode error flag. - * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); -} - -/** - * @brief Get Stream 3 direct mode error flag. - * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); -} - -/** - * @brief Get Stream 4 direct mode error flag. - * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); -} - -/** - * @brief Get Stream 5 direct mode error flag. - * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); -} - -/** - * @brief Get Stream 6 direct mode error flag. - * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); -} - -/** - * @brief Get Stream 7 direct mode error flag. - * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); -} - -/** - * @brief Get Stream 0 FIFO error flag. - * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); -} - -/** - * @brief Get Stream 1 FIFO error flag. - * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); -} - -/** - * @brief Get Stream 2 FIFO error flag. - * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); -} - -/** - * @brief Get Stream 3 FIFO error flag. - * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); -} - -/** - * @brief Get Stream 4 FIFO error flag. - * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); -} - -/** - * @brief Get Stream 5 FIFO error flag. - * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); -} - -/** - * @brief Get Stream 6 FIFO error flag. - * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); -} - -/** - * @brief Get Stream 7 FIFO error flag. - * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); -} - -/** - * @brief Clear Stream 0 half transfer flag. - * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); -} - -/** - * @brief Clear Stream 1 half transfer flag. - * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); -} - -/** - * @brief Clear Stream 2 half transfer flag. - * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); -} - -/** - * @brief Clear Stream 3 half transfer flag. - * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); -} - -/** - * @brief Clear Stream 4 half transfer flag. - * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); -} - -/** - * @brief Clear Stream 5 half transfer flag. - * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); -} - -/** - * @brief Clear Stream 6 half transfer flag. - * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); -} - -/** - * @brief Clear Stream 7 half transfer flag. - * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); -} - -/** - * @brief Clear Stream 0 transfer complete flag. - * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); -} - -/** - * @brief Clear Stream 1 transfer complete flag. - * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); -} - -/** - * @brief Clear Stream 2 transfer complete flag. - * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); -} - -/** - * @brief Clear Stream 3 transfer complete flag. - * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); -} - -/** - * @brief Clear Stream 4 transfer complete flag. - * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); -} - -/** - * @brief Clear Stream 5 transfer complete flag. - * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); -} - -/** - * @brief Clear Stream 6 transfer complete flag. - * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); -} - -/** - * @brief Clear Stream 7 transfer complete flag. - * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); -} - -/** - * @brief Clear Stream 0 transfer error flag. - * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); -} - -/** - * @brief Clear Stream 1 transfer error flag. - * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); -} - -/** - * @brief Clear Stream 2 transfer error flag. - * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); -} - -/** - * @brief Clear Stream 3 transfer error flag. - * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); -} - -/** - * @brief Clear Stream 4 transfer error flag. - * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); -} - -/** - * @brief Clear Stream 5 transfer error flag. - * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); -} - -/** - * @brief Clear Stream 6 transfer error flag. - * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); -} - -/** - * @brief Clear Stream 7 transfer error flag. - * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); -} - -/** - * @brief Clear Stream 0 direct mode error flag. - * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); -} - -/** - * @brief Clear Stream 1 direct mode error flag. - * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); -} - -/** - * @brief Clear Stream 2 direct mode error flag. - * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); -} - -/** - * @brief Clear Stream 3 direct mode error flag. - * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); -} - -/** - * @brief Clear Stream 4 direct mode error flag. - * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); -} - -/** - * @brief Clear Stream 5 direct mode error flag. - * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); -} - -/** - * @brief Clear Stream 6 direct mode error flag. - * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); -} - -/** - * @brief Clear Stream 7 direct mode error flag. - * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); -} - -/** - * @brief Clear Stream 0 FIFO error flag. - * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); -} - -/** - * @brief Clear Stream 1 FIFO error flag. - * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); -} - -/** - * @brief Clear Stream 2 FIFO error flag. - * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); -} - -/** - * @brief Clear Stream 3 FIFO error flag. - * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); -} - -/** - * @brief Clear Stream 4 FIFO error flag. - * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); -} - -/** - * @brief Clear Stream 5 FIFO error flag. - * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); -} - -/** - * @brief Clear Stream 6 FIFO error flag. - * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); -} - -/** - * @brief Clear Stream 7 FIFO error flag. - * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable Half transfer interrupt. - * @rmtoll CR HTIE LL_DMA_EnableIT_HT - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); -} - -/** - * @brief Enable Transfer error interrupt. - * @rmtoll CR TEIE LL_DMA_EnableIT_TE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); -} - -/** - * @brief Enable Transfer complete interrupt. - * @rmtoll CR TCIE LL_DMA_EnableIT_TC - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); -} - -/** - * @brief Enable Direct mode error interrupt. - * @rmtoll CR DMEIE LL_DMA_EnableIT_DME - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); -} - -/** - * @brief Enable FIFO error interrupt. - * @rmtoll FCR FEIE LL_DMA_EnableIT_FE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); -} - -/** - * @brief Disable Half transfer interrupt. - * @rmtoll CR HTIE LL_DMA_DisableIT_HT - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); -} - -/** - * @brief Disable Transfer error interrupt. - * @rmtoll CR TEIE LL_DMA_DisableIT_TE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); -} - -/** - * @brief Disable Transfer complete interrupt. - * @rmtoll CR TCIE LL_DMA_DisableIT_TC - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); -} - -/** - * @brief Disable Direct mode error interrupt. - * @rmtoll CR DMEIE LL_DMA_DisableIT_DME - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); -} - -/** - * @brief Disable FIFO error interrupt. - * @rmtoll FCR FEIE LL_DMA_DisableIT_FE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); -} - -/** - * @brief Check if Half transfer interrup is enabled. - * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); -} - -/** - * @brief Check if Transfer error nterrup is enabled. - * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); -} - -/** - * @brief Check if Transfer complete interrup is enabled. - * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); -} - -/** - * @brief Check if Direct mode error interrupt is enabled. - * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); -} - -/** - * @brief Check if FIFO error interrup is enabled. - * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) -{ - return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 || DMA2 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_DMA_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_dma.h + * @author MCD Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_DMA_H +#define __STM32F7xx_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (DMA1) || defined (DMA2) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ +static const uint8_t STREAM_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), + (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) +}; + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Constants DMA Private Constants + * @{ + */ +#if defined(DMA_SxCR_CHSEL_3) +#define DMA_CHANNEL_SELECTION_8_15 +#endif /* DMA_SxCR_CHSEL_3 */ +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Stream + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Channel; /*!< Specifies the peripheral channel. + This parameter can be a value of @ref DMA_LL_EC_CHANNEL + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ + + uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. + This parameter can be a value of @ref DMA_LL_FIFOMODE + @note The Direct mode (FIFO mode disabled) cannot be used if the + memory-to-memory data transfer is configured on the selected stream + + This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ + + uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. + This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ + + uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_MBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ + + uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. + It specifies the amount of data to be transferred in a single non interruptible + transaction. + This parameter can be a value of @ref DMA_LL_EC_PBURST + @note The burst mode is possible only if the address Increment mode is enabled. + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ + +/** @defgroup DMA_LL_EC_STREAM STREAM + * @{ + */ +#define LL_DMA_STREAM_0 0x00000000U +#define LL_DMA_STREAM_1 0x00000001U +#define LL_DMA_STREAM_2 0x00000002U +#define LL_DMA_STREAM_3 0x00000003U +#define LL_DMA_STREAM_4 0x00000004U +#define LL_DMA_STREAM_5 0x00000005U +#define LL_DMA_STREAM_6 0x00000006U +#define LL_DMA_STREAM_7 0x00000007U +#define LL_DMA_STREAM_ALL 0xFFFF0000U +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION DIRECTION + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE MODE + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ +#define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE + * @{ + */ +#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ +#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH PERIPH + * @{ + */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +#define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY MEMORY + * @{ + */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +#define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE + * @{ + */ +#define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ +#define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY PRIORITY + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ +#define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ +#define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ +#define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ +#define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ +#define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ +#define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ +#define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ +#if defined(DMA_CHANNEL_SELECTION_8_15) +#define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */ +#define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */ +#define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */ +#define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */ +#define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */ +#define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */ +#define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */ +#define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL /* Select Channel15 of DMA Instance */ +#endif /* DMA_CHANNEL_SELECTION_8_15 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MBURST MBURST + * @{ + */ +#define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ +#define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ +#define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ +#define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PBURST PBURST + * @{ + */ +#define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ +#define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ +#define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ +#define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE + * @{ + */ +#define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ +#define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 + * @{ + */ +#define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ +#define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ +#define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ +#define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ +#define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ +#define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD + * @{ + */ +#define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ +#define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ +#define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ +#define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM + * @{ + */ +#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ +#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy + * @{ + */ +/** + * @brief Convert DMAx_Streamy into DMAx + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) + +/** + * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y + * @param __STREAM_INSTANCE__ DMAx_Streamy + * @retval LL_DMA_CHANNEL_y + */ +#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ +(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ + ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ + LL_DMA_STREAM_7) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy + * @param __DMA_INSTANCE__ DMAx + * @param __STREAM__ LL_DMA_STREAM_y + * @retval DMAx_Streamy + */ +#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ + DMA2_Stream7) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA stream. + * @rmtoll CR EN LL_DMA_EnableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); +} + +/** + * @brief Disable DMA stream. + * @rmtoll CR EN LL_DMA_DisableStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); +} + +/** + * @brief Check if DMA stream is enabled or disabled. + * @rmtoll CR EN LL_DMA_IsEnabledStream + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); +} + +/** + * @brief Configure all parameters linked to DMA transfer. + * @rmtoll CR DIR LL_DMA_ConfigTransfer\n + * CR CIRC LL_DMA_ConfigTransfer\n + * CR PINC LL_DMA_ConfigTransfer\n + * CR MINC LL_DMA_ConfigTransfer\n + * CR PSIZE LL_DMA_ConfigTransfer\n + * CR MSIZE LL_DMA_ConfigTransfer\n + * CR PL LL_DMA_ConfigTransfer\n + * CR PFCTRL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + *@retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, + DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CR DIR LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); +} + +/** + * @brief Set DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_SetMode\n + * CR PFCTRL LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); +} + +/** + * @brief Get DMA mode normal, circular or peripheral flow control. + * @rmtoll CR CIRC LL_DMA_GetMode\n + * CR PFCTRL LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_MODE_PFCTRL + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_PERIPH_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param IncrementMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Size This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); +} + +/** + * @brief Get Memory size. + * @rmtoll CR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); +} + +/** + * @brief Set Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param OffsetSize This parameter can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); +} + +/** + * @brief Get Peripheral increment offset size. + * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_OFFSETSIZE_PSIZE + * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 + */ +__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); +} + +/** + * @brief Set Stream priority level. + * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); +} + +/** + * @brief Get Stream priority level. + * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_SetDataLength + * @note This action has no effect if + * stream is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param NbData Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @rmtoll NDTR NDT LL_DMA_GetDataLength + * @note Once the stream is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); +} + +/** + * @brief Select Channel number associated to the Stream. + * @rmtoll CR CHSEL LL_DMA_SetChannelSelection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @arg @ref LL_DMA_CHANNEL_12 (*) + * @arg @ref LL_DMA_CHANNEL_13 (*) + * @arg @ref LL_DMA_CHANNEL_14 (*) + * @arg @ref LL_DMA_CHANNEL_15 (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); +} + +/** + * @brief Get the Channel number associated to the Stream. + * @rmtoll CR CHSEL LL_DMA_GetChannelSelection + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_0 + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @arg @ref LL_DMA_CHANNEL_4 + * @arg @ref LL_DMA_CHANNEL_5 + * @arg @ref LL_DMA_CHANNEL_6 + * @arg @ref LL_DMA_CHANNEL_7 + * @arg @ref LL_DMA_CHANNEL_8 (*) + * @arg @ref LL_DMA_CHANNEL_9 (*) + * @arg @ref LL_DMA_CHANNEL_10 (*) + * @arg @ref LL_DMA_CHANNEL_11 (*) + * @arg @ref LL_DMA_CHANNEL_12 (*) + * @arg @ref LL_DMA_CHANNEL_13 (*) + * @arg @ref LL_DMA_CHANNEL_14 (*) + * @arg @ref LL_DMA_CHANNEL_15 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); +} + +/** + * @brief Set Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Mburst This parameter can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); +} + +/** + * @brief Get Memory burst transfer configuration. + * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MBURST_SINGLE + * @arg @ref LL_DMA_MBURST_INC4 + * @arg @ref LL_DMA_MBURST_INC8 + * @arg @ref LL_DMA_MBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); +} + +/** + * @brief Set Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Pburst This parameter can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); +} + +/** + * @brief Get Peripheral burst transfer configuration. + * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PBURST_SINGLE + * @arg @ref LL_DMA_PBURST_INC4 + * @arg @ref LL_DMA_PBURST_INC8 + * @arg @ref LL_DMA_PBURST_INC16 + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_SetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param CurrentMemory This parameter can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); +} + +/** + * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. + * @rmtoll CR CT LL_DMA_GetCurrentTargetMem + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_CURRENTTARGETMEM0 + * @arg @ref LL_DMA_CURRENTTARGETMEM1 + */ +__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); +} + +/** + * @brief Enable the double buffer mode. + * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Disable the double buffer mode. + * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); +} + +/** + * @brief Get FIFO status. + * @rmtoll FCR FS LL_DMA_GetFIFOStatus + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOSTATUS_0_25 + * @arg @ref LL_DMA_FIFOSTATUS_25_50 + * @arg @ref LL_DMA_FIFOSTATUS_50_75 + * @arg @ref LL_DMA_FIFOSTATUS_75_100 + * @arg @ref LL_DMA_FIFOSTATUS_EMPTY + * @arg @ref LL_DMA_FIFOSTATUS_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); +} + +/** + * @brief Disable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Enable Fifo mode. + * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); +} + +/** + * @brief Select FIFO threshold. + * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); +} + +/** + * @brief Get FIFO threshold. + * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + */ +__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); +} + +/** + * @brief Configure the FIFO . + * @rmtoll FCR FTH LL_DMA_ConfigFifo\n + * FCR DMDIS LL_DMA_ConfigFifo + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param FifoMode This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOMODE_ENABLE + * @arg @ref LL_DMA_FIFOMODE_DISABLE + * @param FifoThreshold This parameter can be one of the following values: + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 + * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 + * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) +{ + MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA stream is enabled. + * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n + * PAR PA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param SrcAddress Between 0 to 0xFFFFFFFF + * @param DstAddress Between 0 to 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @rmtoll PAR PA LL_DMA_SetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param PeriphAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); +} + +/** + * @brief Get the Memory address. + * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); +} + +/** + * @brief Get the Peripheral address. + * @rmtoll PAR PA LL_DMA_GetPeriphAddress + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param MemoryAddress Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) + { + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); + } + +/** + * @brief Get the Memory to Memory Source address. + * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) + { + return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); + } + +/** + * @brief Get the Memory to Memory Destination address. + * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) +{ + return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); +} + +/** + * @brief Set Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_SetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @param Address Between 0 to 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) +{ + WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, Address); +} + +/** + * @brief Get Memory 1 address (used in case of Double buffer mode). + * @rmtoll M1AR M1A LL_DMA_GetMemory1Address + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval Between 0 to 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Stream 0 half transfer flag. + * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); +} + +/** + * @brief Get Stream 1 half transfer flag. + * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); +} + +/** + * @brief Get Stream 2 half transfer flag. + * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); +} + +/** + * @brief Get Stream 3 half transfer flag. + * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); +} + +/** + * @brief Get Stream 4 half transfer flag. + * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); +} + +/** + * @brief Get Stream 5 half transfer flag. + * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); +} + +/** + * @brief Get Stream 6 half transfer flag. + * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); +} + +/** + * @brief Get Stream 7 half transfer flag. + * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); +} + +/** + * @brief Get Stream 0 transfer complete flag. + * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); +} + +/** + * @brief Get Stream 1 transfer complete flag. + * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); +} + +/** + * @brief Get Stream 2 transfer complete flag. + * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); +} + +/** + * @brief Get Stream 3 transfer complete flag. + * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); +} + +/** + * @brief Get Stream 4 transfer complete flag. + * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); +} + +/** + * @brief Get Stream 5 transfer complete flag. + * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); +} + +/** + * @brief Get Stream 6 transfer complete flag. + * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); +} + +/** + * @brief Get Stream 7 transfer complete flag. + * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); +} + +/** + * @brief Get Stream 0 transfer error flag. + * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); +} + +/** + * @brief Get Stream 1 transfer error flag. + * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); +} + +/** + * @brief Get Stream 2 transfer error flag. + * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); +} + +/** + * @brief Get Stream 3 transfer error flag. + * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); +} + +/** + * @brief Get Stream 4 transfer error flag. + * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); +} + +/** + * @brief Get Stream 5 transfer error flag. + * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); +} + +/** + * @brief Get Stream 6 transfer error flag. + * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); +} + +/** + * @brief Get Stream 7 transfer error flag. + * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); +} + +/** + * @brief Get Stream 0 direct mode error flag. + * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); +} + +/** + * @brief Get Stream 1 direct mode error flag. + * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); +} + +/** + * @brief Get Stream 2 direct mode error flag. + * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); +} + +/** + * @brief Get Stream 3 direct mode error flag. + * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); +} + +/** + * @brief Get Stream 4 direct mode error flag. + * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); +} + +/** + * @brief Get Stream 5 direct mode error flag. + * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); +} + +/** + * @brief Get Stream 6 direct mode error flag. + * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); +} + +/** + * @brief Get Stream 7 direct mode error flag. + * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); +} + +/** + * @brief Get Stream 0 FIFO error flag. + * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); +} + +/** + * @brief Get Stream 1 FIFO error flag. + * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); +} + +/** + * @brief Get Stream 2 FIFO error flag. + * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); +} + +/** + * @brief Get Stream 3 FIFO error flag. + * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); +} + +/** + * @brief Get Stream 4 FIFO error flag. + * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); +} + +/** + * @brief Get Stream 5 FIFO error flag. + * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); +} + +/** + * @brief Get Stream 6 FIFO error flag. + * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); +} + +/** + * @brief Get Stream 7 FIFO error flag. + * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); +} + +/** + * @brief Clear Stream 0 half transfer flag. + * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); +} + +/** + * @brief Clear Stream 1 half transfer flag. + * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); +} + +/** + * @brief Clear Stream 2 half transfer flag. + * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); +} + +/** + * @brief Clear Stream 3 half transfer flag. + * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); +} + +/** + * @brief Clear Stream 4 half transfer flag. + * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); +} + +/** + * @brief Clear Stream 5 half transfer flag. + * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); +} + +/** + * @brief Clear Stream 6 half transfer flag. + * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); +} + +/** + * @brief Clear Stream 7 half transfer flag. + * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); +} + +/** + * @brief Clear Stream 0 transfer complete flag. + * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); +} + +/** + * @brief Clear Stream 1 transfer complete flag. + * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); +} + +/** + * @brief Clear Stream 2 transfer complete flag. + * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); +} + +/** + * @brief Clear Stream 3 transfer complete flag. + * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); +} + +/** + * @brief Clear Stream 4 transfer complete flag. + * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); +} + +/** + * @brief Clear Stream 5 transfer complete flag. + * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); +} + +/** + * @brief Clear Stream 6 transfer complete flag. + * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); +} + +/** + * @brief Clear Stream 7 transfer complete flag. + * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); +} + +/** + * @brief Clear Stream 0 transfer error flag. + * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); +} + +/** + * @brief Clear Stream 1 transfer error flag. + * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); +} + +/** + * @brief Clear Stream 2 transfer error flag. + * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); +} + +/** + * @brief Clear Stream 3 transfer error flag. + * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); +} + +/** + * @brief Clear Stream 4 transfer error flag. + * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); +} + +/** + * @brief Clear Stream 5 transfer error flag. + * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); +} + +/** + * @brief Clear Stream 6 transfer error flag. + * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); +} + +/** + * @brief Clear Stream 7 transfer error flag. + * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); +} + +/** + * @brief Clear Stream 0 direct mode error flag. + * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); +} + +/** + * @brief Clear Stream 1 direct mode error flag. + * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); +} + +/** + * @brief Clear Stream 2 direct mode error flag. + * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); +} + +/** + * @brief Clear Stream 3 direct mode error flag. + * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); +} + +/** + * @brief Clear Stream 4 direct mode error flag. + * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); +} + +/** + * @brief Clear Stream 5 direct mode error flag. + * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); +} + +/** + * @brief Clear Stream 6 direct mode error flag. + * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); +} + +/** + * @brief Clear Stream 7 direct mode error flag. + * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); +} + +/** + * @brief Clear Stream 0 FIFO error flag. + * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); +} + +/** + * @brief Clear Stream 1 FIFO error flag. + * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); +} + +/** + * @brief Clear Stream 2 FIFO error flag. + * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); +} + +/** + * @brief Clear Stream 3 FIFO error flag. + * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); +} + +/** + * @brief Clear Stream 4 FIFO error flag. + * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); +} + +/** + * @brief Clear Stream 5 FIFO error flag. + * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); +} + +/** + * @brief Clear Stream 6 FIFO error flag. + * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); +} + +/** + * @brief Clear Stream 7 FIFO error flag. + * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Enable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_EnableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Enable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_EnableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); +} + +/** + * @brief Disable Direct mode error interrupt. + * @rmtoll CR DMEIE LL_DMA_DisableIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); +} + +/** + * @brief Disable FIFO error interrupt. + * @rmtoll FCR FEIE LL_DMA_DisableIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); +} + +/** + * @brief Check if Half transfer interrup is enabled. + * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); +} + +/** + * @brief Check if Transfer error nterrup is enabled. + * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); +} + +/** + * @brief Check if Transfer complete interrup is enabled. + * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); +} + +/** + * @brief Check if Direct mode error interrupt is enabled. + * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); +} + +/** + * @brief Check if FIFO error interrup is enabled. + * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE + * @param DMAx DMAx Instance + * @param Stream This parameter can be one of the following values: + * @arg @ref LL_DMA_STREAM_0 + * @arg @ref LL_DMA_STREAM_1 + * @arg @ref LL_DMA_STREAM_2 + * @arg @ref LL_DMA_STREAM_3 + * @arg @ref LL_DMA_STREAM_4 + * @arg @ref LL_DMA_STREAM_5 + * @arg @ref LL_DMA_STREAM_6 + * @arg @ref LL_DMA_STREAM_7 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) +{ + return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_DMA_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h deleted file mode 100644 index 896eccc2..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_dma2d.h +++ /dev/null @@ -1,2117 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_dma2d.h - * @author MCD Application Team - * @brief Header file of DMA2D LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_DMA2D_H -#define STM32F7xx_LL_DMA2D_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (DMA2D) - -/** @defgroup DMA2D_LL DMA2D - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros - * @{ - */ - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures - * @{ - */ - -/** - * @brief LL DMA2D Init Structure Definition - */ -typedef struct -{ - uint32_t Mode; /*!< Specifies the DMA2D transfer mode. - - This parameter can be one value of @ref DMA2D_LL_EC_MODE. - - This parameter can be modified afterwards, - using unitary function @ref LL_DMA2D_SetMode(). */ - - uint32_t ColorMode; /*!< Specifies the color format of the output image. - - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. - - This parameter can be modified afterwards using, - unitary function @ref LL_DMA2D_SetOutputColorMode(). */ - - uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - - This parameter can be modified afterwards, - using unitary function @ref LL_DMA2D_SetOutputColor() or configuration - function @ref LL_DMA2D_ConfigOutputColor(). */ - - uint32_t OutputGreen; /*!< Specifies the Green value of the output image. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - - This parameter can be modified afterwards - using unitary function @ref LL_DMA2D_SetOutputColor() or configuration - function @ref LL_DMA2D_ConfigOutputColor(). */ - - uint32_t OutputRed; /*!< Specifies the Red value of the output image. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - - This parameter can be modified afterwards - using unitary function @ref LL_DMA2D_SetOutputColor() or configuration - function @ref LL_DMA2D_ConfigOutputColor(). */ - - uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - - This parameter is not considered if RGB888 or RGB565 color mode is selected. - - This parameter can be modified afterwards using, - unitary function @ref LL_DMA2D_SetOutputColor() or configuration - function @ref LL_DMA2D_ConfigOutputColor(). */ - - uint32_t OutputMemoryAddress; /*!< Specifies the memory address. - - This parameter must be a number between: - Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. - - This parameter can be modified afterwards, - using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ - - - - uint32_t LineOffset; /*!< Specifies the output line offset value. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. - - This parameter can be modified afterwards, - using unitary function @ref LL_DMA2D_SetLineOffset(). */ - - uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. - - This parameter must be a number between: - Min_Data = 0x0000 and Max_Data = 0xFFFF. - - This parameter can be modified afterwards, - using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ - - uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. - - This parameter can be modified afterwards using, - unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ - -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode. - - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. - - This parameter can be modified afterwards using, - unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ - - uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode. - - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP. - - This parameter can be modified afterwards using, - unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - -} LL_DMA2D_InitTypeDef; - -/** - * @brief LL DMA2D Layer Configuration Structure Definition - */ -typedef struct -{ - uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. - - This parameter must be a number between: - Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, - - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */ - - uint32_t LineOffset; /*!< Specifies the foreground or background line offset value. - - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer, - - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */ - - uint32_t ColorMode; /*!< Specifies the foreground or background color mode. - - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer, - - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */ - - uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode. - - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer, - - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */ - - uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer, - - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */ - - uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode. - - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer, - - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */ - - uint32_t Alpha; /*!< Specifies the foreground or background Alpha value. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer, - - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */ - - uint32_t Blue; /*!< Specifies the foreground or background Blue color value. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer, - - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */ - - uint32_t Green; /*!< Specifies the foreground or background Green color value. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer, - - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */ - - uint32_t Red; /*!< Specifies the foreground or background Red color value. - - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer, - - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ - - uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. - - This parameter must be a number between: - Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, - - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */ - -#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode. - - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer, - - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */ - - uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode. - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP . - - This parameter can be modified afterwards using unitary functions - - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, - - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - -} LL_DMA2D_LayerCfgTypeDef; - -/** - * @brief LL DMA2D Output Color Structure Definition - */ -typedef struct -{ - uint32_t ColorMode; /*!< Specifies the color format of the output image. - - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. - - This parameter can be modified afterwards using - unitary function @ref LL_DMA2D_SetOutputColorMode(). */ - - uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - - This parameter can be modified afterwards using, - unitary function @ref LL_DMA2D_SetOutputColor() or configuration - function @ref LL_DMA2D_ConfigOutputColor(). */ - - uint32_t OutputGreen; /*!< Specifies the Green value of the output image. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between - Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - - This parameter can be modified afterwards, - using unitary function @ref LL_DMA2D_SetOutputColor() or configuration - function @ref LL_DMA2D_ConfigOutputColor(). */ - - uint32_t OutputRed; /*!< Specifies the Red value of the output image. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - - This parameter can be modified afterwards, - using unitary function @ref LL_DMA2D_SetOutputColor() or configuration - function @ref LL_DMA2D_ConfigOutputColor(). */ - - uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. - - This parameter must be a number between: - Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. - - This parameter is not considered if RGB888 or RGB565 color mode is selected. - - This parameter can be modified afterwards, - using unitary function @ref LL_DMA2D_SetOutputColor() or configuration - function @ref LL_DMA2D_ConfigOutputColor(). */ - -} LL_DMA2D_ColorTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants - * @{ - */ - -/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_DMA2D_ReadReg function - * @{ - */ -#define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ -#define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ -#define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ -#define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ -#define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ -#define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ -/** - * @} - */ - -/** @defgroup DMA2D_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions - * @{ - */ -#define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ -#define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ -#define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ -#define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ -#define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ -#define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ -/** - * @} - */ - -/** @defgroup DMA2D_LL_EC_MODE Mode - * @{ - */ -#define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ -#define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ -#define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ -#define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ -/** - * @} - */ - -/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode - * @{ - */ -#define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ -#define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */ -#define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */ -#define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */ -#define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */ -/** - * @} - */ - -/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode - * @{ - */ -#define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ -#define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */ -#define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */ -#define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */ -#define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */ -#define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */ -#define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */ -#define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */ -#define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */ -#define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */ -#define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */ -/** - * @} - */ - -/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode - * @{ - */ -#define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ -#define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by - programmed alpha value */ -#define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by - programmed alpha value with, - original alpha channel value */ -/** - * @} - */ - - -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) -/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap - * @{ - */ -#define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */ -#define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */ -/** - * @} - */ - -/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion - * @{ - */ -#define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */ -#define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */ -/** - * @} - */ - -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - -/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode - * @{ - */ -#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ -#define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */ -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros - * @{ - */ - -/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in DMA2D register. - * @param __INSTANCE__ DMA2D Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DMA2D register. - * @param __INSTANCE__ DMA2D Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions - * @{ - */ - -/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions - * @{ - */ - -/** - * @brief Start a DMA2D transfer. - * @rmtoll CR START LL_DMA2D_Start - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->CR, DMA2D_CR_START); -} - -/** - * @brief Indicate if a DMA2D transfer is ongoing. - * @rmtoll CR START LL_DMA2D_IsTransferOngoing - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); -} - -/** - * @brief Suspend DMA2D transfer. - * @note This API can be used to suspend automatic foreground or background CLUT loading. - * @rmtoll CR SUSP LL_DMA2D_Suspend - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx) -{ - MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); -} - -/** - * @brief Resume DMA2D transfer. - * @note This API can be used to resume automatic foreground or background CLUT loading. - * @rmtoll CR SUSP LL_DMA2D_Resume - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) -{ - CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START); -} - -/** - * @brief Indicate if DMA2D transfer is suspended. - * @note This API can be used to indicate whether or not automatic foreground or - * background CLUT loading is suspended. - * @rmtoll CR SUSP LL_DMA2D_IsSuspended - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); -} - -/** - * @brief Abort DMA2D transfer. - * @note This API can be used to abort automatic foreground or background CLUT loading. - * @rmtoll CR ABORT LL_DMA2D_Abort - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) -{ - MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); -} - -/** - * @brief Indicate if DMA2D transfer is aborted. - * @note This API can be used to indicate whether or not automatic foreground or - * background CLUT loading is aborted. - * @rmtoll CR ABORT LL_DMA2D_IsAborted - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); -} - -/** - * @brief Set DMA2D mode. - * @rmtoll CR MODE LL_DMA2D_SetMode - * @param DMA2Dx DMA2D Instance - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_MODE_M2M - * @arg @ref LL_DMA2D_MODE_M2M_PFC - * @arg @ref LL_DMA2D_MODE_M2M_BLEND - * @arg @ref LL_DMA2D_MODE_R2M - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) -{ - MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode); -} - -/** - * @brief Return DMA2D mode - * @rmtoll CR MODE LL_DMA2D_GetMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_MODE_M2M - * @arg @ref LL_DMA2D_MODE_M2M_PFC - * @arg @ref LL_DMA2D_MODE_M2M_BLEND - * @arg @ref LL_DMA2D_MODE_R2M - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); -} - -/** - * @brief Set DMA2D output color mode. - * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode - * @param DMA2Dx DMA2D Instance - * @param ColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) -{ - MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode); -} - -/** - * @brief Return DMA2D output color mode. - * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); -} - -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) -/** - * @brief Set DMA2D output Red Blue swap mode. - * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode - * @param DMA2Dx DMA2D Instance - * @param RBSwapMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_RB_MODE_REGULAR - * @arg @ref LL_DMA2D_RB_MODE_SWAP - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) -{ - MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode); -} - -/** - * @brief Return DMA2D output Red Blue swap mode. - * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_RB_MODE_REGULAR - * @arg @ref LL_DMA2D_RB_MODE_SWAP - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); -} - -/** - * @brief Set DMA2D output alpha inversion mode. - * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode - * @param DMA2Dx DMA2D Instance - * @param AlphaInversionMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_REGULAR - * @arg @ref LL_DMA2D_ALPHA_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) -{ - MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode); -} - -/** - * @brief Return DMA2D output alpha inversion mode. - * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_REGULAR - * @arg @ref LL_DMA2D_ALPHA_INVERTED - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); -} - -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - - -/** - * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). - * @rmtoll OOR LO LL_DMA2D_SetLineOffset - * @param DMA2Dx DMA2D Instance - * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) -{ - MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset); -} - -/** - * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). - * @rmtoll OOR LO LL_DMA2D_GetLineOffset - * @param DMA2Dx DMA2D Instance - * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); -} - -/** - * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits). - * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines - * @param DMA2Dx DMA2D Instance - * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines) -{ - MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos)); -} - -/** - * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits) - * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines - * @param DMA2Dx DMA2D Instance - * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); -} - -/** - * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits). - * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines - * @param DMA2Dx DMA2D Instance - * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines) -{ - MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines); -} - -/** - * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits). - * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines - * @param DMA2Dx DMA2D Instance - * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); -} - -/** - * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr - * @param DMA2Dx DMA2D Instance - * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress) -{ - LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress); -} - -/** - * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr - * @param DMA2Dx DMA2D Instance - * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); -} - -/** - * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits). - * @note Output color format depends on output color mode, ARGB8888, RGB888, - * RGB565, ARGB1555 or ARGB4444. - * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting - * with respect to color mode is not done by the user code. - * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n - * OCOLR GREEN LL_DMA2D_SetOutputColor\n - * OCOLR RED LL_DMA2D_SetOutputColor\n - * OCOLR ALPHA LL_DMA2D_SetOutputColor - * @param DMA2Dx DMA2D Instance - * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) -{ - MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ - OutputColor); -} - -/** - * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits). - * @note Alpha channel and red, green, blue color values must be retrieved from the returned - * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444) - * as set by @ref LL_DMA2D_SetOutputColorMode. - * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n - * OCOLR GREEN LL_DMA2D_GetOutputColor\n - * OCOLR RED LL_DMA2D_GetOutputColor\n - * OCOLR ALPHA LL_DMA2D_GetOutputColor - * @param DMA2Dx DMA2D Instance - * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ - (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); -} - -/** - * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits). - * @rmtoll LWR LW LL_DMA2D_SetLineWatermark - * @param DMA2Dx DMA2D Instance - * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark) -{ - MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark); -} - -/** - * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits). - * @rmtoll LWR LW LL_DMA2D_GetLineWatermark - * @param DMA2Dx DMA2D Instance - * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); -} - -/** - * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits). - * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime - * @param DMA2Dx DMA2D Instance - * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime) -{ - MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos)); -} - -/** - * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits). - * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime - * @param DMA2Dx DMA2D Instance - * @retval Dead time value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); -} - -/** - * @brief Enable DMA2D dead time functionality. - * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); -} - -/** - * @brief Disable DMA2D dead time functionality. - * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) -{ - CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); -} - -/** - * @brief Indicate if DMA2D dead time functionality is enabled. - * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); -} - -/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions - * @{ - */ - -/** - * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr - * @param DMA2Dx DMA2D Instance - * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) -{ - LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress); -} - -/** - * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr - * @param DMA2Dx DMA2D Instance - * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); -} - -/** - * @brief Enable DMA2D foreground CLUT loading. - * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START); -} - -/** - * @brief Indicate if DMA2D foreground CLUT loading is enabled. - * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); -} - -/** - * @brief Set DMA2D foreground color mode. - * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode - * @param DMA2Dx DMA2D Instance - * @param ColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 - * @arg @ref LL_DMA2D_INPUT_MODE_L8 - * @arg @ref LL_DMA2D_INPUT_MODE_AL44 - * @arg @ref LL_DMA2D_INPUT_MODE_AL88 - * @arg @ref LL_DMA2D_INPUT_MODE_L4 - * @arg @ref LL_DMA2D_INPUT_MODE_A8 - * @arg @ref LL_DMA2D_INPUT_MODE_A4 - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) -{ - MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode); -} - -/** - * @brief Return DMA2D foreground color mode. - * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 - * @arg @ref LL_DMA2D_INPUT_MODE_L8 - * @arg @ref LL_DMA2D_INPUT_MODE_AL44 - * @arg @ref LL_DMA2D_INPUT_MODE_AL88 - * @arg @ref LL_DMA2D_INPUT_MODE_L4 - * @arg @ref LL_DMA2D_INPUT_MODE_A8 - * @arg @ref LL_DMA2D_INPUT_MODE_A4 - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); -} - -/** - * @brief Set DMA2D foreground alpha mode. - * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode - * @param DMA2Dx DMA2D Instance - * @param AphaMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF - * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE - * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) -{ - MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode); -} - -/** - * @brief Return DMA2D foreground alpha mode. - * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF - * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE - * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); -} - -/** - * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). - * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha - * @param DMA2Dx DMA2D Instance - * @param Alpha Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) -{ - MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos)); -} - -/** - * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). - * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha - * @param DMA2Dx DMA2D Instance - * @retval Alpha value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); -} - -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) -/** - * @brief Set DMA2D foreground Red Blue swap mode. - * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode - * @param DMA2Dx DMA2D Instance - * @param RBSwapMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_RB_MODE_REGULAR - * @arg @ref LL_DMA2D_RB_MODE_SWAP - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) -{ - MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode); -} - -/** - * @brief Return DMA2D foreground Red Blue swap mode. - * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_RB_MODE_REGULAR - * @arg @ref LL_DMA2D_RB_MODE_SWAP - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); -} - -/** - * @brief Set DMA2D foreground alpha inversion mode. - * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode - * @param DMA2Dx DMA2D Instance - * @param AlphaInversionMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_REGULAR - * @arg @ref LL_DMA2D_ALPHA_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) -{ - MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode); -} - -/** - * @brief Return DMA2D foreground alpha inversion mode. - * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_REGULAR - * @arg @ref LL_DMA2D_ALPHA_INVERTED - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); -} - -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - -/** - * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). - * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset - * @param DMA2Dx DMA2D Instance - * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) -{ - MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset); -} - -/** - * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). - * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset - * @param DMA2Dx DMA2D Instance - * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); -} - -/** - * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits). - * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor - * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor - * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor - * @param DMA2Dx DMA2D Instance - * @param Red Value between Min_Data=0 and Max_Data=0xFF - * @param Green Value between Min_Data=0 and Max_Data=0xFF - * @param Blue Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) -{ - MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \ - ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue)); -} - -/** - * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). - * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor - * @param DMA2Dx DMA2D Instance - * @param Red Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) -{ - MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos)); -} - -/** - * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). - * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor - * @param DMA2Dx DMA2D Instance - * @retval Red color value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); -} - -/** - * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). - * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor - * @param DMA2Dx DMA2D Instance - * @param Green Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) -{ - MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos)); -} - -/** - * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). - * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor - * @param DMA2Dx DMA2D Instance - * @retval Green color value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); -} - -/** - * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). - * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor - * @param DMA2Dx DMA2D Instance - * @param Blue Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) -{ - MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue); -} - -/** - * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). - * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor - * @param DMA2Dx DMA2D Instance - * @retval Blue color value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); -} - -/** - * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr - * @param DMA2Dx DMA2D Instance - * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) -{ - LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress); -} - -/** - * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr - * @param DMA2Dx DMA2D Instance - * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); -} - -/** - * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). - * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize - * @param DMA2Dx DMA2D Instance - * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) -{ - MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos)); -} - -/** - * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). - * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize - * @param DMA2Dx DMA2D Instance - * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); -} - -/** - * @brief Set DMA2D foreground CLUT color mode. - * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode - * @param DMA2Dx DMA2D Instance - * @param CLUTColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 - * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) -{ - MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode); -} - -/** - * @brief Return DMA2D foreground CLUT color mode. - * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 - * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 - */ -__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); -} - -/** - * @} - */ - -/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions - * @{ - */ - -/** - * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr - * @param DMA2Dx DMA2D Instance - * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) -{ - LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress); -} - -/** - * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr - * @param DMA2Dx DMA2D Instance - * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); -} - -/** - * @brief Enable DMA2D background CLUT loading. - * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START); -} - -/** - * @brief Indicate if DMA2D background CLUT loading is enabled. - * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); -} - -/** - * @brief Set DMA2D background color mode. - * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode - * @param DMA2Dx DMA2D Instance - * @param ColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 - * @arg @ref LL_DMA2D_INPUT_MODE_L8 - * @arg @ref LL_DMA2D_INPUT_MODE_AL44 - * @arg @ref LL_DMA2D_INPUT_MODE_AL88 - * @arg @ref LL_DMA2D_INPUT_MODE_L4 - * @arg @ref LL_DMA2D_INPUT_MODE_A8 - * @arg @ref LL_DMA2D_INPUT_MODE_A4 - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) -{ - MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode); -} - -/** - * @brief Return DMA2D background color mode. - * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 - * @arg @ref LL_DMA2D_INPUT_MODE_L8 - * @arg @ref LL_DMA2D_INPUT_MODE_AL44 - * @arg @ref LL_DMA2D_INPUT_MODE_AL88 - * @arg @ref LL_DMA2D_INPUT_MODE_L4 - * @arg @ref LL_DMA2D_INPUT_MODE_A8 - * @arg @ref LL_DMA2D_INPUT_MODE_A4 - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); -} - -/** - * @brief Set DMA2D background alpha mode. - * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode - * @param DMA2Dx DMA2D Instance - * @param AphaMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF - * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE - * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) -{ - MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode); -} - -/** - * @brief Return DMA2D background alpha mode. - * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF - * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE - * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); -} - -/** - * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits). - * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha - * @param DMA2Dx DMA2D Instance - * @param Alpha Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) -{ - MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos)); -} - -/** - * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits). - * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha - * @param DMA2Dx DMA2D Instance - * @retval Alpha value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); -} - -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) -/** - * @brief Set DMA2D background Red Blue swap mode. - * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode - * @param DMA2Dx DMA2D Instance - * @param RBSwapMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_RB_MODE_REGULAR - * @arg @ref LL_DMA2D_RB_MODE_SWAP - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) -{ - MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode); -} - -/** - * @brief Return DMA2D background Red Blue swap mode. - * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_RB_MODE_REGULAR - * @arg @ref LL_DMA2D_RB_MODE_SWAP - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); -} - -/** - * @brief Set DMA2D background alpha inversion mode. - * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode - * @param DMA2Dx DMA2D Instance - * @param AlphaInversionMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_REGULAR - * @arg @ref LL_DMA2D_ALPHA_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) -{ - MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode); -} - -/** - * @brief Return DMA2D background alpha inversion mode. - * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_ALPHA_REGULAR - * @arg @ref LL_DMA2D_ALPHA_INVERTED - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); -} - -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - -/** - * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits). - * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset - * @param DMA2Dx DMA2D Instance - * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) -{ - MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset); -} - -/** - * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits). - * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset - * @param DMA2Dx DMA2D Instance - * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); -} - -/** - * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits). - * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor - * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor - * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor - * @param DMA2Dx DMA2D Instance - * @param Red Value between Min_Data=0 and Max_Data=0xFF - * @param Green Value between Min_Data=0 and Max_Data=0xFF - * @param Blue Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) -{ - MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \ - ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue)); -} - -/** - * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits). - * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor - * @param DMA2Dx DMA2D Instance - * @param Red Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) -{ - MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos)); -} - -/** - * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits). - * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor - * @param DMA2Dx DMA2D Instance - * @retval Red color value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); -} - -/** - * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits). - * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor - * @param DMA2Dx DMA2D Instance - * @param Green Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) -{ - MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos)); -} - -/** - * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits). - * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor - * @param DMA2Dx DMA2D Instance - * @retval Green color value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); -} - -/** - * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits). - * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor - * @param DMA2Dx DMA2D Instance - * @param Blue Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) -{ - MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue); -} - -/** - * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits). - * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor - * @param DMA2Dx DMA2D Instance - * @retval Blue color value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); -} - -/** - * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr - * @param DMA2Dx DMA2D Instance - * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) -{ - LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress); -} - -/** - * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). - * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr - * @param DMA2Dx DMA2D Instance - * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); -} - -/** - * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). - * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize - * @param DMA2Dx DMA2D Instance - * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) -{ - MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos)); -} - -/** - * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). - * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize - * @param DMA2Dx DMA2D Instance - * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); -} - -/** - * @brief Set DMA2D background CLUT color mode. - * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode - * @param DMA2Dx DMA2D Instance - * @param CLUTColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 - * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) -{ - MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode); -} - -/** - * @brief Return DMA2D background CLUT color mode. - * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode - * @param DMA2Dx DMA2D Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 - * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 - */ -__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) -{ - return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); -} - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management - * @{ - */ - -/** - * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not - * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not - * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not - * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not - * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not - * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not - * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear DMA2D Configuration Error Interrupt Flag - * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx) -{ - WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF); -} - -/** - * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag - * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx) -{ - WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF); -} - -/** - * @brief Clear DMA2D CLUT Access Error Interrupt Flag - * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx) -{ - WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF); -} - -/** - * @brief Clear DMA2D Transfer Watermark Interrupt Flag - * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx) -{ - WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF); -} - -/** - * @brief Clear DMA2D Transfer Complete Interrupt Flag - * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx) -{ - WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF); -} - -/** - * @brief Clear DMA2D Transfer Error Interrupt Flag - * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx) -{ - WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF); -} - -/** - * @} - */ - -/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management - * @{ - */ - -/** - * @brief Enable Configuration Error Interrupt - * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); -} - -/** - * @brief Enable CLUT Transfer Complete Interrupt - * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); -} - -/** - * @brief Enable CLUT Access Error Interrupt - * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); -} - -/** - * @brief Enable Transfer Watermark Interrupt - * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); -} - -/** - * @brief Enable Transfer Complete Interrupt - * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); -} - -/** - * @brief Enable Transfer Error Interrupt - * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx) -{ - SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); -} - -/** - * @brief Disable Configuration Error Interrupt - * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx) -{ - CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); -} - -/** - * @brief Disable CLUT Transfer Complete Interrupt - * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx) -{ - CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); -} - -/** - * @brief Disable CLUT Access Error Interrupt - * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx) -{ - CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); -} - -/** - * @brief Disable Transfer Watermark Interrupt - * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx) -{ - CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); -} - -/** - * @brief Disable Transfer Complete Interrupt - * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx) -{ - CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); -} - -/** - * @brief Disable Transfer Error Interrupt - * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE - * @param DMA2Dx DMA2D Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) -{ - CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); -} - -/** - * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled. - * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled. - * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled. - * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled. - * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled. - * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled. - * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE - * @param DMA2Dx DMA2D Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) -{ - return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); -} - - - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions - * @{ - */ - -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); -ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); -void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); -void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); -void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); -void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); -void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (DMA2D) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_DMA2D_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h index b240d5d9..8b332e55 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_exti.h @@ -1,948 +1,948 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_exti.h - * @author MCD Application Team - * @brief Header file of EXTI LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_EXTI_H -#define __STM32F7xx_LL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private Macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure - * @{ - */ -typedef struct -{ - - uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 - This parameter can be any combination of @ref EXTI_LL_EC_LINE */ - - FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ - - uint8_t Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_MODE. */ - - uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ -} LL_EXTI_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_LL_EC_LINE LINE - * @{ - */ -#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ -#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ -#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ -#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ -#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ -#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ -#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ -#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ -#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ -#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ -#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ -#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ -#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ -#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ -#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ -#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ -#if defined(EXTI_IMR_IM16) -#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ -#endif -#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ -#if defined(EXTI_IMR_IM18) -#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ -#endif -#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ -#if defined(EXTI_IMR_IM20) -#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ -#endif -#if defined(EXTI_IMR_IM21) -#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ -#endif -#if defined(EXTI_IMR_IM22) -#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ -#endif -#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ -#if defined(EXTI_IMR_IM24) -#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ -#endif -#if defined(EXTI_IMR_IM25) -#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ -#endif -#if defined(EXTI_IMR_IM26) -#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ -#endif -#if defined(EXTI_IMR_IM27) -#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ -#endif -#if defined(EXTI_IMR_IM28) -#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ -#endif -#if defined(EXTI_IMR_IM29) -#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ -#endif -#if defined(EXTI_IMR_IM30) -#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ -#endif -#if defined(EXTI_IMR_IM31) -#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ -#endif -#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ - - -#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ - -#if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup EXTI_LL_EC_MODE Mode - * @{ - */ -#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ -#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ -#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ -/** - * @} - */ - -/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger - * @{ - */ -#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ -#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ -#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ -#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ - -/** - * @} - */ - - -#endif /*USE_FULL_LL_DRIVER*/ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in EXTI register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) - -/** - * @brief Read a value in EXTI register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) -/** - * @} - */ - - -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions - * @{ - */ -/** @defgroup EXTI_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->IMR, ExtiLine); -} - -/** - * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->IMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Event_Management Event_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->EMR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->EMR, ExtiLine); -} - - -/** - * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 - * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24(*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note (*): Available in some devices - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); - -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a Falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for the same interrupt line. - * In this case, both generate a trigger condition. - * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->FTSR, ExtiLine); -} - - -/** - * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management - * @{ - */ - -/** - * @brief Generate a software Interrupt Event for Lines in range 0 to 31 - * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to - * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR - * resulting in an interrupt request generation. - * This bit is cleared by clearing the corresponding bit in the EXTI_PR - * register (by writing a 1 into the bit) - * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->SWIER, ExtiLine); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management - * @{ - */ - -/** - * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); -} - - -/** - * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval @note This bit is set when the selected edge event arrives on the interrupt - */ -__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) -{ - return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); -} - - -/** - * @brief Clear ExtLine Flags for Lines in range 0 to 31 - * @note This bit is set when the selected edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) -{ - WRITE_REG(EXTI->PR, ExtiLine); -} - - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); -uint32_t LL_EXTI_DeInit(void); -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* EXTI */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_EXTI_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_exti.h + * @author MCD Application Team + * @brief Header file of EXTI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_EXTI_H +#define __STM32F7xx_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#if defined(EXTI_IMR_IM16) +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#endif +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#if defined(EXTI_IMR_IM18) +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#endif +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#if defined(EXTI_IMR_IM20) +#define LL_EXTI_LINE_20 EXTI_IMR_IM20 /*!< Extended line 20 */ +#endif +#if defined(EXTI_IMR_IM21) +#define LL_EXTI_LINE_21 EXTI_IMR_IM21 /*!< Extended line 21 */ +#endif +#if defined(EXTI_IMR_IM22) +#define LL_EXTI_LINE_22 EXTI_IMR_IM22 /*!< Extended line 22 */ +#endif +#define LL_EXTI_LINE_23 EXTI_IMR_IM23 /*!< Extended line 23 */ +#if defined(EXTI_IMR_IM24) +#define LL_EXTI_LINE_24 EXTI_IMR_IM24 /*!< Extended line 24 */ +#endif +#if defined(EXTI_IMR_IM25) +#define LL_EXTI_LINE_25 EXTI_IMR_IM25 /*!< Extended line 25 */ +#endif +#if defined(EXTI_IMR_IM26) +#define LL_EXTI_LINE_26 EXTI_IMR_IM26 /*!< Extended line 26 */ +#endif +#if defined(EXTI_IMR_IM27) +#define LL_EXTI_LINE_27 EXTI_IMR_IM27 /*!< Extended line 27 */ +#endif +#if defined(EXTI_IMR_IM28) +#define LL_EXTI_LINE_28 EXTI_IMR_IM28 /*!< Extended line 28 */ +#endif +#if defined(EXTI_IMR_IM29) +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ +#endif +#if defined(EXTI_IMR_IM30) +#define LL_EXTI_LINE_30 EXTI_IMR_IM30 /*!< Extended line 30 */ +#endif +#if defined(EXTI_IMR_IM31) +#define LL_EXTI_LINE_31 EXTI_IMR_IM31 /*!< Extended line 31 */ +#endif +#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR_IM /*!< All Extended line not reserved*/ + + +#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE (0x00000000U) /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_EnableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_DisableIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 + * @note The reset value for the direct or internal lines (see RM) + * is set to 1 in order to enable the interrupt by default. + * Bits are set automatically at Power on. + * @rmtoll IMR IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_EnableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Event request for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_DisableEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 + * @rmtoll EMR EMx LL_EXTI_IsEnabledEvent_0_31 + * @param ExtiLine This parameter can be one of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @arg @ref LL_EXTI_LINE_23 + * @arg @ref LL_EXTI_LINE_24(*) + * @arg @ref LL_EXTI_LINE_ALL_0_31 + * @note (*): Available in some devices + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); + +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_EnableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll RTSR RTx LL_EXTI_DisableRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll RTSR RTx LL_EXTI_IsEnabledRisingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @rmtoll FTSR FTx LL_EXTI_EnableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @rmtoll FTSR FTx LL_EXTI_DisableFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + + +/** + * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 + * @rmtoll FTSR FTx LL_EXTI_IsEnabledFallingTrig_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines in range 0 to 31 + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @rmtoll SWIER SWIx LL_EXTI_GenerateSWI_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_IsActiveFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + + +/** + * @brief Read ExtLine Combination Flag for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ReadFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine) +{ + return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine)); +} + + +/** + * @brief Clear ExtLine Flags for Lines in range 0 to 31 + * @note This bit is set when the selected edge event arrives on the interrupt + * line. This bit is cleared by writing a 1 to the bit. + * @rmtoll PR PIFx LL_EXTI_ClearFlag_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_20 + * @arg @ref LL_EXTI_LINE_21 + * @arg @ref LL_EXTI_LINE_22 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_EXTI_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h deleted file mode 100644 index dd7d7c4f..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_fmc.h +++ /dev/null @@ -1,1151 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_fmc.h - * @author MCD Application Team - * @brief Header file of FMC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_FMC_H -#define STM32F7xx_LL_FMC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup FMC_LL - * @{ - */ - -/** @addtogroup FMC_LL_Private_Macros - * @{ - */ - -#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ - ((__BANK__) == FMC_NORSRAM_BANK2) || \ - ((__BANK__) == FMC_NORSRAM_BANK3) || \ - ((__BANK__) == FMC_NORSRAM_BANK4)) -#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) -#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) -#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) -#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ - ((__SIZE__) == FMC_PAGE_SIZE_128) || \ - ((__SIZE__) == FMC_PAGE_SIZE_256) || \ - ((__SIZE__) == FMC_PAGE_SIZE_512) || \ - ((__SIZE__) == FMC_PAGE_SIZE_1024)) -#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ - ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) -#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ - ((__MODE__) == FMC_ACCESS_MODE_B) || \ - ((__MODE__) == FMC_ACCESS_MODE_C) || \ - ((__MODE__) == FMC_ACCESS_MODE_D)) -#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) -#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) -#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) -#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) -#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) -#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) -#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) -#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) -#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FMC_WRITE_BURST_ENABLE)) -#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) -#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) -#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) -#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) -#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) -#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) -#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) -#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) -#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) - - -#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) -#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ - ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) -#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) -#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ - ((__STATE__) == FMC_NAND_ECC_ENABLE)) - -#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) -#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) -#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) -#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) -#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) -#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) -#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) -#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) - - -#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) -#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ - ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) -#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ - ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ - ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) -#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ - ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) -#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ - ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ - ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) -#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ - ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) -#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ - ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ - ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) -#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) -#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) -#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) -#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) -#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) -#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) -#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) -#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) -#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) -#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) -#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) -#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ - ((__BANK__) == FMC_SDRAM_BANK2)) -#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ - ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ - ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ - ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) -#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ - ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ - ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) -#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ - ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) -#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ - ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ - ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) - - -/** - * @} - */ - -/* Exported typedef ----------------------------------------------------------*/ - -/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types - * @{ - */ - -#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef -#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef -#define FMC_NAND_TypeDef FMC_Bank3_TypeDef -#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef - -#define FMC_NORSRAM_DEVICE FMC_Bank1 -#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E -#define FMC_NAND_DEVICE FMC_Bank3 -#define FMC_SDRAM_DEVICE FMC_Bank5_6 - -/** - * @brief FMC NORSRAM Configuration Structure definition - */ -typedef struct -{ - uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ - - uint32_t DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ - - uint32_t MemoryType; /*!< Specifies the type of external memory attached to - the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ - - uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ - - uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, - valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ - - uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing - the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ - - uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one - clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ - - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ - - uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ - - uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ - - uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, - valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ - - uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ - - uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, - and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ - - uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, - and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ - - uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ -} FMC_NORSRAM_InitTypeDef; - -/** - * @brief FMC NORSRAM Timing parameters structure definition - */ -typedef struct -{ - uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. - This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address hold time. - This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ - - uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the data setup time. - This parameter can be a value between Min_Data = 1 and Max_Data = 255. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ - - uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure - the duration of the bus turnaround. - This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ - - uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and - Max_Data = 16. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ - - uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue - to the memory before getting the first data. - The parameter value depends on the memory type as shown below: - - It must be set to 0 in case of a CRAM - - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 - in NOR Flash memories with synchronous burst mode enable */ - - uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -} FMC_NORSRAM_TimingTypeDef; - -/** - * @brief FMC NAND Configuration Structure definition - */ -typedef struct -{ - uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ - - uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ - - uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ - - uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ - - uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ - - uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between CLE low and RE low. - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - - uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the - delay between ALE low and RE low. - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -} FMC_NAND_InitTypeDef; - -/** - * @brief FMC NAND Timing parameters structure definition - */ -typedef struct -{ - uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before - the command assertion for NAND-Flash read or write access - to common/Attribute or I/O memory space (depending on - the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ - - uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the - command for NAND-Flash read or write access to - common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ - - uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address - (and data for write access) after the command de-assertion - for NAND-Flash read or write access to common/Attribute - or I/O memory space (depending on the memory space timing - to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ - - uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the - data bus is kept in HiZ after the start of a NAND-Flash - write access to common/Attribute or I/O memory space (depending - on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ -} FMC_NAND_PCC_TimingTypeDef; - - -/** - * @brief FMC SDRAM Configuration Structure definition - */ -typedef struct -{ - uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. - This parameter can be a value of @ref FMC_SDRAM_Bank */ - - uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. - This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ - - uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. - This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ - - uint32_t MemoryDataWidth; /*!< Defines the memory device width. - This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ - - uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. - This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ - - uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. - This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ - - uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. - This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ - - uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow - to disable the clock before changing frequency. - This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ - - uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read - commands during the CAS latency and stores data in the Read FIFO. - This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ - - uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. - This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ -} FMC_SDRAM_InitTypeDef; - -/** - * @brief FMC SDRAM Timing parameters structure definition - */ -typedef struct -{ - uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and - an active or Refresh command in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to - issuing the Activate command in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock - cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command - and the delay between two consecutive Refresh commands in number of - memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command - in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - - uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write - command in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ -} FMC_SDRAM_TimingTypeDef; - -/** - * @brief SDRAM command parameters structure definition - */ -typedef struct -{ - uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. - This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ - - uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. - This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ - - uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued - in auto refresh mode. - This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ - - uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ -} FMC_SDRAM_CommandTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants - * @{ - */ - -/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller - * @{ - */ - -/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank - * @{ - */ -#define FMC_NORSRAM_BANK1 (0x00000000U) -#define FMC_NORSRAM_BANK2 (0x00000002U) -#define FMC_NORSRAM_BANK3 (0x00000004U) -#define FMC_NORSRAM_BANK4 (0x00000006U) -/** - * @} - */ - -/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing - * @{ - */ -#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) -#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) -/** - * @} - */ - -/** @defgroup FMC_Memory_Type FMC Memory Type - * @{ - */ -#define FMC_MEMORY_TYPE_SRAM (0x00000000U) -#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) -#define FMC_MEMORY_TYPE_NOR (0x00000008U) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width - * @{ - */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) -/** - * @} - */ - -/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access - * @{ - */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) -/** - * @} - */ - -/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode - * @{ - */ -#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) -#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) -/** - * @} - */ - -/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity - * @{ - */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) -#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) -/** - * @} - */ - -/** @defgroup FMC_Wait_Timing FMC Wait Timing - * @{ - */ -#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) -#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) -/** - * @} - */ - -/** @defgroup FMC_Write_Operation FMC Write Operation - * @{ - */ -#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) -#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) -/** - * @} - */ - -/** @defgroup FMC_Wait_Signal FMC Wait Signal - * @{ - */ -#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) -#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) -/** - * @} - */ - -/** @defgroup FMC_Extended_Mode FMC Extended Mode - * @{ - */ -#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) -#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) -/** - * @} - */ - -/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait - * @{ - */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) -#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) -/** - * @} - */ - -/** @defgroup FMC_Page_Size FMC Page Size - * @{ - */ -#define FMC_PAGE_SIZE_NONE (0x00000000U) -#define FMC_PAGE_SIZE_128 FMC_BCR1_CPSIZE_0 -#define FMC_PAGE_SIZE_256 FMC_BCR1_CPSIZE_1 -#define FMC_PAGE_SIZE_512 (FMC_BCR1_CPSIZE_0\ - | FMC_BCR1_CPSIZE_1) -#define FMC_PAGE_SIZE_1024 FMC_BCR1_CPSIZE_2 -/** - * @} - */ - -/** @defgroup FMC_Write_Burst FMC Write Burst - * @{ - */ -#define FMC_WRITE_BURST_DISABLE (0x00000000U) -#define FMC_WRITE_BURST_ENABLE (0x00080000U) -/** - * @} - */ - -/** @defgroup FMC_Continous_Clock FMC Continuous Clock - * @{ - */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) -/** - * @} - */ - -#if defined(FMC_BCR1_WFDIS) -/** @defgroup FMC_Write_FIFO FMC Write FIFO - * @{ - */ -#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS -#define FMC_WRITE_FIFO_ENABLE (0x00000000U) -#endif /* FMC_BCR1_WFDIS */ -/** - * @} - */ - -/** @defgroup FMC_Access_Mode FMC Access Mode - * @{ - */ -#define FMC_ACCESS_MODE_A (0x00000000U) -#define FMC_ACCESS_MODE_B (0x10000000U) -#define FMC_ACCESS_MODE_C (0x20000000U) -#define FMC_ACCESS_MODE_D (0x30000000U) -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller - * @{ - */ -/** @defgroup FMC_NAND_Bank FMC NAND Bank - * @{ - */ -#define FMC_NAND_BANK3 (0x00000100U) -/** - * @} - */ - -/** @defgroup FMC_Wait_feature FMC Wait feature - * @{ - */ -#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) -#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) -/** - * @} - */ - -/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type - * @{ - */ -#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) -/** - * @} - */ - -/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width - * @{ - */ -#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) -#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) -/** - * @} - */ - -/** @defgroup FMC_ECC FMC ECC - * @{ - */ -#define FMC_NAND_ECC_DISABLE (0x00000000U) -#define FMC_NAND_ECC_ENABLE (0x00000040U) -/** - * @} - */ - -/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size - * @{ - */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller - * @{ - */ -/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank - * @{ - */ -#define FMC_SDRAM_BANK1 (0x00000000U) -#define FMC_SDRAM_BANK2 (0x00000001U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number - * @{ - */ -#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) -#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) -#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) -#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number - * @{ - */ -#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) -#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) -#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width - * @{ - */ -#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) -#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) -#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number - * @{ - */ -#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) -#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency - * @{ - */ -#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) -#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) -#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection - * @{ - */ -#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) -#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period - * @{ - */ -#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) -#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) -#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst - * @{ - */ -#define FMC_SDRAM_RBURST_DISABLE (0x00000000U) -#define FMC_SDRAM_RBURST_ENABLE (0x00001000U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay - * @{ - */ -#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) -#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) -#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode - * @{ - */ -#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) -#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) -#define FMC_SDRAM_CMD_PALL (0x00000002U) -#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) -#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) -#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) -#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target - * @{ - */ -#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 -#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 -#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) -/** - * @} - */ - -/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status - * @{ - */ -#define FMC_SDRAM_NORMAL_MODE (0x00000000U) -#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 -#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition - * @{ - */ -#define FMC_IT_RISING_EDGE (0x00000008U) -#define FMC_IT_LEVEL (0x00000010U) -#define FMC_IT_FALLING_EDGE (0x00000020U) -#define FMC_IT_REFRESH_ERROR (0x00004000U) -/** - * @} - */ - -/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition - * @{ - */ -#define FMC_FLAG_RISING_EDGE (0x00000001U) -#define FMC_FLAG_LEVEL (0x00000002U) -#define FMC_FLAG_FALLING_EDGE (0x00000004U) -#define FMC_FLAG_FEMPT (0x00000040U) -#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE -#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY -#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros - * @{ - */ -/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ - -/** - * @brief Enable the NORSRAM device access. - * @param __INSTANCE__ FMC_NORSRAM Instance - * @param __BANK__ FMC_NORSRAM Bank - * @retval None - */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ - |= FMC_BCR1_MBKEN) - -/** - * @brief Disable the NORSRAM device access. - * @param __INSTANCE__ FMC_NORSRAM Instance - * @param __BANK__ FMC_NORSRAM Bank - * @retval None - */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ - &= ~FMC_BCR1_MBKEN) - -/** - * @} - */ - -/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ - -/** - * @brief Enable the NAND device access. - * @param __INSTANCE__ FMC_NAND Instance - * @retval None - */ -#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) - -/** - * @brief Disable the NAND device access. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @retval None - */ -#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) - -/** - * @} - */ - -/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt - * @brief macros to handle NAND interrupts - * @{ - */ - -/** - * @brief Enable the NAND device interrupt. - * @param __INSTANCE__ FMC_NAND instance - * @param __INTERRUPT__ FMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) - -/** - * @brief Disable the NAND device interrupt. - * @param __INSTANCE__ FMC_NAND Instance - * @param __INTERRUPT__ FMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) - -/** - * @brief Get flag status of the NAND device. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear flag status of the NAND device. - * @param __INSTANCE__ FMC_NAND Instance - * @param __FLAG__ FMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. - * @retval None - */ -#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) - -/** - * @} - */ - - -/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt - * @brief macros to handle SDRAM interrupts - * @{ - */ - -/** - * @brief Enable the SDRAM device interrupt. - * @param __INSTANCE__ FMC_SDRAM instance - * @param __INTERRUPT__ FMC_SDRAM interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error - * @retval None - */ -#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) - -/** - * @brief Disable the SDRAM device interrupt. - * @param __INSTANCE__ FMC_SDRAM instance - * @param __INTERRUPT__ FMC_SDRAM interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error - * @retval None - */ -#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) - -/** - * @brief Get flag status of the SDRAM device. - * @param __INSTANCE__ FMC_SDRAM instance - * @param __FLAG__ FMC_SDRAM flag - * This parameter can be any combination of the following values: - * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. - * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. - * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear flag status of the SDRAM device. - * @param __INSTANCE__ FMC_SDRAM instance - * @param __FLAG__ FMC_SDRAM flag - * This parameter can be any combination of the following values: - * @arg FMC_SDRAM_FLAG_REFRESH_ERROR - * @retval None - */ -#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) - -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions - * @{ - */ - -/** @defgroup FMC_LL_NORSRAM NOR SRAM - * @{ - */ -/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, - uint32_t ExtendedMode); -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); -/** - * @} - */ - -/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions - * @{ - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); -/** - * @} - */ -/** - * @} - */ - -/** @defgroup FMC_LL_NAND NAND - * @{ - */ -/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); -/** - * @} - */ - -/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions - * @{ - */ -HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, - uint32_t Timeout); -/** - * @} - */ -/** - * @} - */ - - -/** @defgroup FMC_LL_SDRAM SDRAM - * @{ - */ -/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -/** - * @} - */ - -/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions - * @{ - */ -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); -HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, - uint32_t AutoRefreshNumber); -uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_FMC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h index 14c67ca3..46b6e60d 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_gpio.h @@ -1,981 +1,981 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_GPIO_H -#define __STM32F7xx_LL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) - -/** @defgroup GPIO_LL GPIO - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros - * @{ - */ - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures - * @{ - */ - -/** - * @brief LL GPIO Init Structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_LL_EC_PIN */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_MODE. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_SPEED. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ - - uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ - - uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_PULL. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ - - uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_AF. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ -} LL_GPIO_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_LL_EC_PIN PIN - * @{ - */ -#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ -#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ -#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ -#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ -#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ -#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ -#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ -#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ -#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ -#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ -#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ -#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ -#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ -#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ -#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ -#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ -#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ - GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ - GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ - GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ - GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ - GPIO_BSRR_BS_15) /*!< Select all pins */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_MODE Mode - * @{ - */ -#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ -#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ -#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ -#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_OUTPUT Output Type - * @{ - */ -#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ -#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_SPEED Output Speed - * @{ - */ -#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ -#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ -#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */ -#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down - * @{ - */ -#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ -#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ -#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_AF Alternate Function - * @{ - */ -#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ -#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ -#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ -#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ -#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ -#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ -#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ -#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ -#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ -#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ -#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ -#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ -#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ -#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ -#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ -#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration - * @{ - */ - -/** - * @brief Configure gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_SetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) -{ - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); -} - -/** - * @brief Return gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_GetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->MODER, - (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); -} - -/** - * @brief Configure gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @param OutputType This parameter can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) -{ - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); -} - -/** - * @brief Return gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); -} - -/** - * @brief Configure gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Speed This parameter can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) -{ - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), - (Speed << (POSITION_VAL(Pin) * 2U))); -} - -/** - * @brief Return gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, - (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); -} - -/** - * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Pull This parameter can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) -{ - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); -} - -/** - * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->PUPDR, - (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)), - (Alternate << (POSITION_VAL(Pin) * 4U))); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[0], - (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), - (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); -} - - -/** - * @brief Lock configuration of several pins for a dedicated port. - * @note When the lock sequence has been applied on a port bit, the - * value of this port bit can no longer be modified until the - * next reset. - * @note Each lock bit freezes a specific configuration register - * (control and alternate function registers). - * @rmtoll LCKR LCKK LL_GPIO_LockPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - __IO uint32_t temp; - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - WRITE_REG(GPIOx->LCKR, PinMask); - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - temp = READ_REG(GPIOx->LCKR); - (void) temp; -} - -/** - * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. - * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); -} - -/** - * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. - * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked - * @param GPIOx GPIO Port - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) -{ - return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); -} - -/** - * @} - */ - -/** @defgroup GPIO_LL_EF_Data_Access Data Access - * @{ - */ - -/** - * @brief Return full input data register value for a dedicated port. - * @rmtoll IDR IDy LL_GPIO_ReadInputPort - * @param GPIOx GPIO Port - * @retval Input data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->IDR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll IDR IDy LL_GPIO_IsInputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); -} - -/** - * @brief Write output data register for the port. - * @rmtoll ODR ODy LL_GPIO_WriteOutputPort - * @param GPIOx GPIO Port - * @param PortValue Level value for each pin of the port - * @retval None - */ -__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) -{ - WRITE_REG(GPIOx->ODR, PortValue); -} - -/** - * @brief Return full output data register value for a dedicated port. - * @rmtoll ODR ODy LL_GPIO_ReadOutputPort - * @param GPIOx GPIO Port - * @retval Output data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->ODR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); -} - -/** - * @brief Set several pins to high level on dedicated gpio port. - * @rmtoll BSRR BSy LL_GPIO_SetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSRR, PinMask); -} - -/** - * @brief Set several pins to low level on dedicated gpio port. - * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSRR, (PinMask << 16)); -} - -/** - * @brief Toggle data value for several pin of dedicated port. - * @rmtoll ODR ODy LL_GPIO_TogglePin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - uint32_t odr = READ_REG(GPIOx->ODR); - WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_GPIO_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_gpio.h + * @author MCD Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_GPIO_H +#define __STM32F7xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) + +/** @defgroup GPIO_LL GPIO + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS_0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS_1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS_2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS_3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS_4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS_5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS_6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS_7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS_8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS_9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS_10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS_11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS_12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS_13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS_14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS_15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1 | GPIO_BSRR_BS_2 | \ + GPIO_BSRR_BS_3 | GPIO_BSRR_BS_4 | GPIO_BSRR_BS_5 | \ + GPIO_BSRR_BS_6 | GPIO_BSRR_BS_7 | GPIO_BSRR_BS_8 | \ + GPIO_BSRR_BS_9 | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \ + GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \ + GPIO_BSRR_BS_15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODER0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODER0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODER0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDER_OSPEEDR0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, + (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)), + (Speed << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, Fast or High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, + (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U))); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, + (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U)), + (Alternate << (POSITION_VAL(Pin) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + (GPIO_AFRL_AFRL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U)), + (Alternate << (POSITION_VAL(Pin >> 8U) * 4U))); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF15 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (GPIO_AFRH_AFRH0 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BSRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, (PinMask << 16)); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + uint32_t odr = READ_REG(GPIOx->ODR); + WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_GPIO_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h index 05192dc0..684177b8 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_i2c.h @@ -1,2239 +1,2239 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_i2c.h - * @author MCD Application Team - * @brief Header file of I2C LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_I2C_H -#define STM32F7xx_LL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) - -/** @defgroup I2C_LL I2C - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_LL_Private_Constants I2C Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2C_LL_Private_Macros I2C Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t PeripheralMode; /*!< Specifies the peripheral mode. - This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetMode(). */ - - uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. - This parameter must be set by referring to the STM32CubeMX Tool and - the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetTiming(). */ - - uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. - - This feature can be modified afterwards using unitary functions - @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ - - uint32_t DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetDigitalFilter(). */ - - uint32_t OwnAddress1; /*!< Specifies the device own address 1. - This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetOwnAddress1(). */ - - uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive - match code or next received byte. - This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_AcknowledgeNextData(). */ - - uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). - This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetOwnAddress1(). */ -} LL_I2C_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_I2C_WriteReg function - * @{ - */ -#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ -#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ -#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ -#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ -#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ -#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ -#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ -#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ -#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_I2C_ReadReg function - * @{ - */ -#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ -#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ -#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ -#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ -#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ -#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ -#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ -#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ -#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ -#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ -#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ -#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ -#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ -#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ -#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions - * @{ - */ -#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ -#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ -#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ -#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ -#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ -#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ -#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode - * @{ - */ -#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ -#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode - (Default address not acknowledge) */ -#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection - * @{ - */ -#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ -#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode - * @{ - */ -#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ -#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length - * @{ - */ -#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ -#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks - * @{ - */ -#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ -#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. - All Address2 are acknowledged. */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation - * @{ - */ -#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ -#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length - * @{ - */ -#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ -#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction - * @{ - */ -#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ -#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_MODE Transfer End Mode - * @{ - */ -#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ -#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode - with no HW PEC comparison. */ -#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode - with no HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode - with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode - with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode - with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) -/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) -/*!< Enable SMBUS Software end mode with HW PEC comparison. */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation - * @{ - */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U -/*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) -/*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -/*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -/*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ - I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) -/*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/*!< Generate Restart for write request, slave 10Bit address.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction - * @{ - */ -#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, - slave enters receiver mode. */ -#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, - slave enters transmitter mode.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data - * @{ - */ -#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for - transmission */ -#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for - reception */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout - * @{ - */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect - SCL low level timeout. */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect - both SCL and SDA high level timeout.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection - * @{ - */ -#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ -#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) - enable bit */ -#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ - I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB -(extended clock) enable bits */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in I2C register - * @param __INSTANCE__ I2C Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in I2C register - * @param __INSTANCE__ I2C Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings - * @{ - */ -/** - * @brief Configure the SDA setup, hold time and the SCL high, low period. - * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - (tscldel = (SCLDEL+1)xtpresc) - * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - (tsdadel = SDADELxtpresc) - * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. - (tsclh = (SCLH+1)xtpresc) - * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. - (tscll = (SCLL+1)xtpresc) - * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable I2C peripheral (PE = 1). - * @rmtoll CR1 PE LL_I2C_Enable - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_PE); -} - -/** - * @brief Disable I2C peripheral (PE = 0). - * @note When PE = 0, the I2C SCL and SDA lines are released. - * Internal state machines and status bits are put back to their reset value. - * When cleared, PE must be kept low for at least 3 APB clock cycles. - * @rmtoll CR1 PE LL_I2C_Disable - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); -} - -/** - * @brief Check if the I2C peripheral is enabled or disabled. - * @rmtoll CR1 PE LL_I2C_IsEnabled - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); -} - -/** - * @brief Configure Noise Filters (Analog and Digital). - * @note If the analog filter is also enabled, the digital filter is added to analog filter. - * The filters can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n - * CR1 DNF LL_I2C_ConfigFilters - * @param I2Cx I2C Instance. - * @param AnalogFilter This parameter can be one of the following values: - * @arg @ref LL_I2C_ANALOGFILTER_ENABLE - * @arg @ref LL_I2C_ANALOGFILTER_DISABLE - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) - and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). - * This parameter is used to configure the digital noise filter on SDA and SCL input. - * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) -{ - MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); -} - -/** - * @brief Configure Digital Noise Filter. - * @note If the analog filter is also enabled, the digital filter is added to analog filter. - * This filter can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter - * @param I2Cx I2C Instance. - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) - and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). - * This parameter is used to configure the digital noise filter on SDA and SCL input. - * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) -{ - MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); -} - -/** - * @brief Get the current Digital Noise Filter configuration. - * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); -} - -/** - * @brief Enable Analog Noise Filter. - * @note This filter can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); -} - -/** - * @brief Disable Analog Noise Filter. - * @note This filter can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); -} - -/** - * @brief Check if Analog Noise Filter is enabled or disabled. - * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA transmission requests. - * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); -} - -/** - * @brief Disable DMA transmission requests. - * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); -} - -/** - * @brief Check if DMA transmission requests are enabled or disabled. - * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA reception requests. - * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); -} - -/** - * @brief Disable DMA reception requests. - * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); -} - -/** - * @brief Check if DMA reception requests are enabled or disabled. - * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n - * RXDR RXDATA LL_I2C_DMA_GetRegAddr - * @param I2Cx I2C Instance - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT - * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) -{ - uint32_t data_reg_addr; - - if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) - { - /* return address of TXDR register */ - data_reg_addr = (uint32_t) &(I2Cx->TXDR); - } - else - { - /* return address of RXDR register */ - data_reg_addr = (uint32_t) &(I2Cx->RXDR); - } - - return data_reg_addr; -} - -/** - * @brief Enable Clock stretching. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); -} - -/** - * @brief Disable Clock stretching. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); -} - -/** - * @brief Check if Clock stretching is enabled or disabled. - * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); -} - -/** - * @brief Enable hardware byte control in slave mode. - * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_SBC); -} - -/** - * @brief Disable hardware byte control in slave mode. - * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); -} - -/** - * @brief Check if hardware byte control in slave mode is enabled or disabled. - * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); -} - -/** - * @brief Enable General Call. - * @note When enabled the Address 0x00 is ACKed. - * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); -} - -/** - * @brief Disable General Call. - * @note When disabled the Address 0x00 is NACKed. - * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); -} - -/** - * @brief Check if General Call is enabled or disabled. - * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); -} - -/** - * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. - * @note Changing this bit is not allowed, when the START bit is set. - * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode - * @param I2Cx I2C Instance. - * @param AddressingMode This parameter can be one of the following values: - * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT - * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); -} - -/** - * @brief Get the Master addressing mode. - * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT - * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT - */ -__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); -} - -/** - * @brief Set the Own Address1. - * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n - * OAR1 OA1MODE LL_I2C_SetOwnAddress1 - * @param I2Cx I2C Instance. - * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. - * @param OwnAddrSize This parameter can be one of the following values: - * @arg @ref LL_I2C_OWNADDRESS1_7BIT - * @arg @ref LL_I2C_OWNADDRESS1_10BIT - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) -{ - MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); -} - -/** - * @brief Enable acknowledge on Own Address1 match address. - * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); -} - -/** - * @brief Disable acknowledge on Own Address1 match address. - * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); -} - -/** - * @brief Check if Own Address1 acknowledge is enabled or disabled. - * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); -} - -/** - * @brief Set the 7bits Own Address2. - * @note This action has no effect if own address2 is enabled. - * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n - * OAR2 OA2MSK LL_I2C_SetOwnAddress2 - * @param I2Cx I2C Instance. - * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. - * @param OwnAddrMask This parameter can be one of the following values: - * @arg @ref LL_I2C_OWNADDRESS2_NOMASK - * @arg @ref LL_I2C_OWNADDRESS2_MASK01 - * @arg @ref LL_I2C_OWNADDRESS2_MASK02 - * @arg @ref LL_I2C_OWNADDRESS2_MASK03 - * @arg @ref LL_I2C_OWNADDRESS2_MASK04 - * @arg @ref LL_I2C_OWNADDRESS2_MASK05 - * @arg @ref LL_I2C_OWNADDRESS2_MASK06 - * @arg @ref LL_I2C_OWNADDRESS2_MASK07 - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) -{ - MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); -} - -/** - * @brief Enable acknowledge on Own Address2 match address. - * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); -} - -/** - * @brief Disable acknowledge on Own Address2 match address. - * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); -} - -/** - * @brief Check if Own Address1 acknowledge is enabled or disabled. - * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); -} - -/** - * @brief Configure the SDA setup, hold time and the SCL high, low period. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming - * @param I2Cx I2C Instance. - * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. - * @note This parameter is computed with the STM32CubeMX Tool. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) -{ - WRITE_REG(I2Cx->TIMINGR, Timing); -} - -/** - * @brief Get the Timing Prescaler setting. - * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); -} - -/** - * @brief Get the SCL low period setting. - * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); -} - -/** - * @brief Get the SCL high period setting. - * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); -} - -/** - * @brief Get the SDA hold time. - * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); -} - -/** - * @brief Get the SDA setup time. - * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); -} - -/** - * @brief Configure peripheral mode. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n - * CR1 SMBDEN LL_I2C_SetMode - * @param I2Cx I2C Instance. - * @param PeripheralMode This parameter can be one of the following values: - * @arg @ref LL_I2C_MODE_I2C - * @arg @ref LL_I2C_MODE_SMBUS_HOST - * @arg @ref LL_I2C_MODE_SMBUS_DEVICE - * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) -{ - MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); -} - -/** - * @brief Get peripheral mode. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n - * CR1 SMBDEN LL_I2C_GetMode - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_MODE_I2C - * @arg @ref LL_I2C_MODE_SMBUS_HOST - * @arg @ref LL_I2C_MODE_SMBUS_DEVICE - * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP - */ -__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); -} - -/** - * @brief Enable SMBus alert (Host or Device mode) - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note SMBus Device mode: - * - SMBus Alert pin is drived low and - * Alert Response Address Header acknowledge is enabled. - * SMBus Host mode: - * - SMBus Alert pin management is supported. - * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); -} - -/** - * @brief Disable SMBus alert (Host or Device mode) - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note SMBus Device mode: - * - SMBus Alert pin is not drived (can be used as a standard GPIO) and - * Alert Response Address Header acknowledge is disabled. - * SMBus Host mode: - * - SMBus Alert pin management is not supported. - * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); -} - -/** - * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable SMBus Packet Error Calculation (PEC). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); -} - -/** - * @brief Disable SMBus Packet Error Calculation (PEC). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); -} - -/** - * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); -} - -/** - * @brief Configure the SMBus Clock Timeout. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). - * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n - * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n - * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout - * @param I2Cx I2C Instance. - * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. - * @param TimeoutAMode This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH - * @param TimeoutB - * @retval None - */ -__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, - uint32_t TimeoutB) -{ - MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, - TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); -} - -/** - * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note These bits can only be programmed when TimeoutA is disabled. - * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA - * @param I2Cx I2C Instance. - * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) -{ - WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); -} - -/** - * @brief Get the SMBus Clock TimeoutA setting. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); -} - -/** - * @brief Set the SMBus Clock TimeoutA mode. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note This bit can only be programmed when TimeoutA is disabled. - * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode - * @param I2Cx I2C Instance. - * @param TimeoutAMode This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) -{ - WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); -} - -/** - * @brief Get the SMBus Clock TimeoutA mode. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH - */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); -} - -/** - * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note These bits can only be programmed when TimeoutB is disabled. - * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB - * @param I2Cx I2C Instance. - * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) -{ - WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); -} - -/** - * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); -} - -/** - * @brief Enable the SMBus Clock Timeout. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n - * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout - * @param I2Cx I2C Instance. - * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA - * @arg @ref LL_I2C_SMBUS_TIMEOUTB - * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) -{ - SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); -} - -/** - * @brief Disable the SMBus Clock Timeout. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n - * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout - * @param I2Cx I2C Instance. - * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA - * @arg @ref LL_I2C_SMBUS_TIMEOUTB - * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) -{ - CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); -} - -/** - * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n - * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout - * @param I2Cx I2C Instance. - * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA - * @arg @ref LL_I2C_SMBUS_TIMEOUTB - * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) -{ - return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ - (ClockTimeout)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable TXIS interrupt. - * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); -} - -/** - * @brief Disable TXIS interrupt. - * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); -} - -/** - * @brief Check if the TXIS Interrupt is enabled or disabled. - * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable RXNE interrupt. - * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); -} - -/** - * @brief Disable RXNE interrupt. - * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); -} - -/** - * @brief Check if the RXNE Interrupt is enabled or disabled. - * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Address match interrupt (slave mode only). - * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); -} - -/** - * @brief Disable Address match interrupt (slave mode only). - * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); -} - -/** - * @brief Check if Address match interrupt is enabled or disabled. - * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Not acknowledge received interrupt. - * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); -} - -/** - * @brief Disable Not acknowledge received interrupt. - * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); -} - -/** - * @brief Check if Not acknowledge received interrupt is enabled or disabled. - * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable STOP detection interrupt. - * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); -} - -/** - * @brief Disable STOP detection interrupt. - * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); -} - -/** - * @brief Check if STOP detection interrupt is enabled or disabled. - * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Transfer Complete interrupt. - * @note Any of these events will generate interrupt : - * Transfer Complete (TC) - * Transfer Complete Reload (TCR) - * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); -} - -/** - * @brief Disable Transfer Complete interrupt. - * @note Any of these events will generate interrupt : - * Transfer Complete (TC) - * Transfer Complete Reload (TCR) - * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); -} - -/** - * @brief Check if Transfer Complete interrupt is enabled or disabled. - * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Error interrupts. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note Any of these errors will generate interrupt : - * Arbitration Loss (ARLO) - * Bus Error detection (BERR) - * Overrun/Underrun (OVR) - * SMBus Timeout detection (TIMEOUT) - * SMBus PEC error detection (PECERR) - * SMBus Alert pin event detection (ALERT) - * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); -} - -/** - * @brief Disable Error interrupts. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note Any of these errors will generate interrupt : - * Arbitration Loss (ARLO) - * Bus Error detection (BERR) - * Overrun/Underrun (OVR) - * SMBus Timeout detection (TIMEOUT) - * SMBus PEC error detection (PECERR) - * SMBus Alert pin event detection (ALERT) - * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); -} - -/** - * @brief Check if Error interrupts are enabled or disabled. - * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_FLAG_management FLAG_management - * @{ - */ - -/** - * @brief Indicate the status of Transmit data register empty flag. - * @note RESET: When next data is written in Transmit data register. - * SET: When Transmit data register is empty. - * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Transmit interrupt flag. - * @note RESET: When next data is written in Transmit data register. - * SET: When Transmit data register is empty. - * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Receive data register not empty flag. - * @note RESET: When Receive data register is read. - * SET: When the received data is copied in Receive data register. - * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Address matched flag (slave mode). - * @note RESET: Clear default value. - * SET: When the received slave address matched with one of the enabled slave address. - * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Not Acknowledge received flag. - * @note RESET: Clear default value. - * SET: When a NACK is received after a byte transmission. - * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Stop detection flag. - * @note RESET: Clear default value. - * SET: When a Stop condition is detected. - * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Transfer complete flag (master mode). - * @note RESET: Clear default value. - * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. - * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Transfer complete flag (master mode). - * @note RESET: Clear default value. - * SET: When RELOAD=1 and NBYTES date have been transferred. - * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Bus error flag. - * @note RESET: Clear default value. - * SET: When a misplaced Start or Stop condition is detected. - * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Arbitration lost flag. - * @note RESET: Clear default value. - * SET: When arbitration lost. - * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Overrun/Underrun flag (slave mode). - * @note RESET: Clear default value. - * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). - * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of SMBus PEC error flag in reception. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note RESET: Clear default value. - * SET: When the received PEC does not match with the PEC register content. - * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of SMBus Timeout detection flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note RESET: Clear default value. - * SET: When a timeout or extended clock timeout occurs. - * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of SMBus alert flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note RESET: Clear default value. - * SET: When SMBus host configuration, SMBus alert enabled and - * a falling edge event occurs on SMBA pin. - * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Bus Busy flag. - * @note RESET: Clear default value. - * SET: When a Start condition is detected. - * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); -} - -/** - * @brief Clear Address Matched flag. - * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); -} - -/** - * @brief Clear Not Acknowledge flag. - * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); -} - -/** - * @brief Clear Stop detection flag. - * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); -} - -/** - * @brief Clear Transmit data register empty flag (TXE). - * @note This bit can be clear by software in order to flush the transmit data register (TXDR). - * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) -{ - WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); -} - -/** - * @brief Clear Bus error flag. - * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); -} - -/** - * @brief Clear Arbitration lost flag. - * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); -} - -/** - * @brief Clear Overrun/Underrun flag. - * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); -} - -/** - * @brief Clear SMBus PEC error flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); -} - -/** - * @brief Clear SMBus Timeout detection flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); -} - -/** - * @brief Clear SMBus Alert flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Enable automatic STOP condition generation (master mode). - * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. - * This bit has no effect in slave mode or when RELOAD bit is set. - * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); -} - -/** - * @brief Disable automatic STOP condition generation (master mode). - * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. - * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); -} - -/** - * @brief Check if automatic STOP condition is enabled or disabled. - * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); -} - -/** - * @brief Enable reload mode (master mode). - * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. - * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); -} - -/** - * @brief Disable reload mode (master mode). - * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). - * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); -} - -/** - * @brief Check if reload mode is enabled or disabled. - * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); -} - -/** - * @brief Configure the number of bytes for transfer. - * @note Changing these bits when START bit is set is not allowed. - * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize - * @param I2Cx I2C Instance. - * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); -} - -/** - * @brief Get the number of bytes configured for transfer. - * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); -} - -/** - * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code - or next received byte. - * @note Usage in Slave mode only. - * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData - * @param I2Cx I2C Instance. - * @param TypeAcknowledge This parameter can be one of the following values: - * @arg @ref LL_I2C_ACK - * @arg @ref LL_I2C_NACK - * @retval None - */ -__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); -} - -/** - * @brief Generate a START or RESTART condition - * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. - * This action has no effect when RELOAD is set. - * @rmtoll CR2 START LL_I2C_GenerateStartCondition - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_START); -} - -/** - * @brief Generate a STOP condition after the current byte transfer (master mode). - * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_STOP); -} - -/** - * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). - * @note The master sends the complete 10bit slave address read sequence : - * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address - in Read direction. - * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); -} - -/** - * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). - * @note The master only sends the first 7 bits of 10bit address in Read direction. - * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); -} - -/** - * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. - * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); -} - -/** - * @brief Configure the transfer direction (master mode). - * @note Changing these bits when START bit is set is not allowed. - * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest - * @param I2Cx I2C Instance. - * @param TransferRequest This parameter can be one of the following values: - * @arg @ref LL_I2C_REQUEST_WRITE - * @arg @ref LL_I2C_REQUEST_READ - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); -} - -/** - * @brief Get the transfer direction requested (master mode). - * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_REQUEST_WRITE - * @arg @ref LL_I2C_REQUEST_READ - */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); -} - -/** - * @brief Configure the slave address for transfer (master mode). - * @note Changing these bits when START bit is set is not allowed. - * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr - * @param I2Cx I2C Instance. - * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); -} - -/** - * @brief Get the slave address programmed for transfer. - * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0x3F - */ -__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n - * CR2 ADD10 LL_I2C_HandleTransfer\n - * CR2 RD_WRN LL_I2C_HandleTransfer\n - * CR2 START LL_I2C_HandleTransfer\n - * CR2 STOP LL_I2C_HandleTransfer\n - * CR2 RELOAD LL_I2C_HandleTransfer\n - * CR2 NBYTES LL_I2C_HandleTransfer\n - * CR2 AUTOEND LL_I2C_HandleTransfer\n - * CR2 HEAD10R LL_I2C_HandleTransfer - * @param I2Cx I2C Instance. - * @param SlaveAddr Specifies the slave address to be programmed. - * @param SlaveAddrSize This parameter can be one of the following values: - * @arg @ref LL_I2C_ADDRSLAVE_7BIT - * @arg @ref LL_I2C_ADDRSLAVE_10BIT - * @param TransferSize Specifies the number of bytes to be programmed. - * This parameter must be a value between Min_Data=0 and Max_Data=255. - * @param EndMode This parameter can be one of the following values: - * @arg @ref LL_I2C_MODE_RELOAD - * @arg @ref LL_I2C_MODE_AUTOEND - * @arg @ref LL_I2C_MODE_SOFTEND - * @arg @ref LL_I2C_MODE_SMBUS_RELOAD - * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC - * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC - * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC - * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC - * @param Request This parameter can be one of the following values: - * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP - * @arg @ref LL_I2C_GENERATE_STOP - * @arg @ref LL_I2C_GENERATE_START_READ - * @arg @ref LL_I2C_GENERATE_START_WRITE - * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ - * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE - * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ - * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE - * @retval None - */ -__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, - uint32_t TransferSize, uint32_t EndMode, uint32_t Request) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ - ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ - (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); - - /* update CR2 register */ - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | - I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | - I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - tmp); -} - -/** - * @brief Indicate the value of transfer direction (slave mode). - * @note RESET: Write transfer, Slave enters in receiver mode. - * SET: Read transfer, Slave enters in transmitter mode. - * @rmtoll ISR DIR LL_I2C_GetTransferDirection - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_DIRECTION_WRITE - * @arg @ref LL_I2C_DIRECTION_READ - */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); -} - -/** - * @brief Return the slave matched address. - * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0x3F - */ -__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); -} - -/** - * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition - or an Address Matched is received. - * This bit has no effect when RELOAD bit is set. - * This bit has no effect in device mode when SBC bit is not set. - * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); -} - -/** - * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); -} - -/** - * @brief Get the SMBus Packet Error byte calculated. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll PECR PEC LL_I2C_GetSMBusPEC - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); -} - -/** - * @brief Read Receive Data register. - * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) -{ - return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); -} - -/** - * @brief Write in Transmit Data Register . - * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 - * @param I2Cx I2C Instance. - * @param Data Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) -{ - WRITE_REG(I2Cx->TXDR, Data); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); -ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); -void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_I2C_H */ +/** + ****************************************************************************** + * @file stm32f7xx_ll_i2c.h + * @author MCD Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_LL_I2C_H +#define STM32F7xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeripheralMode; /*!< Specifies the peripheral mode. + This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetMode(). */ + + uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. + This parameter must be set by referring to the STM32CubeMX Tool and + the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetTiming(). */ + + uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. + + This feature can be modified afterwards using unitary functions + @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ + + uint32_t DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetDigitalFilter(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_AcknowledgeNextData(). */ + + uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). + This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. + + This feature can be modified afterwards using unitary function + @ref LL_I2C_SetOwnAddress1(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_I2C_WriteReg function + * @{ + */ +#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ +#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ +#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ +#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ +#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ +#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ +#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ +#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ +#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ +#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ +#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ +#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ +#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ +#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ +#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ +#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ +#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ +#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ +#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ +#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ +#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ +#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ +#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ +#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ +#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ +#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ +#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ +#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode + * @{ + */ +#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ +#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection + * @{ + */ +#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ +#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode + * @{ + */ +#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ +#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length + * @{ + */ +#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ +#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks + * @{ + */ +#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length + * @{ + */ +#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ +#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction + * @{ + */ +#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ +#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_MODE Transfer End Mode + * @{ + */ +#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ +#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode + with no HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode + with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ +#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) +/*!< Enable SMBUS Software end mode with HW PEC comparison. */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation + * @{ + */ +#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ + I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection + * @{ + */ +#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ + I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings + * @{ + */ +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) + * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF + */ +#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @note When PE = 0, the I2C SCL and SDA lines are released. + * Internal state machines and status bits are put back to their reset value. + * When cleared, PE must be kept low for at least 3 APB clock cycles. + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); +} + +/** + * @brief Configure Noise Filters (Analog and Digital). + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * The filters can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n + * CR1 DNF LL_I2C_ConfigFilters + * @param I2Cx I2C Instance. + * @param AnalogFilter This parameter can be one of the following values: + * @arg @ref LL_I2C_ANALOGFILTER_ENABLE + * @arg @ref LL_I2C_ANALOGFILTER_DISABLE + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); +} + +/** + * @brief Configure Digital Noise Filter. + * @note If the analog filter is also enabled, the digital filter is added to analog filter. + * This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter + * @param I2Cx I2C Instance. + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). + * This parameter is used to configure the digital noise filter on SDA and SCL input. + * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); +} + +/** + * @brief Get the current Digital Noise Filter configuration. + * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); +} + +/** + * @brief Enable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Disable Analog Noise Filter. + * @note This filter can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); +} + +/** + * @brief Check if Analog Noise Filter is enabled or disabled. + * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n + * RXDR RXDATA LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) + { + /* return address of TXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->TXDR); + } + else + { + /* return address of RXDR register */ + data_reg_addr = (uint32_t) &(I2Cx->RXDR); + } + + return data_reg_addr; +} + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); +} + +/** + * @brief Enable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Disable hardware byte control in slave mode. + * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); +} + +/** + * @brief Check if hardware byte control in slave mode is enabled or disabled. + * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. + * @note Changing this bit is not allowed, when the START bit is set. + * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode + * @param I2Cx I2C Instance. + * @param AddressingMode This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); +} + +/** + * @brief Get the Master addressing mode. + * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT + * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT + */ +__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); +} + +/** + * @brief Set the Own Address1. + * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n + * OAR1 OA1MODE LL_I2C_SetOwnAddress1 + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS1_7BIT + * @arg @ref LL_I2C_OWNADDRESS1_10BIT + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); +} + +/** + * @brief Enable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Disable acknowledge on Own Address1 match address. + * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); +} + +/** + * @brief Set the 7bits Own Address2. + * @note This action has no effect if own address2 is enabled. + * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n + * OAR2 OA2MSK LL_I2C_SetOwnAddress2 + * @param I2Cx I2C Instance. + * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. + * @param OwnAddrMask This parameter can be one of the following values: + * @arg @ref LL_I2C_OWNADDRESS2_NOMASK + * @arg @ref LL_I2C_OWNADDRESS2_MASK01 + * @arg @ref LL_I2C_OWNADDRESS2_MASK02 + * @arg @ref LL_I2C_OWNADDRESS2_MASK03 + * @arg @ref LL_I2C_OWNADDRESS2_MASK04 + * @arg @ref LL_I2C_OWNADDRESS2_MASK05 + * @arg @ref LL_I2C_OWNADDRESS2_MASK06 + * @arg @ref LL_I2C_OWNADDRESS2_MASK07 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) +{ + MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); +} + +/** + * @brief Enable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Disable acknowledge on Own Address2 match address. + * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); +} + +/** + * @brief Check if Own Address1 acknowledge is enabled or disabled. + * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SDA setup, hold time and the SCL high, low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming + * @param I2Cx I2C Instance. + * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. + * @note This parameter is computed with the STM32CubeMX Tool. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) +{ + WRITE_REG(I2Cx->TIMINGR, Timing); +} + +/** + * @brief Get the Timing Prescaler setting. + * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); +} + +/** + * @brief Get the SCL low period setting. + * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); +} + +/** + * @brief Get the SCL high period setting. + * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); +} + +/** + * @brief Get the SDA hold time. + * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); +} + +/** + * @brief Get the SDA setup time. + * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xF + */ +__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); +} + +/** + * @brief Configure peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n + * CR1 SMBDEN LL_I2C_SetMode + * @param I2Cx I2C Instance. + * @param PeripheralMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); +} + +/** + * @brief Get peripheral mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n + * CR1 SMBDEN LL_I2C_GetMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_MODE_I2C + * @arg @ref LL_I2C_MODE_SMBUS_HOST + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE + * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP + */ +__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); +} + +/** + * @brief Enable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is drived low and + * Alert Response Address Header acknowledge is enabled. + * SMBus Host mode: + * - SMBus Alert pin management is supported. + * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Disable SMBus alert (Host or Device mode) + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note SMBus Device mode: + * - SMBus Alert pin is not drived (can be used as a standard GPIO) and + * Alert Response Address Header acknowledge is disabled. + * SMBus Host mode: + * - SMBus Alert pin management is not supported. + * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); +} + +/** + * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Disable SMBus Packet Error Calculation (PEC). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); +} + +/** + * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n + * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @param TimeoutB + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, + uint32_t TimeoutB) +{ + MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, + TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); +} + +/** + * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); +} + +/** + * @brief Get the SMBus Clock TimeoutA setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); +} + +/** + * @brief Set the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This bit can only be programmed when TimeoutA is disabled. + * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @param TimeoutAMode This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); +} + +/** + * @brief Get the SMBus Clock TimeoutA mode. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); +} + +/** + * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note These bits can only be programmed when TimeoutB is disabled. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) +{ + WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); +} + +/** + * @brief Enable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Disable the SMBus Clock Timeout. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); +} + +/** + * @brief Check if the SMBus Clock Timeout is enabled or disabled. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n + * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout + * @param I2Cx I2C Instance. + * @param ClockTimeout This parameter can be one of the following values: + * @arg @ref LL_I2C_SMBUS_TIMEOUTA + * @arg @ref LL_I2C_SMBUS_TIMEOUTB + * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) +{ + return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Disable TXIS interrupt. + * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); +} + +/** + * @brief Check if the TXIS Interrupt is enabled or disabled. + * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Disable Address match interrupt (slave mode only). + * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); +} + +/** + * @brief Check if Address match interrupt is enabled or disabled. + * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Disable Not acknowledge received interrupt. + * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); +} + +/** + * @brief Check if Not acknowledge received interrupt is enabled or disabled. + * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Disable STOP detection interrupt. + * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); +} + +/** + * @brief Check if STOP detection interrupt is enabled or disabled. + * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Disable Transfer Complete interrupt. + * @note Any of these events will generate interrupt : + * Transfer Complete (TC) + * Transfer Complete Reload (TCR) + * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); +} + +/** + * @brief Check if Transfer Complete interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Disable Error interrupts. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Arbitration Loss (ARLO) + * Bus Error detection (BERR) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (ALERT) + * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transmit interrupt flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the received slave address matched with one of the enabled slave address. + * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Not Acknowledge received flag. + * @note RESET: Clear default value. + * SET: When a NACK is received after a byte transmission. + * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Stop detection flag. + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. + * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Transfer complete flag (master mode). + * @note RESET: Clear default value. + * SET: When RELOAD=1 and NBYTES date have been transferred. + * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag (slave mode). + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When the received PEC does not match with the PEC register content. + * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When a timeout or extended clock timeout occurs. + * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of SMBus alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note RESET: Clear default value. + * SET: When SMBus host configuration, SMBus alert enabled and + * a falling edge event occurs on SMBA pin. + * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Clear Address Matched flag. + * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); +} + +/** + * @brief Clear Not Acknowledge flag. + * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); +} + +/** + * @brief Clear Stop detection flag. + * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); +} + +/** + * @brief Clear Transmit data register empty flag (TXE). + * @note This bit can be clear by software in order to flush the transmit data register (TXDR). + * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) +{ + WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); +} + +/** + * @brief Clear SMBus PEC error flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); +} + +/** + * @brief Clear SMBus Timeout detection flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); +} + +/** + * @brief Clear SMBus Alert flag. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable automatic STOP condition generation (master mode). + * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. + * This bit has no effect in slave mode or when RELOAD bit is set. + * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Disable automatic STOP condition generation (master mode). + * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. + * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); +} + +/** + * @brief Check if automatic STOP condition is enabled or disabled. + * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); +} + +/** + * @brief Enable reload mode (master mode). + * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. + * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Disable reload mode (master mode). + * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). + * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); +} + +/** + * @brief Check if reload mode is enabled or disabled. + * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); +} + +/** + * @brief Configure the number of bytes for transfer. + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize + * @param I2Cx I2C Instance. + * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Get the number of bytes configured for transfer. + * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. + * @note Usage in Slave mode only. + * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR2 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_STOP); +} + +/** + * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master sends the complete 10bit slave address read sequence : + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). + * @note The master only sends the first 7 bits of 10bit address in Read direction. + * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); +} + +/** + * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. + * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); +} + +/** + * @brief Configure the transfer direction (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest + * @param I2Cx I2C Instance. + * @param TransferRequest This parameter can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); +} + +/** + * @brief Get the transfer direction requested (master mode). + * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_REQUEST_WRITE + * @arg @ref LL_I2C_REQUEST_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); +} + +/** + * @brief Configure the slave address for transfer (master mode). + * @note Changing these bits when START bit is set is not allowed. + * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr + * @param I2Cx I2C Instance. + * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); +} + +/** + * @brief Get the slave address programmed for transfer. + * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n + * CR2 ADD10 LL_I2C_HandleTransfer\n + * CR2 RD_WRN LL_I2C_HandleTransfer\n + * CR2 START LL_I2C_HandleTransfer\n + * CR2 STOP LL_I2C_HandleTransfer\n + * CR2 RELOAD LL_I2C_HandleTransfer\n + * CR2 NBYTES LL_I2C_HandleTransfer\n + * CR2 AUTOEND LL_I2C_HandleTransfer\n + * CR2 HEAD10R LL_I2C_HandleTransfer + * @param I2Cx I2C Instance. + * @param SlaveAddr Specifies the slave address to be programmed. + * @param SlaveAddrSize This parameter can be one of the following values: + * @arg @ref LL_I2C_ADDRSLAVE_7BIT + * @arg @ref LL_I2C_ADDRSLAVE_10BIT + * @param TransferSize Specifies the number of bytes to be programmed. + * This parameter must be a value between Min_Data=0 and Max_Data=255. + * @param EndMode This parameter can be one of the following values: + * @arg @ref LL_I2C_MODE_RELOAD + * @arg @ref LL_I2C_MODE_AUTOEND + * @arg @ref LL_I2C_MODE_SOFTEND + * @arg @ref LL_I2C_MODE_SMBUS_RELOAD + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC + * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC + * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC + * @param Request This parameter can be one of the following values: + * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP + * @arg @ref LL_I2C_GENERATE_STOP + * @arg @ref LL_I2C_GENERATE_START_READ + * @arg @ref LL_I2C_GENERATE_START_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ + * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE + * @retval None + */ +__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, + uint32_t TransferSize, uint32_t EndMode, uint32_t Request) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ + ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ + (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | + I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | + I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, + tmp); +} + +/** + * @brief Indicate the value of transfer direction (slave mode). + * @note RESET: Write transfer, Slave enters in receiver mode. + * SET: Read transfer, Slave enters in transmitter mode. + * @rmtoll ISR DIR LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); +} + +/** + * @brief Return the slave matched address. + * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); +} + +/** + * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. + * This bit has no effect when RELOAD bit is set. + * This bit has no effect in device mode when SBC bit is not set. + * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); +} + +/** + * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) +{ + return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); +} + +/** + * @brief Get the SMBus Packet Error byte calculated. + * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll PECR PEC LL_I2C_GetSMBusPEC + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); +} + +/** + * @brief Read Receive Data register. + * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + WRITE_REG(I2Cx->TXDR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_LL_I2C_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_iwdg.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_iwdg.h deleted file mode 100644 index e99ee923..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_iwdg.h +++ /dev/null @@ -1,338 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_iwdg.h - * @author MCD Application Team - * @brief Header file of IWDG LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_IWDG_H -#define STM32F7xx_LL_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(IWDG) - -/** @defgroup IWDG_LL IWDG - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants - * @{ - */ -#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ -#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ -#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ -#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants - * @{ - */ - -/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_IWDG_ReadReg function - * @{ - */ -#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ -#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ -#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */ -/** - * @} - */ - -/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider - * @{ - */ -#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ -#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */ -#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */ -#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ -#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */ -#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ -#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros - * @{ - */ - -/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in IWDG register - * @param __INSTANCE__ IWDG Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in IWDG register - * @param __INSTANCE__ IWDG Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions - * @{ - */ -/** @defgroup IWDG_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Start the Independent Watchdog - * @note Except if the hardware watchdog option is selected - * @rmtoll KR KEY LL_IWDG_Enable - * @param IWDGx IWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) -{ - WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * @rmtoll KR KEY LL_IWDG_ReloadCounter - * @param IWDGx IWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) -{ - WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); -} - -/** - * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers - * @rmtoll KR KEY LL_IWDG_EnableWriteAccess - * @param IWDGx IWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) -{ - WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); -} - -/** - * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers - * @rmtoll KR KEY LL_IWDG_DisableWriteAccess - * @param IWDGx IWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) -{ - WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); -} - -/** - * @brief Select the prescaler of the IWDG - * @rmtoll PR PR LL_IWDG_SetPrescaler - * @param IWDGx IWDG Instance - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_IWDG_PRESCALER_4 - * @arg @ref LL_IWDG_PRESCALER_8 - * @arg @ref LL_IWDG_PRESCALER_16 - * @arg @ref LL_IWDG_PRESCALER_32 - * @arg @ref LL_IWDG_PRESCALER_64 - * @arg @ref LL_IWDG_PRESCALER_128 - * @arg @ref LL_IWDG_PRESCALER_256 - * @retval None - */ -__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) -{ - WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); -} - -/** - * @brief Get the selected prescaler of the IWDG - * @rmtoll PR PR LL_IWDG_GetPrescaler - * @param IWDGx IWDG Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_IWDG_PRESCALER_4 - * @arg @ref LL_IWDG_PRESCALER_8 - * @arg @ref LL_IWDG_PRESCALER_16 - * @arg @ref LL_IWDG_PRESCALER_32 - * @arg @ref LL_IWDG_PRESCALER_64 - * @arg @ref LL_IWDG_PRESCALER_128 - * @arg @ref LL_IWDG_PRESCALER_256 - */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) -{ - return (READ_REG(IWDGx->PR)); -} - -/** - * @brief Specify the IWDG down-counter reload value - * @rmtoll RLR RL LL_IWDG_SetReloadCounter - * @param IWDGx IWDG Instance - * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF - * @retval None - */ -__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) -{ - WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); -} - -/** - * @brief Get the specified IWDG down-counter reload value - * @rmtoll RLR RL LL_IWDG_GetReloadCounter - * @param IWDGx IWDG Instance - * @retval Value between Min_Data=0 and Max_Data=0x0FFF - */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) -{ - return (READ_REG(IWDGx->RLR)); -} - -/** - * @brief Specify high limit of the window value to be compared to the down-counter. - * @rmtoll WINR WIN LL_IWDG_SetWindow - * @param IWDGx IWDG Instance - * @param Window Value between Min_Data=0 and Max_Data=0x0FFF - * @retval None - */ -__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) -{ - WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window); -} - -/** - * @brief Get the high limit of the window value specified. - * @rmtoll WINR WIN LL_IWDG_GetWindow - * @param IWDGx IWDG Instance - * @retval Value between Min_Data=0 and Max_Data=0x0FFF - */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) -{ - return (READ_REG(IWDGx->WINR)); -} - -/** - * @} - */ - -/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if flag Prescaler Value Update is set or not - * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU - * @param IWDGx IWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) -{ - return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); -} - -/** - * @brief Check if flag Reload Value Update is set or not - * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU - * @param IWDGx IWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) -{ - return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); -} - -/** - * @brief Check if flag Window Value Update is set or not - * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU - * @param IWDGx IWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) -{ - return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); -} - -/** - * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not - * @rmtoll SR PVU LL_IWDG_IsReady\n - * SR RVU LL_IWDG_IsReady\n - * SR WVU LL_IWDG_IsReady - * @param IWDGx IWDG Instance - * @retval State of bits (1 or 0). - */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) -{ - return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* IWDG */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_IWDG_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h deleted file mode 100644 index 895da0ff..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_lptim.h +++ /dev/null @@ -1,1371 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_lptim.h - * @author MCD Application Team - * @brief Header file of LPTIM LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_LPTIM_H -#define STM32F7xx_LL_LPTIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (LPTIM1) - -/** @defgroup LPTIM_LL LPTIM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure - * @{ - */ - -/** - * @brief LPTIM Init structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. - This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. - - This feature can be modified afterwards using unitary - function @ref LL_LPTIM_SetClockSource().*/ - - uint32_t Prescaler; /*!< Specifies the prescaler division ratio. - This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. - - This feature can be modified afterwards using using unitary - function @ref LL_LPTIM_SetPrescaler().*/ - - uint32_t Waveform; /*!< Specifies the waveform shape. - This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. - - This feature can be modified afterwards using unitary - function @ref LL_LPTIM_ConfigOutput().*/ - - uint32_t Polarity; /*!< Specifies waveform polarity. - This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. - - This feature can be modified afterwards using unitary - function @ref LL_LPTIM_ConfigOutput().*/ -} LL_LPTIM_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants - * @{ - */ - -/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_LPTIM_ReadReg function - * @{ - */ -#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ -#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ -#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ -#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ -#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ -#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ -#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ -/** - * @} - */ - -/** @defgroup LPTIM_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions - * @{ - */ -#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ -#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ -#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ -#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ -#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ -#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ -#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ -/** - * @} - */ - -/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode - * @{ - */ -#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!__REG__, (__VALUE__)) - -/** - * @brief Read a value in LPTIM register - * @param __INSTANCE__ LPTIM Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions - * @{ - */ - -/** Legacy definitions for compatibility purpose -@cond 0 - */ -#define LL_LPTIM_ClearFLAG_CMPM LL_LPTIM_ClearFlag_CMPM -#define LL_LPTIM_ClearFLAG_CC1 LL_LPTIM_ClearFlag_CC1 -#define LL_LPTIM_ClearFLAG_CC2 LL_LPTIM_ClearFlag_CC2 -#define LL_LPTIM_ClearFLAG_CC1O LL_LPTIM_ClearFlag_CC1O -#define LL_LPTIM_ClearFLAG_CC2O LL_LPTIM_ClearFlag_CC2O -#define LL_LPTIM_ClearFLAG_ARRM LL_LPTIM_ClearFlag_ARRM -/** -@endcond - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions - * @{ - */ - -ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); -void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration - * @{ - */ - -/** - * @brief Enable the LPTIM instance - * @note After setting the ENABLE bit, a delay of two counter clock is needed - * before the LPTIM instance is actually enabled. - * @rmtoll CR ENABLE LL_LPTIM_Enable - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE); -} - -/** - * @brief Indicates whether the LPTIM instance is enabled. - * @rmtoll CR ENABLE LL_LPTIM_IsEnabled - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); -} - -/** - * @brief Starts the LPTIM counter in the desired mode. - * @note LPTIM instance must be enabled before starting the counter. - * @note It is possible to change on the fly from One Shot mode to - * Continuous mode. - * @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n - * CR SNGSTRT LL_LPTIM_StartCounter - * @param LPTIMx Low-Power Timer instance - * @param OperatingMode This parameter can be one of the following values: - * @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS - * @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode) -{ - MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode); -} - -/** - * @brief Set the LPTIM registers update mode (enable/disable register preload) - * @note This function must be called when the LPTIM instance is disabled. - * @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode - * @param LPTIMx Low-Power Timer instance - * @param UpdateMode This parameter can be one of the following values: - * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE - * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode); -} - -/** - * @brief Get the LPTIM registers update mode - * @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE - * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); -} - -/** - * @brief Set the auto reload value - * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled - * @note After a write to the LPTIMx_ARR register a new write operation to the - * same register can only be performed when the previous write operation - * is completed. Any successive write before the ARROK flag is set, will - * lead to unpredictable results. - * @note autoreload value be strictly greater than the compare value. - * @rmtoll ARR ARR LL_LPTIM_SetAutoReload - * @param LPTIMx Low-Power Timer instance - * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) -{ - MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload); -} - -/** - * @brief Get actual auto reload value - * @rmtoll ARR ARR LL_LPTIM_GetAutoReload - * @param LPTIMx Low-Power Timer instance - * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); -} - -/** - * @brief Set the compare value - * @note After a write to the LPTIMx_CMP register a new write operation to the - * same register can only be performed when the previous write operation - * is completed. Any successive write before the CMPOK flag is set, will - * lead to unpredictable results. - * @rmtoll CMP CMP LL_LPTIM_SetCompare - * @param LPTIMx Low-Power Timer instance - * @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue) -{ - MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue); -} - -/** - * @brief Get actual compare value - * @rmtoll CMP CMP LL_LPTIM_GetCompare - * @param LPTIMx Low-Power Timer instance - * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); -} - -/** - * @brief Get actual counter value - * @note When the LPTIM instance is running with an asynchronous clock, reading - * the LPTIMx_CNT register may return unreliable values. So in this case - * it is necessary to perform two consecutive read accesses and verify - * that the two returned values are identical. - * @rmtoll CNT CNT LL_LPTIM_GetCounter - * @param LPTIMx Low-Power Timer instance - * @retval Counter value - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); -} - -/** - * @brief Set the counter mode (selection of the LPTIM counter clock source). - * @note The counter mode can be set only when the LPTIM instance is disabled. - * @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode - * @param LPTIMx Low-Power Timer instance - * @param CounterMode This parameter can be one of the following values: - * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL - * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode); -} - -/** - * @brief Get the counter mode - * @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL - * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); -} - -/** - * @brief Configure the LPTIM instance output (LPTIMx_OUT) - * @note This function must be called when the LPTIM instance is disabled. - * @note Regarding the LPTIM output polarity the change takes effect - * immediately, so the output default value will change immediately after - * the polarity is re-configured, even before the timer is enabled. - * @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n - * CFGR WAVPOL LL_LPTIM_ConfigOutput - * @param LPTIMx Low-Power Timer instance - * @param Waveform This parameter can be one of the following values: - * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM - * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR - * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity); -} - -/** - * @brief Set waveform shape - * @rmtoll CFGR WAVE LL_LPTIM_SetWaveform - * @param LPTIMx Low-Power Timer instance - * @param Waveform This parameter can be one of the following values: - * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM - * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform); -} - -/** - * @brief Get actual waveform shape - * @rmtoll CFGR WAVE LL_LPTIM_GetWaveform - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM - * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); -} - -/** - * @brief Set output polarity - * @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity - * @param LPTIMx Low-Power Timer instance - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR - * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity); -} - -/** - * @brief Get actual output polarity - * @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR - * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); -} - -/** - * @brief Set actual prescaler division ratio. - * @note This function must be called when the LPTIM instance is disabled. - * @note When the LPTIM is configured to be clocked by an internal clock source - * and the LPTIM counter is configured to be updated by active edges - * detected on the LPTIM external Input1, the internal clock provided to - * the LPTIM must be not be prescaled. - * @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler - * @param LPTIMx Low-Power Timer instance - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_LPTIM_PRESCALER_DIV1 - * @arg @ref LL_LPTIM_PRESCALER_DIV2 - * @arg @ref LL_LPTIM_PRESCALER_DIV4 - * @arg @ref LL_LPTIM_PRESCALER_DIV8 - * @arg @ref LL_LPTIM_PRESCALER_DIV16 - * @arg @ref LL_LPTIM_PRESCALER_DIV32 - * @arg @ref LL_LPTIM_PRESCALER_DIV64 - * @arg @ref LL_LPTIM_PRESCALER_DIV128 - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler); -} - -/** - * @brief Get actual prescaler division ratio. - * @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_PRESCALER_DIV1 - * @arg @ref LL_LPTIM_PRESCALER_DIV2 - * @arg @ref LL_LPTIM_PRESCALER_DIV4 - * @arg @ref LL_LPTIM_PRESCALER_DIV8 - * @arg @ref LL_LPTIM_PRESCALER_DIV16 - * @arg @ref LL_LPTIM_PRESCALER_DIV32 - * @arg @ref LL_LPTIM_PRESCALER_DIV64 - * @arg @ref LL_LPTIM_PRESCALER_DIV128 - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); -} - -/** - * @} - */ - -/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration - * @{ - */ - -/** - * @brief Enable the timeout function - * @note This function must be called when the LPTIM instance is disabled. - * @note The first trigger event will start the timer, any successive trigger - * event will reset the counter and the timer will restart. - * @note The timeout value corresponds to the compare value; if no trigger - * occurs within the expected time frame, the MCU is waked-up by the - * compare match event. - * @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); -} - -/** - * @brief Disable the timeout function - * @note This function must be called when the LPTIM instance is disabled. - * @note A trigger event arriving when the timer is already started will be - * ignored. - * @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT); -} - -/** - * @brief Indicate whether the timeout function is enabled. - * @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); -} - -/** - * @brief Start the LPTIM counter - * @note This function must be called when the LPTIM instance is disabled. - * @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN); -} - -/** - * @brief Configure the external trigger used as a trigger event for the LPTIM. - * @note This function must be called when the LPTIM instance is disabled. - * @note An internal clock source must be present when a digital filter is - * required for the trigger. - * @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n - * CFGR TRGFLT LL_LPTIM_ConfigTrigger\n - * CFGR TRIGEN LL_LPTIM_ConfigTrigger - * @param LPTIMx Low-Power Timer instance - * @param Source This parameter can be one of the following values: - * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 - * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 - * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 - * @param Filter This parameter can be one of the following values: - * @arg @ref LL_LPTIM_TRIG_FILTER_NONE - * @arg @ref LL_LPTIM_TRIG_FILTER_2 - * @arg @ref LL_LPTIM_TRIG_FILTER_4 - * @arg @ref LL_LPTIM_TRIG_FILTER_8 - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING - * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING - * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity); -} - -/** - * @brief Get actual external trigger source. - * @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1 - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2 - * @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3 - * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1 - * @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2 - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); -} - -/** - * @brief Get actual external trigger filter. - * @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_TRIG_FILTER_NONE - * @arg @ref LL_LPTIM_TRIG_FILTER_2 - * @arg @ref LL_LPTIM_TRIG_FILTER_4 - * @arg @ref LL_LPTIM_TRIG_FILTER_8 - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); -} - -/** - * @brief Get actual external trigger polarity. - * @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING - * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING - * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); -} - -/** - * @} - */ - -/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration - * @{ - */ - -/** - * @brief Set the source of the clock used by the LPTIM instance. - * @note This function must be called when the LPTIM instance is disabled. - * @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource - * @param LPTIMx Low-Power Timer instance - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL - * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource); -} - -/** - * @brief Get actual LPTIM instance clock source. - * @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL - * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); -} - -/** - * @brief Configure the active edge or edges used by the counter when - the LPTIM is clocked by an external clock source. - * @note This function must be called when the LPTIM instance is disabled. - * @note When both external clock signal edges are considered active ones, - * the LPTIM must also be clocked by an internal clock source with a - * frequency equal to at least four times the external clock frequency. - * @note An internal clock source must be present when a digital filter is - * required for external clock. - * @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n - * CFGR CKPOL LL_LPTIM_ConfigClock - * @param LPTIMx Low-Power Timer instance - * @param ClockFilter This parameter can be one of the following values: - * @arg @ref LL_LPTIM_CLK_FILTER_NONE - * @arg @ref LL_LPTIM_CLK_FILTER_2 - * @arg @ref LL_LPTIM_CLK_FILTER_4 - * @arg @ref LL_LPTIM_CLK_FILTER_8 - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_LPTIM_CLK_POLARITY_RISING - * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING - * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity); -} - -/** - * @brief Get actual clock polarity - * @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_CLK_POLARITY_RISING - * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING - * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); -} - -/** - * @brief Get actual clock digital filter - * @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_CLK_FILTER_NONE - * @arg @ref LL_LPTIM_CLK_FILTER_2 - * @arg @ref LL_LPTIM_CLK_FILTER_4 - * @arg @ref LL_LPTIM_CLK_FILTER_8 - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); -} - -/** - * @} - */ - -/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode - * @{ - */ - -/** - * @brief Configure the encoder mode. - * @note This function must be called when the LPTIM instance is disabled. - * @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode - * @param LPTIMx Low-Power Timer instance - * @param EncoderMode This parameter can be one of the following values: - * @arg @ref LL_LPTIM_ENCODER_MODE_RISING - * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING - * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode) -{ - MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode); -} - -/** - * @brief Get actual encoder mode. - * @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode - * @param LPTIMx Low-Power Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPTIM_ENCODER_MODE_RISING - * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING - * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING - */ -__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) -{ - return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); -} - -/** - * @brief Enable the encoder mode - * @note This function must be called when the LPTIM instance is disabled. - * @note In this mode the LPTIM instance must be clocked by an internal clock - * source. Also, the prescaler division ratio must be equal to 1. - * @note LPTIM instance must be configured in continuous mode prior enabling - * the encoder mode. - * @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); -} - -/** - * @brief Disable the encoder mode - * @note This function must be called when the LPTIM instance is disabled. - * @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC); -} - -/** - * @brief Indicates whether the LPTIM operates in encoder mode. - * @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); -} - -/** - * @} - */ - -/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management - * @{ - */ - - -/** - * @brief Clear the compare match flag (CMPMCF) - * @rmtoll ICR CMPMCF LL_LPTIM_ClearFlag_CMPM - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPM(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF); -} - -/** - * @brief Inform application whether a compare match interrupt has occurred. - * @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); -} - -/** - * @brief Clear the autoreload match flag (ARRMCF) - * @rmtoll ICR ARRMCF LL_LPTIM_ClearFlag_ARRM - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ClearFlag_ARRM(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF); -} - -/** - * @brief Inform application whether a autoreload match interrupt has occurred. - * @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); -} - -/** - * @brief Clear the external trigger valid edge flag(EXTTRIGCF). - * @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF); -} - -/** - * @brief Inform application whether a valid edge on the selected external trigger input has occurred. - * @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); -} - -/** - * @brief Clear the compare register update interrupt flag (CMPOKCF). - * @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF); -} - -/** - * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully - completed. If so, a new one can be initiated. - * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); -} - -/** - * @brief Clear the autoreload register update interrupt flag (ARROKCF). - * @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF); -} - -/** - * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully - completed. If so, a new one can be initiated. - * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); -} - -/** - * @brief Clear the counter direction change to up interrupt flag (UPCF). - * @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF); -} - -/** - * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance - operates in encoder mode). - * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); -} - -/** - * @brief Clear the counter direction change to down interrupt flag (DOWNCF). - * @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF); -} - -/** - * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance - operates in encoder mode). - * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); -} - -/** - * @} - */ - -/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management - * @{ - */ - -/** - * @brief Enable compare match interrupt (CMPMIE). - * @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE); -} - -/** - * @brief Disable compare match interrupt (CMPMIE). - * @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE); -} - -/** - * @brief Indicates whether the compare match interrupt (CMPMIE) is enabled. - * @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); -} - -/** - * @brief Enable autoreload match interrupt (ARRMIE). - * @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE); -} - -/** - * @brief Disable autoreload match interrupt (ARRMIE). - * @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE); -} - -/** - * @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled. - * @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); -} - -/** - * @brief Enable external trigger valid edge interrupt (EXTTRIGIE). - * @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE); -} - -/** - * @brief Disable external trigger valid edge interrupt (EXTTRIGIE). - * @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE); -} - -/** - * @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled. - * @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); -} - -/** - * @brief Enable compare register write completed interrupt (CMPOKIE). - * @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE); -} - -/** - * @brief Disable compare register write completed interrupt (CMPOKIE). - * @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE); -} - -/** - * @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled. - * @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK - * @param LPTIMx Low-Power Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); -} - -/** - * @brief Enable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE); -} - -/** - * @brief Disable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE); -} - -/** - * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. - * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK - * @param LPTIMx Low-Power Timer instance - * @retval State of bit(1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); -} - -/** - * @brief Enable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE); -} - -/** - * @brief Disable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE); -} - -/** - * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. - * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP - * @param LPTIMx Low-Power Timer instance - * @retval State of bit(1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) -{ - return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); -} - -/** - * @brief Enable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) -{ - SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE); -} - -/** - * @brief Disable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN - * @param LPTIMx Low-Power Timer instance - * @retval None - */ -__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) -{ - CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE); -} - -/** - * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. - * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN - * @param LPTIMx Low-Power Timer instance - * @retval State of bit(1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) -{ - return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* LPTIM1 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_LPTIM_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h index 88e3f70a..4c76a57c 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_pwr.h @@ -1,1016 +1,1016 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_pwr.h - * @author MCD Application Team - * @brief Header file of PWR LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_PWR_H -#define __STM32F7xx_LL_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(PWR) - -/** @defgroup PWR_LL PWR - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_PWR_WriteReg function - * @{ - */ -#define LL_PWR_CR1_CSBF PWR_CR1_CSBF /*!< Clear standby flag */ - -#define LL_PWR_CR2_CWUF6 PWR_CR2_CWUF6 /*!< Clear WKUP pin 6 */ -#define LL_PWR_CR2_CWUF5 PWR_CR2_CWUF5 /*!< Clear WKUP pin 5 */ -#define LL_PWR_CR2_CWUF4 PWR_CR2_CWUF4 /*!< Clear WKUP pin 4 */ -#define LL_PWR_CR2_CWUF3 PWR_CR2_CWUF3 /*!< Clear WKUP pin 3 */ -#define LL_PWR_CR2_CWUF2 PWR_CR2_CWUF2 /*!< Clear WKUP pin 2 */ -#define LL_PWR_CR2_CWUF1 PWR_CR2_CWUF1 /*!< Clear WKUP pin 1 */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_PWR_ReadReg function - * @{ - */ -#define LL_PWR_CSR1_WUIF PWR_CSR1_WUIF /*!< Wakeup flag */ -#define LL_PWR_CSR1_SBF PWR_CSR1_SBF /*!< Standby flag */ -#define LL_PWR_CSR1_PVDO PWR_CSR1_PVDO /*!< Power voltage detector output flag */ -#define LL_PWR_CSR1_BRR PWR_CSR1_BRR /*!< Backup Regulator ready flag */ -#define LL_PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY /*!< Voltage scaling select flag */ -#define LL_PWR_CSR1_ODRDY PWR_CSR1_ODRDY /*!< Over-drive mode ready */ -#define LL_PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY /*!< Over-drive mode switching ready */ -#define LL_PWR_CSR1_UDRDY PWR_CSR1_UDRDY /*!< Under-drive ready flag */ - -#define LL_PWR_CSR2_EWUP1 PWR_CSR2_EWUP1 /*!< Enable WKUP pin 1 */ -#define LL_PWR_CSR2_EWUP2 PWR_CSR2_EWUP2 /*!< Enable WKUP pin 2 */ -#define LL_PWR_CSR2_EWUP3 PWR_CSR2_EWUP3 /*!< Enable WKUP pin 3 */ -#define LL_PWR_CSR2_EWUP4 PWR_CSR2_EWUP4 /*!< Enable WKUP pin 4 */ -#define LL_PWR_CSR2_EWUP5 PWR_CSR2_EWUP5 /*!< Enable WKUP pin 5 */ -#define LL_PWR_CSR2_EWUP6 PWR_CSR2_EWUP6 /*!< Enable WKUP pin 6 */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_MODE_PWR Mode Power - * @{ - */ -#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode (with main Regulator ON) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR1_MRUDS | PWR_CR1_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU PWR_CR1_LPDS /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */ -#define LL_PWR_MODE_STANDBY PWR_CR1_PDDS /*!< Enter Standby mode when the CPU enters deepsleep */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage - * @{ - */ -#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_CR1_VOS_0 -#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1 -#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0 | PWR_CR1_VOS_1) -/** - * @} - */ - -/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode - * @{ - */ -#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ -#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level - * @{ - */ -#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 2.0 V */ -#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */ -#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.3 V */ -#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.5 V */ -#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.6 V */ -#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */ -#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.8 V */ -#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< Voltage threshold detected by PVD 2.9 V */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins - * @{ - */ -#define LL_PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 /*!< WKUP pin 1 : PA0 */ -#define LL_PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 /*!< WKUP pin 2 : PA2 */ -#define LL_PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 /*!< WKUP pin 3 : PC1 */ -#define LL_PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 /*!< WKUP pin 4 : PC13 */ -#define LL_PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 /*!< WKUP pin 5 : PI8 */ -#define LL_PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 /*!< WKUP pin 6 : PI11 */ -/** - * @} - */ - -/** - * @} - */ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in PWR register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) - -/** - * @brief Read a value in PWR register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) -/** - * @} - */ - -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable Under Drive Mode - * @rmtoll CR1 UDEN LL_PWR_EnableUnderDriveMode - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main Regulator or the low power Regulator - * is in low voltage mode. - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage Regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_UDEN); -} - -/** - * @brief Disable Under Drive Mode - * @rmtoll CR1 UDEN LL_PWR_DisableUnderDriveMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN); -} - -/** - * @brief Check if Under Drive Mode is enabled - * @rmtoll CR1 UDEN LL_PWR_IsEnabledUnderDriveMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN)); -} - -/** - * @brief Enable Over drive switching - * @rmtoll CR1 ODSWEN LL_PWR_EnableOverDriveSwitching - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_ODSWEN); -} - -/** - * @brief Disable Over drive switching - * @rmtoll CR1 ODSWEN LL_PWR_DisableOverDriveSwitching - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN); -} - -/** - * @brief Check if Over drive switching is enabled - * @rmtoll CR1 ODSWEN LL_PWR_IsEnabledOverDriveSwitching - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN)); -} - -/** - * @brief Enable Over drive Mode - * @rmtoll CR1 ODEN LL_PWR_EnableOverDriveMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_ODEN); -} - -/** - * @brief Disable Over drive Mode - * @rmtoll CR1 ODEN LL_PWR_DisableOverDriveMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN); -} - -/** - * @brief Check if Over drive switching is enabled - * @rmtoll CR1 ODEN LL_PWR_IsEnabledOverDriveMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN)); -} - -/** - * @brief Set the main internal Regulator output voltage - * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling - * @param VoltageScaling This parameter can be one of the following values: - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) -{ - MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); -} - -/** - * @brief Get the main internal Regulator output voltage - * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) -{ - return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); -} - -/** - * @brief Enable Main Regulator in deepsleep under-drive Mode - * @rmtoll CR1 MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_MRUDS); -} - -/** - * @brief Disable Main Regulator in deepsleep under-drive Mode - * @rmtoll CR1 MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_MRUDS); -} - -/** - * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled - * @rmtoll CR1 MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_MRUDS) == (PWR_CR1_MRUDS)); -} - -/** - * @brief Enable Low Power Regulator in deepsleep under-drive Mode - * @rmtoll CR1 LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_LPUDS); -} - -/** - * @brief Disable Low Power Regulator in deepsleep under-drive Mode - * @rmtoll CR1 LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_LPUDS); -} - -/** - * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled - * @rmtoll CR1 LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_LPUDS) == (PWR_CR1_LPUDS)); -} - -/** - * @brief Enable the Flash Power Down in Stop Mode - * @rmtoll CR1 FPDS LL_PWR_EnableFlashPowerDown - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_FPDS); -} - -/** - * @brief Disable the Flash Power Down in Stop Mode - * @rmtoll CR1 FPDS LL_PWR_DisableFlashPowerDown - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_FPDS); -} - -/** - * @brief Check if the Flash Power Down in Stop Mode is enabled - * @rmtoll CR1 FPDS LL_PWR_IsEnabledFlashPowerDown - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_FPDS) == (PWR_CR1_FPDS)); -} - -/** - * @brief Enable access to the backup domain - * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_DBP); -} - -/** - * @brief Disable access to the backup domain - * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); -} - -/** - * @brief Check if the backup domain is enabled - * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); -} - -/** - * @brief Enable Backup Regulator - * @rmtoll CSR1 BRE LL_PWR_EnableBkUpRegulator - * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and - * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup - * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, - * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that - * the data written into the RAM will be maintained in the Standby and VBAT modes. - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) -{ - SET_BIT(PWR->CSR1, PWR_CSR1_BRE); -} - -/** - * @brief Disable Backup Regulator - * @rmtoll CSR1 BRE LL_PWR_DisableBkUpRegulator - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) -{ - CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE); -} - -/** - * @brief Check if the backup Regulator is enabled - * @rmtoll CSR1 BRE LL_PWR_IsEnabledBkUpRegulator - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE)); -} - -/** - * @brief Set voltage Regulator mode during deep sleep mode - * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS - * @param RegulMode This parameter can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) -{ - MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); -} - -/** - * @brief Get voltage Regulator mode during deep sleep mode - * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_DSMODE_MAIN - * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) -{ - return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); -} - -/** - * @brief Set Power Down mode when CPU enters deepsleep - * @rmtoll CR1 PDDS LL_PWR_SetPowerMode\n - * CR1 LPDS LL_PWR_SetPowerMode\n - * CR1 FPDS LL_PWR_SetPowerMode\n - * CR1 LPUDS LL_PWR_SetPowerMode\n - * CR1 MRUDS LL_PWR_SetPowerMode - * @param PDMode This parameter can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE - * @arg @ref LL_PWR_MODE_STANDBY - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) -{ - MODIFY_REG(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS), PDMode); -} - -/** - * @brief Get Power Down mode when CPU enters deepsleep - * @rmtoll CR1 PDDS LL_PWR_GetPowerMode\n - * CR1 LPDS LL_PWR_GetPowerMode\n - * CR1 FPDS LL_PWR_GetPowerMode\n - * CR1 LPUDS LL_PWR_GetPowerMode\n - * CR1 MRUDS LL_PWR_GetPowerMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_MODE_STOP_MAINREGU - * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE - * @arg @ref LL_PWR_MODE_STOP_LPREGU - * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE - * @arg @ref LL_PWR_MODE_STANDBY - */ -__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) -{ - return (uint32_t)(READ_BIT(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS))); -} - -/** - * @brief Configure the voltage threshold detected by the Power Voltage Detector - * @rmtoll CR1 PLS LL_PWR_SetPVDLevel - * @param PVDLevel This parameter can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) -{ - MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); -} - -/** - * @brief Get the voltage threshold detection - * @rmtoll CR1 PLS LL_PWR_GetPVDLevel - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - */ -__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) -{ - return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); -} - -/** - * @brief Enable Power Voltage Detector - * @rmtoll CR1 PVDE LL_PWR_EnablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_PVDE); -} - -/** - * @brief Disable Power Voltage Detector - * @rmtoll CR1 PVDE LL_PWR_DisablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); -} - -/** - * @brief Check if Power Voltage Detector is enabled - * @rmtoll CR1 PVDE LL_PWR_IsEnabledPVD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE)); -} - -/** - * @brief Enable the WakeUp PINx functionality - * @rmtoll CSR2 EWUP1 LL_PWR_EnableWakeUpPin\n - * CSR2 EWUP2 LL_PWR_EnableWakeUpPin\n - * CSR2 EWUP3 LL_PWR_EnableWakeUpPin\n - * CSR2 EWUP4 LL_PWR_EnableWakeUpPin\n - * CSR2 EWUP5 LL_PWR_EnableWakeUpPin\n - * CSR2 EWUP6 LL_PWR_EnableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) -{ - SET_BIT(PWR->CSR2, WakeUpPin); -} - -/** - * @brief Disable the WakeUp PINx functionality - * @rmtoll CSR2 EWUP1 LL_PWR_DisableWakeUpPin\n - * CSR2 EWUP2 LL_PWR_DisableWakeUpPin\n - * CSR2 EWUP3 LL_PWR_DisableWakeUpPin\n - * CSR2 EWUP4 LL_PWR_DisableWakeUpPin\n - * CSR2 EWUP5 LL_PWR_DisableWakeUpPin\n - * CSR2 EWUP6 LL_PWR_DisableWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) -{ - CLEAR_BIT(PWR->CSR2, WakeUpPin); -} - -/** - * @brief Check if the WakeUp PINx functionality is enabled - * @rmtoll CSR2 EWUP1 LL_PWR_IsEnabledWakeUpPin\n - * CSR2 EWUP2 LL_PWR_IsEnabledWakeUpPin\n - * CSR2 EWUP3 LL_PWR_IsEnabledWakeUpPin\n - * CSR2 EWUP4 LL_PWR_IsEnabledWakeUpPin\n - * CSR2 EWUP5 LL_PWR_IsEnabledWakeUpPin\n - * CSR2 EWUP6 LL_PWR_IsEnabledWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) -{ - return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin)); -} - -/** - * @brief Set the Wake-Up pin polarity low for the event detection - * @rmtoll CR2 WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n - * CR2 WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n - * CR2 WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n - * CR2 WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n - * CR2 WUPP5 LL_PWR_SetWakeUpPinPolarityLow\n - * CR2 WUPP6 LL_PWR_SetWakeUpPinPolarityLow - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) -{ - SET_BIT(PWR->CR2, WakeUpPin); -} - -/** - * @brief Set the Wake-Up pin polarity high for the event detection - * @rmtoll CR2 WUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n - * CR2 WUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n - * CR2 WUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n - * CR2 WUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n - * CR2 WUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n - * CR2 WUPP6 LL_PWR_SetWakeUpPinPolarityHigh - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) -{ - CLEAR_BIT(PWR->CR2, WakeUpPin); -} - -/** - * @brief Get the Wake-Up pin polarity for the event detection - * @rmtoll CR2 WUPP1 LL_PWR_IsWakeUpPinPolarityLow\n - * CR2 WUPP2 LL_PWR_IsWakeUpPinPolarityLow\n - * CR2 WUPP3 LL_PWR_IsWakeUpPinPolarityLow\n - * CR2 WUPP4 LL_PWR_IsWakeUpPinPolarityLow\n - * CR2 WUPP5 LL_PWR_IsWakeUpPinPolarityLow\n - * CR2 WUPP6 LL_PWR_IsWakeUpPinPolarityLow - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) -{ - return (READ_BIT(PWR->CR2, WakeUpPin) == (WakeUpPin)); -} - -/** - * @brief Enable Internal WakeUp - * @rmtoll CSR1 EIWUP LL_PWR_EnableInternalWakeUp - * @note This API must be used when RTC events (Alarm A or Alarm B, RTC Tamper, RTC TimeStamp - * or RTC Wakeup time) are used to wake up the system from Standby mode. - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableInternalWakeUp(void) -{ - SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP); -} - -/** - * @brief Disable Internal WakeUp - * @rmtoll CSR1 EIWUP LL_PWR_DisableInternalWakeUp - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableInternalWakeUp(void) -{ - CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP); -} - -/** - * @brief Check if the Internal WakeUp functionality is enabled - * @rmtoll CSR1 EIWUP LL_PWR_IsEnabledInternalWakeUp - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternalWakeUp(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP)); -} - -/** - * @} - */ - -/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Wake-up Flag 6 - * @rmtoll CSR2 WUPF6 LL_PWR_IsActiveFlag_WU6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) -{ - return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6)); -} - -/** - * @brief Get Wake-up Flag 5 - * @rmtoll CSR2 WUPF5 LL_PWR_IsActiveFlag_WU5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) -{ - return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5)); -} - -/** - * @brief Get Wake-up Flag 4 - * @rmtoll CSR2 WUPF4 LL_PWR_IsActiveFlag_WU4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) -{ - return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4)); -} - -/** - * @brief Get Wake-up Flag 3 - * @rmtoll CSR2 WUPF3 LL_PWR_IsActiveFlag_WU3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) -{ - return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3)); -} - -/** - * @brief Get Wake-up Flag 2 - * @rmtoll CSR2 WUPF2 LL_PWR_IsActiveFlag_WU2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) -{ - return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2)); -} - -/** - * @brief Get Wake-up Flag 1 - * @rmtoll CSR2 WUPF1 LL_PWR_IsActiveFlag_WU1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) -{ - return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1)); -} - -/** - * @brief Get Standby Flag - * @rmtoll CSR1 SBF LL_PWR_IsActiveFlag_SB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF)); -} - -/** - * @brief Indicate whether VDD voltage is below the selected PVD threshold - * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)); -} - -/** - * @brief Get Backup Regulator ready Flag - * @rmtoll CSR1 BRR LL_PWR_IsActiveFlag_BRR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR)); -} - -/** - * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level - * @rmtoll CSR1 VOSRDY LL_PWR_IsActiveFlag_VOS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY)); -} - -/** - * @brief Indicate whether the Over-Drive mode is ready or not - * @rmtoll CSR1 ODRDY LL_PWR_IsActiveFlag_OD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_ODRDY) == (PWR_CSR1_ODRDY)); -} - -/** - * @brief Indicate whether the Over-Drive mode switching is ready or not - * @rmtoll CSR1 ODSWRDY LL_PWR_IsActiveFlag_ODSW - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_ODSWRDY) == (PWR_CSR1_ODSWRDY)); -} - -/** - * @brief Indicate whether the Under-Drive mode is ready or not - * @rmtoll CSR1 UDRDY LL_PWR_IsActiveFlag_UD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void) -{ - return (READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY) == (PWR_CSR1_UDRDY)); -} - -/** - * @brief Clear Standby Flag - * @rmtoll CR1 CSBF LL_PWR_ClearFlag_SB - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_CSBF); -} - -/** - * @brief Clear Wake-up Flag 6 - * @rmtoll CR2 CWUF6 LL_PWR_ClearFlag_WU6 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) -{ - WRITE_REG(PWR->CR2, PWR_CR2_CWUPF6); -} - -/** - * @brief Clear Wake-up Flag 5 - * @rmtoll CR2 CWUF5 LL_PWR_ClearFlag_WU5 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) -{ - WRITE_REG(PWR->CR2, PWR_CR2_CWUPF5); -} - -/** - * @brief Clear Wake-up Flag 4 - * @rmtoll CR2 CWUF4 LL_PWR_ClearFlag_WU4 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) -{ - WRITE_REG(PWR->CR2, PWR_CR2_CWUPF4); -} - -/** - * @brief Clear Wake-up Flag 3 - * @rmtoll CR2 CWUF3 LL_PWR_ClearFlag_WU3 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) -{ - WRITE_REG(PWR->CR2, PWR_CR2_CWUPF3); -} - -/** - * @brief Clear Wake-up Flag 2 - * @rmtoll CR2 CWUF2 LL_PWR_ClearFlag_WU2 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) -{ - WRITE_REG(PWR->CR2, PWR_CR2_CWUPF2); -} - -/** - * @brief Clear Wake-up Flag 1 - * @rmtoll CR2 CWUF1 LL_PWR_ClearFlag_WU1 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) -{ - WRITE_REG(PWR->CR2, PWR_CR2_CWUPF1); -} - -/** - * @brief Clear Under-Drive ready Flag - * @rmtoll CSR1 UDRDY LL_PWR_ClearFlag_UD - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_UD(void) -{ - WRITE_REG(PWR->CSR1, PWR_CSR1_UDRDY); -} - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup PWR_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_PWR_DeInit(void); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(PWR) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_PWR_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_pwr.h + * @author MCD Application Team + * @brief Header file of PWR LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_PWR_H +#define __STM32F7xx_LL_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(PWR) + +/** @defgroup PWR_LL PWR + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants + * @{ + */ + +/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_PWR_WriteReg function + * @{ + */ +#define LL_PWR_CR1_CSBF PWR_CR1_CSBF /*!< Clear standby flag */ + +#define LL_PWR_CR2_CWUF6 PWR_CR2_CWUF6 /*!< Clear WKUP pin 6 */ +#define LL_PWR_CR2_CWUF5 PWR_CR2_CWUF5 /*!< Clear WKUP pin 5 */ +#define LL_PWR_CR2_CWUF4 PWR_CR2_CWUF4 /*!< Clear WKUP pin 4 */ +#define LL_PWR_CR2_CWUF3 PWR_CR2_CWUF3 /*!< Clear WKUP pin 3 */ +#define LL_PWR_CR2_CWUF2 PWR_CR2_CWUF2 /*!< Clear WKUP pin 2 */ +#define LL_PWR_CR2_CWUF1 PWR_CR2_CWUF1 /*!< Clear WKUP pin 1 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_PWR_ReadReg function + * @{ + */ +#define LL_PWR_CSR1_WUIF PWR_CSR1_WUIF /*!< Wakeup flag */ +#define LL_PWR_CSR1_SBF PWR_CSR1_SBF /*!< Standby flag */ +#define LL_PWR_CSR1_PVDO PWR_CSR1_PVDO /*!< Power voltage detector output flag */ +#define LL_PWR_CSR1_BRR PWR_CSR1_BRR /*!< Backup Regulator ready flag */ +#define LL_PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY /*!< Voltage scaling select flag */ +#define LL_PWR_CSR1_ODRDY PWR_CSR1_ODRDY /*!< Over-drive mode ready */ +#define LL_PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY /*!< Over-drive mode switching ready */ +#define LL_PWR_CSR1_UDRDY PWR_CSR1_UDRDY /*!< Under-drive ready flag */ + +#define LL_PWR_CSR2_EWUP1 PWR_CSR2_EWUP1 /*!< Enable WKUP pin 1 */ +#define LL_PWR_CSR2_EWUP2 PWR_CSR2_EWUP2 /*!< Enable WKUP pin 2 */ +#define LL_PWR_CSR2_EWUP3 PWR_CSR2_EWUP3 /*!< Enable WKUP pin 3 */ +#define LL_PWR_CSR2_EWUP4 PWR_CSR2_EWUP4 /*!< Enable WKUP pin 4 */ +#define LL_PWR_CSR2_EWUP5 PWR_CSR2_EWUP5 /*!< Enable WKUP pin 5 */ +#define LL_PWR_CSR2_EWUP6 PWR_CSR2_EWUP6 /*!< Enable WKUP pin 6 */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_MODE_PWR Mode Power + * @{ + */ +#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U /*!< Enter Stop mode (with main Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR1_MRUDS | PWR_CR1_FPDS) /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU PWR_CR1_LPDS /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_FPDS) /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */ +#define LL_PWR_MODE_STANDBY PWR_CR1_PDDS /*!< Enter Standby mode when the CPU enters deepsleep */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage + * @{ + */ +#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_CR1_VOS_0 +#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_CR1_VOS_1 +#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0 | PWR_CR1_VOS_1) +/** + * @} + */ + +/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode + * @{ + */ +#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ +#define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level + * @{ + */ +#define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 2.0 V */ +#define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */ +#define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.3 V */ +#define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.5 V */ +#define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.6 V */ +#define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */ +#define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.8 V */ +#define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< Voltage threshold detected by PVD 2.9 V */ +/** + * @} + */ + +/** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins + * @{ + */ +#define LL_PWR_WAKEUP_PIN1 PWR_CSR2_EWUP1 /*!< WKUP pin 1 : PA0 */ +#define LL_PWR_WAKEUP_PIN2 PWR_CSR2_EWUP2 /*!< WKUP pin 2 : PA2 */ +#define LL_PWR_WAKEUP_PIN3 PWR_CSR2_EWUP3 /*!< WKUP pin 3 : PC1 */ +#define LL_PWR_WAKEUP_PIN4 PWR_CSR2_EWUP4 /*!< WKUP pin 4 : PC13 */ +#define LL_PWR_WAKEUP_PIN5 PWR_CSR2_EWUP5 /*!< WKUP pin 5 : PI8 */ +#define LL_PWR_WAKEUP_PIN6 PWR_CSR2_EWUP6 /*!< WKUP pin 6 : PI11 */ +/** + * @} + */ + +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros + * @{ + */ + +/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in PWR register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) + +/** + * @brief Read a value in PWR register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) +/** + * @} + */ + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable Under Drive Mode + * @rmtoll CR1 UDEN LL_PWR_EnableUnderDriveMode + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main Regulator or the low power Regulator + * is in low voltage mode. + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage Regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_UDEN); +} + +/** + * @brief Disable Under Drive Mode + * @rmtoll CR1 UDEN LL_PWR_DisableUnderDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN); +} + +/** + * @brief Check if Under Drive Mode is enabled + * @rmtoll CR1 UDEN LL_PWR_IsEnabledUnderDriveMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN)); +} + +/** + * @brief Enable Over drive switching + * @rmtoll CR1 ODSWEN LL_PWR_EnableOverDriveSwitching + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ODSWEN); +} + +/** + * @brief Disable Over drive switching + * @rmtoll CR1 ODSWEN LL_PWR_DisableOverDriveSwitching + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN); +} + +/** + * @brief Check if Over drive switching is enabled + * @rmtoll CR1 ODSWEN LL_PWR_IsEnabledOverDriveSwitching + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN)); +} + +/** + * @brief Enable Over drive Mode + * @rmtoll CR1 ODEN LL_PWR_EnableOverDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_ODEN); +} + +/** + * @brief Disable Over drive Mode + * @rmtoll CR1 ODEN LL_PWR_DisableOverDriveMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN); +} + +/** + * @brief Check if Over drive switching is enabled + * @rmtoll CR1 ODEN LL_PWR_IsEnabledOverDriveMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN)); +} + +/** + * @brief Set the main internal Regulator output voltage + * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling + * @param VoltageScaling This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); +} + +/** + * @brief Get the main internal Regulator output voltage + * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 + * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); +} + +/** + * @brief Enable Main Regulator in deepsleep under-drive Mode + * @rmtoll CR1 MRUDS LL_PWR_EnableMainRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_MRUDS); +} + +/** + * @brief Disable Main Regulator in deepsleep under-drive Mode + * @rmtoll CR1 MRUDS LL_PWR_DisableMainRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_MRUDS); +} + +/** + * @brief Check if Main Regulator in deepsleep under-drive Mode is enabled + * @rmtoll CR1 MRUDS LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_MRUDS) == (PWR_CR1_MRUDS)); +} + +/** + * @brief Enable Low Power Regulator in deepsleep under-drive Mode + * @rmtoll CR1 LPUDS LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_LPUDS); +} + +/** + * @brief Disable Low Power Regulator in deepsleep under-drive Mode + * @rmtoll CR1 LPUDS LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPUDS); +} + +/** + * @brief Check if Low Power Regulator in deepsleep under-drive Mode is enabled + * @rmtoll CR1 LPUDS LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_LPUDS) == (PWR_CR1_LPUDS)); +} + +/** + * @brief Enable the Flash Power Down in Stop Mode + * @rmtoll CR1 FPDS LL_PWR_EnableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_FPDS); +} + +/** + * @brief Disable the Flash Power Down in Stop Mode + * @rmtoll CR1 FPDS LL_PWR_DisableFlashPowerDown + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_FPDS); +} + +/** + * @brief Check if the Flash Power Down in Stop Mode is enabled + * @rmtoll CR1 FPDS LL_PWR_IsEnabledFlashPowerDown + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_FPDS) == (PWR_CR1_FPDS)); +} + +/** + * @brief Enable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disable access to the backup domain + * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Check if the backup domain is enabled + * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); +} + +/** + * @brief Enable Backup Regulator + * @rmtoll CSR1 BRE LL_PWR_EnableBkUpRegulator + * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and + * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup + * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, + * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that + * the data written into the RAM will be maintained in the Standby and VBAT modes. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) +{ + SET_BIT(PWR->CSR1, PWR_CSR1_BRE); +} + +/** + * @brief Disable Backup Regulator + * @rmtoll CSR1 BRE LL_PWR_DisableBkUpRegulator + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) +{ + CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE); +} + +/** + * @brief Check if the backup Regulator is enabled + * @rmtoll CSR1 BRE LL_PWR_IsEnabledBkUpRegulator + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE)); +} + +/** + * @brief Set voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS + * @param RegulMode This parameter can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); +} + +/** + * @brief Get voltage Regulator mode during deep sleep mode + * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_REGU_DSMODE_MAIN + * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER + */ +__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); +} + +/** + * @brief Set Power Down mode when CPU enters deepsleep + * @rmtoll CR1 PDDS LL_PWR_SetPowerMode\n + * CR1 LPDS LL_PWR_SetPowerMode\n + * CR1 FPDS LL_PWR_SetPowerMode\n + * CR1 LPUDS LL_PWR_SetPowerMode\n + * CR1 MRUDS LL_PWR_SetPowerMode + * @param PDMode This parameter can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE + * @arg @ref LL_PWR_MODE_STANDBY + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode) +{ + MODIFY_REG(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS), PDMode); +} + +/** + * @brief Get Power Down mode when CPU enters deepsleep + * @rmtoll CR1 PDDS LL_PWR_GetPowerMode\n + * CR1 LPDS LL_PWR_GetPowerMode\n + * CR1 FPDS LL_PWR_GetPowerMode\n + * CR1 LPUDS LL_PWR_GetPowerMode\n + * CR1 MRUDS LL_PWR_GetPowerMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_MODE_STOP_MAINREGU + * @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE + * @arg @ref LL_PWR_MODE_STOP_LPREGU + * @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE + * @arg @ref LL_PWR_MODE_STANDBY + */ +__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS))); +} + +/** + * @brief Configure the voltage threshold detected by the Power Voltage Detector + * @rmtoll CR1 PLS LL_PWR_SetPVDLevel + * @param PVDLevel This parameter can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) +{ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); +} + +/** + * @brief Get the voltage threshold detection + * @rmtoll CR1 PLS LL_PWR_GetPVDLevel + * @retval Returned value can be one of the following values: + * @arg @ref LL_PWR_PVDLEVEL_0 + * @arg @ref LL_PWR_PVDLEVEL_1 + * @arg @ref LL_PWR_PVDLEVEL_2 + * @arg @ref LL_PWR_PVDLEVEL_3 + * @arg @ref LL_PWR_PVDLEVEL_4 + * @arg @ref LL_PWR_PVDLEVEL_5 + * @arg @ref LL_PWR_PVDLEVEL_6 + * @arg @ref LL_PWR_PVDLEVEL_7 + */ +__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) +{ + return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); +} + +/** + * @brief Enable Power Voltage Detector + * @rmtoll CR1 PVDE LL_PWR_EnablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnablePVD(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Disable Power Voltage Detector + * @rmtoll CR1 PVDE LL_PWR_DisablePVD + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisablePVD(void) +{ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Check if Power Voltage Detector is enabled + * @rmtoll CR1 PVDE LL_PWR_IsEnabledPVD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) +{ + return (READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE)); +} + +/** + * @brief Enable the WakeUp PINx functionality + * @rmtoll CSR2 EWUP1 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP2 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP3 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP4 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP5 LL_PWR_EnableWakeUpPin\n + * CSR2 EWUP6 LL_PWR_EnableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CSR2, WakeUpPin); +} + +/** + * @brief Disable the WakeUp PINx functionality + * @rmtoll CSR2 EWUP1 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP2 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP3 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP4 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP5 LL_PWR_DisableWakeUpPin\n + * CSR2 EWUP6 LL_PWR_DisableWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CSR2, WakeUpPin); +} + +/** + * @brief Check if the WakeUp PINx functionality is enabled + * @rmtoll CSR2 EWUP1 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP2 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP3 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP4 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP5 LL_PWR_IsEnabledWakeUpPin\n + * CSR2 EWUP6 LL_PWR_IsEnabledWakeUpPin + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin)); +} + +/** + * @brief Set the Wake-Up pin polarity low for the event detection + * @rmtoll CR2 WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP5 LL_PWR_SetWakeUpPinPolarityLow\n + * CR2 WUPP6 LL_PWR_SetWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + SET_BIT(PWR->CR2, WakeUpPin); +} + +/** + * @brief Set the Wake-Up pin polarity high for the event detection + * @rmtoll CR2 WUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n + * CR2 WUPP6 LL_PWR_SetWakeUpPinPolarityHigh + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) +{ + CLEAR_BIT(PWR->CR2, WakeUpPin); +} + +/** + * @brief Get the Wake-Up pin polarity for the event detection + * @rmtoll CR2 WUPP1 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP2 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP3 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP4 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP5 LL_PWR_IsWakeUpPinPolarityLow\n + * CR2 WUPP6 LL_PWR_IsWakeUpPinPolarityLow + * @param WakeUpPin This parameter can be one of the following values: + * @arg @ref LL_PWR_WAKEUP_PIN1 + * @arg @ref LL_PWR_WAKEUP_PIN2 + * @arg @ref LL_PWR_WAKEUP_PIN3 + * @arg @ref LL_PWR_WAKEUP_PIN4 + * @arg @ref LL_PWR_WAKEUP_PIN5 + * @arg @ref LL_PWR_WAKEUP_PIN6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) +{ + return (READ_BIT(PWR->CR2, WakeUpPin) == (WakeUpPin)); +} + +/** + * @brief Enable Internal WakeUp + * @rmtoll CSR1 EIWUP LL_PWR_EnableInternalWakeUp + * @note This API must be used when RTC events (Alarm A or Alarm B, RTC Tamper, RTC TimeStamp + * or RTC Wakeup time) are used to wake up the system from Standby mode. + * @retval None + */ +__STATIC_INLINE void LL_PWR_EnableInternalWakeUp(void) +{ + SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP); +} + +/** + * @brief Disable Internal WakeUp + * @rmtoll CSR1 EIWUP LL_PWR_DisableInternalWakeUp + * @retval None + */ +__STATIC_INLINE void LL_PWR_DisableInternalWakeUp(void) +{ + CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP); +} + +/** + * @brief Check if the Internal WakeUp functionality is enabled + * @rmtoll CSR1 EIWUP LL_PWR_IsEnabledInternalWakeUp + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternalWakeUp(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP)); +} + +/** + * @} + */ + +/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Wake-up Flag 6 + * @rmtoll CSR2 WUPF6 LL_PWR_IsActiveFlag_WU6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6)); +} + +/** + * @brief Get Wake-up Flag 5 + * @rmtoll CSR2 WUPF5 LL_PWR_IsActiveFlag_WU5 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5)); +} + +/** + * @brief Get Wake-up Flag 4 + * @rmtoll CSR2 WUPF4 LL_PWR_IsActiveFlag_WU4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4)); +} + +/** + * @brief Get Wake-up Flag 3 + * @rmtoll CSR2 WUPF3 LL_PWR_IsActiveFlag_WU3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3)); +} + +/** + * @brief Get Wake-up Flag 2 + * @rmtoll CSR2 WUPF2 LL_PWR_IsActiveFlag_WU2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2)); +} + +/** + * @brief Get Wake-up Flag 1 + * @rmtoll CSR2 WUPF1 LL_PWR_IsActiveFlag_WU1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) +{ + return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1)); +} + +/** + * @brief Get Standby Flag + * @rmtoll CSR1 SBF LL_PWR_IsActiveFlag_SB + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF)); +} + +/** + * @brief Indicate whether VDD voltage is below the selected PVD threshold + * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)); +} + +/** + * @brief Get Backup Regulator ready Flag + * @rmtoll CSR1 BRR LL_PWR_IsActiveFlag_BRR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR)); +} + +/** + * @brief Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level + * @rmtoll CSR1 VOSRDY LL_PWR_IsActiveFlag_VOS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY)); +} + +/** + * @brief Indicate whether the Over-Drive mode is ready or not + * @rmtoll CSR1 ODRDY LL_PWR_IsActiveFlag_OD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_ODRDY) == (PWR_CSR1_ODRDY)); +} + +/** + * @brief Indicate whether the Over-Drive mode switching is ready or not + * @rmtoll CSR1 ODSWRDY LL_PWR_IsActiveFlag_ODSW + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_ODSWRDY) == (PWR_CSR1_ODSWRDY)); +} + +/** + * @brief Indicate whether the Under-Drive mode is ready or not + * @rmtoll CSR1 UDRDY LL_PWR_IsActiveFlag_UD + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void) +{ + return (READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY) == (PWR_CSR1_UDRDY)); +} + +/** + * @brief Clear Standby Flag + * @rmtoll CR1 CSBF LL_PWR_ClearFlag_SB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) +{ + SET_BIT(PWR->CR1, PWR_CR1_CSBF); +} + +/** + * @brief Clear Wake-up Flag 6 + * @rmtoll CR2 CWUF6 LL_PWR_ClearFlag_WU6 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF6); +} + +/** + * @brief Clear Wake-up Flag 5 + * @rmtoll CR2 CWUF5 LL_PWR_ClearFlag_WU5 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF5); +} + +/** + * @brief Clear Wake-up Flag 4 + * @rmtoll CR2 CWUF4 LL_PWR_ClearFlag_WU4 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF4); +} + +/** + * @brief Clear Wake-up Flag 3 + * @rmtoll CR2 CWUF3 LL_PWR_ClearFlag_WU3 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF3); +} + +/** + * @brief Clear Wake-up Flag 2 + * @rmtoll CR2 CWUF2 LL_PWR_ClearFlag_WU2 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF2); +} + +/** + * @brief Clear Wake-up Flag 1 + * @rmtoll CR2 CWUF1 LL_PWR_ClearFlag_WU1 + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) +{ + WRITE_REG(PWR->CR2, PWR_CR2_CWUPF1); +} + +/** + * @brief Clear Under-Drive ready Flag + * @rmtoll CSR1 UDRDY LL_PWR_ClearFlag_UD + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_UD(void) +{ + WRITE_REG(PWR->CSR1, PWR_CSR1_UDRDY); +} + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup PWR_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_PWR_DeInit(void); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(PWR) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_PWR_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h index 360cc30d..209f35b6 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rcc.h @@ -1,5170 +1,5170 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_rcc.h - * @author MCD Application Team - * @brief Header file of RCC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_RCC_H -#define __STM32F7xx_LL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Variables RCC Private Variables - * @{ - */ - -#if defined(RCC_DCKCFGR1_PLLSAIDIVR) -static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; -#endif /* RCC_DCKCFGR1_PLLSAIDIVR */ - -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Private_Macros RCC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Exported_Types RCC Exported Types - * @{ - */ - -/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure - * @{ - */ - -/** - * @brief RCC Clocks Frequency Structure - */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ -} LL_RCC_ClocksTypeDef; - -/** - * @} - */ - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation - * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to - * HW set-up. - * @{ - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ -#endif /* HSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ -#endif /* LSI_VALUE */ - -#if !defined (EXTERNAL_CLOCK_VALUE) -#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ -#endif /* EXTERNAL_CLOCK_VALUE */ - -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) -#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) -#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ -#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_RCC_WriteReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ -#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ -#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ -#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ -#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ -#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ -#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ -#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_RCC_ReadReg function - * @{ - */ -#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ -#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ -#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ -#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ -#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ -#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ -#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions - * @{ - */ -#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ -#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ -#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ -#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ -#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ -#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ -#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability - * @{ - */ -#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ -#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler - * @{ - */ -#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ -#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ -#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ -#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ -#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ -#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ -#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ -#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ -#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) - * @{ - */ -#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ -#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ -#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ -#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ -/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) - * @{ - */ -#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ -#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ -#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ -#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection - * @{ - */ -#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ -#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ -#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ -#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ -#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler - * @{ - */ -#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ -#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ -#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ -#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ -#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ -#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ -#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ -#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ -#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ -#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock - * @{ - */ -#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ -#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ -#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ -#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ -#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ -#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ -#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ -#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ -#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ -#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ -#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ -#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ -#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ -#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ -#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ -#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ -#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ -#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ -#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ -#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ -#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ -#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ -#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ -#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ -#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ -#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ -#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ -#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ -#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ -#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ -#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency - * @{ - */ -#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection - * @{ - */ -#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL) /*!< LSE clock used as USART1 clock source */ -#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL) /*!< LSE clock used as USART2 clock source */ -#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL) /*!< LSE clock used as USART3 clock source */ -#define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART6 clock source */ -#define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_0) /*!< SYSCLK clock used as USART6 clock source */ -#define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_1) /*!< HSI clock used as USART6 clock source */ -#define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL) /*!< LSE clock used as USART6 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection - * @{ - */ -#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */ -#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ -#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ -#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL) /*!< LSE clock used as UART4 clock source */ -#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */ -#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ -#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ -#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL) /*!< LSE clock used as UART5 clock source */ -#define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */ -#define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_0) /*!< SYSCLK clock used as UART7 clock source */ -#define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_1) /*!< HSI clock used as UART7 clock source */ -#define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL) /*!< LSE clock used as UART7 clock source */ -#define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */ -#define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_0) /*!< SYSCLK clock used as UART8 clock source */ -#define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_1) /*!< HSI clock used as UART8 clock source */ -#define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL) /*!< LSE clock used as UART8 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection - * @{ - */ -#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /*!< HSI clock used as I2C1 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C2 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /*!< HSI clock used as I2C2 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 clock used as I2C3 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C3 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /*!< HSI clock used as I2C3 clock source */ -#if defined(I2C4) -#define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 clock used as I2C4 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C4 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /*!< HSI clock used as I2C4 clock source */ -#endif /* I2C4 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection - * @{ - */ -#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection - * @{ - */ -#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_1 >> 16U)) /*!< External pin clock used as SAI1 clock source */ -#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) -#define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL >> 16U)) /*!< Main source clock used as SAI1 clock source */ -#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ -#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_1 >> 16U)) /*!< External pin clock used as SAI2 clock source */ -#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) -#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL >> 16U)) /*!< Main source clock used as SAI2 clock source */ -#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection - * @{ - */ -#define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC1 clock */ -#define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SDMMC1SEL >> 16U)) /*!< System clock clock used as SDMMC1 clock */ -#if defined(SDMMC2) -#define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC2 clock */ -#define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SDMMC2SEL >> 16U)) /*!< System clock clock used as SDMMC2 clock */ -#endif /* SDMMC2 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection - * @{ - */ -#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as RNG clock source */ -#define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI clock used as RNG clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection - * @{ - */ -#define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as USB clock source */ -#define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI1 clock used as USB clock source */ -/** - * @} - */ - -#if defined(DSI) -/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection - * @{ - */ -#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ -#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */ -/** - * @} - */ -#endif /* DSI */ - -#if defined(CEC) -/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection - * @{ - */ -#define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE oscillator clock used as CEC clock */ -#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /*!< HSI oscillator clock divided by 488 used as CEC clock */ -/** - * @} - */ -#endif /* CEC */ - -/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection - * @{ - */ -#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ -#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection - * @{ - */ -#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ -#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ -/** - * @} - */ - -#if defined(DFSDM1_Channel0) -/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection - * @{ - */ -#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */ -#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /*!< SAI2 clock used as DFSDM1 Audio clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection - * @{ - */ -#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ -#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /*!< System clock used as DFSDM1 clock */ -/** - * @} - */ -#endif /* DFSDM1_Channel0 */ - -/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source - * @{ - */ -#define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selection */ -#define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selection */ -#define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selection */ -#define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source - * @{ - */ -#define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection */ -#define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection */ -#define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection */ -#define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source - * @{ - */ -#define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /*!< I2C1 Clock source selection */ -#define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /*!< I2C2 Clock source selection */ -#define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /*!< I2C3 Clock source selection */ -#if defined(I2C4) -#define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /*!< I2C4 Clock source selection */ -#endif /* I2C4 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source - * @{ - */ -#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source - * @{ - */ -#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */ -#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source - * @{ - */ -#define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selection */ -#if defined(SDMMC2) -#define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selection */ -#endif /* SDMMC2 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source - * @{ - */ -#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source - * @{ - */ -#define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source - * @{ - */ -#define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */ -/** - * @} - */ - -#if defined(CEC) -/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source - * @{ - */ -#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ -/** - * @} - */ -#endif /* CEC */ - -/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source - * @{ - */ -#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ -/** - * @} - */ -#if defined(DFSDM1_Channel0) -/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source - * @{ - */ -#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source - * @{ - */ -#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection */ -/** - * @} - */ -#endif /* DFSDM1_Channel0 */ - -#if defined(DSI) -/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source - * @{ - */ -#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */ -/** - * @} - */ -#endif /* DSI */ - -#if defined(LTDC) -/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source - * @{ - */ -#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection */ -/** - * @} - */ -#endif /* LTDC */ - -#if defined(SPDIFRX) -/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source - * @{ - */ -#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source selection */ -/** - * @} - */ -#endif /* SPDIFRX */ - -/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection - * @{ - */ -#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection - * @{ - */ -#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ -#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /*!< Timers clock to four time PCLK */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source - * @{ - */ -#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor - * @{ - */ -#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ -#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ -#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ -#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ -#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ -#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ -#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ -#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ -#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ -#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ -#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ -#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ -#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ -#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ -#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ -#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ -#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ -#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ -#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ -#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ -#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ -#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ -#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ -#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ -#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ -#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ -#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ -#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ -#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ -#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ -#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ -#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ -#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ -#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ -#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ -#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ -#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ -#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ -#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ -#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ -#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ -#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ -#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ -#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ -#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ -#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ -#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ -#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ -#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ -#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ -#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ -#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ -#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ -#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ -#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ -#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ -#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ -#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ -#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ -#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ -#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ -#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ -/** - * @} - */ - -#if defined(RCC_PLLCFGR_PLLR) -/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) - * @{ - */ -#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ -#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ -#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ -#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ -#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ -#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ -/** - * @} - */ -#endif /* RCC_PLLCFGR_PLLR */ - -/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) - * @{ - */ -#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ -#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ -#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ -#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) - * @{ - */ -#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ -#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ -#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ -#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ -#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ -#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ -#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ -#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ -#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ -#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ -#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ -#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ -#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ -#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection - * @{ - */ -#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ -#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) - * @{ - */ -#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ -#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ -#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ -#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ -#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ -#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ -#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ -#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ -#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ -#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ -#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ -#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ -#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ -#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) - * @{ - */ -#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ -#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ -#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ -#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ -#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ -#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ -#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ -#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ -#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ -#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ -#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ -#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ -#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ -#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ -#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ -#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ -#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ -#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ -#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ -#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ -#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ -#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ -#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ -#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ -#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ -#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ -#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ -#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ -#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ -#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ -#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ -#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) - * @{ - */ -#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ -#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ -#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ -#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ -#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ -#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ -/** - * @} - */ - -#if defined(RCC_PLLI2SCFGR_PLLI2SP) -/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) - * @{ - */ -#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ -#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ -#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ -#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ -/** - * @} - */ -#endif /* RCC_PLLI2SCFGR_PLLI2SP */ - -/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) - * @{ - */ -#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ -#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ -#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ -#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ -#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ -#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ -#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ -#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ -#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ -#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ -#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ -#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ -#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ -#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) - * @{ - */ -#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ -#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ -#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ -#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ -#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ -#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ -#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ -#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ -#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ -#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ -#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ -#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ -#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ -#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ -#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ -#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ -#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ -#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ -#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ -#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ -#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ -#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ -#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ -#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ -#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ -#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ -#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ -#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ -#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ -#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ -#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ -#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ -/** - * @} - */ - -#if defined(RCC_PLLSAICFGR_PLLSAIR) -/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) - * @{ - */ -#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ -#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ -#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ -#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ -#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ -#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ -/** - * @} - */ -#endif /* RCC_PLLSAICFGR_PLLSAIR */ - -#if defined(RCC_DCKCFGR1_PLLSAIDIVR) -/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) - * @{ - */ -#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ -#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ -#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ -#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ -/** - * @} - */ -#endif /* RCC_DCKCFGR1_PLLSAIDIVR */ - -/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) - * @{ - */ -#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ -#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ -#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ -#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RCC register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RCC register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) -/** - * @} - */ - -/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies - * @{ - */ - -/** - * @brief Helper macro to calculate the PLLCLK frequency on system domain - * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50 and 432 - * @param __PLLP__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLP_DIV_2 - * @arg @ref LL_RCC_PLLP_DIV_4 - * @arg @ref LL_RCC_PLLP_DIV_6 - * @arg @ref LL_RCC_PLLP_DIV_8 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) - -/** - * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain - * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50 and 432 - * @param __PLLQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLQ_DIV_2 - * @arg @ref LL_RCC_PLLQ_DIV_3 - * @arg @ref LL_RCC_PLLQ_DIV_4 - * @arg @ref LL_RCC_PLLQ_DIV_5 - * @arg @ref LL_RCC_PLLQ_DIV_6 - * @arg @ref LL_RCC_PLLQ_DIV_7 - * @arg @ref LL_RCC_PLLQ_DIV_8 - * @arg @ref LL_RCC_PLLQ_DIV_9 - * @arg @ref LL_RCC_PLLQ_DIV_10 - * @arg @ref LL_RCC_PLLQ_DIV_11 - * @arg @ref LL_RCC_PLLQ_DIV_12 - * @arg @ref LL_RCC_PLLQ_DIV_13 - * @arg @ref LL_RCC_PLLQ_DIV_14 - * @arg @ref LL_RCC_PLLQ_DIV_15 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) - -#if defined(DSI) -/** - * @brief Helper macro to calculate the PLLCLK frequency used on DSI - * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLN__ Between 50 and 432 - * @param __PLLR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ - ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) -#endif /* DSI */ - -/** - * @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains - * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLSAIN__ Between 50 and 432 - * @param __PLLSAIQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIQ_DIV_15 - * @param __PLLSAIDIVQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 - * @retval PLLSAI clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ - (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U))) - -/** - * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain - * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLSAIN__ Between 50 and 432 - * @param __PLLSAIP__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIP_DIV_2 - * @arg @ref LL_RCC_PLLSAIP_DIV_4 - * @arg @ref LL_RCC_PLLSAIP_DIV_6 - * @arg @ref LL_RCC_PLLSAIP_DIV_8 - * @retval PLLSAI clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ - ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U)) - -#if defined(LTDC) -/** - * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain - * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLSAIN__ Between 50 and 432 - * @param __PLLSAIR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIR_DIV_2 - * @arg @ref LL_RCC_PLLSAIR_DIV_3 - * @arg @ref LL_RCC_PLLSAIR_DIV_4 - * @arg @ref LL_RCC_PLLSAIR_DIV_5 - * @arg @ref LL_RCC_PLLSAIR_DIV_6 - * @arg @ref LL_RCC_PLLSAIR_DIV_7 - * @param __PLLSAIDIVR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 - * @retval PLLSAI clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ - (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos]))) -#endif /* LTDC */ - -/** - * @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains - * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLI2SN__ Between 50 and 432 - * @param __PLLI2SQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SQ_DIV_15 - * @param __PLLI2SDIVQ__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 - * @retval PLLI2S clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ - (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U))) - -#if defined(SPDIFRX) -/** - * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain - * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLI2SN__ Between 50 and 432 - * @param __PLLI2SP__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SP_DIV_2 - * @arg @ref LL_RCC_PLLI2SP_DIV_4 - * @arg @ref LL_RCC_PLLI2SP_DIV_6 - * @arg @ref LL_RCC_PLLI2SP_DIV_8 - * @retval PLLI2S clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ - ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) -#endif /* SPDIFRX */ - -/** - * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain - * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), - * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - * @param __PLLM__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param __PLLI2SN__ Between 50 and 432 - * @param __PLLI2SR__ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SR_DIV_2 - * @arg @ref LL_RCC_PLLI2SR_DIV_3 - * @arg @ref LL_RCC_PLLI2SR_DIV_4 - * @arg @ref LL_RCC_PLLI2SR_DIV_5 - * @arg @ref LL_RCC_PLLI2SR_DIV_6 - * @arg @ref LL_RCC_PLLI2SR_DIV_7 - * @retval PLLI2S clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ - ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) - -/** - * @brief Helper macro to calculate the HCLK frequency - * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) - * @param __AHBPRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval HCLK clock frequency (in Hz) - */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) - -/** - * @brief Helper macro to calculate the PCLK1 frequency (ABP1) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval PCLK1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) - -/** - * @brief Helper macro to calculate the PCLK2 frequency (ABP2) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB2PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - * @retval PCLK2 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_LL_EF_HSE HSE - * @{ - */ - -/** - * @brief Enable the Clock Security System. - * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Enable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Disable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Check if HSE oscillator Ready - * @rmtoll CR HSERDY LL_RCC_HSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_HSI HSI - * @{ - */ - -/** - * @brief Enable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Disable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Check if HSI clock is ready - * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); -} - -/** - * @brief Get HSI Calibration value - * @note When HSITRIM is written, HSICAL is updated with the sum of - * HSITRIM and the factory trim value - * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); -} - -/** - * @brief Set HSI Calibration trimming - * @note user-programmable trimming value that is added to the HSICAL - * @note Default value is 16, which, when added to the HSICAL value, - * should trim the HSI to 16 MHz +/- 1 % - * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming - * @param Value Between Min_Data = 0 and Max_Data = 31 - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); -} - -/** - * @brief Get HSI Calibration trimming - * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming - * @retval Between Min_Data = 0 and Max_Data = 31 - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSE LSE - * @{ - */ - -/** - * @brief Enable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Disable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Enable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Disable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Set LSE oscillator drive capability - * @note The oscillator is in Xtal mode when it is not in bypass mode. - * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability - * @param LSEDrive This parameter can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW - * @arg @ref LL_RCC_LSEDRIVE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); -} - -/** - * @brief Get LSE oscillator drive capability - * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW - * @arg @ref LL_RCC_LSEDRIVE_HIGH - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); -} - -/** - * @brief Check if LSE oscillator Ready - * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSI LSI - * @{ - */ - -/** - * @brief Enable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Enable(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Disable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Disable(void) -{ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Check if LSI is Ready - * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_System System - * @{ - */ - -/** - * @brief Configure the system clock source - * @rmtoll CFGR SW LL_RCC_SetSysClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); -} - -/** - * @brief Get the system clock source - * @rmtoll CFGR SWS LL_RCC_GetSysClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL - */ -__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); -} - -/** - * @brief Set AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); -} - -/** - * @brief Set APB1 prescaler - * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); -} - -/** - * @brief Set APB2 prescaler - * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); -} - -/** - * @brief Get AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); -} - -/** - * @brief Get APB1 prescaler - * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); -} - -/** - * @brief Get APB2 prescaler - * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MCO MCO - * @{ - */ - -/** - * @brief Configure MCOx - * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n - * CFGR MCO1PRE LL_RCC_ConfigMCO\n - * CFGR MCO2 LL_RCC_ConfigMCO\n - * CFGR MCO2PRE LL_RCC_ConfigMCO - * @param MCOxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1SOURCE_HSI - * @arg @ref LL_RCC_MCO1SOURCE_LSE - * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK - * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK - * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S - * @arg @ref LL_RCC_MCO2SOURCE_HSE - * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK - * @param MCOxPrescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_DIV_1 - * @arg @ref LL_RCC_MCO1_DIV_2 - * @arg @ref LL_RCC_MCO1_DIV_3 - * @arg @ref LL_RCC_MCO1_DIV_4 - * @arg @ref LL_RCC_MCO1_DIV_5 - * @arg @ref LL_RCC_MCO2_DIV_1 - * @arg @ref LL_RCC_MCO2_DIV_2 - * @arg @ref LL_RCC_MCO2_DIV_3 - * @arg @ref LL_RCC_MCO2_DIV_4 - * @arg @ref LL_RCC_MCO2_DIV_5 - * @retval None - */ -__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) -{ - MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source - * @{ - */ - -/** - * @brief Configure USARTx clock source - * @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n - * DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n - * DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n - * DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource - * @param USARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); -} - -/** - * @brief Configure UARTx clock source - * @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n - * DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n - * DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n - * DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource - * @param UARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE - * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE - * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE - * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); -} - -/** - * @brief Configure I2Cx clock source - * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n - * DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n - * DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n - * DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource - * @param I2CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U)); -} - -/** - * @brief Configure LPTIMx clock source - * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource - * @param LPTIMxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); -} - -/** - * @brief Configure SAIx clock source - * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n - * DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource - * @param SAIxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) -{ - MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); -} - -/** - * @brief Configure SDMMC clock source - * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n - * DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource - * @param SDMMCxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) - * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U)); -} - -/** - * @brief Configure 48Mhz domain clock source - * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource - * @param CK48MxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); -} - -/** - * @brief Configure RNG clock source - * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource - * @param RNGxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); -} - -/** - * @brief Configure USB clock source - * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); -} - -#if defined(CEC) -/** - * @brief Configure CEC clock source - * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE - * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); -} -#endif /* CEC */ - -/** - * @brief Configure I2S clock source - * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); -} - -#if defined(DSI) -/** - * @brief Configure DSI clock source - * @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY - * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source); -} -#endif /* DSI */ - -#if defined(DFSDM1_Channel0) -/** - * @brief Configure DFSDM Audio clock source - * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source); -} - -/** - * @brief Configure DFSDM Kernel clock source - * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source); -} -#endif /* DFSDM1_Channel0 */ - -/** - * @brief Get USARTx clock source - * @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n - * DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n - * DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n - * DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource - * @param USARTx This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE - * @arg @ref LL_RCC_USART2_CLKSOURCE - * @arg @ref LL_RCC_USART3_CLKSOURCE - * @arg @ref LL_RCC_USART6_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U)); -} - -/** - * @brief Get UARTx clock source - * @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n - * DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n - * DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n - * DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource - * @param UARTx This parameter can be one of the following values: - * @arg @ref LL_RCC_UART4_CLKSOURCE - * @arg @ref LL_RCC_UART5_CLKSOURCE - * @arg @ref LL_RCC_UART7_CLKSOURCE - * @arg @ref LL_RCC_UART8_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE - * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE - * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE - * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U)); -} - -/** - * @brief Get I2Cx clock source - * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n - * DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n - * DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n - * DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource - * @param I2Cx This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE - * @arg @ref LL_RCC_I2C2_CLKSOURCE - * @arg @ref LL_RCC_I2C3_CLKSOURCE - * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) -{ - return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx); -} - -/** - * @brief Get LPTIMx clock source - * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource - * @param LPTIMx This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); -} - -/** - * @brief Get SAIx clock source - * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n - * DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource - * @param SAIx This parameter can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE - * @arg @ref LL_RCC_SAI2_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx); -} - -/** - * @brief Get SDMMCx clock source - * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n - * DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource - * @param SDMMCx This parameter can be one of the following values: - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*) - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) - * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx); -} - -/** - * @brief Get 48Mhz domain clock source - * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource - * @param CK48Mx This parameter can be one of the following values: - * @arg @ref LL_RCC_CK48M_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL - * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI - */ -__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); -} - -/** - * @brief Get RNGx clock source - * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource - * @param RNGx This parameter can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL - * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI - */ -__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); -} - -/** - * @brief Get USBx clock source - * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource - * @param USBx This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL - * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); -} - -#if defined(CEC) -/** - * @brief Get CEC Clock Source - * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource - * @param CECx This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE - * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 - */ -__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); -} -#endif /* CEC */ - -/** - * @brief Get I2S Clock Source - * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource - * @param I2Sx This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S - * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN - */ -__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); -} - -#if defined(DFSDM1_Channel0) -/** - * @brief Get DFSDM Audio Clock Source - * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource - * @param DFSDMx This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 - */ -__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); -} - -/** - * @brief Get DFSDM Audio Clock Source - * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource - * @param DFSDMx This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK - */ -__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); -} -#endif /* DFSDM1_Channel0 */ - -#if defined(DSI) -/** - * @brief Get DSI Clock Source - * @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource - * @param DSIx This parameter can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY - * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL - */ -__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx)); -} -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_RTC RTC - * @{ - */ - -/** - * @brief Set RTC Clock Source - * @note Once the RTC clock source has been selected, it cannot be changed anymore unless - * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is - * set). The BDRST bit can be used to reset them. - * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); -} - -/** - * @brief Get RTC Clock Source - * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); -} - -/** - * @brief Enable RTC - * @rmtoll BDCR RTCEN LL_RCC_EnableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableRTC(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Disable RTC - * @rmtoll BDCR RTCEN LL_RCC_DisableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableRTC(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Check if RTC has been enabled or not - * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); -} - -/** - * @brief Force the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Release the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Set HSE Prescalers for RTC Clock - * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_NOCLOCK - * @arg @ref LL_RCC_RTC_HSE_DIV_2 - * @arg @ref LL_RCC_RTC_HSE_DIV_3 - * @arg @ref LL_RCC_RTC_HSE_DIV_4 - * @arg @ref LL_RCC_RTC_HSE_DIV_5 - * @arg @ref LL_RCC_RTC_HSE_DIV_6 - * @arg @ref LL_RCC_RTC_HSE_DIV_7 - * @arg @ref LL_RCC_RTC_HSE_DIV_8 - * @arg @ref LL_RCC_RTC_HSE_DIV_9 - * @arg @ref LL_RCC_RTC_HSE_DIV_10 - * @arg @ref LL_RCC_RTC_HSE_DIV_11 - * @arg @ref LL_RCC_RTC_HSE_DIV_12 - * @arg @ref LL_RCC_RTC_HSE_DIV_13 - * @arg @ref LL_RCC_RTC_HSE_DIV_14 - * @arg @ref LL_RCC_RTC_HSE_DIV_15 - * @arg @ref LL_RCC_RTC_HSE_DIV_16 - * @arg @ref LL_RCC_RTC_HSE_DIV_17 - * @arg @ref LL_RCC_RTC_HSE_DIV_18 - * @arg @ref LL_RCC_RTC_HSE_DIV_19 - * @arg @ref LL_RCC_RTC_HSE_DIV_20 - * @arg @ref LL_RCC_RTC_HSE_DIV_21 - * @arg @ref LL_RCC_RTC_HSE_DIV_22 - * @arg @ref LL_RCC_RTC_HSE_DIV_23 - * @arg @ref LL_RCC_RTC_HSE_DIV_24 - * @arg @ref LL_RCC_RTC_HSE_DIV_25 - * @arg @ref LL_RCC_RTC_HSE_DIV_26 - * @arg @ref LL_RCC_RTC_HSE_DIV_27 - * @arg @ref LL_RCC_RTC_HSE_DIV_28 - * @arg @ref LL_RCC_RTC_HSE_DIV_29 - * @arg @ref LL_RCC_RTC_HSE_DIV_30 - * @arg @ref LL_RCC_RTC_HSE_DIV_31 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); -} - -/** - * @brief Get HSE Prescalers for RTC Clock - * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_NOCLOCK - * @arg @ref LL_RCC_RTC_HSE_DIV_2 - * @arg @ref LL_RCC_RTC_HSE_DIV_3 - * @arg @ref LL_RCC_RTC_HSE_DIV_4 - * @arg @ref LL_RCC_RTC_HSE_DIV_5 - * @arg @ref LL_RCC_RTC_HSE_DIV_6 - * @arg @ref LL_RCC_RTC_HSE_DIV_7 - * @arg @ref LL_RCC_RTC_HSE_DIV_8 - * @arg @ref LL_RCC_RTC_HSE_DIV_9 - * @arg @ref LL_RCC_RTC_HSE_DIV_10 - * @arg @ref LL_RCC_RTC_HSE_DIV_11 - * @arg @ref LL_RCC_RTC_HSE_DIV_12 - * @arg @ref LL_RCC_RTC_HSE_DIV_13 - * @arg @ref LL_RCC_RTC_HSE_DIV_14 - * @arg @ref LL_RCC_RTC_HSE_DIV_15 - * @arg @ref LL_RCC_RTC_HSE_DIV_16 - * @arg @ref LL_RCC_RTC_HSE_DIV_17 - * @arg @ref LL_RCC_RTC_HSE_DIV_18 - * @arg @ref LL_RCC_RTC_HSE_DIV_19 - * @arg @ref LL_RCC_RTC_HSE_DIV_20 - * @arg @ref LL_RCC_RTC_HSE_DIV_21 - * @arg @ref LL_RCC_RTC_HSE_DIV_22 - * @arg @ref LL_RCC_RTC_HSE_DIV_23 - * @arg @ref LL_RCC_RTC_HSE_DIV_24 - * @arg @ref LL_RCC_RTC_HSE_DIV_25 - * @arg @ref LL_RCC_RTC_HSE_DIV_26 - * @arg @ref LL_RCC_RTC_HSE_DIV_27 - * @arg @ref LL_RCC_RTC_HSE_DIV_28 - * @arg @ref LL_RCC_RTC_HSE_DIV_29 - * @arg @ref LL_RCC_RTC_HSE_DIV_30 - * @arg @ref LL_RCC_RTC_HSE_DIV_31 - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM - * @{ - */ - -/** - * @brief Set Timers Clock Prescalers - * @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_TIM_PRESCALER_TWICE - * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler); -} - -/** - * @brief Get Timers Clock Prescalers - * @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_TIM_PRESCALER_TWICE - * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES - */ -__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PLL PLL - * @{ - */ - -/** - * @brief Enable PLL - * @rmtoll CR PLLON LL_RCC_PLL_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Disable PLL - * @note Cannot be disabled if the PLL clock is used as the system clock - * @rmtoll CR PLLON LL_RCC_PLL_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Check if PLL Ready - * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); -} - -/** - * @brief Configure PLL used for SYSCLK Domain - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLP can be written only when PLL is disabled - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n - * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLP This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLP_DIV_2 - * @arg @ref LL_RCC_PLLP_DIV_4 - * @arg @ref LL_RCC_PLLP_DIV_6 - * @arg @ref LL_RCC_PLLP_DIV_8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); -} - -/** - * @brief Configure PLL used for 48Mhz domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLQ can be written only when PLL is disabled - * @note This can be selected for USB, RNG, SDMMC1 - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n - * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLQ_DIV_2 - * @arg @ref LL_RCC_PLLQ_DIV_3 - * @arg @ref LL_RCC_PLLQ_DIV_4 - * @arg @ref LL_RCC_PLLQ_DIV_5 - * @arg @ref LL_RCC_PLLQ_DIV_6 - * @arg @ref LL_RCC_PLLQ_DIV_7 - * @arg @ref LL_RCC_PLLQ_DIV_8 - * @arg @ref LL_RCC_PLLQ_DIV_9 - * @arg @ref LL_RCC_PLLQ_DIV_10 - * @arg @ref LL_RCC_PLLQ_DIV_11 - * @arg @ref LL_RCC_PLLQ_DIV_12 - * @arg @ref LL_RCC_PLLQ_DIV_13 - * @arg @ref LL_RCC_PLLQ_DIV_14 - * @arg @ref LL_RCC_PLLQ_DIV_15 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); -} - -#if defined(DSI) -/** - * @brief Configure PLL used for DSI clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLR can be written only when PLL is disabled - * @note This can be selected for DSI - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n - * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n - * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n - * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, - Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); -} -#endif /* DSI */ - -/** - * @brief Configure PLL clock source - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource - * @param PLLSource This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); -} - -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} - -/** - * @brief Get Main PLL multiplication factor for VCO - * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN - * @retval Between 50 and 432 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); -} - -/** - * @brief Get Main PLL division factor for PLLP - * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLP_DIV_2 - * @arg @ref LL_RCC_PLLP_DIV_4 - * @arg @ref LL_RCC_PLLP_DIV_6 - * @arg @ref LL_RCC_PLLP_DIV_8 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); -} - -/** - * @brief Get Main PLL division factor for PLLQ - * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock) - * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLQ_DIV_2 - * @arg @ref LL_RCC_PLLQ_DIV_3 - * @arg @ref LL_RCC_PLLQ_DIV_4 - * @arg @ref LL_RCC_PLLQ_DIV_5 - * @arg @ref LL_RCC_PLLQ_DIV_6 - * @arg @ref LL_RCC_PLLQ_DIV_7 - * @arg @ref LL_RCC_PLLQ_DIV_8 - * @arg @ref LL_RCC_PLLQ_DIV_9 - * @arg @ref LL_RCC_PLLQ_DIV_10 - * @arg @ref LL_RCC_PLLQ_DIV_11 - * @arg @ref LL_RCC_PLLQ_DIV_12 - * @arg @ref LL_RCC_PLLQ_DIV_13 - * @arg @ref LL_RCC_PLLQ_DIV_14 - * @arg @ref LL_RCC_PLLQ_DIV_15 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); -} - -#if defined(RCC_PLLCFGR_PLLR) -/** - * @brief Get Main PLL division factor for PLLR - * @note used for PLLCLK (system clock) - * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLR_DIV_2 - * @arg @ref LL_RCC_PLLR_DIV_3 - * @arg @ref LL_RCC_PLLR_DIV_4 - * @arg @ref LL_RCC_PLLR_DIV_5 - * @arg @ref LL_RCC_PLLR_DIV_6 - * @arg @ref LL_RCC_PLLR_DIV_7 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); -} -#endif /* RCC_PLLCFGR_PLLR */ - -/** - * @brief Get Division factor for the main PLL and other PLL - * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); -} - -/** - * @brief Configure Spread Spectrum used for PLL - * @note These bits must be written before enabling PLL - * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n - * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n - * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum - * @param Mod Between Min_Data=0 and Max_Data=8191 - * @param Inc Between Min_Data=0 and Max_Data=32767 - * @param Sel This parameter can be one of the following values: - * @arg @ref LL_RCC_SPREAD_SELECT_CENTER - * @arg @ref LL_RCC_SPREAD_SELECT_DOWN - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) -{ - MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); -} - -/** - * @brief Get Spread Spectrum Modulation Period for PLL - * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation - * @retval Between Min_Data=0 and Max_Data=8191 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) -{ - return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); -} - -/** - * @brief Get Spread Spectrum Incrementation Step for PLL - * @note Must be written before enabling PLL - * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation - * @retval Between Min_Data=0 and Max_Data=32767 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) -{ - return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); -} - -/** - * @brief Get Spread Spectrum Selection for PLL - * @note Must be written before enabling PLL - * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SPREAD_SELECT_CENTER - * @arg @ref LL_RCC_SPREAD_SELECT_DOWN - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) -{ - return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); -} - -/** - * @brief Enable Spread Spectrum for PLL. - * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) -{ - SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); -} - -/** - * @brief Disable Spread Spectrum for PLL. - * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) -{ - CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PLLI2S PLLI2S - * @{ - */ - -/** - * @brief Enable PLLI2S - * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLI2SON); -} - -/** - * @brief Disable PLLI2S - * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); -} - -/** - * @brief Check if PLLI2S Ready - * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); -} - -/** - * @brief Configure PLLI2S used for SAI1 and SAI2 domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLQ can be written only when PLLI2S is disabled - * @note This can be selected for SAI1 and SAI2 - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n - * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n - * DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SQ_DIV_15 - * @param PLLDIVQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ); -} - -#if defined(SPDIFRX) -/** - * @brief Configure PLLI2S used for SPDIFRX domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLP can be written only when PLLI2S is disabled - * @note This can be selected for SPDIFRX - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n - * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n - * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n - * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLP This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SP_DIV_2 - * @arg @ref LL_RCC_PLLI2SP_DIV_4 - * @arg @ref LL_RCC_PLLI2SP_DIV_6 - * @arg @ref LL_RCC_PLLI2SP_DIV_8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); -} -#endif /* SPDIFRX */ - -/** - * @brief Configure PLLI2S used for I2S1 domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLR can be written only when PLLI2S is disabled - * @note This can be selected for I2S - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n - * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n - * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n - * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLI2SR_DIV_2 - * @arg @ref LL_RCC_PLLI2SR_DIV_3 - * @arg @ref LL_RCC_PLLI2SR_DIV_4 - * @arg @ref LL_RCC_PLLI2SR_DIV_5 - * @arg @ref LL_RCC_PLLI2SR_DIV_6 - * @arg @ref LL_RCC_PLLI2SR_DIV_7 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); - MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); -} - -/** - * @brief Get I2SPLL multiplication factor for VCO - * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN - * @retval Between 50 and 432 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); -} - -/** - * @brief Get I2SPLL division factor for PLLI2SQ - * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SQ_DIV_15 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); -} - -/** - * @brief Get I2SPLL division factor for PLLI2SR - * @note used for PLLI2SCLK (I2S clock) - * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SR_DIV_2 - * @arg @ref LL_RCC_PLLI2SR_DIV_3 - * @arg @ref LL_RCC_PLLI2SR_DIV_4 - * @arg @ref LL_RCC_PLLI2SR_DIV_5 - * @arg @ref LL_RCC_PLLI2SR_DIV_6 - * @arg @ref LL_RCC_PLLI2SR_DIV_7 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); -} - -#if defined(RCC_PLLI2SCFGR_PLLI2SP) -/** - * @brief Get I2SPLL division factor for PLLI2SP - * @note used for PLLSPDIFRXCLK (SPDIFRX clock) - * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SP_DIV_2 - * @arg @ref LL_RCC_PLLI2SP_DIV_4 - * @arg @ref LL_RCC_PLLI2SP_DIV_6 - * @arg @ref LL_RCC_PLLI2SP_DIV_8 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); -} -#endif /* RCC_PLLI2SCFGR_PLLI2SP */ - -/** - * @brief Get I2SPLL division factor for PLLI2SDIVQ - * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) - * @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PLLSAI PLLSAI - * @{ - */ - -/** - * @brief Enable PLLSAI - * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLSAION); -} - -/** - * @brief Disable PLLSAI - * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); -} - -/** - * @brief Check if PLLSAI Ready - * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) -{ - return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); -} - -/** - * @brief Configure PLLSAI used for SAI1 and SAI2 domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLQ can be written only when PLLSAI is disabled - * @note This can be selected for SAI1 and SAI2 - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n - * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n - * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n - * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n - * DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIQ_DIV_15 - * @param PLLDIVQ This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); - MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ); -} - -/** - * @brief Configure PLLSAI used for 48Mhz domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLP can be written only when PLLSAI is disabled - * @note This can be selected for USB, RNG, SDMMC1 - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n - * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n - * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n - * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLP This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIP_DIV_2 - * @arg @ref LL_RCC_PLLSAIP_DIV_4 - * @arg @ref LL_RCC_PLLSAIP_DIV_6 - * @arg @ref LL_RCC_PLLSAIP_DIV_8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); - MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); -} - -#if defined(LTDC) -/** - * @brief Configure PLLSAI used for LTDC domain clock - * @note PLL Source and PLLM Divider can be written only when PLL, - * PLLI2S and PLLSAI are disabled - * @note PLLN/PLLR can be written only when PLLSAI is disabled - * @note This can be selected for LTDC - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n - * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n - * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n - * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n - * DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @param PLLM This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLM_DIV_2 - * @arg @ref LL_RCC_PLLM_DIV_3 - * @arg @ref LL_RCC_PLLM_DIV_4 - * @arg @ref LL_RCC_PLLM_DIV_5 - * @arg @ref LL_RCC_PLLM_DIV_6 - * @arg @ref LL_RCC_PLLM_DIV_7 - * @arg @ref LL_RCC_PLLM_DIV_8 - * @arg @ref LL_RCC_PLLM_DIV_9 - * @arg @ref LL_RCC_PLLM_DIV_10 - * @arg @ref LL_RCC_PLLM_DIV_11 - * @arg @ref LL_RCC_PLLM_DIV_12 - * @arg @ref LL_RCC_PLLM_DIV_13 - * @arg @ref LL_RCC_PLLM_DIV_14 - * @arg @ref LL_RCC_PLLM_DIV_15 - * @arg @ref LL_RCC_PLLM_DIV_16 - * @arg @ref LL_RCC_PLLM_DIV_17 - * @arg @ref LL_RCC_PLLM_DIV_18 - * @arg @ref LL_RCC_PLLM_DIV_19 - * @arg @ref LL_RCC_PLLM_DIV_20 - * @arg @ref LL_RCC_PLLM_DIV_21 - * @arg @ref LL_RCC_PLLM_DIV_22 - * @arg @ref LL_RCC_PLLM_DIV_23 - * @arg @ref LL_RCC_PLLM_DIV_24 - * @arg @ref LL_RCC_PLLM_DIV_25 - * @arg @ref LL_RCC_PLLM_DIV_26 - * @arg @ref LL_RCC_PLLM_DIV_27 - * @arg @ref LL_RCC_PLLM_DIV_28 - * @arg @ref LL_RCC_PLLM_DIV_29 - * @arg @ref LL_RCC_PLLM_DIV_30 - * @arg @ref LL_RCC_PLLM_DIV_31 - * @arg @ref LL_RCC_PLLM_DIV_32 - * @arg @ref LL_RCC_PLLM_DIV_33 - * @arg @ref LL_RCC_PLLM_DIV_34 - * @arg @ref LL_RCC_PLLM_DIV_35 - * @arg @ref LL_RCC_PLLM_DIV_36 - * @arg @ref LL_RCC_PLLM_DIV_37 - * @arg @ref LL_RCC_PLLM_DIV_38 - * @arg @ref LL_RCC_PLLM_DIV_39 - * @arg @ref LL_RCC_PLLM_DIV_40 - * @arg @ref LL_RCC_PLLM_DIV_41 - * @arg @ref LL_RCC_PLLM_DIV_42 - * @arg @ref LL_RCC_PLLM_DIV_43 - * @arg @ref LL_RCC_PLLM_DIV_44 - * @arg @ref LL_RCC_PLLM_DIV_45 - * @arg @ref LL_RCC_PLLM_DIV_46 - * @arg @ref LL_RCC_PLLM_DIV_47 - * @arg @ref LL_RCC_PLLM_DIV_48 - * @arg @ref LL_RCC_PLLM_DIV_49 - * @arg @ref LL_RCC_PLLM_DIV_50 - * @arg @ref LL_RCC_PLLM_DIV_51 - * @arg @ref LL_RCC_PLLM_DIV_52 - * @arg @ref LL_RCC_PLLM_DIV_53 - * @arg @ref LL_RCC_PLLM_DIV_54 - * @arg @ref LL_RCC_PLLM_DIV_55 - * @arg @ref LL_RCC_PLLM_DIV_56 - * @arg @ref LL_RCC_PLLM_DIV_57 - * @arg @ref LL_RCC_PLLM_DIV_58 - * @arg @ref LL_RCC_PLLM_DIV_59 - * @arg @ref LL_RCC_PLLM_DIV_60 - * @arg @ref LL_RCC_PLLM_DIV_61 - * @arg @ref LL_RCC_PLLM_DIV_62 - * @arg @ref LL_RCC_PLLM_DIV_63 - * @param PLLN Between 50 and 432 - * @param PLLR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIR_DIV_2 - * @arg @ref LL_RCC_PLLSAIR_DIV_3 - * @arg @ref LL_RCC_PLLSAIR_DIV_4 - * @arg @ref LL_RCC_PLLSAIR_DIV_5 - * @arg @ref LL_RCC_PLLSAIR_DIV_6 - * @arg @ref LL_RCC_PLLSAIR_DIV_7 - * @param PLLDIVR This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); - MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); - MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR); -} -#endif /* LTDC */ - -/** - * @brief Get SAIPLL multiplication factor for VCO - * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN - * @retval Between 50 and 432 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); -} - -/** - * @brief Get SAIPLL division factor for PLLSAIQ - * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIQ_DIV_15 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); -} - -#if defined(RCC_PLLSAICFGR_PLLSAIR) -/** - * @brief Get SAIPLL division factor for PLLSAIR - * @note used for PLLSAICLK (SAI clock) - * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIR_DIV_2 - * @arg @ref LL_RCC_PLLSAIR_DIV_3 - * @arg @ref LL_RCC_PLLSAIR_DIV_4 - * @arg @ref LL_RCC_PLLSAIR_DIV_5 - * @arg @ref LL_RCC_PLLSAIR_DIV_6 - * @arg @ref LL_RCC_PLLSAIR_DIV_7 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); -} -#endif /* RCC_PLLSAICFGR_PLLSAIR */ - -/** - * @brief Get SAIPLL division factor for PLLSAIP - * @note used for PLL48MCLK (48M domain clock) - * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIP_DIV_2 - * @arg @ref LL_RCC_PLLSAIP_DIV_4 - * @arg @ref LL_RCC_PLLSAIP_DIV_6 - * @arg @ref LL_RCC_PLLSAIP_DIV_8 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); -} - -/** - * @brief Get SAIPLL division factor for PLLSAIDIVQ - * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) - * @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 - * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ)); -} - -#if defined(RCC_DCKCFGR1_PLLSAIDIVR) -/** - * @brief Get SAIPLL division factor for PLLSAIDIVR - * @note used for LTDC domain clock - * @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 - * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) -{ - return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR)); -} -#endif /* RCC_DCKCFGR1_PLLSAIDIVR */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Clear LSI ready interrupt flag - * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); -} - -/** - * @brief Clear LSE ready interrupt flag - * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); -} - -/** - * @brief Clear HSI ready interrupt flag - * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); -} - -/** - * @brief Clear HSE ready interrupt flag - * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); -} - -/** - * @brief Clear PLL ready interrupt flag - * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); -} - -/** - * @brief Clear PLLI2S ready interrupt flag - * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); -} - -/** - * @brief Clear PLLSAI ready interrupt flag - * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); -} - -/** - * @brief Clear Clock security system interrupt flag - * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_CSSC); -} - -/** - * @brief Check if LSI ready interrupt occurred or not - * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); -} - -/** - * @brief Check if LSE ready interrupt occurred or not - * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); -} - -/** - * @brief Check if HSI ready interrupt occurred or not - * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); -} - -/** - * @brief Check if HSE ready interrupt occurred or not - * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); -} - -/** - * @brief Check if PLL ready interrupt occurred or not - * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); -} - -/** - * @brief Check if PLLI2S ready interrupt occurred or not - * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); -} - -/** - * @brief Check if PLLSAI ready interrupt occurred or not - * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); -} - -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); -} - -/** - * @brief Check if RCC flag Independent Watchdog reset is set or not. - * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); -} - -/** - * @brief Check if RCC flag Low Power reset is set or not. - * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); -} - -/** - * @brief Check if RCC flag Pin reset is set or not. - * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); -} - -/** - * @brief Check if RCC flag POR/PDR reset is set or not. - * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); -} - -/** - * @brief Check if RCC flag Software reset is set or not. - * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); -} - -/** - * @brief Check if RCC flag Window Watchdog reset is set or not. - * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); -} - -/** - * @brief Check if RCC flag BOR reset is set or not. - * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) -{ - return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); -} - -/** - * @brief Set RMVF bit to clear the reset flags. - * @rmtoll CSR RMVF LL_RCC_ClearResetFlags - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearResetFlags(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_IT_Management IT Management - * @{ - */ - -/** - * @brief Enable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Enable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Enable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Enable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Enable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -/** - * @brief Enable PLLI2S ready interrupt - * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); -} - -/** - * @brief Enable PLLSAI ready interrupt - * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) -{ - SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); -} - -/** - * @brief Disable LSI ready interrupt - * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); -} - -/** - * @brief Disable LSE ready interrupt - * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); -} - -/** - * @brief Disable HSI ready interrupt - * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); -} - -/** - * @brief Disable HSE ready interrupt - * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); -} - -/** - * @brief Disable PLL ready interrupt - * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); -} - -/** - * @brief Disable PLLI2S ready interrupt - * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); -} - -/** - * @brief Disable PLLSAI ready interrupt - * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) -{ - CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); -} - -/** - * @brief Checks if LSI ready interrupt source is enabled or disabled. - * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); -} - -/** - * @brief Checks if LSE ready interrupt source is enabled or disabled. - * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); -} - -/** - * @brief Checks if HSI ready interrupt source is enabled or disabled. - * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); -} - -/** - * @brief Checks if HSE ready interrupt source is enabled or disabled. - * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); -} - -/** - * @brief Checks if PLL ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); -} - -/** - * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); -} - -/** - * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. - * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) -{ - return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_RCC_DeInit(void); -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions - * @{ - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); -uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); -uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); -uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); -uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); -uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); -uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); -uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); -#if defined(DFSDM1_Channel0) -uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); -uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); -#endif /* DFSDM1_Channel0 */ -uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); -#if defined(CEC) -uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); -#endif /* CEC */ -#if defined(LTDC) -uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); -#endif /* LTDC */ -#if defined(SPDIFRX) -uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); -#endif /* SPDIFRX */ -#if defined(DSI) -uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); -#endif /* DSI */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_RCC_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_rcc.h + * @author MCD Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_RCC_H +#define __STM32F7xx_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + +#if defined(LTDC) +static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; +#endif /* LTDC */ + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ + uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ + +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ +#endif /* EXTERNAL_CLOCK_VALUE */ + +#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) +#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ + +#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) +#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ +#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ +#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ +#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ +#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ +#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ +#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ +#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ +#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ +/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) + * @{ + */ +#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ +#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ +#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ +#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ +#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ +#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ +#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ +#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ +#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ +#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ +#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ +#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ +#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock + * @{ + */ +#define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ +#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ +#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ +#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ +#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ +#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ +#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ +#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ +#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ +#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ +#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ +#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ +#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ +#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ +#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ +#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ +#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ +#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ +#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ +#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ +#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ +#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ +#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ +#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ +#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ +#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ +#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ +#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ +#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ +#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ +#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_1) /*!< HSI clock used as USART1 clock source */ +#define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL) /*!< LSE clock used as USART1 clock source */ +#define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_1) /*!< HSI clock used as USART2 clock source */ +#define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL) /*!< LSE clock used as USART2 clock source */ +#define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_1) /*!< HSI clock used as USART3 clock source */ +#define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL) /*!< LSE clock used as USART3 clock source */ +#define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_0) /*!< SYSCLK clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_1) /*!< HSI clock used as USART6 clock source */ +#define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL) /*!< LSE clock used as USART6 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ +#define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL) /*!< LSE clock used as UART4 clock source */ +#define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ +#define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL) /*!< LSE clock used as UART5 clock source */ +#define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_0) /*!< SYSCLK clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_1) /*!< HSI clock used as UART7 clock source */ +#define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL) /*!< LSE clock used as UART7 clock source */ +#define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_0) /*!< SYSCLK clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_1) /*!< HSI clock used as UART8 clock source */ +#define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL) /*!< LSE clock used as UART8 clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C1 clock source */ +#define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /*!< HSI clock used as I2C1 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C2 clock source */ +#define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /*!< HSI clock used as I2C2 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C3 clock source */ +#define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /*!< HSI clock used as I2C3 clock source */ +#if defined(I2C4) +#define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C4 clock source */ +#define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /*!< HSI clock used as I2C4 clock source */ +#endif /* I2C4 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI1 clock source */ +#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_1 >> 16U)) /*!< External pin clock used as SAI1 clock source */ +#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) +#define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL >> 16U)) /*!< Main source clock used as SAI1 clock source */ +#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ +#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI2 clock source */ +#define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_1 >> 16U)) /*!< External pin clock used as SAI2 clock source */ +#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) +#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL >> 16U)) /*!< Main source clock used as SAI2 clock source */ +#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC1 clock */ +#define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SDMMC1SEL >> 16U)) /*!< System clock clock used as SDMMC1 clock */ +#if defined(SDMMC2) +#define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC2 clock */ +#define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SDMMC2SEL >> 16U)) /*!< System clock clock used as SDMMC2 clock */ +#endif /* SDMMC2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as RNG clock source */ +#define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI clock used as RNG clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection + * @{ + */ +#define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as USB clock source */ +#define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI1 clock used as USB clock source */ +/** + * @} + */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ +#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE oscillator clock used as CEC clock */ +#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /*!< HSI oscillator clock divided by 488 used as CEC clock */ +/** + * @} + */ +#endif /* CEC */ + +/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection + * @{ + */ +#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ +#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection + * @{ + */ +#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ +#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ +/** + * @} + */ + +#if defined(DFSDM1_Channel0) +/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /*!< SAI2 clock used as DFSDM1 Audio clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection + * @{ + */ +#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ +#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /*!< System clock used as DFSDM1 clock */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 */ + +/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source + * @{ + */ +#define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selection */ +#define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selection */ +#define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selection */ +#define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source + * @{ + */ +#define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection */ +#define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection */ +#define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection */ +#define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source + * @{ + */ +#define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /*!< I2C1 Clock source selection */ +#define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /*!< I2C2 Clock source selection */ +#define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /*!< I2C3 Clock source selection */ +#if defined(I2C4) +#define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /*!< I2C4 Clock source selection */ +#endif /* I2C4 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source + * @{ + */ +#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */ +#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source + * @{ + */ +#define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selection */ +#if defined(SDMMC2) +#define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selection */ +#endif /* SDMMC2 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source + * @{ + */ +#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source + * @{ + */ +#define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source + * @{ + */ +#define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */ +/** + * @} + */ + +#if defined(CEC) +/** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source + * @{ + */ +#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ +/** + * @} + */ +#endif /* CEC */ + +/** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source + * @{ + */ +#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */ +/** + * @} + */ +#if defined(DFSDM1_Channel0) +/** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source + * @{ + */ +#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source + * @{ + */ +#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection */ +/** + * @} + */ +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source + * @{ + */ +#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */ +/** + * @} + */ +#endif /* DSI */ + +#if defined(LTDC) +/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source + * @{ + */ +#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection */ +/** + * @} + */ +#endif /* LTDC */ + +#if defined(SPDIFRX) +/** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source + * @{ + */ +#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source selection */ +/** + * @} + */ +#endif /* SPDIFRX */ + +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection + * @{ + */ +#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ +#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /*!< Timers clock to four time PCLK */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor + * @{ + */ +#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ +#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ +#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ +#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ +#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ +#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ +#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ +#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ +#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ +#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ +#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ +#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ +#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ +#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ +#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ +#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ +#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ +#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ +#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ +#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ +#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ +#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ +#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ +#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ +#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ +#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ +#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ +#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ +#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ +#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ +#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ +#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ +#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ +#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ +#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ +#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ +#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ +#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ +#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ +#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ +#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ +#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ +#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ +#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ +#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ +#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ +#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ +#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ +#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ +#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ +#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ +#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ +#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ +#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ +#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ +#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ +#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ +#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ +#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ +#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ +#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ +#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ +/** + * @} + */ + +#if defined(RCC_PLLCFGR_PLLR) +/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) + * @{ + */ +#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ +#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ +#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ +#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ +#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ +#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ +/** + * @} + */ +#endif /* RCC_PLLCFGR_PLLR */ + +/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) + * @{ + */ +#define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ +#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ +#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ +#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) + * @{ + */ +#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ +#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ +#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ +#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ +#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ +#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ +#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ +#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ +#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ +#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ +#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ +#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ +#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ +#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection + * @{ + */ +#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ +#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) + * @{ + */ +#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ +#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ +#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ +#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ +#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ +#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ +#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ +#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ +#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ +#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ +#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ +#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ +#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ +#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) + * @{ + */ +#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ +#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ +#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ +#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ +#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ +#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ +#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ +#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ +#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ +#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ +#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ +#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ +#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ +#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ +#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ +#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ +#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ +#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ +#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ +#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ +#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ +#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ +#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ +#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ +#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ +#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ +#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ +#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ +#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ +#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ +#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ +#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) + * @{ + */ +#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ +#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ +#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ +#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ +#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ +#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ +/** + * @} + */ + +#if defined(RCC_PLLI2SCFGR_PLLI2SP) +/** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) + * @{ + */ +#define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ +#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ +#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ +#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ +/** + * @} + */ +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + +/** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) + * @{ + */ +#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ +#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ +#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ +#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ +#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ +#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ +#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ +#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ +#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ +#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ +#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ +#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ +#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ +#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) + * @{ + */ +#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ +#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ +#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ +#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ +#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ +#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ +#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ +#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ +#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ +#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ +#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ +#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ +#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ +#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ +#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ +#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ +#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ +#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ +#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ +#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ +#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ +#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ +#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ +#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ +#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ +#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ +#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ +#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ +#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ +#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ +#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ +#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ +/** + * @} + */ + +#if defined(RCC_PLLSAICFGR_PLLSAIR) +/** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) + * @{ + */ +#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ +#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ +#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ +#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ +#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ +#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ +/** + * @} + */ +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + +#if defined(RCC_DCKCFGR1_PLLSAIDIVR) +/** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) + * @{ + */ +#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ +#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ +#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ +#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ +/** + * @} + */ +#endif /* RCC_DCKCFGR1_PLLSAIDIVR */ + +/** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) + * @{ + */ +#define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ +#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ +#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ +#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ + +/** + * @brief Helper macro to calculate the PLLCLK frequency on system domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) + +/** + * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain + * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) + +#if defined(DSI) +/** + * @brief Helper macro to calculate the PLLCLK frequency used on DSI + * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLN__ Between 50 and 432 + * @param __PLLR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ + ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) +#endif /* DSI */ + +/** + * @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains + * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLSAIN__ Between 50 and 432 + * @param __PLLSAIQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + * @param __PLLSAIDIVQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U))) + +/** + * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLSAIN__ Between 50 and 432 + * @param __PLLSAIP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U)) + +#if defined(LTDC) +/** + * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain + * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLSAIN__ Between 50 and 432 + * @param __PLLSAIR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + * @param __PLLSAIDIVR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + * @retval PLLSAI clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ + (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos]))) +#endif /* LTDC */ + +/** + * @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains + * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + * @param __PLLI2SDIVQ__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U))) + +#if defined(SPDIFRX) +/** + * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SP__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) +#endif /* SPDIFRX */ + +/** + * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain + * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), + * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + * @param __PLLM__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param __PLLI2SN__ Between 50 and 432 + * @param __PLLI2SR__ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + * @retval PLLI2S clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ + ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (ABP1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) + +/** + * @brief Helper macro to calculate the PCLK2 frequency (ABP2) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB2PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval PCLK2 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); +} + +/** + * @brief Get HSI Calibration value + * @note When HSITRIM is written, HSICAL is updated with the sum of + * HSITRIM and the factory trim value + * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration + * @retval Between Min_Data = 0x00 and Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); +} + +/** + * @brief Set HSI Calibration trimming + * @note user-programmable trimming value that is added to the HSICAL + * @note Default value is 16, which, when added to the HSICAL value, + * should trim the HSI to 16 MHz +/- 1 % + * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming + * @param Value Between Min_Data = 0 and Max_Data = 31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 31 + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); +} + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); +} + +/** + * @brief Set APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); +} + +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); +} + +/** + * @brief Get APB2 prescaler + * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB2_DIV_1 + * @arg @ref LL_RCC_APB2_DIV_2 + * @arg @ref LL_RCC_APB2_DIV_4 + * @arg @ref LL_RCC_APB2_DIV_8 + * @arg @ref LL_RCC_APB2_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n + * CFGR MCO1PRE LL_RCC_ConfigMCO\n + * CFGR MCO2 LL_RCC_ConfigMCO\n + * CFGR MCO2PRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S + * @arg @ref LL_RCC_MCO2SOURCE_HSE + * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_3 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_5 + * @arg @ref LL_RCC_MCO2_DIV_1 + * @arg @ref LL_RCC_MCO2_DIV_2 + * @arg @ref LL_RCC_MCO2_DIV_3 + * @arg @ref LL_RCC_MCO2_DIV_4 + * @arg @ref LL_RCC_MCO2_DIV_5 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +/** + * @brief Configure USARTx clock source + * @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n + * DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n + * DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n + * DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource + * @param USARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure UARTx clock source + * @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n + * DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n + * DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n + * DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource + * @param UARTxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); +} + +/** + * @brief Configure I2Cx clock source + * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n + * DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n + * DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n + * DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource + * @param I2CxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U)); +} + +/** + * @brief Configure LPTIMx clock source + * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); +} + +/** + * @brief Configure SAIx clock source + * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n + * DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource + * @param SAIxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) +{ + MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); +} + +/** + * @brief Configure SDMMC clock source + * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n + * DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource + * @param SDMMCxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U)); +} + +/** + * @brief Configure 48Mhz domain clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource + * @param CK48MxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); +} + +/** + * @brief Configure RNG clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource + * @param RNGxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); +} + +/** + * @brief Configure USB clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource + * @param USBxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); +} + +#if defined(CEC) +/** + * @brief Configure CEC clock source + * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); +} +#endif /* CEC */ + +/** + * @brief Configure I2S clock source + * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); +} + +#if defined(DSI) +/** + * @brief Configure DSI clock source + * @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source); +} +#endif /* DSI */ + +#if defined(DFSDM1_Channel0) +/** + * @brief Configure DFSDM Audio clock source + * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source); +} + +/** + * @brief Configure DFSDM Kernel clock source + * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source); +} +#endif /* DFSDM1_Channel0 */ + +/** + * @brief Get USARTx clock source + * @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n + * DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n + * DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n + * DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource + * @param USARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE + * @arg @ref LL_RCC_USART2_CLKSOURCE + * @arg @ref LL_RCC_USART3_CLKSOURCE + * @arg @ref LL_RCC_USART6_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE + * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI + * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U)); +} + +/** + * @brief Get UARTx clock source + * @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n + * DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n + * DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n + * DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource + * @param UARTx This parameter can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE + * @arg @ref LL_RCC_UART5_CLKSOURCE + * @arg @ref LL_RCC_UART7_CLKSOURCE + * @arg @ref LL_RCC_UART8_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE + * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI + * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U)); +} + +/** + * @brief Get I2Cx clock source + * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n + * DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n + * DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n + * DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource + * @param I2Cx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE + * @arg @ref LL_RCC_I2C2_CLKSOURCE + * @arg @ref LL_RCC_I2C3_CLKSOURCE + * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI + * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*) + * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) +{ + return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx); +} + +/** + * @brief Get LPTIMx clock source + * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); +} + +/** + * @brief Get SAIx clock source + * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n + * DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource + * @param SAIx This parameter can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE + * @arg @ref LL_RCC_SAI2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*) + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN + * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx); +} + +/** + * @brief Get SDMMCx clock source + * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n + * DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource + * @param SDMMCx This parameter can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*) + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK + * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*) + * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx); +} + +/** + * @brief Get 48Mhz domain clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource + * @param CK48Mx This parameter can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL + * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI + */ +__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); +} + +/** + * @brief Get RNGx clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource + * @param RNGx This parameter can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL + * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI + */ +__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); +} + +/** + * @brief Get USBx clock source + * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource + * @param USBx This parameter can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_USB_CLKSOURCE_PLL + * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI + */ +__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); +} + +#if defined(CEC) +/** + * @brief Get CEC Clock Source + * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource + * @param CECx This parameter can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE + * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 + */ +__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); +} +#endif /* CEC */ + +/** + * @brief Get I2S Clock Source + * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource + * @param I2Sx This parameter can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S + * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN + */ +__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); +} + +#if defined(DFSDM1_Channel0) +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 + * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); +} + +/** + * @brief Get DFSDM Audio Clock Source + * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource + * @param DFSDMx This parameter can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 + * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK + */ +__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx)); +} +#endif /* DFSDM1_Channel0 */ + +#if defined(DSI) +/** + * @brief Get DSI Clock Source + * @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource + * @param DSIx This parameter can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY + * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL + */ +__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx)); +} +#endif /* DSI */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} + +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Set HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); +} + +/** + * @brief Get HSE Prescalers for RTC Clock + * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_NOCLOCK + * @arg @ref LL_RCC_RTC_HSE_DIV_2 + * @arg @ref LL_RCC_RTC_HSE_DIV_3 + * @arg @ref LL_RCC_RTC_HSE_DIV_4 + * @arg @ref LL_RCC_RTC_HSE_DIV_5 + * @arg @ref LL_RCC_RTC_HSE_DIV_6 + * @arg @ref LL_RCC_RTC_HSE_DIV_7 + * @arg @ref LL_RCC_RTC_HSE_DIV_8 + * @arg @ref LL_RCC_RTC_HSE_DIV_9 + * @arg @ref LL_RCC_RTC_HSE_DIV_10 + * @arg @ref LL_RCC_RTC_HSE_DIV_11 + * @arg @ref LL_RCC_RTC_HSE_DIV_12 + * @arg @ref LL_RCC_RTC_HSE_DIV_13 + * @arg @ref LL_RCC_RTC_HSE_DIV_14 + * @arg @ref LL_RCC_RTC_HSE_DIV_15 + * @arg @ref LL_RCC_RTC_HSE_DIV_16 + * @arg @ref LL_RCC_RTC_HSE_DIV_17 + * @arg @ref LL_RCC_RTC_HSE_DIV_18 + * @arg @ref LL_RCC_RTC_HSE_DIV_19 + * @arg @ref LL_RCC_RTC_HSE_DIV_20 + * @arg @ref LL_RCC_RTC_HSE_DIV_21 + * @arg @ref LL_RCC_RTC_HSE_DIV_22 + * @arg @ref LL_RCC_RTC_HSE_DIV_23 + * @arg @ref LL_RCC_RTC_HSE_DIV_24 + * @arg @ref LL_RCC_RTC_HSE_DIV_25 + * @arg @ref LL_RCC_RTC_HSE_DIV_26 + * @arg @ref LL_RCC_RTC_HSE_DIV_27 + * @arg @ref LL_RCC_RTC_HSE_DIV_28 + * @arg @ref LL_RCC_RTC_HSE_DIV_29 + * @arg @ref LL_RCC_RTC_HSE_DIV_30 + * @arg @ref LL_RCC_RTC_HSE_DIV_31 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM + * @{ + */ + +/** + * @brief Set Timers Clock Prescalers + * @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler); +} + +/** + * @brief Get Timers Clock Prescalers + * @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_TIM_PRESCALER_TWICE + * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES + */ +__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); +} + +/** + * @brief Configure PLL used for SYSCLK Domain + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLP can be written only when PLL is disabled + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n + * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP); +} + +/** + * @brief Configure PLL used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLQ can be written only when PLL is disabled + * @note This can be selected for USB, RNG, SDMMC1 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n + * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); +} + +#if defined(DSI) +/** + * @brief Configure PLL used for DSI clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLL is disabled + * @note This can be selected for DSI + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n + * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, + Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); +} +#endif /* DSI */ + +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} + +/** + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 50 and 432 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); +} + +/** + * @brief Get Main PLL division factor for PLLP + * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLP_DIV_2 + * @arg @ref LL_RCC_PLLP_DIV_4 + * @arg @ref LL_RCC_PLLP_DIV_6 + * @arg @ref LL_RCC_PLLP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); +} + +/** + * @brief Get Main PLL division factor for PLLQ + * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock) + * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLQ_DIV_2 + * @arg @ref LL_RCC_PLLQ_DIV_3 + * @arg @ref LL_RCC_PLLQ_DIV_4 + * @arg @ref LL_RCC_PLLQ_DIV_5 + * @arg @ref LL_RCC_PLLQ_DIV_6 + * @arg @ref LL_RCC_PLLQ_DIV_7 + * @arg @ref LL_RCC_PLLQ_DIV_8 + * @arg @ref LL_RCC_PLLQ_DIV_9 + * @arg @ref LL_RCC_PLLQ_DIV_10 + * @arg @ref LL_RCC_PLLQ_DIV_11 + * @arg @ref LL_RCC_PLLQ_DIV_12 + * @arg @ref LL_RCC_PLLQ_DIV_13 + * @arg @ref LL_RCC_PLLQ_DIV_14 + * @arg @ref LL_RCC_PLLQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); +} + +#if defined(RCC_PLLCFGR_PLLR) +/** + * @brief Get Main PLL division factor for PLLR + * @note used for PLLCLK (system clock) + * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLR_DIV_2 + * @arg @ref LL_RCC_PLLR_DIV_3 + * @arg @ref LL_RCC_PLLR_DIV_4 + * @arg @ref LL_RCC_PLLR_DIV_5 + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); +} +#endif /* RCC_PLLCFGR_PLLR */ + +/** + * @brief Get Division factor for the main PLL and other PLL + * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); +} + +/** + * @brief Configure Spread Spectrum used for PLL + * @note These bits must be written before enabling PLL + * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n + * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n + * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum + * @param Mod Between Min_Data=0 and Max_Data=8191 + * @param Inc Between Min_Data=0 and Max_Data=32767 + * @param Sel This parameter can be one of the following values: + * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + * @arg @ref LL_RCC_SPREAD_SELECT_DOWN + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) +{ + MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); +} + +/** + * @brief Get Spread Spectrum Modulation Period for PLL + * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation + * @retval Between Min_Data=0 and Max_Data=8191 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); +} + +/** + * @brief Get Spread Spectrum Incrementation Step for PLL + * @note Must be written before enabling PLL + * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation + * @retval Between Min_Data=0 and Max_Data=32767 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); +} + +/** + * @brief Get Spread Spectrum Selection for PLL + * @note Must be written before enabling PLL + * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SPREAD_SELECT_CENTER + * @arg @ref LL_RCC_SPREAD_SELECT_DOWN + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) +{ + return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); +} + +/** + * @brief Enable Spread Spectrum for PLL. + * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) +{ + SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +} + +/** + * @brief Disable Spread Spectrum for PLL. + * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) +{ + CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLLI2S PLLI2S + * @{ + */ + +/** + * @brief Enable PLLI2S + * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLI2SON); +} + +/** + * @brief Disable PLLI2S + * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); +} + +/** + * @brief Check if PLLI2S Ready + * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); +} + +/** + * @brief Configure PLLI2S used for SAI1 and SAI2 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLQ can be written only when PLLI2S is disabled + * @note This can be selected for SAI1 and SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n + * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n + * DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + * @param PLLDIVQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ); +} + +#if defined(SPDIFRX) +/** + * @brief Configure PLLI2S used for SPDIFRX domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLP can be written only when PLLI2S is disabled + * @note This can be selected for SPDIFRX + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n + * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); +} +#endif /* SPDIFRX */ + +/** + * @brief Configure PLLI2S used for I2S1 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLLI2S is disabled + * @note This can be selected for I2S + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n + * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); +} + +/** + * @brief Get I2SPLL multiplication factor for VCO + * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN + * @retval Between 50 and 432 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); +} + +/** + * @brief Get I2SPLL division factor for PLLI2SQ + * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); +} + +/** + * @brief Get I2SPLL division factor for PLLI2SR + * @note used for PLLI2SCLK (I2S clock) + * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SR_DIV_2 + * @arg @ref LL_RCC_PLLI2SR_DIV_3 + * @arg @ref LL_RCC_PLLI2SR_DIV_4 + * @arg @ref LL_RCC_PLLI2SR_DIV_5 + * @arg @ref LL_RCC_PLLI2SR_DIV_6 + * @arg @ref LL_RCC_PLLI2SR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); +} + +#if defined(RCC_PLLI2SCFGR_PLLI2SP) +/** + * @brief Get I2SPLL division factor for PLLI2SP + * @note used for PLLSPDIFRXCLK (SPDIFRX clock) + * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SP_DIV_2 + * @arg @ref LL_RCC_PLLI2SP_DIV_4 + * @arg @ref LL_RCC_PLLI2SP_DIV_6 + * @arg @ref LL_RCC_PLLI2SP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); +} +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + +/** + * @brief Get I2SPLL division factor for PLLI2SDIVQ + * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) + * @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_PLLSAI PLLSAI + * @{ + */ + +/** + * @brief Enable PLLSAI + * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLSAION); +} + +/** + * @brief Disable PLLSAI + * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); +} + +/** + * @brief Check if PLLSAI Ready + * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) +{ + return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); +} + +/** + * @brief Configure PLLSAI used for SAI1 and SAI2 domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLQ can be written only when PLLSAI is disabled + * @note This can be selected for SAI1 and SAI2 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n + * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n + * DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + * @param PLLDIVQ This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ); +} + +/** + * @brief Configure PLLSAI used for 48Mhz domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLP can be written only when PLLSAI is disabled + * @note This can be selected for USB, RNG, SDMMC1 + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n + * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLP This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); +} + +#if defined(LTDC) +/** + * @brief Configure PLLSAI used for LTDC domain clock + * @note PLL Source and PLLM Divider can be written only when PLL, + * PLLI2S and PLLSAI are disabled + * @note PLLN/PLLR can be written only when PLLSAI is disabled + * @note This can be selected for LTDC + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n + * DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @param PLLM This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLM_DIV_2 + * @arg @ref LL_RCC_PLLM_DIV_3 + * @arg @ref LL_RCC_PLLM_DIV_4 + * @arg @ref LL_RCC_PLLM_DIV_5 + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + * @arg @ref LL_RCC_PLLM_DIV_9 + * @arg @ref LL_RCC_PLLM_DIV_10 + * @arg @ref LL_RCC_PLLM_DIV_11 + * @arg @ref LL_RCC_PLLM_DIV_12 + * @arg @ref LL_RCC_PLLM_DIV_13 + * @arg @ref LL_RCC_PLLM_DIV_14 + * @arg @ref LL_RCC_PLLM_DIV_15 + * @arg @ref LL_RCC_PLLM_DIV_16 + * @arg @ref LL_RCC_PLLM_DIV_17 + * @arg @ref LL_RCC_PLLM_DIV_18 + * @arg @ref LL_RCC_PLLM_DIV_19 + * @arg @ref LL_RCC_PLLM_DIV_20 + * @arg @ref LL_RCC_PLLM_DIV_21 + * @arg @ref LL_RCC_PLLM_DIV_22 + * @arg @ref LL_RCC_PLLM_DIV_23 + * @arg @ref LL_RCC_PLLM_DIV_24 + * @arg @ref LL_RCC_PLLM_DIV_25 + * @arg @ref LL_RCC_PLLM_DIV_26 + * @arg @ref LL_RCC_PLLM_DIV_27 + * @arg @ref LL_RCC_PLLM_DIV_28 + * @arg @ref LL_RCC_PLLM_DIV_29 + * @arg @ref LL_RCC_PLLM_DIV_30 + * @arg @ref LL_RCC_PLLM_DIV_31 + * @arg @ref LL_RCC_PLLM_DIV_32 + * @arg @ref LL_RCC_PLLM_DIV_33 + * @arg @ref LL_RCC_PLLM_DIV_34 + * @arg @ref LL_RCC_PLLM_DIV_35 + * @arg @ref LL_RCC_PLLM_DIV_36 + * @arg @ref LL_RCC_PLLM_DIV_37 + * @arg @ref LL_RCC_PLLM_DIV_38 + * @arg @ref LL_RCC_PLLM_DIV_39 + * @arg @ref LL_RCC_PLLM_DIV_40 + * @arg @ref LL_RCC_PLLM_DIV_41 + * @arg @ref LL_RCC_PLLM_DIV_42 + * @arg @ref LL_RCC_PLLM_DIV_43 + * @arg @ref LL_RCC_PLLM_DIV_44 + * @arg @ref LL_RCC_PLLM_DIV_45 + * @arg @ref LL_RCC_PLLM_DIV_46 + * @arg @ref LL_RCC_PLLM_DIV_47 + * @arg @ref LL_RCC_PLLM_DIV_48 + * @arg @ref LL_RCC_PLLM_DIV_49 + * @arg @ref LL_RCC_PLLM_DIV_50 + * @arg @ref LL_RCC_PLLM_DIV_51 + * @arg @ref LL_RCC_PLLM_DIV_52 + * @arg @ref LL_RCC_PLLM_DIV_53 + * @arg @ref LL_RCC_PLLM_DIV_54 + * @arg @ref LL_RCC_PLLM_DIV_55 + * @arg @ref LL_RCC_PLLM_DIV_56 + * @arg @ref LL_RCC_PLLM_DIV_57 + * @arg @ref LL_RCC_PLLM_DIV_58 + * @arg @ref LL_RCC_PLLM_DIV_59 + * @arg @ref LL_RCC_PLLM_DIV_60 + * @arg @ref LL_RCC_PLLM_DIV_61 + * @arg @ref LL_RCC_PLLM_DIV_62 + * @arg @ref LL_RCC_PLLM_DIV_63 + * @param PLLN Between 50 and 432 + * @param PLLR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + * @param PLLDIVR This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); + MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); + MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR); +} +#endif /* LTDC */ + +/** + * @brief Get SAIPLL multiplication factor for VCO + * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN + * @retval Between 50 and 432 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); +} + +/** + * @brief Get SAIPLL division factor for PLLSAIQ + * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIQ_DIV_15 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); +} + +#if defined(RCC_PLLSAICFGR_PLLSAIR) +/** + * @brief Get SAIPLL division factor for PLLSAIR + * @note used for PLLSAICLK (SAI clock) + * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIR_DIV_2 + * @arg @ref LL_RCC_PLLSAIR_DIV_3 + * @arg @ref LL_RCC_PLLSAIR_DIV_4 + * @arg @ref LL_RCC_PLLSAIR_DIV_5 + * @arg @ref LL_RCC_PLLSAIR_DIV_6 + * @arg @ref LL_RCC_PLLSAIR_DIV_7 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); +} +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + +/** + * @brief Get SAIPLL division factor for PLLSAIP + * @note used for PLL48MCLK (48M domain clock) + * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIP_DIV_2 + * @arg @ref LL_RCC_PLLSAIP_DIV_4 + * @arg @ref LL_RCC_PLLSAIP_DIV_6 + * @arg @ref LL_RCC_PLLSAIP_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); +} + +/** + * @brief Get SAIPLL division factor for PLLSAIDIVQ + * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock) + * @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 + * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ)); +} + +#if defined(RCC_DCKCFGR1_PLLSAIDIVR) +/** + * @brief Get SAIPLL division factor for PLLSAIDIVR + * @note used for LTDC domain clock + * @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 + * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) +{ + return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR)); +} +#endif /* RCC_DCKCFGR1_PLLSAIDIVR */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); +} + +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); +} + +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); +} + +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); +} + +/** + * @brief Clear PLLI2S ready interrupt flag + * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); +} + +/** + * @brief Clear PLLSAI ready interrupt flag + * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); +} + +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_CSSC); +} + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); +} + +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); +} + +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); +} + +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); +} + +/** + * @brief Check if PLLI2S ready interrupt occurred or not + * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); +} + +/** + * @brief Check if PLLSAI ready interrupt occurred or not + * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); +} + +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); +} + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); +} + +/** + * @brief Check if RCC flag Low Power reset is set or not. + * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); +} + +/** + * @brief Check if RCC flag POR/PDR reset is set or not. + * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); +} + +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); +} + +/** + * @brief Check if RCC flag BOR reset is set or not. + * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) +{ + return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Enable PLLI2S ready interrupt + * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +} + +/** + * @brief Enable PLLSAI ready interrupt + * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) +{ + SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +} + +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); +} + +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); +} + +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); +} + +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); +} + +/** + * @brief Disable PLLI2S ready interrupt + * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); +} + +/** + * @brief Disable PLLSAI ready interrupt + * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) +{ + CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); +} + +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); +} + +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); +} + +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); +} + +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); +} + +/** + * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); +} + +/** + * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. + * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) +{ + return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); +uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); +uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); +uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); +uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); +uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); +uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); +#if defined(DFSDM1_Channel0) +uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); +uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); +#endif /* DFSDM1_Channel0 */ +uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); +#if defined(CEC) +uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); +#endif /* CEC */ +#if defined(LTDC) +uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); +#endif /* LTDC */ +#if defined(SPDIFRX) +uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); +#endif /* SPDIFRX */ +#if defined(DSI) +uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); +#endif /* DSI */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_RCC_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rng.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rng.h deleted file mode 100644 index 2b563883..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rng.h +++ /dev/null @@ -1,336 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_rng.h - * @author MCD Application Team - * @brief Header file of RNG LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_RNG_H -#define STM32F7xx_LL_RNG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (RNG) - -/** @defgroup RNG_LL RNG - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants - * @{ - */ - - -/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_RNG_ReadReg function - * @{ - */ -#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */ -#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */ -#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */ -#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */ -#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */ -/** - * @} - */ - -/** @defgroup RNG_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros - * @{ - */ -#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros - * @{ - */ - -/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RNG register - * @param __INSTANCE__ RNG Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RNG register - * @param __INSTANCE__ RNG Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions - * @{ - */ -/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions - * @{ - */ - -/** - * @brief Enable Random Number Generation - * @rmtoll CR RNGEN LL_RNG_Enable - * @param RNGx RNG Instance - * @retval None - */ -__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx) -{ - SET_BIT(RNGx->CR, RNG_CR_RNGEN); -} - -/** - * @brief Disable Random Number Generation - * @rmtoll CR RNGEN LL_RNG_Disable - * @param RNGx RNG Instance - * @retval None - */ -__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) -{ - CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN); -} - -/** - * @brief Check if Random Number Generator is enabled - * @rmtoll CR RNGEN LL_RNG_IsEnabled - * @param RNGx RNG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) -{ - return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Indicate if the RNG Data ready Flag is set or not - * @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY - * @param RNGx RNG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) -{ - return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); -} - -/** - * @brief Indicate if the Clock Error Current Status Flag is set or not - * @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS - * @param RNGx RNG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) -{ - return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); -} - -/** - * @brief Indicate if the Seed Error Current Status Flag is set or not - * @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS - * @param RNGx RNG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) -{ - return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); -} - -/** - * @brief Indicate if the Clock Error Interrupt Status Flag is set or not - * @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS - * @param RNGx RNG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) -{ - return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); -} - -/** - * @brief Indicate if the Seed Error Interrupt Status Flag is set or not - * @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS - * @param RNGx RNG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) -{ - return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); -} - -/** - * @brief Clear Clock Error interrupt Status (CEIS) Flag - * @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS - * @param RNGx RNG Instance - * @retval None - */ -__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx) -{ - WRITE_REG(RNGx->SR, ~RNG_SR_CEIS); -} - -/** - * @brief Clear Seed Error interrupt Status (SEIS) Flag - * @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS - * @param RNGx RNG Instance - * @retval None - */ -__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx) -{ - WRITE_REG(RNGx->SR, ~RNG_SR_SEIS); -} - -/** - * @} - */ - -/** @defgroup RNG_LL_EF_IT_Management IT Management - * @{ - */ - -/** - * @brief Enable Random Number Generator Interrupt - * (applies for either Seed error, Clock Error or Data ready interrupts) - * @rmtoll CR IE LL_RNG_EnableIT - * @param RNGx RNG Instance - * @retval None - */ -__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx) -{ - SET_BIT(RNGx->CR, RNG_CR_IE); -} - -/** - * @brief Disable Random Number Generator Interrupt - * (applies for either Seed error, Clock Error or Data ready interrupts) - * @rmtoll CR IE LL_RNG_DisableIT - * @param RNGx RNG Instance - * @retval None - */ -__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) -{ - CLEAR_BIT(RNGx->CR, RNG_CR_IE); -} - -/** - * @brief Check if Random Number Generator Interrupt is enabled - * (applies for either Seed error, Clock Error or Data ready interrupts) - * @rmtoll CR IE LL_RNG_IsEnabledIT - * @param RNGx RNG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) -{ - return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup RNG_LL_EF_Data_Management Data Management - * @{ - */ - -/** - * @brief Return32-bit Random Number value - * @rmtoll DR RNDATA LL_RNG_ReadRandData32 - * @param RNGx RNG Instance - * @retval Generated 32-bit random value - */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) -{ - return (uint32_t)(READ_REG(RNGx->DR)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions - * @{ - */ -ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* RNG */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_RNG_H */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h deleted file mode 100644 index f8fa9fe8..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_rtc.h +++ /dev/null @@ -1,3834 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_rtc.h - * @author MCD Application Team - * @brief Header file of RTC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_RTC_H -#define STM32F7xx_LL_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(RTC) - -/** @defgroup RTC_LL RTC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RTC_LL_Private_Constants RTC Private Constants - * @{ - */ -/* Masks Definition */ -#define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) - -/* Write protection defines */ -#define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) -#define RTC_WRITE_PROTECTION_ENABLE_1 ((uint8_t)0xCAU) -#define RTC_WRITE_PROTECTION_ENABLE_2 ((uint8_t)0x53U) - -/* Defines used to combine date & time */ -#define RTC_OFFSET_WEEKDAY 24U -#define RTC_OFFSET_DAY 16U -#define RTC_OFFSET_MONTH 8U -#define RTC_OFFSET_HOUR 16U -#define RTC_OFFSET_MINUTE 8U - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_Private_Macros RTC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure - * @{ - */ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t HourFormat; /*!< Specifies the RTC Hours Format. - This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT - - This feature can be modified afterwards using unitary function - @ref LL_RTC_SetHourFormat(). */ - - uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F - - This feature can be modified afterwards using unitary function - @ref LL_RTC_SetAsynchPrescaler(). */ - - uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF - - This feature can be modified afterwards using unitary function - @ref LL_RTC_SetSynchPrescaler(). */ -} LL_RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time. - This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT - - This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */ - - uint8_t Hours; /*!< Specifies the RTC Time Hours. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected. - - This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 - - This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 - - This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */ -} LL_RTC_TimeTypeDef; - -/** - * @brief RTC Date structure definition - */ -typedef struct -{ - uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay. - This parameter can be a value of @ref RTC_LL_EC_WEEKDAY - - This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */ - - uint8_t Month; /*!< Specifies the RTC Date Month. - This parameter can be a value of @ref RTC_LL_EC_MONTH - - This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */ - - uint8_t Day; /*!< Specifies the RTC Date Day. - This parameter must be a number between Min_Data = 1 and Max_Data = 31 - - This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */ - - uint8_t Year; /*!< Specifies the RTC Date Year. - This parameter must be a number between Min_Data = 0 and Max_Data = 99 - - This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */ -} LL_RTC_DateTypeDef; - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - - uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. - This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. - - This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A - or @ref LL_RTC_ALMB_SetMask() for ALARM B. - */ - - uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. - This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B - - This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday() - for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B - */ - - uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay. - If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31. - - This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay() - for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B. - - If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY. - - This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay() - for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B. - */ -} LL_RTC_AlarmTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants - * @{ - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_EC_FORMAT FORMAT - * @{ - */ -#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay - * @{ - */ -#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */ -#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay - * @{ - */ -#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */ -#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */ -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_RTC_ReadReg function - * @{ - */ -#define LL_RTC_ISR_ITSF RTC_ISR_ITSF -#define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF -#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F -#define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F -#define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F -#define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF -#define LL_RTC_ISR_TSF RTC_ISR_TSF -#define LL_RTC_ISR_WUTF RTC_ISR_WUTF -#define LL_RTC_ISR_ALRBF RTC_ISR_ALRBF -#define LL_RTC_ISR_ALRAF RTC_ISR_ALRAF -#define LL_RTC_ISR_INITF RTC_ISR_INITF -#define LL_RTC_ISR_RSF RTC_ISR_RSF -#define LL_RTC_ISR_INITS RTC_ISR_INITS -#define LL_RTC_ISR_SHPF RTC_ISR_SHPF -#define LL_RTC_ISR_WUTWF RTC_ISR_WUTWF -#define LL_RTC_ISR_ALRBWF RTC_ISR_ALRBWF -#define LL_RTC_ISR_ALRAWF RTC_ISR_ALRAWF -/** - * @} - */ - -/** @defgroup RTC_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions - * @{ - */ -#define LL_RTC_CR_TSIE RTC_CR_TSIE -#define LL_RTC_CR_WUTIE RTC_CR_WUTIE -#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE -#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE -#define LL_RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE -#define LL_RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE -#define LL_RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE -#define LL_RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE -/** - * @} - */ - -/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY - * @{ - */ -#define LL_RTC_WEEKDAY_MONDAY ((uint8_t)0x01U) /*!< Monday */ -#define LL_RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */ -#define LL_RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U) /*!< Wednesday */ -#define LL_RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U) /*!< Thrusday */ -#define LL_RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U) /*!< Friday */ -#define LL_RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U) /*!< Saturday */ -#define LL_RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U) /*!< Sunday */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_MONTH MONTH - * @{ - */ -#define LL_RTC_MONTH_JANUARY ((uint8_t)0x01U) /*!< January */ -#define LL_RTC_MONTH_FEBRUARY ((uint8_t)0x02U) /*!< February */ -#define LL_RTC_MONTH_MARCH ((uint8_t)0x03U) /*!< March */ -#define LL_RTC_MONTH_APRIL ((uint8_t)0x04U) /*!< April */ -#define LL_RTC_MONTH_MAY ((uint8_t)0x05U) /*!< May */ -#define LL_RTC_MONTH_JUNE ((uint8_t)0x06U) /*!< June */ -#define LL_RTC_MONTH_JULY ((uint8_t)0x07U) /*!< July */ -#define LL_RTC_MONTH_AUGUST ((uint8_t)0x08U) /*!< August */ -#define LL_RTC_MONTH_SEPTEMBER ((uint8_t)0x09U) /*!< September */ -#define LL_RTC_MONTH_OCTOBER ((uint8_t)0x10U) /*!< October */ -#define LL_RTC_MONTH_NOVEMBER ((uint8_t)0x11U) /*!< November */ -#define LL_RTC_MONTH_DECEMBER ((uint8_t)0x12U) /*!< December */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT - * @{ - */ -#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */ -#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT - * @{ - */ -#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */ -#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */ -#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */ -#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE - * @{ - */ -#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN 0x00000000U /*!< RTC_ALARM, when mapped on PC13, is open-drain output */ -#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL RTC_OR_ALARMOUTTYPE /*!< RTC_ALARM, when mapped on PC13, is push-pull output */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN - * @{ - */ -#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/ -#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT - * @{ - */ -#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */ -#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND - * @{ - */ -#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */ -#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK - * @{ - */ -#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/ -#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */ -#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */ -#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */ -#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */ -#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT - * @{ - */ -#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ -#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK - * @{ - */ -#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B */ -#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT - * @{ - */ -#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ -#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE - * @{ - */ -#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */ -#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT - * @{ - */ -#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */ -#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER TAMPER - * @{ - */ -#define LL_RTC_TAMPER_1 RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */ -#define LL_RTC_TAMPER_2 RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */ -#define LL_RTC_TAMPER_3 RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK - * @{ - */ -#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ -#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ -#define LL_RTC_TAMPER_MASK_TAMPER3 RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE - * @{ - */ -#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ -#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ -#define LL_RTC_TAMPER_NOERASE_TAMPER3 RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION - * @{ - */ -#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */ -#define LL_RTC_TAMPER_DURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */ -#define LL_RTC_TAMPER_DURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */ -#define LL_RTC_TAMPER_DURATION_8RTCCLK RTC_TAMPCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER - * @{ - */ -#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ -#define LL_RTC_TAMPER_FILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ -#define LL_RTC_TAMPER_FILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ -#define LL_RTC_TAMPER_FILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER - * @{ - */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 RTC_TAMPCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ -#define LL_RTC_TAMPER_SAMPLFREQDIV_256 RTC_TAMPCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL - * @{ - */ -#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ -#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ -#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV - * @{ - */ -#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_DIV_8 (RTC_CR_WUCKSEL_0) /*!< RTC/8 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_DIV_4 (RTC_CR_WUCKSEL_1) /*!< RTC/4 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */ -#define LL_RTC_WAKEUPCLOCK_CKSPRE (RTC_CR_WUCKSEL_2) /*!< ck_spre (usually 1 Hz) clock is selected */ -#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_BKP BACKUP - * @{ - */ -#define LL_RTC_BKP_DR0 0x00000000U -#define LL_RTC_BKP_DR1 0x00000001U -#define LL_RTC_BKP_DR2 0x00000002U -#define LL_RTC_BKP_DR3 0x00000003U -#define LL_RTC_BKP_DR4 0x00000004U -#define LL_RTC_BKP_DR5 0x00000005U -#define LL_RTC_BKP_DR6 0x00000006U -#define LL_RTC_BKP_DR7 0x00000007U -#define LL_RTC_BKP_DR8 0x00000008U -#define LL_RTC_BKP_DR9 0x00000009U -#define LL_RTC_BKP_DR10 0x0000000AU -#define LL_RTC_BKP_DR11 0x0000000BU -#define LL_RTC_BKP_DR12 0x0000000CU -#define LL_RTC_BKP_DR13 0x0000000DU -#define LL_RTC_BKP_DR14 0x0000000EU -#define LL_RTC_BKP_DR15 0x0000000FU -#define LL_RTC_BKP_DR16 0x00000010U -#define LL_RTC_BKP_DR17 0x00000011U -#define LL_RTC_BKP_DR18 0x00000012U -#define LL_RTC_BKP_DR19 0x00000013U -#define LL_RTC_BKP_DR20 0x00000014U -#define LL_RTC_BKP_DR21 0x00000015U -#define LL_RTC_BKP_DR22 0x00000016U -#define LL_RTC_BKP_DR23 0x00000017U -#define LL_RTC_BKP_DR24 0x00000018U -#define LL_RTC_BKP_DR25 0x00000019U -#define LL_RTC_BKP_DR26 0x0000001AU -#define LL_RTC_BKP_DR27 0x0000001BU -#define LL_RTC_BKP_DR28 0x0000001CU -#define LL_RTC_BKP_DR29 0x0000001DU -#define LL_RTC_BKP_DR30 0x0000001EU -#define LL_RTC_BKP_DR31 0x0000001FU -/** - * @} - */ - -/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output - * @{ - */ -#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */ -#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */ -#define LL_RTC_CALIB_OUTPUT_512HZ (RTC_CR_COE) /*!< Calibration output is 512 Hz */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion - * @{ - */ -#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ -#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period - * @{ - */ -#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */ -#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */ -#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TSINSEL TIMESTAMP mapping - * @{ - */ -#define LL_RTC_TimeStampPin_Default 0x00000000U /*!< Use RTC_AF1 as TIMESTAMP */ -#define LL_RTC_TimeStampPin_Pos1 RTC_OR_TSINSEL /*!< Use RTC_AF2 as TIMESTAMP */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros - * @{ - */ - -/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RTC register - * @param __INSTANCE__ RTC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RTC register - * @param __INSTANCE__ RTC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup RTC_LL_EM_Convert Convert helper Macros - * @{ - */ - -/** - * @brief Helper macro to convert a value from 2 digit decimal format to BCD format - * @param __VALUE__ Byte to be converted - * @retval Converted byte - */ -#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)) - -/** - * @brief Helper macro to convert a value from BCD format to 2 digit decimal format - * @param __VALUE__ BCD value to be converted - * @retval Converted byte - */ -#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU)) - -/** - * @} - */ - -/** @defgroup RTC_LL_EM_Date Date helper Macros - * @{ - */ - -/** - * @brief Helper macro to retrieve weekday. - * @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function. - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - */ -#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU) - -/** - * @brief Helper macro to retrieve Year in BCD format - * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get - * @retval Year in BCD format (0x00 . . . 0x99) - */ -#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU) - -/** - * @brief Helper macro to retrieve Month in BCD format - * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_MONTH_JANUARY - * @arg @ref LL_RTC_MONTH_FEBRUARY - * @arg @ref LL_RTC_MONTH_MARCH - * @arg @ref LL_RTC_MONTH_APRIL - * @arg @ref LL_RTC_MONTH_MAY - * @arg @ref LL_RTC_MONTH_JUNE - * @arg @ref LL_RTC_MONTH_JULY - * @arg @ref LL_RTC_MONTH_AUGUST - * @arg @ref LL_RTC_MONTH_SEPTEMBER - * @arg @ref LL_RTC_MONTH_OCTOBER - * @arg @ref LL_RTC_MONTH_NOVEMBER - * @arg @ref LL_RTC_MONTH_DECEMBER - */ -#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU) - -/** - * @brief Helper macro to retrieve Day in BCD format - * @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get - * @retval Day in BCD format (0x01 . . . 0x31) - */ -#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU) - -/** - * @} - */ - -/** @defgroup RTC_LL_EM_Time Time helper Macros - * @{ - */ - -/** - * @brief Helper macro to retrieve hour in BCD format - * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function - * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23) - */ -#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU) - -/** - * @brief Helper macro to retrieve minute in BCD format - * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function - * @retval Minutes in BCD format (0x00. . .0x59) - */ -#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU) - -/** - * @brief Helper macro to retrieve second in BCD format - * @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function - * @retval Seconds in format (0x00. . .0x59) - */ -#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Set Hours format (24 hour/day or AM/PM hour format) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR FMT LL_RTC_SetHourFormat - * @param RTCx RTC Instance - * @param HourFormat This parameter can be one of the following values: - * @arg @ref LL_RTC_HOURFORMAT_24HOUR - * @arg @ref LL_RTC_HOURFORMAT_AMPM - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat) -{ - MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat); -} - -/** - * @brief Get Hours format (24 hour/day or AM/PM hour format) - * @rmtoll CR FMT LL_RTC_GetHourFormat - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_HOURFORMAT_24HOUR - * @arg @ref LL_RTC_HOURFORMAT_AMPM - */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); -} - -/** - * @brief Select the flag to be routed to RTC_ALARM output - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR OSEL LL_RTC_SetAlarmOutEvent - * @param RTCx RTC Instance - * @param AlarmOutput This parameter can be one of the following values: - * @arg @ref LL_RTC_ALARMOUT_DISABLE - * @arg @ref LL_RTC_ALARMOUT_ALMA - * @arg @ref LL_RTC_ALARMOUT_ALMB - * @arg @ref LL_RTC_ALARMOUT_WAKEUP - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput) -{ - MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput); -} - -/** - * @brief Get the flag to be routed to RTC_ALARM output - * @rmtoll CR OSEL LL_RTC_GetAlarmOutEvent - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_ALARMOUT_DISABLE - * @arg @ref LL_RTC_ALARMOUT_ALMA - * @arg @ref LL_RTC_ALARMOUT_ALMB - * @arg @ref LL_RTC_ALARMOUT_WAKEUP - */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); -} - -/** - * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) - * @note Used only when RTC_ALARM is mapped on PC13 - * @rmtoll OR ALARMOUTTYPE LL_RTC_SetAlarmOutputType - * @param RTCx RTC Instance - * @param Output This parameter can be one of the following values: - * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN - * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output) -{ - MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output); -} - -/** - * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) - * @note used only when RTC_ALARM is mapped on PC13 - * @rmtoll OR ALARMOUTTYPE LL_RTC_GetAlarmOutputType - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN - * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL - */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE)); -} - -/** - * @brief Enable initialization mode - * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) - * and prescaler register (RTC_PRER). - * Counters are stopped and start counting from the new value when INIT is reset. - * @rmtoll ISR INIT LL_RTC_EnableInitMode - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx) -{ - /* Set the Initialization mode */ - WRITE_REG(RTCx->ISR, RTC_INIT_MASK); -} - -/** - * @brief Disable initialization mode (Free running mode) - * @rmtoll ISR INIT LL_RTC_DisableInitMode - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx) -{ - /* Exit Initialization mode */ - WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT); -} - -/** - * @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR POL LL_RTC_SetOutputPolarity - * @param RTCx RTC Instance - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH - * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity) -{ - MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity); -} - -/** - * @brief Get Output polarity - * @rmtoll CR POL LL_RTC_GetOutputPolarity - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH - * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW - */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); -} - -/** - * @brief Enable Bypass the shadow registers - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BYPSHAD LL_RTC_EnableShadowRegBypass - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_BYPSHAD); -} - -/** - * @brief Disable Bypass the shadow registers - * @rmtoll CR BYPSHAD LL_RTC_DisableShadowRegBypass - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD); -} - -/** - * @brief Check if Shadow registers bypass is enabled or not. - * @rmtoll CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); -} - -/** - * @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR REFCKON LL_RTC_EnableRefClock - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_REFCKON); -} - -/** - * @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll CR REFCKON LL_RTC_DisableRefClock - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON); -} - -/** - * @brief Set Asynchronous prescaler factor - * @rmtoll PRER PREDIV_A LL_RTC_SetAsynchPrescaler - * @param RTCx RTC Instance - * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) -{ - MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos); -} - -/** - * @brief Set Synchronous prescaler factor - * @rmtoll PRER PREDIV_S LL_RTC_SetSynchPrescaler - * @param RTCx RTC Instance - * @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler) -{ - MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler); -} - -/** - * @brief Get Asynchronous prescaler factor - * @rmtoll PRER PREDIV_A LL_RTC_GetAsynchPrescaler - * @param RTCx RTC Instance - * @retval Value between Min_Data = 0 and Max_Data = 0x7F - */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); -} - -/** - * @brief Get Synchronous prescaler factor - * @rmtoll PRER PREDIV_S LL_RTC_GetSynchPrescaler - * @param RTCx RTC Instance - * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF - */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); -} - -/** - * @brief Enable the write protection for RTC registers. - * @rmtoll WPR KEY LL_RTC_EnableWriteProtection - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE); -} - -/** - * @brief Disable the write protection for RTC registers. - * @rmtoll WPR KEY LL_RTC_DisableWriteProtection - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1); - WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Time Time - * @{ - */ - -/** - * @brief Set time format (AM/24-hour or PM notation) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @rmtoll TR PM LL_RTC_TIME_SetFormat - * @param RTCx RTC Instance - * @param TimeFormat This parameter can be one of the following values: - * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 - * @arg @ref LL_RTC_TIME_FORMAT_PM - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) -{ - MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat); -} - -/** - * @brief Get time format (AM or PM notation) - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar - * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). - * @rmtoll TR PM LL_RTC_TIME_GetFormat - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 - * @arg @ref LL_RTC_TIME_FORMAT_PM - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); -} - -/** - * @brief Set Hours in BCD format - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format - * @rmtoll TR HT LL_RTC_TIME_SetHour\n - * TR HU LL_RTC_TIME_SetHour - * @param RTCx RTC Instance - * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) -{ - MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU), - (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))); -} - -/** - * @brief Get Hours in BCD format - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar - * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to - * Binary format - * @rmtoll TR HT LL_RTC_TIME_GetHour\n - * TR HU LL_RTC_TIME_GetHour - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); -} - -/** - * @brief Set Minutes in BCD format - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll TR MNT LL_RTC_TIME_SetMinute\n - * TR MNU LL_RTC_TIME_SetMinute - * @param RTCx RTC Instance - * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) -{ - MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU), - (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos))); -} - -/** - * @brief Get Minutes in BCD format - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar - * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD - * to Binary format - * @rmtoll TR MNT LL_RTC_TIME_GetMinute\n - * TR MNU LL_RTC_TIME_GetMinute - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x59 - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); -} - -/** - * @brief Set Seconds in BCD format - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll TR ST LL_RTC_TIME_SetSecond\n - * TR SU LL_RTC_TIME_SetSecond - * @param RTCx RTC Instance - * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) -{ - MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU), - (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos))); -} - -/** - * @brief Get Seconds in BCD format - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar - * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD - * to Binary format - * @rmtoll TR ST LL_RTC_TIME_GetSecond\n - * TR SU LL_RTC_TIME_GetSecond - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x59 - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); -} - -/** - * @brief Set time (hour, minute and second) in BCD format - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function) - * @note TimeFormat and Hours should follow the same format - * @rmtoll TR PM LL_RTC_TIME_Config\n - * TR HT LL_RTC_TIME_Config\n - * TR HU LL_RTC_TIME_Config\n - * TR MNT LL_RTC_TIME_Config\n - * TR MNU LL_RTC_TIME_Config\n - * TR ST LL_RTC_TIME_Config\n - * TR SU LL_RTC_TIME_Config - * @param RTCx RTC Instance - * @param Format12_24 This parameter can be one of the following values: - * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 - * @arg @ref LL_RTC_TIME_FORMAT_PM - * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 - * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) -{ - uint32_t temp; - - temp = Format12_24 | \ - (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ - (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); - MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); -} - -/** - * @brief Get time (hour, minute and second) in BCD format - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar - * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). - * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND - * are available to get independently each parameter. - * @rmtoll TR HT LL_RTC_TIME_Get\n - * TR HU LL_RTC_TIME_Get\n - * TR MNT LL_RTC_TIME_Get\n - * TR MNU LL_RTC_TIME_Get\n - * TR ST LL_RTC_TIME_Get\n - * TR SU LL_RTC_TIME_Get - * @param RTCx RTC Instance - * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU))); -} - -/** - * @brief Memorize whether the daylight saving time change has been performed - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BKP LL_RTC_TIME_EnableDayLightStore - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_BKP); -} - -/** - * @brief Disable memorization whether the daylight saving time change has been performed. - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR BKP LL_RTC_TIME_DisableDayLightStore - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_BKP); -} - -/** - * @brief Check if RTC Day Light Saving stored operation has been enabled or not - * @rmtoll CR BKP LL_RTC_TIME_IsDayLightStoreEnabled - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); -} - -/** - * @brief Subtract 1 hour (winter time change) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR SUB1H LL_RTC_TIME_DecHour - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_SUB1H); -} - -/** - * @brief Add 1 hour (summer time change) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ADD1H LL_RTC_TIME_IncHour - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_ADD1H); -} - -/** - * @brief Get subseconds value in the synchronous prescaler counter. - * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through - * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar - * SubSeconds value in second fraction ratio with time unit following - * generic formula: - * ==> Seconds fraction ratio * time_unit = - * [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit - * This conversion can be performed only if no shift operation is pending - * (ie. SHFP=0) when PREDIV_S >= SS. - * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond - * @param RTCx RTC Instance - * @retval Subseconds value (number between 0 and 65535) - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); -} - -/** - * @brief Synchronize to a remote clock with a high degree of precision. - * @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second. - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @rmtoll SHIFTR ADD1S LL_RTC_TIME_Synchronize\n - * SHIFTR SUBFS LL_RTC_TIME_Synchronize - * @param RTCx RTC Instance - * @param ShiftSecond This parameter can be one of the following values: - * @arg @ref LL_RTC_SHIFT_SECOND_DELAY - * @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE - * @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF) - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction) -{ - WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Date Date - * @{ - */ - -/** - * @brief Set Year in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format - * @rmtoll DR YT LL_RTC_DATE_SetYear\n - * DR YU LL_RTC_DATE_SetYear - * @param RTCx RTC Instance - * @param Year Value between Min_Data=0x00 and Max_Data=0x99 - * @retval None - */ -__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) -{ - MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU), - (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))); -} - -/** - * @brief Get Year in BCD format - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format - * @rmtoll DR YT LL_RTC_DATE_GetYear\n - * DR YU LL_RTC_DATE_GetYear - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x99 - */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); -} - -/** - * @brief Set Week day - * @rmtoll DR WDU LL_RTC_DATE_SetWeekDay - * @param RTCx RTC Instance - * @param WeekDay This parameter can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - * @retval None - */ -__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) -{ - MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos); -} - -/** - * @brief Get Week day - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); -} - -/** - * @brief Set Month in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format - * @rmtoll DR MT LL_RTC_DATE_SetMonth\n - * DR MU LL_RTC_DATE_SetMonth - * @param RTCx RTC Instance - * @param Month This parameter can be one of the following values: - * @arg @ref LL_RTC_MONTH_JANUARY - * @arg @ref LL_RTC_MONTH_FEBRUARY - * @arg @ref LL_RTC_MONTH_MARCH - * @arg @ref LL_RTC_MONTH_APRIL - * @arg @ref LL_RTC_MONTH_MAY - * @arg @ref LL_RTC_MONTH_JUNE - * @arg @ref LL_RTC_MONTH_JULY - * @arg @ref LL_RTC_MONTH_AUGUST - * @arg @ref LL_RTC_MONTH_SEPTEMBER - * @arg @ref LL_RTC_MONTH_OCTOBER - * @arg @ref LL_RTC_MONTH_NOVEMBER - * @arg @ref LL_RTC_MONTH_DECEMBER - * @retval None - */ -__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) -{ - MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU), - (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos))); -} - -/** - * @brief Get Month in BCD format - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format - * @rmtoll DR MT LL_RTC_DATE_GetMonth\n - * DR MU LL_RTC_DATE_GetMonth - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_MONTH_JANUARY - * @arg @ref LL_RTC_MONTH_FEBRUARY - * @arg @ref LL_RTC_MONTH_MARCH - * @arg @ref LL_RTC_MONTH_APRIL - * @arg @ref LL_RTC_MONTH_MAY - * @arg @ref LL_RTC_MONTH_JUNE - * @arg @ref LL_RTC_MONTH_JULY - * @arg @ref LL_RTC_MONTH_AUGUST - * @arg @ref LL_RTC_MONTH_SEPTEMBER - * @arg @ref LL_RTC_MONTH_OCTOBER - * @arg @ref LL_RTC_MONTH_NOVEMBER - * @arg @ref LL_RTC_MONTH_DECEMBER - */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); -} - -/** - * @brief Set Day in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll DR DT LL_RTC_DATE_SetDay\n - * DR DU LL_RTC_DATE_SetDay - * @param RTCx RTC Instance - * @param Day Value between Min_Data=0x01 and Max_Data=0x31 - * @retval None - */ -__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) -{ - MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU), - (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos))); -} - -/** - * @brief Get Day in BCD format - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll DR DT LL_RTC_DATE_GetDay\n - * DR DU LL_RTC_DATE_GetDay - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x01 and Max_Data=0x31 - */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); -} - -/** - * @brief Set date (WeekDay, Day, Month and Year) in BCD format - * @rmtoll DR WDU LL_RTC_DATE_Config\n - * DR MT LL_RTC_DATE_Config\n - * DR MU LL_RTC_DATE_Config\n - * DR DT LL_RTC_DATE_Config\n - * DR DU LL_RTC_DATE_Config\n - * DR YT LL_RTC_DATE_Config\n - * DR YU LL_RTC_DATE_Config - * @param RTCx RTC Instance - * @param WeekDay This parameter can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - * @param Day Value between Min_Data=0x01 and Max_Data=0x31 - * @param Month This parameter can be one of the following values: - * @arg @ref LL_RTC_MONTH_JANUARY - * @arg @ref LL_RTC_MONTH_FEBRUARY - * @arg @ref LL_RTC_MONTH_MARCH - * @arg @ref LL_RTC_MONTH_APRIL - * @arg @ref LL_RTC_MONTH_MAY - * @arg @ref LL_RTC_MONTH_JUNE - * @arg @ref LL_RTC_MONTH_JULY - * @arg @ref LL_RTC_MONTH_AUGUST - * @arg @ref LL_RTC_MONTH_SEPTEMBER - * @arg @ref LL_RTC_MONTH_OCTOBER - * @arg @ref LL_RTC_MONTH_NOVEMBER - * @arg @ref LL_RTC_MONTH_DECEMBER - * @param Year Value between Min_Data=0x00 and Max_Data=0x99 - * @retval None - */ -__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) -{ - uint32_t temp; - - temp = ( WeekDay << RTC_DR_WDU_Pos) | \ - (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ - (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ - (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); - - MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); -} - -/** - * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set - * before reading this bit - * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, - * and __LL_RTC_GET_DAY are available to get independently each parameter. - * @rmtoll DR WDU LL_RTC_DATE_Get\n - * DR MT LL_RTC_DATE_Get\n - * DR MU LL_RTC_DATE_Get\n - * DR DT LL_RTC_DATE_Get\n - * DR DU LL_RTC_DATE_Get\n - * DR YT LL_RTC_DATE_Get\n - * DR YU LL_RTC_DATE_Get - * @param RTCx RTC Instance - * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). - */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) -{ - uint32_t temp; - - temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); - - return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ - (((temp & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos) << RTC_OFFSET_DAY) | \ - (((temp & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos) << RTC_OFFSET_MONTH) | \ - ((temp & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_ALARMA ALARMA - * @{ - */ - -/** - * @brief Enable Alarm A - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAE LL_RTC_ALMA_Enable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_ALRAE); -} - -/** - * @brief Disable Alarm A - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAE LL_RTC_ALMA_Disable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE); -} - -/** - * @brief Specify the Alarm A masks. - * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK3 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK2 LL_RTC_ALMA_SetMask\n - * ALRMAR MSK1 LL_RTC_ALMA_SetMask - * @param RTCx RTC Instance - * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_ALMA_MASK_NONE - * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY - * @arg @ref LL_RTC_ALMA_MASK_HOURS - * @arg @ref LL_RTC_ALMA_MASK_MINUTES - * @arg @ref LL_RTC_ALMA_MASK_SECONDS - * @arg @ref LL_RTC_ALMA_MASK_ALL - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) -{ - MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask); -} - -/** - * @brief Get the Alarm A masks. - * @rmtoll ALRMAR MSK4 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK3 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK2 LL_RTC_ALMA_GetMask\n - * ALRMAR MSK1 LL_RTC_ALMA_GetMask - * @param RTCx RTC Instance - * @retval Returned value can be can be a combination of the following values: - * @arg @ref LL_RTC_ALMA_MASK_NONE - * @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY - * @arg @ref LL_RTC_ALMA_MASK_HOURS - * @arg @ref LL_RTC_ALMA_MASK_MINUTES - * @arg @ref LL_RTC_ALMA_MASK_SECONDS - * @arg @ref LL_RTC_ALMA_MASK_ALL - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); -} - -/** - * @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) - * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); -} - -/** - * @brief Disable AlarmA Week day selection (DU[3:0] represents the date ) - * @rmtoll ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL); -} - -/** - * @brief Set ALARM A Day in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll ALRMAR DT LL_RTC_ALMA_SetDay\n - * ALRMAR DU LL_RTC_ALMA_SetDay - * @param RTCx RTC Instance - * @param Day Value between Min_Data=0x01 and Max_Data=0x31 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) -{ - MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU), - (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos))); -} - -/** - * @brief Get ALARM A Day in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll ALRMAR DT LL_RTC_ALMA_GetDay\n - * ALRMAR DU LL_RTC_ALMA_GetDay - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x01 and Max_Data=0x31 - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); -} - -/** - * @brief Set ALARM A Weekday - * @rmtoll ALRMAR DU LL_RTC_ALMA_SetWeekDay - * @param RTCx RTC Instance - * @param WeekDay This parameter can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) -{ - MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos); -} - -/** - * @brief Get ALARM A Weekday - * @rmtoll ALRMAR DU LL_RTC_ALMA_GetWeekDay - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); -} - -/** - * @brief Set Alarm A time format (AM/24-hour or PM notation) - * @rmtoll ALRMAR PM LL_RTC_ALMA_SetTimeFormat - * @param RTCx RTC Instance - * @param TimeFormat This parameter can be one of the following values: - * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM - * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) -{ - MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat); -} - -/** - * @brief Get Alarm A time format (AM or PM notation) - * @rmtoll ALRMAR PM LL_RTC_ALMA_GetTimeFormat - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM - * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); -} - -/** - * @brief Set ALARM A Hours in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format - * @rmtoll ALRMAR HT LL_RTC_ALMA_SetHour\n - * ALRMAR HU LL_RTC_ALMA_SetHour - * @param RTCx RTC Instance - * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) -{ - MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU), - (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))); -} - -/** - * @brief Get ALARM A Hours in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll ALRMAR HT LL_RTC_ALMA_GetHour\n - * ALRMAR HU LL_RTC_ALMA_GetHour - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); -} - -/** - * @brief Set ALARM A Minutes in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll ALRMAR MNT LL_RTC_ALMA_SetMinute\n - * ALRMAR MNU LL_RTC_ALMA_SetMinute - * @param RTCx RTC Instance - * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) -{ - MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU), - (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos))); -} - -/** - * @brief Get ALARM A Minutes in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll ALRMAR MNT LL_RTC_ALMA_GetMinute\n - * ALRMAR MNU LL_RTC_ALMA_GetMinute - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x59 - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); -} - -/** - * @brief Set ALARM A Seconds in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll ALRMAR ST LL_RTC_ALMA_SetSecond\n - * ALRMAR SU LL_RTC_ALMA_SetSecond - * @param RTCx RTC Instance - * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) -{ - MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU), - (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos))); -} - -/** - * @brief Get ALARM A Seconds in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll ALRMAR ST LL_RTC_ALMA_GetSecond\n - * ALRMAR SU LL_RTC_ALMA_GetSecond - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x59 - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); -} - -/** - * @brief Set Alarm A Time (hour, minute and second) in BCD format - * @rmtoll ALRMAR PM LL_RTC_ALMA_ConfigTime\n - * ALRMAR HT LL_RTC_ALMA_ConfigTime\n - * ALRMAR HU LL_RTC_ALMA_ConfigTime\n - * ALRMAR MNT LL_RTC_ALMA_ConfigTime\n - * ALRMAR MNU LL_RTC_ALMA_ConfigTime\n - * ALRMAR ST LL_RTC_ALMA_ConfigTime\n - * ALRMAR SU LL_RTC_ALMA_ConfigTime - * @param RTCx RTC Instance - * @param Format12_24 This parameter can be one of the following values: - * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM - * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM - * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 - * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) -{ - uint32_t temp; - - temp = Format12_24 | \ - (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ - (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); - - MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); -} - -/** - * @brief Get Alarm B Time (hour, minute and second) in BCD format - * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND - * are available to get independently each parameter. - * @rmtoll ALRMAR HT LL_RTC_ALMA_GetTime\n - * ALRMAR HU LL_RTC_ALMA_GetTime\n - * ALRMAR MNT LL_RTC_ALMA_GetTime\n - * ALRMAR MNU LL_RTC_ALMA_GetTime\n - * ALRMAR ST LL_RTC_ALMA_GetTime\n - * ALRMAR SU LL_RTC_ALMA_GetTime - * @param RTCx RTC Instance - * @retval Combination of hours, minutes and seconds. - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) -{ - return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); -} - -/** - * @brief Mask the most-significant bits of the subseconds field starting from - * the bit specified in parameter Mask - * @note This register can be written only when ALRAE is reset in RTC_CR register, - * or in initialization mode. - * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask - * @param RTCx RTC Instance - * @param Mask Value between Min_Data=0x00 and Max_Data=0xF - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) -{ - MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos); -} - -/** - * @brief Get Alarm A subseconds mask - * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); -} - -/** - * @brief Set Alarm A subseconds value - * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond - * @param RTCx RTC Instance - * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) -{ - MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond); -} - -/** - * @brief Get Alarm A subseconds value - * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF - */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_ALARMB ALARMB - * @{ - */ - -/** - * @brief Enable Alarm B - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBE LL_RTC_ALMB_Enable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_ALRBE); -} - -/** - * @brief Disable Alarm B - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBE LL_RTC_ALMB_Disable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE); -} - -/** - * @brief Specify the Alarm B masks. - * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK3 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK2 LL_RTC_ALMB_SetMask\n - * ALRMBR MSK1 LL_RTC_ALMB_SetMask - * @param RTCx RTC Instance - * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_ALMB_MASK_NONE - * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY - * @arg @ref LL_RTC_ALMB_MASK_HOURS - * @arg @ref LL_RTC_ALMB_MASK_MINUTES - * @arg @ref LL_RTC_ALMB_MASK_SECONDS - * @arg @ref LL_RTC_ALMB_MASK_ALL - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) -{ - MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask); -} - -/** - * @brief Get the Alarm B masks. - * @rmtoll ALRMBR MSK4 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK3 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK2 LL_RTC_ALMB_GetMask\n - * ALRMBR MSK1 LL_RTC_ALMB_GetMask - * @param RTCx RTC Instance - * @retval Returned value can be can be a combination of the following values: - * @arg @ref LL_RTC_ALMB_MASK_NONE - * @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY - * @arg @ref LL_RTC_ALMB_MASK_HOURS - * @arg @ref LL_RTC_ALMB_MASK_MINUTES - * @arg @ref LL_RTC_ALMB_MASK_SECONDS - * @arg @ref LL_RTC_ALMB_MASK_ALL - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); -} - -/** - * @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care) - * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); -} - -/** - * @brief Disable AlarmB Week day selection (DU[3:0] represents the date ) - * @rmtoll ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL); -} - -/** - * @brief Set ALARM B Day in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format - * @rmtoll ALRMBR DT LL_RTC_ALMB_SetDay\n - * ALRMBR DU LL_RTC_ALMB_SetDay - * @param RTCx RTC Instance - * @param Day Value between Min_Data=0x01 and Max_Data=0x31 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) -{ - MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), - (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); -} - -/** - * @brief Get ALARM B Day in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll ALRMBR DT LL_RTC_ALMB_GetDay\n - * ALRMBR DU LL_RTC_ALMB_GetDay - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x01 and Max_Data=0x31 - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); -} - -/** - * @brief Set ALARM B Weekday - * @rmtoll ALRMBR DU LL_RTC_ALMB_SetWeekDay - * @param RTCx RTC Instance - * @param WeekDay This parameter can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) -{ - MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos); -} - -/** - * @brief Get ALARM B Weekday - * @rmtoll ALRMBR DU LL_RTC_ALMB_GetWeekDay - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); -} - -/** - * @brief Set ALARM B time format (AM/24-hour or PM notation) - * @rmtoll ALRMBR PM LL_RTC_ALMB_SetTimeFormat - * @param RTCx RTC Instance - * @param TimeFormat This parameter can be one of the following values: - * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM - * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat) -{ - MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat); -} - -/** - * @brief Get ALARM B time format (AM or PM notation) - * @rmtoll ALRMBR PM LL_RTC_ALMB_GetTimeFormat - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM - * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); -} - -/** - * @brief Set ALARM B Hours in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format - * @rmtoll ALRMBR HT LL_RTC_ALMB_SetHour\n - * ALRMBR HU LL_RTC_ALMB_SetHour - * @param RTCx RTC Instance - * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) -{ - MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU), - (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))); -} - -/** - * @brief Get ALARM B Hours in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll ALRMBR HT LL_RTC_ALMB_GetHour\n - * ALRMBR HU LL_RTC_ALMB_GetHour - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); -} - -/** - * @brief Set ALARM B Minutes in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format - * @rmtoll ALRMBR MNT LL_RTC_ALMB_SetMinute\n - * ALRMBR MNU LL_RTC_ALMB_SetMinute - * @param RTCx RTC Instance - * @param Minutes between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) -{ - MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU), - (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos))); -} - -/** - * @brief Get ALARM B Minutes in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll ALRMBR MNT LL_RTC_ALMB_GetMinute\n - * ALRMBR MNU LL_RTC_ALMB_GetMinute - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x59 - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); -} - -/** - * @brief Set ALARM B Seconds in BCD format - * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format - * @rmtoll ALRMBR ST LL_RTC_ALMB_SetSecond\n - * ALRMBR SU LL_RTC_ALMB_SetSecond - * @param RTCx RTC Instance - * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) -{ - MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU), - (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos))); -} - -/** - * @brief Get ALARM B Seconds in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll ALRMBR ST LL_RTC_ALMB_GetSecond\n - * ALRMBR SU LL_RTC_ALMB_GetSecond - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x59 - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) -{ - return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); -} - -/** - * @brief Set Alarm B Time (hour, minute and second) in BCD format - * @rmtoll ALRMBR PM LL_RTC_ALMB_ConfigTime\n - * ALRMBR HT LL_RTC_ALMB_ConfigTime\n - * ALRMBR HU LL_RTC_ALMB_ConfigTime\n - * ALRMBR MNT LL_RTC_ALMB_ConfigTime\n - * ALRMBR MNU LL_RTC_ALMB_ConfigTime\n - * ALRMBR ST LL_RTC_ALMB_ConfigTime\n - * ALRMBR SU LL_RTC_ALMB_ConfigTime - * @param RTCx RTC Instance - * @param Format12_24 This parameter can be one of the following values: - * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM - * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM - * @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - * @param Minutes Value between Min_Data=0x00 and Max_Data=0x59 - * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) -{ - uint32_t temp; - - temp = Format12_24 | \ - (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ - (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); - - MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); -} - -/** - * @brief Get Alarm B Time (hour, minute and second) in BCD format - * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND - * are available to get independently each parameter. - * @rmtoll ALRMBR HT LL_RTC_ALMB_GetTime\n - * ALRMBR HU LL_RTC_ALMB_GetTime\n - * ALRMBR MNT LL_RTC_ALMB_GetTime\n - * ALRMBR MNU LL_RTC_ALMB_GetTime\n - * ALRMBR ST LL_RTC_ALMB_GetTime\n - * ALRMBR SU LL_RTC_ALMB_GetTime - * @param RTCx RTC Instance - * @retval Combination of hours, minutes and seconds. - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) -{ - return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx)); -} - -/** - * @brief Mask the most-significant bits of the subseconds field starting from - * the bit specified in parameter Mask - * @note This register can be written only when ALRBE is reset in RTC_CR register, - * or in initialization mode. - * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask - * @param RTCx RTC Instance - * @param Mask Value between Min_Data=0x00 and Max_Data=0xF - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask) -{ - MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos); -} - -/** - * @brief Get Alarm B subseconds mask - * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); -} - -/** - * @brief Set Alarm B subseconds value - * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond - * @param RTCx RTC Instance - * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond) -{ - MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond); -} - -/** - * @brief Get Alarm B subseconds value - * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF - */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Timestamp Timestamp - * @{ - */ - -/** - * @brief Enable internal event timestamp - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ITSE LL_RTC_TS_EnableInternalEvent - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_ITSE); -} - -/** - * @brief Disable internal event timestamp - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ITSE LL_RTC_TS_DisableInternalEvent - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_ITSE); -} - -/** - * @brief Enable Timestamp - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSE LL_RTC_TS_Enable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_TSE); -} - -/** - * @brief Disable Timestamp - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSE LL_RTC_TS_Disable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_TSE); -} - -/** - * @brief Set Time-stamp event active edge - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting - * @rmtoll CR TSEDGE LL_RTC_TS_SetActiveEdge - * @param RTCx RTC Instance - * @param Edge This parameter can be one of the following values: - * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING - * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING - * @retval None - */ -__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) -{ - MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge); -} - -/** - * @brief Get Time-stamp event active edge - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSEDGE LL_RTC_TS_GetActiveEdge - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING - * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); -} - -/** - * @brief Get Timestamp AM/PM notation (AM or 24-hour format) - * @rmtoll TSTR PM LL_RTC_TS_GetTimeFormat - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_TS_TIME_FORMAT_AM - * @arg @ref LL_RTC_TS_TIME_FORMAT_PM - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); -} - -/** - * @brief Get Timestamp Hours in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format - * @rmtoll TSTR HT LL_RTC_TS_GetHour\n - * TSTR HU LL_RTC_TS_GetHour - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); -} - -/** - * @brief Get Timestamp Minutes in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format - * @rmtoll TSTR MNT LL_RTC_TS_GetMinute\n - * TSTR MNU LL_RTC_TS_GetMinute - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x59 - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); -} - -/** - * @brief Get Timestamp Seconds in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format - * @rmtoll TSTR ST LL_RTC_TS_GetSecond\n - * TSTR SU LL_RTC_TS_GetSecond - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x59 - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); -} - -/** - * @brief Get Timestamp time (hour, minute and second) in BCD format - * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND - * are available to get independently each parameter. - * @rmtoll TSTR HT LL_RTC_TS_GetTime\n - * TSTR HU LL_RTC_TS_GetTime\n - * TSTR MNT LL_RTC_TS_GetTime\n - * TSTR MNU LL_RTC_TS_GetTime\n - * TSTR ST LL_RTC_TS_GetTime\n - * TSTR SU LL_RTC_TS_GetTime - * @param RTCx RTC Instance - * @retval Combination of hours, minutes and seconds. - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSTR, - RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); -} - -/** - * @brief Get Timestamp Week day - * @rmtoll TSDR WDU LL_RTC_TS_GetWeekDay - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_WEEKDAY_MONDAY - * @arg @ref LL_RTC_WEEKDAY_TUESDAY - * @arg @ref LL_RTC_WEEKDAY_WEDNESDAY - * @arg @ref LL_RTC_WEEKDAY_THURSDAY - * @arg @ref LL_RTC_WEEKDAY_FRIDAY - * @arg @ref LL_RTC_WEEKDAY_SATURDAY - * @arg @ref LL_RTC_WEEKDAY_SUNDAY - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); -} - -/** - * @brief Get Timestamp Month in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format - * @rmtoll TSDR MT LL_RTC_TS_GetMonth\n - * TSDR MU LL_RTC_TS_GetMonth - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_MONTH_JANUARY - * @arg @ref LL_RTC_MONTH_FEBRUARY - * @arg @ref LL_RTC_MONTH_MARCH - * @arg @ref LL_RTC_MONTH_APRIL - * @arg @ref LL_RTC_MONTH_MAY - * @arg @ref LL_RTC_MONTH_JUNE - * @arg @ref LL_RTC_MONTH_JULY - * @arg @ref LL_RTC_MONTH_AUGUST - * @arg @ref LL_RTC_MONTH_SEPTEMBER - * @arg @ref LL_RTC_MONTH_OCTOBER - * @arg @ref LL_RTC_MONTH_NOVEMBER - * @arg @ref LL_RTC_MONTH_DECEMBER - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); -} - -/** - * @brief Get Timestamp Day in BCD format - * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format - * @rmtoll TSDR DT LL_RTC_TS_GetDay\n - * TSDR DU LL_RTC_TS_GetDay - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x01 and Max_Data=0x31 - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); -} - -/** - * @brief Get Timestamp date (WeekDay, Day and Month) in BCD format - * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH, - * and __LL_RTC_GET_DAY are available to get independently each parameter. - * @rmtoll TSDR WDU LL_RTC_TS_GetDate\n - * TSDR MT LL_RTC_TS_GetDate\n - * TSDR MU LL_RTC_TS_GetDate\n - * TSDR DT LL_RTC_TS_GetDate\n - * TSDR DU LL_RTC_TS_GetDate - * @param RTCx RTC Instance - * @retval Combination of Weekday, Day and Month - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); -} - -/** - * @brief Get time-stamp subseconds value - * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); -} - -#if defined(RTC_TAMPCR_TAMPTS) -/** - * @brief Activate timestamp on tamper detection event - * @rmtoll TAMPCR TAMPTS LL_RTC_TS_EnableOnTamper - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); -} - -/** - * @brief Disable timestamp on tamper detection event - * @rmtoll TAMPCR TAMPTS LL_RTC_TS_DisableOnTamper - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS); -} -#endif /* RTC_TAMPCR_TAMPTS */ - -/** - * @brief Set timestamp Pin - * @rmtoll TAMPCR TSINSEL LL_RTC_TS_SetPin - * @param RTCx RTC Instance - * @param TSPin specifies the RTC Timestamp Pin. - * This parameter can be one of the following values: - * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC Timestamp Pin. - * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is used as RTC Timestamp Pin. - * @retval None - */ -__STATIC_INLINE void LL_RTC_TS_SetPin(RTC_TypeDef *RTCx, uint32_t TSPin) -{ - MODIFY_REG(RTCx->OR, RTC_OR_TSINSEL, TSPin); -} - -/** - * @brief Get timestamp Pin - * @rmtoll TAMPCR TSINSEL LL_RTC_TS_GetPin - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC Timestamp Pin. - * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is used as RTC Timestamp Pin. - * @retval None - */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetPin(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_TSINSEL)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Tamper Tamper - * @{ - */ - -/** - * @brief Enable RTC_TAMPx input detection - * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Enable\n - * TAMPCR TAMP2E LL_RTC_TAMPER_Enable\n - * TAMPCR TAMP3E LL_RTC_TAMPER_Enable - * @param RTCx RTC Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 - * @arg @ref LL_RTC_TAMPER_3 - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) -{ - SET_BIT(RTCx->TAMPCR, Tamper); -} - -/** - * @brief Clear RTC_TAMPx input detection - * @rmtoll TAMPCR TAMP1E LL_RTC_TAMPER_Disable\n - * TAMPCR TAMP2E LL_RTC_TAMPER_Disable\n - * TAMPCR TAMP3E LL_RTC_TAMPER_Disable - * @param RTCx RTC Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 - * @arg @ref LL_RTC_TAMPER_2 - * @arg @ref LL_RTC_TAMPER_3 - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) -{ - CLEAR_BIT(RTCx->TAMPCR, Tamper); -} - -/** - * @brief Enable Tamper mask flag - * @note Associated Tamper IT must not enabled when tamper mask is set. - * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_EnableMask\n - * TAMPCR TAMP2MF LL_RTC_TAMPER_EnableMask\n - * TAMPCR TAMP3MF LL_RTC_TAMPER_EnableMask - * @param RTCx RTC Instance - * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) -{ - SET_BIT(RTCx->TAMPCR, Mask); -} - -/** - * @brief Disable Tamper mask flag - * @rmtoll TAMPCR TAMP1MF LL_RTC_TAMPER_DisableMask\n - * TAMPCR TAMP2MF LL_RTC_TAMPER_DisableMask\n - * TAMPCR TAMP3MF LL_RTC_TAMPER_DisableMask - * @param RTCx RTC Instance - * @param Mask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER1 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER2 - * @arg @ref LL_RTC_TAMPER_MASK_TAMPER3 - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) -{ - CLEAR_BIT(RTCx->TAMPCR, Mask); -} - -/** - * @brief Enable backup register erase after Tamper event detection - * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n - * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_EnableEraseBKP\n - * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_EnableEraseBKP - * @param RTCx RTC Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) -{ - CLEAR_BIT(RTCx->TAMPCR, Tamper); -} - -/** - * @brief Disable backup register erase after Tamper event detection - * @rmtoll TAMPCR TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n - * TAMPCR TAMP2NOERASE LL_RTC_TAMPER_DisableEraseBKP\n - * TAMPCR TAMP3NOERASE LL_RTC_TAMPER_DisableEraseBKP - * @param RTCx RTC Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2 - * @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3 - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) -{ - SET_BIT(RTCx->TAMPCR, Tamper); -} - -/** - * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) - * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); -} - -/** - * @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling) - * @rmtoll TAMPCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS); -} - -/** - * @brief Set RTC_TAMPx precharge duration - * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge - * @param RTCx RTC Instance - * @param Duration This parameter can be one of the following values: - * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK - * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK - * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK - * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration) -{ - MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration); -} - -/** - * @brief Get RTC_TAMPx precharge duration - * @rmtoll TAMPCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK - * @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK - * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK - * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK - */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH)); -} - -/** - * @brief Set RTC_TAMPx filter count - * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_SetFilterCount - * @param RTCx RTC Instance - * @param FilterCount This parameter can be one of the following values: - * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE - * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE - * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE - * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount) -{ - MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount); -} - -/** - * @brief Get RTC_TAMPx filter count - * @rmtoll TAMPCR TAMPFLT LL_RTC_TAMPER_GetFilterCount - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_TAMPER_FILTER_DISABLE - * @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE - * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE - * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE - */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT)); -} - -/** - * @brief Set Tamper sampling frequency - * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq - * @param RTCx RTC Instance - * @param SamplingFreq This parameter can be one of the following values: - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq) -{ - MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq); -} - -/** - * @brief Get Tamper sampling frequency - * @rmtoll TAMPCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 - * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 - */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ)); -} - -/** - * @brief Enable Active level for Tamper input - * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n - * TAMPCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n - * TAMPCR TAMP3TRG LL_RTC_TAMPER_EnableActiveLevel - * @param RTCx RTC Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) -{ - SET_BIT(RTCx->TAMPCR, Tamper); -} - -/** - * @brief Disable Active level for Tamper input - * @rmtoll TAMPCR TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n - * TAMPCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n - * TAMPCR TAMP3TRG LL_RTC_TAMPER_DisableActiveLevel - * @param RTCx RTC Instance - * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) -{ - CLEAR_BIT(RTCx->TAMPCR, Tamper); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Wakeup Wakeup - * @{ - */ - -/** - * @brief Enable Wakeup timer - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTE LL_RTC_WAKEUP_Enable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_WUTE); -} - -/** - * @brief Disable Wakeup timer - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTE LL_RTC_WAKEUP_Disable - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_WUTE); -} - -/** - * @brief Check if Wakeup timer is enabled or not - * @rmtoll CR WUTE LL_RTC_WAKEUP_IsEnabled - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); -} - -/** - * @brief Select Wakeup clock - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 - * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock - * @param RTCx RTC Instance - * @param WakeupClock This parameter can be one of the following values: - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock) -{ - MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock); -} - -/** - * @brief Get Wakeup clock - * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_GetClock - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4 - * @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2 - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE - * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); -} - -/** - * @brief Set Wakeup auto-reload value - * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR - * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload - * @param RTCx RTC Instance - * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value) -{ - MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value); -} - -/** - * @brief Get Wakeup auto-reload value - * @rmtoll WUTR WUT LL_RTC_WAKEUP_GetAutoReload - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @rmtoll BKPxR BKP LL_RTC_BAK_SetRegister - * @param RTCx RTC Instance - * @param BackupRegister This parameter can be one of the following values: - * @arg @ref LL_RTC_BKP_DR0 - * @arg @ref LL_RTC_BKP_DR1 - * @arg @ref LL_RTC_BKP_DR2 - * @arg @ref LL_RTC_BKP_DR3 - * @arg @ref LL_RTC_BKP_DR4 - * @arg @ref LL_RTC_BKP_DR5 - * @arg @ref LL_RTC_BKP_DR6 - * @arg @ref LL_RTC_BKP_DR7 - * @arg @ref LL_RTC_BKP_DR8 - * @arg @ref LL_RTC_BKP_DR9 - * @arg @ref LL_RTC_BKP_DR10 - * @arg @ref LL_RTC_BKP_DR11 - * @arg @ref LL_RTC_BKP_DR12 - * @arg @ref LL_RTC_BKP_DR13 - * @arg @ref LL_RTC_BKP_DR14 - * @arg @ref LL_RTC_BKP_DR15 - * @arg @ref LL_RTC_BKP_DR16 - * @arg @ref LL_RTC_BKP_DR17 - * @arg @ref LL_RTC_BKP_DR18 - * @arg @ref LL_RTC_BKP_DR19 - * @arg @ref LL_RTC_BKP_DR20 - * @arg @ref LL_RTC_BKP_DR21 - * @arg @ref LL_RTC_BKP_DR22 - * @arg @ref LL_RTC_BKP_DR23 - * @arg @ref LL_RTC_BKP_DR24 - * @arg @ref LL_RTC_BKP_DR25 - * @arg @ref LL_RTC_BKP_DR26 - * @arg @ref LL_RTC_BKP_DR27 - * @arg @ref LL_RTC_BKP_DR28 - * @arg @ref LL_RTC_BKP_DR29 - * @arg @ref LL_RTC_BKP_DR30 - * @arg @ref LL_RTC_BKP_DR31 - * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t temp; - - temp = (uint32_t)(&(RTCx->BKP0R)); - temp += (BackupRegister * 4U); - - /* Write the specified register */ - *(__IO uint32_t *)temp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @rmtoll BKPxR BKP LL_RTC_BAK_GetRegister - * @param RTCx RTC Instance - * @param BackupRegister This parameter can be one of the following values: - * @arg @ref LL_RTC_BKP_DR0 - * @arg @ref LL_RTC_BKP_DR1 - * @arg @ref LL_RTC_BKP_DR2 - * @arg @ref LL_RTC_BKP_DR3 - * @arg @ref LL_RTC_BKP_DR4 - * @arg @ref LL_RTC_BKP_DR5 - * @arg @ref LL_RTC_BKP_DR6 - * @arg @ref LL_RTC_BKP_DR7 - * @arg @ref LL_RTC_BKP_DR8 - * @arg @ref LL_RTC_BKP_DR9 - * @arg @ref LL_RTC_BKP_DR10 - * @arg @ref LL_RTC_BKP_DR11 - * @arg @ref LL_RTC_BKP_DR12 - * @arg @ref LL_RTC_BKP_DR13 - * @arg @ref LL_RTC_BKP_DR14 - * @arg @ref LL_RTC_BKP_DR15 - * @arg @ref LL_RTC_BKP_DR16 - * @arg @ref LL_RTC_BKP_DR17 - * @arg @ref LL_RTC_BKP_DR18 - * @arg @ref LL_RTC_BKP_DR19 - * @arg @ref LL_RTC_BKP_DR20 - * @arg @ref LL_RTC_BKP_DR21 - * @arg @ref LL_RTC_BKP_DR22 - * @arg @ref LL_RTC_BKP_DR23 - * @arg @ref LL_RTC_BKP_DR24 - * @arg @ref LL_RTC_BKP_DR25 - * @arg @ref LL_RTC_BKP_DR26 - * @arg @ref LL_RTC_BKP_DR27 - * @arg @ref LL_RTC_BKP_DR28 - * @arg @ref LL_RTC_BKP_DR29 - * @arg @ref LL_RTC_BKP_DR30 - * @arg @ref LL_RTC_BKP_DR31 - * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) -{ - uint32_t temp; - - temp = (uint32_t)(&(RTCx->BKP0R)); - temp += (BackupRegister * 4U); - - /* Read the specified register */ - return (*(__IO uint32_t *)temp); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Calibration Calibration - * @{ - */ - -/** - * @brief Set Calibration output frequency (1 Hz or 512 Hz) - * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR COE LL_RTC_CAL_SetOutputFreq\n - * CR COSEL LL_RTC_CAL_SetOutputFreq - * @param RTCx RTC Instance - * @param Frequency This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ - * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ - * - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) -{ - MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency); -} - -/** - * @brief Get Calibration output frequency (1 Hz or 512 Hz) - * @rmtoll CR COE LL_RTC_CAL_GetOutputFreq\n - * CR COSEL LL_RTC_CAL_GetOutputFreq - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ - * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ - * - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); -} - -/** - * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALP LL_RTC_CAL_SetPulse - * @param RTCx RTC Instance - * @param Pulse This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE - * @arg @ref LL_RTC_CALIB_INSERTPULSE_SET - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse); -} - -/** - * @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm) - * @rmtoll CALR CALP LL_RTC_CAL_IsPulseInserted - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); -} - -/** - * @brief Set smooth calibration cycle period - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n - * CALR CALW16 LL_RTC_CAL_SetPeriod - * @param RTCx RTC Instance - * @param Period This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_PERIOD_32SEC - * @arg @ref LL_RTC_CALIB_PERIOD_16SEC - * @arg @ref LL_RTC_CALIB_PERIOD_8SEC - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period); -} - -/** - * @brief Get smooth calibration cycle period - * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n - * CALR CALW16 LL_RTC_CAL_GetPeriod - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_CALIB_PERIOD_32SEC - * @arg @ref LL_RTC_CALIB_PERIOD_16SEC - * @arg @ref LL_RTC_CALIB_PERIOD_8SEC - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); -} - -/** - * @brief Set smooth Calibration minus - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR - * @rmtoll CALR CALM LL_RTC_CAL_SetMinus - * @param RTCx RTC Instance - * @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) -{ - MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus); -} - -/** - * @brief Get smooth Calibration minus - * @rmtoll CALR CALM LL_RTC_CAL_GetMinus - * @param RTCx RTC Instance - * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Internal Time-stamp flag - * @rmtoll ISR ITSF LL_RTC_IsActiveFlag_ITS - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL); -} - -/** - * @brief Get Recalibration pending Flag - * @rmtoll ISR RECALPF LL_RTC_IsActiveFlag_RECALP - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL); -} - -/** - * @brief Get RTC_TAMP3 detection flag - * @rmtoll ISR TAMP3F LL_RTC_IsActiveFlag_TAMP3 - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL); -} - -/** - * @brief Get RTC_TAMP2 detection flag - * @rmtoll ISR TAMP2F LL_RTC_IsActiveFlag_TAMP2 - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL); -} - -/** - * @brief Get RTC_TAMP1 detection flag - * @rmtoll ISR TAMP1F LL_RTC_IsActiveFlag_TAMP1 - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL); -} - -/** - * @brief Get Time-stamp overflow flag - * @rmtoll ISR TSOVF LL_RTC_IsActiveFlag_TSOV - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL); -} - -/** - * @brief Get Time-stamp flag - * @rmtoll ISR TSF LL_RTC_IsActiveFlag_TS - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL); -} - -/** - * @brief Get Wakeup timer flag - * @rmtoll ISR WUTF LL_RTC_IsActiveFlag_WUT - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL); -} - -/** - * @brief Get Alarm B flag - * @rmtoll ISR ALRBF LL_RTC_IsActiveFlag_ALRB - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL); -} - -/** - * @brief Get Alarm A flag - * @rmtoll ISR ALRAF LL_RTC_IsActiveFlag_ALRA - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL); -} - -/** - * @brief Clear Internal Time-stamp flag - * @rmtoll ISR ITSF LL_RTC_ClearFlag_ITS - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Clear RTC_TAMP3 detection flag - * @rmtoll ISR TAMP3F LL_RTC_ClearFlag_TAMP3 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Clear RTC_TAMP2 detection flag - * @rmtoll ISR TAMP2F LL_RTC_ClearFlag_TAMP2 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Clear RTC_TAMP1 detection flag - * @rmtoll ISR TAMP1F LL_RTC_ClearFlag_TAMP1 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Clear Time-stamp overflow flag - * @rmtoll ISR TSOVF LL_RTC_ClearFlag_TSOV - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Clear Time-stamp flag - * @rmtoll ISR TSF LL_RTC_ClearFlag_TS - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Clear Wakeup timer flag - * @rmtoll ISR WUTF LL_RTC_ClearFlag_WUT - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Clear Alarm B flag - * @rmtoll ISR ALRBF LL_RTC_ClearFlag_ALRB - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Clear Alarm A flag - * @rmtoll ISR ALRAF LL_RTC_ClearFlag_ALRA - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Get Initialization flag - * @rmtoll ISR INITF LL_RTC_IsActiveFlag_INIT - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL); -} - -/** - * @brief Get Registers synchronization flag - * @rmtoll ISR RSF LL_RTC_IsActiveFlag_RS - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL); -} - -/** - * @brief Clear Registers synchronization flag - * @rmtoll ISR RSF LL_RTC_ClearFlag_RS - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) -{ - WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT))); -} - -/** - * @brief Get Initialization status flag - * @rmtoll ISR INITS LL_RTC_IsActiveFlag_INITS - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL); -} - -/** - * @brief Get Shift operation pending flag - * @rmtoll ISR SHPF LL_RTC_IsActiveFlag_SHP - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL); -} - -/** - * @brief Get Wakeup timer write flag - * @rmtoll ISR WUTWF LL_RTC_IsActiveFlag_WUTW - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL); -} - -/** - * @brief Get Alarm B write flag - * @rmtoll ISR ALRBWF LL_RTC_IsActiveFlag_ALRBW - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL); -} - -/** - * @brief Get Alarm A write flag - * @rmtoll ISR ALRAWF LL_RTC_IsActiveFlag_ALRAW - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable Time-stamp interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSIE LL_RTC_EnableIT_TS - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_TSIE); -} - -/** - * @brief Disable Time-stamp interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR TSIE LL_RTC_DisableIT_TS - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_TSIE); -} - -/** - * @brief Enable Wakeup timer interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTIE LL_RTC_EnableIT_WUT - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_WUTIE); -} - -/** - * @brief Disable Wakeup timer interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR WUTIE LL_RTC_DisableIT_WUT - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE); -} - -/** - * @brief Enable Alarm B interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBIE LL_RTC_EnableIT_ALRB - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_ALRBIE); -} - -/** - * @brief Disable Alarm B interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRBIE LL_RTC_DisableIT_ALRB - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE); -} - -/** - * @brief Enable Alarm A interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAIE LL_RTC_EnableIT_ALRA - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CR, RTC_CR_ALRAIE); -} - -/** - * @brief Disable Alarm A interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CR ALRAIE LL_RTC_DisableIT_ALRA - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE); -} - -/** - * @brief Enable Tamper 3 interrupt - * @rmtoll TAMPCR TAMP3IE LL_RTC_EnableIT_TAMP3 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); -} - -/** - * @brief Disable Tamper 3 interrupt - * @rmtoll TAMPCR TAMP3IE LL_RTC_DisableIT_TAMP3 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE); -} - -/** - * @brief Enable Tamper 2 interrupt - * @rmtoll TAMPCR TAMP2IE LL_RTC_EnableIT_TAMP2 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); -} - -/** - * @brief Disable Tamper 2 interrupt - * @rmtoll TAMPCR TAMP2IE LL_RTC_DisableIT_TAMP2 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE); -} - -/** - * @brief Enable Tamper 1 interrupt - * @rmtoll TAMPCR TAMP1IE LL_RTC_EnableIT_TAMP1 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); -} - -/** - * @brief Disable Tamper 1 interrupt - * @rmtoll TAMPCR TAMP1IE LL_RTC_DisableIT_TAMP1 - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE); -} - -/** - * @brief Enable all Tamper Interrupt - * @rmtoll TAMPCR TAMPIE LL_RTC_EnableIT_TAMP - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE); -} - -/** - * @brief Disable all Tamper Interrupt - * @rmtoll TAMPCR TAMPIE LL_RTC_DisableIT_TAMP - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE); -} - -/** - * @brief Check if Time-stamp interrupt is enabled or not - * @rmtoll CR TSIE LL_RTC_IsEnabledIT_TS - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Wakeup timer interrupt is enabled or not - * @rmtoll CR WUTIE LL_RTC_IsEnabledIT_WUT - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Alarm B interrupt is enabled or not - * @rmtoll CR ALRBIE LL_RTC_IsEnabledIT_ALRB - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Alarm A interrupt is enabled or not - * @rmtoll CR ALRAIE LL_RTC_IsEnabledIT_ALRA - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Tamper 3 interrupt is enabled or not - * @rmtoll TAMPCR TAMP3IE LL_RTC_IsEnabledIT_TAMP3 - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->TAMPCR, - RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Tamper 2 interrupt is enabled or not - * @rmtoll TAMPCR TAMP2IE LL_RTC_IsEnabledIT_TAMP2 - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->TAMPCR, - RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL); - -} - -/** - * @brief Check if Tamper 1 interrupt is enabled or not - * @rmtoll TAMPCR TAMP1IE LL_RTC_IsEnabledIT_TAMP1 - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->TAMPCR, - RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL); -} - -/** - * @brief Check if all the TAMPER interrupts are enabled or not - * @rmtoll TAMPCR TAMPIE LL_RTC_IsEnabledIT_TAMP - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) -{ - return ((READ_BIT(RTCx->TAMPCR, - RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); -void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); -ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); -void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); -ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct); -void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct); -ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); -ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); -void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); -void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); -ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RTC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_RTC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h index 4122a813..f6641bfb 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_sdmmc.h @@ -1,1036 +1,1040 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_sdmmc.h - * @author MCD Application Team - * @brief Header file of SDMMC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_SDMMC_H -#define STM32F7xx_LL_SDMMC_H - -#ifdef __cplusplus - extern "C" { -#endif - -#if defined(SDMMC1) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -/** @addtogroup STM32F7xx_Driver - * @{ - */ - -/** @addtogroup SDMMC_LL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types - * @{ - */ - -/** - * @brief SDMMC Configuration Structure definition - */ -typedef struct -{ - uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ - - uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is - enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ - - uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or - disabled when the bus is idle. - This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ - - uint32_t BusWide; /*!< Specifies the SDMMC bus width. - This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ - - uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ - - uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ - -}SDMMC_InitTypeDef; - - -/** - * @brief SDMMC Command Control structure - */ -typedef struct -{ - uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent - to a card as part of a command message. If a command - contains an argument, it must be loaded into this register - before writing the command to the command register. */ - - uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and - Max_Data = 64 */ - - uint32_t Response; /*!< Specifies the SDMMC response type. - This parameter can be a value of @ref SDMMC_LL_Response_Type */ - - uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is - enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ - - uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) - is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_CPSM_State */ -}SDMMC_CmdInitTypeDef; - - -/** - * @brief SDMMC Data Control structure - */ -typedef struct -{ - uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ - - uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ - - uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. - This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ - - uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer - is a read or write. - This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ - - uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. - This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ - - uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) - is enabled or disabled. - This parameter can be a value of @ref SDMMC_LL_DPSM_State */ -}SDMMC_DataInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants - * @{ - */ -#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ -#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ -#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ -#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ -#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ -#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ -#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ -#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ -#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the - number of transferred bytes does not match the block length */ -#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ -#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ -#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ -#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock - command or if there was an attempt to access a locked card */ -#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ -#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ -#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ -#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ -#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ -#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ -#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ -#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ -#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ -#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ -#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out - of erase sequence command was received */ -#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ -#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ -#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ -#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ -#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ -#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ -#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ -#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ -#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ - -/** - * @brief SDMMC Commands Index - */ -#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ -#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ -#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its - operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information - and asks the card whether card supports voltage. */ -#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ -#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ -#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ -#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ -#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands - (read, write, lock). Default block length is fixed to 512 Bytes. Not effective - for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by - STOP_TRANSMISSION command. */ -#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ -#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of - fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ -#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ -#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ -#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ -#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ -#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command - system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. - Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ -#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by - the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather - than a standard command. */ -#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card - for general purpose/application specific commands. */ -#define SDMMC_CMD_NO_CMD 64U /*!< No command */ - -/** - * @brief Following commands are SD Card Specific commands. - * SDMMC_APP_CMD should be sent before sending these commands. - */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus - widths are given in SCR register. */ -#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with - 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to - send its operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ -#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ -#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ -#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SDMMC_CMD_APP_CMD should be sent before sending these commands. - */ -#define SDMMC_CMD_SD_APP_GET_MKB 43U -#define SDMMC_CMD_SD_APP_GET_MID 44U -#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U -#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U -#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U -#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U -#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U -#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U -#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U - -/** - * @brief Masks for errors Card Status R1 (OCR Register) - */ -#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U -#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U -#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U -#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U -#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U -#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U -#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U -#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U -#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U -#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U -#define SDMMC_OCR_CC_ERROR 0x00100000U -#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U -#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U -#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U -#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U -#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U -#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U -#define SDMMC_OCR_ERASE_RESET 0x00002000U -#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U -#define SDMMC_OCR_ERRORBITS 0xFDFFE008U - -/** - * @brief Masks for R6 Response - */ -#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U -#define SDMMC_R6_ILLEGAL_CMD 0x00004000U -#define SDMMC_R6_COM_CRC_FAILED 0x00008000U - -#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U -#define SDMMC_HIGH_CAPACITY 0x40000000U -#define SDMMC_STD_CAPACITY 0x00000000U -#define SDMMC_CHECK_PATTERN 0x000001AAU -#define SD_SWITCH_1_8V_CAPACITY 0x01000000U - -#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU - -#define SDMMC_MAX_TRIAL 0x0000FFFFU - -#define SDMMC_ALLZERO 0x00000000U - -#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U -#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U -#define SDMMC_CARD_LOCKED 0x02000000U - -#ifndef SDMMC_DATATIMEOUT -#define SDMMC_DATATIMEOUT 0xFFFFFFFFU -#endif /* SDMMC_DATATIMEOUT */ - -#define SDMMC_0TO7BITS 0x000000FFU -#define SDMMC_8TO15BITS 0x0000FF00U -#define SDMMC_16TO23BITS 0x00FF0000U -#define SDMMC_24TO31BITS 0xFF000000U -#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU - -#define SDMMC_HALFFIFO 0x00000008U -#define SDMMC_HALFFIFOBYTES 0x00000020U - -/** - * @brief Command Class supported - */ -#define SDMMC_CCCC_ERASE 0x00000020U - -#define SDMMC_CMDTIMEOUT 5000U /* Command send and response timeout */ -#define SDMMC_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ -#define SDMMC_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ - -/** @defgroup SDMMC_LL_Clock_Edge Clock Edge - * @{ - */ -#define SDMMC_CLOCK_EDGE_RISING 0x00000000U -#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE - -#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ - ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass - * @{ - */ -#define SDMMC_CLOCK_BYPASS_DISABLE 0x00000000U -#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS - -#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ - ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving - * @{ - */ -#define SDMMC_CLOCK_POWER_SAVE_DISABLE 0x00000000U -#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV - -#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ - ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Bus_Wide Bus Width - * @{ - */ -#define SDMMC_BUS_WIDE_1B 0x00000000U -#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 -#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 - -#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ - ((WIDE) == SDMMC_BUS_WIDE_4B) || \ - ((WIDE) == SDMMC_BUS_WIDE_8B)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control - * @{ - */ -#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U -#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN - -#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ - ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Clock_Division Clock Division - * @{ - */ -#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Command_Index Command Index - * @{ - */ -#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Response_Type Response Type - * @{ - */ -#define SDMMC_RESPONSE_NO 0x00000000U -#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 -#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP - -#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ - ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ - ((RESPONSE) == SDMMC_RESPONSE_LONG)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt - * @{ - */ -#define SDMMC_WAIT_NO 0x00000000U -#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT -#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND - -#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ - ((WAIT) == SDMMC_WAIT_IT) || \ - ((WAIT) == SDMMC_WAIT_PEND)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_CPSM_State CPSM State - * @{ - */ -#define SDMMC_CPSM_DISABLE 0x00000000U -#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN - -#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ - ((CPSM) == SDMMC_CPSM_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Response_Registers Response Register - * @{ - */ -#define SDMMC_RESP1 0x00000000U -#define SDMMC_RESP2 0x00000004U -#define SDMMC_RESP3 0x00000008U -#define SDMMC_RESP4 0x0000000CU - -#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ - ((RESP) == SDMMC_RESP2) || \ - ((RESP) == SDMMC_RESP3) || \ - ((RESP) == SDMMC_RESP4)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Data_Length Data Length - * @{ - */ -#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size - * @{ - */ -#define SDMMC_DATABLOCK_SIZE_1B 0x00000000U -#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 -#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 -#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) -#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 -#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) -#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) -#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) -#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 -#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) -#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) - -#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ - ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction - * @{ - */ -#define SDMMC_TRANSFER_DIR_TO_CARD 0x00000000U -#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR - -#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ - ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Transfer_Type Transfer Type - * @{ - */ -#define SDMMC_TRANSFER_MODE_BLOCK 0x00000000U -#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE - -#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ - ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_DPSM_State DPSM State - * @{ - */ -#define SDMMC_DPSM_DISABLE 0x00000000U -#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN - -#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ - ((DPSM) == SDMMC_DPSM_ENABLE)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode - * @{ - */ -#define SDMMC_READ_WAIT_MODE_DATA2 0x00000000U -#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) - -#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ - ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) -/** - * @} - */ - -/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources - * @{ - */ -#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE -#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE -#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE -#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE -#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE -#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE -#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE -#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE -#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE -#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE -#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE -#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE -#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE -#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE -#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE -#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE -#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE -#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE -#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE -#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE -#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE -#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE -/** - * @} - */ - -/** @defgroup SDMMC_LL_Flags Flags - * @{ - */ -#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL -#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL -#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT -#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT -#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR -#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR -#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND -#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT -#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND -#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND -#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT -#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT -#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT -#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE -#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF -#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF -#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF -#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE -#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE -#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL -#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL -#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT -#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ - SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ - SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ - SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) - -#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ - SDMMC_FLAG_CMDSENT)) - -#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ - SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros - * @{ - */ - -/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions - * @brief SDMMC_LL registers bit address in the alias region - * @{ - */ -/* ---------------------- SDMMC registers bit mask --------------------------- */ -/* --- CLKCR Register ---*/ -/* CLKCR register clear mask */ -#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ - SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ - SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) - -/* --- DCTRL Register ---*/ -/* SDMMC DCTRL Clear Mask */ -#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ - SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) - -/* --- CMD Register ---*/ -/* CMD Register clear mask */ -#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ - SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ - SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) - -/* SDMMC Initialization Frequency (400KHz max) */ -#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ - -/* SDMMC Data Transfer Frequency (25MHz max) */ -#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ -/** - * @} - */ - -/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ - -/** - * @brief Enable the SDMMC device. - * @param __INSTANCE__: SDMMC Instance - * @retval None - */ -#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) - -/** - * @brief Disable the SDMMC device. - * @param __INSTANCE__: SDMMC Instance - * @retval None - */ -#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) - -/** - * @brief Enable the SDMMC DMA transfer. - * @param __INSTANCE__: SDMMC Instance - * @retval None - */ -#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) - -/** - * @brief Disable the SDMMC DMA transfer. - * @param __INSTANCE__: SDMMC Instance - * @retval None - */ -#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) - -/** - * @brief Enable the SDMMC device interrupt. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt - * @retval None - */ -#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) - -/** - * @brief Disable the SDMMC device interrupt. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt - * @retval None - */ -#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) - -/** - * @brief Checks whether the specified SDMMC flag is set or not. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_CMDACT: Command transfer in progress - * @arg SDMMC_FLAG_TXACT: Data transmit in progress - * @arg SDMMC_FLAG_RXACT: Data receive in progress - * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty - * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full - * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full - * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full - * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty - * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty - * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO - * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO - * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received - * @retval The new state of SDMMC_FLAG (SET or RESET). - */ -#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) - - -/** - * @brief Clears the SDMMC pending flags. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) - * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) - * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout - * @arg SDMMC_FLAG_DTIMEOUT: Data timeout - * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error - * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error - * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) - * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) - * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) - * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) - * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received - * @retval None - */ -#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) - -/** - * @brief Checks whether the specified SDMMC interrupt has occurred or not. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. - * This parameter can be one of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt - * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt - * @arg SDMMC_IT_RXACT: Data receive in progress interrupt - * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt - * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt - * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt - * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt - * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt - * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt - * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt - * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt - * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt - * @retval The new state of SDMMC_IT (SET or RESET). - */ -#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Clears the SDMMC's interrupt pending bits. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be one or a combination of the following values: - * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt - * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt - * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt - * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt - * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt - * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt - * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt - * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt - * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt - * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt - * @retval None - */ -#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) - -/** - * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @retval None - */ -#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) - -/** - * @brief Disable Start the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @retval None - */ -#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) - -/** - * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @retval None - */ -#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) - -/** - * @brief Disable Stop the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @retval None - */ -#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) - -/** - * @brief Enable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @retval None - */ -#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) - -/** - * @brief Disable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @retval None - */ -#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) - -/** - * @brief Enable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @retval None - */ -#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) - -/** - * @brief Disable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @retval None - */ -#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SDMMC_LL_Exported_Functions - * @{ - */ - -/* Initialization/de-initialization functions **********************************/ -/** @addtogroup HAL_SDMMC_LL_Group1 - * @{ - */ -HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); -/** - * @} - */ - -/* I/O operation functions *****************************************************/ -/** @addtogroup HAL_SDMMC_LL_Group2 - * @{ - */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); -HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); -/** - * @} - */ - -/* Peripheral Control functions ************************************************/ -/** @addtogroup HAL_SDMMC_LL_Group3 - * @{ - */ -HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); -HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); - -/* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); - -/* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); - -/* SDMMC Cards mode management functions */ -HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); -/** - * @} - */ - -/* SDMMC Commands management functions */ -/** @addtogroup HAL_SDMMC_LL_Group4 - * @{ - */ -uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); -uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); -uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); -uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); -uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); -uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); -uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); -uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); -uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); -uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); -uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); -uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); -uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); -uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); -uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); -uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); -uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); -uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); -uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); -uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); -/** - * @} - */ - -/* SDMMC Responses management functions *****************************************/ -/** @addtogroup HAL_SDMMC_LL_Group5 - * @{ - */ -uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); -uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); -uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); -uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* SDMMC1 */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_SDMMC_H */ +/** + ****************************************************************************** + * @file stm32f7xx_ll_sdmmc.h + * @author MCD Application Team + * @brief Header file of SDMMC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_LL_SDMMC_H +#define STM32F7xx_LL_SDMMC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(SDMMC1) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +/** @addtogroup STM32F7xx_Driver + * @{ + */ + +/** @addtogroup SDMMC_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types + * @{ + */ + +/** + * @brief SDMMC Configuration Structure definition + */ +typedef struct +{ + uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ + + uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ + + uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ + + uint32_t BusWide; /*!< Specifies the SDMMC bus width. + This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ + + uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ + + uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + +}SDMMC_InitTypeDef; + + +/** + * @brief SDMMC Command Control structure + */ +typedef struct +{ + uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register. */ + + uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and + Max_Data = 64 */ + + uint32_t Response; /*!< Specifies the SDMMC response type. + This parameter can be a value of @ref SDMMC_LL_Response_Type */ + + uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is + enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ + + uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_CPSM_State */ +}SDMMC_CmdInitTypeDef; + + +/** + * @brief SDMMC Data Control structure + */ +typedef struct +{ + uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ + + uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ + + uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. + This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ + + uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ + + uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ + + uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDMMC_LL_DPSM_State */ +}SDMMC_DataInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants + * @{ + */ +#define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ +#define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ +#define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ +#define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ +#define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ +#define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the + number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock + command or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out + of erase sequence command was received */ +#define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ +#define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ +#define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ +#define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ + +/** + * @brief SDMMC Commands Index + */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by + STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command + system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. + Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by + the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather + than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card + for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * SDMMC_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus + widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with + 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDMMC_CMD_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U + +/** + * @brief Masks for errors Card Status R1 (OCR Register) + */ +#define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U +#define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U +#define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U +#define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U +#define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U +#define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U +#define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U +#define SDMMC_OCR_COM_CRC_FAILED 0x00800000U +#define SDMMC_OCR_ILLEGAL_CMD 0x00400000U +#define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U +#define SDMMC_OCR_CC_ERROR 0x00100000U +#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U +#define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U +#define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U +#define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U +#define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U +#define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U +#define SDMMC_OCR_ERASE_RESET 0x00002000U +#define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U +#define SDMMC_OCR_ERRORBITS 0xFDFFE008U + +/** + * @brief Masks for R6 Response + */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U +#define SDMMC_R6_ILLEGAL_CMD 0x00004000U +#define SDMMC_R6_COM_CRC_FAILED 0x00008000U + +#define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U +#define SDMMC_HIGH_CAPACITY 0x40000000U +#define SDMMC_STD_CAPACITY 0x00000000U +#define SDMMC_CHECK_PATTERN 0x000001AAU +#define SD_SWITCH_1_8V_CAPACITY 0x01000000U + +#define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU + +#define SDMMC_MAX_TRIAL 0x0000FFFFU + +#define SDMMC_ALLZERO 0x00000000U + +#define SDMMC_WIDE_BUS_SUPPORT 0x00040000U +#define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U +#define SDMMC_CARD_LOCKED 0x02000000U + +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) +#endif /* SDMMC_DATATIMEOUT */ + +#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ +#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#endif /* SDMMC_SWDATATIMEOUT */ + +#define SDMMC_0TO7BITS 0x000000FFU +#define SDMMC_8TO15BITS 0x0000FF00U +#define SDMMC_16TO23BITS 0x00FF0000U +#define SDMMC_24TO31BITS 0xFF000000U +#define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU + +#define SDMMC_HALFFIFO 0x00000008U +#define SDMMC_HALFFIFOBYTES 0x00000020U + +/** + * @brief Command Class supported + */ +#define SDMMC_CCCC_ERASE 0x00000020U + +#define SDMMC_CMDTIMEOUT 5000U /* Command send and response timeout */ +#define SDMMC_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ +#define SDMMC_STOPTRANSFERTIMEOUT 100000000U /* Timeout for STOP TRANSMISSION command */ + +/** @defgroup SDMMC_LL_Clock_Edge Clock Edge + * @{ + */ +#define SDMMC_CLOCK_EDGE_RISING 0x00000000U +#define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE + +#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ + ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass + * @{ + */ +#define SDMMC_CLOCK_BYPASS_DISABLE 0x00000000U +#define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS + +#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ + ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving + * @{ + */ +#define SDMMC_CLOCK_POWER_SAVE_DISABLE 0x00000000U +#define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV + +#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ + ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Bus_Wide Bus Width + * @{ + */ +#define SDMMC_BUS_WIDE_1B 0x00000000U +#define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 +#define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 + +#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ + ((WIDE) == SDMMC_BUS_WIDE_4B) || \ + ((WIDE) == SDMMC_BUS_WIDE_8B)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control + * @{ + */ +#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U +#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN + +#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ + ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Clock_Division Clock Division + * @{ + */ +#define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Command_Index Command Index + * @{ + */ +#define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Response_Type Response Type + * @{ + */ +#define SDMMC_RESPONSE_NO 0x00000000U +#define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 +#define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP + +#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ + ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ + ((RESPONSE) == SDMMC_RESPONSE_LONG)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt + * @{ + */ +#define SDMMC_WAIT_NO 0x00000000U +#define SDMMC_WAIT_IT SDMMC_CMD_WAITINT +#define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND + +#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ + ((WAIT) == SDMMC_WAIT_IT) || \ + ((WAIT) == SDMMC_WAIT_PEND)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_CPSM_State CPSM State + * @{ + */ +#define SDMMC_CPSM_DISABLE 0x00000000U +#define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN + +#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ + ((CPSM) == SDMMC_CPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Response_Registers Response Register + * @{ + */ +#define SDMMC_RESP1 0x00000000U +#define SDMMC_RESP2 0x00000004U +#define SDMMC_RESP3 0x00000008U +#define SDMMC_RESP4 0x0000000CU + +#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ + ((RESP) == SDMMC_RESP2) || \ + ((RESP) == SDMMC_RESP3) || \ + ((RESP) == SDMMC_RESP4)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Data_Length Data Length + * @{ + */ +#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Data_Block_Size Data Block Size + * @{ + */ +#define SDMMC_DATABLOCK_SIZE_1B 0x00000000U +#define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 +#define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 +#define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) +#define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 +#define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) +#define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) +#define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) +#define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 +#define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) +#define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) + +#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ + ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction + * @{ + */ +#define SDMMC_TRANSFER_DIR_TO_CARD 0x00000000U +#define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR + +#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ + ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Transfer_Type Transfer Type + * @{ + */ +#define SDMMC_TRANSFER_MODE_BLOCK 0x00000000U +#define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE + +#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_DPSM_State DPSM State + * @{ + */ +#define SDMMC_DPSM_DISABLE 0x00000000U +#define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN + +#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ + ((DPSM) == SDMMC_DPSM_ENABLE)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode + * @{ + */ +#define SDMMC_READ_WAIT_MODE_DATA2 0x00000000U +#define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) + +#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ + ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) +/** + * @} + */ + +/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources + * @{ + */ +#define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE +#define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE +#define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE +#define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE +#define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE +#define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE +#define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE +#define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE +#define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE +#define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE +#define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE +#define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE +#define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE +#define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE +#define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE +#define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE +#define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE +#define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE +#define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE +#define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE +#define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE +#define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE +/** + * @} + */ + +/** @defgroup SDMMC_LL_Flags Flags + * @{ + */ +#define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL +#define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL +#define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT +#define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT +#define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR +#define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR +#define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND +#define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT +#define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND +#define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND +#define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT +#define SDMMC_FLAG_TXACT SDMMC_STA_TXACT +#define SDMMC_FLAG_RXACT SDMMC_STA_RXACT +#define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE +#define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF +#define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF +#define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF +#define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE +#define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE +#define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL +#define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL +#define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT +#define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ + SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ + SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ + SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) + +#define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ + SDMMC_FLAG_CMDSENT)) + +#define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ + SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros + * @{ + */ + +/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions + * @brief SDMMC_LL registers bit address in the alias region + * @{ + */ +/* ---------------------- SDMMC registers bit mask --------------------------- */ +/* --- CLKCR Register ---*/ +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ + SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ + SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) + +/* --- DCTRL Register ---*/ +/* SDMMC DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ + SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) + +/* --- CMD Register ---*/ +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ + SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ + SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) + +/* SDMMC Initialization Frequency (400KHz max) */ +#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ + +/* SDMMC Data Transfer Frequency (25MHz max) */ +#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ +/** + * @} + */ + +/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** + * @brief Enable the SDMMC device. + * @param __INSTANCE__: SDMMC Instance + * @retval None + */ +#define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) + +/** + * @brief Disable the SDMMC device. + * @param __INSTANCE__: SDMMC Instance + * @retval None + */ +#define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) + +/** + * @brief Enable the SDMMC DMA transfer. + * @param __INSTANCE__: SDMMC Instance + * @retval None + */ +#define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) + +/** + * @brief Disable the SDMMC DMA transfer. + * @param __INSTANCE__: SDMMC Instance + * @retval None + */ +#define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) + +/** + * @brief Enable the SDMMC device interrupt. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) + +/** + * @brief Disable the SDMMC device interrupt. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) + +/** + * @brief Checks whether the specified SDMMC flag is set or not. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_CMDACT: Command transfer in progress + * @arg SDMMC_FLAG_TXACT: Data transmit in progress + * @arg SDMMC_FLAG_RXACT: Data receive in progress + * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty + * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full + * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full + * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full + * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty + * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty + * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO + * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received + * @retval The new state of SDMMC_FLAG (SET or RESET). + */ +#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) + + +/** + * @brief Clears the SDMMC pending flags. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) + * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) + * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout + * @arg SDMMC_FLAG_DTIMEOUT: Data timeout + * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error + * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error + * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) + * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) + * @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) + * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) + * @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received + * @retval None + */ +#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) + +/** + * @brief Checks whether the specified SDMMC interrupt has occurred or not. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt + * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt + * @arg SDMMC_IT_RXACT: Data receive in progress interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt + * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt + * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @retval The new state of SDMMC_IT (SET or RESET). + */ +#define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the SDMMC's interrupt pending bits. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * This parameter can be one or a combination of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @retval None + */ +#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) + +/** + * @brief Disable Start the SD I/O Read Wait operations. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) + +/** + * @brief Enable Start the SD I/O Read Wait operation. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) + +/** + * @brief Disable Stop the SD I/O Read Wait operations. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) + +/** + * @brief Enable the SD I/O Mode Operation. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) + +/** + * @brief Disable the SD I/O Mode Operation. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) + +/** + * @brief Enable the SD I/O Suspend command sending. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) + +/** + * @brief Disable the SD I/O Suspend command sending. + * @param __INSTANCE__ : Pointer to SDMMC register base + * @retval None + */ +#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SDMMC_LL_Exported_Functions + * @{ + */ + +/* Initialization/de-initialization functions **********************************/ +/** @addtogroup HAL_SDMMC_LL_Group1 + * @{ + */ +HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); +/** + * @} + */ + +/* I/O operation functions *****************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group2 + * @{ + */ +uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); +/** + * @} + */ + +/* Peripheral Control functions ************************************************/ +/** @addtogroup HAL_SDMMC_LL_Group3 + * @{ + */ +HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); +HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); + +/* Command path state machine (CPSM) management functions */ +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); +uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); + +/* Data path state machine (DPSM) management functions */ +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); +uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); + +/* SDMMC Cards mode management functions */ +HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); +/** + * @} + */ + +/* SDMMC Commands management functions */ +/** @addtogroup HAL_SDMMC_LL_Group4 + * @{ + */ +uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); +uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); +uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); +uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); +uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); +uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); +uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); +uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); +uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); +uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); +uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); +uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); +uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA); +uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +/** + * @} + */ + +/* SDMMC Responses management functions *****************************************/ +/** @addtogroup HAL_SDMMC_LL_Group5 + * @{ + */ +uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); +uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); +uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDMMC1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_LL_SDMMC_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h index 7eb04a59..f5f24a70 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_spi.h @@ -1,2282 +1,2297 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_spi.h - * @author MCD Application Team - * @brief Header file of SPI LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_SPI_H -#define STM32F7xx_LL_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) - -/** @defgroup SPI_LL SPI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure - * @{ - */ - -/** - * @brief SPI Init structures definition - */ -typedef struct -{ - uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ - - uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). - This parameter can be a value of @ref SPI_LL_EC_MODE. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ - - uint32_t DataWidth; /*!< Specifies the SPI data width. - This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ - - uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_LL_EC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ - - uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_LL_EC_PHASE. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ - - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ - - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ - - uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ - - uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. - This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ - - uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ - -} LL_SPI_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants - * @{ - */ - -/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_SPI_ReadReg function - * @{ - */ -#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ -#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ -#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ -#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ -#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ -#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ -#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions - * @{ - */ -#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ -#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ -#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_MODE Operation Mode - * @{ - */ -#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ -#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol - * @{ - */ -#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ -#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_PHASE Clock Phase - * @{ - */ -#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ -#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ -#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler - * @{ - */ -#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order - * @{ - */ -#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ -#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode - * @{ - */ -#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ -#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ -#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ -#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode - * @{ - */ -#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ -#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ -#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth - * @{ - */ -#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ -#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ -#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ -#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ -#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ -#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ -#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ -#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ -#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ -#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ -#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ -#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ -#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation - * @{ - */ -#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ -#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length - * @{ - */ -#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ -#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold - * @{ - */ -#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ -#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level - * @{ - */ -#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ -#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ -#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ -#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level - * @{ - */ -#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ -#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ -#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ -#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity - * @{ - */ -#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ -#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros - * @{ - */ - -/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in SPI register - * @param __INSTANCE__ SPI Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in SPI register - * @param __INSTANCE__ SPI Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions - * @{ - */ - -/** @defgroup SPI_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable SPI peripheral - * @rmtoll CR1 SPE LL_SPI_Enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_SPE); -} - -/** - * @brief Disable SPI peripheral - * @note When disabling the SPI, follow the procedure described in the Reference Manual. - * @rmtoll CR1 SPE LL_SPI_Disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); -} - -/** - * @brief Check if SPI peripheral is enabled - * @rmtoll CR1 SPE LL_SPI_IsEnabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); -} - -/** - * @brief Set SPI operation mode to Master or Slave - * @note This bit should not be changed when communication is ongoing. - * @rmtoll CR1 MSTR LL_SPI_SetMode\n - * CR1 SSI LL_SPI_SetMode - * @param SPIx SPI Instance - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_SPI_MODE_MASTER - * @arg @ref LL_SPI_MODE_SLAVE - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); -} - -/** - * @brief Get SPI operation mode (Master or Slave) - * @rmtoll CR1 MSTR LL_SPI_GetMode\n - * CR1 SSI LL_SPI_GetMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_MODE_MASTER - * @arg @ref LL_SPI_MODE_SLAVE - */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); -} - -/** - * @brief Set serial protocol used - * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. - * @rmtoll CR2 FRF LL_SPI_SetStandard - * @param SPIx SPI Instance - * @param Standard This parameter can be one of the following values: - * @arg @ref LL_SPI_PROTOCOL_MOTOROLA - * @arg @ref LL_SPI_PROTOCOL_TI - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); -} - -/** - * @brief Get serial protocol used - * @rmtoll CR2 FRF LL_SPI_GetStandard - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_PROTOCOL_MOTOROLA - * @arg @ref LL_SPI_PROTOCOL_TI - */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); -} - -/** - * @brief Set clock phase - * @note This bit should not be changed when communication is ongoing. - * This bit is not used in SPI TI mode. - * @rmtoll CR1 CPHA LL_SPI_SetClockPhase - * @param SPIx SPI Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref LL_SPI_PHASE_1EDGE - * @arg @ref LL_SPI_PHASE_2EDGE - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); -} - -/** - * @brief Get clock phase - * @rmtoll CR1 CPHA LL_SPI_GetClockPhase - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_PHASE_1EDGE - * @arg @ref LL_SPI_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); -} - -/** - * @brief Set clock polarity - * @note This bit should not be changed when communication is ongoing. - * This bit is not used in SPI TI mode. - * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity - * @param SPIx SPI Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_SPI_POLARITY_LOW - * @arg @ref LL_SPI_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); -} - -/** - * @brief Get clock polarity - * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_POLARITY_LOW - * @arg @ref LL_SPI_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); -} - -/** - * @brief Set baud rate prescaler - * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. - * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler - * @param SPIx SPI Instance - * @param BaudRate This parameter can be one of the following values: - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); -} - -/** - * @brief Get baud rate prescaler - * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 - */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); -} - -/** - * @brief Set transfer bit order - * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. - * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder - * @param SPIx SPI Instance - * @param BitOrder This parameter can be one of the following values: - * @arg @ref LL_SPI_LSB_FIRST - * @arg @ref LL_SPI_MSB_FIRST - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); -} - -/** - * @brief Get transfer bit order - * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_LSB_FIRST - * @arg @ref LL_SPI_MSB_FIRST - */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); -} - -/** - * @brief Set transfer direction mode - * @note For Half-Duplex mode, Rx Direction is set by default. - * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. - * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n - * CR1 BIDIMODE LL_SPI_SetTransferDirection\n - * CR1 BIDIOE LL_SPI_SetTransferDirection - * @param SPIx SPI Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_SPI_FULL_DUPLEX - * @arg @ref LL_SPI_SIMPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_TX - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); -} - -/** - * @brief Get transfer direction mode - * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n - * CR1 BIDIMODE LL_SPI_GetTransferDirection\n - * CR1 BIDIOE LL_SPI_GetTransferDirection - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_FULL_DUPLEX - * @arg @ref LL_SPI_SIMPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_TX - */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); -} - -/** - * @brief Set frame data width - * @rmtoll CR2 DS LL_SPI_SetDataWidth - * @param SPIx SPI Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_SPI_DATAWIDTH_4BIT - * @arg @ref LL_SPI_DATAWIDTH_5BIT - * @arg @ref LL_SPI_DATAWIDTH_6BIT - * @arg @ref LL_SPI_DATAWIDTH_7BIT - * @arg @ref LL_SPI_DATAWIDTH_8BIT - * @arg @ref LL_SPI_DATAWIDTH_9BIT - * @arg @ref LL_SPI_DATAWIDTH_10BIT - * @arg @ref LL_SPI_DATAWIDTH_11BIT - * @arg @ref LL_SPI_DATAWIDTH_12BIT - * @arg @ref LL_SPI_DATAWIDTH_13BIT - * @arg @ref LL_SPI_DATAWIDTH_14BIT - * @arg @ref LL_SPI_DATAWIDTH_15BIT - * @arg @ref LL_SPI_DATAWIDTH_16BIT - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); -} - -/** - * @brief Get frame data width - * @rmtoll CR2 DS LL_SPI_GetDataWidth - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_DATAWIDTH_4BIT - * @arg @ref LL_SPI_DATAWIDTH_5BIT - * @arg @ref LL_SPI_DATAWIDTH_6BIT - * @arg @ref LL_SPI_DATAWIDTH_7BIT - * @arg @ref LL_SPI_DATAWIDTH_8BIT - * @arg @ref LL_SPI_DATAWIDTH_9BIT - * @arg @ref LL_SPI_DATAWIDTH_10BIT - * @arg @ref LL_SPI_DATAWIDTH_11BIT - * @arg @ref LL_SPI_DATAWIDTH_12BIT - * @arg @ref LL_SPI_DATAWIDTH_13BIT - * @arg @ref LL_SPI_DATAWIDTH_14BIT - * @arg @ref LL_SPI_DATAWIDTH_15BIT - * @arg @ref LL_SPI_DATAWIDTH_16BIT - */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); -} - -/** - * @brief Set threshold of RXFIFO that triggers an RXNE event - * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold - * @param SPIx SPI Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_SPI_RX_FIFO_TH_HALF - * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); -} - -/** - * @brief Get threshold of RXFIFO that triggers an RXNE event - * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_RX_FIFO_TH_HALF - * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER - */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_CRC_Management CRC Management - * @{ - */ - -/** - * @brief Enable CRC - * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. - * @rmtoll CR1 CRCEN LL_SPI_EnableCRC - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); -} - -/** - * @brief Disable CRC - * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. - * @rmtoll CR1 CRCEN LL_SPI_DisableCRC - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); -} - -/** - * @brief Check if CRC is enabled - * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. - * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); -} - -/** - * @brief Set CRC Length - * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. - * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth - * @param SPIx SPI Instance - * @param CRCLength This parameter can be one of the following values: - * @arg @ref LL_SPI_CRC_8BIT - * @arg @ref LL_SPI_CRC_16BIT - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); -} - -/** - * @brief Get CRC Length - * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_CRC_8BIT - * @arg @ref LL_SPI_CRC_16BIT - */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); -} - -/** - * @brief Set CRCNext to transfer CRC on the line - * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. - * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); -} - -/** - * @brief Set polynomial for CRC calculation - * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial - * @param SPIx SPI Instance - * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) -{ - WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); -} - -/** - * @brief Get polynomial for CRC calculation - * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial - * @param SPIx SPI Instance - * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->CRCPR)); -} - -/** - * @brief Get Rx CRC - * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC - * @param SPIx SPI Instance - * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->RXCRCR)); -} - -/** - * @brief Get Tx CRC - * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC - * @param SPIx SPI Instance - * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->TXCRCR)); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management - * @{ - */ - -/** - * @brief Set NSS mode - * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. - * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n - * @rmtoll CR2 SSOE LL_SPI_SetNSSMode - * @param SPIx SPI Instance - * @param NSS This parameter can be one of the following values: - * @arg @ref LL_SPI_NSS_SOFT - * @arg @ref LL_SPI_NSS_HARD_INPUT - * @arg @ref LL_SPI_NSS_HARD_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); - MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); -} - -/** - * @brief Get NSS mode - * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n - * @rmtoll CR2 SSOE LL_SPI_GetNSSMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_NSS_SOFT - * @arg @ref LL_SPI_NSS_HARD_INPUT - * @arg @ref LL_SPI_NSS_HARD_OUTPUT - */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) -{ - uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); - uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); - return (Ssm | Ssoe); -} - -/** - * @brief Enable NSS pulse management - * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. - * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_NSSP); -} - -/** - * @brief Disable NSS pulse management - * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. - * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); -} - -/** - * @brief Check if NSS pulse is enabled - * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. - * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Check if Rx buffer is not empty - * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx buffer is empty - * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); -} - -/** - * @brief Get CRC error flag - * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); -} - -/** - * @brief Get mode fault error flag - * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); -} - -/** - * @brief Get overrun error flag - * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Get busy flag - * @note The BSY flag is cleared under any one of the following conditions: - * -When the SPI is correctly disabled - * -When a fault is detected in Master mode (MODF bit set to 1) - * -In Master mode, when it finishes a data transmission and no new data is ready to be - * sent - * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between - * each data transfer. - * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); -} - -/** - * @brief Get frame format error flag - * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); -} - -/** - * @brief Get FIFO reception Level - * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_RX_FIFO_EMPTY - * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL - * @arg @ref LL_SPI_RX_FIFO_HALF_FULL - * @arg @ref LL_SPI_RX_FIFO_FULL - */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); -} - -/** - * @brief Get FIFO Transmission Level - * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_TX_FIFO_EMPTY - * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL - * @arg @ref LL_SPI_TX_FIFO_HALF_FULL - * @arg @ref LL_SPI_TX_FIFO_FULL - */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); -} - -/** - * @brief Clear CRC error flag - * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); -} - -/** - * @brief Clear mode fault error flag - * @note Clearing this flag is done by a read access to the SPIx_SR - * register followed by a write access to the SPIx_CR1 register - * @rmtoll SR MODF LL_SPI_ClearFlag_MODF - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) -{ - __IO uint32_t tmpreg_sr; - tmpreg_sr = SPIx->SR; - (void) tmpreg_sr; - CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); -} - -/** - * @brief Clear overrun error flag - * @note Clearing this flag is done by a read access to the SPIx_DR - * register followed by a read access to the SPIx_SR register - * @rmtoll SR OVR LL_SPI_ClearFlag_OVR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) -{ - __IO uint32_t tmpreg; - tmpreg = SPIx->DR; - (void) tmpreg; - tmpreg = SPIx->SR; - (void) tmpreg; -} - -/** - * @brief Clear frame format error flag - * @note Clearing this flag is done by reading SPIx_SR register - * @rmtoll SR FRE LL_SPI_ClearFlag_FRE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) -{ - __IO uint32_t tmpreg; - tmpreg = SPIx->SR; - (void) tmpreg; -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_IT_Management Interrupt Management - * @{ - */ - -/** - * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). - * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); -} - -/** - * @brief Enable Rx buffer not empty interrupt - * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); -} - -/** - * @brief Enable Tx buffer empty interrupt - * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); -} - -/** - * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). - * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); -} - -/** - * @brief Disable Rx buffer not empty interrupt - * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); -} - -/** - * @brief Disable Tx buffer empty interrupt - * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); -} - -/** - * @brief Check if error interrupt is enabled - * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx buffer not empty interrupt is enabled - * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx buffer empty interrupt - * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_DMA_Management DMA Management - * @{ - */ - -/** - * @brief Enable DMA Rx - * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); -} - -/** - * @brief Disable DMA Rx - * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); -} - -/** - * @brief Check if DMA Rx is enabled - * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Tx - * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); -} - -/** - * @brief Disable DMA Tx - * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); -} - -/** - * @brief Check if DMA Tx is enabled - * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Set parity of Last DMA reception - * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX - * @param SPIx SPI Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_SPI_DMA_PARITY_ODD - * @arg @ref LL_SPI_DMA_PARITY_EVEN - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); -} - -/** - * @brief Get parity configuration for Last DMA reception - * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_DMA_PARITY_ODD - * @arg @ref LL_SPI_DMA_PARITY_EVEN - */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); -} - -/** - * @brief Set parity of Last DMA transmission - * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX - * @param SPIx SPI Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_SPI_DMA_PARITY_ODD - * @arg @ref LL_SPI_DMA_PARITY_EVEN - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); -} - -/** - * @brief Get parity configuration for Last DMA transmission - * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_DMA_PARITY_ODD - * @arg @ref LL_SPI_DMA_PARITY_EVEN - */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); -} - -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll DR DR LL_SPI_DMA_GetRegAddr - * @param SPIx SPI Instance - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) -{ - return (uint32_t) &(SPIx->DR); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_DATA_Management DATA Management - * @{ - */ - -/** - * @brief Read 8-Bits in the data register - * @rmtoll DR DR LL_SPI_ReceiveData8 - * @param SPIx SPI Instance - * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) -{ - return (*((__IO uint8_t *)&SPIx->DR)); -} - -/** - * @brief Read 16-Bits in the data register - * @rmtoll DR DR LL_SPI_ReceiveData16 - * @param SPIx SPI Instance - * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) -{ - return (uint16_t)(READ_REG(SPIx->DR)); -} - -/** - * @brief Write 8-Bits in the data register - * @rmtoll DR DR LL_SPI_TransmitData8 - * @param SPIx SPI Instance - * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) -{ -#if defined (__GNUC__) - __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); - *spidr = TxData; -#else - *((__IO uint8_t *)&SPIx->DR) = TxData; -#endif /* __GNUC__ */ -} - -/** - * @brief Write 16-Bits in the data register - * @rmtoll DR DR LL_SPI_TransmitData16 - * @param SPIx SPI Instance - * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) -{ -#if defined (__GNUC__) - __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); - *spidr = TxData; -#else - SPIx->DR = TxData; -#endif /* __GNUC__ */ -} - -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); -ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); -void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup I2S_LL I2S - * @{ - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure - * @{ - */ - -/** - * @brief I2S Init structure definition - */ - -typedef struct -{ - uint32_t Mode; /*!< Specifies the I2S operating mode. - This parameter can be a value of @ref I2S_LL_EC_MODE - - This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ - - uint32_t Standard; /*!< Specifies the standard used for the I2S communication. - This parameter can be a value of @ref I2S_LL_EC_STANDARD - - This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ - - - uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. - This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT - - This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ - - - uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. - This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT - - This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ - - - uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. - This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ - - Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity - and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ - - - uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. - This parameter can be a value of @ref I2S_LL_EC_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ - -} LL_I2S_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants - * @{ - */ - -/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_I2S_ReadReg function - * @{ - */ -#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ -#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ -#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ -#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ -#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ -#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions - * @{ - */ -#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ -#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ -#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_DATA_FORMAT Data format - * @{ - */ -#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ -#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ -#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ -#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ -#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_STANDARD I2s Standard - * @{ - */ -#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ -#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ -#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ -#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ -#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_MODE Operation Mode - * @{ - */ -#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ -#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ -#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ -#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor - * @{ - */ -#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ -#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output - * @{ - */ -#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ -#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ -/** - * @} - */ - -/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency - * @{ - */ - -#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ -#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ -#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ -#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ -#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ -#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ -#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ -#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ -#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ -#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros - * @{ - */ - -/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in I2S register - * @param __INSTANCE__ I2S Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in I2S register - * @param __INSTANCE__ I2S Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions - * @{ - */ - -/** @defgroup I2S_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Select I2S mode and Enable I2S peripheral - * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n - * I2SCFGR I2SE LL_I2S_Enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); -} - -/** - * @brief Disable I2S peripheral - * @rmtoll I2SCFGR I2SE LL_I2S_Disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); -} - -/** - * @brief Check if I2S peripheral is enabled - * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); -} - -/** - * @brief Set I2S data frame length - * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n - * I2SCFGR CHLEN LL_I2S_SetDataFormat - * @param SPIx SPI Instance - * @param DataFormat This parameter can be one of the following values: - * @arg @ref LL_I2S_DATAFORMAT_16B - * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED - * @arg @ref LL_I2S_DATAFORMAT_24B - * @arg @ref LL_I2S_DATAFORMAT_32B - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) -{ - MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); -} - -/** - * @brief Get I2S data frame length - * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n - * I2SCFGR CHLEN LL_I2S_GetDataFormat - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_DATAFORMAT_16B - * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED - * @arg @ref LL_I2S_DATAFORMAT_24B - * @arg @ref LL_I2S_DATAFORMAT_32B - */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); -} - -/** - * @brief Set I2S clock polarity - * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity - * @param SPIx SPI Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_I2S_POLARITY_LOW - * @arg @ref LL_I2S_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) -{ - SET_BIT(SPIx->I2SCFGR, ClockPolarity); -} - -/** - * @brief Get I2S clock polarity - * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_POLARITY_LOW - * @arg @ref LL_I2S_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); -} - -/** - * @brief Set I2S standard protocol - * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n - * I2SCFGR PCMSYNC LL_I2S_SetStandard - * @param SPIx SPI Instance - * @param Standard This parameter can be one of the following values: - * @arg @ref LL_I2S_STANDARD_PHILIPS - * @arg @ref LL_I2S_STANDARD_MSB - * @arg @ref LL_I2S_STANDARD_LSB - * @arg @ref LL_I2S_STANDARD_PCM_SHORT - * @arg @ref LL_I2S_STANDARD_PCM_LONG - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) -{ - MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); -} - -/** - * @brief Get I2S standard protocol - * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n - * I2SCFGR PCMSYNC LL_I2S_GetStandard - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_STANDARD_PHILIPS - * @arg @ref LL_I2S_STANDARD_MSB - * @arg @ref LL_I2S_STANDARD_LSB - * @arg @ref LL_I2S_STANDARD_PCM_SHORT - * @arg @ref LL_I2S_STANDARD_PCM_LONG - */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); -} - -/** - * @brief Set I2S transfer mode - * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode - * @param SPIx SPI Instance - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_I2S_MODE_SLAVE_TX - * @arg @ref LL_I2S_MODE_SLAVE_RX - * @arg @ref LL_I2S_MODE_MASTER_TX - * @arg @ref LL_I2S_MODE_MASTER_RX - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) -{ - MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); -} - -/** - * @brief Get I2S transfer mode - * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_MODE_SLAVE_TX - * @arg @ref LL_I2S_MODE_SLAVE_RX - * @arg @ref LL_I2S_MODE_MASTER_TX - * @arg @ref LL_I2S_MODE_MASTER_RX - */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); -} - -/** - * @brief Set I2S linear prescaler - * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear - * @param SPIx SPI Instance - * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) -{ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); -} - -/** - * @brief Get I2S linear prescaler - * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear - * @param SPIx SPI Instance - * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); -} - -/** - * @brief Set I2S parity prescaler - * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity - * @param SPIx SPI Instance - * @param PrescalerParity This parameter can be one of the following values: - * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN - * @arg @ref LL_I2S_PRESCALER_PARITY_ODD - * @retval None - */ -__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) -{ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); -} - -/** - * @brief Get I2S parity prescaler - * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN - * @arg @ref LL_I2S_PRESCALER_PARITY_ODD - */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); -} - -/** - * @brief Enable the master clock output (Pin MCK) - * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); -} - -/** - * @brief Disable the master clock output (Pin MCK) - * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); -} - -/** - * @brief Check if the master clock output (Pin MCK) is enabled - * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); -} - -#if defined(SPI_I2SCFGR_ASTRTEN) -/** - * @brief Enable asynchronous start - * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); -} - -/** - * @brief Disable asynchronous start - * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); -} - -/** - * @brief Check if asynchronous start is enabled - * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); -} -#endif /* SPI_I2SCFGR_ASTRTEN */ - -/** - * @} - */ - -/** @defgroup I2S_LL_EF_FLAG FLAG Management - * @{ - */ - -/** - * @brief Check if Rx buffer is not empty - * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_RXNE(SPIx); -} - -/** - * @brief Check if Tx buffer is empty - * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_TXE(SPIx); -} - -/** - * @brief Get busy flag - * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_BSY(SPIx); -} - -/** - * @brief Get overrun error flag - * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_OVR(SPIx); -} - -/** - * @brief Get underrun error flag - * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); -} - -/** - * @brief Get frame format error flag - * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsActiveFlag_FRE(SPIx); -} - -/** - * @brief Get channel side flag. - * @note 0: Channel Left has to be transmitted or has been received\n - * 1: Channel Right has to be transmitted or has been received\n - * It has no significance in PCM mode. - * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); -} - -/** - * @brief Clear overrun error flag - * @rmtoll SR OVR LL_I2S_ClearFlag_OVR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) -{ - LL_SPI_ClearFlag_OVR(SPIx); -} - -/** - * @brief Clear underrun error flag - * @rmtoll SR UDR LL_I2S_ClearFlag_UDR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) -{ - __IO uint32_t tmpreg; - tmpreg = SPIx->SR; - (void)tmpreg; -} - -/** - * @brief Clear frame format error flag - * @rmtoll SR FRE LL_I2S_ClearFlag_FRE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) -{ - LL_SPI_ClearFlag_FRE(SPIx); -} - -/** - * @} - */ - -/** @defgroup I2S_LL_EF_IT Interrupt Management - * @{ - */ - -/** - * @brief Enable error IT - * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). - * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableIT_ERR(SPIx); -} - -/** - * @brief Enable Rx buffer not empty IT - * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableIT_RXNE(SPIx); -} - -/** - * @brief Enable Tx buffer empty IT - * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableIT_TXE(SPIx); -} - -/** - * @brief Disable error IT - * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). - * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableIT_ERR(SPIx); -} - -/** - * @brief Disable Rx buffer not empty IT - * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableIT_RXNE(SPIx); -} - -/** - * @brief Disable Tx buffer empty IT - * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableIT_TXE(SPIx); -} - -/** - * @brief Check if ERR IT is enabled - * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledIT_ERR(SPIx); -} - -/** - * @brief Check if RXNE IT is enabled - * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledIT_RXNE(SPIx); -} - -/** - * @brief Check if TXE IT is enabled - * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledIT_TXE(SPIx); -} - -/** - * @} - */ - -/** @defgroup I2S_LL_EF_DMA DMA Management - * @{ - */ - -/** - * @brief Enable DMA Rx - * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableDMAReq_RX(SPIx); -} - -/** - * @brief Disable DMA Rx - * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableDMAReq_RX(SPIx); -} - -/** - * @brief Check if DMA Rx is enabled - * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledDMAReq_RX(SPIx); -} - -/** - * @brief Enable DMA Tx - * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) -{ - LL_SPI_EnableDMAReq_TX(SPIx); -} - -/** - * @brief Disable DMA Tx - * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) -{ - LL_SPI_DisableDMAReq_TX(SPIx); -} - -/** - * @brief Check if DMA Tx is enabled - * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) -{ - return LL_SPI_IsEnabledDMAReq_TX(SPIx); -} - -/** - * @} - */ - -/** @defgroup I2S_LL_EF_DATA DATA Management - * @{ - */ - -/** - * @brief Read 16-Bits in data register - * @rmtoll DR DR LL_I2S_ReceiveData16 - * @param SPIx SPI Instance - * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) -{ - return LL_SPI_ReceiveData16(SPIx); -} - -/** - * @brief Write 16-Bits in data register - * @rmtoll DR DR LL_I2S_TransmitData16 - * @param SPIx SPI Instance - * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) -{ - LL_SPI_TransmitData16(SPIx, TxData); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); -void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); -void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_SPI_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_spi.h + * @author MCD Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_LL_SPI_H +#define STM32F7xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. + This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. + + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + + uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ +#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ +#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ +#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ +#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol + * @{ + */ +#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ +#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ +#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ +#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ +#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ +#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ +#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ +#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ +#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ +#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ +#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ +#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ +#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ +#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ +#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation + * @{ + */ +#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ +#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length + * @{ + */ +#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ +#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold + * @{ + */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level + * @{ + */ +#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ +#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ +#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ +#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level + * @{ + */ +#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ +#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ +#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ +#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity + * @{ + */ +#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ +#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI operation mode to Master or Slave + * @note This bit should not be changed when communication is ongoing. + * @rmtoll CR1 MSTR LL_SPI_SetMode\n + * CR1 SSI LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); +} + +/** + * @brief Get SPI operation mode (Master or Slave) + * @rmtoll CR1 MSTR LL_SPI_GetMode\n + * CR1 SSI LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); +} + +/** + * @brief Set serial protocol used + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR2 FRF LL_SPI_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); +} + +/** + * @brief Get serial protocol used + * @rmtoll CR2 FRF LL_SPI_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PROTOCOL_MOTOROLA + * @arg @ref LL_SPI_PROTOCOL_TI + */ +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); +} + +/** + * @brief Set clock phase + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); +} + +/** + * @brief Get clock phase + * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); +} + +/** + * @brief Set clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); +} + +/** + * @brief Get clock polarity + * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); +} + +/** + * @brief Set baud rate prescaler + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); +} + +/** + * @brief Get baud rate prescaler + * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); +} + +/** + * @brief Set transfer bit order + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); +} + +/** + * @brief Get transfer bit order + * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); +} + +/** + * @brief Set transfer direction mode + * @note For Half-Duplex mode, Rx Direction is set by default. + * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. + * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + * CR1 BIDIOE LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); +} + +/** + * @brief Get transfer direction mode + * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + * CR1 BIDIOE LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); +} + +/** + * @brief Set frame data width + * @rmtoll CR2 DS LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); +} + +/** + * @brief Get frame data width + * @rmtoll CR2 DS LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_4BIT + * @arg @ref LL_SPI_DATAWIDTH_5BIT + * @arg @ref LL_SPI_DATAWIDTH_6BIT + * @arg @ref LL_SPI_DATAWIDTH_7BIT + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_9BIT + * @arg @ref LL_SPI_DATAWIDTH_10BIT + * @arg @ref LL_SPI_DATAWIDTH_11BIT + * @arg @ref LL_SPI_DATAWIDTH_12BIT + * @arg @ref LL_SPI_DATAWIDTH_13BIT + * @arg @ref LL_SPI_DATAWIDTH_14BIT + * @arg @ref LL_SPI_DATAWIDTH_15BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); +} + +/** + * @brief Set threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); +} + +/** + * @brief Get threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_CRC_Management CRC Management + * @{ + */ + +/** + * @brief Enable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_EnableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Disable CRC + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_DisableCRC + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); +} + +/** + * @brief Check if CRC is enabled + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set CRC Length + * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. + * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth + * @param SPIx SPI Instance + * @param CRCLength This parameter can be one of the following values: + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); +} + +/** + * @brief Get CRC Length + * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_CRC_8BIT + * @arg @ref LL_SPI_CRC_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); +} + +/** + * @brief Set CRCNext to transfer CRC on the line + * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. + * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); +} + +/** + * @brief Set polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial + * @param SPIx SPI Instance + * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) +{ + WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); +} + +/** + * @brief Get polynomial for CRC calculation + * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->CRCPR)); +} + +/** + * @brief Get Rx CRC + * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->RXCRCR)); +} + +/** + * @brief Get Tx CRC + * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC + * @param SPIx SPI Instance + * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_REG(SPIx->TXCRCR)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + * @{ + */ + +/** + * @brief Set NSS mode + * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. + * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); +} + +/** + * @brief Get NSS mode + * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) +{ + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + return (Ssm | Ssoe); +} + +/** + * @brief Enable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_NSSP); +} + +/** + * @brief Disable NSS pulse management + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); +} + +/** + * @brief Check if NSS pulse is enabled + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Get CRC error flag + * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); +} + +/** + * @brief Get mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get busy flag + * @note The BSY flag is cleared under any one of the following conditions: + * -When the SPI is correctly disabled + * -When a fault is detected in Master mode (MODF bit set to 1) + * -In Master mode, when it finishes a data transmission and no new data is ready to be + * sent + * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + * each data transfer. + * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); +} + +/** + * @brief Get FIFO reception Level + * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_EMPTY + * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_RX_FIFO_HALF_FULL + * @arg @ref LL_SPI_RX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); +} + +/** + * @brief Get FIFO Transmission Level + * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TX_FIFO_EMPTY + * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_TX_FIFO_HALF_FULL + * @arg @ref LL_SPI_TX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); +} + +/** + * @brief Clear CRC error flag + * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); +} + +/** + * @brief Clear mode fault error flag + * @note Clearing this flag is done by a read access to the SPIx_SR + * register followed by a write access to the SPIx_CR1 register + * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg_sr; + tmpreg_sr = SPIx->SR; + (void) tmpreg_sr; + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Clear overrun error flag + * @note Clearing this flag is done by a read access to the SPIx_DR + * register followed by a read access to the SPIx_SR register + * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->DR; + (void) tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @brief Clear frame format error flag + * @note Clearing this flag is done by reading SPIx_SR register + * @rmtoll SR FRE LL_SPI_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable error interrupt + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Enable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Enable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Disable error interrupt + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Disable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Disable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Check if error interrupt is enabled + * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx buffer not empty interrupt is enabled + * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set parity of Last DMA reception + * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA reception + * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); +} + +/** + * @brief Set parity of Last DMA transmission + * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA transmission + * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll DR DR LL_SPI_DMA_GetRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) +{ + return (uint32_t) &(SPIx->DR); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (*((__IO uint8_t *)&SPIx->DR)); +} + +/** + * @brief Read 16-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Write 8-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; +#else + *((__IO uint8_t *)&SPIx->DR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write 16-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else + SPIx->DR = TxData; +#endif /* __GNUC__ */ +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup I2S_LL I2S + * @{ + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure + * @{ + */ + +/** + * @brief I2S Init structure definition + */ + +typedef struct +{ + uint32_t Mode; /*!< Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_LL_EC_MODE + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ + + uint32_t Standard; /*!< Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_STANDARD + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ + + + uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ + + + uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT + + This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ + + + uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ + + Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity + and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ + + + uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_LL_EC_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ + +} LL_I2S_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2S_ReadReg function + * @{ + */ +#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ +#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ +#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ +#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_DATA_FORMAT Data format + * @{ + */ +#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */ +#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */ +#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ +#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_STANDARD I2s Standard + * @{ + */ +#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ +#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ +#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ +#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ +#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ +#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ +#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ +#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor + * @{ + */ +#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ +#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output + * @{ + */ +#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ +#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ +/** + * @} + */ + +/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency + * @{ + */ + +#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ +#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ +#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ +#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ +#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ +#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ +#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ +#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ +#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ +#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros + * @{ + */ + +/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2S register + * @param __INSTANCE__ I2S Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions + * @{ + */ + +/** @defgroup I2S_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Select I2S mode and Enable I2S peripheral + * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n + * I2SCFGR I2SE LL_I2S_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Disable I2S peripheral + * @rmtoll I2SCFGR I2SE LL_I2S_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); +} + +/** + * @brief Check if I2S peripheral is enabled + * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); +} + +/** + * @brief Set I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n + * I2SCFGR CHLEN LL_I2S_SetDataFormat + * @param SPIx SPI Instance + * @param DataFormat This parameter can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); +} + +/** + * @brief Get I2S data frame length + * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n + * I2SCFGR CHLEN LL_I2S_GetDataFormat + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_DATAFORMAT_16B + * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED + * @arg @ref LL_I2S_DATAFORMAT_24B + * @arg @ref LL_I2S_DATAFORMAT_32B + */ +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); +} + +/** + * @brief Set I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + SET_BIT(SPIx->I2SCFGR, ClockPolarity); +} + +/** + * @brief Get I2S clock polarity + * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_POLARITY_LOW + * @arg @ref LL_I2S_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); +} + +/** + * @brief Set I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n + * I2SCFGR PCMSYNC LL_I2S_SetStandard + * @param SPIx SPI Instance + * @param Standard This parameter can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); +} + +/** + * @brief Get I2S standard protocol + * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n + * I2SCFGR PCMSYNC LL_I2S_GetStandard + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_STANDARD_PHILIPS + * @arg @ref LL_I2S_STANDARD_MSB + * @arg @ref LL_I2S_STANDARD_LSB + * @arg @ref LL_I2S_STANDARD_PCM_SHORT + * @arg @ref LL_I2S_STANDARD_PCM_LONG + */ +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); +} + +/** + * @brief Set I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); +} + +/** + * @brief Get I2S transfer mode + * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_MODE_SLAVE_TX + * @arg @ref LL_I2S_MODE_SLAVE_RX + * @arg @ref LL_I2S_MODE_MASTER_TX + * @arg @ref LL_I2S_MODE_MASTER_RX + */ +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); +} + +/** + * @brief Set I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear + * @param SPIx SPI Instance + * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); +} + +/** + * @brief Get I2S linear prescaler + * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear + * @param SPIx SPI Instance + * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); +} + +/** + * @brief Set I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity + * @param SPIx SPI Instance + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) +{ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); +} + +/** + * @brief Get I2S parity prescaler + * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); +} + +/** + * @brief Enable the master clock output (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Disable the master clock output (Pin MCK) + * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); +} + +/** + * @brief Check if the master clock output (Pin MCK) is enabled + * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); +} + +#if defined(SPI_I2SCFGR_ASTRTEN) +/** + * @brief Enable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Disable asynchronous start + * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); +} + +/** + * @brief Check if asynchronous start is enabled + * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); +} +#endif /* SPI_I2SCFGR_ASTRTEN */ + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_FLAG FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_RXNE(SPIx); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_TXE(SPIx); +} + +/** + * @brief Get busy flag + * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_BSY(SPIx); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_OVR(SPIx); +} + +/** + * @brief Get underrun error flag + * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Get frame format error flag + * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsActiveFlag_FRE(SPIx); +} + +/** + * @brief Get channel side flag. + * @note 0: Channel Left has to be transmitted or has been received\n + * 1: Channel Right has to be transmitted or has been received\n + * It has no significance in PCM mode. + * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); +} + +/** + * @brief Clear overrun error flag + * @rmtoll SR OVR LL_I2S_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_OVR(SPIx); +} + +/** + * @brief Clear underrun error flag + * @rmtoll SR UDR LL_I2S_ClearFlag_UDR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->SR; + (void)tmpreg; +} + +/** + * @brief Clear frame format error flag + * @rmtoll SR FRE LL_I2S_ClearFlag_FRE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) +{ + LL_SPI_ClearFlag_FRE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_IT Interrupt Management + * @{ + */ + +/** + * @brief Enable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_ERR(SPIx); +} + +/** + * @brief Enable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_RXNE(SPIx); +} + +/** + * @brief Enable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableIT_TXE(SPIx); +} + +/** + * @brief Disable error IT + * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). + * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_ERR(SPIx); +} + +/** + * @brief Disable Rx buffer not empty IT + * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_RXNE(SPIx); +} + +/** + * @brief Disable Tx buffer empty IT + * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableIT_TXE(SPIx); +} + +/** + * @brief Check if ERR IT is enabled + * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_ERR(SPIx); +} + +/** + * @brief Check if RXNE IT is enabled + * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_RXNE(SPIx); +} + +/** + * @brief Check if TXE IT is enabled + * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledIT_TXE(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DMA DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_RX(SPIx); +} + +/** + * @brief Disable DMA Rx + * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_RX(SPIx); +} + +/** + * @brief Check if DMA Rx is enabled + * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_RX(SPIx); +} + +/** + * @brief Enable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_EnableDMAReq_TX(SPIx); +} + +/** + * @brief Disable DMA Tx + * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + LL_SPI_DisableDMAReq_TX(SPIx); +} + +/** + * @brief Check if DMA Tx is enabled + * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) +{ + return LL_SPI_IsEnabledDMAReq_TX(SPIx); +} + +/** + * @} + */ + +/** @defgroup I2S_LL_EF_DATA DATA Management + * @{ + */ + +/** + * @brief Read 16-Bits in data register + * @rmtoll DR DR LL_I2S_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) +{ + return LL_SPI_ReceiveData16(SPIx); +} + +/** + * @brief Write 16-Bits in data register + * @rmtoll DR DR LL_I2S_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ + LL_SPI_TransmitData16(SPIx, TxData); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_LL_SPI_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h index d6aed25b..0cb02b05 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_system.h @@ -1,1018 +1,1018 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_system.h - * @author MCD Application Team - * @brief Header file of SYSTEM LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL SYSTEM driver contains a set of generic APIs that can be - used by user: - (+) Some of the FLASH features need to be handled in the SYSTEM file. - (+) Access to DBGCMU registers - (+) Access to SYSCFG registers - - @endverbatim - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_SYSTEM_H -#define __STM32F7xx_LL_SYSTEM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) - -/** @defgroup SYSTEM_LL SYSTEM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants - * @{ - */ - -/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP -* @{ -*/ -#define LL_SYSCFG_REMAP_BOOT0 0x00000000U /*!< Boot information after Reset */ -#define LL_SYSCFG_REMAP_BOOT1 SYSCFG_MEMRMP_MEM_BOOT /*!< Boot information after Reset */ -/** - * @} - */ - - -#if defined(SYSCFG_MEMRMP_SWP_FB) -/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE - * @{ - */ -#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM) - and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/ - -#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_SWP_FB /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM) - and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */ -/** - * @} - */ -#endif /* SYSCFG_MEMRMP_SWP_FB */ - -#if defined(SYSCFG_PMC_MII_RMII_SEL) - /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC -* @{ -*/ -#define LL_SYSCFG_PMC_ETHMII 0x00000000U /*!< ETH Media MII interface */ -#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */ - -/** - * @} - */ -#endif /* SYSCFG_PMC_MII_RMII_SEL */ - -/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS - * @{ - */ -#if defined(SYSCFG_PMC_I2C1_FMP) -#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ -#endif /* SYSCFG_PMC_I2C1_FMP */ -#if defined(SYSCFG_PMC_I2C4_FMP) -#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ -#endif /* SYSCFG_PMC_I2C4_FMP */ -#if defined(SYSCFG_PMC_I2C_PB6_FMP) -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ -#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ -#endif /* SYSCFG_PMC_I2C_PB6_FMP */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT - * @{ - */ -#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ -#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ -#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ -#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ -#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ -#if defined(GPIOF) -#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ -#endif /* GPIOF */ -#if defined(GPIOG) -#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ -#endif /* GPIOG */ -#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ -#if defined(GPIOI) -#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ -#endif /* GPIOI */ -#if defined(GPIOJ) -#define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ -#endif /* GPIOJ */ -#if defined(GPIOK) -#define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ -#endif /* GPIOK */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE - * @{ - */ -#define LL_SYSCFG_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ -#define LL_SYSCFG_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ -#define LL_SYSCFG_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ -#define LL_SYSCFG_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ -#define LL_SYSCFG_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK - * @{ - */ -#if defined(SYSCFG_CBR_CLL) -#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Lockup output (raised during core - lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8 */ -#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIMER1, TIMER8 Break input. - It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits - of the power controller */ -#endif /* SYSCFG_CBR_CLL */ -/** - * @} - */ -/** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD - * @{ - */ -#define LL_SYSCFG_DISABLE_CMP_PD 0x00000000U /*!< I/O compensation cell power-down mode */ -#define LL_SYSCFG_ENABLE_CMP_PD SYSCFG_CMPCR_CMP_PD /*!< I/O compensation cell enabled */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment - * @{ - */ -#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ -#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIIM1 counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */ -#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ -#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ -#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT) -#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */ -#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ -#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ -#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */ -#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP) -#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */ -#endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ -#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ -#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ -#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ -#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY - * @{ - */ -#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ -#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ -#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ -#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ -#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ -#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ -#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ -#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ -#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ -#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ -#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ -#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ -#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ -#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ -#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ -#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions - * @{ - */ - -/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG - * @{ - */ - -/** - * @brief Enables the FMC Memory Mapping Swapping - * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping - * @note SDRAM is accessible at 0x60000000 and NOR/RAM - * is accessible at 0xC0000000 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) -{ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0); -} - -/** - * @brief Disables the FMC Memory Mapping Swapping - * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping - * @note SDRAM is accessible at 0xC0000000 (default mapping) - * and NOR/RAM is accessible at 0x60000000 (default mapping) - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void) -{ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC); -} - -/** - * @brief Enables the Compensation Cell - * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) -{ - SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); -} - -/** - * @brief Disables the Compensation Cell - * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) -{ - CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); -} - -/** - * @brief Get Compensation Cell ready Flag - * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) -{ - return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)); -} - - -/** - * @brief Get the memory boot mapping as configured by user - * @rmtoll SYSCFG_MEMRMP MEM_BOOT LL_SYSCFG_GetRemapMemoryBoot - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_BOOT0 - * @arg @ref LL_SYSCFG_REMAP_BOOT1 - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)); -} - -#if defined(SYSCFG_PMC_MII_RMII_SEL) -/** - * @brief Select Ethernet PHY interface - * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface - * @param Interface This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_PMC_ETHMII - * @arg @ref LL_SYSCFG_PMC_ETHRMII - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) -{ - MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface); -} - -/** - * @brief Get Ethernet PHY interface - * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_PMC_ETHMII - * @arg @ref LL_SYSCFG_PMC_ETHRMII - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); -} -#endif /* SYSCFG_PMC_MII_RMII_SEL */ - - -#if defined(SYSCFG_MEMRMP_SWP_FB) -/** - * @brief Select Flash bank mode (Bank flashed at 0x08000000) - * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode - * @param Bank This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_BANKMODE_BANK1 - * @arg @ref LL_SYSCFG_BANKMODE_BANK2 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) -{ - MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank); -} - -/** - * @brief Get Flash bank mode (Bank flashed at 0x08000000) - * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_BANKMODE_BANK1 - * @arg @ref LL_SYSCFG_BANKMODE_BANK2 - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB)); -} - -#endif /* SYSCFG_MEMRMP_SWP_FB */ - -#if defined(SYSCFG_PMC_I2C1_FMP) -/** - * @brief Enable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n - * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_EnableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*) - * - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - SET_BIT(SYSCFG->PMC, ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n - * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_DisableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 - * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 - * (*) value not defined in all devices - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus); -} -#endif /* SYSCFG_PMC_I2C1_FMP */ - - -/** - * @brief Configure source input for the EXTI external interrupt. - * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n - * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource - * @param Port This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_PORTA - * @arg @ref LL_SYSCFG_EXTI_PORTB - * @arg @ref LL_SYSCFG_EXTI_PORTC - * @arg @ref LL_SYSCFG_EXTI_PORTD - * @arg @ref LL_SYSCFG_EXTI_PORTE - * @arg @ref LL_SYSCFG_EXTI_PORTF - * @arg @ref LL_SYSCFG_EXTI_PORTG - * @arg @ref LL_SYSCFG_EXTI_PORTH - * @arg @ref LL_SYSCFG_EXTI_PORTI - * @arg @ref LL_SYSCFG_EXTI_PORTJ - * @arg @ref LL_SYSCFG_EXTI_PORTK - * - * (*) value not defined in all devices - * @param Line This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_LINE0 - * @arg @ref LL_SYSCFG_EXTI_LINE1 - * @arg @ref LL_SYSCFG_EXTI_LINE2 - * @arg @ref LL_SYSCFG_EXTI_LINE3 - * @arg @ref LL_SYSCFG_EXTI_LINE4 - * @arg @ref LL_SYSCFG_EXTI_LINE5 - * @arg @ref LL_SYSCFG_EXTI_LINE6 - * @arg @ref LL_SYSCFG_EXTI_LINE7 - * @arg @ref LL_SYSCFG_EXTI_LINE8 - * @arg @ref LL_SYSCFG_EXTI_LINE9 - * @arg @ref LL_SYSCFG_EXTI_LINE10 - * @arg @ref LL_SYSCFG_EXTI_LINE11 - * @arg @ref LL_SYSCFG_EXTI_LINE12 - * @arg @ref LL_SYSCFG_EXTI_LINE13 - * @arg @ref LL_SYSCFG_EXTI_LINE14 - * @arg @ref LL_SYSCFG_EXTI_LINE15 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) -{ - MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); -} - -/** - * @brief Get the configured defined for specific EXTI Line - * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n - * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n - * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n - * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource - * @param Line This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_LINE0 - * @arg @ref LL_SYSCFG_EXTI_LINE1 - * @arg @ref LL_SYSCFG_EXTI_LINE2 - * @arg @ref LL_SYSCFG_EXTI_LINE3 - * @arg @ref LL_SYSCFG_EXTI_LINE4 - * @arg @ref LL_SYSCFG_EXTI_LINE5 - * @arg @ref LL_SYSCFG_EXTI_LINE6 - * @arg @ref LL_SYSCFG_EXTI_LINE7 - * @arg @ref LL_SYSCFG_EXTI_LINE8 - * @arg @ref LL_SYSCFG_EXTI_LINE9 - * @arg @ref LL_SYSCFG_EXTI_LINE10 - * @arg @ref LL_SYSCFG_EXTI_LINE11 - * @arg @ref LL_SYSCFG_EXTI_LINE12 - * @arg @ref LL_SYSCFG_EXTI_LINE13 - * @arg @ref LL_SYSCFG_EXTI_LINE14 - * @arg @ref LL_SYSCFG_EXTI_LINE15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_EXTI_PORTA - * @arg @ref LL_SYSCFG_EXTI_PORTB - * @arg @ref LL_SYSCFG_EXTI_PORTC - * @arg @ref LL_SYSCFG_EXTI_PORTD - * @arg @ref LL_SYSCFG_EXTI_PORTE - * @arg @ref LL_SYSCFG_EXTI_PORTF - * @arg @ref LL_SYSCFG_EXTI_PORTG - * @arg @ref LL_SYSCFG_EXTI_PORTH - * @arg @ref LL_SYSCFG_EXTI_PORTI - * @arg @ref LL_SYSCFG_EXTI_PORTJ - * @arg @ref LL_SYSCFG_EXTI_PORTK - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) -{ - return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); -} - -#if defined(SYSCFG_CBR_CLL) -/** - * @brief Set connections to TIM1/8/15/16/17 Break inputs - * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs\n - * SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs - * @param Break This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * @arg @ref LL_SYSCFG_TIMBREAK_PVD - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) -{ - MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break); -} - -/** - * @brief Get connections to TIM1/8/15/16/17 Break inputs - * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs\n - * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs - * @retval Returned value can be can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * @arg @ref LL_SYSCFG_TIMBREAK_PVD - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL)); -} -#endif /* SYSCFG_CBR_CLL */ - -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU - * @{ - */ - -/** - * @brief Return the device identifier - * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449 - * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451 - * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452 - * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); -} - -/** - * @brief Return the device revision identifier - * @note This field indicates the revision of the device. - For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 - * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); -} - -/** - * @brief Enable the Debug Module during SLEEP mode - * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Set Trace pin assignment control - * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n - * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment - * @param PinAssignment This parameter can be one of the following values: - * @arg @ref LL_DBGMCU_TRACE_NONE - * @arg @ref LL_DBGMCU_TRACE_ASYNCH - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) -{ - MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); -} - -/** - * @brief Get Trace pin assignment control - * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n - * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment - * @retval Returned value can be one of the following values: - * @arg @ref LL_DBGMCU_TRACE_NONE - * @arg @ref LL_DBGMCU_TRACE_ASYNCH - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); -} - -/** - * @brief Freeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB1FZ, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n - * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB1FZ, Periphs); -} - -/** - * @brief Freeze APB2 peripherals - * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB2FZ, Periphs); -} - -/** - * @brief Unfreeze APB2 peripherals - * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n - * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB2FZ, Periphs); -} -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_FLASH FLASH - * @{ - */ - -/** - * @brief Set FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency - * @param Latency This parameter can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - * @arg @ref LL_FLASH_LATENCY_3 - * @arg @ref LL_FLASH_LATENCY_4 - * @arg @ref LL_FLASH_LATENCY_5 - * @arg @ref LL_FLASH_LATENCY_6 - * @arg @ref LL_FLASH_LATENCY_7 - * @arg @ref LL_FLASH_LATENCY_8 - * @arg @ref LL_FLASH_LATENCY_9 - * @arg @ref LL_FLASH_LATENCY_10 - * @arg @ref LL_FLASH_LATENCY_11 - * @arg @ref LL_FLASH_LATENCY_12 - * @arg @ref LL_FLASH_LATENCY_13 - * @arg @ref LL_FLASH_LATENCY_14 - * @arg @ref LL_FLASH_LATENCY_15 - * @retval None - */ -__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) -{ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); -} - -/** - * @brief Get FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency - * @retval Returned value can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - * @arg @ref LL_FLASH_LATENCY_3 - * @arg @ref LL_FLASH_LATENCY_4 - * @arg @ref LL_FLASH_LATENCY_5 - * @arg @ref LL_FLASH_LATENCY_6 - * @arg @ref LL_FLASH_LATENCY_7 - * @arg @ref LL_FLASH_LATENCY_8 - * @arg @ref LL_FLASH_LATENCY_9 - * @arg @ref LL_FLASH_LATENCY_10 - * @arg @ref LL_FLASH_LATENCY_11 - * @arg @ref LL_FLASH_LATENCY_12 - * @arg @ref LL_FLASH_LATENCY_13 - * @arg @ref LL_FLASH_LATENCY_14 - * @arg @ref LL_FLASH_LATENCY_15 - */ -__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) -{ - return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); -} - -/** - * @brief Enable Prefetch - * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); -} - -/** - * @brief Disable Prefetch - * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); -} - -/** - * @brief Check if Prefetch buffer is enabled - * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) -{ - return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); -} - - - -/** - * @brief Enable ART Accelerator - * @rmtoll FLASH_ACR ARTEN LL_FLASH_EnableART - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableART(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN); -} - -/** - * @brief Disable ART Accelerator - * @rmtoll FLASH_ACR ARTEN LL_FLASH_DisableART - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisableART(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN); -} - -/** - * @brief Enable ART Reset - * @rmtoll FLASH_ACR ARTRST LL_FLASH_EnableARTReset - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableARTReset(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_ARTRST); -} - -/** - * @brief Disable ART Reset - * @rmtoll FLASH_ACR ARTRST LL_FLASH_DisableARTReset - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisableARTReset(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTRST); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_SYSTEM_H */ - - +/** + ****************************************************************************** + * @file stm32f7xx_ll_system.h + * @author MCD Application Team + * @brief Header file of SYSTEM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL SYSTEM driver contains a set of generic APIs that can be + used by user: + (+) Some of the FLASH features need to be handled in the SYSTEM file. + (+) Access to DBGCMU registers + (+) Access to SYSCFG registers + + @endverbatim + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_SYSTEM_H +#define __STM32F7xx_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP +* @{ +*/ +#define LL_SYSCFG_REMAP_BOOT0 0x00000000U /*!< Boot information after Reset */ +#define LL_SYSCFG_REMAP_BOOT1 SYSCFG_MEMRMP_MEM_BOOT /*!< Boot information after Reset */ +/** + * @} + */ + + +#if defined(SYSCFG_MEMRMP_SWP_FB) +/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE + * @{ + */ +#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM) + and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/ + +#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_SWP_FB /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM) + and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */ +/** + * @} + */ +#endif /* SYSCFG_MEMRMP_SWP_FB */ + +#if defined(SYSCFG_PMC_MII_RMII_SEL) + /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC +* @{ +*/ +#define LL_SYSCFG_PMC_ETHMII 0x00000000U /*!< ETH Media MII interface */ +#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */ + +/** + * @} + */ +#endif /* SYSCFG_PMC_MII_RMII_SEL */ + +/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS + * @{ + */ +#if defined(SYSCFG_PMC_I2C1_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */ +#endif /* SYSCFG_PMC_I2C1_FMP */ +#if defined(SYSCFG_PMC_I2C4_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */ +#endif /* SYSCFG_PMC_I2C4_FMP */ +#if defined(SYSCFG_PMC_I2C_PB6_FMP) +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#endif /* SYSCFG_PMC_I2C_PB6_FMP */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT + * @{ + */ +#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */ +#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */ +#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */ +#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */ +#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */ +#if defined(GPIOF) +#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */ +#endif /* GPIOF */ +#if defined(GPIOG) +#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */ +#endif /* GPIOG */ +#define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */ +#if defined(GPIOI) +#define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */ +#endif /* GPIOI */ +#if defined(GPIOJ) +#define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */ +#endif /* GPIOJ */ +#if defined(GPIOK) +#define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */ +#endif /* GPIOK */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE + * @{ + */ +#define LL_SYSCFG_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ +#define LL_SYSCFG_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ +#define LL_SYSCFG_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ +#define LL_SYSCFG_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ +#define LL_SYSCFG_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK + * @{ + */ +#if defined(SYSCFG_CBR_CLL) +#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Lockup output (raised during core + lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8 */ +#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIMER1, TIMER8 Break input. + It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits + of the power controller */ +#endif /* SYSCFG_CBR_CLL */ +/** + * @} + */ +/** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD + * @{ + */ +#define LL_SYSCFG_DISABLE_CMP_PD 0x00000000U /*!< I/O compensation cell power-down mode */ +#define LL_SYSCFG_ENABLE_CMP_PD SYSCFG_CMPCR_CMP_PD /*!< I/O compensation cell enabled */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment + * @{ + */ +#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ +#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ +#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */ +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ +#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT) +#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */ +#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ +#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */ +#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP) +#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */ +#endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ +#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */ +#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */ +#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */ +#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */ +#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */ +#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ +#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */ +#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */ +#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ +#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ +#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ +#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ +#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ +#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ +#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Enables the FMC Memory Mapping Swapping + * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping + * @note SDRAM is accessible at 0x60000000 and NOR/RAM + * is accessible at 0xC0000000 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0); +} + +/** + * @brief Disables the FMC Memory Mapping Swapping + * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping + * @note SDRAM is accessible at 0xC0000000 (default mapping) + * and NOR/RAM is accessible at 0x60000000 (default mapping) + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC); +} + +/** + * @brief Enables the Compensation Cell + * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void) +{ + SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Disables the Compensation Cell + * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void) +{ + CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Get Compensation Cell ready Flag + * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void) +{ + return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY)); +} + + +/** + * @brief Get the memory boot mapping as configured by user + * @rmtoll SYSCFG_MEMRMP MEM_BOOT LL_SYSCFG_GetRemapMemoryBoot + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_BOOT0 + * @arg @ref LL_SYSCFG_REMAP_BOOT1 + * + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemoryBoot(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)); +} + +#if defined(SYSCFG_PMC_MII_RMII_SEL) +/** + * @brief Select Ethernet PHY interface + * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface + * @param Interface This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_PMC_ETHMII + * @arg @ref LL_SYSCFG_PMC_ETHRMII + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface) +{ + MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface); +} + +/** + * @brief Get Ethernet PHY interface + * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_PMC_ETHMII + * @arg @ref LL_SYSCFG_PMC_ETHRMII + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL)); +} +#endif /* SYSCFG_PMC_MII_RMII_SEL */ + + +#if defined(SYSCFG_MEMRMP_SWP_FB) +/** + * @brief Select Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode + * @param Bank This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank) +{ + MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB, Bank); +} + +/** + * @brief Get Flash bank mode (Bank flashed at 0x08000000) + * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_BANKMODE_BANK1 + * @arg @ref LL_SYSCFG_BANKMODE_BANK2 + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB)); +} + +#endif /* SYSCFG_MEMRMP_SWP_FB */ + +#if defined(SYSCFG_PMC_I2C1_FMP) +/** + * @brief Enable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n + * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_EnableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*) + * + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + SET_BIT(SYSCFG->PMC, ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n + * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_DisableFastModePlus + * @param ConfigFastModePlus This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*) + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 + * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + CLEAR_BIT(SYSCFG->PMC, ConfigFastModePlus); +} +#endif /* SYSCFG_PMC_I2C1_FMP */ + + +/** + * @brief Configure source input for the EXTI external interrupt. + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource + * @param Port This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * + * (*) value not defined in all devices + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line) +{ + MODIFY_REG(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U), Port << POSITION_VAL((Line >> 16U))); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n + * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource + * @param Line This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_LINE0 + * @arg @ref LL_SYSCFG_EXTI_LINE1 + * @arg @ref LL_SYSCFG_EXTI_LINE2 + * @arg @ref LL_SYSCFG_EXTI_LINE3 + * @arg @ref LL_SYSCFG_EXTI_LINE4 + * @arg @ref LL_SYSCFG_EXTI_LINE5 + * @arg @ref LL_SYSCFG_EXTI_LINE6 + * @arg @ref LL_SYSCFG_EXTI_LINE7 + * @arg @ref LL_SYSCFG_EXTI_LINE8 + * @arg @ref LL_SYSCFG_EXTI_LINE9 + * @arg @ref LL_SYSCFG_EXTI_LINE10 + * @arg @ref LL_SYSCFG_EXTI_LINE11 + * @arg @ref LL_SYSCFG_EXTI_LINE12 + * @arg @ref LL_SYSCFG_EXTI_LINE13 + * @arg @ref LL_SYSCFG_EXTI_LINE14 + * @arg @ref LL_SYSCFG_EXTI_LINE15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_EXTI_PORTA + * @arg @ref LL_SYSCFG_EXTI_PORTB + * @arg @ref LL_SYSCFG_EXTI_PORTC + * @arg @ref LL_SYSCFG_EXTI_PORTD + * @arg @ref LL_SYSCFG_EXTI_PORTE + * @arg @ref LL_SYSCFG_EXTI_PORTF + * @arg @ref LL_SYSCFG_EXTI_PORTG + * @arg @ref LL_SYSCFG_EXTI_PORTH + * @arg @ref LL_SYSCFG_EXTI_PORTI + * @arg @ref LL_SYSCFG_EXTI_PORTJ + * @arg @ref LL_SYSCFG_EXTI_PORTK + * (*) value not defined in all devices + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) +{ + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFFU], (Line >> 16U)) >> POSITION_VAL(Line >> 16U)); +} + +#if defined(SYSCFG_CBR_CLL) +/** + * @brief Set connections to TIM1/8/15/16/17 Break inputs + * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs\n + * SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs + * @param Break This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) +{ + MODIFY_REG(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL, Break); +} + +/** + * @brief Get connections to TIM1/8/15/16/17 Break inputs + * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs\n + * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs + * @retval Returned value can be can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP + * @arg @ref LL_SYSCFG_TIMBREAK_PVD + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL | SYSCFG_CBR_PVDL)); +} +#endif /* SYSCFG_CBR_CLL */ + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU + * @{ + */ + +/** + * @brief Return the device identifier + * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449 + * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451 + * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452 + * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @note This field indicates the revision of the device. + For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 + * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Set Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment + * @param PinAssignment This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) +{ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); +} + +/** + * @brief Get Trace pin assignment control + * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n + * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment + * @retval Returned value can be one of the following values: + * @arg @ref LL_DBGMCU_TRACE_NONE + * @arg @ref LL_DBGMCU_TRACE_ASYNCH + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 + * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); +} + +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n + * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) + * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*) + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB1FZ, Periphs); +} + +/** + * @brief Freeze APB2 peripherals + * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APB2FZ, Periphs); +} + +/** + * @brief Unfreeze APB2 peripherals + * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n + * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP + * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP + * + * (*) value not defined in all devices. + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APB2FZ, Periphs); +} +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @arg @ref LL_FLASH_LATENCY_2 + * @arg @ref LL_FLASH_LATENCY_3 + * @arg @ref LL_FLASH_LATENCY_4 + * @arg @ref LL_FLASH_LATENCY_5 + * @arg @ref LL_FLASH_LATENCY_6 + * @arg @ref LL_FLASH_LATENCY_7 + * @arg @ref LL_FLASH_LATENCY_8 + * @arg @ref LL_FLASH_LATENCY_9 + * @arg @ref LL_FLASH_LATENCY_10 + * @arg @ref LL_FLASH_LATENCY_11 + * @arg @ref LL_FLASH_LATENCY_12 + * @arg @ref LL_FLASH_LATENCY_13 + * @arg @ref LL_FLASH_LATENCY_14 + * @arg @ref LL_FLASH_LATENCY_15 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @brief Enable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnablePrefetch(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Disable Prefetch + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisablePrefetch(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN); +} + +/** + * @brief Check if Prefetch buffer is enabled + * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) +{ + return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)); +} + + + +/** + * @brief Enable ART Accelerator + * @rmtoll FLASH_ACR ARTEN LL_FLASH_EnableART + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableART(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ARTEN); +} + +/** + * @brief Disable ART Accelerator + * @rmtoll FLASH_ACR ARTEN LL_FLASH_DisableART + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableART(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTEN); +} + +/** + * @brief Enable ART Reset + * @rmtoll FLASH_ACR ARTRST LL_FLASH_EnableARTReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_EnableARTReset(void) +{ + SET_BIT(FLASH->ACR, FLASH_ACR_ARTRST); +} + +/** + * @brief Disable ART Reset + * @rmtoll FLASH_ACR ARTRST LL_FLASH_DisableARTReset + * @retval None + */ +__STATIC_INLINE void LL_FLASH_DisableARTReset(void) +{ + CLEAR_BIT(FLASH->ACR, FLASH_ACR_ARTRST); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_SYSTEM_H */ + + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h index 6994e0b7..5aa096dd 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_tim.h @@ -1,4737 +1,4737 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_tim.h - * @author MCD Application Team - * @brief Header file of TIM LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_TIM_H -#define __STM32F7xx_LL_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7) - -/** @defgroup TIM_LL TIM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Variables TIM Private Variables - * @{ - */ -static const uint8_t OFFSET_TAB_CCMRx[] = -{ - 0x00U, /* 0: TIMx_CH1 */ - 0x00U, /* 1: TIMx_CH1N */ - 0x00U, /* 2: TIMx_CH2 */ - 0x00U, /* 3: TIMx_CH2N */ - 0x04U, /* 4: TIMx_CH3 */ - 0x04U, /* 5: TIMx_CH3N */ - 0x04U, /* 6: TIMx_CH4 */ - 0x3CU, /* 7: TIMx_CH5 */ - 0x3CU /* 8: TIMx_CH6 */ -}; - -static const uint8_t SHIFT_TAB_OCxx[] = -{ - 0U, /* 0: OC1M, OC1FE, OC1PE */ - 0U, /* 1: - NA */ - 8U, /* 2: OC2M, OC2FE, OC2PE */ - 0U, /* 3: - NA */ - 0U, /* 4: OC3M, OC3FE, OC3PE */ - 0U, /* 5: - NA */ - 8U, /* 6: OC4M, OC4FE, OC4PE */ - 0U, /* 7: OC5M, OC5FE, OC5PE */ - 8U /* 8: OC6M, OC6FE, OC6PE */ -}; - -static const uint8_t SHIFT_TAB_ICxx[] = -{ - 0U, /* 0: CC1S, IC1PSC, IC1F */ - 0U, /* 1: - NA */ - 8U, /* 2: CC2S, IC2PSC, IC2F */ - 0U, /* 3: - NA */ - 0U, /* 4: CC3S, IC3PSC, IC3F */ - 0U, /* 5: - NA */ - 8U, /* 6: CC4S, IC4PSC, IC4F */ - 0U, /* 7: - NA */ - 0U /* 8: - NA */ -}; - -static const uint8_t SHIFT_TAB_CCxP[] = -{ - 0U, /* 0: CC1P */ - 2U, /* 1: CC1NP */ - 4U, /* 2: CC2P */ - 6U, /* 3: CC2NP */ - 8U, /* 4: CC3P */ - 10U, /* 5: CC3NP */ - 12U, /* 6: CC4P */ - 16U, /* 7: CC5P */ - 20U /* 8: CC6P */ -}; - -static const uint8_t SHIFT_TAB_OISx[] = -{ - 0U, /* 0: OIS1 */ - 1U, /* 1: OIS1N */ - 2U, /* 2: OIS2 */ - 3U, /* 3: OIS2N */ - 4U, /* 4: OIS3 */ - 5U, /* 5: OIS3N */ - 6U, /* 6: OIS4 */ - 8U, /* 7: OIS5 */ - 10U /* 8: OIS6 */ -}; -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Constants TIM Private Constants - * @{ - */ - -#if defined(TIM_BREAK_INPUT_SUPPORT) -/* Defines used for the bit position in the register and perform offsets */ -#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) - -/* Generic bit definitions for TIMx_AF1 register */ -#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ -#endif /* TIM_BREAK_INPUT_SUPPORT */ - -/* Remap mask definitions */ -#define TIMx_OR_RMP_SHIFT 16U -#define TIMx_OR_RMP_MASK 0x0000FFFFU -#define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) -#define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) -#define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) - -/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ -#define DT_DELAY_1 ((uint8_t)0x7F) -#define DT_DELAY_2 ((uint8_t)0x3F) -#define DT_DELAY_3 ((uint8_t)0x1F) -#define DT_DELAY_4 ((uint8_t)0x1F) - -/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ -#define DT_RANGE_1 ((uint8_t)0x00) -#define DT_RANGE_2 ((uint8_t)0x80) -#define DT_RANGE_3 ((uint8_t)0xC0) -#define DT_RANGE_4 ((uint8_t)0xE0) - - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Macros TIM Private Macros - * @{ - */ -/** @brief Convert channel id into channel index. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval none - */ -#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ - (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) - -/** @brief Calculate the deadtime sampling period(in ps). - * @param __TIMCLK__ timer input clock frequency (in Hz). - * @param __CKD__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @retval none - */ -#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ - (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ - ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ - ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure - * @{ - */ - -/** - * @brief TIM Time Base configuration structure definition. - */ -typedef struct -{ - uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_SetPrescaler().*/ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_SetCounterMode().*/ - - uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - Some timer instances may support 32 bits counters. In that case this parameter must - be a number between 0x0000 and 0xFFFFFFFF. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_SetAutoReload().*/ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_SetClockDivision().*/ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and - Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and - Max_Data = 0xFFFF. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_SetRepetitionCounter().*/ -} LL_TIM_InitTypeDef; - -/** - * @brief TIM Output Compare configuration structure definition. - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the output mode. - This parameter can be a value of @ref TIM_LL_EC_OCMODE. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_OC_SetMode().*/ - - uint32_t OCState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - - This feature can be modified afterwards using unitary functions - @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ - - uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - - This feature can be modified afterwards using unitary functions - @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ - - uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - - This feature can be modified afterwards using unitary function - LL_TIM_OC_SetCompareCHx (x=1..6).*/ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_OC_SetPolarity().*/ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_OC_SetPolarity().*/ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_OC_SetIdleState().*/ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_OC_SetIdleState().*/ -} LL_TIM_OC_InitTypeDef; - -/** - * @brief TIM Input Capture configuration structure definition. - */ - -typedef struct -{ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t ICActiveInput; /*!< Specifies the input. - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetFilter().*/ -} LL_TIM_IC_InitTypeDef; - - -/** - * @brief TIM Encoder interface configuration structure definition. - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). - This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_SetEncoderMode().*/ - - uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetFilter().*/ - - uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC2Filter; /*!< Specifies the TI2 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetFilter().*/ - -} LL_TIM_ENCODER_InitTypeDef; - -/** - * @brief TIM Hall sensor interface configuration structure definition. - */ -typedef struct -{ - - uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. - Prescaler must be set to get a maximum counter period longer than the - time interval between 2 consecutive changes on the Hall inputs. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of - @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_IC_SetFilter().*/ - - uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. - A positive pulse (TRGO event) is generated with a programmable delay every time - a change occurs on the Hall inputs. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_OC_SetCompareCH2().*/ -} LL_TIM_HALLSENSOR_InitTypeDef; - -/** - * @brief BDTR (Break and Dead Time) structure definition - */ -typedef struct -{ - uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_LL_EC_OSSR - - This feature can be modified afterwards using unitary function - @ref LL_TIM_SetOffStates() - - @note This bit-field cannot be modified as long as LOCK level 2 has been - programmed. */ - - uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_LL_EC_OSSI - - This feature can be modified afterwards using unitary function - @ref LL_TIM_SetOffStates() - - @note This bit-field cannot be modified as long as LOCK level 2 has been - programmed. */ - - uint32_t LockLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - - @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR - register has been written, their content is frozen until the next reset.*/ - - uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. - - This feature can be modified afterwards using unitary function - @ref LL_TIM_OC_SetDeadTime() - - @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been - programmed. */ - - uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE - - This feature can be modified afterwards using unitary functions - @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() - - @note This bit-field can not be modified as long as LOCK level 1 has been - programmed. */ - - uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY - - This feature can be modified afterwards using unitary function - @ref LL_TIM_ConfigBRK() - - @note This bit-field can not be modified as long as LOCK level 1 has been - programmed. */ - - uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. - This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER - - This feature can be modified afterwards using unitary function - @ref LL_TIM_ConfigBRK() - - @note This bit-field can not be modified as long as LOCK level 1 has been - programmed. */ - - uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. - This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE - - This feature can be modified afterwards using unitary functions - @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() - - @note This bit-field can not be modified as long as LOCK level 1 has been - programmed. */ - - uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. - This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY - - This feature can be modified afterwards using unitary function - @ref LL_TIM_ConfigBRK2() - - @note This bit-field can not be modified as long as LOCK level 1 has been - programmed. */ - - uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. - This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER - - This feature can be modified afterwards using unitary function - @ref LL_TIM_ConfigBRK2() - - @note This bit-field can not be modified as long as LOCK level 1 has been - programmed. */ - - uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE - - This feature can be modified afterwards using unitary functions - @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - - @note This bit-field can not be modified as long as LOCK level 1 has been - programmed. */ -} LL_TIM_BDTR_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_TIM_ReadReg function. - * @{ - */ -#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ -#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ -#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ -#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ -#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ -#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ -#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ -#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ -#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ -#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ -#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ -#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ -#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ -#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ -#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ -#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable - * @{ - */ -#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ -#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable - * @{ - */ -#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ -#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable - * @{ - */ -#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup TIM_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. - * @{ - */ -#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ -#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ -#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ -#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ -#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ -#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ -#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ -#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source - * @{ - */ -#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ -#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode - * @{ - */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode - * @{ - */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ -#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ -#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ -#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ -#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division - * @{ - */ -#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ -#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ -#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction - * @{ - */ -#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ -#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source - * @{ - */ -#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ -#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request - * @{ - */ -#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ -#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level - * @{ - */ -#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ -#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ -#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ -#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_CHANNEL Channel - * @{ - */ -#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ -#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ -#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ -#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ -#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ -#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ -#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ -#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ -#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State - * @{ - */ -#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ -#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** Legacy definitions for compatibility purpose -@cond 0 - */ -#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 -#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 -/** -@endcond - */ - -/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode - * @{ - */ -#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ -#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ -#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) - -/** - * @brief Read a value in TIM register. - * @param __INSTANCE__ TIM Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) -/** - * @} - */ - -/** - * @brief HELPER macro retrieving the UIFCPY flag from the counter value. - * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); - * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied - * to TIMx_CNT register bit 31) - * @param __CNT__ Counter value - * @retval UIF status bit - */ -#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ - (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) - -/** - * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. - * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __CKD__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @param __DT__ deadtime duration (in ns) - * @retval DTG[0:7] - */ -#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ - (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ - (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ - (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ - (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ - (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ - (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ - (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ - 0U) - -/** - * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. - * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __CNTCLK__ counter clock frequency (in Hz) - * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) - -/** - * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. - * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __FREQ__ output signal frequency (in Hz) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ - ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) - -/** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare - * active/inactive delay. - * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @retval Compare value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ - ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) - -/** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration - * (when the timer operates in one pulse mode). - * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @param __PULSE__ pulse duration (in us) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) - -/** - * @brief HELPER macro retrieving the ratio of the input capture prescaler - * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); - * @param __ICPSC__ This parameter can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - * @retval Input capture prescaler ratio (1, 2, 4 or 8) - */ -#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ - ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_LL_EF_Time_Base Time Base configuration - * @{ - */ -/** - * @brief Enable timer counter. - * @rmtoll CR1 CEN LL_TIM_EnableCounter - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_CEN); -} - -/** - * @brief Disable timer counter. - * @rmtoll CR1 CEN LL_TIM_DisableCounter - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); -} - -/** - * @brief Indicates whether the timer counter is enabled. - * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable update event generation. - * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); -} - -/** - * @brief Disable update event generation. - * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_UDIS); -} - -/** - * @brief Indicates whether update event generation is enabled. - * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent - * @param TIMx Timer instance - * @retval Inverted state of bit (0 or 1). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); -} - -/** - * @brief Set update event source - * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events - * generate an update interrupt or DMA request if enabled: - * - Counter overflow/underflow - * - Setting the UG bit - * - Update generation through the slave mode controller - * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter - * overflow/underflow generates an update interrupt or DMA request if enabled. - * @rmtoll CR1 URS LL_TIM_SetUpdateSource - * @param TIMx Timer instance - * @param UpdateSource This parameter can be one of the following values: - * @arg @ref LL_TIM_UPDATESOURCE_REGULAR - * @arg @ref LL_TIM_UPDATESOURCE_COUNTER - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); -} - -/** - * @brief Get actual event update source - * @rmtoll CR1 URS LL_TIM_GetUpdateSource - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_UPDATESOURCE_REGULAR - * @arg @ref LL_TIM_UPDATESOURCE_COUNTER - */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); -} - -/** - * @brief Set one pulse mode (one shot v.s. repetitive). - * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode - * @param TIMx Timer instance - * @param OnePulseMode This parameter can be one of the following values: - * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE - * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); -} - -/** - * @brief Get actual one pulse mode. - * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE - * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE - */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); -} - -/** - * @brief Set the timer counter counting mode. - * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to - * check whether or not the counter mode selection feature is supported - * by a timer instance. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n - * CR1 CMS LL_TIM_SetCounterMode - * @param TIMx Timer instance - * @param CounterMode This parameter can be one of the following values: - * @arg @ref LL_TIM_COUNTERMODE_UP - * @arg @ref LL_TIM_COUNTERMODE_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP - * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) -{ - MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); -} - -/** - * @brief Get actual counter mode. - * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to - * check whether or not the counter mode selection feature is supported - * by a timer instance. - * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n - * CR1 CMS LL_TIM_GetCounterMode - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_COUNTERMODE_UP - * @arg @ref LL_TIM_COUNTERMODE_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP - * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN - */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) -{ - uint32_t counter_mode; - - counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); - - if (counter_mode == 0U) - { - counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); - } - - return counter_mode; -} - -/** - * @brief Enable auto-reload (ARR) preload. - * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_ARPE); -} - -/** - * @brief Disable auto-reload (ARR) preload. - * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); -} - -/** - * @brief Indicates whether auto-reload (ARR) preload is enabled. - * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); -} - -/** - * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators - * (when supported) and the digital filters. - * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check - * whether or not the clock division feature is supported by the timer - * instance. - * @rmtoll CR1 CKD LL_TIM_SetClockDivision - * @param TIMx Timer instance - * @param ClockDivision This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); -} - -/** - * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time - * generators (when supported) and the digital filters. - * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check - * whether or not the clock division feature is supported by the timer - * instance. - * @rmtoll CR1 CKD LL_TIM_GetClockDivision - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); -} - -/** - * @brief Set the counter value. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @rmtoll CNT CNT LL_TIM_SetCounter - * @param TIMx Timer instance - * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) -{ - WRITE_REG(TIMx->CNT, Counter); -} - -/** - * @brief Get the counter value. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @rmtoll CNT CNT LL_TIM_GetCounter - * @param TIMx Timer instance - * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) - */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CNT)); -} - -/** - * @brief Get the current direction of the counter - * @rmtoll CR1 DIR LL_TIM_GetDirection - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_COUNTERDIRECTION_UP - * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN - */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); -} - -/** - * @brief Set the prescaler value. - * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). - * @note The prescaler can be changed on the fly as this control register is buffered. The new - * prescaler ratio is taken into account at the next update event. - * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter - * @rmtoll PSC PSC LL_TIM_SetPrescaler - * @param TIMx Timer instance - * @param Prescaler between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) -{ - WRITE_REG(TIMx->PSC, Prescaler); -} - -/** - * @brief Get the prescaler value. - * @rmtoll PSC PSC LL_TIM_GetPrescaler - * @param TIMx Timer instance - * @retval Prescaler value between Min_Data=0 and Max_Data=65535 - */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->PSC)); -} - -/** - * @brief Set the auto-reload value. - * @note The counter is blocked while the auto-reload value is null. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter - * @rmtoll ARR ARR LL_TIM_SetAutoReload - * @param TIMx Timer instance - * @param AutoReload between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) -{ - WRITE_REG(TIMx->ARR, AutoReload); -} - -/** - * @brief Get the auto-reload value. - * @rmtoll ARR ARR LL_TIM_GetAutoReload - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @param TIMx Timer instance - * @retval Auto-reload value - */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->ARR)); -} - -/** - * @brief Set the repetition counter value. - * @note For advanced timer instances RepetitionCounter can be up to 65535. - * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a repetition counter. - * @rmtoll RCR REP LL_TIM_SetRepetitionCounter - * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) -{ - WRITE_REG(TIMx->RCR, RepetitionCounter); -} - -/** - * @brief Get the repetition counter value. - * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a repetition counter. - * @rmtoll RCR REP LL_TIM_GetRepetitionCounter - * @param TIMx Timer instance - * @retval Repetition counter value - */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->RCR)); -} - -/** - * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read - * in an atomic way. - * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); -} - -/** - * @brief Disable update interrupt flag (UIF) remapping. - * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); -} - -/** - * @brief Indicate whether update interrupt flag (UIF) copy is set. - * @param Counter Counter value - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) -{ - return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration - * @{ - */ -/** - * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, - * they are updated only when a commutation event (COM) occurs. - * @note Only on channels that have a complementary output. - * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR2, TIM_CR2_CCPC); -} - -/** - * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); -} - -/** - * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. - * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); -} - -/** - * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). - * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate - * @param TIMx Timer instance - * @param CCUpdateSource This parameter can be one of the following values: - * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY - * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); -} - -/** - * @brief Set the trigger of the capture/compare DMA request. - * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger - * @param TIMx Timer instance - * @param DMAReqTrigger This parameter can be one of the following values: - * @arg @ref LL_TIM_CCDMAREQUEST_CC - * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); -} - -/** - * @brief Get actual trigger of the capture/compare DMA request. - * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_CCDMAREQUEST_CC - * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE - */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); -} - -/** - * @brief Set the lock level to freeze the - * configuration of several capture/compare parameters. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * the lock mechanism is supported by a timer instance. - * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel - * @param TIMx Timer instance - * @param LockLevel This parameter can be one of the following values: - * @arg @ref LL_TIM_LOCKLEVEL_OFF - * @arg @ref LL_TIM_LOCKLEVEL_1 - * @arg @ref LL_TIM_LOCKLEVEL_2 - * @arg @ref LL_TIM_LOCKLEVEL_3 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); -} - -/** - * @brief Enable capture/compare channels. - * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n - * CCER CC1NE LL_TIM_CC_EnableChannel\n - * CCER CC2E LL_TIM_CC_EnableChannel\n - * CCER CC2NE LL_TIM_CC_EnableChannel\n - * CCER CC3E LL_TIM_CC_EnableChannel\n - * CCER CC3NE LL_TIM_CC_EnableChannel\n - * CCER CC4E LL_TIM_CC_EnableChannel\n - * CCER CC5E LL_TIM_CC_EnableChannel\n - * CCER CC6E LL_TIM_CC_EnableChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) -{ - SET_BIT(TIMx->CCER, Channels); -} - -/** - * @brief Disable capture/compare channels. - * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n - * CCER CC1NE LL_TIM_CC_DisableChannel\n - * CCER CC2E LL_TIM_CC_DisableChannel\n - * CCER CC2NE LL_TIM_CC_DisableChannel\n - * CCER CC3E LL_TIM_CC_DisableChannel\n - * CCER CC3NE LL_TIM_CC_DisableChannel\n - * CCER CC4E LL_TIM_CC_DisableChannel\n - * CCER CC5E LL_TIM_CC_DisableChannel\n - * CCER CC6E LL_TIM_CC_DisableChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) -{ - CLEAR_BIT(TIMx->CCER, Channels); -} - -/** - * @brief Indicate whether channel(s) is(are) enabled. - * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n - * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC2E LL_TIM_CC_IsEnabledChannel\n - * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC3E LL_TIM_CC_IsEnabledChannel\n - * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC4E LL_TIM_CC_IsEnabledChannel\n - * CCER CC5E LL_TIM_CC_IsEnabledChannel\n - * CCER CC6E LL_TIM_CC_IsEnabledChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) -{ - return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration - * @{ - */ -/** - * @brief Configure an output channel. - * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n - * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n - * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n - * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n - * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n - * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n - * CCER CC1P LL_TIM_OC_ConfigOutput\n - * CCER CC2P LL_TIM_OC_ConfigOutput\n - * CCER CC3P LL_TIM_OC_ConfigOutput\n - * CCER CC4P LL_TIM_OC_ConfigOutput\n - * CCER CC5P LL_TIM_OC_ConfigOutput\n - * CCER CC6P LL_TIM_OC_ConfigOutput\n - * CR2 OIS1 LL_TIM_OC_ConfigOutput\n - * CR2 OIS2 LL_TIM_OC_ConfigOutput\n - * CR2 OIS3 LL_TIM_OC_ConfigOutput\n - * CR2 OIS4 LL_TIM_OC_ConfigOutput\n - * CR2 OIS5 LL_TIM_OC_ConfigOutput\n - * CR2 OIS6 LL_TIM_OC_ConfigOutput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW - * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); - MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), - (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); - MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), - (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Define the behavior of the output reference signal OCxREF from which - * OCx and OCxN (when relevant) are derived. - * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n - * CCMR1 OC2M LL_TIM_OC_SetMode\n - * CCMR2 OC3M LL_TIM_OC_SetMode\n - * CCMR2 OC4M LL_TIM_OC_SetMode\n - * CCMR3 OC5M LL_TIM_OC_SetMode\n - * CCMR3 OC6M LL_TIM_OC_SetMode - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_TIM_OCMODE_FROZEN - * @arg @ref LL_TIM_OCMODE_ACTIVE - * @arg @ref LL_TIM_OCMODE_INACTIVE - * @arg @ref LL_TIM_OCMODE_TOGGLE - * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE - * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE - * @arg @ref LL_TIM_OCMODE_PWM1 - * @arg @ref LL_TIM_OCMODE_PWM2 - * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 - * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 - * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 - * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); -} - -/** - * @brief Get the output compare mode of an output channel. - * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n - * CCMR1 OC2M LL_TIM_OC_GetMode\n - * CCMR2 OC3M LL_TIM_OC_GetMode\n - * CCMR2 OC4M LL_TIM_OC_GetMode\n - * CCMR3 OC5M LL_TIM_OC_GetMode\n - * CCMR3 OC6M LL_TIM_OC_GetMode - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCMODE_FROZEN - * @arg @ref LL_TIM_OCMODE_ACTIVE - * @arg @ref LL_TIM_OCMODE_INACTIVE - * @arg @ref LL_TIM_OCMODE_TOGGLE - * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE - * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE - * @arg @ref LL_TIM_OCMODE_PWM1 - * @arg @ref LL_TIM_OCMODE_PWM2 - * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 - * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 - * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 - * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); -} - -/** - * @brief Set the polarity of an output channel. - * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n - * CCER CC1NP LL_TIM_OC_SetPolarity\n - * CCER CC2P LL_TIM_OC_SetPolarity\n - * CCER CC2NP LL_TIM_OC_SetPolarity\n - * CCER CC3P LL_TIM_OC_SetPolarity\n - * CCER CC3NP LL_TIM_OC_SetPolarity\n - * CCER CC4P LL_TIM_OC_SetPolarity\n - * CCER CC5P LL_TIM_OC_SetPolarity\n - * CCER CC6P LL_TIM_OC_SetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH - * @arg @ref LL_TIM_OCPOLARITY_LOW - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Get the polarity of an output channel. - * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n - * CCER CC1NP LL_TIM_OC_GetPolarity\n - * CCER CC2P LL_TIM_OC_GetPolarity\n - * CCER CC2NP LL_TIM_OC_GetPolarity\n - * CCER CC3P LL_TIM_OC_GetPolarity\n - * CCER CC3NP LL_TIM_OC_GetPolarity\n - * CCER CC4P LL_TIM_OC_GetPolarity\n - * CCER CC5P LL_TIM_OC_GetPolarity\n - * CCER CC6P LL_TIM_OC_GetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH - * @arg @ref LL_TIM_OCPOLARITY_LOW - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Set the IDLE state of an output channel - * @note This function is significant only for the timer instances - * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) - * can be used to check whether or not a timer instance provides - * a break input. - * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n - * CR2 OIS2N LL_TIM_OC_SetIdleState\n - * CR2 OIS2 LL_TIM_OC_SetIdleState\n - * CR2 OIS2N LL_TIM_OC_SetIdleState\n - * CR2 OIS3 LL_TIM_OC_SetIdleState\n - * CR2 OIS3N LL_TIM_OC_SetIdleState\n - * CR2 OIS4 LL_TIM_OC_SetIdleState\n - * CR2 OIS5 LL_TIM_OC_SetIdleState\n - * CR2 OIS6 LL_TIM_OC_SetIdleState - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param IdleState This parameter can be one of the following values: - * @arg @ref LL_TIM_OCIDLESTATE_LOW - * @arg @ref LL_TIM_OCIDLESTATE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Get the IDLE state of an output channel - * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n - * CR2 OIS2N LL_TIM_OC_GetIdleState\n - * CR2 OIS2 LL_TIM_OC_GetIdleState\n - * CR2 OIS2N LL_TIM_OC_GetIdleState\n - * CR2 OIS3 LL_TIM_OC_GetIdleState\n - * CR2 OIS3N LL_TIM_OC_GetIdleState\n - * CR2 OIS4 LL_TIM_OC_GetIdleState\n - * CR2 OIS5 LL_TIM_OC_GetIdleState\n - * CR2 OIS6 LL_TIM_OC_GetIdleState - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCIDLESTATE_LOW - * @arg @ref LL_TIM_OCIDLESTATE_HIGH - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Enable fast mode for the output channel. - * @note Acts only if the channel is configured in PWM1 or PWM2 mode. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n - * CCMR1 OC2FE LL_TIM_OC_EnableFast\n - * CCMR2 OC3FE LL_TIM_OC_EnableFast\n - * CCMR2 OC4FE LL_TIM_OC_EnableFast\n - * CCMR3 OC5FE LL_TIM_OC_EnableFast\n - * CCMR3 OC6FE LL_TIM_OC_EnableFast - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); - -} - -/** - * @brief Disable fast mode for the output channel. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n - * CCMR1 OC2FE LL_TIM_OC_DisableFast\n - * CCMR2 OC3FE LL_TIM_OC_DisableFast\n - * CCMR2 OC4FE LL_TIM_OC_DisableFast\n - * CCMR3 OC5FE LL_TIM_OC_DisableFast\n - * CCMR3 OC6FE LL_TIM_OC_DisableFast - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); - -} - -/** - * @brief Indicates whether fast mode is enabled for the output channel. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n - * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n - * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n - * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n - * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n - * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Enable compare register (TIMx_CCRx) preload for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n - * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n - * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n - * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n - * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n - * CCMR3 OC6PE LL_TIM_OC_EnablePreload - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Disable compare register (TIMx_CCRx) preload for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n - * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n - * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n - * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n - * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n - * CCMR3 OC6PE LL_TIM_OC_DisablePreload - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n - * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n - * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n - * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n - * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n - * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Enable clearing the output channel on an external event. - * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n - * CCMR1 OC2CE LL_TIM_OC_EnableClear\n - * CCMR2 OC3CE LL_TIM_OC_EnableClear\n - * CCMR2 OC4CE LL_TIM_OC_EnableClear\n - * CCMR3 OC5CE LL_TIM_OC_EnableClear\n - * CCMR3 OC6CE LL_TIM_OC_EnableClear - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Disable clearing the output channel on an external event. - * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n - * CCMR1 OC2CE LL_TIM_OC_DisableClear\n - * CCMR2 OC3CE LL_TIM_OC_DisableClear\n - * CCMR2 OC4CE LL_TIM_OC_DisableClear\n - * CCMR3 OC5CE LL_TIM_OC_DisableClear\n - * CCMR3 OC6CE LL_TIM_OC_DisableClear - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Indicates clearing the output channel on an external event is enabled for the output channel. - * @note This function enables clearing the output channel on an external event. - * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n - * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n - * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n - * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n - * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n - * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of - * the Ocx and OCxN signals). - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * dead-time insertion feature is supported by a timer instance. - * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter - * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime - * @param TIMx Timer instance - * @param DeadTime between Min_Data=0 and Max_Data=255 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); -} - -/** - * @brief Set compare value for output channel 1 (TIMx_CCR1). - * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * output channel 1 is supported by a timer instance. - * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR1, CompareValue); -} - -/** - * @brief Set compare value for output channel 2 (TIMx_CCR2). - * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * output channel 2 is supported by a timer instance. - * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR2, CompareValue); -} - -/** - * @brief Set compare value for output channel 3 (TIMx_CCR3). - * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * output channel is supported by a timer instance. - * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR3, CompareValue); -} - -/** - * @brief Set compare value for output channel 4 (TIMx_CCR4). - * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * output channel 4 is supported by a timer instance. - * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR4, CompareValue); -} - -/** - * @brief Set compare value for output channel 5 (TIMx_CCR5). - * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not - * output channel 5 is supported by a timer instance. - * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); -} - -/** - * @brief Set compare value for output channel 6 (TIMx_CCR6). - * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not - * output channel 6 is supported by a timer instance. - * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR6, CompareValue); -} - -/** - * @brief Get compare value (TIMx_CCR1) set for output channel 1. - * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * output channel 1 is supported by a timer instance. - * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR1)); -} - -/** - * @brief Get compare value (TIMx_CCR2) set for output channel 2. - * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * output channel 2 is supported by a timer instance. - * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR2)); -} - -/** - * @brief Get compare value (TIMx_CCR3) set for output channel 3. - * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * output channel 3 is supported by a timer instance. - * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR3)); -} - -/** - * @brief Get compare value (TIMx_CCR4) set for output channel 4. - * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * output channel 4 is supported by a timer instance. - * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR4)); -} - -/** - * @brief Get compare value (TIMx_CCR5) set for output channel 5. - * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not - * output channel 5 is supported by a timer instance. - * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); -} - -/** - * @brief Get compare value (TIMx_CCR6) set for output channel 6. - * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not - * output channel 6 is supported by a timer instance. - * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR6)); -} - -/** - * @brief Select on which reference signal the OC5REF is combined to. - * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the combined 3-phase PWM mode. - * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n - * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n - * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels - * @param TIMx Timer instance - * @param GroupCH5 This parameter can be a combination of the following values: - * @arg @ref LL_TIM_GROUPCH5_NONE - * @arg @ref LL_TIM_GROUPCH5_OC1REFC - * @arg @ref LL_TIM_GROUPCH5_OC2REFC - * @arg @ref LL_TIM_GROUPCH5_OC3REFC - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) -{ - MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration - * @{ - */ -/** - * @brief Configure input channel. - * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n - * CCMR1 IC1PSC LL_TIM_IC_Config\n - * CCMR1 IC1F LL_TIM_IC_Config\n - * CCMR1 CC2S LL_TIM_IC_Config\n - * CCMR1 IC2PSC LL_TIM_IC_Config\n - * CCMR1 IC2F LL_TIM_IC_Config\n - * CCMR2 CC3S LL_TIM_IC_Config\n - * CCMR2 IC3PSC LL_TIM_IC_Config\n - * CCMR2 IC3F LL_TIM_IC_Config\n - * CCMR2 CC4S LL_TIM_IC_Config\n - * CCMR2 IC4PSC LL_TIM_IC_Config\n - * CCMR2 IC4F LL_TIM_IC_Config\n - * CCER CC1P LL_TIM_IC_Config\n - * CCER CC1NP LL_TIM_IC_Config\n - * CCER CC2P LL_TIM_IC_Config\n - * CCER CC2NP LL_TIM_IC_Config\n - * CCER CC3P LL_TIM_IC_Config\n - * CCER CC3NP LL_TIM_IC_Config\n - * CCER CC4P LL_TIM_IC_Config\n - * CCER CC4NP LL_TIM_IC_Config - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC - * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 - * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 - * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), - ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ - << SHIFT_TAB_ICxx[iChannel]); - MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), - (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Set the active input. - * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n - * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n - * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n - * CCMR2 CC4S LL_TIM_IC_SetActiveInput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICActiveInput This parameter can be one of the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_TRC - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the current active input. - * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n - * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n - * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n - * CCMR2 CC4S LL_TIM_IC_GetActiveInput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_TRC - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the prescaler of input channel. - * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n - * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n - * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n - * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICPrescaler This parameter can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the current prescaler value acting on an input channel. - * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n - * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n - * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n - * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the input filter duration. - * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n - * CCMR1 IC2F LL_TIM_IC_SetFilter\n - * CCMR2 IC3F LL_TIM_IC_SetFilter\n - * CCMR2 IC4F LL_TIM_IC_SetFilter - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICFilter This parameter can be one of the following values: - * @arg @ref LL_TIM_IC_FILTER_FDIV1 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the input filter duration. - * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n - * CCMR1 IC2F LL_TIM_IC_GetFilter\n - * CCMR2 IC3F LL_TIM_IC_GetFilter\n - * CCMR2 IC4F LL_TIM_IC_GetFilter - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_IC_FILTER_FDIV1 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the input channel polarity. - * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n - * CCER CC1NP LL_TIM_IC_SetPolarity\n - * CCER CC2P LL_TIM_IC_SetPolarity\n - * CCER CC2NP LL_TIM_IC_SetPolarity\n - * CCER CC3P LL_TIM_IC_SetPolarity\n - * CCER CC3NP LL_TIM_IC_SetPolarity\n - * CCER CC4P LL_TIM_IC_SetPolarity\n - * CCER CC4NP LL_TIM_IC_SetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_IC_POLARITY_RISING - * @arg @ref LL_TIM_IC_POLARITY_FALLING - * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), - ICPolarity << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Get the current input channel polarity. - * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n - * CCER CC1NP LL_TIM_IC_GetPolarity\n - * CCER CC2P LL_TIM_IC_GetPolarity\n - * CCER CC2NP LL_TIM_IC_GetPolarity\n - * CCER CC3P LL_TIM_IC_GetPolarity\n - * CCER CC3NP LL_TIM_IC_GetPolarity\n - * CCER CC4P LL_TIM_IC_GetPolarity\n - * CCER CC4NP LL_TIM_IC_GetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_IC_POLARITY_RISING - * @arg @ref LL_TIM_IC_POLARITY_FALLING - * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) -{ - uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> - SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). - * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR2, TIM_CR2_TI1S); -} - -/** - * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. - * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); -} - -/** - * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. - * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); -} - -/** - * @brief Get captured value for input channel 1. - * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * input channel 1 is supported by a timer instance. - * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR1)); -} - -/** - * @brief Get captured value for input channel 2. - * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * input channel 2 is supported by a timer instance. - * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR2)); -} - -/** - * @brief Get captured value for input channel 3. - * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * input channel 3 is supported by a timer instance. - * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR3)); -} - -/** - * @brief Get captured value for input channel 4. - * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. - * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a 32 bits counter. - * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * input channel 4 is supported by a timer instance. - * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR4)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection - * @{ - */ -/** - * @brief Enable external clock mode 2. - * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_EnableExternalClock - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); -} - -/** - * @brief Disable external clock mode 2. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_DisableExternalClock - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); -} - -/** - * @brief Indicate whether external clock mode 2 is enabled. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); -} - -/** - * @brief Set the clock source of the counter clock. - * @note when selected clock source is external clock mode 1, the timer input - * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() - * function. This timer input must be configured by calling - * the @ref LL_TIM_IC_Config() function. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode1. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR SMS LL_TIM_SetClockSource\n - * SMCR ECE LL_TIM_SetClockSource - * @param TIMx Timer instance - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL - * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 - * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); -} - -/** - * @brief Set the encoder interface mode. - * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the encoder mode. - * @rmtoll SMCR SMS LL_TIM_SetEncoderMode - * @param TIMx Timer instance - * @param EncoderMode This parameter can be one of the following values: - * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 - * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 - * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration - * @{ - */ -/** - * @brief Set the trigger output (TRGO) used for timer synchronization . - * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance can operate as a master timer. - * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput - * @param TIMx Timer instance - * @param TimerSynchronization This parameter can be one of the following values: - * @arg @ref LL_TIM_TRGO_RESET - * @arg @ref LL_TIM_TRGO_ENABLE - * @arg @ref LL_TIM_TRGO_UPDATE - * @arg @ref LL_TIM_TRGO_CC1IF - * @arg @ref LL_TIM_TRGO_OC1REF - * @arg @ref LL_TIM_TRGO_OC2REF - * @arg @ref LL_TIM_TRGO_OC3REF - * @arg @ref LL_TIM_TRGO_OC4REF - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); -} - -/** - * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . - * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance can be used for ADC synchronization. - * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 - * @param TIMx Timer Instance - * @param ADCSynchronization This parameter can be one of the following values: - * @arg @ref LL_TIM_TRGO2_RESET - * @arg @ref LL_TIM_TRGO2_ENABLE - * @arg @ref LL_TIM_TRGO2_UPDATE - * @arg @ref LL_TIM_TRGO2_CC1F - * @arg @ref LL_TIM_TRGO2_OC1 - * @arg @ref LL_TIM_TRGO2_OC2 - * @arg @ref LL_TIM_TRGO2_OC3 - * @arg @ref LL_TIM_TRGO2_OC4 - * @arg @ref LL_TIM_TRGO2_OC5 - * @arg @ref LL_TIM_TRGO2_OC6 - * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING - * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING - * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING - * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING - * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING - * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); -} - -/** - * @brief Set the synchronization mode of a slave timer. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR SMS LL_TIM_SetSlaveMode - * @param TIMx Timer instance - * @param SlaveMode This parameter can be one of the following values: - * @arg @ref LL_TIM_SLAVEMODE_DISABLED - * @arg @ref LL_TIM_SLAVEMODE_RESET - * @arg @ref LL_TIM_SLAVEMODE_GATED - * @arg @ref LL_TIM_SLAVEMODE_TRIGGER - * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); -} - -/** - * @brief Set the selects the trigger input to be used to synchronize the counter. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR TS LL_TIM_SetTriggerInput - * @param TIMx Timer instance - * @param TriggerInput This parameter can be one of the following values: - * @arg @ref LL_TIM_TS_ITR0 - * @arg @ref LL_TIM_TS_ITR1 - * @arg @ref LL_TIM_TS_ITR2 - * @arg @ref LL_TIM_TS_ITR3 - * @arg @ref LL_TIM_TS_TI1F_ED - * @arg @ref LL_TIM_TS_TI1FP1 - * @arg @ref LL_TIM_TS_TI2FP2 - * @arg @ref LL_TIM_TS_ETRF - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); -} - -/** - * @brief Enable the Master/Slave mode. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); -} - -/** - * @brief Disable the Master/Slave mode. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); -} - -/** - * @brief Indicates whether the Master/Slave mode is enabled. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); -} - -/** - * @brief Configure the external trigger (ETR) input. - * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an external trigger input. - * @rmtoll SMCR ETP LL_TIM_ConfigETR\n - * SMCR ETPS LL_TIM_ConfigETR\n - * SMCR ETF LL_TIM_ConfigETR - * @param TIMx Timer instance - * @param ETRPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED - * @arg @ref LL_TIM_ETR_POLARITY_INVERTED - * @param ETRPrescaler This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 - * @param ETRFilter This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_FILTER_FDIV1 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, - uint32_t ETRFilter) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Break_Function Break function configuration - * @{ - */ -/** - * @brief Enable the break function. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR BKE LL_TIM_EnableBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); -} - -/** - * @brief Disable the break function. - * @rmtoll BDTR BKE LL_TIM_DisableBRK - * @param TIMx Timer instance - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); -} - -/** - * @brief Configure the break input. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n - * BDTR BKF LL_TIM_ConfigBRK - * @param TIMx Timer instance - * @param BreakPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_POLARITY_LOW - * @arg @ref LL_TIM_BREAK_POLARITY_HIGH - * @param BreakFilter This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, - uint32_t BreakFilter) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); -} - -/** - * @brief Enable the break 2 function. - * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a second break input. - * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); -} - -/** - * @brief Disable the break 2 function. - * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a second break input. - * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); -} - -/** - * @brief Configure the break 2 input. - * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a second break input. - * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n - * BDTR BK2F LL_TIM_ConfigBRK2 - * @param TIMx Timer instance - * @param Break2Polarity This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK2_POLARITY_LOW - * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH - * @param Break2Filter This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); -} - -/** - * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n - * BDTR OSSR LL_TIM_SetOffStates - * @param TIMx Timer instance - * @param OffStateIdle This parameter can be one of the following values: - * @arg @ref LL_TIM_OSSI_DISABLE - * @arg @ref LL_TIM_OSSI_ENABLE - * @param OffStateRun This parameter can be one of the following values: - * @arg @ref LL_TIM_OSSR_DISABLE - * @arg @ref LL_TIM_OSSR_ENABLE - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); -} - -/** - * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); -} - -/** - * @brief Disable automatic output (MOE can be set only by software). - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); -} - -/** - * @brief Indicate whether automatic output is enabled. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); -} - -/** - * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). - * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by - * software and is reset in case of break or break2 event - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); -} - -/** - * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). - * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by - * software and is reset in case of break or break2 event. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); -} - -/** - * @brief Indicates whether outputs are enabled. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); -} - -#if defined(TIM_BREAK_INPUT_SUPPORT) -/** - * @brief Enable the signals connected to the designated timer break input. - * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether - * or not a timer instance allows for break input selection. - * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n - * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n - * AF2 BK2INE LL_TIM_EnableBreakInputSource\n - * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource - * @param TIMx Timer instance - * @param BreakInput This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 - * @param Source This parameter can be one of the following values: - * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) -{ - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); - SET_BIT(*pReg, Source); -} - -/** - * @brief Disable the signals connected to the designated timer break input. - * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether - * or not a timer instance allows for break input selection. - * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n - * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n - * AF2 BK2INE LL_TIM_DisableBreakInputSource\n - * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource - * @param TIMx Timer instance - * @param BreakInput This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 - * @param Source This parameter can be one of the following values: - * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) -{ - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); - CLEAR_BIT(*pReg, Source); -} - -/** - * @brief Set the polarity of the break signal for the timer break input. - * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether - * or not a timer instance allows for break input selection. - * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n - * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n - * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n - * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity - * @param TIMx Timer instance - * @param BreakInput This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_INPUT_BKIN - * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 - * @param Source This parameter can be one of the following values: - * @arg @ref LL_TIM_BKIN_SOURCE_BKIN - * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_TIM_BKIN_POLARITY_LOW - * @arg @ref LL_TIM_BKIN_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, - uint32_t Polarity) -{ - __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); - MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); -} -#endif /* TIM_BREAK_INPUT_SUPPORT */ -/** - * @} - */ - -/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration - * @{ - */ -/** - * @brief Configures the timer DMA burst feature. - * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or - * not a timer instance supports the DMA burst mode. - * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n - * DCR DBA LL_TIM_ConfigDMABurst - * @param TIMx Timer instance - * @param DMABurstBaseAddress This parameter can be one of the following values: - * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR - * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER - * @arg @ref LL_TIM_DMABURST_BASEADDR_SR - * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER - * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT - * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC - * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR - * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 - * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR - * @arg @ref LL_TIM_DMABURST_BASEADDR_OR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) - * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) - * (*) value not defined in all devices - * @param DMABurstLength This parameter can be one of the following values: - * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER - * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) -{ - MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping - * @{ - */ -/** - * @brief Remap TIM inputs (input channel, internal/external triggers). - * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not - * a some timer inputs can be remapped. - * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n - * TIM5_OR TI4_RMP LL_TIM_SetRemap\n - * TIM11_OR TI1_RMP LL_TIM_SetRemap - * @param TIMx Timer instance - * @param Remap Remap param depends on the TIMx. Description available only - * in CHM version of the User Manual (not in .pdf). - * Otherwise see Reference Manual description of OR registers. - * - * Below description summarizes "Timer Instance" and "Remap" param combinations: - * - * TIM2: one of the following values - * - * ITR1_RMP can be one of the following values - * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO - * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP - * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF - * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF - * - * TIM5: one of the following values - * - * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO - * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI - * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE - * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC - * - * TIM11: one of the following values - * - * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO - * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX - * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE - * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 - * - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) -{ - MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management - * @{ - */ -/** - * @brief Clear the update interrupt flag (UIF). - * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); -} - -/** - * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). - * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). - * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); -} - -/** - * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). - * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). - * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); -} - -/** - * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). - * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). - * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); -} - -/** - * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). - * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). - * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); -} - -/** - * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). - * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). - * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); -} - -/** - * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). - * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). - * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); -} - -/** - * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). - * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the commutation interrupt flag (COMIF). - * @rmtoll SR COMIF LL_TIM_ClearFlag_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); -} - -/** - * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). - * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the trigger interrupt flag (TIF). - * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); -} - -/** - * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). - * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the break interrupt flag (BIF). - * @rmtoll SR BIF LL_TIM_ClearFlag_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); -} - -/** - * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). - * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the break 2 interrupt flag (B2IF). - * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); -} - -/** - * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). - * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). - * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); -} - -/** - * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set - * (Capture/Compare 1 interrupt is pending). - * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). - * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); -} - -/** - * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set - * (Capture/Compare 2 over-capture interrupt is pending). - * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). - * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); -} - -/** - * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set - * (Capture/Compare 3 over-capture interrupt is pending). - * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). - * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); -} - -/** - * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set - * (Capture/Compare 4 over-capture interrupt is pending). - * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the system break interrupt flag (SBIF). - * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); -} - -/** - * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). - * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_IT_Management IT-Management - * @{ - */ -/** - * @brief Enable update interrupt (UIE). - * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_UIE); -} - -/** - * @brief Disable update interrupt (UIE). - * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); -} - -/** - * @brief Indicates whether the update interrupt (UIE) is enabled. - * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 1 interrupt (CC1IE). - * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); -} - -/** - * @brief Disable capture/compare 1 interrupt (CC1IE). - * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); -} - -/** - * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. - * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 2 interrupt (CC2IE). - * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); -} - -/** - * @brief Disable capture/compare 2 interrupt (CC2IE). - * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); -} - -/** - * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. - * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 3 interrupt (CC3IE). - * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); -} - -/** - * @brief Disable capture/compare 3 interrupt (CC3IE). - * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); -} - -/** - * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. - * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 4 interrupt (CC4IE). - * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); -} - -/** - * @brief Disable capture/compare 4 interrupt (CC4IE). - * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); -} - -/** - * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. - * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable commutation interrupt (COMIE). - * @rmtoll DIER COMIE LL_TIM_EnableIT_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_COMIE); -} - -/** - * @brief Disable commutation interrupt (COMIE). - * @rmtoll DIER COMIE LL_TIM_DisableIT_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); -} - -/** - * @brief Indicates whether the commutation interrupt (COMIE) is enabled. - * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable trigger interrupt (TIE). - * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_TIE); -} - -/** - * @brief Disable trigger interrupt (TIE). - * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); -} - -/** - * @brief Indicates whether the trigger interrupt (TIE) is enabled. - * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable break interrupt (BIE). - * @rmtoll DIER BIE LL_TIM_EnableIT_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_BIE); -} - -/** - * @brief Disable break interrupt (BIE). - * @rmtoll DIER BIE LL_TIM_DisableIT_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); -} - -/** - * @brief Indicates whether the break interrupt (BIE) is enabled. - * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_DMA_Management DMA Management - * @{ - */ -/** - * @brief Enable update DMA request (UDE). - * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_UDE); -} - -/** - * @brief Disable update DMA request (UDE). - * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); -} - -/** - * @brief Indicates whether the update DMA request (UDE) is enabled. - * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 1 DMA request (CC1DE). - * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); -} - -/** - * @brief Disable capture/compare 1 DMA request (CC1DE). - * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); -} - -/** - * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. - * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 2 DMA request (CC2DE). - * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); -} - -/** - * @brief Disable capture/compare 2 DMA request (CC2DE). - * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); -} - -/** - * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. - * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 3 DMA request (CC3DE). - * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); -} - -/** - * @brief Disable capture/compare 3 DMA request (CC3DE). - * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); -} - -/** - * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. - * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 4 DMA request (CC4DE). - * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); -} - -/** - * @brief Disable capture/compare 4 DMA request (CC4DE). - * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); -} - -/** - * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. - * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable commutation DMA request (COMDE). - * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_COMDE); -} - -/** - * @brief Disable commutation DMA request (COMDE). - * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); -} - -/** - * @brief Indicates whether the commutation DMA request (COMDE) is enabled. - * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); -} - -/** - * @brief Enable trigger interrupt (TDE). - * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_TDE); -} - -/** - * @brief Disable trigger interrupt (TDE). - * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); -} - -/** - * @brief Indicates whether the trigger interrupt (TDE) is enabled. - * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management - * @{ - */ -/** - * @brief Generate an update event. - * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_UG); -} - -/** - * @brief Generate Capture/Compare 1 event. - * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC1G); -} - -/** - * @brief Generate Capture/Compare 2 event. - * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC2G); -} - -/** - * @brief Generate Capture/Compare 3 event. - * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC3G); -} - -/** - * @brief Generate Capture/Compare 4 event. - * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC4G); -} - -/** - * @brief Generate commutation event. - * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_COMG); -} - -/** - * @brief Generate trigger event. - * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_TG); -} - -/** - * @brief Generate break event. - * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_BG); -} - -/** - * @brief Generate break 2 event. - * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_B2G); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions - * @{ - */ - -ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); -void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); -void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); -void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_TIM_H */ +/** + ****************************************************************************** + * @file stm32f7xx_ll_tim.h + * @author MCD Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_TIM_H +#define __STM32F7xx_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U, /* 6: TIMx_CH4 */ + 0x3CU, /* 7: TIMx_CH5 */ + 0x3CU /* 8: TIMx_CH6 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U, /* 6: OC4M, OC4FE, OC4PE */ + 0U, /* 7: OC5M, OC5FE, OC5PE */ + 8U /* 8: OC6M, OC6FE, OC6PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U, /* 6: CC4S, IC4PSC, IC4F */ + 0U, /* 7: - NA */ + 0U /* 8: - NA */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U, /* 6: CC4P */ + 16U, /* 7: CC5P */ + 20U /* 8: CC6P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U, /* 6: OIS4 */ + 8U, /* 7: OIS5 */ + 10U /* 8: OIS6 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + +#if defined(TIM_BREAK_INPUT_SUPPORT) +/* Defines used for the bit position in the register and perform offsets */ +#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL) + +/* Generic bit definitions for TIMx_AF1 register */ +#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */ +#endif /* TIM_BREAK_INPUT_SUPPORT */ + +/* Remap mask definitions */ +#define TIMx_OR_RMP_SHIFT 16U +#define TIMx_OR_RMP_MASK 0x0000FFFFU +#define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) +#define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) +#define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ + + uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. + This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER + + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK2() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ +#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable + * @{ + */ +#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ +#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */ +#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ +#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ +#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ +#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division + * @{ + */ +#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ +#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction + * @{ + */ +#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ +#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source + * @{ + */ +#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ +#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request + * @{ + */ +#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ +#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level + * @{ + */ +#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ +#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_CHANNEL Channel + * @{ + */ +#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ +#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ +#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ +#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ +#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ +#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ +#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ +#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ +#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State + * @{ + */ +#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ +#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** Legacy definitions for compatibility purpose +@cond 0 + */ +#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1 +#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2 +/** +@endcond + */ + +/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode + * @{ + */ +#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** + * @brief HELPER macro retrieving the UIFCPY flag from the counter value. + * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); + * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied + * to TIMx_CNT register bit 31) + * @param __CNT__ Counter value + * @retval UIF status bit + */ +#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ + (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) +{ + uint32_t counter_mode; + + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); + + if (counter_mode == 0U) + { + counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); + } + + return counter_mode; +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note For advanced timer instances RepetitionCounter can be up to 65535. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). + * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read + * in an atomic way. + * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Disable update interrupt flag (UIF) remapping. + * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) copy is set. + * @param Counter Counter value + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter) +{ + return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} + +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel\n + * CCER CC5E LL_TIM_CC_EnableChannel\n + * CCER CC6E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel\n + * CCER CC5E LL_TIM_CC_DisableChannel\n + * CCER CC6E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel\n + * CCER CC5E LL_TIM_CC_IsEnabledChannel\n + * CCER CC6E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n + * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CCER CC5P LL_TIM_OC_ConfigOutput\n + * CCER CC6P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput\n + * CR2 OIS5 LL_TIM_OC_ConfigOutput\n + * CR2 OIS6 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode\n + * CCMR3 OC5M LL_TIM_OC_SetMode\n + * CCMR3 OC6M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode\n + * CCMR3 OC5M LL_TIM_OC_GetMode\n + * CCMR3 OC6M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 + * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 + * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity\n + * CCER CC5P LL_TIM_OC_SetPolarity\n + * CCER CC6P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity\n + * CCER CC5P LL_TIM_OC_GetPolarity\n + * CCER CC6P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState\n + * CR2 OIS5 LL_TIM_OC_SetIdleState\n + * CR2 OIS6 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState\n + * CR2 OIS5 LL_TIM_OC_GetIdleState\n + * CR2 OIS6 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast\n + * CCMR3 OC5FE LL_TIM_OC_EnableFast\n + * CCMR3 OC6FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast\n + * CCMR3 OC5FE LL_TIM_OC_DisableFast\n + * CCMR3 OC6FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n + * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n + * CCMR3 OC6PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n + * CCMR3 OC6PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n + * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear\n + * CCMR3 OC5CE LL_TIM_OC_EnableClear\n + * CCMR3 OC6CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear\n + * CCMR3 OC5CE LL_TIM_OC_DisableClear\n + * CCMR3 OC6CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n + * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @arg @ref LL_TIM_CHANNEL_CH5 + * @arg @ref LL_TIM_CHANNEL_CH6 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Set compare value for output channel 5 (TIMx_CCR5). + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue); +} + +/** + * @brief Set compare value for output channel 6 (TIMx_CCR6). + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR6, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @brief Get compare value (TIMx_CCR5) set for output channel 5. + * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not + * output channel 5 is supported by a timer instance. + * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5)); +} + +/** + * @brief Get compare value (TIMx_CCR6) set for output channel 6. + * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not + * output channel 6 is supported by a timer instance. + * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR6)); +} + +/** + * @brief Select on which reference signal the OC5REF is combined to. + * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the combined 3-phase PWM mode. + * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n + * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels + * @param TIMx Timer instance + * @param GroupCH5 This parameter can be a combination of the following values: + * @arg @ref LL_TIM_GROUPCH5_NONE + * @arg @ref LL_TIM_GROUPCH5_OC1REFC + * @arg @ref LL_TIM_GROUPCH5_OC2REFC + * @arg @ref LL_TIM_GROUPCH5_OC3REFC + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) +{ + MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * CCER CC4NP LL_TIM_IC_Config + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * CCER CC4NP LL_TIM_IC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * CCER CC4NP LL_TIM_IC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) +{ + uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. + * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a 32 bits counter. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . + * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can be used for ADC synchronization. + * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 + * @param TIMx Timer Instance + * @param ADCSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO2_RESET + * @arg @ref LL_TIM_TRGO2_ENABLE + * @arg @ref LL_TIM_TRGO2_UPDATE + * @arg @ref LL_TIM_TRGO2_CC1F + * @arg @ref LL_TIM_TRGO2_OC1 + * @arg @ref LL_TIM_TRGO2_OC2 + * @arg @ref LL_TIM_TRGO2_OC3 + * @arg @ref LL_TIM_TRGO2_OC4 + * @arg @ref LL_TIM_TRGO2_OC5 + * @arg @ref LL_TIM_TRGO2_OC6 + * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING + * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n + * BDTR BKF LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @param BreakFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, + uint32_t BreakFilter) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); +} + +/** + * @brief Enable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Disable the break 2 function. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); +} + +/** + * @brief Configure the break 2 input. + * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a second break input. + * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n + * BDTR BK2F LL_TIM_ConfigBRK2 + * @param TIMx Timer instance + * @param Break2Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_POLARITY_LOW + * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH + * @param Break2Filter This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +#if defined(TIM_BREAK_INPUT_SUPPORT) +/** + * @brief Enable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n + * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n + * AF2 BK2INE LL_TIM_EnableBreakInputSource\n + * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + SET_BIT(*pReg, Source); +} + +/** + * @brief Disable the signals connected to the designated timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n + * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n + * AF2 BK2INE LL_TIM_DisableBreakInputSource\n + * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + CLEAR_BIT(*pReg, Source); +} + +/** + * @brief Set the polarity of the break signal for the timer break input. + * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether + * or not a timer instance allows for break input selection. + * @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n + * AF1 BKDFBKP LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n + * AF2 BK2DFBKP LL_TIM_SetBreakInputSourcePolarity + * @param TIMx Timer instance + * @param BreakInput This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_INPUT_BKIN + * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 + * @param Source This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_SOURCE_BKIN + * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BKIN_POLARITY_LOW + * @arg @ref LL_TIM_BKIN_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, + uint32_t Polarity) +{ + __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput)); + MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); +} +#endif /* TIM_BREAK_INPUT_SUPPORT */ +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @arg @ref LL_TIM_DMABURST_BASEADDR_OR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1 (*) + * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2 (*) + * (*) value not defined in all devices + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping + * @{ + */ +/** + * @brief Remap TIM inputs (input channel, internal/external triggers). + * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not + * a some timer inputs can be remapped. + * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n + * TIM5_OR TI4_RMP LL_TIM_SetRemap\n + * TIM11_OR TI1_RMP LL_TIM_SetRemap + * @param TIMx Timer instance + * @param Remap Remap param depends on the TIMx. Description available only + * in CHM version of the User Manual (not in .pdf). + * Otherwise see Reference Manual description of OR registers. + * + * Below description summarizes "Timer Instance" and "Remap" param combinations: + * + * TIM2: one of the following values + * + * ITR1_RMP can be one of the following values + * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO + * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF + * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF + * + * TIM5: one of the following values + * + * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO + * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI + * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE + * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC + * + * TIM11: one of the following values + * + * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO + * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX + * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE + * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1 + * + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) +{ + MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). + * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); +} + +/** + * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). + * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). + * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); +} + +/** + * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). + * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break 2 interrupt flag (B2IF). + * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); +} + +/** + * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). + * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the system break interrupt flag (SBIF). + * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); +} + +/** + * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). + * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_DMA_Management DMA Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @brief Generate break 2 event. + * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_B2G); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_TIM_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h index daa329e4..582ee952 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usart.h @@ -1,3804 +1,3804 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_usart.h - * @author MCD Application Team - * @brief Header file of USART LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_USART_H -#define STM32F7xx_LL_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ - || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) - -/** @defgroup USART_LL USART - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Constants USART Private Constants - * @{ - */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_Private_Macros USART Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_ES_INIT USART Exported Init structures - * @{ - */ - -/** - * @brief LL USART Init Structure definition - */ -typedef struct -{ - - uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetBaudRate().*/ - - uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetDataWidth().*/ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_LL_EC_STOPBITS. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetStopBitsLength().*/ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_LL_EC_PARITY. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetParity().*/ - - uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_DIRECTION. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetTransferDirection().*/ - - uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetHWFlowCtrl().*/ - - uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. - This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetOverSampling().*/ - -} LL_USART_InitTypeDef; - -/** - * @brief LL USART Clock Init Structure definition - */ -typedef struct -{ - uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_CLOCK. - - USART HW configuration can be modified afterwards using unitary functions - @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). - For more details, refer to description of this function. */ - - uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_LL_EC_POLARITY. - - USART HW configuration can be modified afterwards using unitary - functions @ref LL_USART_SetClockPolarity(). - For more details, refer to description of this function. */ - - uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_LL_EC_PHASE. - - USART HW configuration can be modified afterwards using unitary - functions @ref LL_USART_SetClockPhase(). - For more details, refer to description of this function. */ - - uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - - USART HW configuration can be modified afterwards using unitary - functions @ref LL_USART_SetLastClkPulseOutput(). - For more details, refer to description of this function. */ - -} LL_USART_ClockInitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Constants USART Exported Constants - * @{ - */ - -/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_USART_WriteReg function - * @{ - */ -#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ -#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ -#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected clear flag */ -#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ -#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ -#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ -#if defined(USART_TCBGT_SUPPORT) -#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ -#endif /* USART_TCBGT_SUPPORT */ -#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ -#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ -#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ -#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ -#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_USART_ReadReg function - * @{ - */ -#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ -#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ -#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ -#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ -#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ -#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ -#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ -#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ -#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ -#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ -#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ -#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ -#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ -#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ -#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ -#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ -#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ -#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ -#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ -#if defined(USART_ISR_REACK) -#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ -#endif /* USART_ISR_REACK */ -#if defined(USART_TCBGT_SUPPORT) -#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ -#endif /* USART_TCBGT_SUPPORT */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions - * @{ - */ -#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ -#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ -#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ -#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ -#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ -#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ -#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -#if defined(USART_TCBGT_SUPPORT) -#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ -#endif /* USART_TCBGT_SUPPORT */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DIRECTION Communication Direction - * @{ - */ -#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PARITY Parity Control - * @{ - */ -#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_WAKEUP Wakeup - * @{ - */ -#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ -#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DATAWIDTH Datawidth - * @{ - */ -#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling - * @{ - */ -#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EC_CLOCK Clock Signal - * @{ - */ - -#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ -#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse - * @{ - */ -#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ -#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PHASE Clock Phase - * @{ - */ -#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ -#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ -#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_STOPBITS Stop Bits - * @{ - */ -#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ -#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ -#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap - * @{ - */ -#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ -#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion - * @{ - */ -#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ -#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion - * @{ - */ -#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ -#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion - * @{ - */ -#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ -#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_BITORDER Bit Order - * @{ - */ -#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ -#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection - * @{ - */ -#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ -#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ -#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ -#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection - * @{ - */ -#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ -#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_HWCONTROL Hardware Control - * @{ - */ -#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ -/** - * @} - */ - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUS) -/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation - * @{ - */ -#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ -#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ -#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ -/** - * @} - */ - -#endif /* USART_CR3_WUS */ -#endif /* USART_CR1_UESM */ -/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power - * @{ - */ -#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ -#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length - * @{ - */ -#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ -#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity - * @{ - */ -#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ -#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data - * @{ - */ -#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Macros USART Exported Macros - * @{ - */ - -/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper - * @{ - */ - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case - */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case - */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USART_LL_Exported_Functions USART Exported Functions - * @{ - */ - -/** @defgroup USART_LL_EF_Configuration Configuration functions - * @{ - */ - -/** - * @brief USART Enable - * @rmtoll CR1 UE LL_USART_Enable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief USART Disable (all USART prescalers and outputs are disabled) - * @note When USART is disabled, USART prescalers and outputs are stopped immediately, - * and current operations are discarded. The configuration of the USART is kept, but all the status - * flags, in the USARTx_ISR are set to their default values. - * @rmtoll CR1 UE LL_USART_Disable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief Indicate if USART is enabled - * @rmtoll CR1 UE LL_USART_IsEnabled - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); -} - -#if defined(USART_CR1_UESM) -/** - * @brief USART enabled in STOP Mode. - * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that - * USART clock selection is HSI or LSE in RCC. - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_EnableInStopMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); -} - -/** - * @brief USART disabled in STOP Mode. - * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_DisableInStopMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); -} - -/** - * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); -} - -#if defined(USART_CR3_UCESM) -/** - * @brief USART Clock enabled in STOP Mode - * @note When this function is called, USART Clock is enabled while in STOP mode - * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); -} - -/** - * @brief USART clock disabled in STOP Mode - * @note When this function is called, USART Clock is disabled while in STOP mode - * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); -} - -/** - * @brief Indicate if USART clock is enabled in STOP Mode - * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); -} - -#endif /* USART_CR3_UCESM */ -#endif /* USART_CR1_UESM*/ -/** - * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) - * @rmtoll CR1 RE LL_USART_EnableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Receiver Disable - * @rmtoll CR1 RE LL_USART_DisableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Transmitter Enable - * @rmtoll CR1 TE LL_USART_EnableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Transmitter Disable - * @rmtoll CR1 TE LL_USART_DisableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Configure simultaneously enabled/disabled states - * of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_SetTransferDirection\n - * CR1 TE LL_USART_SetTransferDirection - * @param USARTx USART Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) -{ - ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); -} - -/** - * @brief Return enabled/disabled states of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_GetTransferDirection\n - * CR1 TE LL_USART_GetTransferDirection - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); -} - -/** - * @brief Configure Parity (enabled/disabled and parity mode if enabled). - * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. - * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position - * (9th or 8th bit depending on data width) and parity is checked on the received data. - * @rmtoll CR1 PS LL_USART_SetParity\n - * CR1 PCE LL_USART_SetParity - * @param USARTx USART Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @retval None - */ -__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); -} - -/** - * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) - * @rmtoll CR1 PS LL_USART_GetParity\n - * CR1 PCE LL_USART_GetParity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - */ -__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); -} - -/** - * @brief Set Receiver Wake Up method from Mute mode. - * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod - * @param USARTx USART Instance - * @param Method This parameter can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - * @retval None - */ -__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); -} - -/** - * @brief Return Receiver Wake Up method from Mute mode - * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); -} - -/** - * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M0 LL_USART_SetDataWidth\n - * CR1 M1 LL_USART_SetDataWidth - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); -} - -/** - * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M0 LL_USART_GetDataWidth\n - * CR1 M1 LL_USART_GetDataWidth - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); -} - -/** - * @brief Allow switch between Mute Mode and Active mode - * @rmtoll CR1 MME LL_USART_EnableMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); -} - -/** - * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. - * @rmtoll CR1 MME LL_USART_DisableMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); -} - -/** - * @brief Indicate if switch between Mute Mode and Active mode is allowed - * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); -} - -/** - * @brief Set Oversampling to 8-bit or 16-bit mode - * @rmtoll CR1 OVER8 LL_USART_SetOverSampling - * @param USARTx USART Instance - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); -} - -/** - * @brief Return Oversampling mode - * @rmtoll CR1 OVER8 LL_USART_GetOverSampling - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); -} - -/** - * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput - * @param USARTx USART Instance - * @param LastBitClockPulse This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); -} - -/** - * @brief Retrieve Clock pulse of the last data bit output configuration - * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); -} - -/** - * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_SetClockPhase - * @param USARTx USART Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); -} - -/** - * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_GetClockPhase - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); -} - -/** - * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_SetClockPolarity - * @param USARTx USART Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); -} - -/** - * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_GetClockPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); -} - -/** - * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function - * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function - * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function - * @rmtoll CR2 CPHA LL_USART_ConfigClock\n - * CR2 CPOL LL_USART_ConfigClock\n - * CR2 LBCL LL_USART_ConfigClock - * @param USARTx USART Instance - * @param Phase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @param LBCPOutput This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); -} - -/** - * @brief Enable Clock output on SCLK pin - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Disable Clock output on SCLK pin - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); -} - -/** - * @brief Set the length of the stop bits - * @rmtoll CR2 STOP LL_USART_SetStopBitsLength - * @param USARTx USART Instance - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Retrieve the length of the stop bits - * @rmtoll CR2 STOP LL_USART_GetStopBitsLength - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); -} - -/** - * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) - * @note Call of this function is equivalent to following function call sequence : - * - Data Width configuration using @ref LL_USART_SetDataWidth() function - * - Parity Control and mode configuration using @ref LL_USART_SetParity() function - * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function - * @rmtoll CR1 PS LL_USART_ConfigCharacter\n - * CR1 PCE LL_USART_ConfigCharacter\n - * CR1 M0 LL_USART_ConfigCharacter\n - * CR1 M1 LL_USART_ConfigCharacter\n - * CR2 STOP LL_USART_ConfigCharacter - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, - uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Configure TX/RX pins swapping setting. - * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap - * @param USARTx USART Instance - * @param SwapConfig This parameter can be one of the following values: - * @arg @ref LL_USART_TXRX_STANDARD - * @arg @ref LL_USART_TXRX_SWAPPED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); -} - -/** - * @brief Retrieve TX/RX pins swapping configuration. - * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_TXRX_STANDARD - * @arg @ref LL_USART_TXRX_SWAPPED - */ -__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); -} - -/** - * @brief Configure RX pin active level logic - * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel - * @param USARTx USART Instance - * @param PinInvMethod This parameter can be one of the following values: - * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); -} - -/** - * @brief Retrieve RX pin active level logic configuration - * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED - */ -__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); -} - -/** - * @brief Configure TX pin active level logic - * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel - * @param USARTx USART Instance - * @param PinInvMethod This parameter can be one of the following values: - * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); -} - -/** - * @brief Retrieve TX pin active level logic configuration - * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED - */ -__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); -} - -/** - * @brief Configure Binary data logic. - * @note Allow to define how Logical data from the data register are send/received : - * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) - * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic - * @param USARTx USART Instance - * @param DataLogic This parameter can be one of the following values: - * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE - * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); -} - -/** - * @brief Retrieve Binary data configuration - * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE - * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE - */ -__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); -} - -/** - * @brief Configure transfer bit order (either Less or Most Significant Bit First) - * @note MSB First means data is transmitted/received with the MSB first, following the start bit. - * LSB First means data is transmitted/received with data bit 0 first, following the start bit. - * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder - * @param USARTx USART Instance - * @param BitOrder This parameter can be one of the following values: - * @arg @ref LL_USART_BITORDER_LSBFIRST - * @arg @ref LL_USART_BITORDER_MSBFIRST - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); -} - -/** - * @brief Return transfer bit order (either Less or Most Significant Bit First) - * @note MSB First means data is transmitted/received with the MSB first, following the start bit. - * LSB First means data is transmitted/received with data bit 0 first, following the start bit. - * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_BITORDER_LSBFIRST - * @arg @ref LL_USART_BITORDER_MSBFIRST - */ -__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); -} - -/** - * @brief Enable Auto Baud-Rate Detection - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_ABREN); -} - -/** - * @brief Disable Auto Baud-Rate Detection - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); -} - -/** - * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); -} - -/** - * @brief Set Auto Baud-Rate mode bits - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode - * @param USARTx USART Instance - * @param AutoBaudRateMode This parameter can be one of the following values: - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME - * @retval None - */ -__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); -} - -/** - * @brief Return Auto Baud-Rate mode - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME - */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); -} - -/** - * @brief Enable Receiver Timeout - * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_RTOEN); -} - -/** - * @brief Disable Receiver Timeout - * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); -} - -/** - * @brief Indicate if Receiver Timeout feature is enabled - * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); -} - -/** - * @brief Set Address of the USART node. - * @note This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with address mark detection. - * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. - * (b7-b4 should be set to 0) - * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. - * (This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with 7-bit address mark detection. - * The MSB of the character sent by the transmitter should be equal to 1. - * It may also be used for character detection during normal reception, - * Mute mode inactive (for example, end of block detection in ModBus protocol). - * In this case, the whole received character (8-bit) is compared to the ADD[7:0] - * value and CMF flag is set on match) - * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n - * CR2 ADDM7 LL_USART_ConfigNodeAddress - * @param USARTx USART Instance - * @param AddressLen This parameter can be one of the following values: - * @arg @ref LL_USART_ADDRESS_DETECT_4B - * @arg @ref LL_USART_ADDRESS_DETECT_7B - * @param NodeAddress 4 or 7 bit Address of the USART node. - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, - (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); -} - -/** - * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. - * @note If 4-bit Address Detection is selected in ADDM7, - * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) - * If 7-bit Address Detection is selected in ADDM7, - * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) - * @rmtoll CR2 ADD LL_USART_GetNodeAddress - * @param USARTx USART Instance - * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) - */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); -} - -/** - * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) - * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_ADDRESS_DETECT_4B - * @arg @ref LL_USART_ADDRESS_DETECT_7B - */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); -} - -/** - * @brief Enable RTS HW Flow Control - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Disable RTS HW Flow Control - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Enable CTS HW Flow Control - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Disable CTS HW Flow Control - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n - * CR3 CTSE LL_USART_SetHWFlowCtrl - * @param USARTx USART Instance - * @param HardwareFlowControl This parameter can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - * @retval None - */ -__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); -} - -/** - * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n - * CR3 CTSE LL_USART_GetHWFlowCtrl - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); -} - -/** - * @brief Enable One bit sampling method - * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); -} - -/** - * @brief Disable One bit sampling method - * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); -} - -/** - * @brief Indicate if One bit sampling method is enabled - * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); -} - -/** - * @brief Enable Overrun detection - * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); -} - -/** - * @brief Disable Overrun detection - * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); -} - -/** - * @brief Indicate if Overrun detection is enabled - * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); -} - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUS) -/** - * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUS LL_USART_SetWKUPType - * @param USARTx USART Instance - * @param Type This parameter can be one of the following values: - * @arg @ref LL_USART_WAKEUP_ON_ADDRESS - * @arg @ref LL_USART_WAKEUP_ON_STARTBIT - * @arg @ref LL_USART_WAKEUP_ON_RXNE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); -} - -/** - * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUS LL_USART_GetWKUPType - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_WAKEUP_ON_ADDRESS - * @arg @ref LL_USART_WAKEUP_ON_STARTBIT - * @arg @ref LL_USART_WAKEUP_ON_RXNE - */ -__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); -} - -#endif /* USART_CR3_WUS */ -#endif /* USART_CR1_UESM */ -/** - * @brief Configure USART BRR register for achieving expected Baud Rate value. - * @note Compute and set USARTDIV value in BRR Register (full BRR content) - * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values - * @note Peripheral clock and Baud rate values provided as function parameters should be valid - * (Baud rate value != 0) - * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. - * @rmtoll BRR BRR LL_USART_SetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @param BaudRate Baud Rate - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, - uint32_t BaudRate) -{ - uint32_t usartdiv; - uint32_t brrtemp; - - if (OverSampling == LL_USART_OVERSAMPLING_8) - { - usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); - brrtemp = usartdiv & 0xFFF0U; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - USARTx->BRR = brrtemp; - } - else - { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); - } -} - -/** - * @brief Return current Baud Rate value, according to USARTDIV present in BRR register - * (full BRR content), and to used Peripheral Clock and Oversampling mode values - * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. - * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. - * @rmtoll BRR BRR LL_USART_GetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval Baud Rate - */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) -{ - uint32_t usartdiv; - uint32_t brrresult = 0x0U; - - usartdiv = USARTx->BRR; - - if (usartdiv == 0U) - { - /* Do not perform a division by 0 */ - } - else if (OverSampling == LL_USART_OVERSAMPLING_8) - { - usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; - if (usartdiv != 0U) - { - brrresult = (PeriphClk * 2U) / usartdiv; - } - } - else - { - if ((usartdiv & 0xFFFFU) != 0U) - { - brrresult = PeriphClk / usartdiv; - } - } - return (brrresult); -} - -/** - * @brief Set Receiver Time Out Value (expressed in nb of bits duration) - * @rmtoll RTOR RTO LL_USART_SetRxTimeout - * @param USARTx USART Instance - * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) -{ - MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); -} - -/** - * @brief Get Receiver Time Out Value (expressed in nb of bits duration) - * @rmtoll RTOR RTO LL_USART_GetRxTimeout - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF - */ -__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); -} - -/** - * @brief Set Block Length value in reception - * @rmtoll RTOR BLEN LL_USART_SetBlockLength - * @param USARTx USART Instance - * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) -{ - MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); -} - -/** - * @brief Get Block Length value in reception - * @rmtoll RTOR BLEN LL_USART_GetBlockLength - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature - * @{ - */ - -/** - * @brief Enable IrDA mode - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_EnableIrda - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Disable IrDA mode - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_DisableIrda - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Indicate if IrDA mode is enabled - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_IsEnabledIrda - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); -} - -/** - * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode - * @param USARTx USART Instance - * @param PowerMode This parameter can be one of the following values: - * @arg @ref LL_USART_IRDA_POWER_NORMAL - * @arg @ref LL_USART_IRDA_POWER_LOW - * @retval None - */ -__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); -} - -/** - * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_IRDA_POWER_NORMAL - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); -} - -/** - * @brief Set Irda prescaler value, used for dividing the USART clock source - * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler - * @param USARTx USART Instance - * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); -} - -/** - * @brief Return Irda prescaler value, used for dividing the USART clock source - * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler - * @param USARTx USART Instance - * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) - */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature - * @{ - */ - -/** - * @brief Enable Smartcard NACK transmission - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_NACK); -} - -/** - * @brief Disable Smartcard NACK transmission - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); -} - -/** - * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); -} - -/** - * @brief Enable Smartcard mode - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_EnableSmartcard - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Disable Smartcard mode - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_DisableSmartcard - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Indicate if Smartcard mode is enabled - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); -} - -/** - * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. - * In transmission mode, it specifies the number of automatic retransmission retries, before - * generating a transmission error (FE bit set). - * In reception mode, it specifies the number or erroneous reception trials, before generating a - * reception error (RXNE and PE bits set) - * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount - * @param USARTx USART Instance - * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); -} - -/** - * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount - * @param USARTx USART Instance - * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); -} - -/** - * @brief Set Smartcard prescaler value, used for dividing the USART clock - * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler - * @param USARTx USART Instance - * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); -} - -/** - * @brief Return Smartcard prescaler value, used for dividing the USART clock - * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler - * @param USARTx USART Instance - * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); -} - -/** - * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods - * (GT[7:0] bits : Guard time value) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime - * @param USARTx USART Instance - * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); -} - -/** - * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods - * (GT[7:0] bits : Guard time value) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime - * @param USARTx USART Instance - * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature - * @{ - */ - -/** - * @brief Enable Single Wire Half-Duplex mode - * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Disable Single Wire Half-Duplex mode - * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature - * @{ - */ - -/** - * @brief Set LIN Break Detection Length - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen - * @param USARTx USART Instance - * @param LINBDLength This parameter can be one of the following values: - * @arg @ref LL_USART_LINBREAK_DETECT_10B - * @arg @ref LL_USART_LINBREAK_DETECT_11B - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); -} - -/** - * @brief Return LIN Break Detection Length - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LINBREAK_DETECT_10B - * @arg @ref LL_USART_LINBREAK_DETECT_11B - */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); -} - -/** - * @brief Enable LIN mode - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_EnableLIN - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Disable LIN mode - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_DisableLIN - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Indicate if LIN mode is enabled - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature - * @{ - */ - -/** - * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime - * @param USARTx USART Instance - * @param Time Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); -} - -/** - * @brief Return DEDT (Driver Enable De-Assertion Time) - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime - * @param USARTx USART Instance - * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 - */ -__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); -} - -/** - * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime - * @param USARTx USART Instance - * @param Time Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); -} - -/** - * @brief Return DEAT (Driver Enable Assertion Time) - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime - * @param USARTx USART Instance - * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 - */ -__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); -} - -/** - * @brief Enable Driver Enable (DE) Mode - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_EnableDEMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DEM); -} - -/** - * @brief Disable Driver Enable (DE) Mode - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_DisableDEMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); -} - -/** - * @brief Indicate if Driver Enable (DE) Mode is enabled - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); -} - -/** - * @brief Select Driver Enable Polarity - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity - * @param USARTx USART Instance - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_DE_POLARITY_HIGH - * @arg @ref LL_USART_DE_POLARITY_LOW - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); -} - -/** - * @brief Return Driver Enable Polarity - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DE_POLARITY_HIGH - * @arg @ref LL_USART_DE_POLARITY_LOW - */ -__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services - * @{ - */ - -/** - * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) - * @note In UART mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Asynchronous Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n - * CR2 CLKEN LL_USART_ConfigAsyncMode\n - * CR3 SCEN LL_USART_ConfigAsyncMode\n - * CR3 IREN LL_USART_ConfigAsyncMode\n - * CR3 HDSEL LL_USART_ConfigAsyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) -{ - /* In Asynchronous mode, the following bits must be kept cleared: - - LINEN, CLKEN bits in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Synchronous Mode - * @note In Synchronous mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also sets the USART in Synchronous mode. - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * @note Other remaining configurations items related to Synchronous Mode - * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n - * CR2 CLKEN LL_USART_ConfigSyncMode\n - * CR3 SCEN LL_USART_ConfigSyncMode\n - * CR3 IREN LL_USART_ConfigSyncMode\n - * CR3 HDSEL LL_USART_ConfigSyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) -{ - /* In Synchronous mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); - /* set the UART/USART in Synchronous mode */ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in LIN Mode - * @note In LIN mode, the following bits must be kept cleared: - * - STOP and CLKEN bits in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also set the UART/USART in LIN mode. - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function - * @note Other remaining configurations items related to LIN Mode - * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using - * dedicated functions - * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n - * CR2 STOP LL_USART_ConfigLINMode\n - * CR2 LINEN LL_USART_ConfigLINMode\n - * CR3 IREN LL_USART_ConfigLINMode\n - * CR3 SCEN LL_USART_ConfigLINMode\n - * CR3 HDSEL LL_USART_ConfigLINMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) -{ - /* In LIN mode, the following bits must be kept cleared: - - STOP and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); - /* Set the UART/USART in LIN mode */ - SET_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode - * @note In Half Duplex mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * This function also sets the UART/USART in Half Duplex mode. - * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function - * @note Other remaining configurations items related to Half Duplex Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n - * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n - * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n - * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n - * CR3 IREN LL_USART_ConfigHalfDuplexMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) -{ - /* In Half Duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); - /* set the UART/USART in Half Duplex mode */ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Smartcard Mode - * @note In Smartcard mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also configures Stop bits to 1.5 bits and - * sets the USART in Smartcard mode (SCEN bit). - * Clock Output is also enabled (CLKEN). - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function - * @note Other remaining configurations items related to Smartcard Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n - * CR2 STOP LL_USART_ConfigSmartcardMode\n - * CR2 CLKEN LL_USART_ConfigSmartcardMode\n - * CR3 HDSEL LL_USART_ConfigSmartcardMode\n - * CR3 SCEN LL_USART_ConfigSmartcardMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) -{ - /* In Smartcard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register, - - IREN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); - /* Configure Stop bits to 1.5 bits */ - /* Synchronous mode is activated by default */ - SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); - /* set the UART/USART in Smartcard mode */ - SET_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Irda Mode - * @note In IRDA mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - STOP and CLKEN bits in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function - * @note Other remaining configurations items related to Irda Mode - * (as Baud Rate, Word length, Power mode, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n - * CR2 CLKEN LL_USART_ConfigIrdaMode\n - * CR2 STOP LL_USART_ConfigIrdaMode\n - * CR3 SCEN LL_USART_ConfigIrdaMode\n - * CR3 HDSEL LL_USART_ConfigIrdaMode\n - * CR3 IREN LL_USART_ConfigIrdaMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) -{ - /* In IRDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); - /* set the UART/USART in IRDA mode */ - SET_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Multi processor Mode - * (several USARTs connected in a network, one of the USARTs can be the master, - * its TX output connected to the RX inputs of the other slaves USARTs). - * @note In MultiProcessor mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Multi processor Mode - * (as Baud Rate, Wake Up Method, Node address, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n - * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n - * CR3 SCEN LL_USART_ConfigMultiProcessMode\n - * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n - * CR3 IREN LL_USART_ConfigMultiProcessMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) -{ - /* In Multi Processor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if the USART Parity Error Flag is set or not - * @rmtoll ISR PE LL_USART_IsActiveFlag_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Framing Error Flag is set or not - * @rmtoll ISR FE LL_USART_IsActiveFlag_FE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Noise error detected Flag is set or not - * @rmtoll ISR NE LL_USART_IsActiveFlag_NE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART OverRun Error Flag is set or not - * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART IDLE line detected Flag is set or not - * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Read Data Register Not Empty Flag is set or not - * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Transmission Complete Flag is set or not - * @rmtoll ISR TC LL_USART_IsActiveFlag_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Transmit Data Register Empty Flag is set or not - * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART CTS interrupt Flag is set or not - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART CTS Flag is set or not - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Receiver Time Out Flag is set or not - * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART End Of Block Flag is set or not - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Auto-Baud Rate Error Flag is set or not - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Auto-Baud Rate Flag is set or not - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Busy Flag is set or not - * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Character Match Flag is set or not - * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Send Break Flag is set or not - * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not - * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); -} - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -/** - * @brief Check if the USART Wake Up from stop mode Flag is set or not - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); -} - -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -/** - * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not - * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); -} - -#if defined(USART_ISR_REACK) -/** - * @brief Check if the USART Receive Enable Acknowledge Flag is set or not - * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); -} - -#endif /* USART_ISR_REACK */ -#if defined(USART_TCBGT_SUPPORT) -/* Function available only on devices supporting Transmit Complete before Guard Time feature */ -/** - * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not - * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); -} - -#endif /* USART_TCBGT_SUPPORT */ -/** - * @brief Clear Parity Error Flag - * @rmtoll ICR PECF LL_USART_ClearFlag_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_PECF); -} - -/** - * @brief Clear Framing Error Flag - * @rmtoll ICR FECF LL_USART_ClearFlag_FE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_FECF); -} - -/** - * @brief Clear Noise Error detected Flag - * @rmtoll ICR NCF LL_USART_ClearFlag_NE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_NCF); -} - -/** - * @brief Clear OverRun Error Flag - * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_ORECF); -} - -/** - * @brief Clear IDLE line detected Flag - * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); -} - -/** - * @brief Clear Transmission Complete Flag - * @rmtoll ICR TCCF LL_USART_ClearFlag_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_TCCF); -} - -#if defined(USART_TCBGT_SUPPORT) -/* Function available only on devices supporting Transmit Complete before Guard Time feature */ -/** - * @brief Clear Smartcard Transmission Complete Before Guard Time Flag - * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); -} -#endif /* USART_TCBGT_SUPPORT */ - -/** - * @brief Clear LIN Break Detection Flag - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); -} - -/** - * @brief Clear CTS Interrupt Flag - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); -} - -/** - * @brief Clear Receiver Time Out Flag - * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); -} - -/** - * @brief Clear End Of Block Flag - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); -} - -/** - * @brief Clear Character Match Flag - * @rmtoll ICR CMCF LL_USART_ClearFlag_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_CMCF); -} - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -/** - * @brief Clear Wake Up from stop mode Flag - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_WUCF); -} - -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -/** - * @} - */ - -/** @defgroup USART_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -/** - * @brief Enable RX Not Empty Interrupt - * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); -} - -/** - * @brief Enable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_EnableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -/** - * @brief Enable TX Empty Interrupt - * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); -} - -/** - * @brief Enable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_EnableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Enable Character Match Interrupt - * @rmtoll CR1 CMIE LL_USART_EnableIT_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); -} - -/** - * @brief Enable Receiver Timeout Interrupt - * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); -} - -/** - * @brief Enable End Of Block Interrupt - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); -} - -/** - * @brief Enable LIN Break Detection Interrupt - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_LBDIE); -} - -/** - * @brief Enable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. - * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Enable CTS Interrupt - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -/** - * @brief Enable Wake Up from Stop Mode Interrupt - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); -} - -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -#if defined(USART_TCBGT_SUPPORT) -/* Function available only on devices supporting Transmit Complete before Guard Time feature */ -/** - * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); -} -#endif /* USART_TCBGT_SUPPORT */ - -/** - * @brief Disable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -/** - * @brief Disable RX Not Empty Interrupt - * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); -} - -/** - * @brief Disable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_DisableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -/** - * @brief Disable TX Empty Interrupt - * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); -} - -/** - * @brief Disable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_DisableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Disable Character Match Interrupt - * @rmtoll CR1 CMIE LL_USART_DisableIT_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); -} - -/** - * @brief Disable Receiver Timeout Interrupt - * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); -} - -/** - * @brief Disable End Of Block Interrupt - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); -} - -/** - * @brief Disable LIN Break Detection Interrupt - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); -} - -/** - * @brief Disable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. - * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Disable CTS Interrupt - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -/** - * @brief Disable Wake Up from Stop Mode Interrupt - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); -} - -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -#if defined(USART_TCBGT_SUPPORT) -/* Function available only on devices supporting Transmit Complete before Guard Time feature */ -/** - * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); -} -#endif /* USART_TCBGT_SUPPORT */ - -/** - * @brief Check if the USART IDLE Interrupt source is enabled or disabled. - * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. - * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); -} - -/** - * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. - * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART TX Empty Interrupt is enabled or disabled. - * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); -} - -/** - * @brief Check if the USART Parity Error Interrupt is enabled or disabled. - * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Character Match Interrupt is enabled or disabled. - * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. - * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART End Of Block Interrupt is enabled or disabled. - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Error Interrupt is enabled or disabled. - * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); -} - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) -/** - * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); -} - -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ -#if defined(USART_TCBGT_SUPPORT) -/* Function available only on devices supporting Transmit Complete before Guard Time feature */ -/** - * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); -} -#endif /* USART_TCBGT_SUPPORT */ - -/** - * @} - */ - -/** @defgroup USART_LL_EF_DMA_Management DMA_Management - * @{ - */ - -/** - * @brief Enable DMA Mode for reception - * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Disable DMA Mode for reception - * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Check if DMA Mode is enabled for reception - * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Disable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Check if DMA Mode is enabled for transmission - * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Disabling on Reception Error - * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DDRE); -} - -/** - * @brief Disable DMA Disabling on Reception Error - * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); -} - -/** - * @brief Indicate if DMA Disabling on Reception Error is disabled - * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); -} - -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n - * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr - * @param USARTx USART Instance - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT - * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) -{ - uint32_t data_reg_addr; - - if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) - { - /* return address of TDR register */ - data_reg_addr = (uint32_t) &(USARTx->TDR); - } - else - { - /* return address of RDR register */ - data_reg_addr = (uint32_t) &(USARTx->RDR); - } - - return data_reg_addr; -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Read Receiver Data register (Receive Data value, 8 bits) - * @rmtoll RDR RDR LL_USART_ReceiveData8 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) -{ - return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); -} - -/** - * @brief Read Receiver Data register (Receive Data value, 9 bits) - * @rmtoll RDR RDR LL_USART_ReceiveData9 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x1FF - */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) -{ - return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) - * @rmtoll TDR TDR LL_USART_TransmitData8 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) -{ - USARTx->TDR = Value; -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) - * @rmtoll TDR TDR LL_USART_TransmitData9 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) -{ - USARTx->TDR = (uint16_t)(Value & 0x1FFUL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Execution Execution - * @{ - */ - -/** - * @brief Request an Automatic Baud Rate measurement on next received data frame - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); -} - -/** - * @brief Request Break sending - * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); -} - -/** - * @brief Put USART in mute mode and set the RWU flag - * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); -} - -/** - * @brief Request a Receive Data flush - * @note Allows to discard the received data without reading them, and avoid an overrun - * condition. - * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); -} - -/** - * @brief Request a Transmit data flush - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions - * @{ - */ -ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); -void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_USART_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_LL_USART_H +#define STM32F7xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ + || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NCF USART_ICR_NCF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#if defined(USART_TCBGT_SUPPORT) +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#endif /* USART_TCBGT_SUPPORT */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#if defined(USART_ISR_REACK) +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#endif /* USART_ISR_REACK */ +#if defined(USART_TCBGT_SUPPORT) +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#endif /* USART_TCBGT_SUPPORT */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +#if defined(USART_TCBGT_SUPPORT) +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#endif /* USART_TCBGT_SUPPORT */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUS) +/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +#endif /* USART_CR3_WUS */ +#endif /* USART_CR1_UESM */ +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__PERIPHCLK__)*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +#if defined(USART_CR1_UESM) +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +#if defined(USART_CR3_UCESM) +/** + * @brief USART Clock enabled in STOP Mode + * @note When this function is called, USART Clock is enabled while in STOP mode + * @rmtoll CR3 UCESM LL_USART_EnableClockInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableClockInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief USART clock disabled in STOP Mode + * @note When this function is called, USART Clock is disabled while in STOP mode + * @rmtoll CR3 UCESM LL_USART_DisableClockInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableClockInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_UCESM); +} + +/** + * @brief Indicate if USART clock is enabled in STOP Mode + * @rmtoll CR3 UCESM LL_USART_IsClockEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsClockEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); +} + +#endif /* USART_CR3_UCESM */ +#endif /* USART_CR1_UESM*/ +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUS) +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_SetWKUPType + * @param USARTx USART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_GetWKUPType + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +} + +#endif /* USART_CR3_WUS */ +#endif /* USART_CR1_UESM */ +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, + uint32_t BaudRate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (PeriphClk * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Read Data Register Not Empty Flag is set or not + * @rmtoll ISR RXNE LL_USART_IsActiveFlag_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Data Register Empty Flag is set or not + * @rmtoll ISR TXE LL_USART_IsActiveFlag_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +/** + * @brief Check if the USART Wake Up from stop mode Flag is set or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +#if defined(USART_ISR_REACK) +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +#endif /* USART_ISR_REACK */ +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +#endif /* USART_TCBGT_SUPPORT */ +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NCF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NCF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} +#endif /* USART_TCBGT_SUPPORT */ + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +/** + * @brief Clear Wake Up from stop mode Flag + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +} + +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Enable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Enable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} +#endif /* USART_TCBGT_SUPPORT */ + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Disable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Disable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} +#endif /* USART_TCBGT_SUPPORT */ + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)) ? 1U : 0U); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX Empty Interrupt is enabled or disabled. + * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)) ? 1U : 0U); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) +/** + * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ +#if defined(USART_TCBGT_SUPPORT) +/* Function available only on devices supporting Transmit Complete before Guard Time feature */ +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} +#endif /* USART_TCBGT_SUPPORT */ + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data flush + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32F7xx_LL_USART_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h index 044395ad..20dfaf98 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_usb.h @@ -1,600 +1,600 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_usb.h - * @author MCD Application Team - * @brief Header file of USB Low Layer HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_USB_H -#define STM32F7xx_LL_USB_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal_def.h" - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup USB_LL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -#ifndef HAL_USB_TIMEOUT -#define HAL_USB_TIMEOUT 0xF000000U -#endif /* define HAL_USB_TIMEOUT */ - -#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS -#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U -#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ - -/** - * @brief USB Mode definition - */ - -typedef enum -{ - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 -} USB_ModeTypeDef; - -/** - * @brief URB States definition - */ -typedef enum -{ - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_NYET, - URB_ERROR, - URB_STALL -} USB_URBStateTypeDef; - -/** - * @brief Host channel States definition - */ -typedef enum -{ - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_ACK, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR -} USB_HCStateTypeDef; - - -/** - * @brief USB Instance Initialization Structure definition - */ -typedef struct -{ - uint8_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t dma_enable; /*!< USB DMA state. - If DMA is not supported this parameter shall be set by default to zero */ - - uint8_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - - uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - - uint8_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - - uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - - uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - - uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - - uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - - uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - - uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ - -} USB_CfgTypeDef; - -typedef struct -{ - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_iso_incomplete; /*!< Endpoint isoc condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_LL_EP_Type */ - - uint8_t data_pid_start; /*!< Initial data PID - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - - uint8_t even_odd_frame; /*!< IFrame parity - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint16_t tx_fifo_num; /*!< Transmission FIFO number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - - uint32_t xfer_size; /*!< requested transfer size */ -} USB_EPTypeDef; - -typedef struct -{ - uint8_t dev_addr; /*!< USB device address. - This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ - - uint8_t ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t speed; /*!< USB Host Channel speed. - This parameter can be any value of @ref HCD_Device_Speed: - (HCD_DEVICE_SPEED_xxx) */ - - uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ - uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ - uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ - uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ - - uint8_t hub_port_nbr; /*!< USB HUB port number */ - uint8_t hub_addr; /*!< USB HUB address */ - - uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_LL_EP_Type */ - - uint16_t max_packet; /*!< Endpoint Max packet size. - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t data_pid; /*!< Initial data PID. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - - uint32_t XferSize; /*!< OTG Channel transfer size. */ - - uint32_t xfer_len; /*!< Current transfer length. */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - - uint8_t toggle_in; /*!< IN transfer current toggle flag. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t toggle_out; /*!< OUT transfer current toggle flag - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - - uint32_t ErrCnt; /*!< Host channel error count. */ - uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ - - USB_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_URBStateTypeDef */ - - USB_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_HCStateTypeDef */ -} USB_HCTypeDef; - -typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; -typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; -typedef USB_EPTypeDef USB_OTG_EPTypeDef; -typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; -typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; -typedef USB_HCTypeDef USB_OTG_HCTypeDef; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** @defgroup USB_OTG_CORE VERSION ID - * @{ - */ -#define USB_OTG_CORE_ID_300A 0x4F54300AU -#define USB_OTG_CORE_ID_310A 0x4F54310AU -/** - * @} - */ - -/** @defgroup USB_Core_Mode_ USB Core Mode - * @{ - */ -#define USB_OTG_MODE_DEVICE 0U -#define USB_OTG_MODE_HOST 1U -#define USB_OTG_MODE_DRD 2U -/** - * @} - */ - -/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed - * @{ - */ -#define USB_OTG_SPEED_HIGH 0U -#define USB_OTG_SPEED_HIGH_IN_FULL 1U -#define USB_OTG_SPEED_FULL 3U -/** - * @} - */ - -/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY - * @{ - */ -#define USB_OTG_ULPI_PHY 1U -#define USB_OTG_EMBEDDED_PHY 2U -#define USB_OTG_HS_EMBEDDED_PHY 3U -#if !defined (USB_HS_PHYC_TUNE_VALUE) -#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ -#endif /* USB_HS_PHYC_TUNE_VALUE */ -/** - * @} - */ - -/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value - * @{ - */ -#ifndef USBD_HS_TRDT_VALUE -#define USBD_HS_TRDT_VALUE 9U -#endif /* USBD_HS_TRDT_VALUE */ -#ifndef USBD_FS_TRDT_VALUE -#define USBD_FS_TRDT_VALUE 5U -#define USBD_DEFAULT_TRDT_VALUE 9U -#endif /* USBD_HS_TRDT_VALUE */ -/** - * @} - */ - -/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS - * @{ - */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512U -#define USB_OTG_FS_MAX_PACKET_SIZE 64U -#define USB_OTG_MAX_EP0_SIZE 64U -/** - * @} - */ - -/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency - * @{ - */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) -/** - * @} - */ - -/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval - * @{ - */ -#define DCFG_FRAME_INTERVAL_80 0U -#define DCFG_FRAME_INTERVAL_85 1U -#define DCFG_FRAME_INTERVAL_90 2U -#define DCFG_FRAME_INTERVAL_95 3U -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS - * @{ - */ -#define EP_MPS_64 0U -#define EP_MPS_32 1U -#define EP_MPS_16 2U -#define EP_MPS_8 3U -/** - * @} - */ - -/** @defgroup USB_LL_EP_Type USB Low Layer EP Type - * @{ - */ -#define EP_TYPE_CTRL 0U -#define EP_TYPE_ISOC 1U -#define EP_TYPE_BULK 2U -#define EP_TYPE_INTR 3U -#define EP_TYPE_MSK 3U -/** - * @} - */ - -/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed - * @{ - */ -#define EP_SPEED_LOW 0U -#define EP_SPEED_FULL 1U -#define EP_SPEED_HIGH 2U -/** - * @} - */ - -/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type - * @{ - */ -#define HC_PID_DATA0 0U -#define HC_PID_DATA2 1U -#define HC_PID_DATA1 2U -#define HC_PID_SETUP 3U -/** - * @} - */ - -/** @defgroup USB_LL Device Speed - * @{ - */ -#define USBD_HS_SPEED 0U -#define USBD_HSINFS_SPEED 1U -#define USBH_HS_SPEED 0U -#define USBD_FS_SPEED 2U -#define USBH_FSLS_SPEED 1U -/** - * @} - */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines - * @{ - */ -#define STS_GOUT_NAK 1U -#define STS_DATA_UPDT 2U -#define STS_XFER_COMP 3U -#define STS_SETUP_COMP 4U -#define STS_SETUP_UPDT 6U -/** - * @} - */ - -/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines - * @{ - */ -#define HCFG_30_60_MHZ 0U -#define HCFG_48_MHZ 1U -#define HCFG_6_MHZ 2U -/** - * @} - */ - -/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines - * @{ - */ -#define HFIR_6_MHZ 6000U -#define HFIR_60_MHZ 60000U -#define HFIR_48_MHZ 48000U -/** - * @} - */ - -/** @defgroup USB_LL_PHYC_CLK_INIT_Defines USB Low Layer PHYC Clock Init Defines - * @{ - */ -#define PHYC_12_MHZ 12000000U -#define PHYC_12_5_MHZ 12500000U -#define PHYC_16_MHZ 16000000U -#define PHYC_24_MHZ 24000000U -#define PHYC_25_MHZ 25000000U -#define PHYC_32_MHZ 32000000U -/** - * @} - */ - -/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines - * @{ - */ -#define HPRT0_PRTSPD_HIGH_SPEED 0U -#define HPRT0_PRTSPD_FULL_SPEED 1U -#define HPRT0_PRTSPD_LOW_SPEED 2U -/** - * @} - */ - -#define HCCHAR_CTRL 0U -#define HCCHAR_ISOC 1U -#define HCCHAR_BULK 2U -#define HCCHAR_INTR 3U - -#define GRXSTS_PKTSTS_IN 2U -#define GRXSTS_PKTSTS_IN_XFER_COMP 3U -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U -#define GRXSTS_PKTSTS_CH_HALTED 7U - -#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU - -#define HC_MAX_PKT_CNT 256U -#define ISO_SPLT_MPS 188U - -#define HCSPLT_BEGIN 1U -#define HCSPLT_MIDDLE 2U -#define HCSPLT_END 3U -#define HCSPLT_FULL 4U - -#define TEST_J 1U -#define TEST_K 2U -#define TEST_SE0_NAK 3U -#define TEST_PACKET 4U -#define TEST_FORCE_EN 5U - -#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) -#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) - -#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ - + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) - -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ - + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) - -#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) - -#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ - + USB_OTG_HOST_CHANNEL_BASE\ - + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) - -/* Legacy name for USBPHYC defined in CMSIS device but USBCPHYC used in USB driver - to determine if peripheral is present or not */ -#ifdef USB_HS_PHYC -#define USBPHYC USB_HS_PHYC -#endif /* USB_HS_PHYC */ - -#define EP_ADDR_MSK 0xFU -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) -#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) - -#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) -#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); -HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, - uint8_t ch_ep_num, uint16_t len, uint8_t dma); - -void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); -uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); -uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); -uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); - -HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); -uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); -uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, - uint8_t epnum, uint8_t dev_address, uint8_t speed, - uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, - USB_OTG_HCTypeDef *hc, uint8_t dma); - -uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - -#endif /* STM32F7xx_LL_USB_H */ +/** + ****************************************************************************** + * @file stm32f7xx_ll_usb.h + * @author MCD Application Team + * @brief Header file of USB Low Layer HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32F7xx_LL_USB_H +#define STM32F7xx_LL_USB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal_def.h" + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup USB_LL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef HAL_USB_TIMEOUT +#define HAL_USB_TIMEOUT 0xF000000U +#endif /* define HAL_USB_TIMEOUT */ + +#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS +#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ + +/** + * @brief USB Mode definition + */ + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; + +/** + * @brief URB States definition + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_ACK, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_HCStateTypeDef; + + +/** + * @brief USB Instance Initialization Structure definition + */ +typedef struct +{ + uint8_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t dma_enable; /*!< USB DMA state. + If DMA is not supported this parameter shall be set by default to zero */ + + uint8_t speed; /*!< USB Core speed. + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ + + uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint8_t phy_itface; /*!< Select the used PHY interface. + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ + + uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ + + uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ + + uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ + + uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ + + uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ + + uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + + uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ + +} USB_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_size; /*!< requested transfer size */ +} USB_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ + uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ + + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t XferSize; /*!< OTG Channel transfer size. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ + + USB_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_URBStateTypeDef */ + + USB_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_HCStateTypeDef */ +} USB_HCTypeDef; + +typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; +typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; +typedef USB_EPTypeDef USB_OTG_EPTypeDef; +typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; +typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; +typedef USB_HCTypeDef USB_OTG_HCTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_OTG_CORE VERSION ID + * @{ + */ +#define USB_OTG_CORE_ID_300A 0x4F54300AU +#define USB_OTG_CORE_ID_310A 0x4F54310AU +/** + * @} + */ + +/** @defgroup USB_Core_Mode_ USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +#define USB_OTG_SPEED_FULL 3U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY + * @{ + */ +#define USB_OTG_ULPI_PHY 1U +#define USB_OTG_EMBEDDED_PHY 2U +#define USB_OTG_HS_EMBEDDED_PHY 3U +#if !defined (USB_HS_PHYC_TUNE_VALUE) +#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ +#endif /* USB_HS_PHYC_TUNE_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) +/** + * @} + */ + +/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ + +/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type + * @{ + */ +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U +/** + * @} + */ + +/** @defgroup USB_LL Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_6_MHZ 6000U +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +/** + * @} + */ + +/** @defgroup USB_LL_PHYC_CLK_INIT_Defines USB Low Layer PHYC Clock Init Defines + * @{ + */ +#define PHYC_12_MHZ 12000000U +#define PHYC_12_5_MHZ 12500000U +#define PHYC_16_MHZ 16000000U +#define PHYC_24_MHZ 24000000U +#define PHYC_25_MHZ 25000000U +#define PHYC_32_MHZ 32000000U +/** + * @} + */ + +/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU + +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + +#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) +#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) + +#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) + +#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + +/* Legacy name for USBPHYC defined in CMSIS device but USBCPHYC used in USB driver + to determine if peripheral is present or not */ +#ifdef USB_HS_PHYC +#define USBPHYC USB_HS_PHYC +#endif /* USB_HS_PHYC */ + +#define EP_ADDR_MSK 0xFU +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma); + +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); + +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps); +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, + USB_OTG_HCTypeDef *hc, uint8_t dma); + +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + + +#endif /* STM32F7xx_LL_USB_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h index 87806aef..32e8672d 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h +++ b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_utils.h @@ -1,304 +1,304 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_utils.h - * @author MCD Application Team - * @brief Header file of UTILS LL module. - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL UTILS driver contains a set of generic APIs that can be - used by user: - (+) Device electronic signature - (+) Timing functions - (+) PLL configuration functions - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F7xx_LL_UTILS_H -#define __STM32F7xx_LL_UTILS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -/** @defgroup UTILS_LL UTILS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants - * @{ - */ - -/* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY 0xFFFFFFFFU - -/** - * @brief Unique device ID register base address - */ -#define UID_BASE_ADDRESS UID_BASE - -/** - * @brief Flash size data register base address - */ -#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE - -/** - * @brief Package data register base address - */ -#define PACKAGE_BASE_ADDRESS PACKAGE_BASE - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros - * @{ - */ -/** - * @} - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures - * @{ - */ -/** - * @brief UTILS PLL structure definition - */ -typedef struct -{ - uint32_t PLLM; /*!< Division factor for PLL VCO input clock. - This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ - - uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 50 and Max_Data = 432 - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ - - uint32_t PLLP; /*!< Division for the main system clock. - This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL_ConfigDomain_SYS(). */ -} LL_UTILS_PLLInitTypeDef; - -/** - * @brief UTILS System, AHB and APB buses clock configuration structure definition - */ -typedef struct -{ - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAHBPrescaler(). */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB1_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB1Prescaler(). */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB2_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB2Prescaler(). */ - -} LL_UTILS_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants - * @{ - */ - -/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation - * @{ - */ -#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ -/** - * @} - */ - -/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE - * @{ - */ -#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000100U /*!< LQFP100 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 0x00000200U /*!< LQFP144 or WLCSP143 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 0x00000300U /*!< WLCSP180, LQFP176 or UFBGA176 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 0x00000400U /*!< LQFP176, LQFP208 or TFBGA216 package type */ -#define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208 0x00000500U /*!< LQFP176, LQFP208 or TFBGA216 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208 0x00000600U /*!< LQFP176, LQFP208 or TFBGA216 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216 0x00000700U /*!< LQFP176, LQFP208 or TFBGA216 package type */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions - * @{ - */ - -/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE - * @{ - */ - -/** - * @brief Get Word0 of the unique device identifier (UID based on 96 bits) - * @retval UID[31:0] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word0(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); -} - -/** - * @brief Get Word1 of the unique device identifier (UID based on 96 bits) - * @retval UID[63:32] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word1(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); -} - -/** - * @brief Get Word2 of the unique device identifier (UID based on 96 bits) - * @retval UID[95:64] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word2(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); -} - -/** - * @brief Get Flash memory size - * @note This bitfield indicates the size of the device Flash memory expressed in - * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. - * @retval FLASH_SIZE[15:0]: Flash memory size - */ -__STATIC_INLINE uint32_t LL_GetFlashSize(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); -} - -/** - * @brief Get Package type - * @retval Returned value can be one of the following values: - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*) - * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*) - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*) - * - * (*) value not defined in all devices. - */ -__STATIC_INLINE uint32_t LL_GetPackageType(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); -} - -/** - * @} - */ - -/** @defgroup UTILS_LL_EF_DELAY DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source of the time base. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Frequency of Ticks (Hz) - * @retval None - */ -__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) -{ - /* Configure the SysTick to have interrupt in 1ms time base */ - SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ -} - -void LL_Init1msTick(uint32_t HCLKFrequency); -void LL_mDelay(uint32_t Delay); - -/** - * @} - */ - -/** @defgroup UTILS_EF_SYSTEM SYSTEM - * @{ - */ - -void LL_SetSystemCoreClock(uint32_t HCLKFrequency); -ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32F7xx_LL_UTILS_H */ - +/** + ****************************************************************************** + * @file stm32f7xx_ll_utils.h + * @author MCD Application Team + * @brief Header file of UTILS LL module. + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The LL UTILS driver contains a set of generic APIs that can be + used by user: + (+) Device electronic signature + (+) Timing functions + (+) PLL configuration functions + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_LL_UTILS_H +#define __STM32F7xx_LL_UTILS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx.h" + +/** @addtogroup STM32F7xx_LL_Driver + * @{ + */ + +/** @defgroup UTILS_LL UTILS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants + * @{ + */ + +/* Max delay can be used in LL_mDelay */ +#define LL_MAX_DELAY 0xFFFFFFFFU + +/** + * @brief Unique device ID register base address + */ +#define UID_BASE_ADDRESS UID_BASE + +/** + * @brief Flash size data register base address + */ +#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE + +/** + * @brief Package data register base address + */ +#define PACKAGE_BASE_ADDRESS PACKAGE_BASE + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros + * @{ + */ +/** + * @} + */ +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures + * @{ + */ +/** + * @brief UTILS PLL structure definition + */ +typedef struct +{ + uint32_t PLLM; /*!< Division factor for PLL VCO input clock. + This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. + This parameter must be a number between Min_Data = 50 and Max_Data = 432 + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ + + uint32_t PLLP; /*!< Division for the main system clock. + This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_PLL_ConfigDomain_SYS(). */ +} LL_UTILS_PLLInitTypeDef; + +/** + * @brief UTILS System, AHB and APB buses clock configuration structure definition + */ +typedef struct +{ + uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). + This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAHBPrescaler(). */ + + uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB1_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB1Prescaler(). */ + + uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). + This parameter can be a value of @ref RCC_LL_EC_APB2_DIV + + This feature can be modified afterwards using unitary function + @ref LL_RCC_SetAPB2Prescaler(). */ + +} LL_UTILS_ClkInitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants + * @{ + */ + +/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation + * @{ + */ +#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ +#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ +/** + * @} + */ + +/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE + * @{ + */ +#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000100U /*!< LQFP100 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 0x00000200U /*!< LQFP144 or WLCSP143 package type */ +#define LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 0x00000300U /*!< WLCSP180, LQFP176 or UFBGA176 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 0x00000400U /*!< LQFP176, LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_TFBGA216_LQFP176_LQFP208 0x00000500U /*!< LQFP176, LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP176_TFBGA216_LQFP208 0x00000600U /*!< LQFP176, LQFP208 or TFBGA216 package type */ +#define LL_UTILS_PACKAGETYPE_LQFP208_LQFP176_TFBGA216 0x00000700U /*!< LQFP176, LQFP208 or TFBGA216 package type */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions + * @{ + */ + +/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE + * @{ + */ + +/** + * @brief Get Word0 of the unique device identifier (UID based on 96 bits) + * @retval UID[31:0] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word0(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); +} + +/** + * @brief Get Word1 of the unique device identifier (UID based on 96 bits) + * @retval UID[63:32] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word1(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); +} + +/** + * @brief Get Word2 of the unique device identifier (UID based on 96 bits) + * @retval UID[95:64] + */ +__STATIC_INLINE uint32_t LL_GetUID_Word2(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); +} + +/** + * @brief Get Flash memory size + * @note This bitfield indicates the size of the device Flash memory expressed in + * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. + * @retval FLASH_SIZE[15:0]: Flash memory size + */ +__STATIC_INLINE uint32_t LL_GetFlashSize(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); +} + +/** + * @brief Get Package type + * @retval Returned value can be one of the following values: + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_WLCSP143 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP180_LQFP176_UFBGA176 (*) + * @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_LQFP208_TFBGA216 (*) + * + * (*) value not defined in all devices. + */ +__STATIC_INLINE uint32_t LL_GetPackageType(void) +{ + return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U); +} + +/** + * @} + */ + +/** @defgroup UTILS_LL_EF_DELAY DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source of the time base. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @note When a RTOS is used, it is recommended to avoid changing the SysTick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param Ticks Frequency of Ticks (Hz) + * @retval None + */ +__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) +{ + /* Configure the SysTick to have interrupt in 1ms time base */ + SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ +} + +void LL_Init1msTick(uint32_t HCLKFrequency); +void LL_mDelay(uint32_t Delay); + +/** + * @} + */ + +/** @defgroup UTILS_EF_SYSTEM SYSTEM + * @{ + */ + +void LL_SetSystemCoreClock(uint32_t HCLKFrequency); +ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, + LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, + LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_LL_UTILS_H */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h b/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h deleted file mode 100644 index 186a9ac3..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_wwdg.h +++ /dev/null @@ -1,316 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_wwdg.h - * @author MCD Application Team - * @brief Header file of WWDG LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32F7xx_LL_WWDG_H -#define STM32F7xx_LL_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (WWDG) - -/** @defgroup WWDG_LL WWDG - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants - * @{ - */ - -/** @defgroup WWDG_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions - * @{ - */ -#define LL_WWDG_CFR_EWI WWDG_CFR_EWI -/** - * @} - */ - -/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER - * @{ - */ -#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros - * @{ - */ -/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros - * @{ - */ -/** - * @brief Write a value in WWDG register - * @param __INSTANCE__ WWDG Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in WWDG register - * @param __INSTANCE__ WWDG Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions - * @{ - */ - -/** @defgroup WWDG_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. - * @note It is enabled by setting the WDGA bit in the WWDG_CR register, - * then it cannot be disabled again except by a reset. - * This bit is set by software and only cleared by hardware after a reset. - * When WDGA = 1, the watchdog can generate a reset. - * @rmtoll CR WDGA LL_WWDG_Enable - * @param WWDGx WWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) -{ - SET_BIT(WWDGx->CR, WWDG_CR_WDGA); -} - -/** - * @brief Checks if Window Watchdog is enabled - * @rmtoll CR WDGA LL_WWDG_IsEnabled - * @param WWDGx WWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) -{ - return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); -} - -/** - * @brief Set the Watchdog counter value to provided value (7-bits T[6:0]) - * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset - * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles - * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) - * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) - * @rmtoll CR T LL_WWDG_SetCounter - * @param WWDGx WWDG Instance - * @param Counter 0..0x7F (7 bit counter value) - * @retval None - */ -__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) -{ - MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter); -} - -/** - * @brief Return current Watchdog Counter Value (7 bits counter value) - * @rmtoll CR T LL_WWDG_GetCounter - * @param WWDGx WWDG Instance - * @retval 7 bit Watchdog Counter value - */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->CR, WWDG_CR_T)); -} - -/** - * @brief Set the time base of the prescaler (WDGTB). - * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter - * is decremented every (4096 x 2expWDGTB) PCLK cycles - * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler - * @param WWDGx WWDG Instance - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_WWDG_PRESCALER_1 - * @arg @ref LL_WWDG_PRESCALER_2 - * @arg @ref LL_WWDG_PRESCALER_4 - * @arg @ref LL_WWDG_PRESCALER_8 - * @retval None - */ -__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) -{ - MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler); -} - -/** - * @brief Return current Watchdog Prescaler Value - * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler - * @param WWDGx WWDG Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_WWDG_PRESCALER_1 - * @arg @ref LL_WWDG_PRESCALER_2 - * @arg @ref LL_WWDG_PRESCALER_4 - * @arg @ref LL_WWDG_PRESCALER_8 - */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); -} - -/** - * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]). - * @note This window value defines when write in the WWDG_CR register - * to program Watchdog counter is allowed. - * Watchdog counter value update must occur only when the counter value - * is lower than the Watchdog window register value. - * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value - * (in the control register) is refreshed before the downcounter has reached - * the watchdog window register value. - * Physically is possible to set the Window lower then 0x40 but it is not recommended. - * To generate an immediate reset, it is possible to set the Counter lower than 0x40. - * @rmtoll CFR W LL_WWDG_SetWindow - * @param WWDGx WWDG Instance - * @param Window 0x00..0x7F (7 bit Window value) - * @retval None - */ -__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) -{ - MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window); -} - -/** - * @brief Return current Watchdog Window Value (7 bits value) - * @rmtoll CFR W LL_WWDG_GetWindow - * @param WWDGx WWDG Instance - * @retval 7 bit Watchdog Window value - */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); -} - -/** - * @} - */ - -/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management - * @{ - */ -/** - * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not. - * @note This bit is set by hardware when the counter has reached the value 0x40. - * It must be cleared by software by writing 0. - * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. - * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP - * @param WWDGx WWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) -{ - return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF) - * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP - * @param WWDGx WWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx) -{ - WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); -} - -/** - * @} - */ - -/** @defgroup WWDG_LL_EF_IT_Management IT_Management - * @{ - */ -/** - * @brief Enable the Early Wakeup Interrupt. - * @note When set, an interrupt occurs whenever the counter reaches value 0x40. - * This interrupt is only cleared by hardware after a reset - * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP - * @param WWDGx WWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) -{ - SET_BIT(WWDGx->CFR, WWDG_CFR_EWI); -} - -/** - * @brief Check if Early Wakeup Interrupt is enabled - * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP - * @param WWDGx WWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) -{ - return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* WWDG */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32F7xx_LL_WWDG_H */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c index 3ba2bc69..d6d8a37b 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c @@ -1,620 +1,620 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup HAL_Private_Constants - * @{ - */ -/** - * @brief STM32F7xx HAL Driver version number V1.3.1 - */ -#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32F7xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ -#define __STM32F7xx_HAL_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ -#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ - |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ - |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\ - |(__STM32F7xx_HAL_VERSION_RC)) - -#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Exported variables ---------------------------------------------------------*/ -/** @addtogroup HAL_Exported_Variables - * @{ - */ -__IO uint32_t uwTick; -uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ -HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes the Flash interface the NVIC allocation and initial clock - configuration. It initializes the systick also when timeout is needed - and the backup domain when enabled. - (+) De-Initializes common part of the HAL. - (+) Configure the time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. -@endverbatim - * @{ - */ - -/** - * @brief This function is used to initialize the HAL Library; it must be the first - * instruction to be executed in the main program (before to call any other - * HAL function), it performs the following: - * Configure the Flash prefetch, and instruction cache through ART accelerator. - * Configures the SysTick to generate an interrupt each 1 millisecond, - * which is clocked by the HSI (at this stage, the clock is not yet - * configured and thus the system is running from the internal HSI at 16 MHz). - * Set NVIC Group Priority to 4. - * Calls the HAL_MspInit() callback function defined in user file - * "stm32f7xx_hal_msp.c" to do the global low level hardware initialization - * - * @note SysTick is used as time base for the HAL_Delay() function, the application - * need to ensure that the SysTick time base is always set to 1 millisecond - * to have correct HAL operation. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Instruction cache through ART accelerator */ -#if (ART_ACCELERATOR_ENABLE != 0) - __HAL_FLASH_ART_ENABLE(); -#endif /* ART_ACCELERATOR_ENABLE */ - - /* Configure Flash prefetch */ -#if (PREFETCH_ENABLE != 0U) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - HAL_InitTick(TICK_INT_PRIORITY); - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function de-Initializes common part of the HAL and stops the systick. - * This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB1_FORCE_RESET(); - __HAL_RCC_AHB1_RELEASE_RESET(); - - __HAL_RCC_AHB2_FORCE_RESET(); - __HAL_RCC_AHB2_RELEASE_RESET(); - - __HAL_RCC_AHB3_FORCE_RESET(); - __HAL_RCC_AHB3_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) - { - return HAL_ERROR; - } - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - } - else - { - return HAL_ERROR; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick += uwTickFreq; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function returns a tick priority. - * @retval tick priority - */ -uint32_t HAL_GetTickPrio(void) -{ - return uwTickPrio; -} - -/** - * @brief Set new tick Freq. - * @retval Status - */ -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_TickFreqTypeDef prevTickFreq; - - assert_param(IS_TICKFREQ(Freq)); - - if (uwTickFreq != Freq) - { - /* Back up uwTickFreq frequency */ - prevTickFreq = uwTickFreq; - - /* Update uwTickFreq global variable used by HAL_InitTick() */ - uwTickFreq = Freq; - - /* Apply the new tick Freq */ - status = HAL_InitTick(uwTickPrio); - - if (status != HAL_OK) - { - /* Restore previous tick frequency */ - uwTickFreq = prevTickFreq; - } - } - - return status; -} - -/** - * @brief Return tick frequency. - * @retval Tick frequency. - * Value of @ref HAL_TickFreqTypeDef. - */ -HAL_TickFreqTypeDef HAL_GetTickFreq(void) -{ - return uwTickFreq; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a freq to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait += (uint32_t)(uwTickFreq); - } - - while ((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Returns the HAL revision - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32F7xx_HAL_VERSION; -} - -/** - * @brief Returns the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return((DBGMCU->IDCODE) >> 16U); -} - -/** - * @brief Returns the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); -} - -/** - * @brief Returns first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return(READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Returns second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Returns third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -/** - * @brief Enable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGSleepMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Disable the Debug Module during SLEEP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGSleepMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Enables the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @retval None - */ -void HAL_EnableCompensationCell(void) -{ - SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD; -} - -/** - * @brief Power-down the I/O Compensation Cell. - * @note The I/O compensation cell can be used only when the device supply - * voltage ranges from 2.4 to 3.6 V. - * @retval None - */ -void HAL_DisableCompensationCell(void) -{ - SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD); -} - -/** - * @brief Enables the FMC Memory Mapping Swapping. - * - * @note SDRAM is accessible at 0x60000000 - * and NOR/RAM is accessible at 0xC0000000 - * - * @retval None - */ -void HAL_EnableFMCMemorySwapping(void) -{ - SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; -} - -/** - * @brief Disables the FMC Memory Mapping Swapping - * - * @note SDRAM is accessible at 0xC0000000 (default mapping) - * and NOR/RAM is accessible at 0x60000000 (default mapping) - * - * @retval None - */ -void HAL_DisableFMCMemorySwapping(void) -{ - SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC); -} - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) -/** -* @brief Enable the Internal FLASH Bank Swapping. -* -* @note This function can be used only for STM32F77xx/STM32F76xx devices. -* -* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) -* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) -* -* @retval None -*/ -void HAL_EnableMemorySwappingBank(void) -{ - SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); -} - -/** -* @brief Disable the Internal FLASH Bank Swapping. -* -* @note This function can be used only for STM32F77xx/STM32F76xx devices. -* -* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) -* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) -* -* @retval None -*/ -void HAL_DisableMemorySwappingBank(void) -{ - CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); -} -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - +/** + ****************************************************************************** + * @file stm32f7xx_hal.c + * @author MCD Application Team + * @brief HAL module driver. + * This is the common part of the HAL initialization + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The common HAL driver contains a set of generic and common APIs that can be + used by the PPP peripheral drivers and the user to start using the HAL. + [..] + The HAL contains two APIs' categories: + (+) Common HAL APIs + (+) Services HAL APIs + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup HAL HAL + * @brief HAL module driver. + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup HAL_Private_Constants + * @{ + */ +/** + * @brief STM32F7xx HAL Driver version number V1.3.3 + */ +#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32F7xx_HAL_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32F7xx_HAL_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ + |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ + |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\ + |(__STM32F7xx_HAL_VERSION_RC)) + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Exported variables ---------------------------------------------------------*/ +/** @addtogroup HAL_Exported_Variables + * @{ + */ +__IO uint32_t uwTick; +uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ +HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ + +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initializes the Flash interface the NVIC allocation and initial clock + configuration. It initializes the systick also when timeout is needed + and the backup domain when enabled. + (+) De-Initializes common part of the HAL. + (+) Configure the time base source to have 1ms time base with a dedicated + Tick interrupt priority. + (++) SysTick timer is used by default as source of time base, but user + can eventually implement his proper time base source (a general purpose + timer for example or other time source), keeping in mind that Time base + duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and + handled in milliseconds basis. + (++) Time base configuration function (HAL_InitTick ()) is called automatically + at the beginning of the program after reset by HAL_Init() or at any time + when clock is configured, by HAL_RCC_ClockConfig(). + (++) Source of time base is configured to generate interrupts at regular + time intervals. Care must be taken if HAL_Delay() is called from a + peripheral ISR process, the Tick interrupt line must have higher priority + (numerically lower) than the peripheral interrupt. Otherwise the caller + ISR process will be blocked. + (++) functions affecting time base configurations are declared as __weak + to make override possible in case of other implementations in user file. +@endverbatim + * @{ + */ + +/** + * @brief This function is used to initialize the HAL Library; it must be the first + * instruction to be executed in the main program (before to call any other + * HAL function), it performs the following: + * Configure the Flash prefetch, and instruction cache through ART accelerator. + * Configures the SysTick to generate an interrupt each 1 millisecond, + * which is clocked by the HSI (at this stage, the clock is not yet + * configured and thus the system is running from the internal HSI at 16 MHz). + * Set NVIC Group Priority to 4. + * Calls the HAL_MspInit() callback function defined in user file + * "stm32f7xx_hal_msp.c" to do the global low level hardware initialization + * + * @note SysTick is used as time base for the HAL_Delay() function, the application + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + /* Configure Instruction cache through ART accelerator */ +#if (ART_ACCELERATOR_ENABLE != 0) + __HAL_FLASH_ART_ENABLE(); +#endif /* ART_ACCELERATOR_ENABLE */ + + /* Configure Flash prefetch */ +#if (PREFETCH_ENABLE != 0U) + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); +#endif /* PREFETCH_ENABLE */ + + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + + /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ + HAL_InitTick(TICK_INT_PRIORITY); + + /* Init the low level hardware */ + HAL_MspInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief This function de-Initializes common part of the HAL and stops the systick. + * This function is optional. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DeInit(void) +{ + /* Reset of all peripherals */ + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); + + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); + + __HAL_RCC_AHB1_FORCE_RESET(); + __HAL_RCC_AHB1_RELEASE_RESET(); + + __HAL_RCC_AHB2_FORCE_RESET(); + __HAL_RCC_AHB2_RELEASE_RESET(); + + __HAL_RCC_AHB3_FORCE_RESET(); + __HAL_RCC_AHB3_RELEASE_RESET(); + + /* De-Init the low level hardware */ + HAL_MspDeInit(); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initialize the MSP. + * @retval None + */ +__weak void HAL_MspInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the MSP. + * @retval None + */ +__weak void HAL_MspDeInit(void) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief This function configures the source of the time base. + * The time source is configured to have 1ms time base with a dedicated + * Tick interrupt priority. + * @note This function is called automatically at the beginning of program after + * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). + * @note In the default implementation, SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals. + * Care must be taken if HAL_Delay() is called from a peripheral ISR process, + * The SysTick interrupt must have higher priority (numerically lower) + * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. + * The function is declared as __weak to be overwritten in case of other + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + /* Configure the SysTick to have interrupt in 1ms time basis*/ + if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U) + { + return HAL_ERROR; + } + + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + uwTickPrio = TickPriority; + } + else + { + return HAL_ERROR; + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions + * @brief HAL Control functions + * +@verbatim + =============================================================================== + ##### HAL Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Provide a tick value in millisecond + (+) Provide a blocking delay in millisecond + (+) Suspend the time base source interrupt + (+) Resume the time base source interrupt + (+) Get the HAL API driver version + (+) Get the device identifier + (+) Get the device revision identifier + (+) Enable/Disable Debug module during SLEEP mode + (+) Enable/Disable Debug module during STOP mode + (+) Enable/Disable Debug module during STANDBY mode + +@endverbatim + * @{ + */ + +/** + * @brief This function is called to increment a global variable "uwTick" + * used as application time base. + * @note In the default implementation, this variable is incremented each 1ms + * in SysTick ISR. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + uwTick += uwTickFreq; +} + +/** + * @brief Provides a tick value in millisecond. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval tick value + */ +__weak uint32_t HAL_GetTick(void) +{ + return uwTick; +} + +/** + * @brief This function returns a tick priority. + * @retval tick priority + */ +uint32_t HAL_GetTickPrio(void) +{ + return uwTickPrio; +} + +/** + * @brief Set new tick Freq. + * @retval Status + */ +HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_TickFreqTypeDef prevTickFreq; + + assert_param(IS_TICKFREQ(Freq)); + + if (uwTickFreq != Freq) + { + /* Back up uwTickFreq frequency */ + prevTickFreq = uwTickFreq; + + /* Update uwTickFreq global variable used by HAL_InitTick() */ + uwTickFreq = Freq; + + /* Apply the new tick Freq */ + status = HAL_InitTick(uwTickPrio); + + if (status != HAL_OK) + { + /* Restore previous tick frequency */ + uwTickFreq = prevTickFreq; + } + } + + return status; +} + +/** + * @brief Return tick frequency. + * @retval Tick frequency. + * Value of @ref HAL_TickFreqTypeDef. + */ +HAL_TickFreqTypeDef HAL_GetTickFreq(void) +{ + return uwTickFreq; +} + +/** + * @brief This function provides minimum delay (in milliseconds) based + * on variable incremented. + * @note In the default implementation , SysTick timer is the source of time base. + * It is used to generate interrupts at regular time intervals where uwTick + * is incremented. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +__weak void HAL_Delay(uint32_t Delay) +{ + uint32_t tickstart = HAL_GetTick(); + uint32_t wait = Delay; + + /* Add a freq to guarantee minimum wait */ + if (wait < HAL_MAX_DELAY) + { + wait += (uint32_t)(uwTickFreq); + } + + while ((HAL_GetTick() - tickstart) < wait) + { + } +} + +/** + * @brief Suspend Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() + * is called, the SysTick interrupt will be disabled and so Tick increment + * is suspended. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume Tick increment. + * @note In the default implementation , SysTick timer is the source of time base. It is + * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() + * is called, the SysTick interrupt will be enabled and so Tick increment + * is resumed. + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Returns the HAL revision + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t HAL_GetHalVersion(void) +{ + return __STM32F7xx_HAL_VERSION; +} + +/** + * @brief Returns the device revision identifier. + * @retval Device revision identifier + */ +uint32_t HAL_GetREVID(void) +{ + return((DBGMCU->IDCODE) >> 16U); +} + +/** + * @brief Returns the device identifier. + * @retval Device identifier + */ +uint32_t HAL_GetDEVID(void) +{ + return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK); +} + +/** + * @brief Returns first word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw0(void) +{ + return(READ_REG(*((uint32_t *)UID_BASE))); +} + +/** + * @brief Returns second word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw1(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 4U)))); +} + +/** + * @brief Returns third word of the unique device identifier (UID based on 96 bits) + * @retval Device identifier + */ +uint32_t HAL_GetUIDw2(void) +{ + return(READ_REG(*((uint32_t *)(UID_BASE + 8U)))); +} + +/** + * @brief Enable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Disable the Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGSleepMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); +} + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Enable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Disable the Debug Module during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DisableDBGStandbyMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); +} + +/** + * @brief Enables the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_EnableCompensationCell(void) +{ + SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD; +} + +/** + * @brief Power-down the I/O Compensation Cell. + * @note The I/O compensation cell can be used only when the device supply + * voltage ranges from 2.4 to 3.6 V. + * @retval None + */ +void HAL_DisableCompensationCell(void) +{ + SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD); +} + +/** + * @brief Enables the FMC Memory Mapping Swapping. + * + * @note SDRAM is accessible at 0x60000000 + * and NOR/RAM is accessible at 0xC0000000 + * + * @retval None + */ +void HAL_EnableFMCMemorySwapping(void) +{ + SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0; +} + +/** + * @brief Disables the FMC Memory Mapping Swapping + * + * @note SDRAM is accessible at 0xC0000000 (default mapping) + * and NOR/RAM is accessible at 0x60000000 (default mapping) + * + * @retval None + */ +void HAL_DisableFMCMemorySwapping(void) +{ + SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC); +} + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) +/** +* @brief Enable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_EnableMemorySwappingBank(void) +{ + SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} + +/** +* @brief Disable the Internal FLASH Bank Swapping. +* +* @note This function can be used only for STM32F77xx/STM32F76xx devices. +* +* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM)) +* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM)) +* +* @retval None +*/ +void HAL_DisableMemorySwappingBank(void) +{ + CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB); +} +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c index 15fd1c78..bbfd67b8 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c @@ -1,2114 +1,2115 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_adc.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Converter (ADC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### ADC Peripheral features ##### - ============================================================================== - [..] - (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. - (#) Interrupt generation at the end of conversion, end of injected conversion, - and in case of analog watchdog or overrun events - (#) Single and continuous conversion modes. - (#) Scan mode for automatic conversion of channel 0 to channel x. - (#) Data alignment with in-built data coherency. - (#) Channel-wise programmable sampling time. - (#) External trigger option with configurable polarity for both regular and - injected conversion. - (#) Dual/Triple mode (on devices with 2 ADCs or more). - (#) Configurable DMA data storage in Dual/Triple ADC mode. - (#) Configurable delay between conversions in Dual/Triple interleaved mode. - (#) ADC conversion type (refer to the datasheets). - (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at - slower speed. - (#) ADC input range: VREF(minus) = VIN = VREF(plus). - (#) DMA request generation during regular channel conversion. - - - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): - (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() - (##) ADC pins configuration - (+++) Enable the clock for the ADC GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE() - (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() - (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) - (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) - (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() - (+++) Configure and enable two DMA streams stream for managing data - transfer from peripheral to memory (output stream) - (+++) Associate the initialized DMA handle to the CRYP DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream. - - *** Configuration of ADC, groups regular/injected, channels parameters *** - ============================================================================== - [..] - (#) Configure the ADC parameters (resolution, data alignment, ...) - and regular group parameters (conversion trigger, sequencer, ...) - using function HAL_ADC_Init(). - - (#) Configure the channels for regular group parameters (channel number, - channel rank into sequencer, ..., into regular group) - using function HAL_ADC_ConfigChannel(). - - (#) Optionally, configure the injected group parameters (conversion trigger, - sequencer, ..., of injected group) - and the channels for injected group parameters (channel number, - channel rank into sequencer, ..., into injected group) - using function HAL_ADCEx_InjectedConfigChannel(). - - (#) Optionally, configure the analog watchdog parameters (channels - monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). - - (#) Optionally, for devices with several ADC instances: configure the - multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). - - *** Execution of ADC conversions *** - ============================================================================== - [..] - (#) ADC driver can be used among three modes: polling, interruption, - transfer by DMA. - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the ADC peripheral using HAL_ADC_Start() - (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage - user can specify the value of timeout according to his end application - (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. - (+) Stop the ADC peripheral using HAL_ADC_Stop() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the ADC peripheral using HAL_ADC_Start_IT() - (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine - (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ConvCpltCallback - (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ErrorCallback - (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ConvCpltCallback - (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ErrorCallback - (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() - - *** ADC HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in ADC HAL driver. - - (+) __HAL_ADC_ENABLE : Enable the ADC peripheral - (+) __HAL_ADC_DISABLE : Disable the ADC peripheral - (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt - (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt - (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled - (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags - (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status - (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register - - *** Callback functions *** - ============================== - [..] - (@) Callback functions must be implemented in user program: - (+@) HAL_ADC_ErrorCallback() - (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) - (+@) HAL_ADC_ConvCpltCallback() - (+@) HAL_ADC_ConvHalfCpltCallback - - (@) You can refer to the ADC HAL driver header file for more useful macros - - *** Deinitialization of ADC *** - ============================================================================== - [..] - (#) Disable the ADC interface - (++) ADC clock can be hard reset and disabled at RCC top level. - (++) Hard reset of ADC peripherals - using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). - (++) ADC clock disable using the equivalent macro/functions as configuration step. - (+++) Example: - Into HAL_ADC_MspDeInit() (recommended code location) or with - other device clock parameters configuration: - (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); - (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; - (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) - (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); - - (#) ADC pins configuration - (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) - - (#) Optionally, in case of usage of DMA: - (++) Deinitialize the DMA using function HAL_DMA_DeInit(). - (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) - - *** Callback registration *** - ============================================================================== - [..] - - The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_ADC_RegisterCallback() - to register an interrupt callback. - [..] - - Function HAL_ADC_RegisterCallback() allows to register following callbacks: - (+) ConvCpltCallback : ADC conversion complete callback - (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback - (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback - (+) ErrorCallback : ADC error callback - (+) InjectedConvCpltCallback : ADC group injected conversion complete callback - (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback - (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback - (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback - (+) EndOfSamplingCallback : ADC end of sampling callback - (+) MspInitCallback : ADC Msp Init callback - (+) MspDeInitCallback : ADC Msp DeInit callback - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - [..] - - Use function HAL_ADC_UnRegisterCallback to reset a callback to the default - weak function. - [..] - - HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) ConvCpltCallback : ADC conversion complete callback - (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback - (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback - (+) ErrorCallback : ADC error callback - (+) InjectedConvCpltCallback : ADC group injected conversion complete callback - (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback - (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback - (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback - (+) EndOfSamplingCallback : ADC end of sampling callback - (+) MspInitCallback : ADC Msp Init callback - (+) MspDeInitCallback : ADC Msp DeInit callback - [..] - - By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when - these callbacks are null (not registered beforehand). - [..] - - If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - [..] - - Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - [..] - - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() - or HAL_ADC_Init() function. - [..] - - When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup ADC ADC - * @brief ADC driver modules - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup ADC_Private_Functions - * @{ - */ -/* Private function prototypes -----------------------------------------------*/ -static void ADC_Init(ADC_HandleTypeDef* hadc); -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_DMAError(DMA_HandleTypeDef *hdma); -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADC_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. - (+) De-initialize the ADC. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct and initializes the ADC MSP. - * - * @note This function is used to configure the global features of the ADC ( - * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, - * the rest of the configuration parameters are specific to the regular - * channels group (scan mode activation, continuous mode activation, - * External trigger source and edge, DMA continuous request after the - * last transfer and End of conversion selection). - * - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); - assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); - assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - } - - if(hadc->State == HAL_ADC_STATE_RESET) - { -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - /* Init the ADC Callback settings */ - hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ - hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ - hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ - hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ - hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ - if (hadc->MspInitCallback == NULL) - { - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hadc->MspInitCallback(hadc); -#else - /* Init the low level hardware */ - HAL_ADC_MspInit(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Initialize ADC error code */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Allocate lock resource and initialize it */ - hadc->Lock = HAL_UNLOCKED; - } - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Set ADC parameters */ - ADC_Init(hadc); - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set the ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - else - { - tmp_hal_status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check ADC handle */ - if(hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed. */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: RCC clock, NVIC */ - hadc->MspDeInitCallback(hadc); -#else - /* DeInit the low level hardware: RCC clock, NVIC */ - HAL_ADC_MspDeInit(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set ADC state */ - hadc->State = HAL_ADC_STATE_RESET; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Initializes the ADC MSP. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the ADC MSP. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User ADC Callback - * To be used instead of the weak predefined callback - * @param hadc Pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID - * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID - * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID - * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) - { - switch (CallbackID) - { - case HAL_ADC_CONVERSION_COMPLETE_CB_ID : - hadc->ConvCpltCallback = pCallback; - break; - - case HAL_ADC_CONVERSION_HALF_CB_ID : - hadc->ConvHalfCpltCallback = pCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : - hadc->LevelOutOfWindowCallback = pCallback; - break; - - case HAL_ADC_ERROR_CB_ID : - hadc->ErrorCallback = pCallback; - break; - - case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : - hadc->InjectedConvCpltCallback = pCallback; - break; - - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = pCallback; - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_ADC_STATE_RESET == hadc->State) - { - switch (CallbackID) - { - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = pCallback; - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a ADC Callback - * ADC callback is redirected to the weak predefined callback - * @param hadc Pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID - * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID - * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID - * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) - { - switch (CallbackID) - { - case HAL_ADC_CONVERSION_COMPLETE_CB_ID : - hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; - break; - - case HAL_ADC_CONVERSION_HALF_CB_ID : - hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : - hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; - break; - - case HAL_ADC_ERROR_CB_ID : - hadc->ErrorCallback = HAL_ADC_ErrorCallback; - break; - - case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : - hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; - break; - - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_ADC_STATE_RESET == hadc->State) - { - switch (CallbackID) - { - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular channel. - (+) Stop conversion of regular channel. - (+) Start conversion of regular channel and enable interrupt. - (+) Stop conversion of regular channel and disable interrupt. - (+) Start conversion of regular channel and enable DMA transfer. - (+) Stop conversion of regular channel and disable DMA transfer. - (+) Handle ADC interrupt request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables ADC and starts conversion of the regular channels. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular group operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - else - { - /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - - /* if dual mode is selected, ADC3 works independently. */ - /* check if the mode selected is not triple */ - if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) - { - /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables ADC and stop conversion of regular channels. - * - * @note Caution: This function will stop also injected channels. - * - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Poll for regular conversion complete - * @note ADC conversion flags EOS (end of sequence) and EOC (end of - * conversion) are cleared by this function. - * @note This function cannot be used in a particular setup: ADC configured - * in DMA mode and polling for end of each conversion (ADC init - * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). - * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still - * be performed on the complete sequence. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param Timeout Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Verification that ADC configuration is compliant with polling for */ - /* each conversion: */ - /* Particular case is ADC configured in DMA mode and ADC sequencer with */ - /* several ranks and polling for end of each conversion. */ - /* For code simplicity sake, this particular case is generalized to */ - /* ADC configured in DMA mode and polling for end of each conversion. */ - if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && - HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) - { - /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - } - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Poll for conversion event - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param EventType the ADC event type. - * This parameter can be one of the following values: - * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. - * @arg ADC_OVR_EVENT: ADC Overrun event. - * @param Timeout Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EVENT_TYPE(EventType)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check selected event flag */ - while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) - { - /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc,EventType))) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - } - - /* Analog watchdog (level out of window) event */ - if(EventType == ADC_AWD_EVENT) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - } - /* Overrun event */ - else - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - - /* Clear ADC overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - - /* Return ADC state */ - return HAL_OK; -} - - -/** - * @brief Enables the interrupt and starts ADC conversion of regular channels. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular group operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); - - /* Enable end of conversion interrupt for regular group */ - __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - else - { - /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - - /* if dual mode is selected, ADC3 works independently. */ - /* check if the mode selected is not triple */ - if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) - { - /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables the interrupt and stop ADC conversion of regular channels. - * - * @note Caution: This function will stop also injected channels. - * - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Disable ADC end of conversion interrupt for regular group */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles ADC interrupt request - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) -{ - uint32_t tmp1 = 0, tmp2 = 0; - - uint32_t tmp_sr = hadc->Instance->SR; - uint32_t tmp_cr1 = hadc->Instance->CR1; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); - assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); - - tmp1 = tmp_sr & ADC_FLAG_EOC; - tmp2 = tmp_cr1 & ADC_IT_EOC; - - /* Check End of conversion flag for regular channels */ - if(tmp1 && tmp2) - { - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - } - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvCpltCallback(hadc); -#else - HAL_ADC_ConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - } - - tmp1 = tmp_sr & ADC_FLAG_JEOC; - tmp2 = tmp_cr1 & ADC_IT_JEOC; - /* Check End of conversion flag for injected channels */ - if(tmp1 && tmp2) - { - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - } - - /* Determine whether any further conversion upcoming on group injected */ - /* by external trigger, scan sequence on going or by automatic injected */ - /* conversion from group regular (same conditions as group regular */ - /* interruption disabling above). */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE)))) - { - /* Disable ADC end of single conversion interrupt on group injected */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->InjectedConvCpltCallback(hadc); -#else - HAL_ADCEx_InjectedConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear injected group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); - } - - tmp1 = tmp_sr & ADC_FLAG_AWD; - tmp2 = tmp_cr1 & ADC_IT_AWD; - /* Check Analog watchdog flag */ - if(tmp1 && tmp2) - { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Level out of window callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->LevelOutOfWindowCallback(hadc); -#else - HAL_ADC_LevelOutOfWindowCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - - /* Clear the ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); - } - } - - tmp1 = tmp_sr & ADC_FLAG_OVR; - tmp2 = tmp_cr1 & ADC_IT_OVR; - /* Check Overrun flag */ - if(tmp1 && tmp2) - { - /* Note: On STM32F7, ADC overrun can be set through other parameters */ - /* refer to description of parameter "EOCSelection" for more */ - /* details. */ - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - - /* Clear ADC overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - - /* Error callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear the Overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } -} - -/** - * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from ADC peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular group operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Enable ADC DMA mode */ - hadc->Instance->CR2 |= ADC_CR2_DMA; - - /* Start the DMA channel */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - else - { - /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - /* if dual mode is selected, ADC3 works independently. */ - /* check if the mode selected is not triple */ - if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) - { - /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Disable the selected ADC DMA mode */ - hadc->Instance->CR2 &= ~ADC_CR2_DMA; - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* DMA transfer is on going) */ - if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) - { - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status != HAL_OK) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } - } - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Gets the converted value from data register of regular channel. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval Converted value - */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) -{ - /* Return the selected ADC converted value */ - return hadc->Instance->DR; -} - -/** - * @brief Regular conversion complete callback in non blocking mode - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_ConvCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Regular conversion half DMA transfer callback in non blocking mode - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Analog watchdog callback in non blocking mode - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file - */ -} - -/** - * @brief Error ADC callback. - * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): - * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". - * - If needed, restart a new ADC conversion using function - * "HAL_ADC_Start_DMA()" - * (this function is also clearing overrun flag) - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure regular channels. - (+) Configure injected channels. - (+) Configure multimode. - (+) Configure the analog watch dog. - -@endverbatim - * @{ - */ - - /** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param sConfig ADC configuration structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE)) - { - /* Clear the old sample time */ - hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); - - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); - } - else - { - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); - } - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Clear the old sample time */ - hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); - - /* Set the new sample time */ - hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); - } - - /* For Rank 1 to 6 */ - if (sConfig->Rank < 7) - { - /* Clear the old SQx bits for the selected rank */ - hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); - - /* Set the SQx bits for the selected rank */ - hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); - } - /* For Rank 7 to 12 */ - else if (sConfig->Rank < 13) - { - /* Clear the old SQx bits for the selected rank */ - hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); - - /* Set the SQx bits for the selected rank */ - hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); - } - /* For Rank 13 to 16 */ - else - { - /* Clear the old SQx bits for the selected rank */ - hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); - - /* Set the SQx bits for the selected rank */ - hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); - } - - /* if no internal channel selected */ - if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE)) - { - /* Disable the VBAT & TSVREFE channel*/ - ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE); - } - - /* if ADC1 Channel_18 is selected enable VBAT Channel */ - if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) - { - /* Disable the TEMPSENSOR channel as it is multiplixed with the VBAT channel */ - ADC->CCR &= ~ADC_CCR_TSVREFE; - - /* Enable the VBAT channel*/ - ADC->CCR |= ADC_CCR_VBATE; - } - - /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ - if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) - { - /* Disable the VBAT channel as it is multiplixed with TEMPSENSOR channel */ - ADC->CCR &= ~ADC_CCR_VBATE; - - /* Enable the TSVREFE channel*/ - ADC->CCR |= ADC_CCR_TSVREFE; - - if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the analog watchdog. - * @note Analog watchdog thresholds can be modified while ADC conversion - * is on going. - * In this case, some constraints must be taken into account: - * the programmed threshold values are effective from the next - * ADC EOC (end of unitary conversion). - * Considering that registers write delay may happen due to - * bus activity, this might cause an uncertainty on the - * effective timing of the new programmed threshold values. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure - * that contains the configuration information of ADC analog watchdog. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) -{ -#ifdef USE_FULL_ASSERT - uint32_t tmp = 0; -#endif /* USE_FULL_ASSERT */ - - /* Check the parameters */ - assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - -#ifdef USE_FULL_ASSERT - tmp = ADC_GET_RESOLUTION(hadc); - assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); -#endif /* USE_FULL_ASSERT */ - - /* Process locked */ - __HAL_LOCK(hadc); - - if(AnalogWDGConfig->ITMode == ENABLE) - { - /* Enable the ADC Analog watchdog interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); - } - else - { - /* Disable the ADC Analog watchdog interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); - } - - /* Clear AWDEN, JAWDEN and AWDSGL bits */ - hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); - - /* Set the analog watchdog enable mode */ - hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; - - /* Set the high threshold */ - hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; - - /* Set the low threshold */ - hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; - - /* Clear the Analog watchdog channel select bits */ - hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; - - /* Set the Analog watchdog channel */ - hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions - * @brief ADC Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the ADC state - (+) Check the ADC Error - -@endverbatim - * @{ - */ - -/** - * @brief return the ADC state - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL state - */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) -{ - /* Return ADC state */ - return hadc->State; -} - -/** - * @brief Return the ADC error code - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval ADC Error Code - */ -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) -{ - return hadc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct without initializing the ADC MSP. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -static void ADC_Init(ADC_HandleTypeDef* hadc) -{ - /* Set ADC parameters */ - /* Set the ADC clock prescaler */ - ADC->CCR &= ~(ADC_CCR_ADCPRE); - ADC->CCR |= hadc->Init.ClockPrescaler; - - /* Set ADC scan mode */ - hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); - hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); - - /* Set ADC resolution */ - hadc->Instance->CR1 &= ~(ADC_CR1_RES); - hadc->Instance->CR1 |= hadc->Init.Resolution; - - /* Set ADC data alignment */ - hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); - hadc->Instance->CR2 |= hadc->Init.DataAlign; - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - /* Select external trigger to start conversion */ - hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); - hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; - - /* Select external trigger polarity */ - hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); - hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; - } - else - { - /* Reset the external trigger */ - hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); - hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); - } - - /* Enable or disable ADC continuous conversion mode */ - hadc->Instance->CR2 &= ~(ADC_CR2_CONT); - hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); - - if(hadc->Init.DiscontinuousConvMode != DISABLE) - { - assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); - - /* Enable the selected ADC regular discontinuous mode */ - hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; - - /* Set the number of channels to be converted in discontinuous mode */ - hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); - hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); - } - else - { - /* Disable the selected ADC regular discontinuous mode */ - hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); - } - - /* Set ADC number of conversion */ - hadc->Instance->SQR1 &= ~(ADC_SQR1_L); - hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); - - /* Enable or disable ADC DMA continuous request */ - hadc->Instance->CR2 &= ~(ADC_CR2_DDS); - hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); - - /* Enable or disable ADC end of conversion selection */ - hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); - hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); -} - -/** - * @brief DMA transfer complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) - { - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvCpltCallback(hadc); -#else - HAL_ADC_ConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - else /* DMA and-or internal error occurred */ - { - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) - { - /* Call HAL ADC Error Callback function */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - else - { - /* Call DMA error callback */ - hadc->DMA_Handle->XferErrorCallback(hdma); - } - } -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Half conversion callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvHalfCpltCallback(hadc); -#else - HAL_ADC_ConvHalfCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA error callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - /* Error callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ADC Peripheral features ##### + ============================================================================== + [..] + (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + (#) Interrupt generation at the end of conversion, end of injected conversion, + and in case of analog watchdog or overrun events + (#) Single and continuous conversion modes. + (#) Scan mode for automatic conversion of channel 0 to channel x. + (#) Data alignment with in-built data coherency. + (#) Channel-wise programmable sampling time. + (#) External trigger option with configurable polarity for both regular and + injected conversion. + (#) Dual/Triple mode (on devices with 2 ADCs or more). + (#) Configurable DMA data storage in Dual/Triple ADC mode. + (#) Configurable delay between conversions in Dual/Triple interleaved mode. + (#) ADC conversion type (refer to the datasheets). + (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + slower speed. + (#) ADC input range: VREF(minus) = VIN = VREF(plus). + (#) DMA request generation during regular channel conversion. + + + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): + (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() + (##) ADC pins configuration + (+++) Enable the clock for the ADC GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE() + (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) + (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams stream for managing data + transfer from peripheral to memory (output stream) + (+++) Associate the initialized DMA handle to the CRYP DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA Streams. The output stream should have higher + priority than the input stream. + + *** Configuration of ADC, groups regular/injected, channels parameters *** + ============================================================================== + [..] + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the injected group parameters (conversion trigger, + sequencer, ..., of injected group) + and the channels for injected group parameters (channel number, + channel rank into sequencer, ..., into injected group) + using function HAL_ADCEx_InjectedConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). + + (#) Optionally, for devices with several ADC instances: configure the + multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). + + *** Execution of ADC conversions *** + ============================================================================== + [..] + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the ADC peripheral using HAL_ADC_Start() + (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage + user can specify the value of timeout according to his end application + (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. + (+) Stop the ADC peripheral using HAL_ADC_Stop() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the ADC peripheral using HAL_ADC_Start_IT() + (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine + (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ErrorCallback + (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ErrorCallback + (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() + + *** ADC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in ADC HAL driver. + + (+) __HAL_ADC_ENABLE : Enable the ADC peripheral + (+) __HAL_ADC_DISABLE : Disable the ADC peripheral + (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt + (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt + (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled + (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags + (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status + (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register + + *** Callback functions *** + ============================== + [..] + (@) Callback functions must be implemented in user program: + (+@) HAL_ADC_ErrorCallback() + (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) + (+@) HAL_ADC_ConvCpltCallback() + (+@) HAL_ADC_ConvHalfCpltCallback + + (@) You can refer to the ADC HAL driver header file for more useful macros + + *** Deinitialization of ADC *** + ============================================================================== + [..] + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). + (++) ADC clock disable using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; + (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA using function HAL_DMA_DeInit(). + (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) + + *** Callback registration *** + ============================================================================== + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup ADC_Private_Functions + * @{ + */ +/* Private function prototypes -----------------------------------------------*/ +static void ADC_Init(ADC_HandleTypeDef* hadc); +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct and initializes the ADC MSP. + * + * @note This function is used to configure the global features of the ADC ( + * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, + * the rest of the configuration parameters are specific to the regular + * channels group (scan mode activation, continuous mode activation, + * External trigger source and edge, DMA continuous request after the + * last transfer and End of conversion selection). + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + } + + if(hadc->State == HAL_ADC_STATE_RESET) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Set ADC parameters */ + ADC_Init(hadc); + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + tmp_hal_status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware: RCC clock, NVIC */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Initializes the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular channel. + (+) Stop conversion of regular channel. + (+) Start conversion of regular channel and enable interrupt. + (+) Stop conversion of regular channel and disable interrupt. + (+) Start conversion of regular channel and enable DMA transfer. + (+) Stop conversion of regular channel and disable DMA transfer. + (+) Handle ADC interrupt request. + +@endverbatim + * @{ + */ + +/** + * @brief Enables ADC and starts conversion of the regular channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + + /* if dual mode is selected, ADC3 works independently. */ + /* check if the mode selected is not triple */ + if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) + { + /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables ADC and stop conversion of regular channels. + * + * @note Caution: This function will stop also injected channels. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Poll for regular conversion complete + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function. + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and polling for end of each conversion. */ + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && + HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of conversion flag */ + while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Poll for conversion event + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param EventType the ADC event type. + * This parameter can be one of the following values: + * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. + * @arg ADC_OVR_EVENT: ADC Overrun event. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + /* Analog watchdog (level out of window) event */ + if(EventType == ADC_AWD_EVENT) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + } + /* Overrun event */ + else + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + + /* Return ADC state */ + return HAL_OK; +} + + +/** + * @brief Enables the interrupt and starts ADC conversion of regular channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Enable end of conversion interrupt for regular group */ + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + + /* if dual mode is selected, ADC3 works independently. */ + /* check if the mode selected is not triple */ + if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) + { + /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables the interrupt and stop ADC conversion of regular channels. + * + * @note Caution: This function will stop also injected channels. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable ADC end of conversion interrupt for regular group */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles ADC interrupt request + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + uint32_t tmp_sr = hadc->Instance->SR; + uint32_t tmp_cr1 = hadc->Instance->CR1; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + + tmp1 = tmp_sr & ADC_FLAG_EOC; + tmp2 = tmp_cr1 & ADC_IT_EOC; + + /* Check End of conversion flag for regular channels */ + if(tmp1 && tmp2) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + } + + tmp1 = tmp_sr & ADC_FLAG_JEOC; + tmp2 = tmp_cr1 & ADC_IT_JEOC; + /* Check End of conversion flag for injected channels */ + if(tmp1 && tmp2) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + } + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, scan sequence on going or by automatic injected */ + /* conversion from group regular (same conditions as group regular */ + /* interruption disabling above). */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) + { + /* Disable ADC end of single conversion interrupt on group injected */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedConvCpltCallback(hadc); +#else + HAL_ADCEx_InjectedConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); + } + + tmp1 = tmp_sr & ADC_FLAG_AWD; + tmp2 = tmp_cr1 & ADC_IT_AWD; + /* Check Analog watchdog flag */ + if(tmp1 && tmp2) + { + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Level out of window callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + } + } + + tmp1 = tmp_sr & ADC_FLAG_OVR; + tmp2 = tmp_cr1 & ADC_IT_OVR; + /* Check Overrun flag */ + if(tmp1 && tmp2) + { + /* Note: On STM32F7, ADC overrun can be set through other parameters */ + /* refer to description of parameter "EOCSelection" for more */ + /* details. */ + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } +} + +/** + * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC DMA mode */ + hadc->Instance->CR2 |= ADC_CR2_DMA; + + /* Start the DMA channel */ + status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + /* if dual mode is selected, ADC3 works independently. */ + /* check if the mode selected is not triple */ + if( HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI_4) ) + { + /* if instance of handle correspond to ADC3 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC3) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return status; +} + +/** + * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable the selected ADC DMA mode */ + hadc->Instance->CR2 &= ~ADC_CR2_DMA; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Gets the converted value from data register of regular channel. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval Converted value + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + /* Return the selected ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Regular conversion complete callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Regular conversion half DMA transfer callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Analog watchdog callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file + */ +} + +/** + * @brief Error ADC callback. + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure regular channels. + (+) Configure injected channels. + (+) Configure multimode. + (+) Configure the analog watch dog. + +@endverbatim + * @{ + */ + + /** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param sConfig ADC configuration structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if ((sConfig->Channel > ADC_CHANNEL_9) && (sConfig->Channel != ADC_INTERNAL_NONE)) + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); + + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, ADC_CHANNEL_18); + } + else + { + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); + } + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Clear the old sample time */ + hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); + + /* Set the new sample time */ + hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); + } + + /* For Rank 1 to 6 */ + if (sConfig->Rank < 7) + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); + } + /* For Rank 7 to 12 */ + else if (sConfig->Rank < 13) + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); + } + /* For Rank 13 to 16 */ + else + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); + } + + /* if no internal channel selected */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_INTERNAL_NONE)) + { + /* Disable the VBAT & TSVREFE channel*/ + ADC->CCR &= ~(ADC_CCR_VBATE | ADC_CCR_TSVREFE); + } + + /* if ADC1 Channel_18 is selected enable VBAT Channel */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) + { + /* Disable the TEMPSENSOR channel as it is multiplixed with the VBAT channel */ + ADC->CCR &= ~ADC_CCR_TSVREFE; + + /* Enable the VBAT channel*/ + ADC->CCR |= ADC_CCR_VBATE; + } + + /* if ADC1 Channel_18 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ + if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) + { + /* Disable the VBAT channel as it is multiplixed with TEMPSENSOR channel */ + ADC->CCR &= ~ADC_CCR_VBATE; + + /* Enable the TSVREFE channel*/ + ADC->CCR |= ADC_CCR_TSVREFE; + + if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the analog watchdog. + * @note Analog watchdog thresholds can be modified while ADC conversion + * is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure + * that contains the configuration information of ADC analog watchdog. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ +#ifdef USE_FULL_ASSERT + uint32_t tmp = 0; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters */ + assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + +#ifdef USE_FULL_ASSERT + tmp = ADC_GET_RESOLUTION(hadc); + assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); +#endif /* USE_FULL_ASSERT */ + + /* Process locked */ + __HAL_LOCK(hadc); + + if(AnalogWDGConfig->ITMode == ENABLE) + { + /* Enable the ADC Analog watchdog interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); + } + else + { + /* Disable the ADC Analog watchdog interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); + } + + /* Clear AWDEN, JAWDEN and AWDSGL bits */ + hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); + + /* Set the analog watchdog enable mode */ + hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; + + /* Set the high threshold */ + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; + + /* Set the low threshold */ + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; + + /* Clear the Analog watchdog channel select bits */ + hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; + + /* Set the Analog watchdog channel */ + hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions + * @brief ADC Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the ADC state + (+) Check the ADC Error + +@endverbatim + * @{ + */ + +/** + * @brief return the ADC state + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL state + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +{ + /* Return ADC state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval ADC Error Code + */ +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +{ + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct without initializing the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +static void ADC_Init(ADC_HandleTypeDef* hadc) +{ + /* Set ADC parameters */ + /* Set the ADC clock prescaler */ + ADC->CCR &= ~(ADC_CCR_ADCPRE); + ADC->CCR |= hadc->Init.ClockPrescaler; + + /* Set ADC scan mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); + hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); + + /* Set ADC resolution */ + hadc->Instance->CR1 &= ~(ADC_CR1_RES); + hadc->Instance->CR1 |= hadc->Init.Resolution; + + /* Set ADC data alignment */ + hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); + hadc->Instance->CR2 |= hadc->Init.DataAlign; + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; + + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + } + + /* Enable or disable ADC continuous conversion mode */ + hadc->Instance->CR2 &= ~(ADC_CR2_CONT); + hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); + + if(hadc->Init.DiscontinuousConvMode != DISABLE) + { + assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); + + /* Enable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; + + /* Set the number of channels to be converted in discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); + hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); + } + + /* Set ADC number of conversion */ + hadc->Instance->SQR1 &= ~(ADC_SQR1_L); + hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); + + /* Enable or disable ADC DMA continuous request */ + hadc->Instance->CR2 &= ~(ADC_CR2_DDS); + hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); + + /* Enable or disable ADC end of conversion selection */ + hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); + hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else /* DMA and-or internal error occurred */ + { + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) + { + /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hadc->State= HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c index 669ac290..f4027776 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc_ex.c @@ -1,1069 +1,1070 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_adc_ex.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the ADC extension peripheral: - * + Extended features functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): - (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() - (##) ADC pins configuration - (+++) Enable the clock for the ADC GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE() - (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() - (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) - (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) - (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() - (+++) Configure and enable two DMA streams stream for managing data - transfer from peripheral to memory (output stream) - (+++) Associate the initialized DMA handle to the ADC DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream. - (#) Configure the ADC Prescaler, conversion resolution and data alignment - using the HAL_ADC_Init() function. - - (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() - and HAL_ADC_ConfigChannel() functions. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() - (+) Wait for end of conversion using HAL_ADCEx_InjectedPollForConversion(), at this stage - user can specify the value of timeout according to his end application - (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function. - (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() - (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine - (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback - (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback - (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() - - *** Multi mode ADCs Regular channels configuration *** - ====================================================== - [..] - (+) Select the Multi mode ADC regular channels features (dual or triple mode) - and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. - (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. - - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup ADCEx ADCEx - * @brief ADC Extended driver modules - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup ADCEx_Private_Functions - * @{ - */ -/* Private function prototypes -----------------------------------------------*/ -static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); -static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADCEx_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of injected channel. - (+) Stop conversion of injected channel. - (+) Start multimode and enable DMA transfer. - (+) Stop multimode and disable DMA transfer. - (+) Get result of injected channel conversion. - (+) Get result of multimode conversion. - (+) Configure injected channels. - (+) Configure multimode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables the selected ADC software start conversion of the injected channels. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) -{ - __IO uint32_t counter = 0; - uint32_t tmp1 = 0, tmp2 = 0; - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - - /* Check if a regular conversion is ongoing */ - /* Note: On this device, there is no ADC error code fields related to */ - /* conversions on group injected only. In case of conversion on */ - /* going on group regular, no error code is reset. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - else - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enables the interrupt and starts ADC conversion of injected channels. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) -{ - __IO uint32_t counter = 0; - uint32_t tmp1 = 0, tmp2 = 0; - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for ADC stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to injected group conversion results */ - /* - Set state bitfield related to injected operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, - HAL_ADC_STATE_INJ_BUSY); - - /* Check if a regular conversion is ongoing */ - /* Note: On this device, there is no ADC error code fields related to */ - /* conversions on group injected only. In case of conversion on */ - /* going on group regular, no error code is reset. */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Clear injected group conversion flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Enable end of conversion interrupt for injected channels */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); - - /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - else - { - tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); - tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) - { - /* Enable the selected ADC software conversion for injected group */ - hadc->Instance->CR2 |= ADC_CR2_JSWSTART; - } - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop conversion of injected channels. Disable ADC peripheral if - * no regular conversion is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion and disable ADC peripheral */ - /* Conditioned to: */ - /* - No conversion on the other group (regular group) is intended to */ - /* continue (injected and regular groups stop conversion and ADC disable */ - /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Poll for injected conversion complete - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param Timeout Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) - { - hadc->State= HAL_ADC_STATE_TIMEOUT; - /* Process unlocked */ - __HAL_UNLOCK(hadc); - return HAL_TIMEOUT; - } - } - } - } - - /* Clear injected group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - - /* Determine whether any further conversion upcoming on group injected */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) - { - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Return ADC state */ - return HAL_OK; -} - -/** - * @brief Stop conversion of injected channels, disable interruption of - * end-of-conversion. Disable ADC peripheral if no regular conversion - * is on going. - * @note If ADC must be disabled and if conversion is on going on - * regular group, function HAL_ADC_Stop must be used to stop both - * injected and regular groups, and disable the ADC. - * @note If injected group mode auto-injection is enabled, - * function HAL_ADC_Stop must be used. - * @param hadc ADC handle - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion and disable ADC peripheral */ - /* Conditioned to: */ - /* - No conversion on the other group (regular group) is intended to */ - /* continue (injected and regular groups stop conversion and ADC disable */ - /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) - { - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Disable ADC end of conversion interrupt for injected channels */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Gets the converted value from data register of injected channel. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param InjectedRank the ADC injected rank. - * This parameter can be one of the following values: - * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected - * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected - * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected - * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected - * @retval None - */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) -{ - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - - /* Clear injected group conversion flag to have similar behaviour as */ - /* regular group: reading data register also clears end of conversion flag. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Return the selected ADC converted value */ - switch(InjectedRank) - { - case ADC_INJECTED_RANK_4: - { - tmp = hadc->Instance->JDR4; - } - break; - case ADC_INJECTED_RANK_3: - { - tmp = hadc->Instance->JDR3; - } - break; - case ADC_INJECTED_RANK_2: - { - tmp = hadc->Instance->JDR2; - } - break; - case ADC_INJECTED_RANK_1: - { - tmp = hadc->Instance->JDR1; - } - break; - default: - break; - } - return tmp; -} - -/** - * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral - * - * @note Caution: This function must be used only with the ADC master. - * - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. - * @param Length The length of data to be transferred from ADC peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) -{ - __IO uint32_t counter = 0; - - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Check if ADC peripheral is disabled in order to enable it and wait during - Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { - /* Enable the Peripheral */ - __HAL_ADC_ENABLE(hadc); - - /* Delay for temperature sensor stabilization time */ - /* Compute number of CPU cycles to wait for */ - counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); - while(counter != 0) - { - counter--; - } - } - - /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular group operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, - HAL_ADC_STATE_REG_BUSY); - - /* If conversions on group regular are also triggering group injected, */ - /* update ADC state. */ - if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) - { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - } - - /* State machine update: Check if an injected conversion is ongoing */ - if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); - } - else - { - /* Reset ADC all error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - } - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - if (hadc->Init.DMAContinuousRequests != DISABLE) - { - /* Enable the selected ADC DMA request after last transfer */ - ADC->CCR |= ADC_CCR_DDS; - } - else - { - /* Disable the selected ADC EOC rising on each regular channel conversion */ - ADC->CCR &= ~ADC_CCR_DDS; - } - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); - - /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) - { - /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; - } - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC IP internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Stop potential conversion on going, on regular and injected groups */ - /* Disable ADC peripheral */ - __HAL_ADC_DISABLE(hadc); - - /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) - { - /* Disable the selected ADC DMA mode for multimode */ - ADC->CCR &= ~ADC_CCR_DDS; - - /* Disable the DMA channel (in case of DMA in circular mode or stop while */ - /* DMA transfer is on going) */ - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, - HAL_ADC_STATE_READY); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results - * data in the selected multi mode. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval The converted data value. - */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* Return the multi mode conversion value */ - return ADC->CDR; -} - -/** - * @brief Injected conversion complete callback in non blocking mode - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @retval None - */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Configures for the selected ADC injected channel its corresponding - * rank in the sequencer and its sample time. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param sConfigInjected ADC configuration structure for injected channel. - * @retval None - */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) -{ - -#ifdef USE_FULL_ASSERT - uint32_t tmp = 0; -#endif /* USE_FULL_ASSERT */ - - /* Check the parameters */ - assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); - assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); - assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); - assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); - assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); - assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); - -#ifdef USE_FULL_ASSERT - tmp = ADC_GET_RESOLUTION(hadc); - assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); -#endif /* USE_FULL_ASSERT */ - - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - { - assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ - if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) - { - /* Clear the old sample time */ - hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); - - /* Set the new sample time */ - hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } - else /* ADC_Channel include in ADC_Channel_[0..9] */ - { - /* Clear the old sample time */ - hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); - - /* Set the new sample time */ - hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); - } - - /*---------------------------- ADCx JSQR Configuration -----------------*/ - hadc->Instance->JSQR &= ~(ADC_JSQR_JL); - hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); - - /* Rank configuration */ - - /* Clear the old SQx bits for the selected rank */ - hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); - - /* Set the SQx bits for the selected rank */ - hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - { - /* Select external trigger to start conversion */ - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); - hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; - - /* Select external trigger polarity */ - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); - hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; - } - else - { - /* Reset the external trigger */ - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); - } - - if (sConfigInjected->AutoInjectedConv != DISABLE) - { - /* Enable the selected ADC automatic injected group conversion */ - hadc->Instance->CR1 |= ADC_CR1_JAUTO; - } - else - { - /* Disable the selected ADC automatic injected group conversion */ - hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); - } - - if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) - { - /* Enable the selected ADC injected discontinuous mode */ - hadc->Instance->CR1 |= ADC_CR1_JDISCEN; - } - else - { - /* Disable the selected ADC injected discontinuous mode */ - hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); - } - - switch(sConfigInjected->InjectedRank) - { - case 1: - /* Set injected channel 1 offset */ - hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); - hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; - break; - case 2: - /* Set injected channel 2 offset */ - hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); - hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; - break; - case 3: - /* Set injected channel 3 offset */ - hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); - hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; - break; - default: - /* Set injected channel 4 offset */ - hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); - hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; - break; - } - - /* if ADC1 Channel_18 is selected enable VBAT Channel */ - if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) - { - /* Enable the VBAT channel*/ - ADC->CCR |= ADC_CCR_VBATE; - } - - /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ - if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) - { - /* Enable the TSVREFE channel*/ - ADC->CCR |= ADC_CCR_TSVREFE; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the ADC multi-mode - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains - * the configuration information for multimode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) -{ - /* Check the parameters */ - assert_param(IS_ADC_MODE(multimode->Mode)); - assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); - assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Set ADC mode */ - ADC->CCR &= ~(ADC_CCR_MULTI); - ADC->CCR |= multimode->Mode; - - /* Set the ADC DMA access mode */ - ADC->CCR &= ~(ADC_CCR_DMA); - ADC->CCR |= multimode->DMAAccessMode; - - /* Set delay between two sampling phases */ - ADC->CCR &= ~(ADC_CCR_DELAY); - ADC->CCR |= multimode->TwoSamplingDelay; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - - /** - * @brief DMA transfer complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) - { - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - /* Note: On STM32F7, there is no independent flag of end of sequence. */ - /* The test of scan sequence on going is done either with scan */ - /* sequence disabled or with end of conversion flag set to */ - /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - - /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - - if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - } - - /* Conversion complete callback */ - HAL_ADC_ConvCpltCallback(hadc); - } - else - { - /* Call DMA error callback */ - hadc->DMA_Handle->XferErrorCallback(hdma); - } -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); -} - -/** - * @brief DMA error callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) -{ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - HAL_ADC_ErrorCallback(hadc); -} - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the ADC extension peripheral: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): + (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() + (##) ADC pins configuration + (+++) Enable the clock for the ADC GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE() + (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) + (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams stream for managing data + transfer from peripheral to memory (output stream) + (+++) Associate the initialized DMA handle to the ADC DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA Streams. The output stream should have higher + priority than the input stream. + (#) Configure the ADC Prescaler, conversion resolution and data alignment + using the HAL_ADC_Init() function. + + (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() + and HAL_ADC_ConfigChannel() functions. + + (#) Three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() + (+) Wait for end of conversion using HAL_ADCEx_InjectedPollForConversion(), at this stage + user can specify the value of timeout according to his end application + (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function. + (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() + (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine + (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback + (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback + (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() + + *** Multi mode ADCs Regular channels configuration *** + ====================================================== + [..] + (+) Select the Multi mode ADC regular channels features (dual or triple mode) + and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. + (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC Extended driver modules + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup ADCEx_Private_Functions + * @{ + */ +/* Private function prototypes -----------------------------------------------*/ +static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); +static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of injected channel. + (+) Stop conversion of injected channel. + (+) Start multimode and enable DMA transfer. + (+) Stop multimode and disable DMA transfer. + (+) Get result of injected channel conversion. + (+) Get result of multimode conversion. + (+) Configure injected channels. + (+) Configure multimode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the selected ADC software start conversion of the injected channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0; + uint32_t tmp1 = 0, tmp2 = 0; + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + else + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if((hadc->Instance == ADC1) && tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables the interrupt and starts ADC conversion of injected channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0; + uint32_t tmp1 = 0, tmp2 = 0; + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Enable end of conversion interrupt for injected channels */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + else + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if((hadc->Instance == ADC1) && tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop conversion of injected channels. Disable ADC peripheral if + * no regular conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @note In case of auto-injection mode, HAL_ADC_Stop must be used. + * @param hadc ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Poll for injected conversion complete + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of conversion flag */ + while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + { + hadc->State= HAL_ADC_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + return HAL_TIMEOUT; + } + } + } + } + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Stop conversion of injected channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no regular conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @param hadc ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable ADC end of conversion interrupt for injected channels */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Gets the converted value from data register of injected channel. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param InjectedRank the ADC injected rank. + * This parameter can be one of the following values: + * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected + * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected + * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected + * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected + * @retval None + */ +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); + + /* Clear injected group conversion flag to have similar behaviour as */ + /* regular group: reading data register also clears end of conversion flag. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Return the selected ADC converted value */ + switch(InjectedRank) + { + case ADC_INJECTED_RANK_4: + { + tmp = hadc->Instance->JDR4; + } + break; + case ADC_INJECTED_RANK_3: + { + tmp = hadc->Instance->JDR3; + } + break; + case ADC_INJECTED_RANK_2: + { + tmp = hadc->Instance->JDR2; + } + break; + case ADC_INJECTED_RANK_1: + { + tmp = hadc->Instance->JDR1; + } + break; + default: + break; + } + return tmp; +} + +/** + * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral + * + * @note Caution: This function must be used only with the ADC master. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + __IO uint32_t counter = 0; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); + while(counter != 0) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + if (hadc->Init.DMAContinuousRequests != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + ADC->CCR |= ADC_CCR_DDS; + } + else + { + /* Disable the selected ADC EOC rising on each regular channel conversion */ + ADC->CCR &= ~ADC_CCR_DDS; + } + + /* Enable the DMA Stream */ + tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); + + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable the selected ADC DMA mode for multimode */ + ADC->CCR &= ~ADC_CCR_DDS; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + * data in the selected multi mode. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval The converted data value. + */ +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + + /* Return the multi mode conversion value */ + return ADC->CDR; +} + +/** + * @brief Injected conversion complete callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param sConfigInjected ADC configuration structure for injected channel. + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +{ + +#ifdef USE_FULL_ASSERT + uint32_t tmp = 0; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters */ + assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); + assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + +#ifdef USE_FULL_ASSERT + tmp = ADC_GET_RESOLUTION(hadc); + assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); +#endif /* USE_FULL_ASSERT */ + + if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); + + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Clear the old sample time */ + hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); + + /* Set the new sample time */ + hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); + } + + /*---------------------------- ADCx JSQR Configuration -----------------*/ + hadc->Instance->JSQR &= ~(ADC_JSQR_JL); + hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); + + /* Rank configuration */ + + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + } + + if (sConfigInjected->AutoInjectedConv != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + hadc->Instance->CR1 |= ADC_CR1_JAUTO; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); + } + + if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + hadc->Instance->CR1 |= ADC_CR1_JDISCEN; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); + } + + switch(sConfigInjected->InjectedRank) + { + case 1: + /* Set injected channel 1 offset */ + hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); + hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; + break; + case 2: + /* Set injected channel 2 offset */ + hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); + hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; + break; + case 3: + /* Set injected channel 3 offset */ + hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); + hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; + break; + default: + /* Set injected channel 4 offset */ + hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); + hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; + break; + } + + /* if ADC1 Channel_18 is selected enable VBAT Channel */ + if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) + { + /* Enable the VBAT channel*/ + ADC->CCR |= ADC_CCR_VBATE; + } + + /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ + if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) + { + /* Enable the TSVREFE channel*/ + ADC->CCR |= ADC_CCR_TSVREFE; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the ADC multi-mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains + * the configuration information for multimode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +{ + /* Check the parameters */ + assert_param(IS_ADC_MODE(multimode->Mode)); + assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Set ADC mode */ + ADC->CCR &= ~(ADC_CCR_MULTI); + ADC->CCR |= multimode->Mode; + + /* Set the ADC DMA access mode */ + ADC->CCR &= ~(ADC_CCR_DMA); + ADC->CCR |= multimode->DMAAccessMode; + + /* Set delay between two sampling phases */ + ADC->CCR &= ~(ADC_CCR_DELAY); + ADC->CCR |= multimode->TwoSamplingDelay; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + + /** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F7, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hadc->State= HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + HAL_ADC_ErrorCallback(hadc); +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c index 06cb5483..b815cdb5 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_can.c @@ -1,2464 +1,2466 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_can.c - * @author MCD Application Team - * @brief CAN HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Controller Area Network (CAN) peripheral: - * + Initialization and de-initialization functions - * + Configuration functions - * + Control functions - * + Interrupts management - * + Callbacks functions - * + Peripheral State and Error functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the CAN low level resources by implementing the - HAL_CAN_MspInit(): - (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() - (++) Configure CAN pins - (+++) Enable the clock for the CAN GPIOs - (+++) Configure CAN pins as alternate function - (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) - (+++) Configure the CAN interrupt priority using - HAL_NVIC_SetPriority() - (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() - - (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This - function resorts to HAL_CAN_MspInit() for low-level initialization. - - (#) Configure the reception filters using the following configuration - functions: - (++) HAL_CAN_ConfigFilter() - - (#) Start the CAN module using HAL_CAN_Start() function. At this level - the node is active on the bus: it receive messages, and can send - messages. - - (#) To manage messages transmission, the following Tx control functions - can be used: - (++) HAL_CAN_AddTxMessage() to request transmission of a new - message. - (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending - message. - (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx - mailboxes. - (++) HAL_CAN_IsTxMessagePending() to check if a message is pending - in a Tx mailbox. - (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message - sent, if time triggered communication mode is enabled. - - (#) When a message is received into the CAN Rx FIFOs, it can be retrieved - using the HAL_CAN_GetRxMessage() function. The function - HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are - stored in the Rx Fifo. - - (#) Calling the HAL_CAN_Stop() function stops the CAN module. - - (#) The deinitialization is achieved with HAL_CAN_DeInit() function. - - - *** Polling mode operation *** - ============================== - [..] - (#) Reception: - (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() - until at least one message is received. - (++) Then get the message using HAL_CAN_GetRxMessage(). - - (#) Transmission: - (++) Monitor the Tx mailboxes availability until at least one Tx - mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). - (++) Then request transmission of a message using - HAL_CAN_AddTxMessage(). - - - *** Interrupt mode operation *** - ================================ - [..] - (#) Notifications are activated using HAL_CAN_ActivateNotification() - function. Then, the process can be controlled through the - available user callbacks: HAL_CAN_xxxCallback(), using same APIs - HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). - - (#) Notifications can be deactivated using - HAL_CAN_DeactivateNotification() function. - - (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and - CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig - the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and - HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options - here. - (++) Directly get the Rx message in the callback, using - HAL_CAN_GetRxMessage(). - (++) Or deactivate the notification in the callback without - getting the Rx message. The Rx message can then be got later - using HAL_CAN_GetRxMessage(). Once the Rx message have been - read, the notification can be activated again. - - - *** Sleep mode *** - ================== - [..] - (#) The CAN peripheral can be put in sleep mode (low power), using - HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the - current CAN activity (transmission or reception of a CAN frame) will - be completed. - - (#) A notification can be activated to be informed when the sleep mode - will be entered. - - (#) It can be checked if the sleep mode is entered using - HAL_CAN_IsSleepActive(). - Note that the CAN state (accessible from the API HAL_CAN_GetState()) - is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is - submitted (the sleep mode is not yet entered), and become - HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. - - (#) The wake-up from sleep mode can be triggered by two ways: - (++) Using HAL_CAN_WakeUp(). When returning from this function, - the sleep mode is exited (if return status is HAL_OK). - (++) When a start of Rx CAN frame is detected by the CAN peripheral, - if automatic wake up mode is enabled. - - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. - - Function HAL_CAN_RegisterCallback() allows to register following callbacks: - (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. - (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. - (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. - (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. - (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. - (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. - (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. - (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. - (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. - (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. - (+) SleepCallback : Sleep Callback. - (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. - (+) ErrorCallback : Error Callback. - (+) MspInitCallback : CAN MspInit. - (+) MspDeInitCallback : CAN MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. - (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. - (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. - (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. - (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. - (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. - (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. - (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. - (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. - (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. - (+) SleepCallback : Sleep Callback. - (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. - (+) ErrorCallback : Error Callback. - (+) MspInitCallback : CAN MspInit. - (+) MspDeInitCallback : CAN MspDeInit. - - By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, - all callbacks are set to the corresponding weak functions: - example HAL_CAN_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() - or HAL_CAN_Init() function. - - When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined(CAN1) - -/** @defgroup CAN CAN - * @brief CAN driver modules - * @{ - */ - -#ifdef HAL_CAN_MODULE_ENABLED - -#ifdef HAL_CAN_LEGACY_MODULE_ENABLED -#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" -#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup CAN_Private_Constants CAN Private Constants - * @{ - */ -#define CAN_TIMEOUT_VALUE 10U -#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CAN_Exported_Functions CAN Exported Functions - * @{ - */ - -/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_Init : Initialize and configure the CAN. - (+) HAL_CAN_DeInit : De-initialize the CAN. - (+) HAL_CAN_MspInit : Initialize the CAN MSP. - (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CAN peripheral according to the specified - * parameters in the CAN_InitStruct. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - /* Check CAN handle */ - if (hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); - assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); - assert_param(IS_CAN_MODE(hcan->Init.Mode)); - assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); - assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); - assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); - assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - if (hcan->State == HAL_CAN_STATE_RESET) - { - /* Reset callbacks to legacy functions */ - hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ - hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ - hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ - hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ - hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ - hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ - hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ - hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ - hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ - hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ - hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ - hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ - hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hcan->MspInitCallback == NULL) - { - hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware: CLOCK, NVIC */ - hcan->MspInitCallback(hcan); - } - -#else - if (hcan->State == HAL_CAN_STATE_RESET) - { - /* Init the low level hardware: CLOCK, NVIC */ - HAL_CAN_MspInit(hcan); - } -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait initialisation acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - { - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check Sleep mode leave acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Set the time triggered communication mode */ - if (hcan->Init.TimeTriggeredMode == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); - } - - /* Set the automatic bus-off management */ - if (hcan->Init.AutoBusOff == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); - } - - /* Set the automatic wake-up mode */ - if (hcan->Init.AutoWakeUp == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); - } - - /* Set the automatic retransmission */ - if (hcan->Init.AutoRetransmission == ENABLE) - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); - } - else - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); - } - - /* Set the receive FIFO locked mode */ - if (hcan->Init.ReceiveFifoLocked == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); - } - - /* Set the transmit FIFO priority */ - if (hcan->Init.TransmitFifoPriority == ENABLE) - { - SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - } - else - { - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); - } - - /* Set the bit timing register */ - WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | - hcan->Init.SyncJumpWidth | - hcan->Init.TimeSeg1 | - hcan->Init.TimeSeg2 | - (hcan->Init.Prescaler - 1U))); - - /* Initialize the error code */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Initialize the CAN state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Deinitializes the CAN peripheral registers to their default - * reset values. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) -{ - /* Check CAN handle */ - if (hcan == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); - - /* Stop the CAN module */ - (void)HAL_CAN_Stop(hcan); - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - if (hcan->MspDeInitCallback == NULL) - { - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: CLOCK, NVIC */ - hcan->MspDeInitCallback(hcan); - -#else - /* DeInit the low level hardware: CLOCK, NVIC */ - HAL_CAN_MspDeInit(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - - /* Reset the CAN peripheral */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); - - /* Reset the CAN ErrorCode */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_RESET; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CAN MSP. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the CAN MSP. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_MspDeInit could be implemented in the user file - */ -} - -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 -/** - * @brief Register a CAN CallBack. - * To be used instead of the weak predefined callback - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for CAN module - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, - void (* pCallback)(CAN_HandleTypeDef *_hcan)) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (hcan->State == HAL_CAN_STATE_READY) - { - switch (CallbackID) - { - case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : - hcan->TxMailbox0CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : - hcan->TxMailbox1CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : - hcan->TxMailbox2CompleteCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : - hcan->TxMailbox0AbortCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : - hcan->TxMailbox1AbortCallback = pCallback; - break; - - case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : - hcan->TxMailbox2AbortCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : - hcan->RxFifo0MsgPendingCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO0_FULL_CB_ID : - hcan->RxFifo0FullCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : - hcan->RxFifo1MsgPendingCallback = pCallback; - break; - - case HAL_CAN_RX_FIFO1_FULL_CB_ID : - hcan->RxFifo1FullCallback = pCallback; - break; - - case HAL_CAN_SLEEP_CB_ID : - hcan->SleepCallback = pCallback; - break; - - case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : - hcan->WakeUpFromRxMsgCallback = pCallback; - break; - - case HAL_CAN_ERROR_CB_ID : - hcan->ErrorCallback = pCallback; - break; - - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = pCallback; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcan->State == HAL_CAN_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = pCallback; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a CAN CallBack. - * CAN callback is redirected to the weak predefined callback - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for CAN module - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hcan->State == HAL_CAN_STATE_READY) - { - switch (CallbackID) - { - case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : - hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : - hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : - hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; - break; - - case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : - hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; - break; - - case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : - hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; - break; - - case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : - hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; - break; - - case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : - hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; - break; - - case HAL_CAN_RX_FIFO0_FULL_CB_ID : - hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; - break; - - case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : - hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; - break; - - case HAL_CAN_RX_FIFO1_FULL_CB_ID : - hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; - break; - - case HAL_CAN_SLEEP_CB_ID : - hcan->SleepCallback = HAL_CAN_SleepCallback; - break; - - case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : - hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; - break; - - case HAL_CAN_ERROR_CB_ID : - hcan->ErrorCallback = HAL_CAN_ErrorCallback; - break; - - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = HAL_CAN_MspInit; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcan->State == HAL_CAN_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CAN_MSPINIT_CB_ID : - hcan->MspInitCallback = HAL_CAN_MspInit; - break; - - case HAL_CAN_MSPDEINIT_CB_ID : - hcan->MspDeInitCallback = HAL_CAN_MspDeInit; - break; - - default : - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group2 Configuration functions - * @brief Configuration functions. - * -@verbatim - ============================================================================== - ##### Configuration functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters - -@endverbatim - * @{ - */ - -/** - * @brief Configures the CAN reception filter according to the specified - * parameters in the CAN_FilterInitStruct. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that - * contains the filter configuration information. - * @retval None - */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) -{ - uint32_t filternbrbitpos; - CAN_TypeDef *can_ip = hcan->Instance; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check the parameters */ - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); - assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); - assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); - assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); - assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); - assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); - -#if defined(CAN3) - /* Check the CAN instance */ - if (hcan->Instance == CAN3) - { - /* CAN3 is single instance with 14 dedicated filters banks */ - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); - } - else - { - /* CAN1 and CAN2 are dual instances with 28 common filters banks */ - /* Select master instance to access the filter banks */ - can_ip = CAN1; - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); - assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); - } -#elif defined(CAN2) - /* CAN1 and CAN2 are dual instances with 28 common filters banks */ - /* Select master instance to access the filter banks */ - can_ip = CAN1; - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); - assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); -#else - /* CAN1 is single instance with 14 dedicated filters banks */ - - /* Check the parameters */ - assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); -#endif /* CAN3 */ - - /* Initialisation mode for the filter */ - SET_BIT(can_ip->FMR, CAN_FMR_FINIT); - -#if defined(CAN3) - /* Check the CAN instance */ - if (can_ip == CAN1) - { - /* Select the start filter number of CAN2 slave instance */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); - SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); - } - -#elif defined(CAN2) - /* Select the start filter number of CAN2 slave instance */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); - SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); - -#endif /* CAN3 */ - /* Convert filter number into bit position */ - filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); - - /* Filter Deactivation */ - CLEAR_BIT(can_ip->FA1R, filternbrbitpos); - - /* Filter Scale */ - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) - { - /* 16-bit scale for the filter */ - CLEAR_BIT(can_ip->FS1R, filternbrbitpos); - - /* First 16-bit identifier and First 16-bit mask */ - /* Or First 16-bit identifier and Second 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* Second 16-bit identifier and Second 16-bit mask */ - /* Or Third 16-bit identifier and Fourth 16-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); - } - - if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) - { - /* 32-bit scale for the filter */ - SET_BIT(can_ip->FS1R, filternbrbitpos); - - /* 32-bit identifier or First 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); - - /* 32-bit mask or Second 32-bit identifier */ - can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = - ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | - (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); - } - - /* Filter Mode */ - if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) - { - /* Id/Mask mode for the filter*/ - CLEAR_BIT(can_ip->FM1R, filternbrbitpos); - } - else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ - { - /* Identifier list mode for the filter*/ - SET_BIT(can_ip->FM1R, filternbrbitpos); - } - - /* Filter FIFO assignment */ - if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) - { - /* FIFO 0 assignation for the filter */ - CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); - } - else - { - /* FIFO 1 assignation for the filter */ - SET_BIT(can_ip->FFA1R, filternbrbitpos); - } - - /* Filter activation */ - if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) - { - SET_BIT(can_ip->FA1R, filternbrbitpos); - } - - /* Leave the initialisation mode for the filter */ - CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group3 Control functions - * @brief Control functions - * -@verbatim - ============================================================================== - ##### Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_Start : Start the CAN module - (+) HAL_CAN_Stop : Stop the CAN module - (+) HAL_CAN_RequestSleep : Request sleep mode entry. - (+) HAL_CAN_WakeUp : Wake up from sleep mode. - (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. - (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes - and activate the corresponding - transmission request - (+) HAL_CAN_AbortTxRequest : Abort transmission request - (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level - (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is - pending on the selected Tx mailbox - (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO - (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level - -@endverbatim - * @{ - */ - -/** - * @brief Start the CAN module. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - if (hcan->State == HAL_CAN_STATE_READY) - { - /* Change CAN peripheral state */ - hcan->State = HAL_CAN_STATE_LISTENING; - - /* Request leave initialisation */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Reset the CAN ErrorCode */ - hcan->ErrorCode = HAL_CAN_ERROR_NONE; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; - - return HAL_ERROR; - } -} - -/** - * @brief Stop the CAN module and enable access to configuration registers. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) -{ - uint32_t tickstart; - - if (hcan->State == HAL_CAN_STATE_LISTENING) - { - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - /* Change CAN state */ - hcan->State = HAL_CAN_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Change CAN peripheral state */ - hcan->State = HAL_CAN_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; - - return HAL_ERROR; - } -} - -/** - * @brief Request the sleep mode (low power) entry. - * When returning from this function, Sleep mode will be entered - * as soon as the current CAN activity (transmission or reception - * of a CAN frame) has been completed. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Request Sleep mode */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Wake up from sleep mode. - * When returning with HAL_OK status from this function, Sleep mode - * is exited. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) -{ - __IO uint32_t count = 0; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Wake up request */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); - - /* Wait sleep mode is exited */ - do - { - /* Increment counter */ - count++; - - /* Check if timeout is reached */ - if (count > CAN_WAKEUP_TIMEOUT_COUNTER) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; - - return HAL_ERROR; - } - } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Check is sleep mode is active. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval Status - * - 0 : Sleep mode is not active. - * - 1 : Sleep mode is active. - */ -uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) -{ - uint32_t status = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Sleep mode */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - status = 1U; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Add a message to the first free Tx mailbox and activate the - * corresponding transmission request. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. - * @param aData array containing the payload of the Tx frame. - * @param pTxMailbox pointer to a variable where the function will return - * the TxMailbox used to store the Tx message. - * This parameter can be a value of @arg CAN_Tx_Mailboxes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, - const uint8_t aData[], uint32_t *pTxMailbox) -{ - uint32_t transmitmailbox; - HAL_CAN_StateTypeDef state = hcan->State; - uint32_t tsr = READ_REG(hcan->Instance->TSR); - - /* Check the parameters */ - assert_param(IS_CAN_IDTYPE(pHeader->IDE)); - assert_param(IS_CAN_RTR(pHeader->RTR)); - assert_param(IS_CAN_DLC(pHeader->DLC)); - if (pHeader->IDE == CAN_ID_STD) - { - assert_param(IS_CAN_STDID(pHeader->StdId)); - } - else - { - assert_param(IS_CAN_EXTID(pHeader->ExtId)); - } - assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check that all the Tx mailboxes are not full */ - if (((tsr & CAN_TSR_TME0) != 0U) || - ((tsr & CAN_TSR_TME1) != 0U) || - ((tsr & CAN_TSR_TME2) != 0U)) - { - /* Select an empty transmit mailbox */ - transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; - - /* Store the Tx mailbox */ - *pTxMailbox = (uint32_t)1 << transmitmailbox; - - /* Set up the Id */ - if (pHeader->IDE == CAN_ID_STD) - { - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | - pHeader->RTR); - } - else - { - hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | - pHeader->IDE | - pHeader->RTR); - } - - /* Set up the DLC */ - hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); - - /* Set up the Transmit Global Time mode */ - if (pHeader->TransmitGlobalTime == ENABLE) - { - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); - } - - /* Set up the data field */ - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, - ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | - ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | - ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | - ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); - WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, - ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | - ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | - ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | - ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); - - /* Request transmission */ - SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Abort transmission requests - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailboxes List of the Tx Mailboxes to abort. - * This parameter can be any combination of @arg CAN_Tx_Mailboxes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Tx Mailbox 0 */ - if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) - { - /* Add cancellation request for Tx Mailbox 0 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); - } - - /* Check Tx Mailbox 1 */ - if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) - { - /* Add cancellation request for Tx Mailbox 1 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); - } - - /* Check Tx Mailbox 2 */ - if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) - { - /* Add cancellation request for Tx Mailbox 2 */ - SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); - } - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval Number of free Tx Mailboxes. - */ -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) -{ - uint32_t freelevel = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check Tx Mailbox 0 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) - { - freelevel++; - } - - /* Check Tx Mailbox 1 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) - { - freelevel++; - } - - /* Check Tx Mailbox 2 status */ - if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) - { - freelevel++; - } - } - - /* Return Tx Mailboxes free level */ - return freelevel; -} - -/** - * @brief Check if a transmission request is pending on the selected Tx - * Mailboxes. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailboxes List of Tx Mailboxes to check. - * This parameter can be any combination of @arg CAN_Tx_Mailboxes. - * @retval Status - * - 0 : No pending transmission request on any selected Tx Mailboxes. - * - 1 : Pending transmission request on at least one of the selected - * Tx Mailbox. - */ -uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) -{ - uint32_t status = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check pending transmission request on the selected Tx Mailboxes */ - if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) - { - status = 1U; - } - } - - /* Return status */ - return status; -} - -/** - * @brief Return timestamp of Tx message sent, if time triggered communication - mode is enabled. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param TxMailbox Tx Mailbox where the timestamp of message sent will be - * read. - * This parameter can be one value of @arg CAN_Tx_Mailboxes. - * @retval Timestamp of message sent from Tx Mailbox. - */ -uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) -{ - uint32_t timestamp = 0U; - uint32_t transmitmailbox; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Select the Tx mailbox */ - transmitmailbox = POSITION_VAL(TxMailbox); - - /* Get timestamp */ - timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; - } - - /* Return the timestamp */ - return timestamp; -} - -/** - * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param RxFifo Fifo number of the received message to be read. - * This parameter can be a value of @arg CAN_receive_FIFO_number. - * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header - * of the Rx frame will be stored. - * @param aData array where the payload of the Rx frame will be stored. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, - CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - assert_param(IS_CAN_RX_FIFO(RxFifo)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check the Rx FIFO */ - if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - { - /* Check that the Rx FIFO 0 is not empty */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - else /* Rx element is assigned to Rx FIFO 1 */ - { - /* Check that the Rx FIFO 1 is not empty */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; - - return HAL_ERROR; - } - } - - /* Get the header */ - pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; - if (pHeader->IDE == CAN_ID_STD) - { - pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; - } - else - { - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & - hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; - } - pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); - if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) - { - /* Truncate DLC to 8 if received field is over range */ - pHeader->DLC = 8U; - } - else - { - pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; - } - pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; - pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; - - /* Get the data */ - aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); - aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); - aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); - aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); - aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); - aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); - aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); - aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); - - /* Release the FIFO */ - if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ - { - /* Release RX FIFO 0 */ - SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); - } - else /* Rx element is assigned to Rx FIFO 1 */ - { - /* Release RX FIFO 1 */ - SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); - } - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Return Rx FIFO fill level. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param RxFifo Rx FIFO. - * This parameter can be a value of @arg CAN_receive_FIFO_number. - * @retval Number of messages available in Rx FIFO. - */ -uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) -{ - uint32_t filllevel = 0U; - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_RX_FIFO(RxFifo)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - if (RxFifo == CAN_RX_FIFO0) - { - filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; - } - else /* RxFifo == CAN_RX_FIFO1 */ - { - filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; - } - } - - /* Return Rx FIFO fill level */ - return filllevel; -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group4 Interrupts management - * @brief Interrupts management - * -@verbatim - ============================================================================== - ##### Interrupts management ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_CAN_ActivateNotification : Enable interrupts - (+) HAL_CAN_DeactivateNotification : Disable interrupts - (+) HAL_CAN_IRQHandler : Handles CAN interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Enable interrupts. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param ActiveITs indicates which interrupts will be enabled. - * This parameter can be any combination of @arg CAN_Interrupts. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_IT(ActiveITs)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Enable the selected interrupts */ - __HAL_CAN_ENABLE_IT(hcan, ActiveITs); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Disable interrupts. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @param InactiveITs indicates which interrupts will be disabled. - * This parameter can be any combination of @arg CAN_Interrupts. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - /* Check function parameters */ - assert_param(IS_CAN_IT(InactiveITs)); - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Disable the selected interrupts */ - __HAL_CAN_DISABLE_IT(hcan, InactiveITs); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - return HAL_ERROR; - } -} - -/** - * @brief Handles CAN interrupt request - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) -{ - uint32_t errorcode = HAL_CAN_ERROR_NONE; - uint32_t interrupts = READ_REG(hcan->Instance->IER); - uint32_t msrflags = READ_REG(hcan->Instance->MSR); - uint32_t tsrflags = READ_REG(hcan->Instance->TSR); - uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); - uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); - uint32_t esrflags = READ_REG(hcan->Instance->ESR); - - /* Transmit Mailbox empty interrupt management *****************************/ - if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) - { - /* Transmit Mailbox 0 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP0) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); - - if ((tsrflags & CAN_TSR_TXOK0) != 0U) - { - /* Transmission Mailbox 0 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox0CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox0CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST0) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST0; - } - else if ((tsrflags & CAN_TSR_TERR0) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR0; - } - else - { - /* Transmission Mailbox 0 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox0AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox0AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - - /* Transmit Mailbox 1 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP1) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); - - if ((tsrflags & CAN_TSR_TXOK1) != 0U) - { - /* Transmission Mailbox 1 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox1CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox1CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST1) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST1; - } - else if ((tsrflags & CAN_TSR_TERR1) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR1; - } - else - { - /* Transmission Mailbox 1 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox1AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox1AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - - /* Transmit Mailbox 2 management *****************************************/ - if ((tsrflags & CAN_TSR_RQCP2) != 0U) - { - /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); - - if ((tsrflags & CAN_TSR_TXOK2) != 0U) - { - /* Transmission Mailbox 2 complete callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox2CompleteCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox2CompleteCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - else - { - if ((tsrflags & CAN_TSR_ALST2) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_ALST2; - } - else if ((tsrflags & CAN_TSR_TERR2) != 0U) - { - /* Update error code */ - errorcode |= HAL_CAN_ERROR_TX_TERR2; - } - else - { - /* Transmission Mailbox 2 abort callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->TxMailbox2AbortCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_TxMailbox2AbortCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - } - } - - /* Receive FIFO 0 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) - { - if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) - { - /* Set CAN error code to Rx Fifo 0 overrun error */ - errorcode |= HAL_CAN_ERROR_RX_FOV0; - - /* Clear FIFO0 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); - } - } - - /* Receive FIFO 0 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) - { - if ((rf0rflags & CAN_RF0R_FULL0) != 0U) - { - /* Clear FIFO 0 full Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); - - /* Receive FIFO 0 full Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo0FullCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo0FullCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 0 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) - { - /* Check if message is still pending */ - if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) - { - /* Receive FIFO 0 message pending Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo0MsgPendingCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo0MsgPendingCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 1 overrun interrupt management *****************************/ - if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) - { - if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) - { - /* Set CAN error code to Rx Fifo 1 overrun error */ - errorcode |= HAL_CAN_ERROR_RX_FOV1; - - /* Clear FIFO1 Overrun Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); - } - } - - /* Receive FIFO 1 full interrupt management ********************************/ - if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) - { - if ((rf1rflags & CAN_RF1R_FULL1) != 0U) - { - /* Clear FIFO 1 full Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); - - /* Receive FIFO 1 full Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo1FullCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo1FullCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Receive FIFO 1 message pending interrupt management *********************/ - if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) - { - /* Check if message is still pending */ - if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) - { - /* Receive FIFO 1 message pending Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->RxFifo1MsgPendingCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_RxFifo1MsgPendingCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Sleep interrupt management *********************************************/ - if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) - { - if ((msrflags & CAN_MSR_SLAKI) != 0U) - { - /* Clear Sleep interrupt Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); - - /* Sleep Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->SleepCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_SleepCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* WakeUp interrupt management *********************************************/ - if ((interrupts & CAN_IT_WAKEUP) != 0U) - { - if ((msrflags & CAN_MSR_WKUI) != 0U) - { - /* Clear WakeUp Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); - - /* WakeUp Callback */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->WakeUpFromRxMsgCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_WakeUpFromRxMsgCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } - } - - /* Error interrupts management *********************************************/ - if ((interrupts & CAN_IT_ERROR) != 0U) - { - if ((msrflags & CAN_MSR_ERRI) != 0U) - { - /* Check Error Warning Flag */ - if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && - ((esrflags & CAN_ESR_EWGF) != 0U)) - { - /* Set CAN error code to Error Warning */ - errorcode |= HAL_CAN_ERROR_EWG; - - /* No need for clear of Error Warning Flag as read-only */ - } - - /* Check Error Passive Flag */ - if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && - ((esrflags & CAN_ESR_EPVF) != 0U)) - { - /* Set CAN error code to Error Passive */ - errorcode |= HAL_CAN_ERROR_EPV; - - /* No need for clear of Error Passive Flag as read-only */ - } - - /* Check Bus-off Flag */ - if (((interrupts & CAN_IT_BUSOFF) != 0U) && - ((esrflags & CAN_ESR_BOFF) != 0U)) - { - /* Set CAN error code to Bus-Off */ - errorcode |= HAL_CAN_ERROR_BOF; - - /* No need for clear of Error Bus-Off as read-only */ - } - - /* Check Last Error Code Flag */ - if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && - ((esrflags & CAN_ESR_LEC) != 0U)) - { - switch (esrflags & CAN_ESR_LEC) - { - case (CAN_ESR_LEC_0): - /* Set CAN error code to Stuff error */ - errorcode |= HAL_CAN_ERROR_STF; - break; - case (CAN_ESR_LEC_1): - /* Set CAN error code to Form error */ - errorcode |= HAL_CAN_ERROR_FOR; - break; - case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): - /* Set CAN error code to Acknowledgement error */ - errorcode |= HAL_CAN_ERROR_ACK; - break; - case (CAN_ESR_LEC_2): - /* Set CAN error code to Bit recessive error */ - errorcode |= HAL_CAN_ERROR_BR; - break; - case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): - /* Set CAN error code to Bit Dominant error */ - errorcode |= HAL_CAN_ERROR_BD; - break; - case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): - /* Set CAN error code to CRC error */ - errorcode |= HAL_CAN_ERROR_CRC; - break; - default: - break; - } - - /* Clear Last error code Flag */ - CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); - } - } - - /* Clear ERRI Flag */ - __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); - } - - /* Call the Error call Back in case of Errors */ - if (errorcode != HAL_CAN_ERROR_NONE) - { - /* Update error code in handle */ - hcan->ErrorCode |= errorcode; - - /* Call Error callback function */ -#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 - /* Call registered callback*/ - hcan->ErrorCallback(hcan); -#else - /* Call weak (surcharged) callback */ - HAL_CAN_ErrorCallback(hcan); -#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ - } -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group5 Callback functions - * @brief CAN Callback functions - * -@verbatim - ============================================================================== - ##### Callback functions ##### - ============================================================================== - [..] - This subsection provides the following callback functions: - (+) HAL_CAN_TxMailbox0CompleteCallback - (+) HAL_CAN_TxMailbox1CompleteCallback - (+) HAL_CAN_TxMailbox2CompleteCallback - (+) HAL_CAN_TxMailbox0AbortCallback - (+) HAL_CAN_TxMailbox1AbortCallback - (+) HAL_CAN_TxMailbox2AbortCallback - (+) HAL_CAN_RxFifo0MsgPendingCallback - (+) HAL_CAN_RxFifo0FullCallback - (+) HAL_CAN_RxFifo1MsgPendingCallback - (+) HAL_CAN_RxFifo1FullCallback - (+) HAL_CAN_SleepCallback - (+) HAL_CAN_WakeUpFromRxMsgCallback - (+) HAL_CAN_ErrorCallback - -@endverbatim - * @{ - */ - -/** - * @brief Transmission Mailbox 0 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 1 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 2 complete callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 0 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox0AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 1 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox1AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Transmission Mailbox 2 Cancellation callback. - * @param hcan pointer to an CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_TxMailbox2AbortCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 0 message pending callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 0 full callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo0FullCallback could be implemented in the user - file - */ -} - -/** - * @brief Rx FIFO 1 message pending callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the - user file - */ -} - -/** - * @brief Rx FIFO 1 full callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_RxFifo1FullCallback could be implemented in the user - file - */ -} - -/** - * @brief Sleep callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_SleepCallback could be implemented in the user file - */ -} - -/** - * @brief WakeUp from Rx message callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the - user file - */ -} - -/** - * @brief Error CAN callback. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval None - */ -__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcan); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CAN_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions - * @brief CAN Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) HAL_CAN_GetState() : Return the CAN state. - (+) HAL_CAN_GetError() : Return the CAN error codes if any. - (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. - -@endverbatim - * @{ - */ - -/** - * @brief Return the CAN state. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL state - */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) -{ - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Check sleep mode acknowledge flag */ - if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) - { - /* Sleep mode is active */ - state = HAL_CAN_STATE_SLEEP_ACTIVE; - } - /* Check sleep mode request flag */ - else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) - { - /* Sleep mode request is pending */ - state = HAL_CAN_STATE_SLEEP_PENDING; - } - else - { - /* Neither sleep mode request nor sleep mode acknowledge */ - } - } - - /* Return CAN state */ - return state; -} - -/** - * @brief Return the CAN error code. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval CAN Error Code - */ -uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) -{ - /* Return CAN error code */ - return hcan->ErrorCode; -} - -/** - * @brief Reset the CAN error code. - * @param hcan pointer to a CAN_HandleTypeDef structure that contains - * the configuration information for the specified CAN. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_CAN_StateTypeDef state = hcan->State; - - if ((state == HAL_CAN_STATE_READY) || - (state == HAL_CAN_STATE_LISTENING)) - { - /* Reset CAN error code */ - hcan->ErrorCode = 0U; - } - else - { - /* Update error code */ - hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; - - status = HAL_ERROR; - } - - /* Return the status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CAN_MODULE_ENABLED */ - -/** - * @} - */ - -#endif /* CAN1 */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_can.c + * @author MCD Application Team + * @brief CAN HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Controller Area Network (CAN) peripheral: + * + Initialization and de-initialization functions + * + Configuration functions + * + Control functions + * + Interrupts management + * + Callbacks functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the CAN low level resources by implementing the + HAL_CAN_MspInit(): + (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE() + (++) Configure CAN pins + (+++) Enable the clock for the CAN GPIOs + (+++) Configure CAN pins as alternate function + (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification()) + (+++) Configure the CAN interrupt priority using + HAL_NVIC_SetPriority() + (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler() + + (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This + function resorts to HAL_CAN_MspInit() for low-level initialization. + + (#) Configure the reception filters using the following configuration + functions: + (++) HAL_CAN_ConfigFilter() + + (#) Start the CAN module using HAL_CAN_Start() function. At this level + the node is active on the bus: it receive messages, and can send + messages. + + (#) To manage messages transmission, the following Tx control functions + can be used: + (++) HAL_CAN_AddTxMessage() to request transmission of a new + message. + (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending + message. + (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx + mailboxes. + (++) HAL_CAN_IsTxMessagePending() to check if a message is pending + in a Tx mailbox. + (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message + sent, if time triggered communication mode is enabled. + + (#) When a message is received into the CAN Rx FIFOs, it can be retrieved + using the HAL_CAN_GetRxMessage() function. The function + HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are + stored in the Rx Fifo. + + (#) Calling the HAL_CAN_Stop() function stops the CAN module. + + (#) The deinitialization is achieved with HAL_CAN_DeInit() function. + + + *** Polling mode operation *** + ============================== + [..] + (#) Reception: + (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel() + until at least one message is received. + (++) Then get the message using HAL_CAN_GetRxMessage(). + + (#) Transmission: + (++) Monitor the Tx mailboxes availability until at least one Tx + mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel(). + (++) Then request transmission of a message using + HAL_CAN_AddTxMessage(). + + + *** Interrupt mode operation *** + ================================ + [..] + (#) Notifications are activated using HAL_CAN_ActivateNotification() + function. Then, the process can be controlled through the + available user callbacks: HAL_CAN_xxxCallback(), using same APIs + HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage(). + + (#) Notifications can be deactivated using + HAL_CAN_DeactivateNotification() function. + + (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and + CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig + the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and + HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options + here. + (++) Directly get the Rx message in the callback, using + HAL_CAN_GetRxMessage(). + (++) Or deactivate the notification in the callback without + getting the Rx message. The Rx message can then be got later + using HAL_CAN_GetRxMessage(). Once the Rx message have been + read, the notification can be activated again. + + + *** Sleep mode *** + ================== + [..] + (#) The CAN peripheral can be put in sleep mode (low power), using + HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the + current CAN activity (transmission or reception of a CAN frame) will + be completed. + + (#) A notification can be activated to be informed when the sleep mode + will be entered. + + (#) It can be checked if the sleep mode is entered using + HAL_CAN_IsSleepActive(). + Note that the CAN state (accessible from the API HAL_CAN_GetState()) + is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is + submitted (the sleep mode is not yet entered), and become + HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective. + + (#) The wake-up from sleep mode can be triggered by two ways: + (++) Using HAL_CAN_WakeUp(). When returning from this function, + the sleep mode is exited (if return status is HAL_OK). + (++) When a start of Rx CAN frame is detected by the CAN peripheral, + if automatic wake up mode is enabled. + + *** Callback registration *** + ============================================= + + The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. + + Function HAL_CAN_RegisterCallback() allows to register following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. + (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. + (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. + (+) TxMailbox0AbortCallback : Tx Mailbox 0 Abort Callback. + (+) TxMailbox1AbortCallback : Tx Mailbox 1 Abort Callback. + (+) TxMailbox2AbortCallback : Tx Mailbox 2 Abort Callback. + (+) RxFifo0MsgPendingCallback : Rx Fifo 0 Message Pending Callback. + (+) RxFifo0FullCallback : Rx Fifo 0 Full Callback. + (+) RxFifo1MsgPendingCallback : Rx Fifo 1 Message Pending Callback. + (+) RxFifo1FullCallback : Rx Fifo 1 Full Callback. + (+) SleepCallback : Sleep Callback. + (+) WakeUpFromRxMsgCallback : Wake Up From Rx Message Callback. + (+) ErrorCallback : Error Callback. + (+) MspInitCallback : CAN MspInit. + (+) MspDeInitCallback : CAN MspDeInit. + + By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + all callbacks are set to the corresponding weak functions: + example HAL_CAN_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() + or HAL_CAN_Init() function. + + When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +#if defined(CAN1) + +/** @defgroup CAN CAN + * @brief CAN driver modules + * @{ + */ + +#ifdef HAL_CAN_MODULE_ENABLED + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED +#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup CAN_Private_Constants CAN Private Constants + * @{ + */ +#define CAN_TIMEOUT_VALUE 10U +#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CAN_Exported_Functions CAN Exported Functions + * @{ + */ + +/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Init : Initialize and configure the CAN. + (+) HAL_CAN_DeInit : De-initialize the CAN. + (+) HAL_CAN_MspInit : Initialize the CAN MSP. + (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked)); + assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority)); + assert_param(IS_CAN_MODE(hcan->Init.Mode)); + assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth)); + assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1)); + assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2)); + assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Reset callbacks to legacy functions */ + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */ + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */ + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */ + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */ + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */ + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */ + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */ + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */ + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */ + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */ + hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */ + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */ + hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */ + + if (hcan->MspInitCallback == NULL) + { + hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware: CLOCK, NVIC */ + hcan->MspInitCallback(hcan); + } + +#else + if (hcan->State == HAL_CAN_STATE_RESET) + { + /* Init the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspInit(hcan); + } +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Set the time triggered communication mode */ + if (hcan->Init.TimeTriggeredMode == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM); + } + + /* Set the automatic bus-off management */ + if (hcan->Init.AutoBusOff == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM); + } + + /* Set the automatic wake-up mode */ + if (hcan->Init.AutoWakeUp == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM); + } + + /* Set the automatic retransmission */ + if (hcan->Init.AutoRetransmission == ENABLE) + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + else + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_NART); + } + + /* Set the receive FIFO locked mode */ + if (hcan->Init.ReceiveFifoLocked == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM); + } + + /* Set the transmit FIFO priority */ + if (hcan->Init.TransmitFifoPriority == ENABLE) + { + SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + else + { + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP); + } + + /* Set the bit timing register */ + WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode | + hcan->Init.SyncJumpWidth | + hcan->Init.TimeSeg1 | + hcan->Init.TimeSeg2 | + (hcan->Init.Prescaler - 1U))); + + /* Initialize the error code */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Initialize the CAN state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Deinitializes the CAN peripheral registers to their default + * reset values. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan) +{ + /* Check CAN handle */ + if (hcan == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); + + /* Stop the CAN module */ + (void)HAL_CAN_Stop(hcan); + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + if (hcan->MspDeInitCallback == NULL) + { + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: CLOCK, NVIC */ + hcan->MspDeInitCallback(hcan); + +#else + /* DeInit the low level hardware: CLOCK, NVIC */ + HAL_CAN_MspDeInit(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + + /* Reset the CAN peripheral */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET); + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_RESET; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the CAN MSP. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_MspDeInit could be implemented in the user file + */ +} + +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 +/** + * @brief Register a CAN CallBack. + * To be used instead of the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = pCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = pCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = pCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = pCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = pCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = pCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = pCallback; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a CAN CallBack. + * CAN callback is redirected to the weak predefined callback + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for CAN module + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID + * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (hcan->State == HAL_CAN_STATE_READY) + { + switch (CallbackID) + { + case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID : + hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID : + hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID : + hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; + break; + + case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID : + hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID : + hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; + break; + + case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID : + hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; + break; + + case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID : + hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO0_FULL_CB_ID : + hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; + break; + + case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID : + hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; + break; + + case HAL_CAN_RX_FIFO1_FULL_CB_ID : + hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; + break; + + case HAL_CAN_SLEEP_CB_ID : + hcan->SleepCallback = HAL_CAN_SleepCallback; + break; + + case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID : + hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; + break; + + case HAL_CAN_ERROR_CB_ID : + hcan->ErrorCallback = HAL_CAN_ErrorCallback; + break; + + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hcan->State == HAL_CAN_STATE_RESET) + { + switch (CallbackID) + { + case HAL_CAN_MSPINIT_CB_ID : + hcan->MspInitCallback = HAL_CAN_MspInit; + break; + + case HAL_CAN_MSPDEINIT_CB_ID : + hcan->MspDeInitCallback = HAL_CAN_MspDeInit; + break; + + default : + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group2 Configuration functions + * @brief Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters + +@endverbatim + * @{ + */ + +/** + * @brief Configures the CAN reception filter according to the specified + * parameters in the CAN_FilterInitStruct. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that + * contains the filter configuration information. + * @retval None + */ +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) +{ + uint32_t filternbrbitpos; + CAN_TypeDef *can_ip; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the parameters */ + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh)); + assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow)); + assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); + assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); + assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); + assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation)); + +#if defined(CAN3) + /* Check the CAN instance */ + if (hcan->Instance == CAN3) + { + /* CAN3 is single instance with 14 dedicated filters banks */ + can_ip = hcan->Instance; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); + } + else + { + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); + } +#elif defined(CAN2) + /* CAN1 and CAN2 are dual instances with 28 common filters banks */ + /* Select master instance to access the filter banks */ + can_ip = CAN1; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank)); + assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank)); +#else + /* CAN1 is single instance with 14 dedicated filters banks */ + can_ip = hcan->Instance; + + /* Check the parameters */ + assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank)); +#endif /* CAN3 */ + + /* Initialisation mode for the filter */ + SET_BIT(can_ip->FMR, CAN_FMR_FINIT); + +#if defined(CAN3) + /* Check the CAN instance */ + if (can_ip == CAN1) + { + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + } + +#elif defined(CAN2) + /* Select the start filter number of CAN2 slave instance */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB); + SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos); + +#endif /* CAN3 */ + /* Convert filter number into bit position */ + filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU); + + /* Filter Deactivation */ + CLEAR_BIT(can_ip->FA1R, filternbrbitpos); + + /* Filter Scale */ + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) + { + /* 16-bit scale for the filter */ + CLEAR_BIT(can_ip->FS1R, filternbrbitpos); + + /* First 16-bit identifier and First 16-bit mask */ + /* Or First 16-bit identifier and Second 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* Second 16-bit identifier and Second 16-bit mask */ + /* Or Third 16-bit identifier and Fourth 16-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh); + } + + if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) + { + /* 32-bit scale for the filter */ + SET_BIT(can_ip->FS1R, filternbrbitpos); + + /* 32-bit identifier or First 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow); + + /* 32-bit mask or Second 32-bit identifier */ + can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 = + ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) | + (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow); + } + + /* Filter Mode */ + if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) + { + /* Id/Mask mode for the filter*/ + CLEAR_BIT(can_ip->FM1R, filternbrbitpos); + } + else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ + { + /* Identifier list mode for the filter*/ + SET_BIT(can_ip->FM1R, filternbrbitpos); + } + + /* Filter FIFO assignment */ + if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) + { + /* FIFO 0 assignation for the filter */ + CLEAR_BIT(can_ip->FFA1R, filternbrbitpos); + } + else + { + /* FIFO 1 assignation for the filter */ + SET_BIT(can_ip->FFA1R, filternbrbitpos); + } + + /* Filter activation */ + if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE) + { + SET_BIT(can_ip->FA1R, filternbrbitpos); + } + + /* Leave the initialisation mode for the filter */ + CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim + ============================================================================== + ##### Control functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_Start : Start the CAN module + (+) HAL_CAN_Stop : Stop the CAN module + (+) HAL_CAN_RequestSleep : Request sleep mode entry. + (+) HAL_CAN_WakeUp : Wake up from sleep mode. + (+) HAL_CAN_IsSleepActive : Check is sleep mode is active. + (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes + and activate the corresponding + transmission request + (+) HAL_CAN_AbortTxRequest : Abort transmission request + (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level + (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is + pending on the selected Tx mailbox + (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO + (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level + +@endverbatim + * @{ + */ + +/** + * @brief Start the CAN module. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_READY) + { + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_LISTENING; + + /* Request leave initialisation */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Reset the CAN ErrorCode */ + hcan->ErrorCode = HAL_CAN_ERROR_NONE; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY; + + return HAL_ERROR; + } +} + +/** + * @brief Stop the CAN module and enable access to configuration registers. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan) +{ + uint32_t tickstart; + + if (hcan->State == HAL_CAN_STATE_LISTENING) + { + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait the acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + /* Change CAN state */ + hcan->State = HAL_CAN_STATE_ERROR; + + return HAL_ERROR; + } + } + + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Change CAN peripheral state */ + hcan->State = HAL_CAN_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED; + + return HAL_ERROR; + } +} + +/** + * @brief Request the sleep mode (low power) entry. + * When returning from this function, Sleep mode will be entered + * as soon as the current CAN activity (transmission or reception + * of a CAN frame) has been completed. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Request Sleep mode */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Wake up from sleep mode. + * When returning with HAL_OK status from this function, Sleep mode + * is exited. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) +{ + __IO uint32_t count = 0; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Wake up request */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + + /* Wait sleep mode is exited */ + do + { + /* Increment counter */ + count++; + + /* Check if timeout is reached */ + if (count > CAN_WAKEUP_TIMEOUT_COUNTER) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT; + + return HAL_ERROR; + } + } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Check is sleep mode is active. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Status + * - 0 : Sleep mode is not active. + * - 1 : Sleep mode is active. + */ +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Sleep mode */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + status = 1U; + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Add a message to the first free Tx mailbox and activate the + * corresponding transmission request. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param pHeader pointer to a CAN_TxHeaderTypeDef structure. + * @param aData array containing the payload of the Tx frame. + * @param pTxMailbox pointer to a variable where the function will return + * the TxMailbox used to store the Tx message. + * This parameter can be a value of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox) +{ + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + uint32_t tsr = READ_REG(hcan->Instance->TSR); + + /* Check the parameters */ + assert_param(IS_CAN_IDTYPE(pHeader->IDE)); + assert_param(IS_CAN_RTR(pHeader->RTR)); + assert_param(IS_CAN_DLC(pHeader->DLC)); + if (pHeader->IDE == CAN_ID_STD) + { + assert_param(IS_CAN_STDID(pHeader->StdId)); + } + else + { + assert_param(IS_CAN_EXTID(pHeader->ExtId)); + } + assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check that all the Tx mailboxes are not full */ + if (((tsr & CAN_TSR_TME0) != 0U) || + ((tsr & CAN_TSR_TME1) != 0U) || + ((tsr & CAN_TSR_TME2) != 0U)) + { + /* Select an empty transmit mailbox */ + transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos; + + /* Store the Tx mailbox */ + *pTxMailbox = (uint32_t)1 << transmitmailbox; + + /* Set up the Id */ + if (pHeader->IDE == CAN_ID_STD) + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) | + pHeader->RTR); + } + else + { + hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) | + pHeader->IDE | + pHeader->RTR); + } + + /* Set up the DLC */ + hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC); + + /* Set up the Transmit Global Time mode */ + if (pHeader->TransmitGlobalTime == ENABLE) + { + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT); + } + + /* Set up the data field */ + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR, + ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) | + ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) | + ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) | + ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos)); + WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR, + ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) | + ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) | + ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) | + ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos)); + + /* Request transmission */ + SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Abort transmission requests + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of the Tx Mailboxes to abort. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 */ + if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U) + { + /* Add cancellation request for Tx Mailbox 0 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0); + } + + /* Check Tx Mailbox 1 */ + if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U) + { + /* Add cancellation request for Tx Mailbox 1 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1); + } + + /* Check Tx Mailbox 2 */ + if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U) + { + /* Add cancellation request for Tx Mailbox 2 */ + SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval Number of free Tx Mailboxes. + */ +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) +{ + uint32_t freelevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check Tx Mailbox 0 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 1 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U) + { + freelevel++; + } + + /* Check Tx Mailbox 2 status */ + if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U) + { + freelevel++; + } + } + + /* Return Tx Mailboxes free level */ + return freelevel; +} + +/** + * @brief Check if a transmission request is pending on the selected Tx + * Mailboxes. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailboxes List of Tx Mailboxes to check. + * This parameter can be any combination of @arg CAN_Tx_Mailboxes. + * @retval Status + * - 0 : No pending transmission request on any selected Tx Mailboxes. + * - 1 : Pending transmission request on at least one of the selected + * Tx Mailbox. + */ +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +{ + uint32_t status = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check pending transmission request on the selected Tx Mailboxes */ + if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos)) + { + status = 1U; + } + } + + /* Return status */ + return status; +} + +/** + * @brief Return timestamp of Tx message sent, if time triggered communication + mode is enabled. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param TxMailbox Tx Mailbox where the timestamp of message sent will be + * read. + * This parameter can be one value of @arg CAN_Tx_Mailboxes. + * @retval Timestamp of message sent from Tx Mailbox. + */ +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +{ + uint32_t timestamp = 0U; + uint32_t transmitmailbox; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_TX_MAILBOX(TxMailbox)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Select the Tx mailbox */ + transmitmailbox = POSITION_VAL(TxMailbox); + + /* Get timestamp */ + timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos; + } + + /* Return the timestamp */ + return timestamp; +} + +/** + * @brief Get an CAN frame from the Rx FIFO zone into the message RAM. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Fifo number of the received message to be read. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header + * of the Rx frame will be stored. + * @param aData array where the payload of the Rx frame will be stored. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check the Rx FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Check that the Rx FIFO 0 is not empty */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Check that the Rx FIFO 1 is not empty */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U) + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_PARAM; + + return HAL_ERROR; + } + } + + /* Get the header */ + pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR; + if (pHeader->IDE == CAN_ID_STD) + { + pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos; + } + else + { + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + } + pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); + if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U) + { + /* Truncate DLC to 8 if received field is over range */ + pHeader->DLC = 8U; + } + else + { + pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; + } + pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos; + pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos; + + /* Get the data */ + aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos); + aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos); + aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos); + aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos); + aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos); + aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos); + aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos); + aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos); + + /* Release the FIFO */ + if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */ + { + /* Release RX FIFO 0 */ + SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0); + } + else /* Rx element is assigned to Rx FIFO 1 */ + { + /* Release RX FIFO 1 */ + SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1); + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Return Rx FIFO fill level. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param RxFifo Rx FIFO. + * This parameter can be a value of @arg CAN_receive_FIFO_number. + * @retval Number of messages available in Rx FIFO. + */ +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) +{ + uint32_t filllevel = 0U; + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_RX_FIFO(RxFifo)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + if (RxFifo == CAN_RX_FIFO0) + { + filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0; + } + else /* RxFifo == CAN_RX_FIFO1 */ + { + filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1; + } + } + + /* Return Rx FIFO fill level */ + return filllevel; +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) HAL_CAN_ActivateNotification : Enable interrupts + (+) HAL_CAN_DeactivateNotification : Disable interrupts + (+) HAL_CAN_IRQHandler : Handles CAN interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(ActiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Enable the selected interrupts */ + __HAL_CAN_ENABLE_IT(hcan, ActiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Disable interrupts. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg CAN_Interrupts. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + /* Check function parameters */ + assert_param(IS_CAN_IT(InactiveITs)); + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Disable the selected interrupts */ + __HAL_CAN_DISABLE_IT(hcan, InactiveITs); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + return HAL_ERROR; + } +} + +/** + * @brief Handles CAN interrupt request + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan) +{ + uint32_t errorcode = HAL_CAN_ERROR_NONE; + uint32_t interrupts = READ_REG(hcan->Instance->IER); + uint32_t msrflags = READ_REG(hcan->Instance->MSR); + uint32_t tsrflags = READ_REG(hcan->Instance->TSR); + uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R); + uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R); + uint32_t esrflags = READ_REG(hcan->Instance->ESR); + + /* Transmit Mailbox empty interrupt management *****************************/ + if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U) + { + /* Transmit Mailbox 0 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP0) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0); + + if ((tsrflags & CAN_TSR_TXOK0) != 0U) + { + /* Transmission Mailbox 0 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST0; + } + else if ((tsrflags & CAN_TSR_TERR0) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR0; + } + else + { + /* Transmission Mailbox 0 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox0AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox0AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 1 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP1) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1); + + if ((tsrflags & CAN_TSR_TXOK1) != 0U) + { + /* Transmission Mailbox 1 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST1; + } + else if ((tsrflags & CAN_TSR_TERR1) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR1; + } + else + { + /* Transmission Mailbox 1 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox1AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox1AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + + /* Transmit Mailbox 2 management *****************************************/ + if ((tsrflags & CAN_TSR_RQCP2) != 0U) + { + /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2); + + if ((tsrflags & CAN_TSR_TXOK2) != 0U) + { + /* Transmission Mailbox 2 complete callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2CompleteCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2CompleteCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + else + { + if ((tsrflags & CAN_TSR_ALST2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_ALST2; + } + else if ((tsrflags & CAN_TSR_TERR2) != 0U) + { + /* Update error code */ + errorcode |= HAL_CAN_ERROR_TX_TERR2; + } + else + { + /* Transmission Mailbox 2 abort callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->TxMailbox2AbortCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_TxMailbox2AbortCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + } + } + + /* Receive FIFO 0 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U) + { + if ((rf0rflags & CAN_RF0R_FOVR0) != 0U) + { + /* Set CAN error code to Rx Fifo 0 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV0; + + /* Clear FIFO0 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0); + } + } + + /* Receive FIFO 0 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U) + { + if ((rf0rflags & CAN_RF0R_FULL0) != 0U) + { + /* Clear FIFO 0 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0); + + /* Receive FIFO 0 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 0 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U) + { + /* Receive FIFO 0 message pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo0MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo0MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 overrun interrupt management *****************************/ + if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U) + { + if ((rf1rflags & CAN_RF1R_FOVR1) != 0U) + { + /* Set CAN error code to Rx Fifo 1 overrun error */ + errorcode |= HAL_CAN_ERROR_RX_FOV1; + + /* Clear FIFO1 Overrun Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1); + } + } + + /* Receive FIFO 1 full interrupt management ********************************/ + if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U) + { + if ((rf1rflags & CAN_RF1R_FULL1) != 0U) + { + /* Clear FIFO 1 full Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1); + + /* Receive FIFO 1 full Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1FullCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1FullCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Receive FIFO 1 message pending interrupt management *********************/ + if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U) + { + /* Check if message is still pending */ + if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U) + { + /* Receive FIFO 1 message pending Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->RxFifo1MsgPendingCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_RxFifo1MsgPendingCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Sleep interrupt management *********************************************/ + if ((interrupts & CAN_IT_SLEEP_ACK) != 0U) + { + if ((msrflags & CAN_MSR_SLAKI) != 0U) + { + /* Clear Sleep interrupt Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI); + + /* Sleep Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->SleepCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_SleepCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* WakeUp interrupt management *********************************************/ + if ((interrupts & CAN_IT_WAKEUP) != 0U) + { + if ((msrflags & CAN_MSR_WKUI) != 0U) + { + /* Clear WakeUp Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU); + + /* WakeUp Callback */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->WakeUpFromRxMsgCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_WakeUpFromRxMsgCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } + } + + /* Error interrupts management *********************************************/ + if ((interrupts & CAN_IT_ERROR) != 0U) + { + if ((msrflags & CAN_MSR_ERRI) != 0U) + { + /* Check Error Warning Flag */ + if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) && + ((esrflags & CAN_ESR_EWGF) != 0U)) + { + /* Set CAN error code to Error Warning */ + errorcode |= HAL_CAN_ERROR_EWG; + + /* No need for clear of Error Warning Flag as read-only */ + } + + /* Check Error Passive Flag */ + if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) && + ((esrflags & CAN_ESR_EPVF) != 0U)) + { + /* Set CAN error code to Error Passive */ + errorcode |= HAL_CAN_ERROR_EPV; + + /* No need for clear of Error Passive Flag as read-only */ + } + + /* Check Bus-off Flag */ + if (((interrupts & CAN_IT_BUSOFF) != 0U) && + ((esrflags & CAN_ESR_BOFF) != 0U)) + { + /* Set CAN error code to Bus-Off */ + errorcode |= HAL_CAN_ERROR_BOF; + + /* No need for clear of Error Bus-Off as read-only */ + } + + /* Check Last Error Code Flag */ + if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) && + ((esrflags & CAN_ESR_LEC) != 0U)) + { + switch (esrflags & CAN_ESR_LEC) + { + case (CAN_ESR_LEC_0): + /* Set CAN error code to Stuff error */ + errorcode |= HAL_CAN_ERROR_STF; + break; + case (CAN_ESR_LEC_1): + /* Set CAN error code to Form error */ + errorcode |= HAL_CAN_ERROR_FOR; + break; + case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0): + /* Set CAN error code to Acknowledgement error */ + errorcode |= HAL_CAN_ERROR_ACK; + break; + case (CAN_ESR_LEC_2): + /* Set CAN error code to Bit recessive error */ + errorcode |= HAL_CAN_ERROR_BR; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0): + /* Set CAN error code to Bit Dominant error */ + errorcode |= HAL_CAN_ERROR_BD; + break; + case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1): + /* Set CAN error code to CRC error */ + errorcode |= HAL_CAN_ERROR_CRC; + break; + default: + break; + } + + /* Clear Last error code Flag */ + CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC); + } + } + + /* Clear ERRI Flag */ + __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI); + } + + /* Call the Error call Back in case of Errors */ + if (errorcode != HAL_CAN_ERROR_NONE) + { + /* Update error code in handle */ + hcan->ErrorCode |= errorcode; + + /* Call Error callback function */ +#if USE_HAL_CAN_REGISTER_CALLBACKS == 1 + /* Call registered callback*/ + hcan->ErrorCallback(hcan); +#else + /* Call weak (surcharged) callback */ + HAL_CAN_ErrorCallback(hcan); +#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */ + } +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group5 Callback functions + * @brief CAN Callback functions + * +@verbatim + ============================================================================== + ##### Callback functions ##### + ============================================================================== + [..] + This subsection provides the following callback functions: + (+) HAL_CAN_TxMailbox0CompleteCallback + (+) HAL_CAN_TxMailbox1CompleteCallback + (+) HAL_CAN_TxMailbox2CompleteCallback + (+) HAL_CAN_TxMailbox0AbortCallback + (+) HAL_CAN_TxMailbox1AbortCallback + (+) HAL_CAN_TxMailbox2AbortCallback + (+) HAL_CAN_RxFifo0MsgPendingCallback + (+) HAL_CAN_RxFifo0FullCallback + (+) HAL_CAN_RxFifo1MsgPendingCallback + (+) HAL_CAN_RxFifo1FullCallback + (+) HAL_CAN_SleepCallback + (+) HAL_CAN_WakeUpFromRxMsgCallback + (+) HAL_CAN_ErrorCallback + +@endverbatim + * @{ + */ + +/** + * @brief Transmission Mailbox 0 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 complete callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 0 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox0AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 1 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox1AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Transmission Mailbox 2 Cancellation callback. + * @param hcan pointer to an CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_TxMailbox2AbortCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 0 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo0FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Rx FIFO 1 message pending callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the + user file + */ +} + +/** + * @brief Rx FIFO 1 full callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_RxFifo1FullCallback could be implemented in the user + file + */ +} + +/** + * @brief Sleep callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_SleepCallback could be implemented in the user file + */ +} + +/** + * @brief WakeUp from Rx message callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the + user file + */ +} + +/** + * @brief Error CAN callback. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval None + */ +__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hcan); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_CAN_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions + * @brief CAN Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) HAL_CAN_GetState() : Return the CAN state. + (+) HAL_CAN_GetError() : Return the CAN error codes if any. + (+) HAL_CAN_ResetError(): Reset the CAN error codes if any. + +@endverbatim + * @{ + */ + +/** + * @brief Return the CAN state. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL state + */ +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) +{ + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Check sleep mode acknowledge flag */ + if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + { + /* Sleep mode is active */ + state = HAL_CAN_STATE_SLEEP_ACTIVE; + } + /* Check sleep mode request flag */ + else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U) + { + /* Sleep mode request is pending */ + state = HAL_CAN_STATE_SLEEP_PENDING; + } + else + { + /* Neither sleep mode request nor sleep mode acknowledge */ + } + } + + /* Return CAN state */ + return state; +} + +/** + * @brief Return the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval CAN Error Code + */ +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) +{ + /* Return CAN error code */ + return hcan->ErrorCode; +} + +/** + * @brief Reset the CAN error code. + * @param hcan pointer to a CAN_HandleTypeDef structure that contains + * the configuration information for the specified CAN. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) +{ + HAL_StatusTypeDef status = HAL_OK; + HAL_CAN_StateTypeDef state = hcan->State; + + if ((state == HAL_CAN_STATE_READY) || + (state == HAL_CAN_STATE_LISTENING)) + { + /* Reset CAN error code */ + hcan->ErrorCode = 0U; + } + else + { + /* Update error code */ + hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED; + + status = HAL_ERROR; + } + + /* Return the status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CAN_MODULE_ENABLED */ + +/** + * @} + */ + +#endif /* CAN1 */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c deleted file mode 100644 index 2f085660..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cec.c +++ /dev/null @@ -1,997 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cec.c - * @author MCD Application Team - * @brief CEC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the High Definition Multimedia Interface - * Consumer Electronics Control Peripheral (CEC). - * + Initialization and de-initialization function - * + IO operation function - * + Peripheral Control function - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The CEC HAL driver can be used as follow: - - (#) Declare a CEC_HandleTypeDef handle structure. - (#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API: - (##) Enable the CEC interface clock. - (##) CEC pins configuration: - (+++) Enable the clock for the CEC GPIOs. - (+++) Configure these CEC pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT() - and HAL_CEC_Receive_IT() APIs): - (+++) Configure the CEC interrupt priority. - (+++) Enable the NVIC CEC IRQ handle. - (+++) The specific CEC interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit - and receive process. - - (#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in - in case of Bit Rising Error, Error-Bit generation conditions, device logical - address and Listen mode in the hcec Init structure. - - (#) Initialize the CEC registers by calling the HAL_CEC_Init() API. - - [..] - (@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_CEC_MspInit() API. - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback() - to register an interrupt callback. - - Function HAL_CEC_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : Tx Transfer completed callback. - (+) ErrorCallback : callback for error detection. - (+) MspInitCallback : CEC MspInit. - (+) MspDeInitCallback : CEC MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks - HAL_CEC_RegisterRxCpltCallback(). - - Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxCpltCallback : Tx Transfer completed callback. - (+) ErrorCallback : callback for error detection. - (+) MspInitCallback : CEC MspInit. - (+) MspDeInitCallback : CEC MspDeInit. - - For callback HAL_CEC_RxCpltCallback use dedicated unregister callback : - HAL_CEC_UnRegisterRxCpltCallback(). - - By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET - all callbacks are set to the corresponding weak functions : - examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit() - keep and use the user MspInit/MspDeInit functions (registered beforehand) - - Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only. - Exception done MspInit/MspDeInit callbacks that can be registered/unregistered - in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit() - or HAL_CEC_Init() function. - - When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup CEC CEC - * @brief HAL CEC module driver - * @{ - */ -#ifdef HAL_CEC_MODULE_ENABLED -#if defined (CEC) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup CEC_Private_Constants CEC Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup CEC_Private_Functions CEC Private Functions - * @{ - */ -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup CEC_Exported_Functions CEC Exported Functions - * @{ - */ - -/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the CEC - (+) The following parameters need to be configured: - (++) SignalFreeTime - (++) Tolerance - (++) BRERxStop (RX stopped or not upon Bit Rising Error) - (++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error) - (++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error) - (++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error) - (++) SignalFreeTimeOption (SFT Timer start definition) - (++) OwnAddress (CEC device address) - (++) ListenMode - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the CEC mode according to the specified - * parameters in the CEC_InitTypeDef and creates the associated handle . - * @param hcec CEC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) -{ - /* Check the CEC handle allocation */ - if ((hcec == NULL) || (hcec->Init.RxBuffer == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); - assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime)); - assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); - assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop)); - assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen)); - assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen)); - assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen)); - assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption)); - assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode)); - assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress)); - -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) - if (hcec->gState == HAL_CEC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcec->Lock = HAL_UNLOCKED; - - hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hcec->MspInitCallback == NULL) - { - hcec->MspInitCallback = HAL_CEC_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hcec->MspInitCallback(hcec); - } -#else - if (hcec->gState == HAL_CEC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcec->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK */ - HAL_CEC_MspInit(hcec); - } -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ - - hcec->gState = HAL_CEC_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_CEC_DISABLE(hcec); - - /* Write to CEC Control Register */ - hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop | \ - hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | \ - hcec->Init.BroadcastMsgNoErrorBitGen | \ - hcec->Init.SignalFreeTimeOption | ((uint32_t)(hcec->Init.OwnAddress) << 16U) | \ - hcec->Init.ListenMode; - - /* Enable the following CEC Transmission/Reception interrupts as - * well as the following CEC Transmission/Reception Errors interrupts - * Rx Byte Received IT - * End of Reception IT - * Rx overrun - * Rx bit rising error - * Rx short bit period error - * Rx long bit period error - * Rx missing acknowledge - * Tx Byte Request IT - * End of Transmission IT - * Tx Missing Acknowledge IT - * Tx-Error IT - * Tx-Buffer Underrun IT - * Tx arbitration lost */ - __HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND | - CEC_IER_TX_ALL_ERR); - - /* Enable the CEC Peripheral */ - __HAL_CEC_ENABLE(hcec); - - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->gState = HAL_CEC_STATE_READY; - hcec->RxState = HAL_CEC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the CEC peripheral - * @param hcec CEC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) -{ - /* Check the CEC handle allocation */ - if (hcec == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); - - hcec->gState = HAL_CEC_STATE_BUSY; - -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) - if (hcec->MspDeInitCallback == NULL) - { - hcec->MspDeInitCallback = HAL_CEC_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hcec->MspDeInitCallback(hcec); - -#else - /* DeInit the low level hardware */ - HAL_CEC_MspDeInit(hcec); -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ - - /* Disable the Peripheral */ - __HAL_CEC_DISABLE(hcec); - - /* Clear Flags */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND | CEC_FLAG_TXBR | CEC_FLAG_RXBR | CEC_FLAG_RXEND | CEC_ISR_ALL_ERROR); - - /* Disable the following CEC Transmission/Reception interrupts as - * well as the following CEC Transmission/Reception Errors interrupts - * Rx Byte Received IT - * End of Reception IT - * Rx overrun - * Rx bit rising error - * Rx short bit period error - * Rx long bit period error - * Rx missing acknowledge - * Tx Byte Request IT - * End of Transmission IT - * Tx Missing Acknowledge IT - * Tx-Error IT - * Tx-Buffer Underrun IT - * Tx arbitration lost */ - __HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR | CEC_IT_RXEND | CEC_IER_RX_ALL_ERR | CEC_IT_TXBR | CEC_IT_TXEND | - CEC_IER_TX_ALL_ERR); - - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->gState = HAL_CEC_STATE_RESET; - hcec->RxState = HAL_CEC_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(hcec); - - return HAL_OK; -} - -/** - * @brief Initializes the Own Address of the CEC device - * @param hcec CEC handle - * @param CEC_OwnAddress The CEC own address. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) -{ - /* Check the parameters */ - assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress)); - - if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY)) - { - /* Process Locked */ - __HAL_LOCK(hcec); - - hcec->gState = HAL_CEC_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_CEC_DISABLE(hcec); - - if (CEC_OwnAddress != CEC_OWN_ADDRESS_NONE) - { - hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress << 16); - } - else - { - hcec->Instance->CFGR &= ~(CEC_CFGR_OAR); - } - - hcec->gState = HAL_CEC_STATE_READY; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - /* Enable the Peripheral */ - __HAL_CEC_ENABLE(hcec); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief CEC MSP Init - * @param hcec CEC handle - * @retval None - */ -__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_MspInit can be implemented in the user file - */ -} - -/** - * @brief CEC MSP DeInit - * @param hcec CEC handle - * @retval None - */ -__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_MspDeInit can be implemented in the user file - */ -} -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User CEC Callback - * To be used instead of the weak predefined callback - * @param hcec CEC handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID - * @arg HAL_CEC_ERROR_CB_ID Error callback ID - * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID - * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, - pCEC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hcec); - - if (hcec->gState == HAL_CEC_STATE_READY) - { - switch (CallbackID) - { - case HAL_CEC_TX_CPLT_CB_ID : - hcec->TxCpltCallback = pCallback; - break; - - case HAL_CEC_ERROR_CB_ID : - hcec->ErrorCallback = pCallback; - break; - - case HAL_CEC_MSPINIT_CB_ID : - hcec->MspInitCallback = pCallback; - break; - - case HAL_CEC_MSPDEINIT_CB_ID : - hcec->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcec->gState == HAL_CEC_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CEC_MSPINIT_CB_ID : - hcec->MspInitCallback = pCallback; - break; - - case HAL_CEC_MSPDEINIT_CB_ID : - hcec->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hcec); - - return status; -} - -/** - * @brief Unregister an CEC Callback - * CEC callback is redirected to the weak predefined callback - * @param hcec uart handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg HAL_CEC_TX_CPLT_CB_ID Tx Complete callback ID - * @arg HAL_CEC_ERROR_CB_ID Error callback ID - * @arg HAL_CEC_MSPINIT_CB_ID MspInit callback ID - * @arg HAL_CEC_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hcec); - - if (hcec->gState == HAL_CEC_STATE_READY) - { - switch (CallbackID) - { - case HAL_CEC_TX_CPLT_CB_ID : - hcec->TxCpltCallback = HAL_CEC_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_CEC_ERROR_CB_ID : - hcec->ErrorCallback = HAL_CEC_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_CEC_MSPINIT_CB_ID : - hcec->MspInitCallback = HAL_CEC_MspInit; - break; - - case HAL_CEC_MSPDEINIT_CB_ID : - hcec->MspDeInitCallback = HAL_CEC_MspDeInit; - break; - - default : - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcec->gState == HAL_CEC_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CEC_MSPINIT_CB_ID : - hcec->MspInitCallback = HAL_CEC_MspInit; - break; - - case HAL_CEC_MSPDEINIT_CB_ID : - hcec->MspDeInitCallback = HAL_CEC_MspDeInit; - break; - - default : - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hcec); - - return status; -} - -/** - * @brief Register CEC RX complete Callback - * To be used instead of the weak HAL_CEC_RxCpltCallback() predefined callback - * @param hcec CEC handle - * @param pCallback pointer to the Rx transfer compelete Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hcec); - - if (HAL_CEC_STATE_READY == hcec->RxState) - { - hcec->RxCpltCallback = pCallback; - } - else - { - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hcec); - return status; -} - -/** - * @brief UnRegister CEC RX complete Callback - * CEC RX complete Callback is redirected to the weak HAL_CEC_RxCpltCallback() predefined callback - * @param hcec CEC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hcec); - - if (HAL_CEC_STATE_READY == hcec->RxState) - { - hcec->RxCpltCallback = HAL_CEC_RxCpltCallback; /* Legacy weak CEC RxCpltCallback */ - } - else - { - /* Update the error code */ - hcec->ErrorCode |= HAL_CEC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hcec); - return status; -} -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions - * @brief CEC Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the CEC data transfers. - - (#) The CEC handle must contain the initiator (TX side) and the destination (RX side) - logical addresses (4-bit long addresses, 0xF for broadcast messages destination) - - (#) The communication is performed using Interrupts. - These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated CEC IRQ when using Interrupt mode. - The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_CEC_ErrorCallback() user callback will be executed when a communication - error is detected - - (#) API's with Interrupt are : - (+) HAL_CEC_Transmit_IT() - (+) HAL_CEC_IRQHandler() - - (#) A set of User Callbacks are provided: - (+) HAL_CEC_TxCpltCallback() - (+) HAL_CEC_RxCpltCallback() - (+) HAL_CEC_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Send data in interrupt mode - * @param hcec CEC handle - * @param InitiatorAddress Initiator address - * @param DestinationAddress destination logical address - * @param pData pointer to input byte data buffer - * @param Size amount of data to be sent in bytes (without counting the header). - * 0 means only the header is sent (ping operation). - * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - const uint8_t *pData, uint32_t Size) -{ - /* if the peripheral isn't already busy and if there is no previous transmission - already pending due to arbitration lost */ - if (hcec->gState == HAL_CEC_STATE_READY) - { - if ((pData == NULL) && (Size > 0U)) - { - return HAL_ERROR; - } - - assert_param(IS_CEC_ADDRESS(DestinationAddress)); - assert_param(IS_CEC_ADDRESS(InitiatorAddress)); - assert_param(IS_CEC_MSGSIZE(Size)); - - /* Process Locked */ - __HAL_LOCK(hcec); - hcec->pTxBuffPtr = pData; - hcec->gState = HAL_CEC_STATE_BUSY_TX; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - - /* initialize the number of bytes to send, - * 0 means only one header is sent (ping operation) */ - hcec->TxXferCount = (uint16_t)Size; - - /* in case of no payload (Size = 0), sender is only pinging the system; - Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */ - if (Size == 0U) - { - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - - /* send header block */ - hcec->Instance->TXDR = (uint32_t)(((uint32_t)InitiatorAddress << CEC_INITIATOR_LSB_POS) | DestinationAddress); - - /* Set TX Start of Message (TXSOM) bit */ - __HAL_CEC_FIRST_BYTE_TX_SET(hcec); - - /* Process Unlocked */ - __HAL_UNLOCK(hcec); - - return HAL_OK; - - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Get size of the received frame. - * @param hcec CEC handle - * @retval Frame size - */ -uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec) -{ - return hcec->RxXferSize; -} - -/** - * @brief Change Rx Buffer. - * @param hcec CEC handle - * @param Rxbuffer Rx Buffer - * @note This function can be called only inside the HAL_CEC_RxCpltCallback() - * @retval Frame size - */ -void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer) -{ - hcec->Init.RxBuffer = Rxbuffer; -} - -/** - * @brief This function handles CEC interrupt requests. - * @param hcec CEC handle - * @retval None - */ -void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) -{ - - /* save interrupts register for further error or interrupts handling purposes */ - uint32_t itflag; - itflag = hcec->Instance->ISR; - - - /* ----------------------------Arbitration Lost Management----------------------------------*/ - /* CEC TX arbitration error interrupt occurred --------------------------------------*/ - if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST)) - { - hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); - } - - /* ----------------------------Rx Management----------------------------------*/ - /* CEC RX byte received interrupt ---------------------------------------------------*/ - if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR)) - { - /* reception is starting */ - hcec->RxState = HAL_CEC_STATE_BUSY_RX; - hcec->RxXferSize++; - /* read received byte */ - *hcec->Init.RxBuffer = (uint8_t) hcec->Instance->RXDR; - hcec->Init.RxBuffer++; - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR); - } - - /* CEC RX end received interrupt ---------------------------------------------------*/ - if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND)) - { - /* clear IT */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); - - /* Rx process is completed, restore hcec->RxState to Ready */ - hcec->RxState = HAL_CEC_STATE_READY; - hcec->ErrorCode = HAL_CEC_ERROR_NONE; - hcec->Init.RxBuffer -= hcec->RxXferSize; -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) - hcec->RxCpltCallback(hcec, hcec->RxXferSize); -#else - HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize); -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ - hcec->RxXferSize = 0U; - } - - /* ----------------------------Tx Management----------------------------------*/ - /* CEC TX byte request interrupt ------------------------------------------------*/ - if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR)) - { - --hcec->TxXferCount; - if (hcec->TxXferCount == 0U) - { - /* if this is the last byte transmission, set TX End of Message (TXEOM) bit */ - __HAL_CEC_LAST_BYTE_TX_SET(hcec); - } - /* In all cases transmit the byte */ - hcec->Instance->TXDR = (uint8_t) * hcec->pTxBuffPtr; - hcec->pTxBuffPtr++; - /* clear Tx-Byte request flag */ - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); - } - - /* CEC TX end interrupt ------------------------------------------------*/ - if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND)) - { - __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); - - /* Tx process is ended, restore hcec->gState to Ready */ - hcec->gState = HAL_CEC_STATE_READY; - /* Call the Process Unlocked before calling the Tx call back API to give the possibility to - start again the Transmission under the Tx call back API */ - __HAL_UNLOCK(hcec); - hcec->ErrorCode = HAL_CEC_ERROR_NONE; -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) - hcec->TxCpltCallback(hcec); -#else - HAL_CEC_TxCpltCallback(hcec); -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ - } - - /* ----------------------------Rx/Tx Error Management----------------------------------*/ - if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | - CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) - { - hcec->ErrorCode = itflag; - __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | - HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE); - - - if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) - { - hcec->Init.RxBuffer -= hcec->RxXferSize; - hcec->RxXferSize = 0U; - hcec->RxState = HAL_CEC_STATE_READY; - } - else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) - { - /* Set the CEC state ready to be able to start again the process */ - hcec->gState = HAL_CEC_STATE_READY; - } - else - { - /* Nothing todo*/ - } -#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1U) - hcec->ErrorCallback(hcec); -#else - /* Error Call Back */ - HAL_CEC_ErrorCallback(hcec); -#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ - } - else - { - /* Nothing todo*/ - } -} - -/** - * @brief Tx Transfer completed callback - * @param hcec CEC handle - * @retval None - */ -__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback - * @param hcec CEC handle - * @param RxFrameSize Size of frame - * @retval None - */ -__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - UNUSED(RxFrameSize); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief CEC error callbacks - * @param hcec CEC handle - * @retval None - */ -__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcec); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CEC_ErrorCallback can be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function - * @brief CEC control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control function ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the CEC. - (+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral. - (+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral. -@endverbatim - * @{ - */ -/** - * @brief return the CEC state - * @param hcec pointer to a CEC_HandleTypeDef structure that contains - * the configuration information for the specified CEC module. - * @retval HAL state - */ -HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec) -{ - uint32_t temp1; - uint32_t temp2; - temp1 = hcec->gState; - temp2 = hcec->RxState; - - return (HAL_CEC_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the CEC error code - * @param hcec pointer to a CEC_HandleTypeDef structure that contains - * the configuration information for the specified CEC. - * @retval CEC Error Code - */ -uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec) -{ - return hcec->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* CEC */ -#endif /* HAL_CEC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c index d89d8656..03b89f61 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c @@ -1,529 +1,529 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M4 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() - function according to the following table. - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). - (#) please refer to programming manual for details in how to configure priority. - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest preemption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure Systick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32f7xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @brief CORTEX HAL module driver - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - Systick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Sets the priority grouping field (preemption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority - * 0 bits for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Sets the priority of an interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @param PreemptPriority The preemption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup = 0x00; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enables a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disables a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiates a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - return SysTick_Config(TicksNumb); -} -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - -@endverbatim - * @{ - */ - -#if (__MPU_PRESENT == 1) -/** - * @brief Disables the MPU - * @retval None - */ -void HAL_MPU_Disable(void) -{ - /* Make sure outstanding transfers are done */ - __DMB(); - - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU and clear the control register*/ - MPU->CTRL = 0; -} - -/** - * @brief Enables the MPU - * @param MPU_Control Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -void HAL_MPU_Enable(uint32_t MPU_Control) -{ - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - - /* Ensure MPU setting take effects */ - __DSB(); - __ISB(); -} - -/** - * @brief Enables the MPU Region. - * @retval None - */ -void HAL_MPU_EnableRegion(uint32_t RegionNumber) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); - - /* Set the Region number */ - MPU->RNR = RegionNumber; - - /* Enable the Region */ - SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); -} - -/** - * @brief Disables the MPU Region. - * @retval None - */ -void HAL_MPU_DisableRegion(uint32_t RegionNumber) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); - - /* Set the Region number */ - MPU->RNR = RegionNumber; - - /* Disable the Region */ - CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); -} - -/** - * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); - assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); - assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); - assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); - assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); - assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); - assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); - assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); - assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); - - /* Set the Region number */ - MPU->RNR = MPU_Init->Number; - - /* Disable the Region */ - CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); - - /* Apply configuration */ - MPU->RBAR = MPU_Init->BaseAddress; - MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | - ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | - ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | - ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | - ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | - ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | - ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | - ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | - ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); -} -#endif /* __MPU_PRESENT */ - -/** - * @brief Gets the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Gets the priority of an interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @param PriorityGroup the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority - * 1 bits for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority - * 0 bits for subpriority - * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Sets Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Gets Pending Interrupt (reads the pending register in the NVIC - * and returns the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clears the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configures the SysTick clock source. - * @param CLKSource specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - if (CLKSource == SYSTICK_CLKSOURCE_HCLK) - { - SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; - } - else - { - SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; - } -} - -/** - * @brief This function handles SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_cortex.c + * @author MCD Application Team + * @brief CORTEX HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the CORTEX: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + *** How to configure Interrupts using CORTEX HAL driver *** + =========================================================== + [..] + This section provides functions allowing to configure the NVIC interrupts (IRQ). + The Cortex-M4 exceptions are managed by CMSIS functions. + + (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() + function according to the following table. + (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). + (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). + (#) please refer to programming manual for details in how to configure priority. + + -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. + The pending IRQ priority will be managed only by the sub priority. + + -@- IRQ priority order (sorted by highest to lowest priority): + (+@) Lowest preemption priority + (+@) Lowest sub priority + (+@) Lowest hardware priority (IRQ number) + + [..] + *** How to configure Systick using CORTEX HAL driver *** + ======================================================== + [..] + Setup SysTick Timer for time base. + + (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which + is a CMSIS function that: + (++) Configures the SysTick Reload register with value passed as function parameter. + (++) Configures the SysTick IRQ priority to the lowest value (0x0F). + (++) Resets the SysTick Counter register. + (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). + (++) Enables the SysTick Interrupt. + (++) Starts the SysTick Counter. + + (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro + __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the + HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined + inside the stm32f7xx_hal_cortex.h file. + + (+) You can change the SysTick IRQ priority by calling the + HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function + call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. + + (+) To adjust the SysTick time base, use the following formula: + + Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) + (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function + (++) Reload Value should not exceed 0xFFFFFF + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup CORTEX CORTEX + * @brief CORTEX HAL module driver + * @{ + */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides the CORTEX HAL driver functions allowing to configure Interrupts + Systick functionalities + +@endverbatim + * @{ + */ + + +/** + * @brief Sets the priority grouping field (preemption priority and subpriority) + * using the required unlock sequence. + * @param PriorityGroup The priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); +} + +/** + * @brief Sets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @param PreemptPriority The preemption priority for the IRQn channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority + * @param SubPriority the subpriority level for the IRQ channel. + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t prioritygroup = 0x00; + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); +} + +/** + * @brief Enables a device specific interrupt in the NVIC interrupt controller. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); +} + +/** + * @brief Disables a device specific interrupt in the NVIC interrupt controller. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); +} + +/** + * @brief Initiates a system reset request to reset the MCU. + * @retval None + */ +void HAL_NVIC_SystemReset(void) +{ + /* System Reset */ + NVIC_SystemReset(); +} + +/** + * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. + * Counter is in free running mode to generate periodic interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + return SysTick_Config(TicksNumb); +} +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the CORTEX + (NVIC, SYSTICK, MPU) functionalities. + + +@endverbatim + * @{ + */ + +#if (__MPU_PRESENT == 1) +/** + * @brief Disables the MPU + * @retval None + */ +void HAL_MPU_Disable(void) +{ + /* Make sure outstanding transfers are done */ + __DMB(); + + /* Disable fault exceptions */ + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; + + /* Disable the MPU and clear the control register*/ + MPU->CTRL = 0; +} + +/** + * @brief Enables the MPU + * @param MPU_Control Specifies the control mode of the MPU during hard fault, + * NMI, FAULTMASK and privileged access to the default memory + * This parameter can be one of the following values: + * @arg MPU_HFNMI_PRIVDEF_NONE + * @arg MPU_HARDFAULT_NMI + * @arg MPU_PRIVILEGED_DEFAULT + * @arg MPU_HFNMI_PRIVDEF + * @retval None + */ +void HAL_MPU_Enable(uint32_t MPU_Control) +{ + /* Enable the MPU */ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; + + /* Enable fault exceptions */ + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; + + /* Ensure MPU setting take effects */ + __DSB(); + __ISB(); +} + +/** + * @brief Enables the MPU Region. + * @retval None + */ +void HAL_MPU_EnableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Enable the Region */ + SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Disables the MPU Region. + * @retval None + */ +void HAL_MPU_DisableRegion(uint32_t RegionNumber) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); + + /* Set the Region number */ + MPU->RNR = RegionNumber; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); +} + +/** + * @brief Initializes and configures the Region and the memory to be protected. + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains + * the initialization and configuration information. + * @retval None + */ +void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) +{ + /* Check the parameters */ + assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); + assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); + assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); + assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); + assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); + assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); + assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); + assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); + assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); + assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); + + /* Set the Region number */ + MPU->RNR = MPU_Init->Number; + + /* Disable the Region */ + CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); + + /* Apply configuration */ + MPU->RBAR = MPU_Init->BaseAddress; + MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | + ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | + ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | + ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | + ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | + ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | + ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | + ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | + ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); +} +#endif /* __MPU_PRESENT */ + +/** + * @brief Gets the priority grouping field from the NVIC Interrupt Controller. + * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) + */ +uint32_t HAL_NVIC_GetPriorityGrouping(void) +{ + /* Get the PRIGROUP[10:8] field value */ + return NVIC_GetPriorityGrouping(); +} + +/** + * @brief Gets the priority of an interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @param PriorityGroup the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority + * 4 bits for subpriority + * @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority + * 3 bits for subpriority + * @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority + * 2 bits for subpriority + * @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority + * 1 bits for subpriority + * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority + * 0 bits for subpriority + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). + * @retval None + */ +void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + /* Get priority for Cortex-M system or device specific interrupts */ + NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); +} + +/** + * @brief Sets Pending bit of an external interrupt. + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Set interrupt pending */ + NVIC_SetPendingIRQ(IRQn); +} + +/** + * @brief Gets Pending Interrupt (reads the pending register in the NVIC + * and returns the pending bit for the specified interrupt). + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if pending else 0 */ + return NVIC_GetPendingIRQ(IRQn); +} + +/** + * @brief Clears the pending bit of an external interrupt. + * @param IRQn External interrupt number. + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval None + */ +void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Clear pending interrupt */ + NVIC_ClearPendingIRQ(IRQn); +} + +/** + * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit). + * @param IRQn External interrupt number + * This parameter can be an enumerator of IRQn_Type enumeration + * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) + * @retval status: - 0 Interrupt status is not pending. + * - 1 Interrupt status is pending. + */ +uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) +{ + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Return 1 if active else 0 */ + return NVIC_GetActive(IRQn); +} + +/** + * @brief Configures the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. + * This parameter can be one of the following values: + * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. + * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. + * @retval None + */ +void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) +{ + /* Check the parameters */ + assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); + if (CLKSource == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; + } +} + +/** + * @brief This function handles SYSTICK interrupt request. + * @retval None + */ +void HAL_SYSTICK_IRQHandler(void) +{ + HAL_SYSTICK_Callback(); +} + +/** + * @brief SYSTICK callback. + * @retval None + */ +__weak void HAL_SYSTICK_Callback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_SYSTICK_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_CORTEX_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c deleted file mode 100644 index 1e59801f..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c +++ /dev/null @@ -1,516 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_crc.c - * @author MCD Application Team - * @brief CRC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Cyclic Redundancy Check (CRC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - (+) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); - (+) Initialize CRC calculator - (++) specify generating polynomial (peripheral default or non-default one) - (++) specify initialization value (peripheral default or non-default one) - (++) specify input data format - (++) specify input or output data inversion mode if any - (+) Use HAL_CRC_Accumulate() function to compute the CRC value of the - input data buffer starting with the previously computed CRC as - initialization value - (+) Use HAL_CRC_Calculate() function to compute the CRC value of the - input data buffer starting with the defined initialization value - (default or non-default) to initiate CRC calculation - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup CRC CRC - * @brief CRC HAL module driver. - * @{ - */ - -#ifdef HAL_CRC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup CRC_Private_Functions CRC Private Functions - * @{ - */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CRC_Exported_Functions CRC Exported Functions - * @{ - */ - -/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the CRC according to the specified parameters - in the CRC_InitTypeDef and create the associated handle - (+) DeInitialize the CRC peripheral - (+) Initialize the CRC MSP (MCU Specific Package) - (+) DeInitialize the CRC MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the CRC according to the specified - * parameters in the CRC_InitTypeDef and create the associated handle. - * @param hcrc CRC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) -{ - /* Check the CRC handle allocation */ - if (hcrc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - - if (hcrc->State == HAL_CRC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcrc->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_CRC_MspInit(hcrc); - } - - hcrc->State = HAL_CRC_STATE_BUSY; - - /* check whether or not non-default generating polynomial has been - * picked up by user */ - assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse)); - if (hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE) - { - /* initialize peripheral with default generating polynomial */ - WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B); - } - else - { - /* initialize CRC peripheral with generating polynomial defined by user */ - if (HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK) - { - return HAL_ERROR; - } - } - - /* check whether or not non-default CRC initial value has been - * picked up by user */ - assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse)); - if (hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE) - { - WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE); - } - else - { - WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue); - } - - - /* set input data inversion mode */ - assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode); - - /* set output data inversion mode */ - assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode)); - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode); - - /* makes sure the input data format (bytes, halfwords or words stream) - * is properly specified by user */ - assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat)); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitialize the CRC peripheral. - * @param hcrc CRC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) -{ - /* Check the CRC handle allocation */ - if (hcrc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); - - /* Check the CRC peripheral state */ - if (hcrc->State == HAL_CRC_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* Reset CRC calculation unit */ - __HAL_CRC_DR_RESET(hcrc); - - /* Reset IDR register content */ - __HAL_CRC_SET_IDR(hcrc, 0); - - /* DeInit the low level hardware */ - HAL_CRC_MspDeInit(hcrc); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_RESET; - - /* Process unlocked */ - __HAL_UNLOCK(hcrc); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the CRC MSP. - * @param hcrc CRC handle - * @retval None - */ -__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcrc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CRC_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the CRC MSP. - * @param hcrc CRC handle - * @retval None - */ -__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcrc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CRC_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - using combination of the previous CRC value and the new one. - - [..] or - - (+) compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - independently of the previous CRC value. - -@endverbatim - * @{ - */ - -/** - * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - * starting with the previously computed CRC as initialization value. - * @param hcrc CRC handle - * @param pBuffer pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. - * @param BufferLength input data buffer length (number of bytes if pBuffer - * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, - * number of words if pBuffer type is * uint32_t). - * @note By default, the API expects a uint32_t pointer as input buffer parameter. - * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. - * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ -uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index; /* CRC input data buffer index */ - uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - switch (hcrc->InputDataFormat) - { - case CRC_INPUTDATA_FORMAT_WORDS: - /* Enter Data to the CRC calculator */ - for (index = 0U; index < BufferLength; index++) - { - hcrc->Instance->DR = pBuffer[index]; - } - temp = hcrc->Instance->DR; - break; - - case CRC_INPUTDATA_FORMAT_BYTES: - temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); - break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: - temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ - break; - default: - break; - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return the CRC computed value */ - return temp; -} - -/** - * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer - * starting with hcrc->Instance->INIT as initialization value. - * @param hcrc CRC handle - * @param pBuffer pointer to the input data buffer, exact input data format is - * provided by hcrc->InputDataFormat. - * @param BufferLength input data buffer length (number of bytes if pBuffer - * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, - * number of words if pBuffer type is * uint32_t). - * @note By default, the API expects a uint32_t pointer as input buffer parameter. - * Input buffer pointers with other types simply need to be cast in uint32_t - * and the API will internally adjust its input data processing based on the - * handle field hcrc->InputDataFormat. - * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ -uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) -{ - uint32_t index; /* CRC input data buffer index */ - uint32_t temp = 0U; /* CRC output (read from hcrc->Instance->DR register) */ - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* Reset CRC Calculation Unit (hcrc->Instance->INIT is - * written in hcrc->Instance->DR) */ - __HAL_CRC_DR_RESET(hcrc); - - switch (hcrc->InputDataFormat) - { - case CRC_INPUTDATA_FORMAT_WORDS: - /* Enter 32-bit input data to the CRC calculator */ - for (index = 0U; index < BufferLength; index++) - { - hcrc->Instance->DR = pBuffer[index]; - } - temp = hcrc->Instance->DR; - break; - - case CRC_INPUTDATA_FORMAT_BYTES: - /* Specific 8-bit input data handling */ - temp = CRC_Handle_8(hcrc, (uint8_t *)pBuffer, BufferLength); - break; - - case CRC_INPUTDATA_FORMAT_HALFWORDS: - /* Specific 16-bit input data handling */ - temp = CRC_Handle_16(hcrc, (uint16_t *)(void *)pBuffer, BufferLength); /* Derogation MisraC2012 R.11.5 */ - break; - - default: - break; - } - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return the CRC computed value */ - return temp; -} - -/** - * @} - */ - -/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Return the CRC handle state. - * @param hcrc CRC handle - * @retval HAL state - */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc) -{ - /* Return CRC handle state */ - return hcrc->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup CRC_Private_Functions - * @{ - */ - -/** - * @brief Enter 8-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. - * @param hcrc CRC handle - * @param pBuffer pointer to the input data buffer - * @param BufferLength input data buffer length - * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ -static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) -{ - uint32_t i; /* input data buffer index */ - uint16_t data; - __IO uint16_t *pReg; - - /* Processing time optimization: 4 bytes are entered in a row with a single word write, - * last bytes must be carefully fed to the CRC calculator to ensure a correct type - * handling by the peripheral */ - for (i = 0U; i < (BufferLength / 4U); i++) - { - hcrc->Instance->DR = ((uint32_t)pBuffer[4U * i] << 24U) | \ - ((uint32_t)pBuffer[(4U * i) + 1U] << 16U) | \ - ((uint32_t)pBuffer[(4U * i) + 2U] << 8U) | \ - (uint32_t)pBuffer[(4U * i) + 3U]; - } - /* last bytes specific handling */ - if ((BufferLength % 4U) != 0U) - { - if ((BufferLength % 4U) == 1U) - { - *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ - } - if ((BufferLength % 4U) == 2U) - { - data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ - *pReg = data; - } - if ((BufferLength % 4U) == 3U) - { - data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ - *pReg = data; - - *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ - } - } - - /* Return the CRC computed value */ - return hcrc->Instance->DR; -} - -/** - * @brief Enter 16-bit input data to the CRC calculator. - * Specific data handling to optimize processing time. - * @param hcrc CRC handle - * @param pBuffer pointer to the input data buffer - * @param BufferLength input data buffer length - * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) - */ -static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) -{ - uint32_t i; /* input data buffer index */ - __IO uint16_t *pReg; - - /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, - * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure - * a correct type handling by the peripheral */ - for (i = 0U; i < (BufferLength / 2U); i++) - { - hcrc->Instance->DR = ((uint32_t)pBuffer[2U * i] << 16U) | (uint32_t)pBuffer[(2U * i) + 1U]; - } - if ((BufferLength % 2U) != 0U) - { - pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ - *pReg = pBuffer[2U * i]; - } - - /* Return the CRC computed value */ - return hcrc->Instance->DR; -} - -/** - * @} - */ - -#endif /* HAL_CRC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c deleted file mode 100644 index 6483bdb6..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c +++ /dev/null @@ -1,232 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_crc_ex.c - * @author MCD Application Team - * @brief Extended CRC HAL module driver. - * This file provides firmware functions to manage the extended - * functionalities of the CRC peripheral. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim -================================================================================ - ##### How to use this driver ##### -================================================================================ - [..] - (+) Set user-defined generating polynomial through HAL_CRCEx_Polynomial_Set() - (+) Configure Input or Output data inversion - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup CRCEx CRCEx - * @brief CRC Extended HAL module driver - * @{ - */ - -#ifdef HAL_CRC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions - * @{ - */ - -/** @defgroup CRCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions - * @brief Extended Initialization and Configuration functions. - * -@verbatim - =============================================================================== - ##### Extended configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the generating polynomial - (+) Configure the input data inversion - (+) Configure the output data inversion - -@endverbatim - * @{ - */ - - -/** - * @brief Initialize the CRC polynomial if different from default one. - * @param hcrc CRC handle - * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long). - * This parameter is written in normal representation, e.g. - * @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 - * @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 - * @param PolyLength CRC polynomial length. - * This parameter can be one of the following values: - * @arg @ref CRC_POLYLENGTH_7B 7-bit long CRC (generating polynomial of degree 7) - * @arg @ref CRC_POLYLENGTH_8B 8-bit long CRC (generating polynomial of degree 8) - * @arg @ref CRC_POLYLENGTH_16B 16-bit long CRC (generating polynomial of degree 16) - * @arg @ref CRC_POLYLENGTH_32B 32-bit long CRC (generating polynomial of degree 32) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t msb = 31U; /* polynomial degree is 32 at most, so msb is initialized to max value */ - - /* Check the parameters */ - assert_param(IS_CRC_POL_LENGTH(PolyLength)); - - /* Ensure that the generating polynomial is odd */ - if ((Pol & (uint32_t)(0x1U)) == 0U) - { - status = HAL_ERROR; - } - else - { - /* check polynomial definition vs polynomial size: - * polynomial length must be aligned with polynomial - * definition. HAL_ERROR is reported if Pol degree is - * larger than that indicated by PolyLength. - * Look for MSB position: msb will contain the degree of - * the second to the largest polynomial member. E.g., for - * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while ((msb-- > 0U) && ((Pol & ((uint32_t)(0x1U) << (msb & 0x1FU))) == 0U)) - { - } - - switch (PolyLength) - { - - case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_8B: - if (msb >= HAL_CRC_LENGTH_8B) - { - status = HAL_ERROR; - } - break; - case CRC_POLYLENGTH_16B: - if (msb >= HAL_CRC_LENGTH_16B) - { - status = HAL_ERROR; - } - break; - - case CRC_POLYLENGTH_32B: - /* no polynomial definition vs. polynomial length issue possible */ - break; - default: - status = HAL_ERROR; - break; - } - } - if (status == HAL_OK) - { - /* set generating polynomial */ - WRITE_REG(hcrc->Instance->POL, Pol); - - /* set generating polynomial size */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength); - } - /* Return function status */ - return status; -} - -/** - * @brief Set the Reverse Input data mode. - * @param hcrc CRC handle - * @param InputReverseMode Input Data inversion mode. - * This parameter can be one of the following values: - * @arg @ref CRC_INPUTDATA_INVERSION_NONE no change in bit order (default value) - * @arg @ref CRC_INPUTDATA_INVERSION_BYTE Byte-wise bit reversal - * @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD HalfWord-wise bit reversal - * @arg @ref CRC_INPUTDATA_INVERSION_WORD Word-wise bit reversal - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) -{ - /* Check the parameters */ - assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* set input data inversion mode */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode); - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the Reverse Output data mode. - * @param hcrc CRC handle - * @param OutputReverseMode Output Data inversion mode. - * This parameter can be one of the following values: - * @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion (default value) - * @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) -{ - /* Check the parameters */ - assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_BUSY; - - /* set output data inversion mode */ - MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode); - - /* Change CRC peripheral state */ - hcrc->State = HAL_CRC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - - - - -/** - * @} - */ - - -/** - * @} - */ - - -#endif /* HAL_CRC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c deleted file mode 100644 index a1e63130..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp.c +++ /dev/null @@ -1,7152 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cryp.c - * @author MCD Application Team - * @brief CRYP HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Cryptography (CRYP) peripheral: - * + Initialization, de-initialization, set config and get config functions - * + DES/TDES, AES processing functions - * + DMA callback functions - * + CRYP IRQ handler management - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The CRYP HAL driver can be used in CRYP or TinyAES IP as follows: - - (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP - (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT()) - (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA()) - (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE() - (+++) Configure and enable two DMA streams one for managing data transfer from - memory to peripheral (input stream) and another stream for managing data - transfer from peripheral to memory (output stream) - (+++) Associate the initialized DMA handle to the CRYP DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ() - - (#)Initialize the CRYP according to the specified parameters : - (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit. - (##) The key size: 128, 192 or 256. - (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM. - (##) The initialization vector (counter). It is not used in ECB mode. - (##) The key buffer used for encryption/decryption. - (##) The Header used only in AES GCM and CCM Algorithm for authentication. - (##) The HeaderSize The size of header buffer in word. - (##) The B0 block is the first authentication block used only in AES CCM mode. - - (#)Three processing (encryption/decryption) functions are available: - (##) Polling mode: encryption and decryption APIs are blocking functions - i.e. they process the data and wait till the processing is finished, - e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt - (##) Interrupt mode: encryption and decryption APIs are not blocking functions - i.e. they process the data under interrupt, - e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT - (##) DMA mode: encryption and decryption APIs are not blocking functions - i.e. the data transfer is ensured by DMA, - e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA - - (#)When the processing function is called at first time after HAL_CRYP_Init() - the CRYP peripheral is configured and processes the buffer in input. - At second call, no need to Initialize the CRYP, user have to get current configuration via - HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set - new parametres, finally user can start encryption/decryption. - - (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. - - (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt() - without having to configure again the Key or the Initialization Vector between each API call, - the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE. - Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA() - or HAL_CRYP_Decrypt_DMA(). - - [..] - The cryptographic processor supports following standards: - (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP: - (##)64-bit data block processing - (##) chaining modes supported : - (+++) Electronic Code Book(ECB) - (+++) Cipher Block Chaining (CBC) - (##) keys length supported :64-bit, 128-bit and 192-bit. - (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP: - (##)128-bit data block processing - (##) chaining modes supported : - (+++) Electronic Code Book(ECB) - (+++) Cipher Block Chaining (CBC) - (+++) Counter mode (CTR) - (+++) Galois/counter mode (GCM/GMAC) - (+++) Counter with Cipher Block Chaining-Message(CCM) - (##) keys length Supported : - (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit. - (+++) for TinyAES IP: 128-bit and 256-bit - - [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP: - (#) Algorithm supported : - (##) Galois/counter mode (GCM) - (##) Galois message authentication code (GMAC) :is exactly the same as - GCM algorithm composed only by an header. - (#) Four phases are performed in GCM : - (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing - (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash - computation only. - (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream - encryption + data XORing. It works in a similar way for ciphertext (C). - (##) Final phase: IP generates the authenticated tag (T) using the last block of data. - (#) structure of message construction in GCM is defined as below : - (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter - (##) The authenticated header A (also knows as Additional Authentication Data AAD) - this part of the message is only authenticated, not encrypted. - (##) The plaintext message P is both authenticated and encrypted as ciphertext. - GCM standard specifies that ciphertext has same bit length as the plaintext. - (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext - (on 64 bits) - - [..] This section describe The AES Counter with Cipher Block Chaining-Message - Authentication Code (CCM) supported by both CRYP1 IP: - (#) Specific parameters for CCM : - - (##) B0 block : According to NIST Special Publication 800-38C, - The first block B0 is formatted as follows, where l(m) is encoded in - most-significant-byte first order(see below table 3) - - (+++) Q: a bit string representation of the octet length of P (plaintext) - (+++) q The octet length of the binary representation of the octet length of the payload - (+++) A nonce (N), n The octet length of the where n+q=15. - (+++) Flags: most significant octet containing four flags for control information, - (+++) t The octet length of the MAC. - (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A) - the associated data length expressed in bytes (a) defined as below: - (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets - (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets - (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets - (##) CTRx block : control blocks - (+++) Generation of CTR1 from first block B0 information : - equal to B0 with first 5 bits zeroed and most significant bits storing octet - length of P also zeroed, then incremented by one ( see below Table 4) - (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero. - - (#) Four phases are performed in CCM for CRYP1 IP: - (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing - (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash - computation only. - (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream - encryption + data XORing. It works in a similar way for ciphertext (C). - (##) Final phase: IP generates the authenticated tag (T) using the last block of data. - - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() - to register an interrupt callback. - - Function HAL_CRYP_RegisterCallback() allows to register following callbacks: - (+) InCpltCallback : Input FIFO transfer completed callback. - (+) OutCpltCallback : Output FIFO transfer completed callback. - (+) ErrorCallback : callback for error detection. - (+) MspInitCallback : CRYP MspInit. - (+) MspDeInitCallback : CRYP MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) InCpltCallback : Input FIFO transfer completed callback. - (+) OutCpltCallback : Output FIFO transfer completed callback. - (+) ErrorCallback : callback for error detection. - (+) MspInitCallback : CRYP MspInit. - (+) MspDeInitCallback : CRYP MspDeInit. - - By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET - all callbacks are set to the corresponding weak functions : - examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit() - keep and use the user MspInit/MspDeInit functions (registered beforehand) - - Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only. - Exception done MspInit/MspDeInit callbacks that can be registered/unregistered - in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit() - or HAL_CRYP_Init() function. - - When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - Table 1. Initial Counter Block (ICB) - +-------------------------------------------------------+ - | Initialization vector (IV) | Counter | - |----------------|----------------|-----------|---------| - 127 95 63 31 0 - - - Bit Number Register Contents - ---------- --------------- ----------- - 127 ...96 CRYP_IV1R[31:0] ICB[127:96] - 95 ...64 CRYP_IV1L[31:0] B0[95:64] - 63 ... 32 CRYP_IV0R[31:0] ICB[63:32] - 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2 - - Table 2. GCM last block definition - - +-------------------------------------------------------------------+ - | Bit[0] | Bit[32] | Bit[64] | Bit[96] | - |-----------|--------------------|-----------|----------------------| - | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] | - |-----------|--------------------|-----------|----------------------| - - Table 3. B0 block - Octet Number Contents - ------------ --------- - 0 Flags - 1 ... 15-q Nonce N - 16-q ... 15 Q - - the Flags field is formatted as follows: - - Bit Number Contents - ---------- ---------------------- - 7 Reserved (always zero) - 6 Adata - 5 ... 3 (t-2)/2 - 2 ... 0 [q-1]3 - - Table 4. CTRx block - Bit Number Register Contents - ---------- --------------- ----------- - 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for - bit 0 that is set to 1 - 95 ...64 CRYP_IV1L[31:0] B0[95:64] - 63 ... 32 CRYP_IV0R[31:0] B0[63:32] - 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0 - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined (AES) || defined (CRYP) - -/** @defgroup CRYP CRYP - * @brief CRYP HAL module driver. - * @{ - */ - - -#ifdef HAL_CRYP_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup CRYP_Private_Defines - * @{ - */ -#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/ -#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/ - -#define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */ -#define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */ - -#if defined(AES) -#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */ -#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */ -#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */ -#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */ -#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ -#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ -#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ -#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */ -#else /* CRYP */ -#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ -#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */ -#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */ -#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */ -#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */ -#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */ -#endif /* End CRYP or AES */ - -/* CTR1 information to use in CCM algorithm */ -#define CRYP_CCM_CTR1_0 0x07FFFFFFU -#define CRYP_CCM_CTR1_1 0xFFFFFF00U -#define CRYP_CCM_CTR1_2 0x00000001U - - -/** - * @} - */ - - -/* Private macro -------------------------------------------------------------*/ -/** @addtogroup CRYP_Private_Macros - * @{ - */ - -#if defined(CRYP) - -#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\ - (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\ - }while(0) - -#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH) - -#else /*AES*/ -#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\ - (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\ - }while(0) -#endif /* End AES or CRYP*/ - - -/** - * @} - */ - -/* Private struct -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup CRYP_Private_Functions_prototypes - * @{ - */ - -static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); -static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); -static void CRYP_DMAError(DMA_HandleTypeDef *hdma); -static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize); -static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp); - -static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp); -static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp); -static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp); -static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp); -static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp); -static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp); -static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp); - -static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp); -static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp); -static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp); -#if defined (CRYP) -static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp); - -static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); - -static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -#else /*AES*/ -static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout); -#endif /* End CRYP or AES */ - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup CRYP_Exported_Functions CRYP Exported Functions - * @{ - */ - - -/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - ======================================================================================== - ##### Initialization, de-initialization and Set and Get configuration functions ##### - ======================================================================================== - [..] This section provides functions allowing to: - (+) Initialize the CRYP - (+) DeInitialize the CRYP - (+) Initialize the CRYP MSP - (+) DeInitialize the CRYP MSP - (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef - Parameters which are configured in This section are : - (+) Key size - (+) Data Type : 32,16, 8 or 1bit - (+) AlgoMode : - - for CRYP1 IP : - ECB and CBC in DES/TDES Standard - ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard. - - for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported. - (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef - - -@endverbatim - * @{ - */ - - -/** - * @brief Initializes the CRYP according to the specified - * parameters in the CRYP_ConfigTypeDef and creates the associated handle. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) -{ - /* Check the CRYP handle allocation */ - if (hcryp == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize)); - assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); - assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm)); - assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip)); - -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - if (hcryp->State == HAL_CRYP_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcryp->Lock = HAL_UNLOCKED; - - hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ - hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ - hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hcryp->MspInitCallback == NULL) - { - hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hcryp->MspInitCallback(hcryp); - } -#else - if (hcryp->State == HAL_CRYP_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hcryp->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_CRYP_MspInit(hcryp); - } -#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */ - - /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */ -#if defined (CRYP) - - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, - hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); - -#else /*AES*/ - - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, - hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); - -#endif /* End AES or CRYP*/ - - /* Reset Error Code field */ - hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Set the default CRYP phase */ - hcryp->Phase = CRYP_PHASE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief De-Initializes the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) -{ - /* Check the CRYP handle allocation */ - if (hcryp == NULL) - { - return HAL_ERROR; - } - - /* Set the default CRYP phase */ - hcryp->Phase = CRYP_PHASE_READY; - - /* Reset CrypInCount and CrypOutCount */ - hcryp->CrypInCount = 0; - hcryp->CrypOutCount = 0; - hcryp->CrypHeaderCount = 0; - - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - - if (hcryp->MspDeInitCallback == NULL) - { - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */ - } - /* DeInit the low level hardware */ - hcryp->MspDeInitCallback(hcryp); - -#else - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_CRYP_MspDeInit(hcryp); - -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the CRYP according to the specified - * parameters in the CRYP_ConfigTypeDef - * @param hcryp: pointer to a CRYP_HandleTypeDef structure - * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) -{ - /* Check the CRYP handle allocation */ - if ((hcryp == NULL) || (pConf == NULL)) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_CRYP_KEYSIZE(pConf->KeySize)); - assert_param(IS_CRYP_DATATYPE(pConf->DataType)); - assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm)); - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Set CRYP parameters */ - hcryp->Init.DataType = pConf->DataType; - hcryp->Init.pKey = pConf->pKey; - hcryp->Init.Algorithm = pConf->Algorithm; - hcryp->Init.KeySize = pConf->KeySize; - hcryp->Init.pInitVect = pConf->pInitVect; - hcryp->Init.Header = pConf->Header; - hcryp->Init.HeaderSize = pConf->HeaderSize; - hcryp->Init.B0 = pConf->B0; - hcryp->Init.DataWidthUnit = pConf->DataWidthUnit; - hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip; - hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit; - - /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/ -#if defined (CRYP) - - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE, - hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); - -#else /*AES*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD, - hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm); - - /*clear error flags*/ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR); - -#endif /* End AES or CRYP */ - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Reset Error Code field */ - hcryp->ErrorCode = HAL_CRYP_ERROR_NONE; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Set the default CRYP phase */ - hcryp->Phase = CRYP_PHASE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - return HAL_ERROR; - } -} - -/** - * @brief Get CRYP Configuration parameters in associated handle. - * @param pConf: pointer to a CRYP_ConfigTypeDef structure - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf) -{ - /* Check the CRYP handle allocation */ - if ((hcryp == NULL) || (pConf == NULL)) - { - return HAL_ERROR; - } - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Get CRYP parameters */ - pConf->DataType = hcryp->Init.DataType; - pConf->pKey = hcryp->Init.pKey; - pConf->Algorithm = hcryp->Init.Algorithm; - pConf->KeySize = hcryp->Init.KeySize ; - pConf->pInitVect = hcryp->Init.pInitVect; - pConf->Header = hcryp->Init.Header ; - pConf->HeaderSize = hcryp->Init.HeaderSize; - pConf->B0 = hcryp->Init.B0; - pConf->DataWidthUnit = hcryp->Init.DataWidthUnit; - pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip; - pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - return HAL_ERROR; - } -} -/** - * @brief Initializes the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CRYP_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitializes CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CRYP_MspDeInit can be implemented in the user file - */ -} - -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User CRYP Callback - * To be used instead of the weak predefined callback - * @param hcryp cryp handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID - * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID - * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, - pCRYP_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hcryp); - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - switch (CallbackID) - { - case HAL_CRYP_INPUT_COMPLETE_CB_ID : - hcryp->InCpltCallback = pCallback; - break; - - case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : - hcryp->OutCpltCallback = pCallback; - break; - - case HAL_CRYP_ERROR_CB_ID : - hcryp->ErrorCallback = pCallback; - break; - - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = pCallback; - break; - - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcryp->State == HAL_CRYP_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = pCallback; - break; - - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hcryp); - - return status; -} - -/** - * @brief Unregister an CRYP Callback - * CRYP callback is redirected to the weak predefined callback - * @param hcryp cryp handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID - * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID - * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID - * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hcryp); - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - switch (CallbackID) - { - case HAL_CRYP_INPUT_COMPLETE_CB_ID : - hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */ - break; - - case HAL_CRYP_OUTPUT_COMPLETE_CB_ID : - hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */ - break; - - case HAL_CRYP_ERROR_CB_ID : - hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = HAL_CRYP_MspInit; - break; - - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; - break; - - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hcryp->State == HAL_CRYP_STATE_RESET) - { - switch (CallbackID) - { - case HAL_CRYP_MSPINIT_CB_ID : - hcryp->MspInitCallback = HAL_CRYP_MspInit; - break; - - case HAL_CRYP_MSPDEINIT_CB_ID : - hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; - break; - - default : - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hcryp); - - return status; -} -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions - * @brief processing functions. - * -@verbatim - ============================================================================== - ##### Encrypt Decrypt functions ##### - ============================================================================== - [..] This section provides API allowing to Encrypt/Decrypt Data following - Standard DES/TDES or AES, and Algorithm configured by the user: - (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported : - - Electronic Code Book(ECB) - - Cipher Block Chaining (CBC) - (+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported: - - Electronic Code Book(ECB) - - Cipher Block Chaining (CBC) - - Counter mode (CTR) - - Cipher Block Chaining (CBC) - - Counter mode (CTR) - - Galois/counter mode (GCM) - - Counter with Cipher Block Chaining-Message(CCM) - [..] Three processing functions are available: - (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt - (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT - (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA - -@endverbatim - * @{ - */ - - -/** - * @brief Encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the input buffer (plaintext) - * @param Size: Length of the plaintext buffer in word. - * @param Output: Pointer to the output buffer(ciphertext) - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, - uint32_t Timeout) -{ - uint32_t algo; - HAL_StatusTypeDef status; - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Change state Busy */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - hcryp->pCrypInBuffPtr = Input; - hcryp->pCrypOutBuffPtr = Output; - - /* Calculate Size parameter in Byte*/ - if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) - { - hcryp->Size = Size * 4U; - } - else - { - hcryp->Size = Size; - } - -#if defined (CRYP) - /* Set Encryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - - switch (algo) - { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: - - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); - } - - /*Set Initialization Vector (IV)*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - } - - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DES/TDES encryption process */ - status = CRYP_TDES_Process(hcryp, Timeout); - break; - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES encryption */ - status = CRYP_AES_Encrypt(hcryp, Timeout); - break; - - case CRYP_AES_GCM: - - /* AES GCM encryption */ - status = CRYP_AESGCM_Process(hcryp, Timeout); - - break; - - case CRYP_AES_CCM: - - /* AES CCM encryption */ - status = CRYP_AESCCM_Process(hcryp, Timeout); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - -#else /*AES*/ - - /* Set the operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & AES_CR_CHMOD; - - switch (algo) - { - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES encryption */ - status = CRYP_AES_Encrypt(hcryp, Timeout); - break; - - case CRYP_AES_GCM_GMAC: - - /* AES GCM encryption */ - status = CRYP_AESGCM_Process(hcryp, Timeout) ; - break; - - case CRYP_AES_CCM: - - /* AES CCM encryption */ - status = CRYP_AESCCM_Process(hcryp, Timeout); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } -#endif /*end AES or CRYP */ - - if (status == HAL_OK) - { - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - } - else - { - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - return HAL_ERROR; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the input buffer (ciphertext ) - * @param Size: Length of the plaintext buffer in word. - * @param Output: Pointer to the output buffer(plaintext) - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, - uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t algo; - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Change state Busy */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - hcryp->pCrypInBuffPtr = Input; - hcryp->pCrypOutBuffPtr = Output; - - /* Calculate Size parameter in Byte*/ - if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) - { - hcryp->Size = Size * 4U; - } - else - { - hcryp->Size = Size; - } - -#if defined (CRYP) - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - - switch (algo) - { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: - - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); - } - - /*Set Initialization Vector (IV)*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - } - - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DES/TDES decryption process */ - status = CRYP_TDES_Process(hcryp, Timeout); - - break; - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES decryption */ - status = CRYP_AES_Decrypt(hcryp, Timeout); - break; - - case CRYP_AES_GCM: - - /* AES GCM decryption */ - status = CRYP_AESGCM_Process(hcryp, Timeout) ; - break; - - case CRYP_AES_CCM: - - /* AES CCM decryption */ - status = CRYP_AESCCM_Process(hcryp, Timeout); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - -#else /*AES*/ - - /* Set Decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & AES_CR_CHMOD; - - switch (algo) - { - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES decryption */ - status = CRYP_AES_Decrypt(hcryp, Timeout); - break; - - case CRYP_AES_GCM_GMAC: - - /* AES GCM decryption */ - status = CRYP_AESGCM_Process(hcryp, Timeout) ; - break; - - case CRYP_AES_CCM: - - /* AES CCM decryption */ - status = CRYP_AESCCM_Process(hcryp, Timeout); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } -#endif /* End AES or CRYP */ - - if (status == HAL_OK) - { - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - } - else - { - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - return HAL_ERROR; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Encryption in interrupt mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the input buffer (plaintext) - * @param Size: Length of the plaintext buffer in word - * @param Output: Pointer to the output buffer(ciphertext) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) -{ - uint32_t algo; - HAL_StatusTypeDef status = HAL_OK; - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Change state Busy */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - hcryp->pCrypInBuffPtr = Input; - hcryp->pCrypOutBuffPtr = Output; - - /* Calculate Size parameter in Byte*/ - if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) - { - hcryp->Size = Size * 4U; - } - else - { - hcryp->Size = Size; - } - -#if defined (CRYP) - - /* Set encryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); - - /* algo get algorithm selected */ - algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE); - - switch (algo) - { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: - - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); - } - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - } - - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP to start DES/TDES process*/ - __HAL_CRYP_ENABLE(hcryp); - break; - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - status = CRYP_AES_Encrypt_IT(hcryp); - break; - - case CRYP_AES_GCM: - - status = CRYP_AESGCM_Process_IT(hcryp) ; - break; - - case CRYP_AES_CCM: - - status = CRYP_AESCCM_Process_IT(hcryp); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - status = HAL_ERROR; - break; - } - -#else /* AES */ - - /* Set encryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & AES_CR_CHMOD; - - switch (algo) - { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES encryption */ - status = CRYP_AES_Encrypt_IT(hcryp); - break; - - case CRYP_AES_GCM_GMAC: - - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_IT(hcryp) ; - break; - - case CRYP_AES_CCM: - - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - status = HAL_ERROR; - break; - } -#endif /*end AES or CRYP*/ - - } - else - { - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @brief Decryption in itnterrupt mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the input buffer (ciphertext ) - * @param Size: Length of the plaintext buffer in word. - * @param Output: Pointer to the output buffer(plaintext) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) -{ - uint32_t algo; - HAL_StatusTypeDef status = HAL_OK; - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Change state Busy */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - hcryp->pCrypInBuffPtr = Input; - hcryp->pCrypOutBuffPtr = Output; - - /* Calculate Size parameter in Byte*/ - if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) - { - hcryp->Size = Size * 4U; - } - else - { - hcryp->Size = Size; - } - -#if defined (CRYP) - - /* Set decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - - switch (algo) - { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: - - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); - } - - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - } - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP and start DES/TDES process*/ - __HAL_CRYP_ENABLE(hcryp); - - break; - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES decryption */ - status = CRYP_AES_Decrypt_IT(hcryp); - break; - - case CRYP_AES_GCM: - - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_IT(hcryp) ; - break; - - case CRYP_AES_CCM: - - /* AES CCMdecryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - status = HAL_ERROR; - break; - } - -#else /*AES*/ - - /* Set decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & AES_CR_CHMOD; - - switch (algo) - { - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES decryption */ - status = CRYP_AES_Decrypt_IT(hcryp); - break; - - case CRYP_AES_GCM_GMAC: - - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_IT(hcryp) ; - break; - - case CRYP_AES_CCM: - - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_IT(hcryp); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - status = HAL_ERROR; - break; - } -#endif /* End AES or CRYP */ - - } - else - { - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @brief Encryption in DMA mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the input buffer (plaintext) - * @param Size: Length of the plaintext buffer in word. - * @param Output: Pointer to the output buffer(ciphertext) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) -{ - uint32_t algo; - HAL_StatusTypeDef status = HAL_OK; - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Change state Busy */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/ - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - hcryp->pCrypInBuffPtr = Input; - hcryp->pCrypOutBuffPtr = Output; - - /* Calculate Size parameter in Byte*/ - if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) - { - hcryp->Size = Size * 4U; - } - else - { - hcryp->Size = Size; - } - -#if defined (CRYP) - - /* Set encryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - - switch (algo) - { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: - - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); - } - - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - } - - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DMA process transfer for DES/TDES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), - (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - } - } - - if (DoKeyIVConfig == 1U) - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the Initialization Vector*/ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U); - } - } /* if (DoKeyIVConfig == 1U) */ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), - (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; - - case CRYP_AES_GCM: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_DMA(hcryp) ; - break; - - case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - status = HAL_ERROR; - break; - } - -#else /*AES*/ - /* Set encryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & AES_CR_CHMOD; - - switch (algo) - { - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - } - } - - if (DoKeyIVConfig == 1U) - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the Initialization Vector*/ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - } - } /* if (DoKeyIVConfig == 1U) */ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DMA process transfer for AES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; - - case CRYP_AES_GCM_GMAC: - /* AES GCM encryption */ - status = CRYP_AESGCM_Process_DMA(hcryp) ; - break; - - case CRYP_AES_CCM: - /* AES CCM encryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - status = HAL_ERROR; - break; - } -#endif /* End AES or CRYP */ - - } - else - { - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @brief Decryption in DMA mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Input: Pointer to the input buffer (ciphertext ) - * @param Size: Length of the plaintext buffer in word - * @param Output: Pointer to the output buffer(plaintext) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output) -{ - uint32_t algo; - HAL_StatusTypeDef status = HAL_OK; - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - - /* Change state Busy */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/ - hcryp->CrypInCount = 0U; - hcryp->CrypOutCount = 0U; - hcryp->pCrypInBuffPtr = Input; - hcryp->pCrypOutBuffPtr = Output; - - /* Calculate Size parameter in Byte*/ - if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) - { - hcryp->Size = Size * 4U; - } - else - { - hcryp->Size = Size; - } - -#if defined (CRYP) - - /* Set decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE; - - switch (algo) - { - case CRYP_DES_ECB: - case CRYP_DES_CBC: - case CRYP_TDES_ECB: - case CRYP_TDES_CBC: - - /*Set Key */ - hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); - if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); - } - - /* Set the Initialization Vector*/ - if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - } - - /* Flush FIFO */ - HAL_CRYP_FIFO_FLUSH(hcryp); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Start DMA process transfer for DES/TDES */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U), - (uint32_t)(hcryp->pCrypOutBuffPtr)); - break; - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES decryption */ - status = CRYP_AES_Decrypt_DMA(hcryp); - break; - - case CRYP_AES_GCM: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_DMA(hcryp) ; - break; - - case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - status = HAL_ERROR; - break; - } - -#else /*AES*/ - - /* Set decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - - /* algo get algorithm selected */ - algo = hcryp->Instance->CR & AES_CR_CHMOD; - - switch (algo) - { - - case CRYP_AES_ECB: - case CRYP_AES_CBC: - case CRYP_AES_CTR: - - /* AES decryption */ - status = CRYP_AES_Decrypt_DMA(hcryp); - break; - - case CRYP_AES_GCM_GMAC: - /* AES GCM decryption */ - status = CRYP_AESGCM_Process_DMA(hcryp) ; - break; - - case CRYP_AES_CCM: - /* AES CCM decryption */ - status = CRYP_AESCCM_Process_DMA(hcryp); - break; - - default: - hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED; - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - status = HAL_ERROR; - break; - } -#endif /* End AES or CRYP */ - } - else - { - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management - * @brief CRYP IRQ handler. - * -@verbatim - ============================================================================== - ##### CRYP IRQ handler management ##### - ============================================================================== -[..] This section provides CRYP IRQ handler and callback functions. - (+) HAL_CRYP_IRQHandler CRYP interrupt request - (+) HAL_CRYP_InCpltCallback input data transfer complete callback - (+) HAL_CRYP_OutCpltCallback output data transfer complete callback - (+) HAL_CRYP_ErrorCallback CRYP error callback - (+) HAL_CRYP_GetState return the CRYP state - (+) HAL_CRYP_GetError return the CRYP error code -@endverbatim - * @{ - */ - -/** - * @brief This function handles cryptographic interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval None - */ -void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) -{ - -#if defined (CRYP) - - uint32_t itstatus = hcryp->Instance->MISR; - - if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U) - { - if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC) - || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC)) - { - CRYP_TDES_IT(hcryp); /* DES or TDES*/ - } - else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC) - || (hcryp->Init.Algorithm == CRYP_AES_CTR)) - { - CRYP_AES_IT(hcryp); /*AES*/ - } - - else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM)) - { - /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) - { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); - } - else /* if payload phase */ - { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); - } - } - - else - { - /* Nothing to do */ - } - } - -#else /*AES*/ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET) - { - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET) - { - - /* Clear computation complete flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - - /* if header phase */ - if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER) - { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); - } - else /* if payload phase */ - { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); - } - } - else if (hcryp->Init.Algorithm == CRYP_AES_CCM) - { - /* if header phase */ - if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount) - { - CRYP_GCMCCM_SetHeaderPhase_IT(hcryp); - } - else /* if payload phase */ - { - CRYP_GCMCCM_SetPayloadPhase_IT(hcryp); - } - } - else /* AES Algorithm ECB,CBC or CTR*/ - { - CRYP_AES_IT(hcryp); - } - } - } - /* Check if error occurred */ - if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET) - { - /* If write Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET) - { - hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE; - } - /* If read Error occurred */ - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET) - { - hcryp->ErrorCode |= HAL_CRYP_ERROR_READ; - } - } -#endif /* End AES or CRYP */ -} - -/** - * @brief Return the CRYP error code. - * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for the CRYP IP - * @retval CRYP error code - */ -uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp) -{ - return hcryp->ErrorCode; -} - -/** - * @brief Returns the CRYP state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @retval HAL state - */ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) -{ - return hcryp->State; -} - -/** - * @brief Input FIFO transfer completed callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @retval None - */ -__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Output FIFO transfer completed callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @retval None - */ -__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback can be implemented in the user file - */ -} - -/** - * @brief CRYP error callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @retval None - */ -__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hcryp); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ErrorCallback could be implemented in the user file - */ -} -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup CRYP_Private_Functions - * @{ - */ - -#if defined (CRYP) - -/** - * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Timeout: specify Timeout value - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t temp[2]; /* Temporary CrypOutBuff */ - uint16_t incount; /* Temporary CrypInCount Value */ - uint16_t outcount; /* Temporary CrypOutCount Value */ - uint32_t i; - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - /*Start processing*/ - while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) - { - /* Temporary CrypInCount Value */ - incount = hcryp->CrypInCount; - /* Write plain data and get cipher data */ - if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - - /* Wait for OFNE flag to be raised */ - if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state & errorCode*/ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) - { - /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ - for (i = 0U; i < 2U; i++) - { - temp[i] = hcryp->Instance->DOUT; - } - i = 0U; - while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } - } - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - } - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief CRYP block input/output data handling under interruption with DES/TDES standard. - * @note The function is called under interruption only, once - * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @retval none - */ -static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp) -{ - uint32_t temp[2]; /* Temporary CrypOutBuff */ - uint32_t i; - - if (hcryp->State == HAL_CRYP_STATE_BUSY) - { - if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U) - { - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U) - { - /* Write input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - - if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U)) - { - /* Disable interruption */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - /* Call the input data transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - } - if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U) - { - if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U) - { - /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */ - for (i = 0U; i < 2U; i++) - { - temp[i] = hcryp->Instance->DOUT; - } - i = 0U; - while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } - if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U)) - { - /* Disable interruption */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - /* Call output transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); -#else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } -} - -#endif /* CRYP */ - -/** - * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard - * @param hcryp: pointer to a CRYP_HandleTypeDef structure - * @param Timeout: specify Timeout value - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint16_t outcount; /* Temporary CrypOutCount Value */ - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - } - } - - if (DoKeyIVConfig == 1U) - { - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ -#if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#endif /* End AES or CRYP */ - } - } /* if (DoKeyIVConfig == 1U) */ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) - { - /* Write plain Ddta and get cipher data */ - CRYP_AES_ProcessData(hcryp, Timeout); - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - } - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) -{ - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - } - } - - if (DoKeyIVConfig == 1U) - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ -#if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - -#else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#endif /* End AES or CRYP */ - } - } /* if (DoKeyIVConfig == 1U) */ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - if (hcryp->Size != 0U) - { -#if defined (AES) - - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Increment the pointer before writing the input block in the IN FIFO to make sure that - when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value - and it is ready for the next operation. */ - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - -#else /* CRYP */ - - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - -#endif /* End AES or CRYP */ - } - else - { - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Decryption in ECB/CBC & CTR mode with AES Standard - * @param hcryp: pointer to a CRYP_HandleTypeDef structure - * @param Timeout: Specify Timeout value - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint16_t outcount; /* Temporary CrypOutCount Value */ - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - } - } - - if (DoKeyIVConfig == 1U) - { - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) - { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ - { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Wait for CCF flag to be raised */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state & error code*/ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - } - else /*Mode 4 : decryption & Key preparation*/ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & Key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); - } -#else /* CRYP */ - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Wait for BUSY flag to be raised */ - if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - -#endif /* End AES or CRYP */ - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ -#if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#endif /* End AES or CRYP */ - } - } /* if (DoKeyIVConfig == 1U) */ - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U))) - { - /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp, Timeout); - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - } - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Return function status */ - return HAL_OK; -} -/** - * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) -{ - __IO uint32_t count = 0U; - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - } - } - - if (DoKeyIVConfig == 1U) - { - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) - { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/ - { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - } - else /*Mode 4 : decryption & key preparation*/ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); - } -#else /* CRYP */ - - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Wait for BUSY flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count-- ; - if (count == 0U) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - -#endif /* End AES or CRYP */ - } - - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - /* Set IV */ - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ -#if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#endif /* End AES or CRYP */ - } - } /* if (DoKeyIVConfig == 1U) */ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - if (hcryp->Size != 0U) - { - -#if defined (AES) - - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Increment the pointer before writing the input block in the IN FIFO to make sure that - when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value - and it is ready for the next operation. */ - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); - -#else /* CRYP */ - - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - -#endif /* End AES or CRYP */ - } - else - { - /* Process locked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - } - - /* Return function status */ - return HAL_OK; -} -/** - * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) -{ - __IO uint32_t count = 0U; - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - } - } - if (DoKeyIVConfig == 1U) - { - /* Key preparation for ECB/CBC */ - if (hcryp->Init.Algorithm != CRYP_AES_CTR) - { -#if defined (AES) - if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/ - { - /* Set key preparation for decryption operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Wait for CCF flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Return to decryption operating mode(Mode 3)*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT); - } - else /*Mode 4 : decryption & key preparation*/ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set decryption & Key preparation operating mode*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT); - } -#else /* CRYP */ - /* change ALGOMODE to key preparation for decryption*/ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY); - - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Wait for BUSY flag to be raised */ - count = CRYP_TIMEOUT_KEYPREPARATION; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - - /* Turn back to ALGOMODE of the configuration */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); - -#endif /* End AES or CRYP */ - } - else /*Algorithm CTR */ - { - /* Set the Key*/ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - } - - if (hcryp->Init.Algorithm != CRYP_AES_ECB) - { - /* Set the Initialization Vector*/ -#if defined (AES) - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#else /* CRYP */ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); -#endif /* End AES or CRYP */ - } - } /* if (DoKeyIVConfig == 1U) */ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - if (hcryp->Size != 0U) - { - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - } - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief DMA CRYP input data process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit - in the DMACR register */ -#if defined (CRYP) - hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN); - -#else /* AES */ - CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); - - /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */ - if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) - { - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - } -#endif /* End AES or CRYP */ - - /* Call input data transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA CRYP output data process complete callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable the DMA transfer for output FIFO request by resetting - the DOEN bit in the DMACR register */ - -#if defined (CRYP) - - hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN); - if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM) - { - /* Disable CRYP (not allowed in GCM)*/ - __HAL_CRYP_DISABLE(hcryp); - } -#else /* AES */ - - CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) - { - /* Disable CRYP (not allowed in GCM)*/ - __HAL_CRYP_DISABLE(hcryp); - } -#endif /* End AES or CRYP */ - - /* Change the CRYP state to ready */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - /* Call output data transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); -#else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle - * @retval None - */ -static void CRYP_DMAError(DMA_HandleTypeDef *hdma) -{ - CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* DMA error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; - -#if defined (AES) - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - -#endif /* AES */ - - /* Call error callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ -} - -/** - * @brief Set the DMA configuration and start the DMA transfer - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param inputaddr: address of the input buffer - * @param Size: size of the input buffer, must be a multiple of 16. - * @param outputaddr: address of the output buffer - * @retval None - */ -static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) -{ - /* Set the CRYP DMA transfer complete callback */ - hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt; - - /* Set the DMA input error callback */ - hcryp->hdmain->XferErrorCallback = CRYP_DMAError; - - /* Set the CRYP DMA transfer complete callback */ - hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; - - /* Set the DMA output error callback */ - hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; - -#if defined (CRYP) - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - - /* Enable the input DMA Stream */ - if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK) - { - /* DMA error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; - - /* Call error callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - /* Enable the output DMA Stream */ - if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK) - { - /* DMA error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; - - /* Call error callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - /* Enable In/Out DMA request */ - hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN; - -#else /* AES */ - - if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC) - && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM)) - { - /* Enable CRYP (not allowed in GCM & CCM)*/ - __HAL_CRYP_ENABLE(hcryp); - } - - /* Enable the DMA input stream */ - if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK) - { - /* DMA error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; - - /* Call error callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - /* Enable the DMA output stream */ - if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK) - { - /* DMA error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA; - - /* Call error callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Enable In and Out DMA requests */ - if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM) - { - /* Enable only In DMA requests for CCM*/ - SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN)); - } - else - { - /* Enable In and Out DMA requests */ - SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); - } -#endif /* End AES or CRYP */ -} - -/** - * @brief Process Data: Write Input data in polling mode and used in AES functions. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Timeout: Specify Timeout value - * @retval None - */ -static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - - uint32_t temp[4]; /* Temporary CrypOutBuff */ - uint32_t i; -#if defined (CRYP) - uint16_t incount; /* Temporary CrypInCount Value */ - uint16_t outcount; /* Temporary CrypOutCount Value */ -#endif - -#if defined (CRYP) - - /*Temporary CrypOutCount Value*/ - incount = hcryp->CrypInCount; - - if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - - /* Wait for OFNE flag to be raised */ - if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state & error code*/ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) - { - /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - for (i = 0U; i < 4U; i++) - { - temp[i] = hcryp->Instance->DOUT; - } - i = 0U; - while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } - } - -#else /* AES */ - - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - - /* Wait for CCF flag to be raised */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - for (i = 0U; i < 4U; i++) - { - temp[i] = hcryp->Instance->DOUTR; - } - i = 0U; - while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } -#endif /* End AES or CRYP */ -} - -/** - * @brief Handle CRYP block input/output data handling under interruption. - * @note The function is called under interruption only, once - * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @retval HAL status - */ -static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) -{ - uint32_t temp[4]; /* Temporary CrypOutBuff */ - uint32_t i; -#if defined (CRYP) - uint16_t incount; /* Temporary CrypInCount Value */ - uint16_t outcount; /* Temporary CrypOutCount Value */ -#endif - - if (hcryp->State == HAL_CRYP_STATE_BUSY) - { -#if defined (CRYP) - - /*Temporary CrypOutCount Value*/ - incount = hcryp->CrypInCount; - if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U))) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U)) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - - /* Call the input data transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U))) - { - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - for (i = 0U; i < 4U; i++) - { - temp[i] = hcryp->Instance->DOUT; - } - i = 0U; - while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } - if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U)) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Call Output transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); -#else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - -#else /*AES*/ - - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - for (i = 0U; i < 4U; i++) - { - temp[i] = hcryp->Instance->DOUTR; - } - i = 0U; - while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } - - if (hcryp->CrypOutCount == (hcryp->Size / 4U)) - { - /* Disable Computation Complete flag and errors interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Call Output transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); -#else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - else - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - - if (hcryp->CrypInCount == (hcryp->Size / 4U)) - { - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } -#endif /* End AES or CRYP */ - - } - else - { - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Writes Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param KeySize: Size of Key - * @retval None - */ -static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize) -{ -#if defined (CRYP) - - switch (KeySize) - { - case CRYP_KEYSIZE_256B: - hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1); - hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7); - break; - case CRYP_KEYSIZE_192B: - hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1); - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1); - hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3); - - break; - default: - break; - } -#else /*AES*/ - switch (KeySize) - { - case CRYP_KEYSIZE_256B: - hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1); - hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3); - hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4); - hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5); - hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6); - hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7); - break; - case CRYP_KEYSIZE_128B: - hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey); - hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1); - hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2); - hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3); - - break; - default: - break; - } -#endif /* End AES or CRYP */ -} - - -/** - * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ; - uint16_t outcount; /* Temporary CrypOutCount Value */ - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ - } - } - else - { - hcryp->SizesSum = hcryp->Size; - } - - if (DoKeyIVConfig == 1U) - { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; - - /****************************** Init phase **********************************/ - - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - -#if defined(CRYP) - - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /*Wait for the CRYPEN bit to be cleared*/ - while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - -#else /* AES */ - /* Workaround 1 : only AES. - Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); - - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* just wait for hash computation */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - -#endif /* End AES or CRYP */ - - /************************ Header phase *************************************/ - - if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } - - /*************************Payload phase ************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - -#if defined(CRYP) - - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - -#else /* AES */ - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - -#endif /* End AES or CRYP */ - } /* if (DoKeyIVConfig == 1U) */ - - if ((hcryp->Size % 16U) != 0U) - { - /* recalculate wordsize */ - wordsize = ((wordsize / 4U) * 4U) ; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - /* Write input data and get output Data */ - while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) - { - /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp, Timeout); - - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state & error code */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - - if ((hcryp->Size % 16U) != 0U) - { - /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of - 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption - is selected, then the TAG message will be wrong.*/ - CRYP_Workaround(hcryp, Timeout); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) -{ - __IO uint32_t count = 0U; - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ -#if defined(AES) - uint32_t loopcounter; - uint32_t lastwordsize; - uint32_t npblb; -#endif /* AES */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ - } - } - else - { - hcryp->SizesSum = hcryp->Size; - } - - /* Configure Key, IV and process message (header and payload) */ - if (DoKeyIVConfig == 1U) - { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; - - /******************************* Init phase *********************************/ - - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - -#if defined(CRYP) - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - -#else /* AES */ - - /* Workaround 1 : only AES - Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); - - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - -#endif /* End AES or CRYP */ - - /***************************** Header phase *********************************/ - -#if defined(CRYP) - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - -#else /* AES */ - - /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable computation complete flag and error interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/ - { - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - - /* Write the payload Input block in the IN FIFO */ - if (hcryp->Size == 0U) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - else if (hcryp->Size >= 16U) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - if (hcryp->CrypInCount == (hcryp->Size / 4U)) - { - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - else /* Size < 16Bytes : first block is the last block*/ - { - /* Workaround not implemented*/ - /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: - Workaround is implemented in polling mode, so if last block of - payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ - - /* Compute the number of padding bytes in last block of payload */ - npblb = 16U - (uint32_t)(hcryp->Size); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (loopcounter < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - } - } - else if ((hcryp->Init.HeaderSize) < 4U) - { - for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while (loopcounter < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - else if ((hcryp->Init.HeaderSize) >= 4U) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - } - else - { - /* Nothing to do */ - } - -#endif /* End AES or CRYP */ - } /* end of if (DoKeyIVConfig == 1U) */ - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) -{ - __IO uint32_t count = 0U; - uint32_t wordsize; - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ - } - } - else - { - hcryp->SizesSum = hcryp->Size; - } - - if (DoKeyIVConfig == 1U) - { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; - - /*************************** Init phase ************************************/ - - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - -#if defined(CRYP) - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - -#else /* AES */ - - /*Workaround 1 : only AES - Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re - enabling the IP, datatype different from 32 bits can be configured.*/ - /* Select DATATYPE 32 */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B); - - /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/ - hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect); - hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1); - hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2); - hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* just wait for hash computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - -#endif /* End AES or CRYP */ - - /************************ Header phase *************************************/ - - if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; - } - - /************************ Payload phase ************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - -#if defined(CRYP) - - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - -#endif /* CRYP */ - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - } /* if (DoKeyIVConfig == 1U) */ - - if (hcryp->Size != 0U) - { - /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption: - Workaround is implemented in polling mode, so if last block of - payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */ - /* Set the input and output addresses and start DMA transfer */ - if ((hcryp->Size % 16U) == 0U) - { - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */ - { - wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ; - - /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U), - (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - } - else - { - /* Process unLocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief AES CCM encryption/decryption processing in polling mode - * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Timeout: Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U; - uint16_t outcount; /* Temporary CrypOutCount Value */ - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ -#if defined(AES) - uint32_t loopcounter; - uint32_t npblb; - uint32_t lastwordsize; -#endif /* AES */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ - } - } - else - { - hcryp->SizesSum = hcryp->Size; - } - - if (DoKeyIVConfig == 1U) - { - - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; - -#if defined(CRYP) - - /********************** Init phase ******************************************/ - - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Write B0 packet into CRYP_DIN Register*/ - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); - } - /* Get tick */ - tickstart = HAL_GetTick(); - - /*Wait for the CRYPEN bit to be cleared*/ - while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } -#else /* AES */ - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* configured encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); - - /* wait until the end of computation */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* From that point the whole message must be processed, first the Header then the payload. - First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/ - - if (hcryp->Init.HeaderSize != 0U) - { - if ((hcryp->Init.HeaderSize % 4U) == 0U) - { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) - { - /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - } - else - { - /*Write Header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while (loopcounter < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - } - } /* if (DoKeyIVConfig == 1U) */ - /* Then the payload: cleartext payload (not the ciphertext payload). - Write input Data, no output Data to get */ - if (hcryp->Size != 0U) - { - if ((hcryp->Size % 16U) != 0U) - { - /* recalculate wordsize */ - wordsize = ((wordsize / 4U) * 4U) ; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) - { - /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp, Timeout); - - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - - if ((hcryp->Size % 16U) != 0U) - { - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) - { - /* Write the last input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (loopcounter < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - loopcounter++; - } - /* Wait for CCF flag to be raised */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - } - } -#endif /* End AES or CRYP */ - -#if defined(CRYP) - - /************************* Header phase *************************************/ - /* Header block(B1) : associated data length expressed in bytes concatenated - with Associated Data (A)*/ - - if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK) - { - return HAL_ERROR; - } - - /********************** Payload phase ***************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - } /* if (DoKeyIVConfig == 1U) */ - - if ((hcryp->Size % 16U) != 0U) - { - /* recalculate wordsize */ - wordsize = ((wordsize / 4U) * 4U) ; - } - /* Get tick */ - tickstart = HAL_GetTick(); - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - /* Write input data and get output data */ - while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize)) - { - /* Write plain data and get cipher data */ - CRYP_AES_ProcessData(hcryp, Timeout); - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - - if ((hcryp->Size % 16U) != 0U) - { - /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of - 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption - is selected, then the TAG message will be wrong.*/ - CRYP_Workaround(hcryp, Timeout); - } -#endif /* CRYP */ - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief AES CCM encryption/decryption process in interrupt mode - * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) -{ - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ -#if defined(CRYP) - __IO uint32_t count = 0U; -#endif /* CRYP */ - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ - } - } - else - { - hcryp->SizesSum = hcryp->Size; - } - - /* Configure Key, IV and process message (header and payload) */ - if (DoKeyIVConfig == 1U) - { - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; - -#if defined(CRYP) - - /************ Init phase ************/ - - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Write the B0 packet into CRYP_DIN Register*/ - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); - } - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - } /* end of if (DoKeyIVConfig == 1U) */ - - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI); - - /* Enable CRYP */ - __HAL_CRYP_ENABLE(hcryp); - -#else /* AES */ - - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* configured mode and encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; - - /* Enable interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); - - } /* end of if (DoKeyIVConfig == 1U) */ -#endif /* End AES or CRYP */ - - /* Return function status */ - return HAL_OK; -} -/** - * @brief AES CCM encryption/decryption process in DMA mode - * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) -{ - uint32_t wordsize; - __IO uint32_t count = 0U; - uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ -#if defined(AES) - uint32_t loopcounter; - uint32_t npblb; - uint32_t lastwordsize; -#endif - - if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE) - { - if (hcryp->KeyIVConfig == 1U) - { - /* If the Key and IV configuration has to be done only once - and if it has already been done, skip it */ - DoKeyIVConfig = 0U; - hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */ - } - else - { - /* If the Key and IV configuration has to be done only once - and if it has not been done already, do it and set KeyIVConfig - to keep track it won't have to be done again next time */ - hcryp->KeyIVConfig = 1U; - hcryp->SizesSum = hcryp->Size; /* Merely store payload length */ - } - } - else - { - hcryp->SizesSum = hcryp->Size; - } - - if (DoKeyIVConfig == 1U) - { - - /* Reset CrypHeaderCount */ - hcryp->CrypHeaderCount = 0U; - -#if defined(CRYP) - - /************************** Init phase **************************************/ - - CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the initialization vector (IV) with CTR1 information */ - hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0; - hcryp->Instance->IV0RR = hcryp->Init.B0[1]; - hcryp->Instance->IV1LR = hcryp->Init.B0[2]; - hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2; - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Write the B0 packet into CRYP_DIN Register*/ - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16); - hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2)); - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3)); - } - else - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3); - } - - /*Wait for the CRYPEN bit to be cleared*/ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); - -#else /* AES */ - - /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */ - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* configured encryption mode */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT); - - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.KeySize); - - /* Set the initialization vector with zero values*/ - hcryp->Instance->IVR3 = 0U; - hcryp->Instance->IVR2 = 0U; - hcryp->Instance->IVR1 = 0U; - hcryp->Instance->IVR0 = 0U; - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /*Write the B0 packet into CRYP_DIN*/ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2); - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3); - - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* From that point the whole message must be processed, first the Header then the payload. - First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/ - - if (hcryp->Init.HeaderSize != 0U) - { - if ((hcryp->Init.HeaderSize % 4U) == 0U) - { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U) - { - /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /* wait until the end of computation */ - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - } - else - { - /*Write Header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - while (loopcounter < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - } - } /* if (DoKeyIVConfig == 1U) */ - /* Then the payload: cleartext payload (not the ciphertext payload). - Write input Data, no output Data to get */ - if (hcryp->Size != 0U) - { - if (hcryp->Size >= 16U) - { - if ((hcryp->Size % 16U) == 0U) - { - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */ - { - wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ; - - /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U), - (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - } - if ((hcryp->Size < 16U) != 0U) - { - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++) - { - /* Write the last input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (loopcounter < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - loopcounter++; - } - count = CRYP_TIMEOUT_GCMCCMINITPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } - } - else - { - /* Process unLocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } -#endif /* AES */ -#if defined(CRYP) - /********************* Header phase *****************************************/ - - if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK) - { - return HAL_ERROR; - } - - /******************** Payload phase *****************************************/ - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - } /* if (DoKeyIVConfig == 1U) */ - if (hcryp->Size != 0U) - { - /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption - Workaround is implemented in polling mode, so if last block of - payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */ - /* Set the input and output addresses and start DMA transfer */ - if ((hcryp->Size % 16U) == 0U) - { - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - else - { - wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ; - - /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/ - CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U, - (uint32_t)(hcryp->pCrypOutBuffPtr)); - } - } - else /*Size = 0*/ - { - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state and phase */ - hcryp->State = HAL_CRYP_STATE_READY; - } -#endif /* CRYP */ - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Sets the payload phase in interrupt mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @retval state - */ -static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) -{ - uint32_t loopcounter; - uint32_t temp[4]; /* Temporary CrypOutBuff */ - uint32_t lastwordsize; - uint32_t npblb; - uint32_t i; -#if defined(AES) - uint16_t outcount; /* Temporary CrypOutCount Value */ -#endif /* AES */ - - /***************************** Payload phase *******************************/ - -#if defined(CRYP) - if (hcryp->Size == 0U) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - } - - else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U)) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - - /* Call the input data transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - if (hcryp->CrypOutCount < (hcryp->Size / 4U)) - { - /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */ - for (i = 0U; i < 4U; i++) - { - temp[i] = hcryp->Instance->DOUT; - } - i = 0U; - while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } - if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U)) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Call output transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); -#else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - } - else if ((hcryp->Size % 16U) != 0U) - { - /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption - Workaround is implemented in polling mode, so if last block of - payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */ - - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (loopcounter < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DIN = 0x0U; - loopcounter++; - } - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - - if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) - { - for (i = 0U; i < 4U; i++) - { - temp[i] = hcryp->Instance->DOUT; - } - if (((hcryp->Size) / 4U) == 0U) - { - for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - } - } - i = 0x0U; - while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } - } - if (hcryp->CrypOutCount >= (hcryp->Size / 4U)) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Call output transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); -#else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - else - { - /* Nothing to do */ - } -#else /* AES */ - - /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/ - for (i = 0U; i < 4U; i++) - { - temp[i] = hcryp->Instance->DOUTR; - } - i = 0U; - while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U)) - { - *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i]; - hcryp->CrypOutCount++; - i++; - } - /*Temporary CrypOutCount Value*/ - outcount = hcryp->CrypOutCount; - - if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size)) - { - /* Disable computation complete flag and errors interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Call output transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Output complete callback*/ - hcryp->OutCpltCallback(hcryp); -#else - /*Call legacy weak Output complete callback*/ - HAL_CRYP_OutCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - - else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) - { - /* Call Input transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - else /* Last block of payload < 128bit*/ - { - /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly - generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of - payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */ - - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (loopcounter < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - } -#endif /* AES */ - -} - - -/** - * @brief Sets the header phase in polling mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module(Header & HeaderSize) - * @param Timeout: Timeout value - * @retval state - */ -static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t loopcounter; - uint32_t size_in_bytes; - uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ - - /***************************** Header phase for GCM/GMAC or CCM *********************************/ - - if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) - { - size_in_bytes = hcryp->Init.HeaderSize * 4U; - } - else - { - size_in_bytes = hcryp->Init.HeaderSize; - } - - if (size_in_bytes != 0U) - { - -#if defined(CRYP) - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - if ((size_in_bytes % 16U) == 0U) - { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /* Wait for IFEM to be raised */ - if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - else - { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /* Wait for IFEM to be raised */ - if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - /* If the header size is a multiple of words */ - if ((size_in_bytes % 4U) == 0U) - { - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; - } - } - else - { - /* Enter last bytes, padded with zeroes */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; - hcryp->Instance->DIN = tmp; - loopcounter++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; - } - } - /* Wait for CCF IFEM to be raised */ - if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - /* Wait until the complete message has been processed */ - if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked & return error */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - -#else /* AES */ - - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - } - /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */ - if ((size_in_bytes % 16U) == 0U) - { - /* No padding */ - for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - } - else - { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - /* Write last complete words */ - for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - /* If the header size is a multiple of words */ - if ((size_in_bytes % 4U) == 0U) - { - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - } - else - { - /* Enter last bytes, padded with zeroes */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)]; - hcryp->Instance->DINR = tmp; - loopcounter++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - } - - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } -#endif /* End AES or CRYP */ - } - else - { -#if defined(AES) - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } -#endif /* AES */ - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Sets the header phase when using DMA in process - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module(Header & HeaderSize) - * @retval None - */ -static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp) -{ - __IO uint32_t count = 0U; - uint32_t loopcounter; - uint32_t headersize_in_bytes; - uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ - - /***************************** Header phase for GCM/GMAC or CCM *********************************/ - if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) - { - headersize_in_bytes = hcryp->Init.HeaderSize * 4U; - } - else - { - headersize_in_bytes = hcryp->Init.HeaderSize; - } - - if (headersize_in_bytes != 0U) - { - -#if defined(CRYP) - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - if ((headersize_in_bytes % 16U) == 0U) - { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /* Wait for IFEM to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); - } - } - else - { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /* Wait for IFEM to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - /* If the header size is a multiple of words */ - if ((headersize_in_bytes % 4U) == 0U) - { - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; - } - } - else - { - /* Enter last bytes, padded with zeroes */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; - hcryp->Instance->DIN = tmp; - loopcounter++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; - } - } - /* Wait for IFEM to be raised */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); - } - /* Wait until the complete message has been processed */ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); - -#else /* AES */ - - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } - if ((headersize_in_bytes % 16U) == 0U) - { - /* HeaderSize %4, no padding */ - for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U) - { - /* Write the input block in the data input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - } - else - { - /*Write header block in the IN FIFO without last block */ - for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U) - { - /* Write the Input block in the Data Input register */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - /* If the header size is a multiple of words */ - if ((headersize_in_bytes % 4U) == 0U) - { - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - } - else - { - /* Enter last bytes, padded with zeroes */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; - hcryp->Instance->DINR = tmp; - loopcounter++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - } - /*Wait on CCF flag*/ - count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; - do - { - count-- ; - if (count == 0U) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - } -#endif /* End AES or CRYP */ - } - else - { -#if defined(AES) - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/ - MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); - - /* Select header phase */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } -#endif /* AES */ - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Sets the header phase in interrupt mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module(Header & HeaderSize) - * @retval None - */ -static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) -{ - uint32_t loopcounter; -#if defined(AES) - uint32_t lastwordsize; - uint32_t npblb; -#endif - uint32_t headersize_in_bytes; - uint32_t tmp; - uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */ - - if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) - { - headersize_in_bytes = hcryp->Init.HeaderSize * 4U; - } - else - { - headersize_in_bytes = hcryp->Init.HeaderSize; - } - - /***************************** Header phase *********************************/ - -#if defined(CRYP) - if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI); - - /* Disable the CRYP peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Select payload phase once the header phase is performed */ - CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD); - - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - } - else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U) - - { - /* HeaderSize %4, no padding */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - else - { - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++) - { - hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - if ((headersize_in_bytes % 4U) == 0U) - { - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; - hcryp->CrypHeaderCount++; - } - } - else - { - /* Enter last bytes, padded with zeros */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; - hcryp->Instance->DIN = tmp; - loopcounter++; - hcryp->CrypHeaderCount++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; - hcryp->CrypHeaderCount++; - } - } - } -#else /* AES */ - - if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U)) - { - /* Set the phase */ - hcryp->Phase = CRYP_PHASE_PROCESS; - - /* Payload phase not supported in CCM AES2 */ - if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC) - { - /* Select payload phase once the header phase is performed */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD); - } - if (hcryp->Init.Algorithm == CRYP_AES_CCM) - { - /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */ - hcryp->CrypHeaderCount++; - } - /* Write the payload Input block in the IN FIFO */ - if (hcryp->Size == 0U) - { - /* Disable interrupts */ - __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - else if (hcryp->Size >= 16U) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - - if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) - { - /* Call the input data transfer complete callback */ -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); -#else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - else /* Size < 4 words : first block is the last block*/ - { - /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly - generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of - payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */ - - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (loopcounter < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0x0U; - loopcounter++; - } - } - } - else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U) - { - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++; - } - else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/ - { - /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++) - { - hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - hcryp->CrypHeaderCount++ ; - } - /* If the header size is a multiple of words */ - if ((headersize_in_bytes % 4U) == 0U) - { - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - hcryp->CrypHeaderCount++; - } - } - else - { - /* Enter last bytes, padded with zeros */ - tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); - tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)]; - hcryp->Instance->DINR = tmp; - loopcounter++; - hcryp->CrypHeaderCount++; - /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; - hcryp->CrypHeaderCount++; - } - } - } -#endif /* End AES or CRYP */ -} - - -/** - * @brief Workaround used for GCM/CCM mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param Timeout: specify Timeout value - * @retval None - */ -static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t lastwordsize; - uint32_t npblb; -#if defined(CRYP) - uint32_t iv1temp; - uint32_t temp[4] = {0}; - uint32_t temp2[4] = {0}; -#endif /* CRYP */ - uint32_t intermediate_data[4] = {0}; - uint32_t index; - - /* Compute the number of padding bytes in last block of payload */ - npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size); - - /* Number of valid words (lastwordsize) in last block */ - if ((npblb % 4U) == 0U) - { - lastwordsize = (16U - npblb) / 4U; - } - else - { - lastwordsize = ((16U - npblb) / 4U) + 1U; - } - -#if defined(CRYP) - - /* Workaround 2, case GCM encryption */ - if (hcryp->Init.Algorithm == CRYP_AES_GCM) - { - if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) - { - /*Workaround in order to properly compute authentication tags while doing - a GCM encryption with the last block of payload size inferior to 128 bits*/ - /* Disable CRYP to start the final phase */ - __HAL_CRYP_DISABLE(hcryp); - - /*Update CRYP_IV1R register and ALGOMODE*/ - hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U); - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR); - - /* Enable CRYP to start the final phase */ - __HAL_CRYP_ENABLE(hcryp); - } - /* Last block optionally pad the data with zeros*/ - for (index = 0; index < lastwordsize; index ++) - { - /* Write the last input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DIN = 0U; - index++; - } - /* Wait for OFNE flag to be raised */ - if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) - { - for (index = 0U; index < 4U; index++) - { - /* Read the output block from the output FIFO */ - intermediate_data[index] = hcryp->Instance->DOUT; - - /* Intermediate data buffer to be used in for the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; - hcryp->CrypOutCount++; - } - } - - if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT) - { - /*workaround in order to properly compute authentication tags while doing - a GCM encryption with the last block of payload size inferior to 128 bits*/ - /* Change the AES mode to GCM mode and Select Final phase */ - /* configured CHMOD GCM */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM); - - /* configured final phase */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - - if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B) - { - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= 0xFF000000U; - } - } - else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B) - { - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U); - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U); - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U); - } - } - else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B) - { - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16); - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16); - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16); - } - } - else /*CRYP_DATATYPE_1B*/ - { - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U); - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U); - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U); - } - } - for (index = 0U; index < lastwordsize; index ++) - { - /*Write the intermediate_data in the IN FIFO */ - hcryp->Instance->DIN = intermediate_data[index]; - } - while (index < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DIN = 0x0U; - index++; - } - /* Wait for OFNE flag to be raised */ - if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - - if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) - { - for (index = 0U; index < 4U; index++) - { - intermediate_data[index] = hcryp->Instance->DOUT; - } - } - } - } /* End of GCM encryption */ - else - { - /* Workaround 2, case CCM decryption, in order to properly compute - authentication tags while doing a CCM decryption with the last block - of payload size inferior to 128 bits*/ - - if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) - { - iv1temp = hcryp->Instance->CSGCMCCM7R; - - /* Disable CRYP to start the final phase */ - __HAL_CRYP_DISABLE(hcryp); - - temp[0] = hcryp->Instance->CSGCMCCM0R; - temp[1] = hcryp->Instance->CSGCMCCM1R; - temp[2] = hcryp->Instance->CSGCMCCM2R; - temp[3] = hcryp->Instance->CSGCMCCM3R; - - hcryp->Instance->IV1RR = iv1temp; - - /* Configured CHMOD CTR */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR); - - /* Enable CRYP to start the final phase */ - __HAL_CRYP_ENABLE(hcryp); - } - /* Last block optionally pad the data with zeros*/ - for (index = 0; index < lastwordsize; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* Pad the data with zeros to have a complete block */ - hcryp->Instance->DIN = 0U; - index++; - } - /* Wait for OFNE flag to be raised */ - if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - - if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) - { - for (index = 0U; index < 4U; index++) - { - /* Read the Output block from the Output FIFO */ - intermediate_data[index] = hcryp->Instance->DOUT; - - /*intermediate data buffer to be used in for the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; - hcryp->CrypOutCount++; - } - } - - if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT) - { - temp2[0] = hcryp->Instance->CSGCMCCM0R; - temp2[1] = hcryp->Instance->CSGCMCCM1R; - temp2[2] = hcryp->Instance->CSGCMCCM2R; - temp2[3] = hcryp->Instance->CSGCMCCM3R; - - /* configured CHMOD CCM */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM); - - /* configured Header phase */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER); - - /*set to zero the bits corresponding to the padded bits*/ - for (index = lastwordsize; index < 4U; index ++) - { - intermediate_data[index] = 0U; - } - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= 0xFF000000U; - } - for (index = 0U; index < 4U ; index ++) - { - intermediate_data[index] ^= temp[index]; - intermediate_data[index] ^= temp2[index]; - } - for (index = 0U; index < 4U; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DIN = intermediate_data[index] ; - } - - /* Wait for BUSY flag to be raised */ - if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - } - } /* End of CCM WKA*/ - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - -#else /* AES */ - - /*Workaround 2: case GCM encryption, during payload phase and before inserting - the last block of paylaod, which size is inferior to 128 bits */ - - if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) - { - /* configured CHMOD CTR */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR); - } - /* last block optionally pad the data with zeros*/ - for (index = 0U; index < lastwordsize; index ++) - { - /* Write the last Input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); - hcryp->CrypInCount++; - } - while (index < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - index++; - } - /* Wait for CCF flag to be raised */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - hcryp->State = HAL_CRYP_STATE_READY; - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - for (index = 0U; index < 4U; index++) - { - /* Read the Output block from the Output FIFO */ - intermediate_data[index] = hcryp->Instance->DOUTR; - - /*intermediate data buffer to be used in the workaround*/ - *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index]; - hcryp->CrypOutCount++; - } - - if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) - { - /* configured CHMOD GCM */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC); - - /* Select final phase */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); - - if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B) - { - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U; - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U; - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= 0xFF000000U; - } - } - else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B) - { - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U); - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U); - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U); - } - } - else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B) - { - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16); - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16); - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16); - } - } - else /*CRYP_DATATYPE_1B*/ - { - if ((npblb % 4U) == 1U) - { - intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U); - } - if ((npblb % 4U) == 2U) - { - intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U); - } - if ((npblb % 4U) == 3U) - { - intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U); - } - } - - /*Write the intermediate_data in the IN FIFO */ - for (index = 0U; index < lastwordsize; index ++) - { - hcryp->Instance->DINR = intermediate_data[index]; - } - while (index < 4U) - { - /* pad the data with zeros to have a complete block */ - hcryp->Instance->DINR = 0U; - index++; - } - /* Wait for CCF flag to be raised */ - if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); -#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) - /*Call registered error callback*/ - hcryp->ErrorCallback(hcryp); -#else - /*Call legacy weak error callback*/ - HAL_CRYP_ErrorCallback(hcryp); -#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - - for (index = 0U; index < 4U; index++) - { - intermediate_data[index] = hcryp->Instance->DOUTR; - } - }/*End of Workaround 2*/ -#endif /* End AES or CRYP */ -} - -#if defined (CRYP) - -/** - * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - return HAL_ERROR; - } - } - } - return HAL_OK; -} - -/** - * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - return HAL_ERROR; - } - } - } - return HAL_OK; -} - - -/** - * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - return HAL_ERROR; - } - } - } - return HAL_OK; -} - -#else /* AES */ - -/** - * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module. - * @param Timeout: Timeout duration. - * @retval HAL status - */ -static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - return HAL_ERROR; - } - } - } - return HAL_OK; -} - -#endif /* End AES or CRYP */ - - -/** - * @} - */ - - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_CRYP_MODULE_ENABLED */ - - -/** - * @} - */ -#endif /* TinyAES or CRYP*/ -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c deleted file mode 100644 index 05ec88c6..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cryp_ex.c +++ /dev/null @@ -1,680 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_cryp_ex.c - * @author MCD Application Team - * @brief Extended CRYP HAL module driver - * This file provides firmware functions to manage the following - * functionalities of CRYP extension peripheral: - * + Extended AES processing functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The CRYP extension HAL driver can be used as follows: - (#)After AES-GCM or AES-CCM Encryption/Decryption user can start following API - to get the authentication messages : - (##) HAL_CRYPEx_AESGCM_GenerateAuthTAG - (##) HAL_CRYPEx_AESCCM_GenerateAuthTAG - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (AES) || defined (CRYP) - -/** @defgroup CRYPEx CRYPEx - * @brief CRYP Extension HAL module driver. - * @{ - */ - - -#ifdef HAL_CRYP_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup CRYPEx_Private_Defines - * @{ - */ -#if defined(AES) -#define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */ -#define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */ -#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */ -#define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */ - -#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */ -#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions */ -#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption */ -#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions */ - -#else /* CRYP */ - -#define CRYP_PHASE_INIT 0x00000000U -#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 -#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 -#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH - -#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U -#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR -#endif /* End AES or CRYP */ - -#define CRYPEx_PHASE_PROCESS 0x02U /*!< CRYP peripheral is in processing phase */ -#define CRYPEx_PHASE_FINAL 0x03U /*!< CRYP peripheral is in final phase this is relevant only with CCM and GCM modes */ - -/* CTR0 information to use in CCM algorithm */ -#define CRYP_CCM_CTR0_0 0x07FFFFFFU -#define CRYP_CCM_CTR0_3 0xFFFFFF00U - - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - - - -/* Exported functions---------------------------------------------------------*/ -/** @addtogroup CRYPEx_Exported_Functions - * @{ - */ - -/** @defgroup CRYPEx_Exported_Functions_Group1 Extended AES processing functions - * @brief Extended processing functions. - * -@verbatim - ============================================================================== - ##### Extended AES processing functions ##### - ============================================================================== - [..] This section provides functions allowing to generate the authentication - TAG in Polling mode - (#)HAL_CRYPEx_AESGCM_GenerateAuthTAG - (#)HAL_CRYPEx_AESCCM_GenerateAuthTAG - they should be used after Encrypt/Decrypt operation. - -@endverbatim - * @{ - */ - - -/** - * @brief generate the GCM authentication TAG. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) -{ - uint32_t tickstart; - /* Assume first Init.HeaderSize is in words */ - uint64_t headerlength = (uint64_t)(hcryp->Init.HeaderSize) * 32U; /* Header length in bits */ - uint64_t inputlength = (uint64_t)hcryp->SizesSum * 8U; /* Input length in bits */ - uint32_t tagaddr = (uint32_t)AuthTag; - - /* Correct headerlength if Init.HeaderSize is actually in bytes */ - if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_BYTE) - { - headerlength /= 4U; - } - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if (hcryp->Phase == CRYPEx_PHASE_PROCESS) - { - /* Change the CRYP phase */ - hcryp->Phase = CRYPEx_PHASE_FINAL; - } - else /* Initialization phase has not been performed*/ - { - /* Disable the Peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Sequence error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - -#if defined(CRYP) - - /* Disable CRYP to start the final phase */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select final phase */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL); - - /*ALGODIR bit must be set to '0'.*/ - hcryp->Instance->CR &= ~CRYP_CR_ALGODIR; - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write the number of bits in header (64 bits) followed by the number of bits - in the payload */ - if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = 0U; - hcryp->Instance->DIN = __RBIT((uint32_t)(headerlength)); - hcryp->Instance->DIN = 0U; - hcryp->Instance->DIN = __RBIT((uint32_t)(inputlength)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = 0U; - hcryp->Instance->DIN = __REV((uint32_t)(headerlength)); - hcryp->Instance->DIN = 0U; - hcryp->Instance->DIN = __REV((uint32_t)(inputlength)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = 0U; - hcryp->Instance->DIN = __ROR((uint32_t)headerlength, 16U); - hcryp->Instance->DIN = 0U; - hcryp->Instance->DIN = __ROR((uint32_t)inputlength, 16U); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_32B) - { - hcryp->Instance->DIN = 0U; - hcryp->Instance->DIN = (uint32_t)(headerlength); - hcryp->Instance->DIN = 0U; - hcryp->Instance->DIN = (uint32_t)(inputlength); - } - else - { - /* Nothing to do */ - } - - /* Wait for OFNE flag to be raised */ - tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP Peripheral Clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - - /* Read the authentication TAG in the output FIFO */ - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; - -#else /* AES*/ - - /* Select final phase */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); - - /* Write the number of bits in header (64 bits) followed by the number of bits - in the payload */ - if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DINR = 0U; - hcryp->Instance->DINR = __RBIT((uint32_t)(headerlength)); - hcryp->Instance->DINR = 0U; - hcryp->Instance->DINR = __RBIT((uint32_t)(inputlength)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DINR = 0U; - hcryp->Instance->DINR = __REV((uint32_t)(headerlength)); - hcryp->Instance->DINR = 0U; - hcryp->Instance->DINR = __REV((uint32_t)(inputlength)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DINR = 0U; - hcryp->Instance->DINR = __ROR((uint32_t)headerlength, 16U); - hcryp->Instance->DINR = 0U; - hcryp->Instance->DINR = __ROR((uint32_t)inputlength, 16U); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_32B) - { - hcryp->Instance->DINR = 0U; - hcryp->Instance->DINR = (uint32_t)(headerlength); - hcryp->Instance->DINR = 0U; - hcryp->Instance->DINR = (uint32_t)(inputlength); - } - else - { - /* Nothing to do */ - } - /* Wait for CCF flag to be raised */ - tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - - /* Read the authentication TAG in the output FIFO */ - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; - - /* Clear CCF flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - -#endif /* End AES or CRYP */ - - /* Disable the peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - } - else - { - /* Busy error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; - return HAL_ERROR; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief AES CCM Authentication TAG generation. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains - * the configuration information for CRYP module - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) -{ - uint32_t tagaddr = (uint32_t)AuthTag; - uint32_t ctr0 [4] = {0}; - uint32_t ctr0addr = (uint32_t)ctr0; - uint32_t tickstart; - - if (hcryp->State == HAL_CRYP_STATE_READY) - { - /* Process locked */ - __HAL_LOCK(hcryp); - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if (hcryp->Phase == CRYPEx_PHASE_PROCESS) - { - /* Change the CRYP phase */ - hcryp->Phase = CRYPEx_PHASE_FINAL; - } - else /* Initialization phase has not been performed*/ - { - /* Disable the peripheral */ - __HAL_CRYP_DISABLE(hcryp); - - /* Sequence error code field */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE; - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - -#if defined(CRYP) - - /* Disable CRYP to start the final phase */ - __HAL_CRYP_DISABLE(hcryp); - - /* Select final phase & ALGODIR bit must be set to '0'. */ - MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH | CRYP_CR_ALGODIR, CRYP_PHASE_FINAL | CRYP_OPERATINGMODE_ENCRYPT); - - /* Enable the CRYP peripheral */ - __HAL_CRYP_ENABLE(hcryp); - - /* Write the counter block in the IN FIFO, CTR0 information from B0 - data has to be swapped according to the DATATYPE*/ - ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; - ctr0[1] = hcryp->Init.B0[1]; - ctr0[2] = hcryp->Init.B0[2]; - ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; - - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DIN = __REV(*(uint32_t *)(ctr0addr)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); - ctr0addr += 4U; - hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); - ctr0addr += 4U; - hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); - ctr0addr += 4U; - hcryp->Instance->DIN = __ROR(*(uint32_t *)(ctr0addr), 16U); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DIN = __RBIT(*(uint32_t *)(ctr0addr)); - } - else - { - hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); - ctr0addr += 4U; - hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); - ctr0addr += 4U; - hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); - ctr0addr += 4U; - hcryp->Instance->DIN = *(uint32_t *)(ctr0addr); - } - /* Wait for OFNE flag to be raised */ - tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral Clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - - /* Read the Auth TAG in the IN FIFO */ - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUT; - -#else /* AES */ - - /* Select final phase */ - MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL); - - /* Write the counter block in the IN FIFO, CTR0 information from B0 - data has to be swapped according to the DATATYPE*/ - if (hcryp->Init.DataType == CRYP_DATATYPE_8B) - { - ctr0[0] = (__REV(hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0); - ctr0[1] = __REV(hcryp->Init.B0[1]); - ctr0[2] = __REV(hcryp->Init.B0[2]); - ctr0[3] = (__REV(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DINR = __REV(*(uint32_t *)(ctr0addr)); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_16B) - { - ctr0[0] = (__ROR((hcryp->Init.B0[0]), 16U)& CRYP_CCM_CTR0_0); - ctr0[1] = __ROR((hcryp->Init.B0[1]), 16U); - ctr0[2] = __ROR((hcryp->Init.B0[2]), 16U); - ctr0[3] = (__ROR((hcryp->Init.B0[3]), 16U)& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); - ctr0addr += 4U; - hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); - ctr0addr += 4U; - hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); - ctr0addr += 4U; - hcryp->Instance->DINR = __ROR(*(uint32_t *)(ctr0addr), 16U); - } - else if (hcryp->Init.DataType == CRYP_DATATYPE_1B) - { - ctr0[0] = (__RBIT(hcryp->Init.B0[0])& CRYP_CCM_CTR0_0); - ctr0[1] = __RBIT(hcryp->Init.B0[1]); - ctr0[2] = __RBIT(hcryp->Init.B0[2]); - ctr0[3] = (__RBIT(hcryp->Init.B0[3])& CRYP_CCM_CTR0_3); - - hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); - ctr0addr += 4U; - hcryp->Instance->DINR = __RBIT(*(uint32_t *)(ctr0addr)); - } - else - { - ctr0[0] = (hcryp->Init.B0[0]) & CRYP_CCM_CTR0_0; - ctr0[1] = hcryp->Init.B0[1]; - ctr0[2] = hcryp->Init.B0[2]; - ctr0[3] = hcryp->Init.B0[3] & CRYP_CCM_CTR0_3; - - hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); - ctr0addr += 4U; - hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); - ctr0addr += 4U; - hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); - ctr0addr += 4U; - hcryp->Instance->DINR = *(uint32_t *)(ctr0addr); - } - - /* Wait for CCF flag to be raised */ - tickstart = HAL_GetTick(); - while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable the CRYP peripheral Clock */ - __HAL_CRYP_DISABLE(hcryp); - - /* Change state */ - hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT; - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - return HAL_ERROR; - } - } - } - - /* Read the authentication TAG in the output FIFO */ - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; - tagaddr += 4U; - *(uint32_t *)(tagaddr) = hcryp->Instance->DOUTR; - - /* Clear CCF Flag */ - __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); - -#endif /* End of AES || CRYP */ - - /* Change the CRYP peripheral state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hcryp); - - /* Disable CRYP */ - __HAL_CRYP_DISABLE(hcryp); - } - else - { - /* Busy error code field */ - hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY; - return HAL_ERROR; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -#if defined (AES) -/** @defgroup CRYPEx_Exported_Functions_Group2 Key Derivation functions - * @brief AutoKeyDerivation functions - * -@verbatim - ============================================================================== - ##### Key Derivation functions ##### - ============================================================================== - [..] This section provides functions allowing to Enable or Disable the - the AutoKeyDerivation parameter in CRYP_HandleTypeDef structure - These function are allowed only in TinyAES IP. - -@endverbatim - * @{ - */ - -/** - * @brief AES enable key derivation functions - * @param hcryp: pointer to a CRYP_HandleTypeDef structure. - * @retval None - */ -void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) -{ - if (hcryp->State == HAL_CRYP_STATE_READY) - { - hcryp->AutoKeyDerivation = ENABLE; - } - else - { - /* Busy error code field */ - hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY; - } -} -/** - * @brief AES disable key derivation functions - * @param hcryp: pointer to a CRYP_HandleTypeDef structure. - * @retval None - */ -void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) -{ - if (hcryp->State == HAL_CRYP_STATE_READY) - { - hcryp->AutoKeyDerivation = DISABLE; - } - else - { - /* Busy error code field */ - hcryp->ErrorCode = HAL_CRYP_ERROR_BUSY; - } -} - -/** - * @} - */ - -#endif /* AES */ -#endif /* HAL_CRYP_MODULE_ENABLED */ - -/** - * @} - */ -#endif /* TinyAES or CRYP*/ -/** - * @} - */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c deleted file mode 100644 index 99e112b7..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac.c +++ /dev/null @@ -1,1382 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dac.c - * @author MCD Application Team - * @brief DAC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Digital to Analog Converter (DAC) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### DAC Peripheral features ##### - ============================================================================== - [..] - *** DAC Channels *** - ==================== - [..] - STM32F7 devices integrates two 12-bit Digital Analog Converters that can - be used independently or simultaneously (dual mode): - (#) DAC channel1 with DAC_OUT1 (PA4) as output - (#) DAC channel2 with DAC_OUT2 (PA5) as output - - *** DAC Triggers *** - ==================== - [..] - Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE - and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. - [..] - Digital to Analog conversion can be triggered by: - (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9. - The used pin (GPIOx_Pin9) must be configured in input mode. - - (#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8 - (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...) - - (#) Software using DAC_TRIGGER_SOFTWARE - - *** DAC Buffer mode feature *** - =============================== - [..] - Each DAC channel integrates an output buffer that can be used to - reduce the output impedance, and to drive external loads directly - without having to add an external operational amplifier. - To enable, the output buffer use - sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; - [..] - (@) Refer to the device datasheet for more details about output - impedance value with and without output buffer. - - *** DAC wave generation feature *** - =================================== - [..] - Both DAC channels can be used to generate - (#) Noise wave - (#) Triangle wave - - *** DAC data format *** - ======================= - [..] - The DAC data format can be: - (#) 8-bit right alignment using DAC_ALIGN_8B_R - (#) 12-bit left alignment using DAC_ALIGN_12B_L - (#) 12-bit right alignment using DAC_ALIGN_12B_R - - *** DAC data value to voltage correspondence *** - ================================================ - [..] - The analog output voltage on each DAC channel pin is determined - by the following equation: - [..] - DAC_OUTx = VREF+ * DOR / 4095 - (+) with DOR is the Data Output Register - [..] - VREF+ is the input voltage reference (refer to the device datasheet) - [..] - e.g. To set DAC_OUT1 to 0.7V, use - (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V - - *** DMA requests *** - ===================== - [..] - A DMA request can be generated when an external trigger (but not a software trigger) - occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). - DMA1 requests are mapped as following: - (#) DAC channel1 mapped on DMA1 Stream5 channel7 which must be - already configured - (#) DAC channel2 mapped on DMA1 Stream6 channel7 which must be - already configured - - [..] - (@) For Dual mode and specific signal (Triangle and noise) generation please - refer to Extended Features Driver description - - ##### How to use this driver ##### - ============================================================================== - [..] - (+) DAC APB clock must be enabled to get write access to DAC - registers using HAL_DAC_Init() - (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. - (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. - (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions. - - - *** Polling mode IO operation *** - ================================= - [..] - (+) Start the DAC peripheral using HAL_DAC_Start() - (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. - (+) Stop the DAC peripheral using HAL_DAC_Stop() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue(). - (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer - HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - function is executed and user can add his own code by customization of function pointer - HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() - (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can - add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 - (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. - HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() - function is executed and user can add his own code by customization of function pointer - HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and - add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() - (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - Use Functions HAL_DAC_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. - (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. - (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. - (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. - (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. - (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. - (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. - (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. - (+) MspInitCallback : DAC MspInit. - (+) MspDeInitCallback : DAC MspdeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. It allows to reset following callbacks: - (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. - (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. - (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. - (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. - (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. - (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. - (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. - (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. - (+) MspInitCallback : DAC MspInit. - (+) MspDeInitCallback : DAC MspdeInit. - (+) All Callbacks - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the HAL_DAC_Init - and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit - or HAL_DAC_Init function. - - When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. - - *** DAC HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DAC HAL driver. - - (+) __HAL_DAC_ENABLE : Enable the DAC peripheral - (+) __HAL_DAC_DISABLE : Disable the DAC peripheral - (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags - (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status - - [..] - (@) You can refer to the DAC HAL driver header file for more useful macros - -@endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_DAC_MODULE_ENABLED -#if defined(DAC) - -/** @defgroup DAC DAC - * @brief DAC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions -------------------------------------------------------*/ - -/** @defgroup DAC_Exported_Functions DAC Exported Functions - * @{ - */ - -/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DAC. - (+) De-initialize the DAC. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DAC peripheral according to the specified parameters - * in the DAC_InitStruct and initialize the associated handle. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac) -{ - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - /* Check the parameters */ - assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - - if (hdac->State == HAL_DAC_STATE_RESET) - { -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - /* Init the DAC Callback settings */ - hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; - hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; - hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; - hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; - - hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; - hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; - hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; - hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; - - if (hdac->MspInitCallback == NULL) - { - hdac->MspInitCallback = HAL_DAC_MspInit; - } -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - /* Allocate lock resource and initialize it */ - hdac->Lock = HAL_UNLOCKED; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - /* Init the low level hardware */ - hdac->MspInitCallback(hdac); -#else - /* Init the low level hardware */ - HAL_DAC_MspInit(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - } - - /* Initialize the DAC state*/ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Set DAC error code to none */ - hdac->ErrorCode = HAL_DAC_ERROR_NONE; - - /* Initialize the DAC state*/ - hdac->State = HAL_DAC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Deinitialize the DAC peripheral registers to their default reset values. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac) -{ - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - if (hdac->MspDeInitCallback == NULL) - { - hdac->MspDeInitCallback = HAL_DAC_MspDeInit; - } - /* DeInit the low level hardware */ - hdac->MspDeInitCallback(hdac); -#else - /* DeInit the low level hardware */ - HAL_DAC_MspDeInit(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - /* Set DAC error code to none */ - hdac->ErrorCode = HAL_DAC_ERROR_NONE; - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the DAC MSP. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DAC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the DAC MSP. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DAC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion. - (+) Stop conversion. - (+) Start conversion and enable DMA transfer. - (+) Stop conversion and disable DMA transfer. - (+) Get result of conversion. - -@endverbatim - * @{ - */ - -/** - * @brief Enables DAC and starts conversion of channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel) -{ - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); - - if (Channel == DAC_CHANNEL_1) - { - /* Check if software trigger enabled */ - if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) - { - /* Enable the selected DAC software conversion */ - SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); - } - } - - else - { - /* Check if software trigger enabled */ - if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL))) - { - /* Enable the selected DAC software conversion*/ - SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); - } - } - - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables DAC and stop conversion of channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) -{ - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, Channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enables DAC and starts conversion of channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to DAC peripheral - * @param Alignment Specifies the data alignment for DAC channel. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected - * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected - * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length, - uint32_t Alignment) -{ - HAL_StatusTypeDef status; - uint32_t tmpreg; - - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_ALIGN(Alignment)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - if (Channel == DAC_CHANNEL_1) - { - /* Set the DMA transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - - /* Set the DMA half transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - - /* Set the DMA error callback for channel1 */ - hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - - /* Enable the selected DAC channel1 DMA request */ - SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); - - /* Case of use of channel 1 */ - switch (Alignment) - { - case DAC_ALIGN_12B_R: - /* Get DHR12R1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12R1; - break; - case DAC_ALIGN_12B_L: - /* Get DHR12L1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12L1; - break; - default: /* case DAC_ALIGN_8B_R */ - /* Get DHR8R1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR8R1; - break; - } - } - - else - { - /* Set the DMA transfer complete callback for channel2 */ - hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; - - /* Set the DMA half transfer complete callback for channel2 */ - hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; - - /* Set the DMA error callback for channel2 */ - hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; - - /* Enable the selected DAC channel2 DMA request */ - SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); - - /* Case of use of channel 2 */ - switch (Alignment) - { - case DAC_ALIGN_12B_R: - /* Get DHR12R2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12R2; - break; - case DAC_ALIGN_12B_L: - /* Get DHR12L2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12L2; - break; - default: /* case DAC_ALIGN_8B_R */ - /* Get DHR8R2 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR8R2; - break; - } - } - - if (Channel == DAC_CHANNEL_1) - { - /* Enable the DAC DMA underrun interrupt */ - __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - - /* Enable the DMA Stream */ - status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - } - - else - { - /* Enable the DAC DMA underrun interrupt */ - __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); - - /* Enable the DMA Stream */ - status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); - } - - - /* Process Unlocked */ - __HAL_UNLOCK(hdac); - - if (status == HAL_OK) - { - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, Channel); - } - else - { - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - } - - /* Return function status */ - return status; -} - -/** - * @brief Disables DAC and stop conversion of channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel) -{ - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL)); - - /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, Channel); - - /* Disable the DMA Stream */ - - /* Channel1 is used */ - if (Channel == DAC_CHANNEL_1) - { - /* Disable the DMA Stream */ - (void)HAL_DMA_Abort(hdac->DMA_Handle1); - - /* Disable the DAC DMA underrun interrupt */ - __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); - } - - else /* Channel2 is used for */ - { - /* Disable the DMA Stream */ - (void)HAL_DMA_Abort(hdac->DMA_Handle2); - - /* Disable the DAC DMA underrun interrupt */ - __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); - } - - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles DAC interrupt request - * This function uses the interruption of DMA - * underrun. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac) -{ - uint32_t itsource = hdac->Instance->CR; - uint32_t itflag = hdac->Instance->SR; - - if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1) - { - /* Check underrun flag of DAC channel 1 */ - if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to channel1 DMA underrun error */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1); - - /* Disable the selected DAC channel1 DMA request */ - __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1); - - /* Error callback */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->DMAUnderrunCallbackCh1(hdac); -#else - HAL_DAC_DMAUnderrunCallbackCh1(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - } - } - - - if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2) - { - /* Check underrun flag of DAC channel 2 */ - if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to channel2 DMA underrun error */ - SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2); - - /* Disable the selected DAC channel2 DMA request */ - __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2); - - /* Error callback */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->DMAUnderrunCallbackCh2(hdac); -#else - HAL_DACEx_DMAUnderrunCallbackCh2(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - } - } - -} - -/** - * @brief Set the specified data holding register value for DAC channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment Specifies the data alignment. - * This parameter can be one of the following values: - * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected - * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected - * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data Data to be loaded in the selected data holding register. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) -{ - __IO uint32_t tmp = 0UL; - - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_ALIGN(Alignment)); - assert_param(IS_DAC_DATA(Data)); - - tmp = (uint32_t)hdac->Instance; - if (Channel == DAC_CHANNEL_1) - { - tmp += DAC_DHR12R1_ALIGNMENT(Alignment); - } - - else - { - tmp += DAC_DHR12R2_ALIGNMENT(Alignment); - } - - - /* Set the DAC channel selected data holding register */ - *(__IO uint32_t *) tmp = Data; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Conversion complete callback in non-blocking mode for Channel1 - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief Error DAC callback for Channel1. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief DMA underrun DAC callback for channel1. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels. - (+) Set the specified data holding register value for DAC channel. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the last data output value of the selected DAC channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval The selected DAC channel data output value. - */ -uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel) -{ - uint32_t result; - - /* Check the DAC peripheral handle */ - assert_param(hdac != NULL); - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - - if (Channel == DAC_CHANNEL_1) - { - result = hdac->Instance->DOR1; - } - - else - { - result = hdac->Instance->DOR2; - } - - /* Returns the DAC channel data output register value */ - return result; -} - -/** - * @brief Configures the selected DAC channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param sConfig DAC configuration structure. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, - const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpreg1; - uint32_t tmpreg2; - - /* Check the DAC peripheral handle and channel configuration struct */ - if ((hdac == NULL) || (sConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check the DAC parameters */ - assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); - assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); - assert_param(IS_DAC_CHANNEL(Channel)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Get the DAC CR value */ - tmpreg1 = hdac->Instance->CR; - /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) - << (Channel & 0x10UL)); - /* Configure for the selected DAC channel: buffer output, trigger */ - /* Set TSELx and TENx bits according to DAC_Trigger value */ - /* Set BOFFx bit according to DAC_OutputBuffer value */ - tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); - /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << (Channel & 0x10UL); - /* Write to DAC CR */ - hdac->Instance->CR = tmpreg1; - /* Disable wave generation */ - CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL))); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DAC state. - (+) Check the DAC Errors. - -@endverbatim - * @{ - */ - -/** - * @brief return the DAC handle state - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL state - */ -HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac) -{ - /* Return DAC handle state */ - return hdac->State; -} - - -/** - * @brief Return the DAC error code - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval DAC Error Code - */ -uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac) -{ - return hdac->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DAC_Exported_Functions - * @{ - */ - -/** @addtogroup DAC_Exported_Functions_Group1 - * @{ - */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User DAC Callback - * To be used instead of the weak (overridden) predefined callback - * @note The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register - * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID - * @param hdac DAC handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID - * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID - * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID - * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID - * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID - * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID - * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID - * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID - * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID - * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID - * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID - * - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, - pDAC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - if (pCallback == NULL) - { - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - - if (hdac->State == HAL_DAC_STATE_READY) - { - switch (CallbackID) - { - case HAL_DAC_CH1_COMPLETE_CB_ID : - hdac->ConvCpltCallbackCh1 = pCallback; - break; - case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : - hdac->ConvHalfCpltCallbackCh1 = pCallback; - break; - case HAL_DAC_CH1_ERROR_ID : - hdac->ErrorCallbackCh1 = pCallback; - break; - case HAL_DAC_CH1_UNDERRUN_CB_ID : - hdac->DMAUnderrunCallbackCh1 = pCallback; - break; - - case HAL_DAC_CH2_COMPLETE_CB_ID : - hdac->ConvCpltCallbackCh2 = pCallback; - break; - case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : - hdac->ConvHalfCpltCallbackCh2 = pCallback; - break; - case HAL_DAC_CH2_ERROR_ID : - hdac->ErrorCallbackCh2 = pCallback; - break; - case HAL_DAC_CH2_UNDERRUN_CB_ID : - hdac->DMAUnderrunCallbackCh2 = pCallback; - break; - - case HAL_DAC_MSPINIT_CB_ID : - hdac->MspInitCallback = pCallback; - break; - case HAL_DAC_MSPDEINIT_CB_ID : - hdac->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hdac->State == HAL_DAC_STATE_RESET) - { - switch (CallbackID) - { - case HAL_DAC_MSPINIT_CB_ID : - hdac->MspInitCallback = pCallback; - break; - case HAL_DAC_MSPDEINIT_CB_ID : - hdac->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a User DAC Callback - * DAC Callback is redirected to the weak (overridden) predefined callback - * @note The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register - * callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID - * @param hdac DAC handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID - * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID - * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID - * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID - * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID - * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID - * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID - * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID - * @arg @ref HAL_DAC_MSPINIT_CB_ID DAC MSP Init Callback ID - * @arg @ref HAL_DAC_MSPDEINIT_CB_ID DAC MSP DeInit Callback ID - * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks - * @retval status - */ -HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - if (hdac->State == HAL_DAC_STATE_READY) - { - switch (CallbackID) - { - case HAL_DAC_CH1_COMPLETE_CB_ID : - hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; - break; - case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : - hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; - break; - case HAL_DAC_CH1_ERROR_ID : - hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; - break; - case HAL_DAC_CH1_UNDERRUN_CB_ID : - hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; - break; - - case HAL_DAC_CH2_COMPLETE_CB_ID : - hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; - break; - case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : - hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; - break; - case HAL_DAC_CH2_ERROR_ID : - hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; - break; - case HAL_DAC_CH2_UNDERRUN_CB_ID : - hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; - break; - - case HAL_DAC_MSPINIT_CB_ID : - hdac->MspInitCallback = HAL_DAC_MspInit; - break; - case HAL_DAC_MSPDEINIT_CB_ID : - hdac->MspDeInitCallback = HAL_DAC_MspDeInit; - break; - case HAL_DAC_ALL_CB_ID : - hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; - hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; - hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; - hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; - - hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; - hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; - hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; - hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; - - hdac->MspInitCallback = HAL_DAC_MspInit; - hdac->MspDeInitCallback = HAL_DAC_MspDeInit; - break; - default : - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hdac->State == HAL_DAC_STATE_RESET) - { - switch (CallbackID) - { - case HAL_DAC_MSPINIT_CB_ID : - hdac->MspInitCallback = HAL_DAC_MspInit; - break; - case HAL_DAC_MSPDEINIT_CB_ID : - hdac->MspDeInitCallback = HAL_DAC_MspDeInit; - break; - default : - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DAC_Private_Functions - * @{ - */ - -/** - * @brief DMA conversion complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ConvCpltCallbackCh1(hdac); -#else - HAL_DAC_ConvCpltCallbackCh1(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - hdac->State = HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - /* Conversion complete callback */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ConvHalfCpltCallbackCh1(hdac); -#else - HAL_DAC_ConvHalfCpltCallbackCh1(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA error callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ErrorCallbackCh1(hdac); -#else - HAL_DAC_ErrorCallbackCh1(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - hdac->State = HAL_DAC_STATE_READY; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DAC */ - -#endif /* HAL_DAC_MODULE_ENABLED */ -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c deleted file mode 100644 index 421c042a..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c +++ /dev/null @@ -1,516 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dac_ex.c - * @author MCD Application Team - * @brief Extended DAC HAL module driver. - * This file provides firmware functions to manage the extended - * functionalities of the DAC peripheral. - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - *** Signal generation operation *** - =================================== - [..] - (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. - (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. - - @endverbatim - ****************************************************************************** - */ - - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_DAC_MODULE_ENABLED - -#if defined(DAC) - -/** @defgroup DACEx DACEx - * @brief DAC Extended HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup DACEx_Exported_Functions DACEx Exported Functions - * @{ - */ - -/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions - * @brief Extended IO operation functions - * -@verbatim - ============================================================================== - ##### Extended features functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion. - (+) Stop conversion. - (+) Start conversion and enable DMA transfer. - (+) Stop conversion and disable DMA transfer. - (+) Get result of conversion. - (+) Get result of dual mode conversion. - -@endverbatim - * @{ - */ - - -/** - * @brief Enables DAC and starts conversion of both channels. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac) -{ - uint32_t tmp_swtrig = 0UL; - - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1); - __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2); - - /* Check if software trigger enabled */ - if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE) - { - tmp_swtrig |= DAC_SWTRIGR_SWTRIG1; - } - if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL))) - { - tmp_swtrig |= DAC_SWTRIGR_SWTRIG2; - } - /* Enable the selected DAC software conversion*/ - SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disables DAC and stop conversion of both channels. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) -{ - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - - /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1); - __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Enable or disable the selected DAC channel wave generation. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude Select max triangle amplitude. - * This parameter can be one of the following values: - * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 - * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 - * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 - * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 - * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 - * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 - * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 - * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 - * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 - * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 - * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 - * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) -{ - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the triangle wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), - (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL)); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enable or disable the selected DAC channel wave generation. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Channel The selected DAC channel. - * This parameter can be one of the following values: - * @arg DAC_CHANNEL_1: DAC Channel1 selected - * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude Unmask DAC channel LFSR for noise wave generation. - * This parameter can be one of the following values: - * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation - * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation - * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) -{ - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(Channel)); - assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the noise wave generation for the selected DAC channel */ - MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), - (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL)); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @param Alignment Specifies the data alignment for dual channel DAC. - * This parameter can be one of the following values: - * DAC_ALIGN_8B_R: 8bit right data alignment selected - * DAC_ALIGN_12B_L: 12bit left data alignment selected - * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1 Data for DAC Channel1 to be loaded in the selected data holding register. - * @param Data2 Data for DAC Channel2 to be loaded in the selected data holding register. - * @note In dual mode, a unique register access is required to write in both - * DAC channels at the same time. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) -{ - uint32_t data; - uint32_t tmp; - - /* Check the DAC peripheral handle */ - if (hdac == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DAC_ALIGN(Alignment)); - assert_param(IS_DAC_DATA(Data1)); - assert_param(IS_DAC_DATA(Data2)); - - /* Calculate and set dual DAC data holding register value */ - if (Alignment == DAC_ALIGN_8B_R) - { - data = ((uint32_t)Data2 << 8U) | Data1; - } - else - { - data = ((uint32_t)Data2 << 16U) | Data1; - } - - tmp = (uint32_t)hdac->Instance; - tmp += DAC_DHR12RD_ALIGNMENT(Alignment); - - /* Set the dual DAC selected data holding register */ - *(__IO uint32_t *)tmp = data; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Conversion complete callback in non-blocking mode for Channel2. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief Conversion half DMA transfer callback in non-blocking mode for Channel2. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief Error DAC callback for Channel2. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file - */ -} - -/** - * @brief DMA underrun DAC callback for Channel2. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdac); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file - */ -} - - - -/** - * @} - */ - -/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Set the specified data holding register value for DAC channel. - -@endverbatim - * @{ - */ - - -/** - * @brief Return the last data output value of the selected DAC channel. - * @param hdac pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval The selected DAC channel data output value. - */ -uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac) -{ - uint32_t tmp = 0UL; - - tmp |= hdac->Instance->DOR1; - - tmp |= hdac->Instance->DOR2 << 16UL; - - /* Returns the DAC channel data output register value */ - return tmp; -} - - -/** - * @} - */ -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DACEx_Private_Functions DACEx private functions - * @brief Extended private functions - * @{ - */ - - -/** - * @brief DMA conversion complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ConvCpltCallbackCh2(hdac); -#else - HAL_DACEx_ConvCpltCallbackCh2(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - hdac->State = HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - /* Conversion complete callback */ -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ConvHalfCpltCallbackCh2(hdac); -#else - HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA error callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - -#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - hdac->ErrorCallbackCh2(hdac); -#else - HAL_DACEx_ErrorCallbackCh2(hdac); -#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ - - hdac->State = HAL_DAC_STATE_READY; -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DAC */ - -#endif /* HAL_DAC_MODULE_ENABLED */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c deleted file mode 100644 index b59b805f..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c +++ /dev/null @@ -1,1269 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dcmi.c - * @author MCD Application Team - * @brief DCMI HAL module driver - * This file provides firmware functions to manage the following - * functionalities of the Digital Camera Interface (DCMI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Error functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The sequence below describes how to use this driver to capture image - from a camera module connected to the DCMI Interface. - This sequence does not take into account the configuration of the - camera module, which should be made before to configure and enable - the DCMI to capture images. - - (#) Program the required configuration through following parameters: - horizontal and vertical polarity, pixel clock polarity, Capture Rate, - Synchronization Mode, code of the frame delimiter and data width - using HAL_DCMI_Init() function. - - (#) Configure the selected DMA stream to transfer Data from DCMI DR - register to the destination memory buffer. - - (#) Program the required configuration through following parameters: - DCMI mode, destination memory Buffer address and the data length - and enable capture using HAL_DCMI_Start_DMA() function. - - (#) Optionally, configure and Enable the CROP feature to select a rectangular - window from the received image using HAL_DCMI_ConfigCrop() - and HAL_DCMI_EnableCrop() functions - - (#) The capture can be stopped using HAL_DCMI_Stop() function. - - (#) To control DCMI state you can use the function HAL_DCMI_GetState(). - - *** DCMI HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DCMI HAL driver. - - (+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral. - (+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral. - (+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags. - (+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags. - (+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts. - (+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts. - (+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not. - - [..] - (@) You can refer to the DCMI HAL driver header file for more useful macros - - *** Callback registration *** - ============================= - - The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use functions HAL_DCMI_RegisterCallback() to register a user callback. - - Function HAL_DCMI_RegisterCallback() allows to register following callbacks: - (+) FrameEventCallback : callback for DCMI Frame Event. - (+) VsyncEventCallback : callback for DCMI Vsync Event. - (+) LineEventCallback : callback for DCMI Line Event. - (+) ErrorCallback : callback for DCMI error detection. - (+) MspInitCallback : callback for DCMI MspInit. - (+) MspDeInitCallback : callback for DCMI MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. - HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the callback ID. - This function allows to reset following callbacks: - (+) FrameEventCallback : callback for DCMI Frame Event. - (+) VsyncEventCallback : callback for DCMI Vsync Event. - (+) LineEventCallback : callback for DCMI Line Event. - (+) ErrorCallback : callback for DCMI error. - (+) MspInitCallback : callback for DCMI MspInit. - (+) MspDeInitCallback : callback for DCMI MspDeInit. - - By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples FrameEventCallback(), HAL_DCMI_ErrorCallback(). - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init - and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_DCMI_RegisterCallback before calling HAL_DCMI_DeInit - or HAL_DCMI_Init function. - - When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -#ifdef HAL_DCMI_MODULE_ENABLED -#if defined (DCMI) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -/** @defgroup DCMI DCMI - * @brief DCMI HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup DCMI_Private_Constants DCMI Private Constants - * @{ - */ - -/** @defgroup DCMI_Stop_TimeOut DCMI Stop Time Out - * @{ - */ -#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */ -/** - * @} - */ - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup DCMI_Private_Functions DCMI Private Functions - * @{ - */ -static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma); -static void DCMI_DMAError(DMA_HandleTypeDef *hdma); - -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup DCMI_Exported_Functions DCMI Exported Functions - * @{ - */ - -/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DCMI - (+) De-initialize the DCMI - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the DCMI according to the specified - * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) -{ - /* Check the DCMI peripheral state */ - if (hdcmi == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance)); - assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity)); - assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity)); - assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity)); - assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode)); - assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate)); - assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode)); - assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode)); - -#ifdef DCMI_CR_BSM - assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode)); - assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart)); - assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode)); - assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart)); -#endif - - if (hdcmi->State == HAL_DCMI_STATE_RESET) - { - /* Init the DCMI Callback settings */ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - /* Reset callback pointers to the weak predefined callbacks */ - hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ - hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ - hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ - hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hdcmi->MspInitCallback == NULL) - { - /* Legacy weak MspInit Callback */ - hdcmi->MspInitCallback = HAL_DCMI_MspInit; - } - /* Initialize the low level hardware (MSP) */ - hdcmi->MspInitCallback(hdcmi); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_DCMI_MspInit(hdcmi); -#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */ - } - - /* Change the DCMI state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - -#ifdef DCMI_CR_BSM - if (hdcmi->Init.ExtendedDataMode != DCMI_EXTEND_DATA_8B) - { - /* Byte select mode must be programmed to the reset value if the extended mode - is not set to 8-bit data capture on every pixel clock */ - hdcmi->Init.ByteSelectMode = DCMI_BSM_ALL; - } -#endif - /* Configures the HS, VS, DE and PC polarity */ -#ifdef DCMI_CR_BSM - hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \ - DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG | \ - DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS | \ - DCMI_CR_LSM | DCMI_CR_OELS); - - hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \ - hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \ - hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \ - hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode | \ - hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode | \ - hdcmi->Init.LineSelectStart); -#else - hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 | \ - DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG); - - hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \ - hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \ - hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \ - hdcmi->Init.JPEGMode); -#endif - - if (hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED) - { - hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) | \ - ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos) | \ - ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) | \ - ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos)); - - } - - /* Enable the Line, Vsync, Error and Overrun interrupts */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); - - /* Update error code */ - hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; - - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Deinitializes the DCMI peripheral registers to their default reset - * values. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi) -{ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - if (hdcmi->MspDeInitCallback == NULL) - { - hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; - } - /* De-Initialize the low level hardware (MSP) */ - hdcmi->MspDeInitCallback(hdcmi); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_DCMI_MspDeInit(hdcmi); -#endif /* (USE_HAL_DCMI_REGISTER_CALLBACKS) */ - - /* Update error code */ - hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE; - - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @brief Initializes the DCMI MSP. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the DCMI MSP. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ -/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure destination address and data length and - Enables DCMI DMA request and enables DCMI capture - (+) Stop the DCMI capture. - (+) Handles DCMI interrupt request. - -@endverbatim - * @{ - */ - -/** - * @brief Enables DCMI DMA request and enables DCMI capture - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param DCMI_Mode DCMI capture mode snapshot or continuous grab. - * @param pData The destination memory Buffer address (LCD Frame buffer). - * @param Length The length of capture to be transferred. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef *hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) -{ - uint32_t tmp_length = Length; - /* Initialize the second memory address */ - uint32_t SecondMemAddress; - - /* Check function parameters */ - assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode)); - - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Enable DCMI by setting DCMIEN bit */ - __HAL_DCMI_ENABLE(hdcmi); - - /* Configure the DCMI Mode */ - hdcmi->Instance->CR &= ~(DCMI_CR_CM); - hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode); - - /* Set the DMA memory0 conversion complete callback */ - hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt; - - /* Set the DMA error callback */ - hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError; - - /* Set the dma abort callback */ - hdcmi->DMA_Handle->XferAbortCallback = NULL; - - /* Reset transfer counters value */ - hdcmi->XferCount = 0; - hdcmi->XferTransferNumber = 0; - hdcmi->XferSize = 0; - hdcmi->pBuffPtr = 0; - - if (tmp_length <= 0xFFFFU) - { - /* Enable the DMA Stream */ - if (HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, tmp_length) != HAL_OK) - { - /* Set Error Code */ - hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA; - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - /* Release Lock */ - __HAL_UNLOCK(hdcmi); - /* Return function status */ - return HAL_ERROR; - } - } - else /* DCMI_DOUBLE_BUFFER Mode */ - { - /* Set the DMA memory1 conversion complete callback */ - hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt; - - /* Initialize transfer parameters */ - hdcmi->XferCount = 1; - hdcmi->XferSize = tmp_length; - hdcmi->pBuffPtr = pData; - - /* Get the number of buffer */ - while (hdcmi->XferSize > 0xFFFFU) - { - hdcmi->XferSize = (hdcmi->XferSize / 2U); - hdcmi->XferCount = hdcmi->XferCount * 2U; - } - - /* Update DCMI counter and transfer number*/ - hdcmi->XferCount = (hdcmi->XferCount - 2U); - hdcmi->XferTransferNumber = hdcmi->XferCount; - - /* Update second memory address */ - SecondMemAddress = (uint32_t)(pData + (4U * hdcmi->XferSize)); - - /* Start DMA multi buffer transfer */ - if (HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize) != HAL_OK) - { - /* Set Error Code */ - hdcmi->ErrorCode = HAL_DCMI_ERROR_DMA; - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - /* Release Lock */ - __HAL_UNLOCK(hdcmi); - /* Return function status */ - return HAL_ERROR; - } - } - - /* Enable Capture */ - hdcmi->Instance->CR |= DCMI_CR_CAPTURE; - - /* Release Lock */ - __HAL_UNLOCK(hdcmi); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Disable DCMI DMA request and Disable DCMI capture - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef *hdcmi) -{ - uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U); - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Disable Capture */ - hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE); - - /* Check if the DCMI capture effectively disabled */ - do - { - count-- ; - if (count == 0U) - { - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - - status = HAL_TIMEOUT; - break; - } - } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); - - /* Disable the DCMI */ - __HAL_DCMI_DISABLE(hdcmi); - - /* Disable the DMA */ - (void)HAL_DMA_Abort(hdcmi->DMA_Handle); - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Return function status */ - return status; -} - -/** - * @brief Suspend DCMI capture - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef *hdcmi) -{ - uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock / 8U / 1000U); - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdcmi); - - if (hdcmi->State == HAL_DCMI_STATE_BUSY) - { - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_SUSPENDED; - - /* Disable Capture */ - hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE); - - /* Check if the DCMI capture effectively disabled */ - do - { - count-- ; - if (count == 0U) - { - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_READY; - - status = HAL_TIMEOUT; - break; - } - } while ((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0U); - } - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Return function status */ - return status; -} - -/** - * @brief Resume DCMI capture - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef *hdcmi) -{ - /* Process locked */ - __HAL_LOCK(hdcmi); - - if (hdcmi->State == HAL_DCMI_STATE_SUSPENDED) - { - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Enable Capture */ - hdcmi->Instance->CR |= DCMI_CR_CAPTURE; - } - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handles DCMI interrupt request. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for the DCMI. - * @retval None - */ -void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi) -{ - uint32_t isr_value = READ_REG(hdcmi->Instance->MISR); - - /* Synchronization error interrupt management *******************************/ - if ((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI) - { - /* Clear the Synchronization error flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI); - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_ERROR; - - /* Set the synchronization error callback */ - hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; - - /* Abort the DMA Transfer */ - if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK) - { - DCMI_DMAError(hdcmi->DMA_Handle); - } - } - /* Overflow interrupt management ********************************************/ - if ((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI) - { - /* Clear the Overflow flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI); - - /* Update error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR; - - /* Change DCMI state */ - hdcmi->State = HAL_DCMI_STATE_ERROR; - - /* Set the overflow callback */ - hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError; - - /* Abort the DMA Transfer */ - if (HAL_DMA_Abort_IT(hdcmi->DMA_Handle) != HAL_OK) - { - DCMI_DMAError(hdcmi->DMA_Handle); - } - } - /* Line Interrupt management ************************************************/ - if ((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI) - { - /* Clear the Line interrupt flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI); - - /* Line interrupt Callback */ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - /*Call registered DCMI line event callback*/ - hdcmi->LineEventCallback(hdcmi); -#else - HAL_DCMI_LineEventCallback(hdcmi); -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ - } - /* VSYNC interrupt management ***********************************************/ - if ((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI) - { - /* Clear the VSYNC flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI); - - /* VSYNC Callback */ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - /*Call registered DCMI vsync event callback*/ - hdcmi->VsyncEventCallback(hdcmi); -#else - HAL_DCMI_VsyncEventCallback(hdcmi); -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ - } - /* FRAME interrupt management ***********************************************/ - if ((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI) - { - /* When snapshot mode, disable Vsync, Error and Overrun interrupts */ - if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) - { - /* Disable the Line, Vsync, Error and Overrun interrupts */ - __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR); - } - - /* Disable the Frame interrupt */ - __HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME); - - /* Clear the End of Frame flag */ - __HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI); - - /* Frame Callback */ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - /*Call registered DCMI frame event callback*/ - hdcmi->FrameEventCallback(hdcmi); -#else - HAL_DCMI_FrameEventCallback(hdcmi); -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Error DCMI callback. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Line Event callback. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_LineEventCallback could be implemented in the user file - */ -} - -/** - * @brief VSYNC Event callback. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_VsyncEventCallback could be implemented in the user file - */ -} - -/** - * @brief Frame Event callback. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval None - */ -__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdcmi); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DCMI_FrameEventCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== -[..] This section provides functions allowing to: - (+) Configure the CROP feature. - (+) Enable/Disable the CROP feature. - (+) Set embedded synchronization delimiters unmasks. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the DCMI CROP coordinate. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param YSize DCMI Line number - * @param XSize DCMI Pixel per line - * @param X0 DCMI window X offset - * @param Y0 DCMI window Y offset - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, - uint32_t YSize) -{ - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_DCMI_WINDOW_COORDINATE(X0)); - assert_param(IS_DCMI_WINDOW_HEIGHT(Y0)); - assert_param(IS_DCMI_WINDOW_COORDINATE(XSize)); - assert_param(IS_DCMI_WINDOW_COORDINATE(YSize)); - - /* Configure CROP */ - hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos)); - hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos)); - - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @brief Disable the Crop feature. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi) -{ - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Disable DCMI Crop feature */ - hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP; - - /* Change the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @brief Enable the Crop feature. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi) -{ - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Enable DCMI Crop feature */ - hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP; - - /* Change the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @brief Set embedded synchronization delimiters unmasks. - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @param SyncUnmask pointer to a DCMI_SyncUnmaskTypeDef structure that contains - * the embedded synchronization delimiters unmasks. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask) -{ - /* Process Locked */ - __HAL_LOCK(hdcmi); - - /* Lock the DCMI peripheral state */ - hdcmi->State = HAL_DCMI_STATE_BUSY; - - /* Write DCMI embedded synchronization unmask register */ - hdcmi->Instance->ESUR = (((uint32_t)SyncUnmask->FrameStartUnmask) | \ - ((uint32_t)SyncUnmask->LineStartUnmask << DCMI_ESUR_LSU_Pos) | \ - ((uint32_t)SyncUnmask->LineEndUnmask << DCMI_ESUR_LEU_Pos) | \ - ((uint32_t)SyncUnmask->FrameEndUnmask << DCMI_ESUR_FEU_Pos)); - - /* Change the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdcmi); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DCMI state. - (+) Get the specific DCMI error flag. - -@endverbatim - * @{ - */ - -/** - * @brief Return the DCMI state - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval HAL state - */ -HAL_DCMI_StateTypeDef HAL_DCMI_GetState(const DCMI_HandleTypeDef *hdcmi) -{ - return hdcmi->State; -} - -/** - * @brief Return the DCMI error code - * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains - * the configuration information for DCMI. - * @retval DCMI Error Code - */ -uint32_t HAL_DCMI_GetError(const DCMI_HandleTypeDef *hdcmi) -{ - return hdcmi->ErrorCode; -} - -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User DCMI Callback - * To be used instead of the weak predefined callback - * @param hdcmi DCMI handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID - * @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID - * @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID - * @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID - * @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, - pDCMI_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - else - { - if (hdcmi->State == HAL_DCMI_STATE_READY) - { - switch (CallbackID) - { - case HAL_DCMI_FRAME_EVENT_CB_ID : - hdcmi->FrameEventCallback = pCallback; - break; - - case HAL_DCMI_VSYNC_EVENT_CB_ID : - hdcmi->VsyncEventCallback = pCallback; - break; - - case HAL_DCMI_LINE_EVENT_CB_ID : - hdcmi->LineEventCallback = pCallback; - break; - - case HAL_DCMI_ERROR_CB_ID : - hdcmi->ErrorCallback = pCallback; - break; - - case HAL_DCMI_MSPINIT_CB_ID : - hdcmi->MspInitCallback = pCallback; - break; - - case HAL_DCMI_MSPDEINIT_CB_ID : - hdcmi->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hdcmi->State == HAL_DCMI_STATE_RESET) - { - switch (CallbackID) - { - case HAL_DCMI_MSPINIT_CB_ID : - hdcmi->MspInitCallback = pCallback; - break; - - case HAL_DCMI_MSPDEINIT_CB_ID : - hdcmi->MspDeInitCallback = pCallback; - break; - - default : - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Unregister a DCMI Callback - * DCMI callback is redirected to the weak predefined callback - * @param hdcmi DCMI handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_DCMI_LINE_EVENT_CB_ID Line Event callback ID - * @arg @ref HAL_DCMI_FRAME_EVENT_CB_ID Frame Event callback ID - * @arg @ref HAL_DCMI_VSYNC_EVENT_CB_ID Vsync Event callback ID - * @arg @ref HAL_DCMI_ERROR_CB_ID Error callback ID - * @arg @ref HAL_DCMI_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_DCMI_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hdcmi->State == HAL_DCMI_STATE_READY) - { - switch (CallbackID) - { - case HAL_DCMI_FRAME_EVENT_CB_ID : - hdcmi->FrameEventCallback = HAL_DCMI_FrameEventCallback; /* Legacy weak FrameEventCallback */ - break; - - case HAL_DCMI_VSYNC_EVENT_CB_ID : - hdcmi->VsyncEventCallback = HAL_DCMI_VsyncEventCallback; /* Legacy weak VsyncEventCallback */ - break; - - case HAL_DCMI_LINE_EVENT_CB_ID : - hdcmi->LineEventCallback = HAL_DCMI_LineEventCallback; /* Legacy weak LineEventCallback */ - break; - - case HAL_DCMI_ERROR_CB_ID : - hdcmi->ErrorCallback = HAL_DCMI_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_DCMI_MSPINIT_CB_ID : - hdcmi->MspInitCallback = HAL_DCMI_MspInit; - break; - - case HAL_DCMI_MSPDEINIT_CB_ID : - hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; - break; - - default : - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hdcmi->State == HAL_DCMI_STATE_RESET) - { - switch (CallbackID) - { - case HAL_DCMI_MSPINIT_CB_ID : - hdcmi->MspInitCallback = HAL_DCMI_MspInit; - break; - - case HAL_DCMI_MSPDEINIT_CB_ID : - hdcmi->MspDeInitCallback = HAL_DCMI_MspDeInit; - break; - - default : - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update the error code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DCMI_Private_Functions DCMI Private Functions - * @{ - */ -/** - * @brief DMA conversion complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp ; - - DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdcmi->XferCount != 0U) - { - /* Update memory 0 address location */ - tmp = ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR) & DMA_SxCR_CT); - if (((hdcmi->XferCount % 2U) == 0U) && (tmp != 0U)) - { - tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR; - (void)HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U * hdcmi->XferSize)), MEMORY0); - hdcmi->XferCount--; - } - /* Update memory 1 address location */ - else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U) - { - tmp = ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR; - (void)HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8U * hdcmi->XferSize)), MEMORY1); - hdcmi->XferCount--; - } - else - { - /* Nothing to do */ - } - } - /* Update memory 0 address location */ - else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) != 0U) - { - ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M0AR = hdcmi->pBuffPtr; - } - /* Update memory 1 address location */ - else if ((((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->CR & DMA_SxCR_CT) == 0U) - { - tmp = hdcmi->pBuffPtr; - ((DMA_Stream_TypeDef *)(hdcmi->DMA_Handle->Instance))->M1AR = (tmp + (4U * hdcmi->XferSize)); - hdcmi->XferCount = hdcmi->XferTransferNumber; - } - else - { - /* Nothing to do */ - } - - /* Check if the frame is transferred */ - if (hdcmi->XferCount == hdcmi->XferTransferNumber) - { - /* Enable the Frame interrupt */ - __HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME); - - /* When snapshot mode, set dcmi state to ready */ - if ((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT) - { - hdcmi->State = HAL_DCMI_STATE_READY; - } - } -} - -/** - * @brief DMA error callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void DCMI_DMAError(DMA_HandleTypeDef *hdma) -{ - DCMI_HandleTypeDef *hdcmi = (DCMI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE) - { - /* Initialize the DCMI state*/ - hdcmi->State = HAL_DCMI_STATE_READY; - - /* Set DCMI Error Code */ - hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA; - } - - /* DCMI error Callback */ -#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1) - /*Call registered DCMI error callback*/ - hdcmi->ErrorCallback(hdcmi); -#else - HAL_DCMI_ErrorCallback(hdcmi); -#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */ - -} - -/** - * @} - */ -#endif /* DCMI */ -#endif /* HAL_DCMI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c deleted file mode 100644 index 5ef42bc0..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi_ex.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dcmi_ex.c - * @author MCD Application Team - * @brief Empty file; This file is no longer used to handle the Black&White - * feature. Its content is now moved to common files - * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within - * this family. It's just kept for compatibility reasons. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c deleted file mode 100644 index aea56ac2..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dfsdm.c +++ /dev/null @@ -1,3549 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dfsdm.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Digital Filter for Sigma-Delta Modulators - * (DFSDM) peripherals: - * + Initialization and configuration of channels and filters - * + Regular channels configuration - * + Injected channels configuration - * + Regular/Injected Channels DMA Configuration - * + Interrupts and flags management - * + Analog watchdog feature - * + Short-circuit detector feature - * + Extremes detector feature - * + Clock absence detector feature - * + Break generation on analog watchdog or short-circuit event - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - *** Channel initialization *** - ============================== - [..] - (#) User has first to initialize channels (before filters initialization). - (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() : - (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE(). - (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). - (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init(). - (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (#) Configure the output clock, input, serial interface, analog watchdog, - offset and data right bit shift parameters for this channel using the - HAL_DFSDM_ChannelInit() function. - - *** Channel clock absence detector *** - ====================================== - [..] - (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or - HAL_DFSDM_ChannelCkabStart_IT(). - (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock - absence. - (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if - clock absence is detected. - (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or - HAL_DFSDM_ChannelCkabStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used - for all channels because the channels are sharing the same interrupt. - (#) Please note also that in interrupt mode, if clock absence detector is - stopped for one channel, interrupt will be disabled for all channels. - - *** Channel short circuit detector *** - ====================================== - [..] - (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or - or HAL_DFSDM_ChannelScdStart_IT(). - (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short - circuit. - (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if - short circuit is detected. - (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or - or HAL_DFSDM_ChannelScdStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used - for all channels because the channels are sharing the same interrupt. - (#) Please note also that in interrupt mode, if short circuit detector is - stopped for one channel, interrupt will be disabled for all channels. - - *** Channel analog watchdog value *** - ===================================== - [..] - (#) Get analog watchdog filter value of a channel using - HAL_DFSDM_ChannelGetAwdValue(). - - *** Channel offset value *** - ===================================== - [..] - (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset(). - - *** Filter initialization *** - ============================= - [..] - (#) After channel initialization, user has to init filters. - (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() : - (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - Please note that DFSDMz_FLT0 global interrupt could be already - enabled if interrupt is used for channel. - (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it - with DFSDMz filter handle using __HAL_LINKDMA(). - (#) Configure the regular conversion, injected conversion and filter - parameters for this filter using the HAL_DFSDM_FilterInit() function. - - *** Filter regular channel conversion *** - ========================================= - [..] - (#) Select regular channel and enable/disable continuous mode using - HAL_DFSDM_FilterConfigRegChannel(). - (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(), - HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or - HAL_DFSDM_FilterRegularMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect - the end of regular conversion. - (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called - at the end of regular conversion. - (#) Get value of regular conversion and corresponding channel using - HAL_DFSDM_FilterGetRegularValue(). - (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and - HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that - HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA - circular mode. - (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(), - HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA(). - - *** Filter injected channels conversion *** - =========================================== - [..] - (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel(). - (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(), - HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or - HAL_DFSDM_FilterInjectedMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect - the end of injected conversion. - (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called - at the end of injected conversion. - (#) Get value of injected conversion and corresponding channel using - HAL_DFSDM_FilterGetInjectedValue(). - (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and - HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that - HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA - circular mode. - (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(), - HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA(). - - *** Filter analog watchdog *** - ============================== - [..] - (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT(). - (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs. - (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT(). - - *** Filter extreme detector *** - =============================== - [..] - (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart(). - (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue(). - (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue(). - (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop(). - - *** Filter conversion time *** - ============================== - [..] - (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue(). - - *** Callback registration *** - ============================= - [..] - The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use functions HAL_DFSDM_Channel_RegisterCallback(), - HAL_DFSDM_Filter_RegisterCallback() or - HAL_DFSDM_Filter_RegisterAwdCallback() to register a user callback. - - [..] - Function HAL_DFSDM_Channel_RegisterCallback() allows to register - following callbacks: - (+) CkabCallback : DFSDM channel clock absence detection callback. - (+) ScdCallback : DFSDM channel short circuit detection callback. - (+) MspInitCallback : DFSDM channel MSP init callback. - (+) MspDeInitCallback : DFSDM channel MSP de-init callback. - [..] - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Function HAL_DFSDM_Filter_RegisterCallback() allows to register - following callbacks: - (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback. - (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback. - (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback. - (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback. - (+) ErrorCallback : DFSDM filter error callback. - (+) MspInitCallback : DFSDM filter MSP init callback. - (+) MspDeInitCallback : DFSDM filter MSP de-init callback. - [..] - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - For specific DFSDM filter analog watchdog callback use dedicated register callback: - HAL_DFSDM_Filter_RegisterAwdCallback(). - - [..] - Use functions HAL_DFSDM_Channel_UnRegisterCallback() or - HAL_DFSDM_Filter_UnRegisterCallback() to reset a callback to the default - weak function. - - [..] - HAL_DFSDM_Channel_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - [..] - This function allows to reset following callbacks: - (+) CkabCallback : DFSDM channel clock absence detection callback. - (+) ScdCallback : DFSDM channel short circuit detection callback. - (+) MspInitCallback : DFSDM channel MSP init callback. - (+) MspDeInitCallback : DFSDM channel MSP de-init callback. - - [..] - HAL_DFSDM_Filter_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - [..] - This function allows to reset following callbacks: - (+) RegConvCpltCallback : DFSDM filter regular conversion complete callback. - (+) RegConvHalfCpltCallback : DFSDM filter half regular conversion complete callback. - (+) InjConvCpltCallback : DFSDM filter injected conversion complete callback. - (+) InjConvHalfCpltCallback : DFSDM filter half injected conversion complete callback. - (+) ErrorCallback : DFSDM filter error callback. - (+) MspInitCallback : DFSDM filter MSP init callback. - (+) MspDeInitCallback : DFSDM filter MSP de-init callback. - - [..] - For specific DFSDM filter analog watchdog callback use dedicated unregister callback: - HAL_DFSDM_Filter_UnRegisterAwdCallback(). - - [..] - By default, after the call of init function and if the state is RESET - all callbacks are reset to the corresponding legacy weak functions: - examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback(). - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak functions in the init and de-init only when these - callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the init and de-init keep and use - the user MspInit/MspDeInit callbacks (registered beforehand) - - [..] - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the init/de-init. - In that case first register the MspInit/MspDeInit user callbacks using - HAL_DFSDM_Channel_RegisterCallback() or - HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function. - - [..] - When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#ifdef HAL_DFSDM_MODULE_ENABLED -#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx) -/** @defgroup DFSDM DFSDM - * @brief DFSDM HAL driver module - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup DFSDM_Private_Define DFSDM Private Define - * @{ - */ - -#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8 - -#define DFSDM_MSB_MASK 0xFFFF0000U -#define DFSDM_LSB_MASK 0x0000FFFFU -#define DFSDM_CKAB_TIMEOUT 5000U -#define DFSDM1_CHANNEL_NUMBER 8U -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DFSDM_Private_Variables DFSDM Private Variables - * @{ - */ -__IO uint32_t v_dfsdm1ChannelCounter = 0; -DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL}; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup DFSDM_Private_Functions DFSDM Private Functions - * @{ - */ -static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); -static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance); -static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); -static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma); -static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma); -static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma); -static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma); -static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions - * @{ - */ - -/** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions - * @brief Channel initialization and de-initialization functions - * -@verbatim - ============================================================================== - ##### Channel initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the DFSDM channel. - (+) De-initialize the DFSDM channel. -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DFSDM channel according to the specified parameters - * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_channel DFSDM channel handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Check DFSDM Channel handle */ - if(hdfsdm_channel == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation)); - assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer)); - assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking)); - assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins)); - assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type)); - assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock)); - assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder)); - assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling)); - assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset)); - assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift)); - - /* Check that channel has not been already initialized */ - if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) - { - return HAL_ERROR; - } - -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - /* Reset callback pointers to the weak predefined callbacks */ - hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback; - hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback; - - /* Call MSP init function */ - if(hdfsdm_channel->MspInitCallback == NULL) - { - hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; - } - hdfsdm_channel->MspInitCallback(hdfsdm_channel); -#else - /* Call MSP init function */ - HAL_DFSDM_ChannelMspInit(hdfsdm_channel); -#endif - - /* Update the channel counter */ - v_dfsdm1ChannelCounter++; - - /* Configure output serial clock and enable global DFSDM interface only for first channel */ - if(v_dfsdm1ChannelCounter == 1) - { - assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection)); - /* Set the output serial clock source */ - DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); - DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; - - /* Reset clock divider */ - DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); - if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) - { - assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); - /* Set the output clock divider */ - DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) << - DFSDM_CHCFGR1_CKOUTDIV_Pos); - } - - /* enable the DFSDM global interface */ - DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; - } - - /* Set channel input parameters */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | - DFSDM_CHCFGR1_CHINSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | - hdfsdm_channel->Init.Input.DataPacking | - hdfsdm_channel->Init.Input.Pins); - - /* Set serial interface parameters */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | - hdfsdm_channel->Init.SerialInterface.SpiClock); - - /* Set analog watchdog parameters */ - hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); - hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | - ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_AWFOSR_Pos)); - - /* Set channel offset and right bit shift */ - hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | - (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); - - /* Enable DFSDM channel */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; - - /* Set DFSDM Channel to ready state */ - hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; - - /* Store channel handle in DFSDM channel handle table */ - a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; - - return HAL_OK; -} - -/** - * @brief De-initialize the DFSDM channel. - * @param hdfsdm_channel DFSDM channel handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Check DFSDM Channel handle */ - if(hdfsdm_channel == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check that channel has not been already deinitialized */ - if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) - { - return HAL_ERROR; - } - - /* Disable the DFSDM channel */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); - - /* Update the channel counter */ - v_dfsdm1ChannelCounter--; - - /* Disable global DFSDM at deinit of last channel */ - if(v_dfsdm1ChannelCounter == 0) - { - DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN); - } - - /* Call MSP deinit function */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - if(hdfsdm_channel->MspDeInitCallback == NULL) - { - hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; - } - hdfsdm_channel->MspDeInitCallback(hdfsdm_channel); -#else - HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel); -#endif - - /* Set DFSDM Channel in reset state */ - hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET; - - /* Reset channel handle in DFSDM channel handle table */ - a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL; - - return HAL_OK; -} - -/** - * @brief Initialize the DFSDM channel MSP. - * @param hdfsdm_channel DFSDM channel handle. - * @retval None - */ -__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_channel); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_DFSDM_ChannelMspInit could be implemented in the user file. - */ -} - -/** - * @brief De-initialize the DFSDM channel MSP. - * @param hdfsdm_channel DFSDM channel handle. - * @retval None - */ -__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_channel); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file. - */ -} -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a user DFSDM channel callback - * to be used instead of the weak predefined callback. - * @param hdfsdm_channel DFSDM channel handle. - * @param CallbackID ID of the callback to be registered. - * This parameter can be one of the following values: - * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID. - * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID. - * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID. - * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID. - * @param pCallback pointer to the callback function. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, - pDFSDM_Channel_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(pCallback == NULL) - { - /* update return status */ - status = HAL_ERROR; - } - else - { - if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State) - { - switch (CallbackID) - { - case HAL_DFSDM_CHANNEL_CKAB_CB_ID : - hdfsdm_channel->CkabCallback = pCallback; - break; - case HAL_DFSDM_CHANNEL_SCD_CB_ID : - hdfsdm_channel->ScdCallback = pCallback; - break; - case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : - hdfsdm_channel->MspInitCallback = pCallback; - break; - case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : - hdfsdm_channel->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State) - { - switch (CallbackID) - { - case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : - hdfsdm_channel->MspInitCallback = pCallback; - break; - case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : - hdfsdm_channel->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - } - return status; -} - -/** - * @brief Unregister a user DFSDM channel callback. - * DFSDM channel callback is redirected to the weak predefined callback. - * @param hdfsdm_channel DFSDM channel handle. - * @param CallbackID ID of the callback to be unregistered. - * This parameter can be one of the following values: - * @arg @ref HAL_DFSDM_CHANNEL_CKAB_CB_ID clock absence detection callback ID. - * @arg @ref HAL_DFSDM_CHANNEL_SCD_CB_ID short circuit detection callback ID. - * @arg @ref HAL_DFSDM_CHANNEL_MSPINIT_CB_ID MSP init callback ID. - * @arg @ref HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID MSP de-init callback ID. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DFSDM_CHANNEL_STATE_READY == hdfsdm_channel->State) - { - switch (CallbackID) - { - case HAL_DFSDM_CHANNEL_CKAB_CB_ID : - hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback; - break; - case HAL_DFSDM_CHANNEL_SCD_CB_ID : - hdfsdm_channel->ScdCallback = HAL_DFSDM_ChannelScdCallback; - break; - case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : - hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; - break; - case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : - hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if(HAL_DFSDM_CHANNEL_STATE_RESET == hdfsdm_channel->State) - { - switch (CallbackID) - { - case HAL_DFSDM_CHANNEL_MSPINIT_CB_ID : - hdfsdm_channel->MspInitCallback = HAL_DFSDM_ChannelMspInit; - break; - case HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID : - hdfsdm_channel->MspDeInitCallback = HAL_DFSDM_ChannelMspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - return status; -} -#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions - * @brief Channel operation functions - * -@verbatim - ============================================================================== - ##### Channel operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Manage clock absence detector feature. - (+) Manage short circuit detector feature. - (+) Get analog watchdog value. - (+) Modify offset value. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to start clock absence detection in polling mode. - * @note Same mode has to be used for all channels. - * @note If clock is not available on this channel during 5 seconds, - * clock absence detection will not be activated and function - * will return HAL_TIMEOUT error. - * @param hdfsdm_channel DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - uint32_t tickstart; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Get channel number from channel instance */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) - { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); - - /* Check the Timeout */ - if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) - { - /* Set timeout status */ - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - /* Start clock absence detection */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; - } - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the clock absence detection. - * @param hdfsdm_channel DFSDM channel handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - return HAL_ERROR; - } - else - { - /* Get channel number from channel instance */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait clock absence detection */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) == 0) - { - /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Return timeout status */ - return HAL_TIMEOUT; - } - } - } - - /* Clear clock absence detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); - - /* Return function status */ - return HAL_OK; - } -} - -/** - * @brief This function allows to stop clock absence detection in polling mode. - * @param hdfsdm_channel DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop clock absence detection */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - - /* Clear clock absence flag */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start clock absence detection in interrupt mode. - * @note Same mode has to be used for all channels. - * @note If clock is not available on this channel during 5 seconds, - * clock absence detection will not be activated and function - * will return HAL_TIMEOUT error. - * @param hdfsdm_channel DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - uint32_t tickstart; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Get channel number from channel instance */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Clear clock absence flag */ - while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0) - { - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); - - /* Check the Timeout */ - if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT) - { - /* Set timeout status */ - status = HAL_TIMEOUT; - break; - } - } - - if(status == HAL_OK) - { - /* Activate clock absence detection interrupt */ - DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE; - - /* Start clock absence detection */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; - } - } - /* Return function status */ - return status; -} - -/** - * @brief Clock absence detection callback. - * @param hdfsdm_channel DFSDM channel handle. - * @retval None - */ -__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_channel); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file - */ -} - -/** - * @brief This function allows to stop clock absence detection in interrupt mode. - * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop clock absence detection */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - - /* Clear clock absence flag */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); - - /* Disable clock absence detection interrupt */ - DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start short circuit detection in polling mode. - * @note Same mode has to be used for all channels - * @param hdfsdm_channel DFSDM channel handle. - * @param Threshold Short circuit detector threshold. - * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal Break signals assigned to short circuit event. - * This parameter can be a values combination of @ref DFSDM_BreakSignals. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - uint32_t Threshold, - uint32_t BreakSignal) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); - assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Configure threshold and break signals */ - hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ - Threshold); - - /* Start short circuit detection */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the short circuit detection. - * @param hdfsdm_channel DFSDM channel handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - return HAL_ERROR; - } - else - { - /* Get channel number from channel instance */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait short circuit detection */ - while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0) - { - /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Return timeout status */ - return HAL_TIMEOUT; - } - } - } - - /* Clear short circuit detection flag */ - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); - - /* Return function status */ - return HAL_OK; - } -} - -/** - * @brief This function allows to stop short circuit detection in polling mode. - * @param hdfsdm_channel DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop short circuit detection */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - - /* Clear short circuit detection flag */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start short circuit detection in interrupt mode. - * @note Same mode has to be used for all channels - * @param hdfsdm_channel DFSDM channel handle. - * @param Threshold Short circuit detector threshold. - * This parameter must be a number between Min_Data = 0 and Max_Data = 255. - * @param BreakSignal Break signals assigned to short circuit event. - * This parameter can be a values combination of @ref DFSDM_BreakSignals. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - uint32_t Threshold, - uint32_t BreakSignal) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); - assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Activate short circuit detection interrupt */ - DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE; - - /* Configure threshold and break signals */ - hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); - hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ - Threshold); - - /* Start short circuit detection */ - hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; - } - /* Return function status */ - return status; -} - -/** - * @brief Short circuit detection callback. - * @param hdfsdm_channel DFSDM channel handle. - * @retval None - */ -__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_channel); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_ChannelScdCallback could be implemented in the user file - */ -} - -/** - * @brief This function allows to stop short circuit detection in interrupt mode. - * @note Interrupt will be disabled for all channels - * @param hdfsdm_channel DFSDM channel handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t channel; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop short circuit detection */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - - /* Clear short circuit detection flag */ - channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); - - /* Disable short circuit detection interrupt */ - DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get channel analog watchdog value. - * @param hdfsdm_channel DFSDM channel handle. - * @retval Channel analog watchdog value. - */ -int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - return (int16_t) hdfsdm_channel->Instance->CHWDATAR; -} - -/** - * @brief This function allows to modify channel offset value. - * @param hdfsdm_channel DFSDM channel handle. - * @param Offset DFSDM channel offset. - * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, - int32_t Offset) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset)); - - /* Check DFSDM channel state */ - if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Modify channel offset */ - hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET); - hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos); - } - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function - * @brief Channel state function - * -@verbatim - ============================================================================== - ##### Channel state function ##### - ============================================================================== - [..] This section provides function allowing to: - (+) Get channel handle state. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to get the current DFSDM channel handle state. - * @param hdfsdm_channel DFSDM channel handle. - * @retval DFSDM channel state. - */ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ - /* Return DFSDM channel handle state */ - return hdfsdm_channel->State; -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions - * @brief Filter initialization and de-initialization functions - * -@verbatim - ============================================================================== - ##### Filter initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the DFSDM filter. - (+) De-initialize the DFSDM filter. -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DFSDM filter according to the specified parameters - * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Check DFSDM Channel handle */ - if(hdfsdm_filter == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode)); - assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode)); - assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode)); - assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder)); - assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling)); - assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling)); - - /* Check parameters compatibility */ - if((hdfsdm_filter->Instance == DFSDM1_Filter0) && - ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || - (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) - { - return HAL_ERROR; - } - - /* Initialize DFSDM filter variables with default values */ - hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF; - hdfsdm_filter->InjectedChannelsNbr = 1; - hdfsdm_filter->InjConvRemaining = 1; - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE; - -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - /* Reset callback pointers to the weak predefined callbacks */ - hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback; - hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback; - hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback; - hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback; - hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback; - hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback; - - /* Call MSP init function */ - if(hdfsdm_filter->MspInitCallback == NULL) - { - hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; - } - hdfsdm_filter->MspInitCallback(hdfsdm_filter); -#else - /* Call MSP init function */ - HAL_DFSDM_FilterMspInit(hdfsdm_filter); -#endif - - /* Set regular parameters */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); - if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST; - } - else - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST); - } - - if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN; - } - else - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN); - } - - /* Set injected parameters */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL); - if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER) - { - assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger)); - assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge)); - hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger); - } - - if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN; - } - else - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN); - } - - if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN; - } - else - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN); - } - - /* Set filter parameters */ - hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); - hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | - ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_Pos) | - (hdfsdm_filter->Init.FilterParam.IntOversampling - 1)); - - /* Store regular and injected triggers and injected scan mode*/ - hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger; - hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger; - hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge; - hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode; - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* Set DFSDM filter to ready state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY; - - return HAL_OK; -} - -/** - * @brief De-initializes the DFSDM filter. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Check DFSDM filter handle */ - if(hdfsdm_filter == NULL) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Disable the DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - /* Call MSP deinit function */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - if(hdfsdm_filter->MspDeInitCallback == NULL) - { - hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; - } - hdfsdm_filter->MspDeInitCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterMspDeInit(hdfsdm_filter); -#endif - - /* Set DFSDM filter in reset state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the DFSDM filter MSP. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_DFSDM_FilterMspInit could be implemented in the user file. - */ -} - -/** - * @brief De-initializes the DFSDM filter MSP. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_DFSDM_FilterMspDeInit could be implemented in the user file. - */ -} - -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a user DFSDM filter callback - * to be used instead of the weak predefined callback. - * @param hdfsdm_filter DFSDM filter handle. - * @param CallbackID ID of the callback to be registered. - * This parameter can be one of the following values: - * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID. - * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID. - * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID. - * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID. - * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID. - * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID. - * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID. - * @param pCallback pointer to the callback function. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, - pDFSDM_Filter_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(pCallback == NULL) - { - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - else - { - if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) - { - switch (CallbackID) - { - case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID : - hdfsdm_filter->RegConvCpltCallback = pCallback; - break; - case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID : - hdfsdm_filter->RegConvHalfCpltCallback = pCallback; - break; - case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID : - hdfsdm_filter->InjConvCpltCallback = pCallback; - break; - case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID : - hdfsdm_filter->InjConvHalfCpltCallback = pCallback; - break; - case HAL_DFSDM_FILTER_ERROR_CB_ID : - hdfsdm_filter->ErrorCallback = pCallback; - break; - case HAL_DFSDM_FILTER_MSPINIT_CB_ID : - hdfsdm_filter->MspInitCallback = pCallback; - break; - case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : - hdfsdm_filter->MspDeInitCallback = pCallback; - break; - default : - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State) - { - switch (CallbackID) - { - case HAL_DFSDM_FILTER_MSPINIT_CB_ID : - hdfsdm_filter->MspInitCallback = pCallback; - break; - case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : - hdfsdm_filter->MspDeInitCallback = pCallback; - break; - default : - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - } - return status; -} - -/** - * @brief Unregister a user DFSDM filter callback. - * DFSDM filter callback is redirected to the weak predefined callback. - * @param hdfsdm_filter DFSDM filter handle. - * @param CallbackID ID of the callback to be unregistered. - * This parameter can be one of the following values: - * @arg @ref HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID regular conversion complete callback ID. - * @arg @ref HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID half regular conversion complete callback ID. - * @arg @ref HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID injected conversion complete callback ID. - * @arg @ref HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID half injected conversion complete callback ID. - * @arg @ref HAL_DFSDM_FILTER_ERROR_CB_ID error callback ID. - * @arg @ref HAL_DFSDM_FILTER_MSPINIT_CB_ID MSP init callback ID. - * @arg @ref HAL_DFSDM_FILTER_MSPDEINIT_CB_ID MSP de-init callback ID. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) - { - switch (CallbackID) - { - case HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID : - hdfsdm_filter->RegConvCpltCallback = HAL_DFSDM_FilterRegConvCpltCallback; - break; - case HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID : - hdfsdm_filter->RegConvHalfCpltCallback = HAL_DFSDM_FilterRegConvHalfCpltCallback; - break; - case HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID : - hdfsdm_filter->InjConvCpltCallback = HAL_DFSDM_FilterInjConvCpltCallback; - break; - case HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID : - hdfsdm_filter->InjConvHalfCpltCallback = HAL_DFSDM_FilterInjConvHalfCpltCallback; - break; - case HAL_DFSDM_FILTER_ERROR_CB_ID : - hdfsdm_filter->ErrorCallback = HAL_DFSDM_FilterErrorCallback; - break; - case HAL_DFSDM_FILTER_MSPINIT_CB_ID : - hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; - break; - case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : - hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; - break; - default : - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if(HAL_DFSDM_FILTER_STATE_RESET == hdfsdm_filter->State) - { - switch (CallbackID) - { - case HAL_DFSDM_FILTER_MSPINIT_CB_ID : - hdfsdm_filter->MspInitCallback = HAL_DFSDM_FilterMspInit; - break; - case HAL_DFSDM_FILTER_MSPDEINIT_CB_ID : - hdfsdm_filter->MspDeInitCallback = HAL_DFSDM_FilterMspDeInit; - break; - default : - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - return status; -} - -/** - * @brief Register a user DFSDM filter analog watchdog callback - * to be used instead of the weak predefined callback. - * @param hdfsdm_filter DFSDM filter handle. - * @param pCallback pointer to the DFSDM filter analog watchdog callback function. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - pDFSDM_Filter_AwdCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(pCallback == NULL) - { - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - else - { - if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) - { - hdfsdm_filter->AwdCallback = pCallback; - } - else - { - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - } - return status; -} - -/** - * @brief Unregister a user DFSDM filter analog watchdog callback. - * DFSDM filter AWD callback is redirected to the weak predefined callback. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(HAL_DFSDM_FILTER_STATE_READY == hdfsdm_filter->State) - { - hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback; - } - else - { - /* update the error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - return status; -} -#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions - * @brief Filter control functions - * -@verbatim - ============================================================================== - ##### Filter control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Select channel and enable/disable continuous mode for regular conversion. - (+) Select channels for injected conversion. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to select channel and to enable/disable - * continuous mode for regular conversion. - * @param hdfsdm_filter DFSDM filter handle. - * @param Channel Channel for regular conversion. - * This parameter can be a value of @ref DFSDM_Channel_Selection. - * @param ContinuousMode Enable/disable continuous mode for regular conversion. - * This parameter can be a value of @ref DFSDM_ContinuousMode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel, - uint32_t ContinuousMode) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel)); - assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Configure channel and continuous mode for regular conversion */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT); - if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON) - { - hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) | - DFSDM_FLTCR1_RCONT); - } - else - { - hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET); - } - /* Store continuous mode information */ - hdfsdm_filter->RegularContMode = ContinuousMode; - } - else - { - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to select channels for injected conversion. - * @param hdfsdm_filter DFSDM filter handle. - * @param Channel Channels for injected conversion. - * This parameter can be a values combination of @ref DFSDM_Channel_Selection. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Configure channel for injected conversion */ - hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK); - /* Store number of injected channels */ - hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel); - /* Update number of injected channels remaining */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions - * @brief Filter operation functions - * -@verbatim - ============================================================================== - ##### Filter operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular/injected channel. - (+) Poll for the end of regular/injected conversion. - (+) Stop conversion of regular/injected channel. - (+) Start conversion of regular/injected channel and enable interrupt. - (+) Call the callback functions at the end of regular/injected conversions. - (+) Stop conversion of regular/injected channel and disable interrupt. - (+) Start conversion of regular/injected channel and enable DMA transfer. - (+) Stop conversion of regular/injected channel and disable DMA transfer. - (+) Start analog watchdog and enable interrupt. - (+) Call the callback function when analog watchdog occurs. - (+) Stop analog watchdog and disable interrupt. - (+) Start extreme detector. - (+) Stop extreme detector. - (+) Get result of regular channel conversion. - (+) Get result of injected channel conversion. - (+) Get extreme detector maximum and minimum values. - (+) Get conversion time. - (+) Handle DFSDM interrupt request. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to start regular conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) - { - /* Start regular conversion */ - DFSDM_RegConvStart(hdfsdm_filter); - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the end of regular conversion. - * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - return HAL_ERROR; - } - else - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait end of regular conversion */ - while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) - { - /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Return timeout status */ - return HAL_TIMEOUT; - } - } - } - /* Check if overrun occurs */ - if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF) - { - /* Update error code and call error callback */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->ErrorCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); -#endif - - /* Clear regular overrun flag */ - hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; - } - /* Update DFSDM filter state only if not continuous conversion and SW trigger */ - if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) - { - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; - } - /* Return function status */ - return HAL_OK; - } -} - -/** - * @brief This function allows to stop regular conversion in polling mode. - * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop regular conversion */ - DFSDM_RegConvStop(hdfsdm_filter); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start regular conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if injected conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) - { - /* Enable interrupts for regular conversions */ - hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - - /* Start regular conversion */ - DFSDM_RegConvStart(hdfsdm_filter); - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop regular conversion in interrupt mode. - * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Disable interrupts for regular conversions */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - - /* Stop regular conversion */ - DFSDM_RegConvStop(hdfsdm_filter); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start regular conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if injected conversion is ongoing. - * Please note that data on buffer will contain signed regular conversion - * value on 24 most significant bits and corresponding channel on 3 least - * significant bits. - * @param hdfsdm_filter DFSDM filter handle. - * @param pData The destination buffer address. - * @param Length The length of data to be transferred from DFSDM filter to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - int32_t *pData, - uint32_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) - { - status = HAL_ERROR; - } - /* Check that DMA is enabled for regular conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) - { - status = HAL_ERROR; - } - /* Check parameters compatibility */ - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) - { - status = HAL_ERROR; - } - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) - { - status = HAL_ERROR; - } - /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) - { - /* Set callbacks on DMA handler */ - hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; - hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ - DFSDM_DMARegularHalfConvCplt : NULL; - - /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ - (uint32_t) pData, Length) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Start regular conversion */ - DFSDM_RegConvStart(hdfsdm_filter); - } - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start regular conversion in DMA mode and to get - * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if injected conversion is ongoing. - * Please note that data on buffer will contain signed 16 most significant - * bits of regular conversion. - * @param hdfsdm_filter DFSDM filter handle. - * @param pData The destination buffer address. - * @param Length The length of data to be transferred from DFSDM filter to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - int16_t *pData, - uint32_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) - { - status = HAL_ERROR; - } - /* Check that DMA is enabled for regular conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN) - { - status = HAL_ERROR; - } - /* Check parameters compatibility */ - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \ - (Length != 1)) - { - status = HAL_ERROR; - } - else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR)) - { - status = HAL_ERROR; - } - /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)) - { - /* Set callbacks on DMA handler */ - hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt; - hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ - DFSDM_DMARegularHalfConvCplt : NULL; - - /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2, \ - (uint32_t) pData, Length) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Start regular conversion */ - DFSDM_RegConvStart(hdfsdm_filter); - } - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop regular conversion in DMA mode. - * @note This function should be called only if regular conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop current DMA transfer */ - if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Stop regular conversion */ - DFSDM_RegConvStop(hdfsdm_filter); - } - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get regular conversion value. - * @param hdfsdm_filter DFSDM filter handle. - * @param Channel Corresponding channel of regular conversion. - * @retval Regular conversion value - */ -int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t *Channel) -{ - uint32_t reg = 0; - int32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); - - /* Get value of data register for regular channel */ - reg = hdfsdm_filter->Instance->FLTRDATAR; - - /* Extract channel and regular conversion value */ - *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); - value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos); - - /* return regular conversion value */ - return value; -} - -/** - * @brief This function allows to start injected conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) - { - /* Start injected conversion */ - DFSDM_InjConvStart(hdfsdm_filter); - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the end of injected conversion. - * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - return HAL_ERROR; - } - else - { - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait end of injected conversions */ - while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) - { - /* Check the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) - { - /* Return timeout status */ - return HAL_TIMEOUT; - } - } - } - /* Check if overrun occurs */ - if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF) - { - /* Update error code and call error callback */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->ErrorCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); -#endif - - /* Clear injected overrun flag */ - hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; - } - - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining--; - if(hdfsdm_filter->InjConvRemaining == 0) - { - /* Update DFSDM filter state only if trigger is software */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; - } - - /* end of injected sequence, reset the value */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - - /* Return function status */ - return HAL_OK; - } -} - -/** - * @brief This function allows to stop injected conversion in polling mode. - * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop injected conversion */ - DFSDM_InjConvStop(hdfsdm_filter); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start injected conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if regular conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) - { - /* Enable interrupts for injected conversions */ - hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - - /* Start injected conversion */ - DFSDM_InjConvStart(hdfsdm_filter); - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop injected conversion in interrupt mode. - * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Disable interrupts for injected conversions */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - - /* Stop injected conversion */ - DFSDM_InjConvStop(hdfsdm_filter); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start injected conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if regular conversion is ongoing. - * Please note that data on buffer will contain signed injected conversion - * value on 24 most significant bits and corresponding channel on 3 least - * significant bits. - * @param hdfsdm_filter DFSDM filter handle. - * @param pData The destination buffer address. - * @param Length The length of data to be transferred from DFSDM filter to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - int32_t *pData, - uint32_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) - { - status = HAL_ERROR; - } - /* Check that DMA is enabled for injected conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) - { - status = HAL_ERROR; - } - /* Check parameters compatibility */ - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ - (Length > hdfsdm_filter->InjConvRemaining)) - { - status = HAL_ERROR; - } - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) - { - status = HAL_ERROR; - } - /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) - { - /* Set callbacks on DMA handler */ - hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; - hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ - DFSDM_DMAInjectedHalfConvCplt : NULL; - - /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ - (uint32_t) pData, Length) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Start injected conversion */ - DFSDM_InjConvStart(hdfsdm_filter); - } - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start injected conversion in DMA mode and to get - * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is - * in idle state or if regular conversion is ongoing. - * Please note that data on buffer will contain signed 16 most significant - * bits of injected conversion. - * @param hdfsdm_filter DFSDM filter handle. - * @param pData The destination buffer address. - * @param Length The length of data to be transferred from DFSDM filter to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - int16_t *pData, - uint32_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check destination address and length */ - if((pData == NULL) || (Length == 0)) - { - status = HAL_ERROR; - } - /* Check that DMA is enabled for injected conversion */ - else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN) - { - status = HAL_ERROR; - } - /* Check parameters compatibility */ - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \ - (Length > hdfsdm_filter->InjConvRemaining)) - { - status = HAL_ERROR; - } - else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \ - (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR)) - { - status = HAL_ERROR; - } - /* Check DFSDM filter state */ - else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG)) - { - /* Set callbacks on DMA handler */ - hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt; - hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; - hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ - DFSDM_DMAInjectedHalfConvCplt : NULL; - - /* Start DMA in interrupt mode */ - if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2, \ - (uint32_t) pData, Length) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Start injected conversion */ - DFSDM_InjConvStart(hdfsdm_filter); - } - } - else - { - status = HAL_ERROR; - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop injected conversion in DMA mode. - * @note This function should be called only if injected conversion is ongoing. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \ - (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Stop current DMA transfer */ - if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK) - { - /* Set DFSDM filter in error state */ - hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Stop regular conversion */ - DFSDM_InjConvStop(hdfsdm_filter); - } - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get injected conversion value. - * @param hdfsdm_filter DFSDM filter handle. - * @param Channel Corresponding channel of injected conversion. - * @retval Injected conversion value - */ -int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t *Channel) -{ - uint32_t reg = 0; - int32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); - - /* Get value of data register for injected channel */ - reg = hdfsdm_filter->Instance->FLTJDATAR; - - /* Extract channel and injected conversion value */ - *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); - value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos); - - /* return regular conversion value */ - return value; -} - -/** - * @brief This function allows to start filter analog watchdog in interrupt mode. - * @param hdfsdm_filter DFSDM filter handle. - * @param awdParam DFSDM filter analog watchdog parameters. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - const DFSDM_Filter_AwdParamTypeDef *awdParam) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource)); - assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel)); - assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold)); - assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold)); - assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal)); - assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Set analog watchdog data source */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL); - hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource; - - /* Set thresholds and break signals */ - hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); - hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \ - awdParam->HighBreakSignal); - hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); - hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \ - awdParam->LowBreakSignal); - - /* Set channels and interrupt for analog watchdog */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH); - hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \ - DFSDM_FLTCR2_AWDIE); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop filter analog watchdog in interrupt mode. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Reset channels for analog watchdog and deactivate interrupt */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE); - - /* Clear all analog watchdog flags */ - hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF); - - /* Reset thresholds and break signals */ - hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); - hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); - - /* Reset analog watchdog data source */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start extreme detector feature. - * @param hdfsdm_filter DFSDM filter handle. - * @param Channel Channels where extreme detector is enabled. - * This parameter can be a values combination of @ref DFSDM_Channel_Selection. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Set channels for extreme detector */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop extreme detector feature. - * @param hdfsdm_filter DFSDM filter handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t reg1; - __IO uint32_t reg2; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Check DFSDM filter state */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ - (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) - { - /* Return error status */ - status = HAL_ERROR; - } - else - { - /* Reset channels for extreme detector */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - - /* Clear extreme detector values */ - reg1 = hdfsdm_filter->Instance->FLTEXMAX; - reg2 = hdfsdm_filter->Instance->FLTEXMIN; - UNUSED(reg1); /* To avoid GCC warning */ - UNUSED(reg2); /* To avoid GCC warning */ - } - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get extreme detector maximum value. - * @param hdfsdm_filter DFSDM filter handle. - * @param Channel Corresponding channel. - * @retval Extreme detector maximum value - * This value is between Min_Data = -8388608 and Max_Data = 8388607. - */ -int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t *Channel) -{ - uint32_t reg = 0; - int32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); - - /* Get value of extreme detector maximum register */ - reg = hdfsdm_filter->Instance->FLTEXMAX; - - /* Extract channel and extreme detector maximum value */ - *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); - value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos); - - /* return extreme detector maximum value */ - return value; -} - -/** - * @brief This function allows to get extreme detector minimum value. - * @param hdfsdm_filter DFSDM filter handle. - * @param Channel Corresponding channel. - * @retval Extreme detector minimum value - * This value is between Min_Data = -8388608 and Max_Data = 8388607. - */ -int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t *Channel) -{ - uint32_t reg = 0; - int32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - assert_param(Channel != NULL); - - /* Get value of extreme detector minimum register */ - reg = hdfsdm_filter->Instance->FLTEXMIN; - - /* Extract channel and extreme detector minimum value */ - *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); - value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos); - - /* return extreme detector minimum value */ - return value; -} - -/** - * @brief This function allows to get conversion time value. - * @param hdfsdm_filter DFSDM filter handle. - * @retval Conversion time value - * @note To get time in second, this value has to be divided by DFSDM clock frequency. - */ -uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - uint32_t reg = 0; - uint32_t value = 0; - - /* Check parameters */ - assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - - /* Get value of conversion timer register */ - reg = hdfsdm_filter->Instance->FLTCNVTIMR; - - /* Extract conversion time value */ - value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos); - - /* return extreme detector minimum value */ - return value; -} - -/** - * @brief This function handles the DFSDM interrupts. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Check if overrun occurs during regular conversion */ - if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0)) - { - /* Clear regular overrun flag */ - hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF; - - /* Update error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN; - - /* Call error callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->ErrorCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); -#endif - } - /* Check if overrun occurs during injected conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0)) - { - /* Clear injected overrun flag */ - hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF; - - /* Update error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN; - - /* Call error callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->ErrorCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); -#endif - } - /* Check if end of regular conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0)) - { - /* Call regular conversion complete callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); -#endif - - /* End of conversion if mode is not continuous and software trigger */ - if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) - { - /* Disable interrupts for regular conversions */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE); - - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; - } - } - /* Check if end of injected conversion */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0)) - { - /* Call injected conversion complete callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); -#endif - - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining--; - if(hdfsdm_filter->InjConvRemaining == 0) - { - /* End of conversion if trigger is software */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - /* Disable interrupts for injected conversions */ - hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE); - - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; - } - /* end of injected sequence, reset the value */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - } - /* Check if analog watchdog occurs */ - else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0)) - { - uint32_t reg = 0; - uint32_t threshold = 0; - uint32_t channel = 0; - - /* Get channel and threshold */ - reg = hdfsdm_filter->Instance->FLTAWSR; - threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; - if(threshold == DFSDM_AWD_HIGH_THRESHOLD) - { - reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos; - } - while((reg & 1) == 0) - { - channel++; - reg = reg >> 1; - } - /* Clear analog watchdog flag */ - hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \ - (1 << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \ - (1 << channel); - - /* Call analog watchdog callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->AwdCallback(hdfsdm_filter, channel, threshold); -#else - HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold); -#endif - } - /* Check if clock absence occurs */ - else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ - ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0)) - { - uint32_t reg = 0; - uint32_t channel = 0; - - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); - - while(channel < DFSDM1_CHANNEL_NUMBER) - { - /* Check if flag is set and corresponding channel is enabled */ - if(((reg & 1) != 0) && (a_dfsdm1ChannelHandle[channel] != NULL)) - { - /* Check clock absence has been enabled for this channel */ - if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0) - { - /* Clear clock absence flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); - - /* Call clock absence callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - a_dfsdm1ChannelHandle[channel]->CkabCallback(a_dfsdm1ChannelHandle[channel]); -#else - HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]); -#endif - } - } - channel++; - reg = reg >> 1; - } - } - /* Check if short circuit detection occurs */ - else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ - ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0) && \ - ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0)) - { - uint32_t reg = 0; - uint32_t channel = 0; - - /* Get channel */ - reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); - while((reg & 1) == 0) - { - channel++; - reg = reg >> 1; - } - - /* Clear short circuit detection flag */ - hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); - - /* Call short circuit detection callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - a_dfsdm1ChannelHandle[channel]->ScdCallback(a_dfsdm1ChannelHandle[channel]); -#else - HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); -#endif - } -} - -/** - * @brief Regular conversion complete callback. - * @note In interrupt mode, user has to read conversion value in this function - * using HAL_DFSDM_FilterGetRegularValue. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file. - */ -} - -/** - * @brief Half regular conversion complete callback. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file. - */ -} - -/** - * @brief Injected conversion complete callback. - * @note In interrupt mode, user has to read conversion value in this function - * using HAL_DFSDM_FilterGetInjectedValue. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file. - */ -} - -/** - * @brief Half injected conversion complete callback. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file. - */ -} - -/** - * @brief Filter analog watchdog callback. - * @param hdfsdm_filter DFSDM filter handle. - * @param Channel Corresponding channel. - * @param Threshold Low or high threshold has been reached. - * @retval None - */ -__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - uint32_t Channel, uint32_t Threshold) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - UNUSED(Channel); - UNUSED(Threshold); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterAwdCallback could be implemented in the user file. - */ -} - -/** - * @brief Error callback. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdfsdm_filter); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_DFSDM_FilterErrorCallback could be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions - * @brief Filter state functions - * -@verbatim - ============================================================================== - ##### Filter state functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Get the DFSDM filter state. - (+) Get the DFSDM filter error. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to get the current DFSDM filter handle state. - * @param hdfsdm_filter DFSDM filter handle. - * @retval DFSDM filter state. - */ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - /* Return DFSDM filter handle state */ - return hdfsdm_filter->State; -} - -/** - * @brief This function allows to get the current DFSDM filter error. - * @param hdfsdm_filter DFSDM filter handle. - * @retval DFSDM filter error code. - */ -uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) -{ - return hdfsdm_filter->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DFSDM_Private_Functions DFSDM Private Functions - * @{ - */ - -/** - * @brief DMA half transfer complete callback for regular conversion. - * @param hdma DMA handle. - * @retval None - */ -static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Call regular half conversion complete callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->RegConvHalfCpltCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter); -#endif -} - -/** - * @brief DMA transfer complete callback for regular conversion. - * @param hdma DMA handle. - * @retval None - */ -static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Call regular conversion complete callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->RegConvCpltCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter); -#endif -} - -/** - * @brief DMA half transfer complete callback for injected conversion. - * @param hdma DMA handle. - * @retval None - */ -static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Call injected half conversion complete callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->InjConvHalfCpltCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter); -#endif -} - -/** - * @brief DMA transfer complete callback for injected conversion. - * @param hdma DMA handle. - * @retval None - */ -static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Call injected conversion complete callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->InjConvCpltCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter); -#endif -} - -/** - * @brief DMA error callback. - * @param hdma DMA handle. - * @retval None - */ -static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Get DFSDM filter handle */ - DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; - - /* Update error code */ - hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA; - - /* Call error callback */ -#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) - hdfsdm_filter->ErrorCallback(hdfsdm_filter); -#else - HAL_DFSDM_FilterErrorCallback(hdfsdm_filter); -#endif -} - -/** - * @brief This function allows to get the number of injected channels. - * @param Channels bitfield of injected channels. - * @retval Number of injected channels. - */ -static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) -{ - uint32_t nbChannels = 0; - uint32_t tmp; - - /* Get the number of channels from bitfield */ - tmp = (uint32_t) (Channels & DFSDM_LSB_MASK); - while(tmp != 0) - { - if((tmp & 1) != 0) - { - nbChannels++; - } - tmp = (uint32_t) (tmp >> 1); - } - return nbChannels; -} - -/** - * @brief This function allows to get the channel number from channel instance. - * @param Instance DFSDM channel instance. - * @retval Channel number. - */ -static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance) -{ - uint32_t channel; - - /* Get channel from instance */ - if(Instance == DFSDM1_Channel0) - { - channel = 0; - } - else if(Instance == DFSDM1_Channel1) - { - channel = 1; - } - else if(Instance == DFSDM1_Channel2) - { - channel = 2; - } - else if(Instance == DFSDM1_Channel3) - { - channel = 3; - } - else if(Instance == DFSDM1_Channel4) - { - channel = 4; - } - else if(Instance == DFSDM1_Channel5) - { - channel = 5; - } - else if(Instance == DFSDM1_Channel6) - { - channel = 6; - } - else /* DFSDM1_Channel7 */ - { - channel = 7; - } - - return channel; -} - -/** - * @brief This function allows to really start regular conversion. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) -{ - /* Check regular trigger */ - if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) - { - /* Software start of regular conversion */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; - } - else /* synchronous trigger */ - { - /* Disable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - /* Set RSYNC bit in DFSDM_FLTCR1 register */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC; - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* If injected conversion was in progress, restart it */ - if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) - { - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; - } - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - } - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ - HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ; -} - -/** - * @brief This function allows to really stop regular conversion. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) -{ - /* Disable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */ - if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER) - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC); - } - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* If injected conversion was in progress, restart it */ - if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) - { - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; - } - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - } - - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; -} - -/** - * @brief This function allows to really start injected conversion. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) -{ - /* Check injected trigger */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) - { - /* Software start of injected conversion */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART; - } - else /* external or synchronous trigger */ - { - /* Disable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) - { - /* Set JSYNC bit in DFSDM_FLTCR1 register */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC; - } - else /* external trigger */ - { - /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ - hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge; - } - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* If regular conversion was in progress, restart it */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; - } - } - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \ - HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ; -} - -/** - * @brief This function allows to really stop injected conversion. - * @param hdfsdm_filter DFSDM filter handle. - * @retval None - */ -static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) -{ - /* Disable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - - /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */ - if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) - { - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC); - } - else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER) - { - /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ - hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN); - } - - /* Enable DFSDM filter */ - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - - /* If regular conversion was in progress, restart it */ - if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ - (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) - { - hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART; - } - - /* Update remaining injected conversions */ - hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ - hdfsdm_filter->InjectedChannelsNbr : 1; - - /* Update DFSDM filter state */ - hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ - HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; -} - -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ -#endif /* HAL_DFSDM_MODULE_ENABLED */ -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c index 65d9596e..6c084ac3 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma.c @@ -1,1312 +1,1312 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma.c - * @author MCD Application Team - * @brief DMA HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Direct Memory Access (DMA) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and errors functions - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable and configure the peripheral to be connected to the DMA Stream - (except for internal SRAM/FLASH memories: no initialization is - necessary) please refer to Reference manual for connection between peripherals - and DMA requests. - - (#) For a given Stream, program the required configuration through the following parameters: - Transfer Direction, Source and Destination data formats, - Circular, Normal or peripheral flow control mode, Stream Priority level, - Source and Destination Increment mode, FIFO mode and its Threshold (if needed), - Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. - - -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: - __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). - - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source - address and destination address and the Length of data to be transferred. - (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this - case a fixed Timeout can be configured by User depending from his application. - (+) Use HAL_DMA_Abort() function to abort the current transfer. - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - (+) Select Callbacks functions using HAL_DMA_RegisterCallback() - (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of - Source address and destination address and the Length of data to be transferred. In this - case the DMA interrupt is configured - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine - (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback and - XferErrorCallback (i.e a member of DMA handle structure). - [..] - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. - - (#) Use HAL_DMA_Abort_IT() function to abort the current transfer - - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. - - -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is - possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set - Half-Word data size for the peripheral to access its data register and set Word data size - for the Memory to gain in access time. Each two half words will be packed and written in - a single access to a Word in the Memory). - - -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source - and Destination. In this case the Peripheral Data Size will be applied to both Source - and Destination. - - *** DMA HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. - (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. - (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. - - [..] - (@) You can refer to the DMA HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -typedef struct -{ - __IO uint32_t ISR; /*!< DMA interrupt status register */ - __IO uint32_t Reserved0; - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ -} DMA_Base_Registers; - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup DMA_Private_Constants - * @{ - */ - #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DMA_Private_Functions - * @{ - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @addtogroup DMA_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize the DMA Stream source - and destination addresses, incrementation and data sizes, transfer direction, - circular/normal mode selection, memory-to-memory mode selection and Stream priority value. - [..] - The HAL_DMA_Init() function follows the DMA configuration procedures as described in - reference manual. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA according to the specified - * parameters in the DMA_InitTypeDef and create the associated handle. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) -{ - uint32_t tmp = 0U; - uint32_t tickstart = HAL_GetTick(); - DMA_Base_Registers *regs; - - /* Check the DMA peripheral state */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); - assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); - assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); - assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); - /* Check the memory burst, peripheral burst and FIFO threshold parameters only - when FIFO mode is enabled */ - if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) - { - assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); - assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); - assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); - } - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); - - - /* Disable the peripheral */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA Stream is effectively disabled */ - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Get the CR register value */ - tmp = hdma->Instance->CR; - - /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ - tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ - DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ - DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ - DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); - - /* Prepare the DMA Stream configuration */ - tmp |= hdma->Init.Channel | hdma->Init.Direction | - hdma->Init.PeriphInc | hdma->Init.MemInc | - hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | - hdma->Init.Mode | hdma->Init.Priority; - - /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ - if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) - { - /* Get memory burst and peripheral burst */ - tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; - } - - /* Write to DMA Stream CR register */ - hdma->Instance->CR = tmp; - - /* Get the FCR register value */ - tmp = hdma->Instance->FCR; - - /* Clear Direct mode and FIFO threshold bits */ - tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); - - /* Prepare the DMA Stream FIFO configuration */ - tmp |= hdma->Init.FIFOMode; - - /* The FIFO threshold is not used when the FIFO mode is disabled */ - if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) - { - /* Get the FIFO threshold */ - tmp |= hdma->Init.FIFOThreshold; - - /* Check compatibility between FIFO threshold level and size of the memory burst */ - /* for INCR4, INCR8, INCR16 bursts */ - if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) - { - if (DMA_CheckFifoParam(hdma) != HAL_OK) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_PARAM; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - return HAL_ERROR; - } - } - } - - /* Write to DMA Stream FCR */ - hdma->Instance->FCR = tmp; - - /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate - DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ - regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); - - /* Clear all interrupt flags */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Initialize the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the DMA peripheral - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) -{ - DMA_Base_Registers *regs; - - /* Check the DMA peripheral state */ - if(hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the DMA peripheral state */ - if(hdma->State == HAL_DMA_STATE_BUSY) - { - /* Return error status */ - return HAL_BUSY; - } - - /* Check the parameters */ - assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); - - /* Disable the selected DMA Streamx */ - __HAL_DMA_DISABLE(hdma); - - /* Reset DMA Streamx control register */ - hdma->Instance->CR = 0U; - - /* Reset DMA Streamx number of data to transfer register */ - hdma->Instance->NDTR = 0U; - - /* Reset DMA Streamx peripheral address register */ - hdma->Instance->PAR = 0U; - - /* Reset DMA Streamx memory 0 address register */ - hdma->Instance->M0AR = 0U; - - /* Reset DMA Streamx memory 1 address register */ - hdma->Instance->M1AR = 0U; - - /* Reset DMA Streamx FIFO control register */ - hdma->Instance->FCR = (uint32_t)0x00000021U; - - /* Get DMA steam Base Address */ - regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Clean all callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferM1CpltCallback = NULL; - hdma->XferM1HalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - - /* Reset the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Reset the DMA state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and Start DMA transfer - (+) Configure the source, destination address and data length and - Start DMA transfer with interrupt - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Starts the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Start the DMA Transfer with interrupt enabled. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Configure the source, destination address and the data length */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Enable Common interrupts*/ - hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; - hdma->Instance->FCR |= DMA_IT_FE; - - if(hdma->XferHalfCpltCallback != NULL) - { - hdma->Instance->CR |= DMA_IT_HT; - } - - /* Enable the Peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - - return status; -} - -/** - * @brief Aborts the DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * - * @note After disabling a DMA Stream, a check for wait until the DMA Stream is - * effectively disabled is added. If a Stream is disabled - * while a data transfer is ongoing, the current data will be transferred - * and the Stream will be effectively disabled only after the transfer of - * this single data is finished. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) -{ - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - uint32_t tickstart = HAL_GetTick(); - - if(hdma->State != HAL_DMA_STATE_BUSY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - { - /* Disable all the transfer interrupts */ - hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); - hdma->Instance->FCR &= ~(DMA_IT_FE); - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA Stream is effectively disabled */ - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_TIMEOUT; - } - } - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Change the DMA state*/ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - } - return HAL_OK; -} - -/** - * @brief Aborts the DMA Transfer in Interrupt mode. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) -{ - if(hdma->State != HAL_DMA_STATE_BUSY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - return HAL_ERROR; - } - else - { - /* Set Abort State */ - hdma->State = HAL_DMA_STATE_ABORT; - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - } - - return HAL_OK; -} - -/** - * @brief Polling for transfer complete. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CompleteLevel Specifies the DMA level complete. - * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. - * This model could be used for debug purpose. - * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t mask_cpltlevel; - uint32_t tickstart = HAL_GetTick(); - uint32_t tmpisr; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs; - - if(HAL_DMA_STATE_BUSY != hdma->State) - { - /* No transfer ongoing */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - __HAL_UNLOCK(hdma); - return HAL_ERROR; - } - - /* Polling mode not supported in circular mode and double buffering mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Transfer Complete flag */ - mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - } - else - { - /* Half Transfer Complete flag */ - mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - } - - regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - tmpisr = regs->ISR; - - while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) - { - /* Check for the Timeout (Not applicable in circular mode)*/ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_TIMEOUT; - } - } - - /* Get the ISR register value */ - tmpisr = regs->ISR; - - if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - - /* Clear the transfer error flag */ - regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - } - - if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - - /* Clear the FIFO error flag */ - regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; - } - - if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) - { - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - - /* Clear the Direct Mode error flag */ - regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; - } - } - - if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) - { - if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) - { - HAL_DMA_Abort(hdma); - - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - - /* Change the DMA state */ - hdma->State= HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - - /* Get the level transfer complete flag */ - if(CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Clear the half transfer and transfer complete flags */ - regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - } - else - { - /* Clear the half transfer flag */ - regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; - } - - return status; -} - -/** - * @brief Handles DMA interrupt request. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval None - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) -{ - uint32_t tmpisr; - __IO uint32_t count = 0; - uint32_t timeout = SystemCoreClock / 9600; - - /* calculate DMA base and stream number */ - DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; - - tmpisr = regs->ISR; - - /* Transfer Error Interrupt management ***************************************/ - if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) - { - /* Disable the transfer error interrupt */ - hdma->Instance->CR &= ~(DMA_IT_TE); - - /* Clear the transfer error flag */ - regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TE; - } - } - /* FIFO Error Interrupt management ******************************************/ - if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) - { - /* Clear the FIFO error flag */ - regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_FE; - } - } - /* Direct Mode Error Interrupt management ***********************************/ - if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) - { - /* Clear the direct mode error flag */ - regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; - - /* Update error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DME; - } - } - /* Half Transfer Complete Interrupt management ******************************/ - if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) - { - /* Clear the half transfer complete flag */ - regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; - - /* Multi_Buffering mode enabled */ - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) - { - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) - { - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - /* Current memory buffer used is Memory 1 */ - else - { - if(hdma->XferM1HalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferM1HalfCpltCallback(hdma); - } - } - } - else - { - /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ - if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) - { - /* Disable the half transfer interrupt */ - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - if(hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - } - } - /* Transfer Complete Interrupt management ***********************************/ - if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) - { - if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) - { - /* Clear the transfer complete flag */ - regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; - - if(HAL_DMA_STATE_ABORT == hdma->State) - { - /* Disable all the transfer interrupts */ - hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); - hdma->Instance->FCR &= ~(DMA_IT_FE); - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR &= ~(DMA_IT_HT); - } - - /* Clear all interrupt flags at correct offset within the register */ - regs->IFCR = 0x3FU << hdma->StreamIndex; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - if(hdma->XferAbortCallback != NULL) - { - hdma->XferAbortCallback(hdma); - } - return; - } - - if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) - { - /* Current memory buffer used is Memory 0 */ - if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) - { - if(hdma->XferM1CpltCallback != NULL) - { - /* Transfer complete Callback for memory1 */ - hdma->XferM1CpltCallback(hdma); - } - } - /* Current memory buffer used is Memory 1 */ - else - { - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete Callback for memory0 */ - hdma->XferCpltCallback(hdma); - } - } - } - /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ - else - { - if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) - { - /* Disable the transfer complete interrupt */ - hdma->Instance->CR &= ~(DMA_IT_TC); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - } - - if(hdma->XferCpltCallback != NULL) - { - /* Transfer complete callback */ - hdma->XferCpltCallback(hdma); - } - } - } - } - - /* manage error case */ - if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) - { - if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) - { - hdma->State = HAL_DMA_STATE_ABORT; - - /* Disable the stream */ - __HAL_DMA_DISABLE(hdma); - - do - { - if (++count > timeout) - { - break; - } - } - while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - } - - if(hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } -} - -/** - * @brief Register callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifier - * a DMA_HandleTypeDef structure as parameter. - * @param pCallback pointer to private callbacsk function which has pointer to - * a DMA_HandleTypeDef structure as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) -{ - - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_M1CPLT_CB_ID: - hdma->XferM1CpltCallback = pCallback; - break; - - case HAL_DMA_XFER_M1HALFCPLT_CB_ID: - hdma->XferM1HalfCpltCallback = pCallback; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = pCallback; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = pCallback; - break; - - default: - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @brief UnRegister callbacks - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifier - * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - hdma->XferCpltCallback = NULL; - break; - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - hdma->XferHalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_M1CPLT_CB_ID: - hdma->XferM1CpltCallback = NULL; - break; - - case HAL_DMA_XFER_M1HALFCPLT_CB_ID: - hdma->XferM1HalfCpltCallback = NULL; - break; - - case HAL_DMA_XFER_ERROR_CB_ID: - hdma->XferErrorCallback = NULL; - break; - - case HAL_DMA_XFER_ABORT_CB_ID: - hdma->XferAbortCallback = NULL; - break; - - case HAL_DMA_XFER_ALL_CB_ID: - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferM1CpltCallback = NULL; - hdma->XferM1HalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - break; - - default: - status = HAL_ERROR; - break; - } - } - else - { - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return status; -} - -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * -@verbatim - =============================================================================== - ##### State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DMA state - (+) Get error code - -@endverbatim - * @{ - */ - -/** - * @brief Returns the DMA state. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL state - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) -{ - return hdma->State; -} - -/** - * @brief Return the DMA error code - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval DMA Error Code - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) -{ - return hdma->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMA_Private_Functions - * @{ - */ - -/** - * @brief Sets the DMA Transfer parameter. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Clear DBM bit */ - hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); - - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Memory to Peripheral */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Peripheral to Memory */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} - -/** - * @brief Returns the DMA Stream base address depending on stream number - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval Stream base address - */ -static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) -{ - uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; - - /* lookup table for necessary bitshift of flags within status registers */ - static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; - hdma->StreamIndex = flagBitshiftOffset[stream_number]; - - if (stream_number > 3U) - { - /* return pointer to HISR and HIFCR */ - hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); - } - else - { - /* return pointer to LISR and LIFCR */ - hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); - } - - return hdma->StreamBaseAddress; -} - -/** - * @brief Check compatibility between FIFO threshold level and size of the memory burst - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @retval HAL status - */ -static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = hdma->Init.FIFOThreshold; - - /* Memory Data size equal to Byte */ - if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_HALFFULL: - if (hdma->Init.MemBurst == DMA_MBURST_INC16) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_FULL: - break; - default: - break; - } - } - - /* Memory Data size equal to Half-Word */ - else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - status = HAL_ERROR; - break; - case DMA_FIFO_THRESHOLD_HALFFULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - case DMA_FIFO_THRESHOLD_FULL: - if (hdma->Init.MemBurst == DMA_MBURST_INC16) - { - status = HAL_ERROR; - } - break; - default: - break; - } - } - - /* Memory Data size equal to Word */ - else - { - switch (tmp) - { - case DMA_FIFO_THRESHOLD_1QUARTERFULL: - case DMA_FIFO_THRESHOLD_HALFFULL: - case DMA_FIFO_THRESHOLD_3QUARTERSFULL: - status = HAL_ERROR; - break; - case DMA_FIFO_THRESHOLD_FULL: - if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) - { - status = HAL_ERROR; - } - break; - default: - break; - } - } - - return status; -} - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma.c + * @author MCD Application Team + * @brief DMA HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access (DMA) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and errors functions + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable and configure the peripheral to be connected to the DMA Stream + (except for internal SRAM/FLASH memories: no initialization is + necessary) please refer to Reference manual for connection between peripherals + and DMA requests. + + (#) For a given Stream, program the required configuration through the following parameters: + Transfer Direction, Source and Destination data formats, + Circular, Normal or peripheral flow control mode, Stream Priority level, + Source and Destination Increment mode, FIFO mode and its Threshold (if needed), + Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function. + + -@- Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros: + __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE(). + + *** Polling mode IO operation *** + ================================= + [..] + (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source + address and destination address and the Length of data to be transferred. + (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this + case a fixed Timeout can be configured by User depending from his application. + (+) Use HAL_DMA_Abort() function to abort the current transfer. + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() + (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() + (+) Select Callbacks functions using HAL_DMA_RegisterCallback() + (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of + Source address and destination address and the Length of data to be transferred. In this + case the DMA interrupt is configured + (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine + (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can + add his own function by customization of function pointer XferCpltCallback and + XferErrorCallback (i.e a member of DMA handle structure). + [..] + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. + + (#) Use HAL_DMA_Abort_IT() function to abort the current transfer + + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + + -@- The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is + possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set + Half-Word data size for the peripheral to access its data register and set Word data size + for the Memory to gain in access time. Each two half words will be packed and written in + a single access to a Word in the Memory). + + -@- When FIFO is disabled, it is not allowed to configure different Data Sizes for Source + and Destination. In this case the Peripheral Data Size will be applied to both Source + and Destination. + + *** DMA HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DMA HAL driver. + + (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream. + (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream. + (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. + + [..] + (@) You can refer to the DMA HAL driver header file for more useful macros + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMA DMA + * @brief DMA HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register */ + __IO uint32_t Reserved0; + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register */ +} DMA_Base_Registers; + +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Constants + * @{ + */ + #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)5) /* 5 ms */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Private_Functions + * @{ + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @addtogroup DMA_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize the DMA Stream source + and destination addresses, incrementation and data sizes, transfer direction, + circular/normal mode selection, memory-to-memory mode selection and Stream priority value. + [..] + The HAL_DMA_Init() function follows the DMA configuration procedures as described in + reference manual. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and create the associated handle. + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + uint32_t tmp = 0U; + uint32_t tickstart = HAL_GetTick(); + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); + assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); + assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); + assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); + assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); + assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); + assert_param(IS_DMA_MODE(hdma->Init.Mode)); + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); + /* Check the memory burst, peripheral burst and FIFO threshold parameters only + when FIFO mode is enabled */ + if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) + { + assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); + assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); + assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); + + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + + /* Get the CR register value */ + tmp = hdma->Instance->CR; + + /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ + tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ + DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ + DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ + DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); + + /* Prepare the DMA Stream configuration */ + tmp |= hdma->Init.Channel | hdma->Init.Direction | + hdma->Init.PeriphInc | hdma->Init.MemInc | + hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | + hdma->Init.Mode | hdma->Init.Priority; + + /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get memory burst and peripheral burst */ + tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; + } + + /* Write to DMA Stream CR register */ + hdma->Instance->CR = tmp; + + /* Get the FCR register value */ + tmp = hdma->Instance->FCR; + + /* Clear Direct mode and FIFO threshold bits */ + tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); + + /* Prepare the DMA Stream FIFO configuration */ + tmp |= hdma->Init.FIFOMode; + + /* The FIFO threshold is not used when the FIFO mode is disabled */ + if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) + { + /* Get the FIFO threshold */ + tmp |= hdma->Init.FIFOThreshold; + + /* Check compatibility between FIFO threshold level and size of the memory burst */ + /* for INCR4, INCR8, INCR16 bursts */ + if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) + { + if (DMA_CheckFifoParam(hdma) != HAL_OK) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_PARAM; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + return HAL_ERROR; + } + } + } + + /* Write to DMA Stream FCR */ + hdma->Instance->FCR = tmp; + + /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate + DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the DMA peripheral + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + DMA_Base_Registers *regs; + + /* Check the DMA peripheral state */ + if(hdma == NULL) + { + return HAL_ERROR; + } + + /* Check the DMA peripheral state */ + if(hdma->State == HAL_DMA_STATE_BUSY) + { + /* Return error status */ + return HAL_BUSY; + } + + /* Check the parameters */ + assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Streamx */ + __HAL_DMA_DISABLE(hdma); + + /* Reset DMA Streamx control register */ + hdma->Instance->CR = 0U; + + /* Reset DMA Streamx number of data to transfer register */ + hdma->Instance->NDTR = 0U; + + /* Reset DMA Streamx peripheral address register */ + hdma->Instance->PAR = 0U; + + /* Reset DMA Streamx memory 0 address register */ + hdma->Instance->M0AR = 0U; + + /* Reset DMA Streamx memory 1 address register */ + hdma->Instance->M1AR = 0U; + + /* Reset DMA Streamx FIFO control register */ + hdma->Instance->FCR = (uint32_t)0x00000021U; + + /* Get DMA steam Base Address */ + regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Clean all callbacks */ + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + + /* Reset the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Reset the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group2 + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and Start DMA transfer + (+) Configure the source, destination address and data length and + Start DMA transfer with interrupt + (+) Abort DMA transfer + (+) Poll for transfer complete + (+) Handle DMA interrupt request + +@endverbatim + * @{ + */ + +/** + * @brief Starts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Start the DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Configure the source, destination address and the data length */ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if(hdma->XferHalfCpltCallback != NULL) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + + return status; +} + +/** + * @brief Aborts the DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * + * @note After disabling a DMA Stream, a check for wait until the DMA Stream is + * effectively disabled is added. If a Stream is disabled + * while a data transfer is ongoing, the current data will be transferred + * and the Stream will be effectively disabled only after the transfer of + * this single data is finished. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + uint32_t tickstart = HAL_GetTick(); + + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + else + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + /* Check if the DMA Stream is effectively disabled */ + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Change the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + } + return HAL_OK; +} + +/** + * @brief Aborts the DMA Transfer in Interrupt mode. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + if(hdma->State != HAL_DMA_STATE_BUSY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + return HAL_ERROR; + } + else + { + /* Set Abort State */ + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + } + + return HAL_OK; +} + +/** + * @brief Polling for transfer complete. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CompleteLevel Specifies the DMA level complete. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. + * This model could be used for debug purpose. + * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t mask_cpltlevel; + uint32_t tickstart = HAL_GetTick(); + uint32_t tmpisr; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs; + + if(HAL_DMA_STATE_BUSY != hdma->State) + { + /* No transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + __HAL_UNLOCK(hdma); + return HAL_ERROR; + } + + /* Polling mode not supported in circular mode and double buffering mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + } + else + { + /* Half Transfer Complete flag */ + mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + } + + regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + tmpisr = regs->ISR; + + while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) + { + /* Check for the Timeout (Not applicable in circular mode)*/ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_TIMEOUT; + } + } + + /* Get the ISR register value */ + tmpisr = regs->ISR; + + if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + } + + if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + + /* Clear the Direct Mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + } + } + + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + (void)HAL_DMA_Abort(hdma); + + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + /* Change the DMA state */ + hdma->State= HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + return HAL_ERROR; + } + } + + /* Get the level transfer complete flag */ + if(CompleteLevel == HAL_DMA_FULL_TRANSFER) + { + /* Clear the half transfer and transfer complete flags */ + regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + } + else + { + /* Clear the half transfer flag */ + regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; + } + + return status; +} + +/** + * @brief Handles DMA interrupt request. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + uint32_t tmpisr; + __IO uint32_t count = 0; + uint32_t timeout = SystemCoreClock / 9600; + + /* calculate DMA base and stream number */ + DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; + + tmpisr = regs->ISR; + + /* Transfer Error Interrupt management ***************************************/ + if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) + { + /* Disable the transfer error interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TE); + + /* Clear the transfer error flag */ + regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_TE; + } + } + /* FIFO Error Interrupt management ******************************************/ + if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) + { + /* Clear the FIFO error flag */ + regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_FE; + } + } + /* Direct Mode Error Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) + { + /* Clear the direct mode error flag */ + regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; + + /* Update error code */ + hdma->ErrorCode |= HAL_DMA_ERROR_DME; + } + } + /* Half Transfer Complete Interrupt management ******************************/ + if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) + { + /* Clear the half transfer complete flag */ + regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; + + /* Multi_Buffering mode enabled */ + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferM1HalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferM1HalfCpltCallback(hdma); + } + } + } + else + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the half transfer interrupt */ + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + if(hdma->XferHalfCpltCallback != NULL) + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + } + } + } + } + /* Transfer Complete Interrupt management ***********************************/ + if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) + { + if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) + { + /* Clear the transfer complete flag */ + regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; + + if(HAL_DMA_STATE_ABORT == hdma->State) + { + /* Disable all the transfer interrupts */ + hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); + hdma->Instance->FCR &= ~(DMA_IT_FE); + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR &= ~(DMA_IT_HT); + } + + /* Clear all interrupt flags at correct offset within the register */ + regs->IFCR = 0x3FU << hdma->StreamIndex; + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + if(hdma->XferAbortCallback != NULL) + { + hdma->XferAbortCallback(hdma); + } + return; + } + + if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) + { + /* Current memory buffer used is Memory 0 */ + if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) + { + if(hdma->XferM1CpltCallback != NULL) + { + /* Transfer complete Callback for memory1 */ + hdma->XferM1CpltCallback(hdma); + } + } + /* Current memory buffer used is Memory 1 */ + else + { + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete Callback for memory0 */ + hdma->XferCpltCallback(hdma); + } + } + } + /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */ + else + { + if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) + { + /* Disable the transfer complete interrupt */ + hdma->Instance->CR &= ~(DMA_IT_TC); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + } + + if(hdma->XferCpltCallback != NULL) + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + } + } + } + } + + /* manage error case */ + if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) + { + if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) + { + hdma->State = HAL_DMA_STATE_ABORT; + + /* Disable the stream */ + __HAL_DMA_DISABLE(hdma); + + do + { + if (++count > timeout) + { + break; + } + } + while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + + } + + if(hdma->XferErrorCallback != NULL) + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + } + } +} + +/** + * @brief Register callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifier + * a DMA_HandleTypeDef structure as parameter. + * @param pCallback pointer to private callbacsk function which has pointer to + * a DMA_HandleTypeDef structure as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)) +{ + + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = pCallback; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = pCallback; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = pCallback; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = pCallback; + break; + + default: + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @brief UnRegister callbacks + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param CallbackID User Callback identifier + * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + switch (CallbackID) + { + case HAL_DMA_XFER_CPLT_CB_ID: + hdma->XferCpltCallback = NULL; + break; + + case HAL_DMA_XFER_HALFCPLT_CB_ID: + hdma->XferHalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1CPLT_CB_ID: + hdma->XferM1CpltCallback = NULL; + break; + + case HAL_DMA_XFER_M1HALFCPLT_CB_ID: + hdma->XferM1HalfCpltCallback = NULL; + break; + + case HAL_DMA_XFER_ERROR_CB_ID: + hdma->XferErrorCallback = NULL; + break; + + case HAL_DMA_XFER_ABORT_CB_ID: + hdma->XferAbortCallback = NULL; + break; + + case HAL_DMA_XFER_ALL_CB_ID: + hdma->XferCpltCallback = NULL; + hdma->XferHalfCpltCallback = NULL; + hdma->XferM1CpltCallback = NULL; + hdma->XferM1HalfCpltCallback = NULL; + hdma->XferErrorCallback = NULL; + hdma->XferAbortCallback = NULL; + break; + + default: + status = HAL_ERROR; + break; + } + } + else + { + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hdma); + + return status; +} + +/** + * @} + */ + +/** @addtogroup DMA_Exported_Functions_Group3 + * +@verbatim + =============================================================================== + ##### State and Errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the DMA state + (+) Get error code + +@endverbatim + * @{ + */ + +/** + * @brief Returns the DMA state. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL state + */ +HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) +{ + return hdma->State; +} + +/** + * @brief Return the DMA error code + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval DMA Error Code + */ +uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) +{ + return hdma->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMA_Private_Functions + * @{ + */ + +/** + * @brief Sets the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Clear DBM bit */ + hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); + + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Memory to Peripheral */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Peripheral to Memory */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @brief Returns the DMA Stream base address depending on stream number + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval Stream base address + */ +static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) +{ + uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; + + /* lookup table for necessary bitshift of flags within status registers */ + static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U}; + hdma->StreamIndex = flagBitshiftOffset[stream_number]; + + if (stream_number > 3U) + { + /* return pointer to HISR and HIFCR */ + hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); + } + else + { + /* return pointer to LISR and LIFCR */ + hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); + } + + return hdma->StreamBaseAddress; +} + +/** + * @brief Check compatibility between FIFO threshold level and size of the memory burst + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @retval HAL status + */ +static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = hdma->Init.FIFOThreshold; + + /* Memory Data size equal to Byte */ + if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + break; + default: + break; + } + } + + /* Memory Data size equal to Half-Word */ + else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_HALFFULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + case DMA_FIFO_THRESHOLD_FULL: + if (hdma->Init.MemBurst == DMA_MBURST_INC16) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + /* Memory Data size equal to Word */ + else + { + switch (tmp) + { + case DMA_FIFO_THRESHOLD_1QUARTERFULL: + case DMA_FIFO_THRESHOLD_HALFFULL: + case DMA_FIFO_THRESHOLD_3QUARTERSFULL: + status = HAL_ERROR; + break; + case DMA_FIFO_THRESHOLD_FULL: + if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) + { + status = HAL_ERROR; + } + break; + default: + break; + } + } + + return status; +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c deleted file mode 100644 index 1ff3b63a..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma2d.c +++ /dev/null @@ -1,2146 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma2d.c - * @author MCD Application Team - * @brief DMA2D HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the DMA2D peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Program the required configuration through the following parameters: - the transfer mode, the output color mode and the output offset using - HAL_DMA2D_Init() function. - - (#) Program the required configuration through the following parameters: - the input color mode, the input color, the input alpha value, the alpha mode, - the red/blue swap mode, the inverted alpha mode and the input offset using - HAL_DMA2D_ConfigLayer() function for foreground or/and background layer. - - *** Polling mode IO operation *** - ================================= - [..] - (#) Configure pdata parameter (explained hereafter), destination and data length - and enable the transfer using HAL_DMA2D_Start(). - (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage - user can specify the value of timeout according to his end application. - - *** Interrupt mode IO operation *** - =================================== - [..] - (#) Configure pdata parameter, destination and data length and enable - the transfer using HAL_DMA2D_Start_IT(). - (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine. - (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can - add his own function by customization of function pointer XferCpltCallback (member - of DMA2D handle structure). - (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback - XferErrorCallback. - - -@- In Register-to-Memory transfer mode, pdata parameter is the register - color, in Memory-to-memory or Memory-to-Memory with pixel format - conversion pdata is the source address. - - -@- Configure the foreground source address, the background source address, - the destination and data length then Enable the transfer using - HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT() - in interrupt mode. - - -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions - are used if the memory to memory with blending transfer mode is selected. - - (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling - mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode. - - (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent(). - - (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two - consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime() - and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or - HAL_DMA2D_DisableDeadTime(). - - (#) The transfer can be suspended, resumed and aborted using the following - functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort(). - - (#) The CLUT loading can be suspended, resumed and aborted using the following - functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(), - HAL_DMA2D_CLUTLoading_Abort(). - - (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState(). - - (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError(). - - *** DMA2D HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DMA2D HAL driver : - - (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral. - (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags. - (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags. - (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts. - (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts. - (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not. - - *** Callback registration *** - =================================== - [..] - (#) The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback. - - (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks: - (+) XferCpltCallback : callback for transfer complete. - (+) XferErrorCallback : callback for transfer error. - (+) LineEventCallback : callback for line event. - (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. - (+) MspInitCallback : DMA2D MspInit. - (+) MspDeInitCallback : DMA2D MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. - @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) XferCpltCallback : callback for transfer complete. - (+) XferErrorCallback : callback for transfer error. - (+) LineEventCallback : callback for line event. - (+) CLUTLoadingCpltCallback : callback for CLUT loading completion. - (+) MspInitCallback : DMA2D MspInit. - (+) MspDeInitCallback : DMA2D MspDeInit. - - (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions: - examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback() - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the @ref HAL_DMA2D_Init - and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - Exception as well for Transfer Completion and Transfer Error callbacks that are not defined - as weak (overridden) functions. They must be defined by the user to be resorted to. - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit - or @ref HAL_DMA2D_Init function. - - When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. - - [..] - (@) You can refer to the DMA2D HAL driver header file for more useful macros - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -#ifdef HAL_DMA2D_MODULE_ENABLED -#if defined (DMA2D) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA2D DMA2D - * @brief DMA2D HAL module driver - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup DMA2D_Private_Constants DMA2D Private Constants - * @{ - */ - -/** @defgroup DMA2D_TimeOut DMA2D Time Out - * @{ - */ -#define DMA2D_TIMEOUT_ABORT (1000U) /*!< 1s */ -#define DMA2D_TIMEOUT_SUSPEND (1000U) /*!< 1s */ -/** - * @} - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup DMA2D_Private_Functions DMA2D Private Functions - * @{ - */ -static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, - uint32_t Height); -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions - * @{ - */ - -/** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DMA2D - (+) De-initialize the DMA2D - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA2D according to the specified - * parameters in the DMA2D_InitTypeDef and create the associated handle. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) -{ - /* Check the DMA2D peripheral state */ - if (hdma2d == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance)); - assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode)); - assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode)); - assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset)); -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted)); - assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap)); -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - if (hdma2d->State == HAL_DMA2D_STATE_RESET) - { - /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */ - hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; - hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; - if (hdma2d->MspInitCallback == NULL) - { - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; - } - - /* Init the low level hardware */ - hdma2d->MspInitCallback(hdma2d); - } -#else - if (hdma2d->State == HAL_DMA2D_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hdma2d->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_DMA2D_MspInit(hdma2d); - } -#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* DMA2D CR register configuration -------------------------------------------*/ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode); - - /* DMA2D OPFCCR register configuration ---------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode); - - /* DMA2D OOR register configuration ------------------------------------------*/ - MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset); -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/ - MODIFY_REG(hdma2d->Instance->OPFCCR, (DMA2D_OPFCCR_AI | DMA2D_OPFCCR_RBS), - ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | \ - (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos))); -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - - /* Update error code */ - hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; - - /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Deinitializes the DMA2D peripheral registers to their default reset - * values. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ - -HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d) -{ - - /* Check the DMA2D peripheral state */ - if (hdma2d == NULL) - { - return HAL_ERROR; - } - - /* Before aborting any DMA2D transfer or CLUT loading, check - first whether or not DMA2D clock is enabled */ - if (__HAL_RCC_DMA2D_IS_CLK_ENABLED()) - { - /* Abort DMA2D transfer if any */ - if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START) - { - if (HAL_DMA2D_Abort(hdma2d) != HAL_OK) - { - /* Issue when aborting DMA2D transfer */ - return HAL_ERROR; - } - } - else - { - /* Abort background CLUT loading if any */ - if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) - { - if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK) - { - /* Issue when aborting background CLUT loading */ - return HAL_ERROR; - } - } - else - { - /* Abort foreground CLUT loading if any */ - if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) - { - if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK) - { - /* Issue when aborting foreground CLUT loading */ - return HAL_ERROR; - } - } - } - } - } - - /* Reset DMA2D control registers*/ - hdma2d->Instance->CR = 0U; - hdma2d->Instance->IFCR = 0x3FU; - hdma2d->Instance->FGOR = 0U; - hdma2d->Instance->BGOR = 0U; - hdma2d->Instance->FGPFCCR = 0U; - hdma2d->Instance->BGPFCCR = 0U; - hdma2d->Instance->OPFCCR = 0U; - -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - - if (hdma2d->MspDeInitCallback == NULL) - { - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; - } - - /* DeInit the low level hardware */ - hdma2d->MspDeInitCallback(hdma2d); - -#else - /* Carry on with de-initialization of low level hardware */ - HAL_DMA2D_MspDeInit(hdma2d); -#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ - - /* Update error code */ - hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE; - - /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Initializes the DMA2D MSP. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ -__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma2d); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_DMA2D_MspInit can be implemented in the user file. - */ -} - -/** - * @brief DeInitializes the DMA2D MSP. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ -__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma2d); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_DMA2D_MspDeInit can be implemented in the user file. - */ -} - -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User DMA2D Callback - * To be used instead of the weak (overridden) predefined callback - * @param hdma2d DMA2D handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID - * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID - * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID - * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID - * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID - * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID - * @retval status - */ -HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, - pDMA2D_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hdma2d); - - if (HAL_DMA2D_STATE_READY == hdma2d->State) - { - switch (CallbackID) - { - case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : - hdma2d->XferCpltCallback = pCallback; - break; - - case HAL_DMA2D_TRANSFERERROR_CB_ID : - hdma2d->XferErrorCallback = pCallback; - break; - - case HAL_DMA2D_LINEEVENT_CB_ID : - hdma2d->LineEventCallback = pCallback; - break; - - case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : - hdma2d->CLUTLoadingCpltCallback = pCallback; - break; - - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = pCallback; - break; - - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_DMA2D_STATE_RESET == hdma2d->State) - { - switch (CallbackID) - { - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = pCallback; - break; - - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma2d); - return status; -} - -/** - * @brief Unregister a DMA2D Callback - * DMA2D Callback is redirected to the weak (overridden) predefined callback - * @param hdma2d DMA2D handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID - * @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID - * @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID - * @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID - * @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID - * @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID - * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID - * @retval status - */ -HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdma2d); - - if (HAL_DMA2D_STATE_READY == hdma2d->State) - { - switch (CallbackID) - { - case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID : - hdma2d->XferCpltCallback = NULL; - break; - - case HAL_DMA2D_TRANSFERERROR_CB_ID : - hdma2d->XferErrorCallback = NULL; - break; - - case HAL_DMA2D_LINEEVENT_CB_ID : - hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback; - break; - - case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID : - hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback; - break; - - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ - break; - - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ - break; - - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_DMA2D_STATE_RESET == hdma2d->State) - { - switch (CallbackID) - { - case HAL_DMA2D_MSPINIT_CB_ID : - hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */ - break; - - case HAL_DMA2D_MSPDEINIT_CB_ID : - hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */ - break; - - default : - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdma2d); - return status; -} -#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ - -/** - * @} - */ - - -/** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the pdata, destination address and data size then - start the DMA2D transfer. - (+) Configure the source for foreground and background, destination address - and data size then start a MultiBuffer DMA2D transfer. - (+) Configure the pdata, destination address and data size then - start the DMA2D transfer with interrupt. - (+) Configure the source for foreground and background, destination address - and data size then start a MultiBuffer DMA2D transfer with interrupt. - (+) Abort DMA2D transfer. - (+) Suspend DMA2D transfer. - (+) Resume DMA2D transfer. - (+) Enable CLUT transfer. - (+) Configure CLUT loading then start transfer in polling mode. - (+) Configure CLUT loading then start transfer in interrupt mode. - (+) Abort DMA2D CLUT loading. - (+) Suspend DMA2D CLUT loading. - (+) Resume DMA2D CLUT loading. - (+) Poll for transfer complete. - (+) handle DMA2D interrupt request. - (+) Transfer watermark callback. - (+) CLUT Transfer Complete callback. - - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA2D Transfer. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param pdata Configure the source memory Buffer address if - * Memory-to-Memory or Memory-to-Memory with pixel format - * conversion mode is selected, or configure - * the color value if Register-to-Memory mode is selected. - * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source - * to destination (expressed in number of pixels per line). - * @param Height The height of data to be transferred from source to destination (expressed in number of lines). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, - uint32_t Height) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); - - /* Enable the Peripheral */ - __HAL_DMA2D_ENABLE(hdma2d); - - return HAL_OK; -} - -/** - * @brief Start the DMA2D Transfer with interrupt enabled. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param pdata Configure the source memory Buffer address if - * the Memory-to-Memory or Memory-to-Memory with pixel format - * conversion mode is selected, or configure - * the color value if Register-to-Memory mode is selected. - * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source - * to destination (expressed in number of pixels per line). - * @param Height The height of data to be transferred from source to destination (expressed in number of lines). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, - uint32_t Height) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height); - - /* Enable the transfer complete, transfer error and configuration error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); - - /* Enable the Peripheral */ - __HAL_DMA2D_ENABLE(hdma2d); - - return HAL_OK; -} - -/** - * @brief Start the multi-source DMA2D Transfer. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param SrcAddress1 The source memory Buffer address for the foreground layer. - * @param SrcAddress2 The source memory Buffer address for the background layer. - * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source - * to destination (expressed in number of pixels per line). - * @param Height The height of data to be transferred from source to destination (expressed in number of lines). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, - uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure DMA2D Stream source2 address */ - WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); - - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); - - /* Enable the Peripheral */ - __HAL_DMA2D_ENABLE(hdma2d); - - return HAL_OK; -} - -/** - * @brief Start the multi-source DMA2D Transfer with interrupt enabled. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param SrcAddress1 The source memory Buffer address for the foreground layer. - * @param SrcAddress2 The source memory Buffer address for the background layer. - * @param DstAddress The destination memory Buffer address. - * @param Width The width of data to be transferred from source - * to destination (expressed in number of pixels per line). - * @param Height The height of data to be transferred from source to destination (expressed in number of lines). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, - uint32_t DstAddress, uint32_t Width, uint32_t Height) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LINE(Height)); - assert_param(IS_DMA2D_PIXEL(Width)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure DMA2D Stream source2 address */ - WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2); - - /* Configure the source, destination address and the data size */ - DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height); - - /* Enable the transfer complete, transfer error and configuration error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); - - /* Enable the Peripheral */ - __HAL_DMA2D_ENABLE(hdma2d); - - return HAL_OK; -} - -/** - * @brief Abort the DMA2D Transfer. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d) -{ - uint32_t tickstart; - - /* Abort the DMA2D transfer */ - /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no - effect on START bitvalue) */ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the DMA2D is effectively disabled */ - while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) - { - if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_TIMEOUT; - } - } - - /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE); - - /* Change the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Suspend the DMA2D Transfer. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d) -{ - uint32_t tickstart; - - /* Suspend the DMA2D transfer */ - /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no - effect on START bitvalue). */ - MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the DMA2D is effectively suspended */ - while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START) - { - if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ - if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) - { - hdma2d->State = HAL_DMA2D_STATE_SUSPEND; - } - else - { - /* Make sure SUSP bit is cleared since it is meaningless - when no transfer is on-going */ - CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - } - - return HAL_OK; -} - -/** - * @brief Resume the DMA2D Transfer. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d) -{ - /* Check the SUSP and START bits */ - if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START)) - { - /* Ongoing transfer is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - } - - /* Resume the DMA2D transfer */ - /* START bit is reset to make sure not to set it again, in the event the HW clears it - between the register read and the register write by the CPU (writing 0 has no - effect on START bitvalue). */ - CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START)); - - return HAL_OK; -} - - -/** - * @brief Enable the DMA2D CLUT Transfer. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - if (LayerIdx == DMA2D_BACKGROUND_LAYER) - { - /* Enable the background CLUT loading */ - SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); - } - else - { - /* Enable the foreground CLUT loading */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); - } - - return HAL_OK; -} - -/** - * @brief Start DMA2D CLUT Loading. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains - * the configuration information for the color look up table. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the CLUT of the background DMA2D layer */ - if (LayerIdx == DMA2D_BACKGROUND_LAYER) - { - /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT); - - /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); - - /* Enable the CLUT loading for the background */ - SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT); - - /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); - - /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); - } - - return HAL_OK; -} - -/** - * @brief Start DMA2D CLUT Loading with interrupt enabled. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains - * the configuration information for the color look up table. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, - uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the CLUT of the background DMA2D layer */ - if (LayerIdx == DMA2D_BACKGROUND_LAYER) - { - /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT); - - /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); - - /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); - - /* Enable the CLUT loading for the background */ - SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT); - - /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); - - /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); - - /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); - } - - return HAL_OK; -} - -/** - * @brief Start DMA2D CLUT Loading. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains - * the configuration information for the color look up table. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @note API obsolete and maintained for compatibility with legacy. User is - * invited to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from - * code compactness, code size and improved heap usage. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the CLUT of the background DMA2D layer */ - if (LayerIdx == DMA2D_BACKGROUND_LAYER) - { - /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); - - /* Enable the CLUT loading for the background */ - SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); - - /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); - } - - return HAL_OK; -} - -/** - * @brief Start DMA2D CLUT Loading with interrupt enabled. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains - * the configuration information for the color look up table. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @note API obsolete and maintained for compatibility with legacy. User is - * invited to resort to HAL_DMA2D_CLUTStartLoad_IT() instead to benefit - * from code compactness, code size and improved heap usage. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the CLUT of the background DMA2D layer */ - if (LayerIdx == DMA2D_BACKGROUND_LAYER) - { - /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); - - /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); - - /* Enable the CLUT loading for the background */ - SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); - - /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); - - /* Enable the CLUT loading for the foreground */ - SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START); - } - - return HAL_OK; -} - -/** - * @brief Abort the DMA2D CLUT loading. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - uint32_t tickstart; - const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ - - /* Abort the CLUT loading */ - SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT); - - /* If foreground CLUT loading is considered, update local variables */ - if (LayerIdx == DMA2D_FOREGROUND_LAYER) - { - reg = &(hdma2d->Instance->FGPFCCR); - } - - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the CLUT loading is aborted */ - while ((*reg & DMA2D_BGPFCCR_START) != 0U) - { - if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_TIMEOUT; - } - } - - /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE); - - /* Change the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Suspend the DMA2D CLUT loading. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - uint32_t tickstart; - uint32_t loadsuspended; - const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */ - - /* Suspend the CLUT loading */ - SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - - /* If foreground CLUT loading is considered, update local variables */ - if (LayerIdx == DMA2D_FOREGROUND_LAYER) - { - reg = &(hdma2d->Instance->FGPFCCR); - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the CLUT loading is suspended */ - /* 1st condition: Suspend Check */ - loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL; - /* 2nd condition: Not Start Check */ - loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL; - while (loadsuspended == 0UL) - { - if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - /* 1st condition: Suspend Check */ - loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL; - /* 2nd condition: Not Start Check */ - loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL; - } - - /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */ - if ((*reg & DMA2D_BGPFCCR_START) != 0U) - { - hdma2d->State = HAL_DMA2D_STATE_SUSPEND; - } - else - { - /* Make sure SUSP bit is cleared since it is meaningless - when no transfer is on-going */ - CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - } - - return HAL_OK; -} - -/** - * @brief Resume the DMA2D CLUT loading. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - /* Check the SUSP and START bits for background or foreground CLUT loading */ - if (LayerIdx == DMA2D_BACKGROUND_LAYER) - { - /* Background CLUT loading suspension check */ - if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) - { - if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START) - { - /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - } - } - } - else - { - /* Foreground CLUT loading suspension check */ - if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) - { - if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START) - { - /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - } - } - } - - /* Resume the CLUT loading */ - CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP); - - return HAL_OK; -} - - -/** - - * @brief Polling for transfer complete or CLUT loading. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t layer_start; - __IO uint32_t isrflags = 0x0U; - - /* Polling for DMA2D transfer */ - if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U) - { - isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) - { - if ((isrflags & DMA2D_FLAG_CE) != 0U) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; - } - if ((isrflags & DMA2D_FLAG_TE) != 0U) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; - } - /* Clear the transfer and configuration error flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE); - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_TIMEOUT; - } - } - } - } - /* Polling for CLUT loading (foreground or background) */ - layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START; - layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START; - if (layer_start != 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U) - { - isrflags = READ_REG(hdma2d->Instance->ISR); - if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U) - { - if ((isrflags & DMA2D_FLAG_CAE) != 0U) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; - } - if ((isrflags & DMA2D_FLAG_CE) != 0U) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; - } - if ((isrflags & DMA2D_FLAG_TE) != 0U) - { - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; - } - /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE); - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_ERROR; - } - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT; - - /* Change the DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_TIMEOUT; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_TIMEOUT; - } - } - } - } - - /* Clear the transfer complete and CLUT loading flags */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC); - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} -/** - * @brief Handle DMA2D interrupt request. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL status - */ -void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d) -{ - uint32_t isrflags = READ_REG(hdma2d->Instance->ISR); - uint32_t crflags = READ_REG(hdma2d->Instance->CR); - - /* Transfer Error Interrupt management ***************************************/ - if ((isrflags & DMA2D_FLAG_TE) != 0U) - { - if ((crflags & DMA2D_IT_TE) != 0U) - { - /* Disable the transfer Error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE; - - /* Clear the transfer error flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE); - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - if (hdma2d->XferErrorCallback != NULL) - { - /* Transfer error Callback */ - hdma2d->XferErrorCallback(hdma2d); - } - } - } - /* Configuration Error Interrupt management **********************************/ - if ((isrflags & DMA2D_FLAG_CE) != 0U) - { - if ((crflags & DMA2D_IT_CE) != 0U) - { - /* Disable the Configuration Error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE); - - /* Clear the Configuration error flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE; - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - if (hdma2d->XferErrorCallback != NULL) - { - /* Transfer error Callback */ - hdma2d->XferErrorCallback(hdma2d); - } - } - } - /* CLUT access Error Interrupt management ***********************************/ - if ((isrflags & DMA2D_FLAG_CAE) != 0U) - { - if ((crflags & DMA2D_IT_CAE) != 0U) - { - /* Disable the CLUT access error interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE); - - /* Clear the CLUT access error flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE; - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - if (hdma2d->XferErrorCallback != NULL) - { - /* Transfer error Callback */ - hdma2d->XferErrorCallback(hdma2d); - } - } - } - /* Transfer watermark Interrupt management **********************************/ - if ((isrflags & DMA2D_FLAG_TW) != 0U) - { - if ((crflags & DMA2D_IT_TW) != 0U) - { - /* Disable the transfer watermark interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW); - - /* Clear the transfer watermark flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW); - - /* Transfer watermark Callback */ -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - hdma2d->LineEventCallback(hdma2d); -#else - HAL_DMA2D_LineEventCallback(hdma2d); -#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ - - } - } - /* Transfer Complete Interrupt management ************************************/ - if ((isrflags & DMA2D_FLAG_TC) != 0U) - { - if ((crflags & DMA2D_IT_TC) != 0U) - { - /* Disable the transfer complete interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC); - - /* Clear the transfer complete flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - if (hdma2d->XferCpltCallback != NULL) - { - /* Transfer complete Callback */ - hdma2d->XferCpltCallback(hdma2d); - } - } - } - /* CLUT Transfer Complete Interrupt management ******************************/ - if ((isrflags & DMA2D_FLAG_CTC) != 0U) - { - if ((crflags & DMA2D_IT_CTC) != 0U) - { - /* Disable the CLUT transfer complete interrupt */ - __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC); - - /* Clear the CLUT transfer complete flag */ - __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC); - - /* Update error code */ - hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE; - - /* Change DMA2D state */ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - /* CLUT Transfer complete Callback */ -#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) - hdma2d->CLUTLoadingCpltCallback(hdma2d); -#else - HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d); -#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ - } - } - -} - -/** - * @brief Transfer watermark callback. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ -__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma2d); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_DMA2D_LineEventCallback can be implemented in the user file. - */ -} - -/** - * @brief CLUT Transfer Complete callback. - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval None - */ -__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma2d); - - /* NOTE : This function should not be modified; when the callback is needed, - the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the DMA2D foreground or background layer parameters. - (+) Configure the DMA2D CLUT transfer. - (+) Configure the line watermark - (+) Configure the dead time value. - (+) Enable or disable the dead time value functionality. - - -@endverbatim - * @{ - */ - -/** - * @brief Configure the DMA2D Layer according to the specified - * parameters in the DMA2D_HandleTypeDef. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx) -{ - DMA2D_LayerCfgTypeDef *pLayerCfg; - uint32_t regMask; - uint32_t regValue; - - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset)); - if (hdma2d->Init.Mode != DMA2D_R2M) - { - assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode)); - if (hdma2d->Init.Mode != DMA2D_M2M) - { - assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode)); - } - } -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted)); - assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap)); -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - pLayerCfg = &hdma2d->LayerCfg[LayerIdx]; - - /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */ -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) | \ - (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos); - regMask = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS); -#else - regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos); - regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA; -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - - if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA); - } - else - { - regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos); - } - - /* Configure the background DMA2D layer */ - if (LayerIdx == DMA2D_BACKGROUND_LAYER) - { - /* Write DMA2D BGPFCCR register */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue); - - /* DMA2D BGOR register configuration -------------------------------------*/ - WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset); - - /* DMA2D BGCOLR register configuration -------------------------------------*/ - if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \ - DMA2D_BGCOLR_RED)); - } - } - /* Configure the foreground DMA2D layer */ - else - { - - - /* Write DMA2D FGPFCCR register */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue); - - /* DMA2D FGOR register configuration -------------------------------------*/ - WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset); - - /* DMA2D FGCOLR register configuration -------------------------------------*/ - if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8)) - { - WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \ - DMA2D_FGCOLR_RED)); - } - } - /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Configure the DMA2D CLUT Transfer. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains - * the configuration information for the color look up table. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1) - * @note API obsolete and maintained for compatibility with legacy. User is invited - * to resort to HAL_DMA2D_CLUTStartLoad() instead to benefit from code compactness, - * code size and improved heap usage. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_DMA2D_LAYER(LayerIdx)); - assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode)); - assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size)); - - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Configure the CLUT of the background DMA2D layer */ - if (LayerIdx == DMA2D_BACKGROUND_LAYER) - { - /* Write background CLUT memory address */ - WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write background CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos))); - } - /* Configure the CLUT of the foreground DMA2D layer */ - else - { - /* Write foreground CLUT memory address */ - WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT); - - /* Write foreground CLUT size and CLUT color mode */ - MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM), - ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos))); - } - - /* Set the DMA2D state to Ready*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - - -/** - * @brief Configure the line watermark. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @param Line Line Watermark configuration (maximum 16-bit long value expected). - * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt. - * @note The transfer watermark interrupt is disabled once it has occurred. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line) -{ - /* Check the parameters */ - if (Line > DMA2D_LWR_LW) - { - return HAL_ERROR; - } - else - { - /* Process locked */ - __HAL_LOCK(hdma2d); - - /* Change DMA2D peripheral state */ - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Sets the Line watermark configuration */ - WRITE_REG(hdma2d->Instance->LWR, Line); - - /* Enable the Line interrupt */ - __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW); - - /* Initialize the DMA2D state*/ - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; - } -} - -/** - * @brief Enable DMA2D dead time feature. - * @param hdma2d DMA2D handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d) -{ - /* Process Locked */ - __HAL_LOCK(hdma2d); - - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Set DMA2D_AMTCR EN bit */ - SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); - - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Disable DMA2D dead time feature. - * @param hdma2d DMA2D handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d) -{ - /* Process Locked */ - __HAL_LOCK(hdma2d); - - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Clear DMA2D_AMTCR EN bit */ - CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN); - - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @brief Configure dead time. - * @note The dead time value represents the guaranteed minimum number of cycles between - * two consecutive transactions on the AHB bus. - * @param hdma2d DMA2D handle. - * @param DeadTime dead time value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime) -{ - /* Process Locked */ - __HAL_LOCK(hdma2d); - - hdma2d->State = HAL_DMA2D_STATE_BUSY; - - /* Set DMA2D_AMTCR DT field */ - MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos)); - - hdma2d->State = HAL_DMA2D_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma2d); - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to: - (+) Get the DMA2D state - (+) Get the DMA2D error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the DMA2D state - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the DMA2D. - * @retval HAL state - */ -HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d) -{ - return hdma2d->State; -} - -/** - * @brief Return the DMA2D error code - * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for DMA2D. - * @retval DMA2D Error Code - */ -uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d) -{ - return hdma2d->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup DMA2D_Private_Functions DMA2D Private Functions - * @{ - */ - -/** - * @brief Set the DMA2D transfer parameters. - * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains - * the configuration information for the specified DMA2D. - * @param pdata The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param Width The width of data to be transferred from source to destination. - * @param Height The height of data to be transferred from source to destination. - * @retval HAL status - */ -static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, - uint32_t Height) -{ - uint32_t tmp; - uint32_t tmp1; - uint32_t tmp2; - uint32_t tmp3; - uint32_t tmp4; - - /* Configure DMA2D data size */ - MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos))); - - /* Configure DMA2D destination address */ - WRITE_REG(hdma2d->Instance->OMAR, DstAddress); - - /* Register to memory DMA2D mode selected */ - if (hdma2d->Init.Mode == DMA2D_R2M) - { - tmp1 = pdata & DMA2D_OCOLR_ALPHA_1; - tmp2 = pdata & DMA2D_OCOLR_RED_1; - tmp3 = pdata & DMA2D_OCOLR_GREEN_1; - tmp4 = pdata & DMA2D_OCOLR_BLUE_1; - - /* Prepare the value to be written to the OCOLR register according to the color mode */ - if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888) - { - tmp = (tmp3 | tmp2 | tmp1 | tmp4); - } - else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888) - { - tmp = (tmp3 | tmp2 | tmp4); - } - else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565) - { - tmp2 = (tmp2 >> 19U); - tmp3 = (tmp3 >> 10U); - tmp4 = (tmp4 >> 3U); - tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4); - } - else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555) - { - tmp1 = (tmp1 >> 31U); - tmp2 = (tmp2 >> 19U); - tmp3 = (tmp3 >> 11U); - tmp4 = (tmp4 >> 3U); - tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4); - } - else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */ - { - tmp1 = (tmp1 >> 28U); - tmp2 = (tmp2 >> 20U); - tmp3 = (tmp3 >> 12U); - tmp4 = (tmp4 >> 4U); - tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4); - } - /* Write to DMA2D OCOLR register */ - WRITE_REG(hdma2d->Instance->OCOLR, tmp); - } - else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */ - { - /* Configure DMA2D source address */ - WRITE_REG(hdma2d->Instance->FGMAR, pdata); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* DMA2D */ -#endif /* HAL_DMA2D_MODULE_ENABLED */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c index 8aadcc44..6f8634db 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dma_ex.c @@ -1,308 +1,308 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dma_ex.c - * @author MCD Application Team - * @brief DMA Extension HAL module driver - * This file provides firmware functions to manage the following - * functionalities of the DMA Extension peripheral: - * + Extended features functions - * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The DMA Extension HAL driver can be used as follows: - (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function - for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. - - -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. - -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. - -@- In Multi (Double) buffer mode, it is possible to update the base address for - the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @brief DMA Extended HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private Constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup DMAEx_Private_Functions - * @{ - */ - -static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); - -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @addtogroup DMAEx_Exported_Functions - * @{ - */ - - -/** @addtogroup DMAEx_Exported_Functions_Group1 - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the source, destination address and data length and - Start MultiBuffer DMA transfer - (+) Configure the source, destination address and data length and - Start MultiBuffer DMA transfer with interrupt - (+) Change on the fly the memory0 or memory1 address. - -@endverbatim - * @{ - */ - - -/** - * @brief Starts the multi_buffer DMA Transfer. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Memory-to-memory transfer not supported in double buffering mode */ - if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - status = HAL_ERROR; - } - else - { - /* Process Locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Enable the double buffer mode */ - hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - - /* Configure DMA Stream destination address */ - hdma->Instance->M1AR = SecondMemAddress; - - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Return error status */ - status = HAL_BUSY; - } - } - return status; -} - -/** - * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_DMA_BUFFER_SIZE(DataLength)); - - /* Memory-to-memory transfer not supported in double buffering mode */ - if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) - { - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hdma); - - if(HAL_DMA_STATE_READY == hdma->State) - { - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Initialize the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Enable the Double buffer mode */ - hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; - - /* Configure DMA Stream destination address */ - hdma->Instance->M1AR = SecondMemAddress; - - /* Configure the source, destination address and the data length */ - DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); - __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); - - /* Enable Common interrupts*/ - hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; - hdma->Instance->FCR |= DMA_IT_FE; - - if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) - { - hdma->Instance->CR |= DMA_IT_HT; - } - - /* Enable the peripheral */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - /* Return error status */ - status = HAL_BUSY; - } - return status; -} - -/** - * @brief Change the memory0 or memory1 address on the fly. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param Address The new address - * @param memory the memory to be changed, This parameter can be one of - * the following values: - * MEMORY0 / - * MEMORY1 - * @note The MEMORY0 address can be changed only when the current transfer use - * MEMORY1 and the MEMORY1 address can be changed only when the current - * transfer use MEMORY0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) -{ - if(memory == MEMORY0) - { - /* change the memory0 address */ - hdma->Instance->M0AR = Address; - } - else - { - /* change the memory1 address */ - hdma->Instance->M1AR = Address; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup DMAEx_Private_Functions - * @{ - */ - -/** - * @brief Set the DMA Transfer parameter. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA Stream. - * @param SrcAddress The source memory Buffer address - * @param DstAddress The destination memory Buffer address - * @param DataLength The length of data to be transferred from source to destination - * @retval HAL status - */ -static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) -{ - /* Configure DMA Stream data length */ - hdma->Instance->NDTR = DataLength; - - /* Peripheral to Memory */ - if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Configure DMA Stream destination address */ - hdma->Instance->PAR = DstAddress; - - /* Configure DMA Stream source address */ - hdma->Instance->M0AR = SrcAddress; - } - /* Memory to Peripheral */ - else - { - /* Configure DMA Stream source address */ - hdma->Instance->PAR = SrcAddress; - - /* Configure DMA Stream destination address */ - hdma->Instance->M0AR = DstAddress; - } -} - -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_dma_ex.c + * @author MCD Application Team + * @brief DMA Extension HAL module driver + * This file provides firmware functions to manage the following + * functionalities of the DMA Extension peripheral: + * + Extended features functions + * + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The DMA Extension HAL driver can be used as follows: + (+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function + for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode. + + -@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed. + -@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default. + -@- In Multi (Double) buffer mode, it is possible to update the base address for + the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup DMAEx DMAEx + * @brief DMA Extended HAL module driver + * @{ + */ + +#ifdef HAL_DMA_MODULE_ENABLED + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private Constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @addtogroup DMAEx_Exported_Functions + * @{ + */ + + +/** @addtogroup DMAEx_Exported_Functions_Group1 + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer + (+) Configure the source, destination address and data length and + Start MultiBuffer DMA transfer with interrupt + (+) Change on the fly the memory0 or memory1 address. + +@endverbatim + * @{ + */ + + +/** + * @brief Starts the multi_buffer DMA Transfer. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + status = HAL_ERROR; + } + else + { + /* Process Locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Enable the double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Return error status */ + status = HAL_BUSY; + } + } + return status; +} + +/** + * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Memory-to-memory transfer not supported in double buffering mode */ + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + { + hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hdma); + + if(HAL_DMA_STATE_READY == hdma->State) + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + + /* Enable the Double buffer mode */ + hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM; + + /* Configure DMA Stream destination address */ + hdma->Instance->M1AR = SecondMemAddress; + + /* Configure the source, destination address and the data length */ + DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); + + /* Clear all flags */ + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); + __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); + + /* Enable Common interrupts*/ + hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; + hdma->Instance->FCR |= DMA_IT_FE; + + if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) + { + hdma->Instance->CR |= DMA_IT_HT; + } + + /* Enable the peripheral */ + __HAL_DMA_ENABLE(hdma); + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdma); + + /* Return error status */ + status = HAL_BUSY; + } + return status; +} + +/** + * @brief Change the memory0 or memory1 address on the fly. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of + * the following values: + * MEMORY0 / + * MEMORY1 + * @note The MEMORY0 address can be changed only when the current transfer use + * MEMORY1 and the MEMORY1 address can be changed only when the current + * transfer use MEMORY0. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory) +{ + if(memory == MEMORY0) + { + /* change the memory0 address */ + hdma->Instance->M0AR = Address; + } + else + { + /* change the memory1 address */ + hdma->Instance->M1AR = Address; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup DMAEx_Private_Functions + * @{ + */ + +/** + * @brief Set the DMA Transfer parameter. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Stream. + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + /* Configure DMA Stream data length */ + hdma->Instance->NDTR = DataLength; + + /* Peripheral to Memory */ + if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + { + /* Configure DMA Stream destination address */ + hdma->Instance->PAR = DstAddress; + + /* Configure DMA Stream source address */ + hdma->Instance->M0AR = SrcAddress; + } + /* Memory to Peripheral */ + else + { + /* Configure DMA Stream source address */ + hdma->Instance->PAR = SrcAddress; + + /* Configure DMA Stream destination address */ + hdma->Instance->M0AR = DstAddress; + } +} + +/** + * @} + */ + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c deleted file mode 100644 index bc55f82f..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dsi.c +++ /dev/null @@ -1,3172 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_dsi.c - * @author MCD Application Team - * @brief DSI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the DSI peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The DSI HAL driver can be used as follows: - - (#) Declare a DSI_HandleTypeDef handle structure, for example: DSI_HandleTypeDef hdsi; - - (#) Initialize the DSI low level resources by implementing the HAL_DSI_MspInit() API: - (##) Enable the DSI interface clock - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the DSI interrupt priority - (+++) Enable the NVIC DSI IRQ Channel - - (#) Initialize the DSI Host peripheral, the required PLL parameters, number of lances and - TX Escape clock divider by calling the HAL_DSI_Init() API which calls HAL_DSI_MspInit(). - - *** Configuration *** - ========================= - [..] - (#) Use HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted - command mode. - - (#) When operating in video mode , use HAL_DSI_ConfigVideoMode() to configure the DSI host. - - (#) Function HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. - - (#) To configure the DSI PHY timings parameters, use function HAL_DSI_ConfigPhyTimer(). - - (#) The DSI Host can be started/stopped using respectively functions HAL_DSI_Start() and HAL_DSI_Stop(). - Functions HAL_DSI_ShortWrite(), HAL_DSI_LongWrite() and HAL_DSI_Read() allows respectively - to write DSI short packets, long packets and to read DSI packets. - - (#) The DSI Host Offers two Low power modes : - (++) Low Power Mode on data lanes only: Only DSI data lanes are shut down. - It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPMData() - and HAL_DSI_ExitULPMData() - - (++) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. - It is possible to enter/exit from this mode using respectively functions HAL_DSI_EnterULPM() - and HAL_DSI_ExitULPM() - - (#) To control DSI state you can use the following function: HAL_DSI_GetState() - - *** Error management *** - ======================== - [..] - (#) User can select the DSI errors to be reported/monitored using function HAL_DSI_ConfigErrorMonitor() - When an error occurs, the callback HAL_DSI_ErrorCallback() is asserted and then user can retrieve - the error code by calling function HAL_DSI_GetError() - - *** DSI HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in DSI HAL driver. - - (+) __HAL_DSI_ENABLE: Enable the DSI Host. - (+) __HAL_DSI_DISABLE: Disable the DSI Host. - (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper. - (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper. - (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL. - (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL. - (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator. - (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator. - (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags. - (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags. - (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts. - (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts. - (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not. - - [..] - (@) You can refer to the DSI HAL driver header file for more useful macros - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function HAL_DSI_RegisterCallback() to register a callback. - - [..] - Function HAL_DSI_RegisterCallback() allows to register following callbacks: - (+) TearingEffectCallback : DSI Tearing Effect Callback. - (+) EndOfRefreshCallback : DSI End Of Refresh Callback. - (+) ErrorCallback : DSI Error Callback - (+) MspInitCallback : DSI MspInit. - (+) MspDeInitCallback : DSI MspDeInit. - [..] - This function takes as parameters the HAL peripheral handle, the callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_DSI_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the callback ID. - [..] - This function allows to reset following callbacks: - (+) TearingEffectCallback : DSI Tearing Effect Callback. - (+) EndOfRefreshCallback : DSI End Of Refresh Callback. - (+) ErrorCallback : DSI Error Callback - (+) MspInitCallback : DSI MspInit. - (+) MspDeInitCallback : DSI MspDeInit. - - [..] - By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_DSI_TearingEffectCallback(), HAL_DSI_EndOfRefreshCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (overridden) functions in the HAL_DSI_Init() - and HAL_DSI_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_DSI_Init() and HAL_DSI_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_DSI_RegisterCallback() before calling HAL_DSI_DeInit() - or HAL_DSI_Init() function. - - [..] - When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_DSI_MODULE_ENABLED - -#if defined(DSI) - -/** @addtogroup DSI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @addtogroup DSI_Private_Constants - * @{ - */ -#define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */ - -#define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ - DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ - DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ - DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) -#define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) -#define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX -#define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX -#define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) -#define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE -#define DSI_ERROR_PSE_MASK DSI_ISR1_PSE -#define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE -#define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE -#define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, - uint32_t Data1); - -static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t Param1, - uint32_t Param2); -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DSI_Private_Functions DSI Private Functions - * @{ - */ -/** - * @brief Generic DSI packet header configuration - * @param DSIx Pointer to DSI register base - * @param ChannelID Virtual channel ID of the header packet - * @param DataType Packet data type of the header packet - * This parameter can be any value of : - * @arg DSI_SHORT_WRITE_PKT_Data_Type - * @arg DSI_LONG_WRITE_PKT_Data_Type - * @arg DSI_SHORT_READ_PKT_Data_Type - * @arg DSI_MAX_RETURN_PKT_SIZE - * @param Data0 Word count LSB - * @param Data1 Word count MSB - * @retval None - */ -static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, - uint32_t ChannelID, - uint32_t DataType, - uint32_t Data0, - uint32_t Data1) -{ - /* Update the DSI packet header with new information */ - DSIx->GHCR = (DataType | (ChannelID << 6U) | (Data0 << 8U) | (Data1 << 16U)); -} - -/** - * @brief write short DCS or short Generic command - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ChannelID Virtual channel ID. - * @param Mode DSI short packet data type. - * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type. - * @param Param1 DSC command or first generic parameter. - * This parameter can be any value of @arg DSI_DCS_Command or a - * generic command code. - * @param Param2 DSC parameter or second generic parameter. - * @retval HAL status - */ -static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t Param1, - uint32_t Param2) -{ - uint32_t tickstart; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for Command FIFO Empty */ - while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the packet to send a short DCS command with 0 or 1 parameter */ - /* Update the DSI packet header with new information */ - hdsi->Instance->GHCR = (Mode | (ChannelID << 6U) | (Param1 << 8U) | (Param2 << 16U)); - - return HAL_OK; -} - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DSI_Exported_Functions - * @{ - */ - -/** @defgroup DSI_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the DSI - (+) De-initialize the DSI - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the DSI according to the specified - * parameters in the DSI_InitTypeDef and create the associated handle. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains - * the PLL Clock structure definition for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) -{ - uint32_t tickstart; - uint32_t unitIntervalx4; - uint32_t tempIDF; - - /* Check the DSI handle allocation */ - if (hdsi == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); - assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); - assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); - assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); - assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); - -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) - if (hdsi->State == HAL_DSI_STATE_RESET) - { - /* Reset the DSI callback to the legacy weak callbacks */ - hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ - hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ - hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hdsi->MspInitCallback == NULL) - { - hdsi->MspInitCallback = HAL_DSI_MspInit; - } - /* Initialize the low level hardware */ - hdsi->MspInitCallback(hdsi); - } -#else - if (hdsi->State == HAL_DSI_STATE_RESET) - { - /* Initialize the low level hardware */ - HAL_DSI_MspInit(hdsi); - } -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - - /* Change DSI peripheral state */ - hdsi->State = HAL_DSI_STATE_BUSY; - - /**************** Turn on the regulator and enable the DSI PLL ****************/ - - /* Enable the regulator */ - __HAL_DSI_REG_ENABLE(hdsi); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the regulator is ready */ - while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set the PLL division factors */ - hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); - hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ - ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \ - ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos)); - - /* Enable the DSI PLL */ - __HAL_DSI_PLL_ENABLE(hdsi); - - /* Requires min of 400us delay before reading the PLLLS flag */ - /* 1ms delay is inserted that is the minimum HAL delay granularity */ - HAL_Delay(1); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for the lock of the PLL */ - while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - __HAL_DSI_ENABLE(hdsi); - - /************************ Set the DSI clock parameters ************************/ - /* Set the TX escape clock division factor */ - hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; - hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; - - /*************************** Set the PHY parameters ***************************/ - /* D-PHY clock and digital enable*/ - hdsi->Instance->PCTLR |= DSI_PCTLR_DEN; - - hdsi->Instance->PCTLR |= DSI_PCTLR_CKE; - - - /* Configure the number of active data lanes */ - hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; - hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; - - /* Get tick */ - tickstart = HAL_GetTick(); - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | DSI_PSR_PSSC)) - { - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else - { - while ((hdsi->Instance->PSR & (DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_PSSC)) != (DSI_PSR_PSS0 | \ - DSI_PSR_PSS1 | DSI_PSR_PSSC)) - { - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - - /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ - /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ - /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ - tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; - unitIntervalx4 = (4000000U * tempIDF * ((1UL << (0x3U & PLLInit->PLLODF)))) / ((HSE_VALUE / 1000U) * PLLInit->PLLNDIV); - - /* Set the bit period in high-speed mode */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; - hdsi->Instance->WPCR[0U] |= unitIntervalx4; - - /****************************** Error management *****************************/ - - /* Disable all error interrupts and reset the Error Mask */ - hdsi->Instance->IER[0U] = 0U; - hdsi->Instance->IER[1U] = 0U; - hdsi->ErrorMsk = 0U; - - __HAL_DSI_DISABLE(hdsi); - - /* Clock lane configuration */ - hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); - hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); - - /* Initialize the error code */ - hdsi->ErrorCode = HAL_DSI_ERROR_NONE; - - /* Initialize the DSI state*/ - hdsi->State = HAL_DSI_STATE_READY; - - return HAL_OK; -} - -/** - * @brief De-initializes the DSI peripheral registers to their default reset - * values. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) -{ - /* Check the DSI handle allocation */ - if (hdsi == NULL) - { - return HAL_ERROR; - } - - /* Change DSI peripheral state */ - hdsi->State = HAL_DSI_STATE_BUSY; - - /* Disable the DSI wrapper */ - __HAL_DSI_WRAPPER_DISABLE(hdsi); - - /* Disable the DSI host */ - __HAL_DSI_DISABLE(hdsi); - - /* D-PHY clock and digital disable */ - hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); - - /* Turn off the DSI PLL */ - __HAL_DSI_PLL_DISABLE(hdsi); - - /* Disable the regulator */ - __HAL_DSI_REG_DISABLE(hdsi); - -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) - if (hdsi->MspDeInitCallback == NULL) - { - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; - } - /* DeInit the low level hardware */ - hdsi->MspDeInitCallback(hdsi); -#else - /* DeInit the low level hardware */ - HAL_DSI_MspDeInit(hdsi); -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - - /* Initialize the error code */ - hdsi->ErrorCode = HAL_DSI_ERROR_NONE; - - /* Initialize the DSI state*/ - hdsi->State = HAL_DSI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Enable the error monitor flags - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ActiveErrors indicates which error interrupts will be enabled. - * This parameter can be any combination of @arg DSI_Error_Data_Type. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - hdsi->Instance->IER[0U] = 0U; - hdsi->Instance->IER[1U] = 0U; - - /* Store active errors to the handle */ - hdsi->ErrorMsk = ActiveErrors; - - if ((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_TX) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_RX) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; - } - - if ((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U) - { - /* Enable the interrupt generation on selected errors */ - hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Initializes the DSI MSP. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_MspInit could be implemented in the user file - */ -} - -/** - * @brief De-initializes the DSI MSP. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User DSI Callback - * To be used instead of the weak predefined callback - * @param hdsi dsi handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID - * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID - * @arg HAL_DSI_ERROR_CB_ID Error Callback ID - * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID - * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, - pDSI_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hdsi); - - if (hdsi->State == HAL_DSI_STATE_READY) - { - switch (CallbackID) - { - case HAL_DSI_TEARING_EFFECT_CB_ID : - hdsi->TearingEffectCallback = pCallback; - break; - - case HAL_DSI_ENDOF_REFRESH_CB_ID : - hdsi->EndOfRefreshCallback = pCallback; - break; - - case HAL_DSI_ERROR_CB_ID : - hdsi->ErrorCallback = pCallback; - break; - - case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = pCallback; - break; - - case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hdsi->State == HAL_DSI_STATE_RESET) - { - switch (CallbackID) - { - case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = pCallback; - break; - - case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdsi); - - return status; -} - -/** - * @brief Unregister a DSI Callback - * DSI callback is redirected to the weak predefined callback - * @param hdsi dsi handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID - * @arg HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID - * @arg HAL_DSI_ERROR_CB_ID Error Callback ID - * @arg HAL_DSI_MSPINIT_CB_ID MspInit callback ID - * @arg HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hdsi); - - if (hdsi->State == HAL_DSI_STATE_READY) - { - switch (CallbackID) - { - case HAL_DSI_TEARING_EFFECT_CB_ID : - hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ - break; - - case HAL_DSI_ENDOF_REFRESH_CB_ID : - hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ - break; - - case HAL_DSI_ERROR_CB_ID : - hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ - break; - - case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ - break; - - default : - /* Update the error code */ - hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hdsi->State == HAL_DSI_STATE_RESET) - { - switch (CallbackID) - { - case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ - break; - - case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ - break; - - default : - /* Update the error code */ - hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hdsi); - - return status; -} -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup DSI_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides function allowing to: - (+) Handle DSI interrupt request - -@endverbatim - * @{ - */ -/** - * @brief Handles DSI interrupt request. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) -{ - uint32_t ErrorStatus0; - uint32_t ErrorStatus1; - - /* Tearing Effect Interrupt management ***************************************/ - if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) - { - if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U) - { - /* Clear the Tearing Effect Interrupt Flag */ - __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); - - /* Tearing Effect Callback */ -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) - /*Call registered Tearing Effect callback */ - hdsi->TearingEffectCallback(hdsi); -#else - /*Call legacy Tearing Effect callback*/ - HAL_DSI_TearingEffectCallback(hdsi); -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - } - } - - /* End of Refresh Interrupt management ***************************************/ - if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U) - { - if (__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U) - { - /* Clear the End of Refresh Interrupt Flag */ - __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); - - /* End of Refresh Callback */ -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) - /*Call registered End of refresh callback */ - hdsi->EndOfRefreshCallback(hdsi); -#else - /*Call Legacy End of refresh callback */ - HAL_DSI_EndOfRefreshCallback(hdsi); -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - } - } - - /* Error Interrupts management ***********************************************/ - if (hdsi->ErrorMsk != 0U) - { - ErrorStatus0 = hdsi->Instance->ISR[0U]; - ErrorStatus0 &= hdsi->Instance->IER[0U]; - ErrorStatus1 = hdsi->Instance->ISR[1U]; - ErrorStatus1 &= hdsi->Instance->IER[1U]; - - if ((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; - } - - if ((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; - } - - if ((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_TX; - } - - if ((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_RX; - } - - if ((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; - } - - if ((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; - } - - if ((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; - } - - if ((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; - } - - if ((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; - } - - if ((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U) - { - hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; - } - - /* Check only selected errors */ - if (hdsi->ErrorCode != HAL_DSI_ERROR_NONE) - { - /* DSI error interrupt callback */ -#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) - /*Call registered Error callback */ - hdsi->ErrorCallback(hdsi); -#else - /*Call Legacy Error callback */ - HAL_DSI_ErrorCallback(hdsi); -#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - } - } -} - -/** - * @brief Tearing Effect DSI callback. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_TearingEffectCallback could be implemented in the user file - */ -} - -/** - * @brief End of Refresh DSI callback. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_EndOfRefreshCallback could be implemented in the user file - */ -} - -/** - * @brief Operation Error DSI callback. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval None - */ -__weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdsi); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DSI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup DSI_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the Generic interface read-back Virtual Channel ID - (+) Select video mode and configure the corresponding parameters - (+) Configure command transmission mode: High-speed or Low-power - (+) Configure the flow control - (+) Configure the DSI PHY timer - (+) Configure the DSI HOST timeout - (+) Configure the DSI HOST timeout - (+) Start/Stop the DSI module - (+) Refresh the display in command mode - (+) Controls the display color mode in Video mode - (+) Control the display shutdown in Video mode - (+) write short DCS or short Generic command - (+) write long DCS or long Generic command - (+) Read command (DCS or generic) - (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running) - (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off) - (+) Start/Stop test pattern generation - (+) Slew-Rate And Delay Tuning - (+) Low-Power Reception Filter Tuning - (+) Activate an additional current path on all lanes to meet the SDDTx parameter - (+) Custom lane pins configuration - (+) Set custom timing for the PHY - (+) Force the Clock/Data Lane in TX Stop Mode - (+) Force LP Receiver in Low-Power Mode - (+) Force Data Lanes in RX Mode after a BTA - (+) Enable a pull-down on the lanes to prevent from floating states when unused - (+) Switch off the contention detection on data lanes - -@endverbatim - * @{ - */ - -/** - * @brief Configure the Generic interface read-back Virtual Channel ID. - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param VirtualChannelID Virtual channel ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Update the GVCID register */ - hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; - hdsi->Instance->GVCIDR |= VirtualChannelID; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Select video mode and configure the corresponding parameters - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains - * the DSI video mode configuration parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); - assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); - assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); - assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); - assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); - assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); - assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); - assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); - assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); - assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); - assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); - assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); - assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); - /* Check the LooselyPacked variant only in 18-bit mode */ - if (VidCfg->ColorCoding == DSI_RGB666) - { - assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); - } - - /* Select video mode by resetting CMDM and DSIM bits */ - hdsi->Instance->MCR &= ~DSI_MCR_CMDM; - hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; - - /* Configure the video mode transmission type */ - hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; - hdsi->Instance->VMCR |= VidCfg->Mode; - - /* Configure the video packet size */ - hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; - hdsi->Instance->VPCR |= VidCfg->PacketSize; - - /* Set the chunks number to be transmitted through the DSI link */ - hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; - hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; - - /* Set the size of the null packet */ - hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; - hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; - - /* Select the virtual channel for the LTDC interface traffic */ - hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; - hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; - - /* Configure the polarity of control signals */ - hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); - hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); - - /* Select the color coding for the host */ - hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; - hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; - - /* Select the color coding for the wrapper */ - hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; - hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding) << 1U); - - /* Enable/disable the loosely packed variant to 18-bit configuration */ - if (VidCfg->ColorCoding == DSI_RGB666) - { - hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; - hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; - } - - /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ - hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; - hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; - - /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ - hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; - hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; - - /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ - hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; - hdsi->Instance->VLCR |= VidCfg->HorizontalLine; - - /* Set the Vertical Synchronization Active (VSA) */ - hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; - hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; - - /* Set the Vertical Back Porch (VBP)*/ - hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; - hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; - - /* Set the Vertical Front Porch (VFP)*/ - hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; - hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; - - /* Set the Vertical Active period*/ - hdsi->Instance->VVACR &= ~DSI_VVACR_VA; - hdsi->Instance->VVACR |= VidCfg->VerticalActive; - - /* Configure the command transmission mode */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; - hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; - - /* Low power largest packet size */ - hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; - hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize) << 16U); - - /* Low power VACT largest packet size */ - hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; - hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; - - /* Enable LP transition in HFP period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; - hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; - - /* Enable LP transition in HBP period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; - hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; - - /* Enable LP transition in VACT period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; - hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; - - /* Enable LP transition in VFP period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; - hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; - - /* Enable LP transition in VBP period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; - hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; - - /* Enable LP transition in vertical sync period */ - hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; - hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; - - /* Enable the request for an acknowledge response at the end of a frame */ - hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; - hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Select adapted command mode and configure the corresponding parameters - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains - * the DSI command mode configuration parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); - assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); - assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); - assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); - assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); - assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); - assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); - assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); - assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); - - /* Select command mode by setting CMDM and DSIM bits */ - hdsi->Instance->MCR |= DSI_MCR_CMDM; - hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; - hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; - - /* Select the virtual channel for the LTDC interface traffic */ - hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; - hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; - - /* Configure the polarity of control signals */ - hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); - hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); - - /* Select the color coding for the host */ - hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; - hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; - - /* Select the color coding for the wrapper */ - hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; - hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding) << 1U); - - /* Configure the maximum allowed size for write memory command */ - hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; - hdsi->Instance->LCCR |= CmdCfg->CommandSize; - - /* Configure the tearing effect source and polarity and select the refresh mode */ - hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); - hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | - CmdCfg->VSyncPol); - - /* Configure the tearing effect acknowledge request */ - hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; - hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; - - /* Enable the Tearing Effect interrupt */ - __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); - - /* Enable the End of Refresh interrupt */ - __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Configure command transmission mode: High-speed or Low-power - * and enable/disable acknowledge request after packet transmission - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains - * the DSI command transmission mode configuration parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); - assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); - assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); - assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); - assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); - assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); - assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); - assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); - assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); - assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); - assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); - assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); - assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); - - /* Select High-speed or Low-power for command transmission */ - hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX | \ - DSI_CMCR_GSW1TX | \ - DSI_CMCR_GSW2TX | \ - DSI_CMCR_GSR0TX | \ - DSI_CMCR_GSR1TX | \ - DSI_CMCR_GSR2TX | \ - DSI_CMCR_GLWTX | \ - DSI_CMCR_DSW0TX | \ - DSI_CMCR_DSW1TX | \ - DSI_CMCR_DSR0TX | \ - DSI_CMCR_DLWTX | \ - DSI_CMCR_MRDPS); - hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP | \ - LPCmd->LPGenShortWriteOneP | \ - LPCmd->LPGenShortWriteTwoP | \ - LPCmd->LPGenShortReadNoP | \ - LPCmd->LPGenShortReadOneP | \ - LPCmd->LPGenShortReadTwoP | \ - LPCmd->LPGenLongWrite | \ - LPCmd->LPDcsShortWriteNoP | \ - LPCmd->LPDcsShortWriteOneP | \ - LPCmd->LPDcsShortReadNoP | \ - LPCmd->LPDcsLongWrite | \ - LPCmd->LPMaxReadPacket); - - /* Configure the acknowledge request after each packet transmission */ - hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; - hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Configure the flow control parameters - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param FlowControl flow control feature(s) to be enabled. - * This parameter can be any combination of @arg DSI_FlowControl. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); - - /* Set the DSI Host Protocol Configuration Register */ - hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; - hdsi->Instance->PCR |= FlowControl; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Configure the DSI PHY timer parameters - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains - * the DSI PHY timing parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) -{ - uint32_t maxTime; - /* Process locked */ - __HAL_LOCK(hdsi); - - maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime) ? PhyTimers->ClockLaneLP2HSTime : - PhyTimers->ClockLaneHS2LPTime; - - /* Clock lane timer configuration */ - - /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two - High-Speed transmission. - To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed - to Low-Power and from Low-Power to High-Speed. - This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration - Register (DSI_CLTCR). - But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. - - Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. - */ - hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); - hdsi->Instance->CLTCR |= (maxTime | ((maxTime) << 16U)); - - /* Data lane timer configuration */ - hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); - hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime) << 16U) | (( - PhyTimers->DataLaneHS2LPTime) << 24U)); - - /* Configure the wait period to request HS transmission after a stop state */ - hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; - hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime) << 8U); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Configure the DSI HOST timeout parameters - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains - * the DSI host timeout parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Set the timeout clock division factor */ - hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; - hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv) << 8U); - - /* High-speed transmission timeout */ - hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; - hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout) << 16U); - - /* Low-power reception timeout */ - hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; - hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout; - - /* High-speed read timeout */ - hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT; - hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout; - - /* Low-power read timeout */ - hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT; - hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout; - - /* High-speed write timeout */ - hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT; - hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout; - - /* High-speed write presp mode */ - hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM; - hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode; - - /* Low-speed write timeout */ - hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT; - hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout; - - /* BTA timeout */ - hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT; - hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Start the DSI module - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Enable the DSI host */ - __HAL_DSI_ENABLE(hdsi); - - /* Enable the DSI wrapper */ - __HAL_DSI_WRAPPER_ENABLE(hdsi); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Stop the DSI module - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Disable the DSI host */ - __HAL_DSI_DISABLE(hdsi); - - /* Disable the DSI wrapper */ - __HAL_DSI_WRAPPER_DISABLE(hdsi); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Refresh the display in command mode - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Update the display */ - hdsi->Instance->WCR |= DSI_WCR_LTDCEN; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Controls the display color mode in Video mode - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ColorMode Color mode (full or 8-colors). - * This parameter can be any value of @arg DSI_Color_Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_COLOR_MODE(ColorMode)); - - /* Update the display color mode */ - hdsi->Instance->WCR &= ~DSI_WCR_COLM; - hdsi->Instance->WCR |= ColorMode; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Control the display shutdown in Video mode - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Shutdown Shut-down (Display-ON or Display-OFF). - * This parameter can be any value of @arg DSI_ShutDown - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_SHUT_DOWN(Shutdown)); - - /* Update the display Shutdown */ - hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; - hdsi->Instance->WCR |= Shutdown; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief write short DCS or short Generic command - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ChannelID Virtual channel ID. - * @param Mode DSI short packet data type. - * This parameter can be any value of @arg DSI_SHORT_WRITE_PKT_Data_Type. - * @param Param1 DSC command or first generic parameter. - * This parameter can be any value of @arg DSI_DCS_Command or a - * generic command code. - * @param Param2 DSC parameter or second generic parameter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t Param1, - uint32_t Param2) -{ - HAL_StatusTypeDef status; - /* Check the parameters */ - assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); - - /* Process locked */ - __HAL_LOCK(hdsi); - - status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return status; -} - -/** - * @brief write long DCS or long Generic command - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ChannelID Virtual channel ID. - * @param Mode DSI long packet data type. - * This parameter can be any value of @arg DSI_LONG_WRITE_PKT_Data_Type. - * @param NbParams Number of parameters. - * @param Param1 DSC command or first generic parameter. - * This parameter can be any value of @arg DSI_DCS_Command or a - * generic command code - * @param ParametersTable Pointer to parameter values table. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t NbParams, - uint32_t Param1, - const uint8_t *ParametersTable) -{ - uint32_t uicounter; - uint32_t nbBytes; - uint32_t count; - uint32_t tickstart; - uint32_t fifoword; - const uint8_t *pparams = ParametersTable; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for Command FIFO Empty */ - while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/ - fifoword = Param1; - nbBytes = (NbParams < 3U) ? NbParams : 3U; - - for (count = 0U; count < nbBytes; count++) - { - fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U * count))); - } - hdsi->Instance->GPDR = fifoword; - - uicounter = NbParams - nbBytes; - pparams += nbBytes; - /* Set the Next parameters on the write FIFO command*/ - while (uicounter != 0U) - { - nbBytes = (uicounter < 4U) ? uicounter : 4U; - fifoword = 0U; - for (count = 0U; count < nbBytes; count++) - { - fifoword |= (((uint32_t)(*(pparams + count))) << (8U * count)); - } - hdsi->Instance->GPDR = fifoword; - - uicounter -= nbBytes; - pparams += nbBytes; - } - - /* Configure the packet to send a long DCS command */ - DSI_ConfigPacketHeader(hdsi->Instance, - ChannelID, - Mode, - ((NbParams + 1U) & 0x00FFU), - (((NbParams + 1U) & 0xFF00U) >> 8U)); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Read command (DCS or generic) - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param ChannelNbr Virtual channel ID - * @param Array pointer to a buffer to store the payload of a read back operation. - * @param Size Data size to be read (in byte). - * @param Mode DSI read packet data type. - * This parameter can be any value of @arg DSI_SHORT_READ_PKT_Data_Type. - * @param DCSCmd DCS get/read command. - * @param ParametersTable Pointer to parameter values table. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, - uint32_t ChannelNbr, - uint8_t *Array, - uint32_t Size, - uint32_t Mode, - uint32_t DCSCmd, - uint8_t *ParametersTable) -{ - uint32_t tickstart; - uint8_t *pdata = Array; - uint32_t datasize = Size; - uint32_t fifoword; - uint32_t nbbytes; - uint32_t count; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check the parameters */ - assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); - - if (datasize > 2U) - { - /* set max return packet size */ - if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU), - (((datasize) >> 8U) & 0xFFU)) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - } - - /* Configure the packet to read command */ - if (Mode == DSI_DCS_SHORT_PKT_READ) - { - DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U); - } - else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) - { - DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U); - } - else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) - { - DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U); - } - else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) - { - DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* If DSI fifo is not empty, read requested bytes */ - while (((int32_t)(datasize)) > 0) - { - if ((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) - { - fifoword = hdsi->Instance->GPDR; - nbbytes = (datasize < 4U) ? datasize : 4U; - - for (count = 0U; count < nbbytes; count++) - { - *pdata = (uint8_t)(fifoword >> (8U * count)); - pdata++; - datasize--; - } - } - - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - - /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */ - /* issued to the panel and the read data is not captured by the DSI Host */ - /* which returns Packet Size Error. */ - /* Need to ensure that the Read command has finished before checking PSE */ - if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U) - { - if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running - * (only data lanes are in ULPM) - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) -{ - uint32_t tickstart; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Verify the initial status of the DSI Host */ - - /* Verify that the clock lane and the digital section of the D-PHY are enabled */ - if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Verify that the D-PHY PLL and the reference bias are enabled */ - if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - else - { - /* Nothing to do */ - } - - /* Verify that there are no ULPS exit or request on data lanes */ - if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Verify that there are no Transmission trigger */ - if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Requires min of 400us delay before reading the PLLLS flag */ - /* 1ms delay is inserted that is the minimum HAL delay granularity */ - HAL_Delay(1); - - /* Verify that D-PHY PLL is locked */ - tickstart = HAL_GetTick(); - - while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Verify that all active lanes are in Stop state */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* ULPS Request on Data Lanes */ - hdsi->Instance->PUCR |= DSI_PUCR_URDL; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the D-PHY active lanes enter into ULPM */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running - * (only data lanes are in ULPM) - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) -{ - uint32_t tickstart; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Verify that all active lanes are in ULPM */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* Turn on the DSI PLL */ - __HAL_DSI_PLL_ENABLE(hdsi); - - /* Requires min of 400us delay before reading the PLLLS flag */ - /* 1ms delay is inserted that is the minimum HAL delay granularity */ - HAL_Delay(1); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for the lock of the PLL */ - while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Exit ULPS on Data Lanes */ - hdsi->Instance->PUCR |= DSI_PUCR_UEDL; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until all active lanes exit ULPM */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* wait for 1 ms*/ - HAL_Delay(1U); - - /* De-assert the ULPM requests and the ULPM exit bits */ - hdsi->Instance->PUCR = 0U; - - /* Verify that D-PHY PLL is enabled */ - if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Verify that all active lanes are in Stop state */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Verify that D-PHY PLL is locked */ - /* Requires min of 400us delay before reading the PLLLS flag */ - /* 1ms delay is inserted that is the minimum HAL delay granularity */ - HAL_Delay(1); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for the lock of the PLL */ - while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off - * (both data and clock lanes are in ULPM) - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) -{ - uint32_t tickstart; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Verify the initial status of the DSI Host */ - - /* Verify that the clock lane and the digital section of the D-PHY are enabled */ - if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Verify that the D-PHY PLL and the reference bias are enabled */ - if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - else if ((hdsi->Instance->WRPCR & DSI_WRPCR_REGEN) != DSI_WRPCR_REGEN) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - else - { - /* Nothing to do */ - } - - /* Verify that there are no ULPS exit or request on both data and clock lanes */ - if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Verify that there are no Transmission trigger */ - if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Requires min of 400us delay before reading the PLLLS flag */ - /* 1ms delay is inserted that is the minimum HAL delay granularity */ - HAL_Delay(1); - - /* Verify that D-PHY PLL is locked */ - tickstart = HAL_GetTick(); - - while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Verify that all active lanes are in Stop state */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ - DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Clock lane configuration: no more HS request */ - hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; - - /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ - __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR); - - /* ULPS Request on Clock and Data Lanes */ - hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until all active lanes enter ULPM */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* Turn off the DSI PLL */ - __HAL_DSI_PLL_DISABLE(hdsi); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off - * (both data and clock lanes are in ULPM) - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) -{ - uint32_t tickstart; - - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Verify that all active lanes are in ULPM */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \ - DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \ - DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* Turn on the DSI PLL */ - __HAL_DSI_PLL_ENABLE(hdsi); - - /* Requires min of 400us delay before reading the PLLLS flag */ - /* 1ms delay is inserted that is the minimum HAL delay granularity */ - HAL_Delay(1); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for the lock of the PLL */ - while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Exit ULPS on Clock and Data Lanes */ - hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until all active lanes exit ULPM */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | - DSI_PSR_UANC)) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* wait for 1 ms */ - HAL_Delay(1U); - - /* De-assert the ULPM requests and the ULPM exit bits */ - hdsi->Instance->PUCR = 0U; - - /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */ - __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); - - /* Restore clock lane configuration to HS */ - hdsi->Instance->CLCR |= DSI_CLCR_DPCC; - - /* Verify that D-PHY PLL is enabled */ - if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Verify that all active lanes are in Stop state */ - if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) - { - if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - } - else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) - { - if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ - DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - return HAL_ERROR; - } - - /* Verify that D-PHY PLL is locked */ - /* Requires min of 400us delay before reading the PLLLS flag */ - /* 1ms delay is inserted that is the minimum HAL delay granularity */ - HAL_Delay(1); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for the lock of the PLL */ - while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) - { - /* Process Unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_TIMEOUT; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Start test pattern generation - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Mode Pattern generator mode - * This parameter can be one of the following values: - * 0 : Color bars (horizontal or vertical) - * 1 : BER pattern (vertical only) - * @param Orientation Pattern generator orientation - * This parameter can be one of the following values: - * 0 : Vertical color bars - * 1 : Horizontal color bars - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Configure pattern generator mode and orientation */ - hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); - hdsi->Instance->VMCR |= ((Mode << 20U) | (Orientation << 24U)); - - /* Enable pattern generator by setting PGE bit */ - hdsi->Instance->VMCR |= DSI_VMCR_PGE; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Stop test pattern generation - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Disable pattern generator by clearing PGE bit */ - hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Set Slew-Rate And Delay Tuning - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param CommDelay Communication delay to be adjusted. - * This parameter can be any value of @arg DSI_Communication_Delay - * @param Lane select between clock or data lanes. - * This parameter can be any value of @arg DSI_Lane_Group - * @param Value Custom value of the slew-rate or delay - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, - uint32_t Value) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); - assert_param(IS_DSI_LANE_GROUP(Lane)); - - switch (CommDelay) - { - case DSI_SLEW_RATE_HSTX: - if (Lane == DSI_CLOCK_LANE) - { - /* High-Speed Transmission Slew Rate Control on Clock Lane */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL; - hdsi->Instance->WPCR[1U] |= Value << 16U; - } - else if (Lane == DSI_DATA_LANES) - { - /* High-Speed Transmission Slew Rate Control on Data Lanes */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; - hdsi->Instance->WPCR[1U] |= Value << 18U; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - break; - case DSI_SLEW_RATE_LPTX: - if (Lane == DSI_CLOCK_LANE) - { - /* Low-Power transmission Slew Rate Compensation on Clock Lane */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL; - hdsi->Instance->WPCR[1U] |= Value << 6U; - } - else if (Lane == DSI_DATA_LANES) - { - /* Low-Power transmission Slew Rate Compensation on Data Lanes */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; - hdsi->Instance->WPCR[1U] |= Value << 8U; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - break; - case DSI_HS_DELAY: - if (Lane == DSI_CLOCK_LANE) - { - /* High-Speed Transmission Delay on Clock Lane */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL; - hdsi->Instance->WPCR[1U] |= Value; - } - else if (Lane == DSI_DATA_LANES) - { - /* High-Speed Transmission Delay on Data Lanes */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; - hdsi->Instance->WPCR[1U] |= Value << 2U; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - break; - default: - break; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Low-Power Reception Filter Tuning - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Frequency cutoff frequency of low-pass filter at the input of LPRX - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Low-Power RX low-pass Filtering Tuning */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT; - hdsi->Instance->WPCR[1U] |= Frequency << 25U; - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Activate an additional current path on all lanes to meet the SDDTx parameter - * defined in the MIPI D-PHY specification - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Activate/Disactivate additional current path on all lanes */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC; - hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Custom lane pins configuration - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param CustomLane Function to be applied on selected lane. - * This parameter can be any value of @arg DSI_CustomLane - * @param Lane select between clock or data lane 0 or data lane 1. - * This parameter can be any value of @arg DSI_Lane_Select - * @param State ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, - FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); - assert_param(IS_DSI_LANE(Lane)); - assert_param(IS_FUNCTIONAL_STATE(State)); - - switch (CustomLane) - { - case DSI_SWAP_LANE_PINS: - if (Lane == DSI_CLK_LANE) - { - /* Swap pins on clock lane */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); - } - else if (Lane == DSI_DATA_LANE0) - { - /* Swap pins on data lane 0 */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); - } - else if (Lane == DSI_DATA_LANE1) - { - /* Swap pins on data lane 1 */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - break; - case DSI_INVERT_HS_SIGNAL: - if (Lane == DSI_CLK_LANE) - { - /* Invert HS signal on clock lane */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U); - } - else if (Lane == DSI_DATA_LANE0) - { - /* Invert HS signal on data lane 0 */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U); - } - else if (Lane == DSI_DATA_LANE1) - { - /* Invert HS signal on data lane 1 */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - break; - default: - break; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Set custom timing for the PHY - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Timing PHY timing to be adjusted. - * This parameter can be any value of @arg DSI_PHY_Timing - * @param State ENABLE or DISABLE - * @param Value Custom value of the timing - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_DSI_PHY_TIMING(Timing)); - assert_param(IS_FUNCTIONAL_STATE(State)); - - switch (Timing) - { - case DSI_TCLK_POST: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; - hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; - } - - break; - case DSI_TLPX_CLK: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; - hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; - } - - break; - case DSI_THS_EXIT: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; - hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; - } - - break; - case DSI_TLPX_DATA: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; - hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; - } - - break; - case DSI_THS_ZERO: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; - hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; - } - - break; - case DSI_THS_TRAIL: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; - hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; - } - - break; - case DSI_THS_PREPARE: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; - hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; - } - - break; - case DSI_TCLK_ZERO: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; - hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; - } - - break; - case DSI_TCLK_PREPARE: - /* Enable/Disable custom timing setting */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); - - if (State != DISABLE) - { - /* Set custom value */ - hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; - hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; - } - - break; - default: - break; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Force the Clock/Data Lane in TX Stop Mode - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param Lane select between clock or data lanes. - * This parameter can be any value of @arg DSI_Lane_Group - * @param State ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_DSI_LANE_GROUP(Lane)); - assert_param(IS_FUNCTIONAL_STATE(State)); - - if (Lane == DSI_CLOCK_LANE) - { - /* Force/Unforce the Clock Lane in TX Stop Mode */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U); - } - else if (Lane == DSI_DATA_LANES) - { - /* Force/Unforce the Data Lanes in TX Stop Mode */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Force LP Receiver in Low-Power Mode - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Force/Unforce LP Receiver in Low-Power Mode */ - hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM; - hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Force Data Lanes in RX Mode after a BTA - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Force Data Lanes in RX Mode */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Enable a pull-down on the lanes to prevent from floating states when unused - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Enable/Disable pull-down on lanes */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @brief Switch off the contention detection on data lanes - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @param State ENABLE or DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) -{ - /* Process locked */ - __HAL_LOCK(hdsi); - - /* Check function parameters */ - assert_param(IS_FUNCTIONAL_STATE(State)); - - /* Contention Detection on Data Lanes OFF */ - hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL; - hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U); - - /* Process unlocked */ - __HAL_UNLOCK(hdsi); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup DSI_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the DSI state. - (+) Get error code. - -@endverbatim - * @{ - */ - -/** - * @brief Return the DSI state - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval HAL state - */ -HAL_DSI_StateTypeDef HAL_DSI_GetState(const DSI_HandleTypeDef *hdsi) -{ - return hdsi->State; -} - -/** - * @brief Return the DSI error code - * @param hdsi pointer to a DSI_HandleTypeDef structure that contains - * the configuration information for the DSI. - * @retval DSI Error Code - */ -uint32_t HAL_DSI_GetError(const DSI_HandleTypeDef *hdsi) -{ - /* Get the error code */ - return hdsi->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DSI */ - -#endif /* HAL_DSI_MODULE_ENABLED */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c deleted file mode 100644 index b07d0b2b..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_eth.c +++ /dev/null @@ -1,3238 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_eth.c - * @author MCD Application Team - * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Ethernet (ETH) peripheral: - * + Initialization and deinitialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The ETH HAL driver can be used as follows: - - (#)Declare a ETH_HandleTypeDef handle structure, for example: - ETH_HandleTypeDef heth; - - (#)Fill parameters of Init structure in heth handle - - (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) - - (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - (##) Enable the Ethernet interface clock using - (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE() - (+++) __HAL_RCC_ETH1TX_CLK_ENABLE() - (+++) __HAL_RCC_ETH1RX_CLK_ENABLE() - - (##) Initialize the related GPIO clocks - (##) Configure Ethernet pinout - (##) Configure Ethernet NVIC interrupt (in Interrupt mode) - - (#) Ethernet data reception is asynchronous, so call the following API - to start the listening mode: - (##) HAL_ETH_Start(): - This API starts the MAC and DMA transmission and reception process, - without enabling end of transfer interrupts, in this mode user - has to poll for data reception by calling HAL_ETH_ReadData() - (##) HAL_ETH_Start_IT(): - This API starts the MAC and DMA transmission and reception process, - end of transfer interrupts are enabled in this mode, - HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received - - (#) When data is received user can call the following API to get received data: - (##) HAL_ETH_ReadData(): Read a received packet - - (#) For transmission path, two APIs are available: - (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode - (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode, - HAL_ETH_TxCpltCallback() will be executed when end of transfer occur - - (#) Communication with an external PHY device: - (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY - (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register - - (#) Configure the Ethernet MAC after ETH peripheral initialization - (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef - (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef - - (#) Configure the Ethernet DMA after ETH peripheral initialization - (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef - (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef - - (#) Configure the Ethernet PTP after ETH peripheral initialization - (##) Define HAL_ETH_USE_PTP to use PTP APIs. - (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef - (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef - (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers - (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers - (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers - (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission - (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp - (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp - - -@- The ARP offload feature is not supported in this driver. - - -@- The PTP offload feature is not supported in this driver. - - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function HAL_ETH_RegisterCallback() to register an interrupt callback. - - Function HAL_ETH_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : Tx Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) PMTCallback : Power Management Callback - (+) EEECallback : EEE Callback. - (+) WakeUpCallback : Wake UP Callback - (+) MspInitCallback : MspInit Callback. - (+) MspDeInitCallback: MspDeInit Callback. - - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - For specific callbacks RxAllocateCallback use dedicated register callbacks: - respectively HAL_ETH_RegisterRxAllocateCallback(). - - For specific callbacks RxLinkCallback use dedicated register callbacks: - respectively HAL_ETH_RegisterRxLinkCallback(). - - For specific callbacks TxFreeCallback use dedicated register callbacks: - respectively HAL_ETH_RegisterTxFreeCallback(). - - For specific callbacks TxPtpCallback use dedicated register callbacks: - respectively HAL_ETH_RegisterTxPtpCallback(). - - Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxCpltCallback : Tx Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) PMTCallback : Power Management Callback - (+) EEECallback : EEE Callback. - (+) WakeUpCallback : Wake UP Callback - (+) MspInitCallback : MspInit Callback. - (+) MspDeInitCallback: MspDeInit Callback. - - For specific callbacks RxAllocateCallback use dedicated unregister callbacks: - respectively HAL_ETH_UnRegisterRxAllocateCallback(). - - For specific callbacks RxLinkCallback use dedicated unregister callbacks: - respectively HAL_ETH_UnRegisterRxLinkCallback(). - - For specific callbacks TxFreeCallback use dedicated unregister callbacks: - respectively HAL_ETH_UnRegisterTxFreeCallback(). - - For specific callbacks TxPtpCallback use dedicated unregister callbacks: - respectively HAL_ETH_UnRegisterTxPtpCallback(). - - By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit - or HAL_ETH_Init function. - - When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#ifdef HAL_ETH_MODULE_ENABLED - -#if defined(ETH) - -/** @defgroup ETH ETH - * @brief ETH HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup ETH_Private_Constants ETH Private Constants - * @{ - */ -#define ETH_MACCR_MASK 0xFFFB7F7CU -#define ETH_MACECR_MASK 0x3F077FFFU -#define ETH_MACFFR_MASK 0x800007FFU -#define ETH_MACWTR_MASK 0x0000010FU -#define ETH_MACTFCR_MASK 0xFFFF00F2U -#define ETH_MACRFCR_MASK 0x00000003U -#define ETH_MTLTQOMR_MASK 0x00000072U -#define ETH_MTLRQOMR_MASK 0x0000007BU - -#define ETH_DMAMR_MASK 0x00007802U -#define ETH_DMASBMR_MASK 0x0000D001U -#define ETH_DMACCR_MASK 0x00013FFFU -#define ETH_DMACTCR_MASK 0x003F1010U -#define ETH_DMACRCR_MASK 0x803F0000U -#define ETH_MACPMTCSR_MASK (ETH_MACPMTCSR_PD | ETH_MACPMTCSR_WFE | \ - ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU) - -/* Timeout values */ -#define ETH_SWRESET_TIMEOUT 500U -#define ETH_MDIO_BUS_TIMEOUT 1000U - -#define ETH_DMARXDESC_ERRORS_MASK ((uint32_t)(ETH_DMARXDESC_DBE | ETH_DMARXDESC_RE | \ - ETH_DMARXDESC_OE | ETH_DMARXDESC_RWT |\ - ETH_DMARXDESC_LC | ETH_DMARXDESC_CE |\ - ETH_DMARXDESC_DE | ETH_DMARXDESC_IPV4HCE)) - -#define ETH_MAC_US_TICK 1000000U - -#define ETH_MACTSCR_MASK 0x0087FF2FU - -#define ETH_PTPTSHR_VALUE 0xFFFFFFFFU -#define ETH_PTPTSLR_VALUE 0xBB9ACA00U - -/* Ethernet MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U - -/* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY 0x00000001U - -/* ETHERNET MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK 0xFD20810FU - -/* ETHERNET MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U - -/* ETHERNET DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U - -/* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ - -/* ETHERNET DMA Rx descriptors Frame length Shift */ -#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ETH_Private_Macros ETH Private Macros - * @{ - */ -/* Helper macros for TX descriptor handling */ -#define INCR_TX_DESC_INDEX(inx, offset) do {\ - (inx) += (offset);\ - if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\ - (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\ - } while (0) - -/* Helper macros for RX descriptor handling */ -#define INCR_RX_DESC_INDEX(inx, offset) do {\ - (inx) += (offset);\ - if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\ - (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\ - } while (0) -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup ETH_Private_Functions ETH Private Functions - * @{ - */ -static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf); -static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf); -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth); -static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); -static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); -static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, - uint32_t ItMode); -static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup ETH_Exported_Functions ETH Exported Functions - * @{ - */ - -/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the ETH peripheral: - - (+) User must Implement HAL_ETH_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO and NVIC ). - - (+) Call the function HAL_ETH_Init() to configure the selected device with - the selected configuration: - (++) MAC address - (++) Media interface (MII or RMII) - (++) Rx DMA Descriptors Tab - (++) Tx DMA Descriptors Tab - (++) Length of Rx Buffers - - (+) Call the function HAL_ETH_DeInit() to restore the default configuration - of the selected ETH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the Ethernet peripheral registers. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) -{ - uint32_t tickstart; - - if (heth == NULL) - { - return HAL_ERROR; - } - if (heth->gState == HAL_ETH_STATE_RESET) - { - heth->gState = HAL_ETH_STATE_BUSY; - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - - ETH_InitCallbacksToDefault(heth); - - if (heth->MspInitCallback == NULL) - { - heth->MspInitCallback = HAL_ETH_MspInit; - } - - /* Init the low level hardware */ - heth->MspInitCallback(heth); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspInit(heth); - -#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ - } - - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Select MII or RMII Mode*/ - SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); - SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; - /* Dummy read to sync SYSCFG with ETH */ - (void)SYSCFG->PMC; - - /* Ethernet Software reset */ - /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ - /* After reset all the registers holds their respective reset values */ - SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for software reset */ - while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) - { - if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) - { - /* Set Error Code */ - heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; - /* Set State as Error */ - heth->gState = HAL_ETH_STATE_ERROR; - /* Return Error */ - return HAL_ERROR; - } - } - - - /*------------------ MAC, MTL and DMA default Configuration ----------------*/ - ETH_MACDMAConfig(heth); - - - /*------------------ DMA Tx Descriptors Configuration ----------------------*/ - ETH_DMATxDescListInit(heth); - - /*------------------ DMA Rx Descriptors Configuration ----------------------*/ - ETH_DMARxDescListInit(heth); - - /*--------------------- ETHERNET MAC Address Configuration ------------------*/ - ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); - - /* Disable MMC Interrupts */ - SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM); - - /* Disable Rx MMC Interrupts */ - SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \ - ETH_MMCRIMR_RFCEM); - - /* Disable Tx MMC Interrupts */ - SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \ - ETH_MMCTIMR_TGFSCM); - - heth->ErrorCode = HAL_ETH_ERROR_NONE; - heth->gState = HAL_ETH_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the ETH peripheral. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) -{ - /* Set the ETH peripheral state to BUSY */ - heth->gState = HAL_ETH_STATE_BUSY; - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - - if (heth->MspDeInitCallback == NULL) - { - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - } - /* DeInit the low level hardware */ - heth->MspDeInitCallback(heth); -#else - - /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ - HAL_ETH_MspDeInit(heth); - -#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ - - /* Set ETH HAL state to Disabled */ - heth->gState = HAL_ETH_STATE_RESET; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User ETH Callback - * To be used instead of the weak predefined callback - * @param heth eth handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID - * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID - * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, - pETH_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - - if (heth->gState == HAL_ETH_STATE_READY) - { - switch (CallbackID) - { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = pCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = pCallback; - break; - - case HAL_ETH_ERROR_CB_ID : - heth->ErrorCallback = pCallback; - break; - - case HAL_ETH_PMT_CB_ID : - heth->PMTCallback = pCallback; - break; - - - case HAL_ETH_WAKEUP_CB_ID : - heth->WakeUpCallback = pCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (heth->gState == HAL_ETH_STATE_RESET) - { - switch (CallbackID) - { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an ETH Callback - * ETH callback is redirected to the weak predefined callback - * @param heth eth handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID - * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID - * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (heth->gState == HAL_ETH_STATE_READY) - { - switch (CallbackID) - { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; - break; - - case HAL_ETH_ERROR_CB_ID : - heth->ErrorCallback = HAL_ETH_ErrorCallback; - break; - - case HAL_ETH_PMT_CB_ID : - heth->PMTCallback = HAL_ETH_PMTCallback; - break; - - - case HAL_ETH_WAKEUP_CB_ID : - heth->WakeUpCallback = HAL_ETH_WakeUpCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default : - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (heth->gState == HAL_ETH_STATE_RESET) - { - switch (CallbackID) - { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default : - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief ETH Transmit and Receive functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the ETH - data transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Enables Ethernet MAC and DMA reception and transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) -{ - uint32_t tmpreg1; - - if (heth->gState == HAL_ETH_STATE_READY) - { - heth->gState = HAL_ETH_STATE_BUSY; - - /* Set number of descriptors to build */ - heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; - - /* Build all descriptors */ - ETH_UpdateDescriptor(heth); - - /* Enable the MAC transmission */ - SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /* Enable the MAC reception */ - SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Enable the DMA transmission */ - SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); - - /* Enable the DMA reception */ - SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); - - heth->gState = HAL_ETH_STATE_STARTED; - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) -{ - uint32_t tmpreg1; - - if (heth->gState == HAL_ETH_STATE_READY) - { - heth->gState = HAL_ETH_STATE_BUSY; - - /* save IT mode to ETH Handle */ - heth->RxDescList.ItMode = 1U; - - /* Set number of descriptors to build */ - heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; - - /* Build all descriptors */ - ETH_UpdateDescriptor(heth); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /* Enable the DMA transmission */ - SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); - - /* Enable the DMA reception */ - SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - - /* Enable the MAC transmission */ - SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /* Enable the MAC reception */ - SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); - - /* Enable ETH DMA interrupts: - - Tx complete interrupt - - Rx complete interrupt - - Fatal bus interrupt - */ - __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE | - ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); - - heth->gState = HAL_ETH_STATE_STARTED; - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) -{ - uint32_t tmpreg1; - - if (heth->gState == HAL_ETH_STATE_STARTED) - { - /* Set the ETH peripheral state to BUSY */ - heth->gState = HAL_ETH_STATE_BUSY; - - /* Disable the DMA transmission */ - CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); - - /* Disable the DMA reception */ - CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); - - /* Disable the MAC reception */ - CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Disable the MAC transmission */ - CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - heth->gState = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) -{ - ETH_DMADescTypeDef *dmarxdesc; - uint32_t descindex; - uint32_t tmpreg1; - - if (heth->gState == HAL_ETH_STATE_STARTED) - { - /* Set the ETH peripheral state to BUSY */ - heth->gState = HAL_ETH_STATE_BUSY; - - __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE | - ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); - - /* Disable the DMA transmission */ - CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); - - /* Disable the DMA reception */ - CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); - - /* Disable the MAC reception */ - CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); - - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Disable the MAC transmission */ - CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /* Clear IOC bit to all Rx descriptors */ - for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) - { - dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; - SET_BIT(dmarxdesc->DESC1, ETH_DMARXDESC_DIC); - } - - heth->RxDescList.ItMode = 0U; - - heth->gState = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sends an Ethernet Packet in polling mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pTxConfig: Hold the configuration of packet to be transmitted - * @param Timeout: timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout) -{ - uint32_t tickstart; - ETH_DMADescTypeDef *dmatxdesc; - - if (pTxConfig == NULL) - { - heth->ErrorCode |= HAL_ETH_ERROR_PARAM; - return HAL_ERROR; - } - - if (heth->gState == HAL_ETH_STATE_STARTED) - { - /* Config DMA Tx descriptor by Tx Packet info */ - if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE) - { - /* Set the ETH error code */ - heth->ErrorCode |= HAL_ETH_ERROR_BUSY; - return HAL_ERROR; - } - - /* Ensure completion of descriptor preparation before transmission start */ - __DSB(); - - dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc]; - - /* Incr current tx desc index */ - INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); - - /* Start transmission */ - /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ - WRITE_REG(heth->Instance->DMATPDR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); - - tickstart = HAL_GetTick(); - - /* Wait for data to be transmitted or timeout occurred */ - while ((dmatxdesc->DESC0 & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { - if ((heth->Instance->DMASR & ETH_DMASR_FBES) != (uint32_t)RESET) - { - heth->ErrorCode |= HAL_ETH_ERROR_DMA; - heth->DMAErrorCode = heth->Instance->DMASR; - /* Return function status */ - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT; - /* Clear TX descriptor so that we can proceed */ - dmatxdesc->DESC0 = (ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - return HAL_ERROR; - } - } - } - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sends an Ethernet Packet in interrupt mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pTxConfig: Hold the configuration of packet to be transmitted - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig) -{ - if (pTxConfig == NULL) - { - heth->ErrorCode |= HAL_ETH_ERROR_PARAM; - return HAL_ERROR; - } - - if (heth->gState == HAL_ETH_STATE_STARTED) - { - /* Save the packet pointer to release. */ - heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; - - /* Config DMA Tx descriptor by Tx Packet info */ - if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE) - { - heth->ErrorCode |= HAL_ETH_ERROR_BUSY; - return HAL_ERROR; - } - - /* Ensure completion of descriptor preparation before transmission start */ - __DSB(); - - /* Incr current tx desc index */ - INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); - - /* Start transmission */ - /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ - if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - (heth->Instance)->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - (heth->Instance)->DMATPDR = 0U; - } - - return HAL_OK; - - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Read a received packet. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pAppBuff: Pointer to an application buffer to receive the packet. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) -{ - uint32_t descidx; - ETH_DMADescTypeDef *dmarxdesc; - uint32_t desccnt = 0U; - uint32_t desccntmax; - uint32_t bufflength; - uint8_t rxdataready = 0U; - - if (pAppBuff == NULL) - { - heth->ErrorCode |= HAL_ETH_ERROR_PARAM; - return HAL_ERROR; - } - - if (heth->gState != HAL_ETH_STATE_STARTED) - { - return HAL_ERROR; - } - - descidx = heth->RxDescList.RxDescIdx; - dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; - desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; - - /* Check if descriptor is not owned by DMA */ - while ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) - && (rxdataready == 0U)) - { - if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) - { - /* Get timestamp high */ - heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC7; - /* Get timestamp low */ - heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC6; - } - if ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) - { - /* Check first descriptor */ - if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) - { - heth->RxDescList.RxDescCnt = 0; - heth->RxDescList.RxDataLength = 0; - } - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - bufflength = ((dmarxdesc->DESC0 & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT); - - /* Check if last descriptor */ - if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) - { - /* Save Last descriptor index */ - heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC0; - - /* Packet ready */ - rxdataready = 1; - } - - /* Link data */ - WRITE_REG(dmarxdesc->BackupAddr0, dmarxdesc->DESC2); -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Link callback*/ - heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, - (uint8_t *)dmarxdesc->BackupAddr0, bufflength); -#else - /* Link callback */ - HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, - (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - heth->RxDescList.RxDescCnt++; - heth->RxDescList.RxDataLength += bufflength; - - /* Clear buffer pointer */ - dmarxdesc->BackupAddr0 = 0; - } - - /* Increment current rx descriptor index */ - INCR_RX_DESC_INDEX(descidx, 1U); - /* Get current descriptor address */ - dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; - desccnt++; - } - - heth->RxDescList.RxBuildDescCnt += desccnt; - if ((heth->RxDescList.RxBuildDescCnt) != 0U) - { - /* Update Descriptors */ - ETH_UpdateDescriptor(heth); - } - - heth->RxDescList.RxDescIdx = descidx; - - if (rxdataready == 1U) - { - /* Return received packet */ - *pAppBuff = heth->RxDescList.pRxStart; - /* Reset first element */ - heth->RxDescList.pRxStart = NULL; - - return HAL_OK; - } - - /* Packet not ready */ - return HAL_ERROR; -} - -/** - * @brief This function gives back Rx Desc of the last received Packet - * to the DMA, so ETH DMA will be able to use these descriptors - * to receive next Packets. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) -{ - uint32_t descidx; - uint32_t tailidx; - uint32_t desccount; - ETH_DMADescTypeDef *dmarxdesc; - uint8_t *buff = NULL; - uint8_t allocStatus = 1U; - - descidx = heth->RxDescList.RxBuildDescIdx; - dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; - desccount = heth->RxDescList.RxBuildDescCnt; - - while ((desccount > 0U) && (allocStatus != 0U)) - { - /* Check if a buffer's attached the descriptor */ - if (READ_REG(dmarxdesc->BackupAddr0) == 0U) - { - /* Get a new buffer. */ -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Allocate callback*/ - heth->rxAllocateCallback(&buff); -#else - /* Allocate callback */ - HAL_ETH_RxAllocateCallback(&buff); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - if (buff == NULL) - { - allocStatus = 0U; - } - else - { - WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); - WRITE_REG(dmarxdesc->DESC2, (uint32_t)buff); - } - } - - if (allocStatus != 0U) - { - if (heth->RxDescList.ItMode == 0U) - { - WRITE_REG(dmarxdesc->DESC1, heth->Init.RxBuffLen | ETH_DMARXDESC_DIC | ETH_DMARXDESC_RCH); - } - else - { - WRITE_REG(dmarxdesc->DESC1, heth->Init.RxBuffLen | ETH_DMARXDESC_RCH); - } - - SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN); - - /* Increment current rx descriptor index */ - INCR_RX_DESC_INDEX(descidx, 1U); - /* Get current descriptor address */ - dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; - desccount--; - } - } - - if (heth->RxDescList.RxBuildDescCnt != desccount) - { - /* Set the tail pointer index */ - tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; - - /* DMB instruction to avoid race condition */ - __DMB(); - - /* Set the Tail pointer address */ - WRITE_REG(heth->Instance->DMARPDR, ((uint32_t)(heth->Init.RxDesc + (tailidx)))); - - heth->RxDescList.RxBuildDescIdx = descidx; - heth->RxDescList.RxBuildDescCnt = desccount; - } -} - -/** - * @brief Register the Rx alloc callback. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param rxAllocateCallback: pointer to function to alloc buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, - pETH_rxAllocateCallbackTypeDef rxAllocateCallback) -{ - if (rxAllocateCallback == NULL) - { - /* No buffer to save */ - return HAL_ERROR; - } - - /* Set function to allocate buffer */ - heth->rxAllocateCallback = rxAllocateCallback; - - return HAL_OK; -} - -/** - * @brief Unregister the Rx alloc callback. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth) -{ - /* Set function to allocate buffer */ - heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; - - return HAL_OK; -} - -/** - * @brief Rx Allocate callback. - * @param buff: pointer to allocated buffer - * @retval None - */ -__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(buff); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_RxAllocateCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Link callback. - * @param pStart: pointer to packet start - * @param pEnd: pointer to packet end - * @param buff: pointer to received data - * @param Length: received data length - * @retval None - */ -__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(pStart); - UNUSED(pEnd); - UNUSED(buff); - UNUSED(Length); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_RxLinkCallback could be implemented in the user file - */ -} - -/** - * @brief Set the Rx link data function. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param rxLinkCallback: pointer to function to link data - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback) -{ - if (rxLinkCallback == NULL) - { - /* No buffer to save */ - return HAL_ERROR; - } - - /* Set function to link data */ - heth->rxLinkCallback = rxLinkCallback; - - return HAL_OK; -} - -/** - * @brief Unregister the Rx link callback. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth) -{ - /* Set function to allocate buffer */ - heth->rxLinkCallback = HAL_ETH_RxLinkCallback; - - return HAL_OK; -} - -/** - * @brief Get the error state of the last received packet. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pErrorCode: pointer to uint32_t to hold the error code - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode) -{ - /* Get error bits. */ - *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXDESC_ERRORS_MASK); - - return HAL_OK; -} - -/** - * @brief Set the Tx free function. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param txFreeCallback: pointer to function to release the packet - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback) -{ - if (txFreeCallback == NULL) - { - /* No buffer to save */ - return HAL_ERROR; - } - - /* Set function to free transmmitted packet */ - heth->txFreeCallback = txFreeCallback; - - return HAL_OK; -} - -/** - * @brief Unregister the Tx free callback. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth) -{ - /* Set function to allocate buffer */ - heth->txFreeCallback = HAL_ETH_TxFreeCallback; - - return HAL_OK; -} - -/** - * @brief Tx Free callback. - * @param buff: pointer to buffer to free - * @retval None - */ -__weak void HAL_ETH_TxFreeCallback(uint32_t *buff) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(buff); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxFreeCallback could be implemented in the user file - */ -} - -/** - * @brief Release transmitted Tx packets. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) -{ - ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; - uint32_t numOfBuf = dmatxdesclist->BuffersInUse; - uint32_t idx = dmatxdesclist->releaseIndex; - uint8_t pktTxStatus = 1U; - uint8_t pktInUse; -#ifdef HAL_ETH_USE_PTP - ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; -#endif /* HAL_ETH_USE_PTP */ - - /* Loop through buffers in use. */ - while ((numOfBuf != 0U) && (pktTxStatus != 0U)) - { - pktInUse = 1U; - numOfBuf--; - /* If no packet, just examine the next packet. */ - if (dmatxdesclist->PacketAddress[idx] == NULL) - { - /* No packet in use, skip to next. */ - INCR_TX_DESC_INDEX(idx, 1U); - pktInUse = 0U; - } - - if (pktInUse != 0U) - { - /* Determine if the packet has been transmitted. */ - if ((heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_OWN) == 0U) - { -#ifdef HAL_ETH_USE_PTP - if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXDESC_LS) - && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXDESC_TTSS)) - { - /* Get timestamp low */ - timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC6; - /* Get timestamp high */ - timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC7; - } - else - { - timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX; - } -#endif /* HAL_ETH_USE_PTP */ - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered callbacks*/ -#ifdef HAL_ETH_USE_PTP - /* Handle Ptp */ - if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) - { - heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); - } -#endif /* HAL_ETH_USE_PTP */ - /* Release the packet. */ - heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]); -#else - /* Call callbacks */ -#ifdef HAL_ETH_USE_PTP - /* Handle Ptp */ - if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) - { - HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); - } -#endif /* HAL_ETH_USE_PTP */ - /* Release the packet. */ - HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the entry in the in-use array. */ - dmatxdesclist->PacketAddress[idx] = NULL; - - /* Update the transmit relesae index and number of buffers in use. */ - INCR_TX_DESC_INDEX(idx, 1U); - dmatxdesclist->BuffersInUse = numOfBuf; - dmatxdesclist->releaseIndex = idx; - } - else - { - /* Get out of the loop! */ - pktTxStatus = 0U; - } - } - } - return HAL_OK; -} - -#ifdef HAL_ETH_USE_PTP -/** - * @brief Set the Ethernet PTP configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains - * the configuration information for PTP - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) -{ - uint32_t tmpTSCR; - ETH_TimeTypeDef time; - - if (ptpconfig == NULL) - { - return HAL_ERROR; - } - - tmpTSCR = ptpconfig->Timestamp | - ((uint32_t)ptpconfig->TimestampUpdate << ETH_PTPTSCR_TSFCU_Pos) | - ((uint32_t)ptpconfig->TimestampAll << ETH_PTPTSCR_TSSARFE_Pos) | - ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_PTPTSCR_TSSSR_Pos) | - ((uint32_t)ptpconfig->TimestampV2 << ETH_PTPTSCR_TSPTPPSV2E_Pos) | - ((uint32_t)ptpconfig->TimestampEthernet << ETH_PTPTSCR_TSSPTPOEFE_Pos) | - ((uint32_t)ptpconfig->TimestampIPv6 << ETH_PTPTSCR_TSSIPV6FE_Pos) | - ((uint32_t)ptpconfig->TimestampIPv4 << ETH_PTPTSCR_TSSIPV4FE_Pos) | - ((uint32_t)ptpconfig->TimestampEvent << ETH_PTPTSCR_TSSEME_Pos) | - ((uint32_t)ptpconfig->TimestampMaster << ETH_PTPTSCR_TSSMRME_Pos) | - ((uint32_t)ptpconfig->TimestampFilter << ETH_PTPTSCR_TSPFFMAE_Pos) | - ((uint32_t)ptpconfig->TimestampClockType << ETH_PTPTSCR_TSCNT_Pos); - - /* Write to MACTSCR */ - MODIFY_REG(heth->Instance->PTPTSCR, ETH_MACTSCR_MASK, tmpTSCR); - - /* Enable Timestamp */ - SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSE); - WRITE_REG(heth->Instance->PTPSSIR, ptpconfig->TimestampSubsecondInc); - WRITE_REG(heth->Instance->PTPTSAR, ptpconfig->TimestampAddend); - - /* Enable Timestamp */ - if (ptpconfig->TimestampAddendUpdate == ENABLE) - { - SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSARU); - while ((heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU) != 0) - { - - } - } - - /* Ptp Init */ - SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTI); - - /* Set PTP Configuration done */ - heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURED; - - /* Set Seconds */ - time.Seconds = heth->Instance->PTPTSHR; - /* Set NanoSeconds */ - time.NanoSeconds = heth->Instance->PTPTSLR; - - HAL_ETH_PTP_SetTime(heth, &time); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Get the Ethernet PTP configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains - * the configuration information for PTP - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) -{ - if (ptpconfig == NULL) - { - return HAL_ERROR; - } - ptpconfig->Timestamp = READ_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSE); - ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSFCU) >> ETH_PTPTSCR_TSFCU_Pos) > 0U) ? ENABLE : DISABLE; - ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSSARFE) >> ETH_PTPTSCR_TSSARFE_Pos) > 0U) ? ENABLE : DISABLE; - ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSSSR) >> ETH_PTPTSCR_TSSSR_Pos) > 0U) - ? ENABLE : DISABLE; - ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSPTPPSV2E) >> ETH_PTPTSCR_TSPTPPSV2E_Pos) > 0U) ? ENABLE : DISABLE; - ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSSPTPOEFE) >> ETH_PTPTSCR_TSSPTPOEFE_Pos) > 0U) - ? ENABLE : DISABLE; - ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSSIPV6FE) >> ETH_PTPTSCR_TSSIPV6FE_Pos) > 0U) ? ENABLE : DISABLE; - ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSSIPV4FE) >> ETH_PTPTSCR_TSSIPV4FE_Pos) > 0U) ? ENABLE : DISABLE; - ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSSEME) >> ETH_PTPTSCR_TSSEME_Pos) > 0U) ? ENABLE : DISABLE; - ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSSMRME) >> ETH_PTPTSCR_TSSMRME_Pos) > 0U) ? ENABLE : DISABLE; - ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSPFFMAE) >> ETH_PTPTSCR_TSPFFMAE_Pos) > 0U) ? ENABLE : DISABLE; - ptpconfig->TimestampClockType = ((READ_BIT(heth->Instance->PTPTSCR, - ETH_PTPTSCR_TSCNT) >> ETH_PTPTSCR_TSCNT_Pos) > 0U) ? ENABLE : DISABLE; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param time: pointer to a ETH_TimeTypeDef structure that contains - * time to set - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) -{ - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) - { - /* Set Seconds */ - heth->Instance->PTPTSHUR = time->Seconds; - - /* Set NanoSeconds */ - heth->Instance->PTPTSLUR = time->NanoSeconds; - - /* the system time is updated */ - SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTU); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param time: pointer to a ETH_TimeTypeDef structure that contains - * time to get - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) -{ - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) - { - /* Get Seconds */ - time->Seconds = heth->Instance->PTPTSHR; - /* Get NanoSeconds */ - time->NanoSeconds = heth->Instance->PTPTSLR; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Update time for the Ethernet PTP registers. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains - * the time update information - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, - ETH_TimeTypeDef *timeoffset) -{ - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) - { - if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE) - { - /* Set Seconds update */ - heth->Instance->PTPTSHUR = ETH_PTPTSHR_VALUE - timeoffset->Seconds + 1U; - - if (READ_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSSR) == ETH_PTPTSCR_TSSSR) - { - /* Set nanoSeconds update */ - heth->Instance->PTPTSLUR = ETH_PTPTSLR_VALUE - timeoffset->NanoSeconds; - } - else - { - heth->Instance->PTPTSLUR = ETH_PTPTSHR_VALUE - timeoffset->NanoSeconds + 1U; - } - } - else - { - /* Set Seconds update */ - heth->Instance->PTPTSHUR = timeoffset->Seconds; - /* Set nanoSeconds update */ - heth->Instance->PTPTSLUR = timeoffset->NanoSeconds; - } - - SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTU); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Insert Timestamp in transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) -{ - ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; - uint32_t descidx = dmatxdesclist->CurTxDesc; - ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; - - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) - { - /* Enable Time Stamp transmission */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TTSE); - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Get transmission timestamp. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains - * transmission timestamp - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) -{ - ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; - uint32_t idx = dmatxdesclist->releaseIndex; - ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx]; - - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) - { - /* Get timestamp low */ - timestamp->TimeStampLow = dmatxdesc->DESC0; - /* Get timestamp high */ - timestamp->TimeStampHigh = dmatxdesc->DESC1; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Get receive timestamp. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains - * receive timestamp - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) -{ - if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURED) - { - /* Get timestamp low */ - timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow; - /* Get timestamp high */ - timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Return function status */ - return HAL_ERROR; - } -} - -/** - * @brief Register the Tx Ptp callback. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param txPtpCallback: Function to handle Ptp transmission - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback) -{ - if (txPtpCallback == NULL) - { - /* No buffer to save */ - return HAL_ERROR; - } - /* Set Function to handle Tx Ptp */ - heth->txPtpCallback = txPtpCallback; - - return HAL_OK; -} - -/** - * @brief Unregister the Tx Ptp callback. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) -{ - /* Set function to allocate buffer */ - heth->txPtpCallback = HAL_ETH_TxPtpCallback; - - return HAL_OK; -} - -/** - * @brief Tx Ptp callback. - * @param buff: pointer to application buffer - * @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains - * transmission timestamp - * @retval None - */ -__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(buff); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxPtpCallback could be implemented in the user file - */ -} -#endif /* HAL_ETH_USE_PTP */ - -/** - * @brief This function handles ETH interrupt request. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) -{ - uint32_t mac_flag = READ_REG(heth->Instance->MACSR); - uint32_t dma_flag = READ_REG(heth->Instance->DMASR); - uint32_t dma_itsource = READ_REG(heth->Instance->DMAIER); - uint32_t exti_flag = READ_REG(EXTI->PR); - - /* Packet received */ - if (((dma_flag & ETH_DMASR_RS) != 0U) && ((dma_itsource & ETH_DMAIER_RIE) != 0U)) - { - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_RS | ETH_DMASR_NIS); - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Receive complete callback*/ - heth->RxCpltCallback(heth); -#else - /* Receive complete callback */ - HAL_ETH_RxCpltCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - } - - /* Packet transmitted */ - if (((dma_flag & ETH_DMASR_TS) != 0U) && ((dma_itsource & ETH_DMAIER_TIE) != 0U)) - { - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_TS | ETH_DMASR_NIS); - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Transmit complete callback*/ - heth->TxCpltCallback(heth); -#else - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - } - - /* ETH DMA Error */ - if (((dma_flag & ETH_DMASR_AIS) != 0U) && ((dma_itsource & ETH_DMAIER_AISE) != 0U)) - { - heth->ErrorCode |= HAL_ETH_ERROR_DMA; - /* if fatal bus error occurred */ - if ((dma_flag & ETH_DMASR_FBES) != 0U) - { - /* Get DMA error code */ - heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_FBES | ETH_DMASR_TPS | ETH_DMASR_RPS)); - - /* Disable all interrupts */ - __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMAIER_NISE | ETH_DMAIER_AISE); - - /* Set HAL state to ERROR */ - heth->gState = HAL_ETH_STATE_ERROR; - } - else - { - /* Get DMA error status */ - heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_ETS | ETH_DMASR_RWTS | - ETH_DMASR_RBUS | ETH_DMASR_AIS)); - - /* Clear the interrupt summary flag */ - __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMASR_ETS | ETH_DMASR_RWTS | - ETH_DMASR_RBUS | ETH_DMASR_AIS)); - } -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call registered Error callback*/ - heth->ErrorCallback(heth); -#else - /* Ethernet DMA Error callback */ - HAL_ETH_ErrorCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - } - - - /* ETH PMT IT */ - if ((mac_flag & ETH_MAC_PMT_IT) != 0U) - { - /* Get MAC Wake-up source and clear the status register pending bit */ - heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPMTCSR, (ETH_MACPMTCSR_WFR | ETH_MACPMTCSR_MPR)); - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call registered PMT callback*/ - heth->PMTCallback(heth); -#else - /* Ethernet PMT callback */ - HAL_ETH_PMTCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - heth->MACWakeUpEvent = (uint32_t)(0x0U); - } - - - /* check ETH WAKEUP exti flag */ - if ((exti_flag & ETH_WAKEUP_EXTI_LINE) != 0U) - { - /* Clear ETH WAKEUP Exti pending bit */ - __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call registered WakeUp callback*/ - heth->WakeUpCallback(heth); -#else - /* ETH WAKEUP callback */ - HAL_ETH_WakeUpCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Tx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Ethernet transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Ethernet Power Management module IT callback - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_PMTCallback could be implemented in the user file - */ -} - - -/** - * @brief ETH WAKEUP interrupt callback - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_WakeUpCallback could be implemented in the user file - */ -} - -/** - * @brief Read a PHY register - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYAddr: PHY port address, must be a value from 0 to 31 - * @param PHYReg: PHY register address, must be a value from 0 to 31 - * @param pRegValue: parameter to hold read value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, - uint32_t *pRegValue) -{ - uint32_t tmpreg1; - uint32_t tickstart; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII address register value */ - tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg1; - - - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > PHY_READ_TO) - { - return HAL_ERROR; - } - - tmpreg1 = heth->Instance->MACMIIAR; - } - - /* Get MACMIIDR value */ - *pRegValue = (uint16_t)(heth->Instance->MACMIIDR); - - return HAL_OK; -} - -/** - * @brief Writes to a PHY register. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYAddr: PHY port address, must be a value from 0 to 31 - * @param PHYReg: PHY register address, must be a value from 0 to 31 - * @param RegValue: the value to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, - uint32_t RegValue) -{ - uint32_t tmpreg1; - uint32_t tickstart; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII register address value */ - tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Give the value to the MII data register */ - heth->Instance->MACMIIDR = (uint16_t)RegValue; - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO) - { - return HAL_ERROR; - } - - tmpreg1 = heth->Instance->MACMIIAR; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief ETH control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the ETH - peripheral. - -@endverbatim - * @{ - */ -/** - * @brief Get the configuration of the MAC and MTL subsystems. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold - * the configuration of the MAC. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) -{ - if (macconf == NULL) - { - return HAL_ERROR; - } - - /* Get MAC parameters */ - macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; - macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); - macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_RD) >> 9) == 0U) ? ENABLE : DISABLE; - macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSD) >> 16) > 0U) - ? ENABLE : DISABLE; - macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ROD) >> 13) == 0U) ? ENABLE : DISABLE; - macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; - macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); - macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); - macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 22) == 0U) ? ENABLE : DISABLE; - macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 23) == 0U) ? ENABLE : DISABLE; - macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_APCS) >> 7) > 0U) ? ENABLE : DISABLE; - macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IFG); - macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPCO) >> 10U) > 0U) ? ENABLE : DISABLE; - macconf->CRCStripTypePacket = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSTF) >> 25U) > 0U) ? ENABLE : DISABLE; - - macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_TFCE) >> 1) > 0U) ? ENABLE : DISABLE; - macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_ZQPD) >> 7) == 0U) ? ENABLE : DISABLE; - macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PLT); - macconf->PauseTime = (READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PT) >> 16); - macconf->ReceiveFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_RFCE) >> 2U) > 0U) ? ENABLE : DISABLE; - macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_UPFD) >> 3U) > 0U) - ? ENABLE : DISABLE; - - return HAL_OK; -} - -/** - * @brief Get the configuration of the DMA. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold - * the configuration of the ETH DMA. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) -{ - if (dmaconf == NULL) - { - return HAL_ERROR; - } - - dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMABMR, - (ETH_DMAARBITRATION_RXPRIORTX | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1)); - dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_AAB) >> 25U) > 0U) ? ENABLE : DISABLE; - dmaconf->BurstMode = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_FB | ETH_DMABMR_MB); - dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_RDP); - dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_PBL); - dmaconf->EnhancedDescriptorFormat = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_EDE) >> 7) > 0U) ? ENABLE : DISABLE; - dmaconf->DescriptorSkipLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_DSL) >> 2; - - dmaconf->DropTCPIPChecksumErrorFrame = ((READ_BIT(heth->Instance->DMAOMR, - ETH_DMAOMR_DTCEFD) >> 26) > 0U) ? DISABLE : ENABLE; - dmaconf->ReceiveStoreForward = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RSF) >> 25) > 0U) ? ENABLE : DISABLE; - dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_FTF) >> 20) > 0U) ? DISABLE : ENABLE; - dmaconf->TransmitStoreForward = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_TSF) >> 21) > 0U) ? ENABLE : DISABLE; - dmaconf->TransmitThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_TTC); - dmaconf->ForwardErrorFrames = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_FEF) >> 7) > 0U) ? ENABLE : DISABLE; - dmaconf->ForwardUndersizedGoodFrames = ((READ_BIT(heth->Instance->DMAOMR, - ETH_DMAOMR_FUGF) >> 6) > 0U) ? ENABLE : DISABLE; - dmaconf->ReceiveThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RTC); - dmaconf->SecondFrameOperate = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_OSF) >> 2) > 0U) ? ENABLE : DISABLE; - - return HAL_OK; -} - -/** - * @brief Set the MAC configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains - * the configuration of the MAC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) -{ - if (macconf == NULL) - { - return HAL_ERROR; - } - - if (heth->gState == HAL_ETH_STATE_READY) - { - ETH_SetMACConfig(heth, macconf); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Set the ETH DMA configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold - * the configuration of the ETH DMA. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) -{ - if (dmaconf == NULL) - { - return HAL_ERROR; - } - - if (heth->gState == HAL_ETH_STATE_READY) - { - ETH_SetDMAConfig(heth, dmaconf); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configures the Clock range of ETH MDIO interface. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) -{ - uint32_t hclk; - uint32_t tmpreg; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg = (heth->Instance)->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg &= ETH_MACMIIAR_CR_MASK; - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - /* Set CR bits depending on hclk value */ - if (hclk < 35000000U) - { - /* CSR Clock Range between 0-35 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; - } - else if (hclk < 60000000U) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else if (hclk < 100000000U) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } - else if (hclk < 150000000U) - { - /* CSR Clock Range between 100-150 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; - } - else /* (hclk >= 150000000) */ - { - /* CSR Clock >= 150 MHz */ - tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; - } - - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - (heth->Instance)->MACMIIAR = (uint32_t)tmpreg; -} - -/** - * @brief Set the ETH MAC (L2) Filters configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains - * the configuration of the ETH MAC filters. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig) -{ - uint32_t filterconfig; - uint32_t tmpreg1; - - if (pFilterConfig == NULL) - { - return HAL_ERROR; - } - - filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode | - ((uint32_t)pFilterConfig->HashUnicast << 1) | - ((uint32_t)pFilterConfig->HashMulticast << 2) | - ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | - ((uint32_t)pFilterConfig->PassAllMulticast << 4) | - ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | - ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | - ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | - ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | - ((uint32_t)pFilterConfig->ReceiveAllMode << 31) | - pFilterConfig->ControlPacketsFilter); - - MODIFY_REG(heth->Instance->MACFFR, ETH_MACFFR_MASK, filterconfig); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg1; - - return HAL_OK; -} - -/** - * @brief Get the ETH MAC (L2) Filters configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold - * the configuration of the ETH MAC filters. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) -{ - if (pFilterConfig == NULL) - { - return HAL_ERROR; - } - - pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PM)) > 0U) ? ENABLE : DISABLE; - pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HU) >> 1) > 0U) ? ENABLE : DISABLE; - pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HM) >> 2) > 0U) ? ENABLE : DISABLE; - pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR, - ETH_MACFFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; - pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PAM) >> 4) > 0U) ? ENABLE : DISABLE; - pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_BFD) >> 5) == 0U) ? ENABLE : DISABLE; - pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PCF); - pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR, - ETH_MACFFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; - pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE; - pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HPF) >> 10) > 0U) - ? ENABLE : DISABLE; - pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_RA) >> 31) > 0U) ? ENABLE : DISABLE; - - return HAL_OK; -} - -/** - * @brief Set the source MAC Address to be matched. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param AddrNbr: The MAC address to configure - * This parameter must be a value of the following: - * ETH_MAC_ADDRESS1 - * ETH_MAC_ADDRESS2 - * ETH_MAC_ADDRESS3 - * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, - const uint8_t *pMACAddr) -{ - uint32_t macaddrlr; - uint32_t macaddrhr; - - if (pMACAddr == NULL) - { - return HAL_ERROR; - } - - /* Get mac addr high reg offset */ - macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr); - /* Get mac addr low reg offset */ - macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr); - - /* Set MAC addr bits 32 to 47 */ - (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]); - /* Set MAC addr bits 0 to 31 */ - (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) | - ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]); - - /* Enable address and set source address bit */ - (*(__IO uint32_t *)macaddrhr) |= (ETH_MACA1HR_AE | ETH_MACA1HR_SA); - - return HAL_OK; -} - -/** - * @brief Set the ETH Hash Table Value. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pHashTable: pointer to a table of two 32 bit values, that contains - * the 64 bits of the hash table. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable) -{ - uint32_t tmpreg1; - if (pHashTable == NULL) - { - return HAL_ERROR; - } - - heth->Instance->MACHTHR = pHashTable[0]; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACHTHR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACHTHR = tmpreg1; - - heth->Instance->MACHTLR = pHashTable[1]; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACHTLR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACHTLR = tmpreg1; - - return HAL_OK; -} - -/** - * @brief Set the VLAN Identifier for Rx packets - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param ComparisonBits: 12 or 16 bit comparison mode - must be a value of @ref ETH_VLAN_Tag_Comparison - * @param VLANIdentifier: VLAN Identifier value - * @retval None - */ -void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier) -{ - uint32_t tmpreg1; - MODIFY_REG(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTI, VLANIdentifier); - if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) - { - CLEAR_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC); - } - else - { - SET_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC); - } - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg1; -} - -/** - * @brief Enters the Power down mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure - * that contains the Power Down configuration - * @retval None. - */ -void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig) -{ - uint32_t powerdownconfig; - - powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << ETH_MACPMTCSR_MPE_Pos) | - ((uint32_t)pPowerDownConfig->WakeUpPacket << ETH_MACPMTCSR_WFE_Pos) | - ((uint32_t)pPowerDownConfig->GlobalUnicast << ETH_MACPMTCSR_GU_Pos) | - ETH_MACPMTCSR_PD); - - MODIFY_REG(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_MASK, powerdownconfig); -} - -/** - * @brief Exits from the Power down mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None. - */ -void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) -{ - uint32_t tmpreg1; - - /* clear wake up sources */ - CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFE | ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACPMTCSR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACPMTCSR = tmpreg1; - - if (READ_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD) != 0U) - { - /* Exit power down mode */ - CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACPMTCSR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACPMTCSR = tmpreg1; - } - - /* Disable PMT interrupt */ - SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_PMTIM); -} - -/** - * @brief Set the WakeUp filter. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pFilter: pointer to filter registers values - * @param Count: number of filter registers, must be from 1 to 8. - * @retval None. - */ -HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count) -{ - uint32_t regindex; - - if (pFilter == NULL) - { - return HAL_ERROR; - } - - /* Reset Filter Pointer */ - SET_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFFRPR); - - /* Wake up packet filter config */ - for (regindex = 0; regindex < Count; regindex++) - { - /* Write filter regs */ - WRITE_REG(heth->Instance->MACRWUFFR, pFilter[regindex]); - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief ETH State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of - ETH communication process, return Peripheral Errors occurred during communication - process - - -@endverbatim - * @{ - */ - -/** - * @brief Returns the ETH state. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL state - */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(const ETH_HandleTypeDef *heth) -{ - return heth->gState; -} - -/** - * @brief Returns the ETH error code - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval ETH Error Code - */ -uint32_t HAL_ETH_GetError(const ETH_HandleTypeDef *heth) -{ - return heth->ErrorCode; -} - -/** - * @brief Returns the ETH DMA error code - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval ETH DMA Error Code - */ -uint32_t HAL_ETH_GetDMAError(const ETH_HandleTypeDef *heth) -{ - return heth->DMAErrorCode; -} - -/** - * @brief Returns the ETH MAC error code - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval ETH MAC Error Code - */ -uint32_t HAL_ETH_GetMACError(const ETH_HandleTypeDef *heth) -{ - return heth->MACErrorCode; -} - -/** - * @brief Returns the ETH MAC WakeUp event source - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval ETH MAC WakeUp event source - */ -uint32_t HAL_ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) -{ - return heth->MACWakeUpEvent; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup ETH_Private_Functions ETH Private Functions - * @{ - */ - -/** - * @brief Clears the ETHERNET transmit FIFO. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg = 0; - - /* Set the Flush Transmit FIFO bit */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg; -} - -static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf) -{ - uint32_t tmpreg1; - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg1 = (heth->Instance)->MACCR; - /* Clear CSTF, WD, PCE, PS, TE and RE bits */ - tmpreg1 &= ETH_MACCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)(((uint32_t)macconf->CRCStripTypePacket << 25U) | - ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | - ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | - (uint32_t)macconf->InterPacketGapVal | - ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | - macconf->Speed | - ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | - ((uint32_t)macconf->LoopbackMode << 12U) | - macconf->DuplexMode | - ((uint32_t)macconf->ChecksumOffload << 10U) | - ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | - ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | - macconf->BackOffLimit | - ((uint32_t)macconf->DeferralCheck << 4U)); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg1 = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | - ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | - macconf->PauseLowThreshold | - ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | - ((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) | - ((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U)); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg1; -} - -static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf) -{ - uint32_t tmpreg1; - - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ - tmpreg1 = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | - ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | - ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | - ((uint32_t)dmaconf->TransmitStoreForward << 21U) | - dmaconf->TransmitThresholdControl | - ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | - ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | - dmaconf->ReceiveThresholdControl | - ((uint32_t)dmaconf->SecondFrameOperate << 2U)); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; - - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | - dmaconf->BurstMode | - dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or - Rx it is applied for the other */ - dmaconf->TxDMABurstLength | - ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | - (dmaconf->DescriptorSkipLength << 2U) | - dmaconf->DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg1; -} - -/** - * @brief Configures Ethernet MAC and DMA with default parameters. - * called by HAL_ETH_Init() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) -{ - ETH_MACConfigTypeDef macDefaultConf; - ETH_DMAConfigTypeDef dmaDefaultConf; - - /*--------------- ETHERNET MAC registers default Configuration --------------*/ - macDefaultConf.Watchdog = ENABLE; - macDefaultConf.Jabber = ENABLE; - macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT; - macDefaultConf.CarrierSenseDuringTransmit = DISABLE; - macDefaultConf.ReceiveOwn = ENABLE; - macDefaultConf.LoopbackMode = DISABLE; - macDefaultConf.CRCStripTypePacket = ENABLE; - macDefaultConf.ChecksumOffload = ENABLE; - macDefaultConf.RetryTransmission = DISABLE; - macDefaultConf.AutomaticPadCRCStrip = DISABLE; - macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; - macDefaultConf.DeferralCheck = DISABLE; - macDefaultConf.PauseTime = 0x0U; - macDefaultConf.ZeroQuantaPause = DISABLE; - macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; - macDefaultConf.ReceiveFlowControl = DISABLE; - macDefaultConf.TransmitFlowControl = DISABLE; - macDefaultConf.Speed = ETH_SPEED_100M; - macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; - macDefaultConf.UnicastPausePacketDetect = DISABLE; - - /* MAC default configuration */ - ETH_SetMACConfig(heth, &macDefaultConf); - - /*--------------- ETHERNET DMA registers default Configuration --------------*/ - dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE; - dmaDefaultConf.ReceiveStoreForward = ENABLE; - dmaDefaultConf.FlushRxPacket = ENABLE; - dmaDefaultConf.TransmitStoreForward = ENABLE; - dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; - dmaDefaultConf.ForwardErrorFrames = DISABLE; - dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE; - dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; - dmaDefaultConf.SecondFrameOperate = ENABLE; - dmaDefaultConf.AddressAlignedBeats = ENABLE; - dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; - dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; - dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmaDefaultConf.EnhancedDescriptorFormat = ENABLE; - dmaDefaultConf.DescriptorSkipLength = 0x0U; - dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - - /* DMA default configuration */ - ETH_SetDMAConfig(heth, &dmaDefaultConf); -} -/** - * @brief Configures the selected MAC address. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param MacAddr The MAC address to configure - * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 - * @arg ETH_MAC_Address2: MAC Address2 - * @arg ETH_MAC_Address3: MAC Address3 - * @param Addr Pointer to MAC address buffer data (6 bytes) - * @retval HAL status - */ -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) -{ - uint32_t tmpreg1; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - - /* Calculate the selected MAC address high register */ - tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; - /* Load the selected MAC address high register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; - /* Calculate the selected MAC address low register */ - tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; - - /* Load the selected MAC address low register */ - (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; -} - -/** - * @brief Initializes the DMA Tx descriptors. - * called by HAL_ETH_Init() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) -{ - ETH_DMADescTypeDef *dmatxdesc; - uint32_t i; - - /* Fill each DMATxDesc descriptor with the right values */ - for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) - { - dmatxdesc = heth->Init.TxDesc + i; - - WRITE_REG(dmatxdesc->DESC0, 0x0U); - WRITE_REG(dmatxdesc->DESC1, 0x0U); - WRITE_REG(dmatxdesc->DESC2, 0x0U); - WRITE_REG(dmatxdesc->DESC3, 0x0U); - - WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); - - /* Set Second Address Chained bit */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH); - - if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U)) - { - WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U)); - } - else - { - WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc)); - } - - /* Set the DMA Tx descriptors checksum insertion */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL); - } - - heth->TxDescList.CurTxDesc = 0; - - /* Set Transmit Descriptor List Address */ - WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc); -} - -/** - * @brief Initializes the DMA Rx descriptors in chain mode. - * called by HAL_ETH_Init() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) -{ - ETH_DMADescTypeDef *dmarxdesc; - uint32_t i; - - for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) - { - dmarxdesc = heth->Init.RxDesc + i; - - WRITE_REG(dmarxdesc->DESC0, 0x0U); - WRITE_REG(dmarxdesc->DESC1, 0x0U); - WRITE_REG(dmarxdesc->DESC2, 0x0U); - WRITE_REG(dmarxdesc->DESC3, 0x0U); - WRITE_REG(dmarxdesc->BackupAddr0, 0x0U); - WRITE_REG(dmarxdesc->BackupAddr1, 0x0U); - - /* Set Own bit of the Rx descriptor Status */ - dmarxdesc->DESC0 = ETH_DMARXDESC_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - dmarxdesc->DESC1 = heth->Init.RxBuffLen | ETH_DMARXDESC_RCH; - - /* Enable Ethernet DMA Rx Descriptor interrupt */ - dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC; - /* Set Rx descritors addresses */ - WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); - - if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U)) - { - WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U)); - } - else - { - WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc)); - } - } - - WRITE_REG(heth->RxDescList.RxDescIdx, 0U); - WRITE_REG(heth->RxDescList.RxDescCnt, 0U); - WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U); - WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U); - WRITE_REG(heth->RxDescList.ItMode, 0U); - - /* Set Receive Descriptor List Address */ - WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc); -} - -/** - * @brief Prepare Tx DMA descriptor before transmission. - * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param pTxConfig: Tx packet configuration - * @param ItMode: Enable or disable Tx EOT interrept - * @retval Status - */ -static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, - uint32_t ItMode) -{ - ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; - uint32_t descidx = dmatxdesclist->CurTxDesc; - uint32_t firstdescidx = dmatxdesclist->CurTxDesc; - uint32_t idx; - uint32_t descnbr = 0; - ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; - - ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; - uint32_t bd_count = 0; - uint32_t primask_bit; - - /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ - if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN) - || (dmatxdesclist->PacketAddress[descidx] != NULL)) - { - return HAL_ETH_ERROR_BUSY; - } - - - descnbr += 1U; - - /* Set header or buffer 1 address */ - WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); - - /* Set header or buffer 1 Length */ - MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len); - - if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U) - { - MODIFY_REG(dmatxdesc->DESC0, ETH_DMATXDESC_CIC, pTxConfig->ChecksumCtrl); - } - - if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U) - { - MODIFY_REG(dmatxdesc->DESC0, ETH_CRC_PAD_DISABLE, pTxConfig->CRCPadCtrl); - } - - - if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U) - { - /* Set Vlan Type */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_VF); - } - - /* Mark it as First Descriptor */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS); - - /* only if the packet is split into more than one descriptors > 1 */ - while (txbuffer->next != NULL) - { - /* Clear the LD bit of previous descriptor */ - CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS); - if (ItMode != ((uint32_t)RESET)) - { - /* Set Interrupt on completion bit */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); - } - else - { - /* Clear Interrupt on completion bit */ - CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); - } - /* Increment current tx descriptor index */ - INCR_TX_DESC_INDEX(descidx, 1U); - /* Get current descriptor address */ - dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; - - /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ - if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN) - || (dmatxdesclist->PacketAddress[descidx] != NULL)) - { - descidx = firstdescidx; - dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; - - /* clear previous desc own bit */ - for (idx = 0; idx < descnbr; idx ++) - { - /* Ensure rest of descriptor is written to RAM before the OWN bit */ - __DMB(); - - CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); - - /* Increment current tx descriptor index */ - INCR_TX_DESC_INDEX(descidx, 1U); - /* Get current descriptor address */ - dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; - } - - return HAL_ETH_ERROR_BUSY; - } - - /* Clear the FD bit of new Descriptor */ - CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS); - - descnbr += 1U; - - /* Get the next Tx buffer in the list */ - txbuffer = txbuffer->next; - - /* Set header or buffer 1 address */ - WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); - - /* Set header or buffer 1 Length */ - MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len); - - bd_count += 1U; - - /* Ensure rest of descriptor is written to RAM before the OWN bit */ - __DMB(); - /* Set Own bit */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); - } - - if (ItMode != ((uint32_t)RESET)) - { - /* Set Interrupt on completion bit */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); - } - else - { - /* Clear Interrupt on completion bit */ - CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); - } - - /* Mark it as LAST descriptor */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS); - - /* Get address of first descriptor */ - dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[firstdescidx]; - /* Ensure rest of descriptor is written to RAM before the OWN bit */ - __DMB(); - /* set OWN bit of FIRST descriptor */ - SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); - /* Save the current packet address to expose it to the application */ - dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; - - dmatxdesclist->CurTxDesc = descidx; - - /* Enter critical section */ - primask_bit = __get_PRIMASK(); - __set_PRIMASK(1); - - dmatxdesclist->BuffersInUse += bd_count + 1U; - - /* Exit critical section: restore previous priority mask */ - __set_PRIMASK(primask_bit); - - /* Return function status */ - return HAL_ETH_ERROR_NONE; -} - -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) -{ - /* Init the ETH Callback settings */ - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ - heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */ - heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ - heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ - heth->rxLinkCallback = HAL_ETH_RxLinkCallback; /* Legacy weak RxLinkCallback */ - heth->txFreeCallback = HAL_ETH_TxFreeCallback; /* Legacy weak TxFreeCallback */ -#ifdef HAL_ETH_USE_PTP - heth->txPtpCallback = HAL_ETH_TxPtpCallback; /* Legacy weak TxPtpCallback */ -#endif /* HAL_ETH_USE_PTP */ - heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */ -} -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ETH */ - -#endif /* HAL_ETH_MODULE_ENABLED */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c index 3feffc6f..b9840a9b 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_exti.c @@ -1,547 +1,547 @@ -/** - ****************************************************************************** - * @file stm32F7xx_hal_exti.c - * @author MCD Application Team - * @brief EXTI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2018 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### EXTI Peripheral features ##### - ============================================================================== - [..] - (+) Each Exti line can be configured within this driver. - - (+) Exti line can be configured in 3 different modes - (++) Interrupt - (++) Event - (++) Both of them - - (+) Configurable Exti lines can be configured with 3 different triggers - (++) Rising - (++) Falling - (++) Both of them - - (+) When set in interrupt mode, configurable Exti lines have two different - interrupts pending registers which allow to distinguish which transition - occurs: - (++) Rising edge pending interrupt - (++) Falling - - (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can - be selected through multiplexer. - - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). - (++) Choose the interrupt line number by setting "Line" member from - EXTI_ConfigTypeDef structure. - (++) Configure the interrupt and/or event mode using "Mode" member from - EXTI_ConfigTypeDef structure. - (++) For configurable lines, configure rising and/or falling trigger - "Trigger" member from EXTI_ConfigTypeDef structure. - (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" - member from GPIO_InitTypeDef structure. - - (#) Get current Exti configuration of a dedicated line using - HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). - (++) Provide exiting handle as parameter. - - (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). - (++) Provide exiting handle as first parameter. - (++) Provide which callback will be registered using one value from - EXTI_CallbackIDTypeDef. - (++) Provide callback function pointer. - - (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). - - (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ -/** MISRA C:2012 deviation rule has been granted for following rule: - * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out - * of bounds [0,3] in following API : - * HAL_EXTI_SetConfigLine - * HAL_EXTI_GetConfigLine - * HAL_EXTI_ClearConfigLine - */ - -#ifdef HAL_EXTI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup EXTI_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_Exported_Functions_Group1 - * @brief Configuration functions - * -@verbatim - =============================================================================== - ##### Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Set configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on EXTI configuration to be set. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_EXTI_LINE(pExtiConfig->Line)); - assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); - - /* Assign line number to handle */ - hexti->Line = pExtiConfig->Line; - - /* Compute line mask */ - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* Configure triggers for configurable lines */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) - { - assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); - - /* Configure rising trigger */ - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) - { - EXTI->RTSR |= maskline; - } - else - { - EXTI->RTSR &= ~maskline; - } - - /* Configure falling trigger */ - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) - { - EXTI->FTSR |= maskline; - } - else - { - EXTI->FTSR &= ~maskline; - } - - - /* Configure gpio port selection in case of gpio exti line */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = SYSCFG->EXTICR[linepos >> 2u]; - regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - SYSCFG->EXTICR[linepos >> 2u] = regval; - } - } - - /* Configure interrupt mode : read current mode */ - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) - { - EXTI->IMR |= maskline; - } - else - { - EXTI->IMR &= ~maskline; - } - - /* Configure event mode : read current mode */ - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) - { - EXTI->EMR |= maskline; - } - else - { - EXTI->EMR &= ~maskline; - } - - return HAL_OK; -} - -/** - * @brief Get configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on structure to store Exti configuration. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* Store handle line number to configuration structure */ - pExtiConfig->Line = hexti->Line; - - /* Compute line mask */ - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* 1] Get core mode : interrupt */ - - /* Check if selected line is enable */ - if ((EXTI->IMR & maskline) != 0x00u) - { - pExtiConfig->Mode = EXTI_MODE_INTERRUPT; - } - else - { - pExtiConfig->Mode = EXTI_MODE_NONE; - } - - /* Get event mode */ - /* Check if selected line is enable */ - if ((EXTI->EMR & maskline) != 0x00u) - { - pExtiConfig->Mode |= EXTI_MODE_EVENT; - } - - /* Get default Trigger and GPIOSel configuration */ - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; - - /* 2] Get trigger for configurable lines : rising */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) - { - /* Check if configuration of selected line is enable */ - if ((EXTI->RTSR & maskline) != 0x00u) - { - pExtiConfig->Trigger = EXTI_TRIGGER_RISING; - } - - /* Get falling configuration */ - /* Check if configuration of selected line is enable */ - if ((EXTI->FTSR & maskline) != 0x00u) - { - pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; - } - - /* Get Gpio port selection for gpio lines */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = SYSCFG->EXTICR[linepos >> 2u]; - pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; - } - } - - return HAL_OK; -} - -/** - * @brief Clear whole configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* compute line mask */ - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* 1] Clear interrupt mode */ - EXTI->IMR = (EXTI->IMR & ~maskline); - - /* 2] Clear event mode */ - EXTI->EMR = (EXTI->EMR & ~maskline); - - /* 3] Clear triggers in case of configurable lines */ - if ((hexti->Line & EXTI_CONFIG) != 0x00u) - { - EXTI->RTSR = (EXTI->RTSR & ~maskline); - EXTI->FTSR = (EXTI->FTSR & ~maskline); - - /* Get Gpio port selection for gpio lines */ - if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = SYSCFG->EXTICR[linepos >> 2u]; - regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); - SYSCFG->EXTICR[linepos >> 2u] = regval; - } - } - - return HAL_OK; -} - -/** - * @brief Register callback for a dedicated Exti line. - * @param hexti Exti handle. - * @param CallbackID User callback identifier. - * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. - * @param pPendingCbfn function pointer to be stored as callback. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) -{ - HAL_StatusTypeDef status = HAL_OK; - - switch (CallbackID) - { - case HAL_EXTI_COMMON_CB_ID: - hexti->PendingCallback = pPendingCbfn; - break; - - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Store line number as handle private field. - * @param hexti Exti handle. - * @param ExtiLine Exti line number. - * This parameter can be from 0 to @ref EXTI_LINE_NB. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(ExtiLine)); - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - else - { - /* Store line number as handle private field */ - hexti->Line = ExtiLine; - - return HAL_OK; - } -} - -/** - * @} - */ - -/** @addtogroup EXTI_Exported_Functions_Group2 - * @brief EXTI IO functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Handle EXTI interrupt request. - * @param hexti Exti handle. - * @retval none. - */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) -{ - uint32_t regval; - uint32_t maskline; - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Get pending bit */ - regval = (EXTI->PR & maskline); - if (regval != 0x00u) - { - /* Clear pending bit */ - EXTI->PR = maskline; - - /* Call callback */ - if (hexti->PendingCallback != NULL) - { - hexti->PendingCallback(); - } - } -} - -/** - * @brief Get interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be checked. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING_FALLING - * This parameter is kept for compatibility with other series. - * @retval 1 if interrupt is pending else 0. - */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* Compute line mask */ - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1uL << linepos); - - /* return 1 if bit is set else 0 */ - regval = ((EXTI->PR & maskline) >> linepos); - return regval; -} - -/** - * @brief Clear interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be clear. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING_FALLING - * This parameter is kept for compatibility with other series. - * @retval None. - */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Clear Pending bit */ - EXTI->PR = maskline; -} - -/** - * @brief Generate a software interrupt for a dedicated line. - * @param hexti Exti handle. - * @retval None. - */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) -{ - uint32_t maskline; - - /* Check parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - - /* Compute line mask */ - maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); - - /* Generate Software interrupt */ - EXTI->SWIER = maskline; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_EXTI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32F7xx_hal_exti.c + * @author MCD Application Team + * @brief EXTI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Extended Interrupts and events controller (EXTI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### EXTI Peripheral features ##### + ============================================================================== + [..] + (+) Each Exti line can be configured within this driver. + + (+) Exti line can be configured in 3 different modes + (++) Interrupt + (++) Event + (++) Both of them + + (+) Configurable Exti lines can be configured with 3 different triggers + (++) Rising + (++) Falling + (++) Both of them + + (+) When set in interrupt mode, configurable Exti lines have two different + interrupts pending registers which allow to distinguish which transition + occurs: + (++) Rising edge pending interrupt + (++) Falling + + (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can + be selected through multiplexer. + + ##### How to use this driver ##### + ============================================================================== + [..] + + (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). + (++) Choose the interrupt line number by setting "Line" member from + EXTI_ConfigTypeDef structure. + (++) Configure the interrupt and/or event mode using "Mode" member from + EXTI_ConfigTypeDef structure. + (++) For configurable lines, configure rising and/or falling trigger + "Trigger" member from EXTI_ConfigTypeDef structure. + (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" + member from GPIO_InitTypeDef structure. + + (#) Get current Exti configuration of a dedicated line using + HAL_EXTI_GetConfigLine(). + (++) Provide exiting handle as parameter. + (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. + + (#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine(). + (++) Provide exiting handle as parameter. + + (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). + (++) Provide exiting handle as first parameter. + (++) Provide which callback will be registered using one value from + EXTI_CallbackIDTypeDef. + (++) Provide callback function pointer. + + (#) Get interrupt pending bit using HAL_EXTI_GetPending(). + + (#) Clear interrupt pending bit using HAL_EXTI_ClearPending(). + + (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup EXTI + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rule: + * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out + * of bounds [0,3] in following API : + * HAL_EXTI_SetConfigLine + * HAL_EXTI_GetConfigLine + * HAL_EXTI_ClearConfigLine + */ + +#ifdef HAL_EXTI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup EXTI_Private_Constants EXTI Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup EXTI_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_Exported_Functions_Group1 + * @brief Configuration functions + * +@verbatim + =============================================================================== + ##### Configuration functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Set configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on EXTI configuration to be set. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_EXTI_LINE(pExtiConfig->Line)); + assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); + + /* Assign line number to handle */ + hexti->Line = pExtiConfig->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* Configure triggers for configurable lines */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); + + /* Configure rising trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u) + { + EXTI->RTSR |= maskline; + } + else + { + EXTI->RTSR &= ~maskline; + } + + /* Configure falling trigger */ + /* Mask or set line */ + if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u) + { + EXTI->FTSR |= maskline; + } + else + { + EXTI->FTSR &= ~maskline; + } + + + /* Configure gpio port selection in case of gpio exti line */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + /* Configure interrupt mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u) + { + EXTI->IMR |= maskline; + } + else + { + EXTI->IMR &= ~maskline; + } + + /* Configure event mode : read current mode */ + /* Mask or set line */ + if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u) + { + EXTI->EMR |= maskline; + } + else + { + EXTI->EMR &= ~maskline; + } + + return HAL_OK; +} + +/** + * @brief Get configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @param pExtiConfig Pointer on structure to store Exti configuration. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if ((hexti == NULL) || (pExtiConfig == NULL)) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* Store handle line number to configuration structure */ + pExtiConfig->Line = hexti->Line; + + /* Compute line mask */ + linepos = (pExtiConfig->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Get core mode : interrupt */ + + /* Check if selected line is enable */ + if ((EXTI->IMR & maskline) != 0x00u) + { + pExtiConfig->Mode = EXTI_MODE_INTERRUPT; + } + else + { + pExtiConfig->Mode = EXTI_MODE_NONE; + } + + /* Get event mode */ + /* Check if selected line is enable */ + if ((EXTI->EMR & maskline) != 0x00u) + { + pExtiConfig->Mode |= EXTI_MODE_EVENT; + } + + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + + /* 2] Get trigger for configurable lines : rising */ + if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) + { + /* Check if configuration of selected line is enable */ + if ((EXTI->RTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger = EXTI_TRIGGER_RISING; + } + + /* Get falling configuration */ + /* Check if configuration of selected line is enable */ + if ((EXTI->FTSR & maskline) != 0x00u) + { + pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; + } + + /* Get Gpio port selection for gpio lines */ + if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; + } + } + + return HAL_OK; +} + +/** + * @brief Clear whole configuration of a dedicated Exti line. + * @param hexti Exti handle. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + + /* Check the parameter */ + assert_param(IS_EXTI_LINE(hexti->Line)); + + /* compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* 1] Clear interrupt mode */ + EXTI->IMR = (EXTI->IMR & ~maskline); + + /* 2] Clear event mode */ + EXTI->EMR = (EXTI->EMR & ~maskline); + + /* 3] Clear triggers in case of configurable lines */ + if ((hexti->Line & EXTI_CONFIG) != 0x00u) + { + EXTI->RTSR = (EXTI->RTSR & ~maskline); + EXTI->FTSR = (EXTI->FTSR & ~maskline); + + /* Get Gpio port selection for gpio lines */ + if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) + { + assert_param(IS_EXTI_GPIO_PIN(linepos)); + + regval = SYSCFG->EXTICR[linepos >> 2u]; + regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))); + SYSCFG->EXTICR[linepos >> 2u] = regval; + } + } + + return HAL_OK; +} + +/** + * @brief Register callback for a dedicated Exti line. + * @param hexti Exti handle. + * @param CallbackID User callback identifier. + * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. + * @param pPendingCbfn function pointer to be stored as callback. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)) +{ + HAL_StatusTypeDef status = HAL_OK; + + switch (CallbackID) + { + case HAL_EXTI_COMMON_CB_ID: + hexti->PendingCallback = pPendingCbfn; + break; + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Store line number as handle private field. + * @param hexti Exti handle. + * @param ExtiLine Exti line number. + * This parameter can be from 0 to @ref EXTI_LINE_NB. + * @retval HAL Status. + */ +HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) +{ + /* Check the parameters */ + assert_param(IS_EXTI_LINE(ExtiLine)); + + /* Check null pointer */ + if (hexti == NULL) + { + return HAL_ERROR; + } + else + { + /* Store line number as handle private field */ + hexti->Line = ExtiLine; + + return HAL_OK; + } +} + +/** + * @} + */ + +/** @addtogroup EXTI_Exported_Functions_Group2 + * @brief EXTI IO functions. + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Handle EXTI interrupt request. + * @param hexti Exti handle. + * @retval none. + */ +void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +{ + uint32_t regval; + uint32_t maskline; + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Get pending bit */ + regval = (EXTI->PR & maskline); + if (regval != 0x00u) + { + /* Clear pending bit */ + EXTI->PR = maskline; + + /* Call callback */ + if (hexti->PendingCallback != NULL) + { + hexti->PendingCallback(); + } + } +} + +/** + * @brief Get interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be checked. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval 1 if interrupt is pending else 0. + */ +uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t regval; + uint32_t linepos; + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + linepos = (hexti->Line & EXTI_PIN_MASK); + maskline = (1uL << linepos); + + /* return 1 if bit is set else 0 */ + regval = ((EXTI->PR & maskline) >> linepos); + return regval; +} + +/** + * @brief Clear interrupt pending bit of a dedicated line. + * @param hexti Exti handle. + * @param Edge Specify which pending edge as to be clear. + * This parameter can be one of the following values: + * @arg @ref EXTI_TRIGGER_RISING_FALLING + * This parameter is kept for compatibility with other series. + * @retval None. + */ +void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + assert_param(IS_EXTI_PENDING_EDGE(Edge)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Clear Pending bit */ + EXTI->PR = maskline; +} + +/** + * @brief Generate a software interrupt for a dedicated line. + * @param hexti Exti handle. + * @retval None. + */ +void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +{ + uint32_t maskline; + + /* Check parameters */ + assert_param(IS_EXTI_LINE(hexti->Line)); + assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); + + /* Compute line mask */ + maskline = (1uL << (hexti->Line & EXTI_PIN_MASK)); + + /* Generate Software interrupt */ + EXTI->SWIER = maskline; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_EXTI_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c index d82d6295..c3ce7e83 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash.c @@ -1,819 +1,825 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral Errors functions - * - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - - [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses - to the Flash memory. It implements the erase and program Flash memory operations - and the read and write protection mechanisms. - - [..] The Flash memory interface accelerates code execution with a system of instruction - prefetch and cache lines. - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Prefetch on I-Code - (+) 64 cache lines of 128 bits on I-Code - (+) 8 cache lines of 128 bits on D-Code - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32F7xx devices. - - (#) FLASH Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Program functions: byte, half word, word and double word - (++) There Two modes of programming : - (+++) Polling mode using HAL_FLASH_Program() function - (+++) Interrupt mode using HAL_FLASH_Program_IT() function - - (#) Interrupts and flags management functions : - (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() - (++) Wait for last FLASH operation according to its status - (++) Get error flag status by calling HAL_SetErrorCode() - [..] - In addition to these functions, this driver includes a set of macros allowing - to handle the following operations: - (+) Set the latency - (+) Enable/Disable the prefetch buffer - (+) Enable/Disable the Instruction cache and the Data cache - (+) Reset the Instruction cache and the Data cache - (+) Enable/Disable the FLASH interrupts - (+) Monitor the FLASH flags status - [..] - (@) For any Flash memory program operation (erase or program), the CPU clock frequency - (HCLK) must be at least 1MHz. - (@) The contents of the Flash memory are not guaranteed if a device reset occurs during - a Flash memory operation. - (@) Any attempt to read the Flash memory while it is being written or erased, causes the - bus to stall. Read operations are processed correctly once the program operation has - completed. This means that code or data fetches cannot be performed while a write/erase - operation is ongoing. - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup FLASH_Private_Constants - * @{ - */ -#define SECTOR_MASK ((uint32_t)0xFFFFFF07U) -#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup FLASH_Private_Variables - * @{ - */ -/* Variable used for Erase sectors under interruption */ -FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup FLASH_Private_Functions - * @{ - */ -/* Program operations */ -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); -static void FLASH_Program_Word(uint32_t Address, uint32_t Data); -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); -static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); -static void FLASH_SetErrorCode(void); - -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim - =============================================================================== - ##### Programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations. - -@endverbatim - * @{ - */ - -/** - * @brief Program byte, halfword, word or double word at a specified address - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - switch(TypeProgram) - { - case FLASH_TYPEPROGRAM_BYTE : - { - /*Program byte (8-bit) at a specified address.*/ - FLASH_Program_Byte(Address, (uint8_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_HALFWORD : - { - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(Address, (uint16_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_WORD : - { - /*Program word (32-bit) at a specified address.*/ - FLASH_Program_Word(Address, (uint32_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_DOUBLEWORD : - { - /*Program double word (64-bit) at a specified address.*/ - FLASH_Program_DoubleWord(Address, Data); - break; - } - default : - break; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); - - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - pFlash.Address = Address; - - switch(TypeProgram) - { - case FLASH_TYPEPROGRAM_BYTE : - { - /*Program byte (8-bit) at a specified address.*/ - FLASH_Program_Byte(Address, (uint8_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_HALFWORD : - { - /*Program halfword (16-bit) at a specified address.*/ - FLASH_Program_HalfWord(Address, (uint16_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_WORD : - { - /*Program word (32-bit) at a specified address.*/ - FLASH_Program_Word(Address, (uint32_t) Data); - break; - } - - case FLASH_TYPEPROGRAM_DOUBLEWORD : - { - /*Program double word (64-bit) at a specified address.*/ - FLASH_Program_DoubleWord(Address, Data); - break; - } - default : - break; - } - return status; -} - -/** - * @brief This function handles FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t temp = 0; - - /* If the program operation is completed, disable the PG Bit */ - FLASH->CR &= (~FLASH_CR_PG); - - /* If the erase operation is completed, disable the SER Bit */ - FLASH->CR &= (~FLASH_CR_SER); - FLASH->CR &= SECTOR_MASK; - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_MER_BIT); - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - - switch (pFlash.ProcedureOnGoing) - { - case FLASH_PROC_SECTERASE : - { - /* Nb of sector to erased can be decreased */ - pFlash.NbSectorsToErase--; - - /* Check if there are still sectors to erase */ - if(pFlash.NbSectorsToErase != 0) - { - temp = pFlash.Sector; - /* Indicate user which sector has been erased */ - HAL_FLASH_EndOfOperationCallback(temp); - - /* Increment sector number */ - temp = ++pFlash.Sector; - FLASH_Erase_Sector(temp, pFlash.VoltageForErase); - } - else - { - /* No more sectors to Erase, user callback can be called.*/ - /* Reset Sector and stop Erase sectors procedure */ - pFlash.Sector = temp = 0xFFFFFFFFU; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(temp); - /* Sector Erase procedure is completed */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - break; - } - - case FLASH_PROC_MASSERASE : - { - /* MassErase ended. Return the selected bank : in this product we don't have Banks */ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(0); - /* MAss Erase procedure is completed */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - break; - } - - case FLASH_PROC_PROGRAM : - { - /*Program ended. Return the selected address*/ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - /* Programming procedure is completed */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - break; - } - default : - break; - } - } - - /* Check FLASH operation error flags */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) - { - switch (pFlash.ProcedureOnGoing) - { - case FLASH_PROC_SECTERASE : - { - /* return the faulty sector */ - temp = pFlash.Sector; - pFlash.Sector = 0xFFFFFFFFU; - break; - } - case FLASH_PROC_MASSERASE : - { - /* No return in case of Mass Erase */ - temp = 0; - break; - } - case FLASH_PROC_PROGRAM : - { - /*return the faulty address*/ - temp = pFlash.Address; - break; - } - default : - break; - } - /*Save the Error code*/ - FLASH_SetErrorCode(); - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(temp); - - /*Stop the procedure ongoing */ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - } - - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) - { - /* Disable End of FLASH Operation interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); - - /* Disable Error source interrupt */ - __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } - -} - -/** - * @brief FLASH end of operation interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that - * all the selected sectors have been erased) - * - Program : Address which was selected for data program - * - Mass Erase : No return value expected - * @retval None - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that - * all the selected sectors have been erased) - * - Program : Address which was selected for data program - * - Mass Erase : No return value expected - * @retval None - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->KEYR, FLASH_KEY1); - WRITE_REG(FLASH->KEYR, FLASH_KEY2); - - /* Verify Flash is unlocked */ - if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Locks the FLASH control register access - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - /* Set the LOCK Bit to lock the FLASH Registers access */ - FLASH->CR |= FLASH_CR_LOCK; - - return HAL_OK; -} - -/** - * @brief Unlock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) - { - /* Authorizes the Option Byte register programming */ - FLASH->OPTKEYR = FLASH_OPT_KEY1; - FLASH->OPTKEYR = FLASH_OPT_KEY2; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Control Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; - - return HAL_OK; -} - -/** - * @brief Launch the option byte loading. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the OPTSTRT bit in OPTCR register */ - FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; - - /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time Errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode: The returned value can be: - * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag - * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag - * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout maximum flash operationtimeout - * @retval HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - uint32_t tickstart = 0; - - /* Clear Error Code */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. - Even if the FLASH operation fails, the BUSY flag will be reset and an error - flag will be set */ - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) - { - /*Save the error code*/ - FLASH_SetErrorCode(); - return HAL_ERROR; - } - - /* Check FLASH End of Operation flag */ - if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) - { - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - /* If there is an error flag set */ - return HAL_OK; - -} - -/** - * @brief Program a double word (64-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.6V and an External Vpp is present. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; - FLASH->CR |= FLASH_CR_PG; - - /* Program first word */ - *(__IO uint32_t*)Address = (uint32_t)Data; - /* Barrier to ensure programming is performed in 2 steps, in right order - (independently of compiler optimization behavior) */ - __ISB(); - - /* Program second word */ - *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - - -/** - * @brief Program word (32-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.7V to 3.3V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_Word(uint32_t Address, uint32_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint32_t*)Address = Data; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Program a half-word (16-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 2.1V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_HALF_WORD; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint16_t*)Address = Data; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); - -} - -/** - * @brief Program byte (8-bit) at a specified address. - * @note This function must be used when the device voltage range is from - * 1.7V to 3.6V. - * - * @note If an erase and a program operations are requested simultaneously, - * the erase operation is performed before the program one. - * - * @param Address specifies the address to be programmed. - * @param Data specifies the data to be programmed. - * @retval None - */ -static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) -{ - /* Check the parameters */ - assert_param(IS_FLASH_ADDRESS(Address)); - - /* If the previous operation is completed, proceed to program the new data */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_PSIZE_BYTE; - FLASH->CR |= FLASH_CR_PG; - - *(__IO uint8_t*)Address = Data; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Set the specific FLASH error flag. - * @retval None - */ -static void FLASH_SetErrorCode(void) -{ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; - } - - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; - } - -#if defined (FLASH_OPTCR2_PCROP) - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) - { - pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; - } -#endif /* FLASH_OPTCR2_PCROP */ - - /* Clear error programming flags */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash.c + * @author MCD Application Team + * @brief FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the internal FLASH memory: + * + Program operations functions + * + Memory Control functions + * + Peripheral Errors functions + * + @verbatim + ============================================================================== + ##### FLASH peripheral features ##### + ============================================================================== + + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations + and the read and write protection mechanisms. + + [..] The Flash memory interface accelerates code execution with a system of instruction + prefetch and cache lines. + + [..] The FLASH main features are: + (+) Flash memory read operations + (+) Flash memory program/erase operations + (+) Read / write protections + (+) Prefetch on I-Code + (+) 64 cache lines of 128 bits on I-Code + (+) 8 cache lines of 128 bits on D-Code + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver provides functions and macros to configure and program the FLASH + memory of all STM32F7xx devices. + + (#) FLASH Memory IO Programming functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Program functions: byte, half word, word and double word + (++) There Two modes of programming : + (+++) Polling mode using HAL_FLASH_Program() function + (+++) Interrupt mode using HAL_FLASH_Program_IT() function + + (#) Interrupts and flags management functions : + (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() + (++) Wait for last FLASH operation according to its status + (++) Get error flag status by calling HAL_SetErrorCode() + [..] + In addition to these functions, this driver includes a set of macros allowing + to handle the following operations: + (+) Set the latency + (+) Enable/Disable the prefetch buffer + (+) Enable/Disable the Instruction cache and the Data cache + (+) Reset the Instruction cache and the Data cache + (+) Enable/Disable the FLASH interrupts + (+) Monitor the FLASH flags status + [..] + (@) For any Flash memory program operation (erase or program), the CPU clock frequency + (HCLK) must be at least 1MHz. + (@) The contents of the Flash memory are not guaranteed if a device reset occurs during + a Flash memory operation. + (@) Any attempt to read the Flash memory while it is being written or erased, causes the + bus to stall. Read operations are processed correctly once the program operation has + completed. This means that code or data fetches cannot be performed while a write/erase + operation is ongoing. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASH FLASH + * @brief FLASH HAL module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Constants + * @{ + */ +#define SECTOR_MASK ((uint32_t)0xFFFFFF07U) +#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables + * @{ + */ +/* Variable used for Erase sectors under interruption */ +FLASH_ProcessTypeDef pFlash = {.ProcedureOnGoing = FLASH_PROC_NONE, + .NbSectorsToErase = 0U, + .VoltageForErase= FLASH_VOLTAGE_RANGE_1, + .Sector = 0U, + .Address = 0U, + .Lock = HAL_UNLOCKED, + .ErrorCode = HAL_FLASH_ERROR_NONE}; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASH_Private_Functions + * @{ + */ +/* Program operations */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data); +static void FLASH_Program_Word(uint32_t Address, uint32_t Data); +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data); +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data); +static void FLASH_SetErrorCode(void); + +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASH_Exported_Functions FLASH Exported Functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @brief Programming operation functions + * +@verbatim + =============================================================================== + ##### Programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the FLASH + program operations. + +@endverbatim + * @{ + */ + +/** + * @brief Program byte, halfword, word or double word at a specified address + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + switch(TypeProgram) + { + case FLASH_TYPEPROGRAM_BYTE : + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_HALFWORD : + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_WORD : + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_DOUBLEWORD : + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + break; + } + default : + break; + } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Program byte, halfword, word or double word at a specified address with interrupt enabled. + * @param TypeProgram Indicate the way to program at a specified address. + * This parameter can be a value of @ref FLASH_Type_Program + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + + pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + pFlash.Address = Address; + + switch(TypeProgram) + { + case FLASH_TYPEPROGRAM_BYTE : + { + /*Program byte (8-bit) at a specified address.*/ + FLASH_Program_Byte(Address, (uint8_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_HALFWORD : + { + /*Program halfword (16-bit) at a specified address.*/ + FLASH_Program_HalfWord(Address, (uint16_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_WORD : + { + /*Program word (32-bit) at a specified address.*/ + FLASH_Program_Word(Address, (uint32_t) Data); + break; + } + + case FLASH_TYPEPROGRAM_DOUBLEWORD : + { + /*Program double word (64-bit) at a specified address.*/ + FLASH_Program_DoubleWord(Address, Data); + break; + } + default : + break; + } + return status; +} + +/** + * @brief This function handles FLASH interrupt request. + * @retval None + */ +void HAL_FLASH_IRQHandler(void) +{ + uint32_t temp = 0; + + /* If the program operation is completed, disable the PG Bit */ + FLASH->CR &= (~FLASH_CR_PG); + + /* If the erase operation is completed, disable the SER Bit */ + FLASH->CR &= (~FLASH_CR_SER); + FLASH->CR &= SECTOR_MASK; + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + switch (pFlash.ProcedureOnGoing) + { + case FLASH_PROC_SECTERASE : + { + /* Nb of sector to erased can be decreased */ + pFlash.NbSectorsToErase--; + + /* Check if there are still sectors to erase */ + if(pFlash.NbSectorsToErase != 0) + { + temp = pFlash.Sector; + /* Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(temp); + + /* Increment sector number */ + temp = ++pFlash.Sector; + FLASH_Erase_Sector(temp, pFlash.VoltageForErase); + } + else + { + /* No more sectors to Erase, user callback can be called.*/ + /* Reset Sector and stop Erase sectors procedure */ + pFlash.Sector = temp = 0xFFFFFFFFU; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(temp); + /* Sector Erase procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + break; + } + + case FLASH_PROC_MASSERASE : + { + /* MassErase ended. Return the selected bank : in this product we don't have Banks */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(0); + /* MAss Erase procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + break; + } + + case FLASH_PROC_PROGRAM : + { + /*Program ended. Return the selected address*/ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(pFlash.Address); + /* Programming procedure is completed */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + break; + } + default : + break; + } + } + + /* Check FLASH operation error flags */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + { + switch (pFlash.ProcedureOnGoing) + { + case FLASH_PROC_SECTERASE : + { + /* return the faulty sector */ + temp = pFlash.Sector; + pFlash.Sector = 0xFFFFFFFFU; + break; + } + case FLASH_PROC_MASSERASE : + { + /* No return in case of Mass Erase */ + temp = 0; + break; + } + case FLASH_PROC_PROGRAM : + { + /*return the faulty address*/ + temp = pFlash.Address; + break; + } + default : + break; + } + /*Save the Error code*/ + FLASH_SetErrorCode(); + + /* FLASH error interrupt user callback */ + HAL_FLASH_OperationErrorCallback(temp); + + /*Stop the procedure ongoing */ + pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + + if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + { + /* Disable End of FLASH Operation interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); + + /* Disable Error source interrupt */ + __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + } + +} + +/** + * @brief FLASH end of operation interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that + * all the selected sectors have been erased) + * - Program : Address which was selected for data program + * - Mass Erase : No return value expected + * @retval None + */ +__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_EndOfOperationCallback could be implemented in the user file + */ +} + +/** + * @brief FLASH operation error interrupt callback + * @param ReturnValue The value saved in this parameter depends on the ongoing procedure + * - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that + * all the selected sectors have been erased) + * - Program : Address which was selected for data program + * - Mass Erase : No return value expected + * @retval None + */ +__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ReturnValue); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_FLASH_OperationErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the FLASH + memory operations. + +@endverbatim + * @{ + */ + +/** + * @brief Unlock the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Unlock(void) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + /* Authorize the FLASH Registers access */ + WRITE_REG(FLASH->KEYR, FLASH_KEY1); + WRITE_REG(FLASH->KEYR, FLASH_KEY2); + + /* Verify Flash is unlocked */ + if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET) + { + status = HAL_ERROR; + } + } + + return status; +} + +/** + * @brief Locks the FLASH control register access + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH Registers access */ + FLASH->CR |= FLASH_CR_LOCK; + + return HAL_OK; +} + +/** + * @brief Unlock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) +{ + if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET) + { + /* Authorizes the Option Byte register programming */ + FLASH->OPTKEYR = FLASH_OPT_KEY1; + FLASH->OPTKEYR = FLASH_OPT_KEY2; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Lock the FLASH Option Control Registers access. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + + return HAL_OK; +} + +/** + * @brief Launch the option byte loading. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) +{ + /* Set the OPTSTRT bit in OPTCR register */ + FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT; + + /* Wait for last operation to be completed */ + return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); +} + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief Peripheral Errors functions + * +@verbatim + =============================================================================== + ##### Peripheral Errors functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time Errors of the FLASH peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the specific FLASH error flag. + * @retval FLASH_ErrorCode: The returned value can be: + * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag + * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag + * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg FLASH_ERROR_OPERATION: FLASH operation Error flag + */ +uint32_t HAL_FLASH_GetError(void) +{ + return pFlash.ErrorCode; +} + +/** + * @} + */ + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout maximum flash operationtimeout + * @retval HAL Status + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) +{ + uint32_t tickstart = 0; + + /* Clear Error Code */ + pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + return HAL_TIMEOUT; + } + } + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET) + { + /*Save the error code*/ + FLASH_SetErrorCode(); + return HAL_ERROR; + } + + /* Check FLASH End of Operation flag */ + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + } + + /* If there is an error flag set */ + return HAL_OK; + +} + +/** + * @brief Program a double word (64-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.6V and an External Vpp is present. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD; + FLASH->CR |= FLASH_CR_PG; + + /* Program first word */ + *(__IO uint32_t*)Address = (uint32_t)Data; + /* Barrier to ensure programming is performed in 2 steps, in right order + (independently of compiler optimization behavior) */ + __ISB(); + + /* Program second word */ + *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32); + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + + +/** + * @brief Program word (32-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.7V to 3.3V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Word(uint32_t Address, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint32_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Program a half-word (16-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 2.1V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_HALF_WORD; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint16_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); + +} + +/** + * @brief Program byte (8-bit) at a specified address. + * @note This function must be used when the device voltage range is from + * 1.7V to 3.6V. + * + * @note If an erase and a program operations are requested simultaneously, + * the erase operation is performed before the program one. + * + * @param Address specifies the address to be programmed. + * @param Data specifies the data to be programmed. + * @retval None + */ +static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_FLASH_ADDRESS(Address)); + + /* If the previous operation is completed, proceed to program the new data */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_PSIZE_BYTE; + FLASH->CR |= FLASH_CR_PG; + + *(__IO uint8_t*)Address = Data; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Set the specific FLASH error flag. + * @retval None + */ +static void FLASH_SetErrorCode(void) +{ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP; + } + + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS; + } + +#if defined (FLASH_OPTCR2_PCROP) + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) + { + pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + } +#endif /* FLASH_OPTCR2_PCROP */ + + /* Clear error programming flags */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS); +} + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c index b10c0d0d..ea1d699c 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_flash_ex.c @@ -1,1119 +1,1119 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the FLASH extension peripheral: - * + Extended programming operations functions - * - @verbatim - ============================================================================== - ##### Flash Extension features ##### - ============================================================================== - - [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx - devices contains the following additional features - - (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write - capability (RWW) - (+) Dual bank memory organization - (+) Dual boot mode - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32F7xx devices. It includes - (#) FLASH Memory Erase functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Erase function: Erase sector, erase all sectors - (++) There are two modes of erase : - (+++) Polling Mode using HAL_FLASHEx_Erase() - (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() - - (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : - (++) Set/Reset the write protection - (++) Set the Read protection Level - (++) Set the BOR level - (++) Program the user Option Bytes - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH HAL Extension module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Constants - * @{ - */ -#define SECTOR_MASK 0xFFFFFF07U -#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ -/* Option bytes control */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector); -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector); -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); -static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); -static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address); -static uint32_t FLASH_OB_GetUser(void); -static uint32_t FLASH_OB_GetWRP(void); -static uint8_t FLASH_OB_GetRDP(void); -static uint32_t FLASH_OB_GetBOR(void); -static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption); - -#if defined (FLASH_OPTCR_nDBANK) -static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ - uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot); -#else -static void FLASH_MassErase(uint8_t VoltageRange); -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); -#endif /* FLASH_OPTCR_nDBANK */ - -#if defined (FLASH_OPTCR2_PCROP) -static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector); -static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp); -static uint32_t FLASH_OB_GetPCROP(void); -static uint32_t FLASH_OB_GetPCROPRDP(void); -#endif /* FLASH_OPTCR2_PCROP */ - -extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions - * -@verbatim - =============================================================================== - ##### Extended programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the Extension FLASH - programming operations Operations. - -@endverbatim - * @{ - */ -/** - * @brief Perform a mass erase or erase the specified FLASH memory sectors - * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] SectorError pointer to variable that - * contains the configuration information on faulty sector in case of error - * (0xFFFFFFFF means that all the sectors have been correctly erased) - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) -{ - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t index = 0; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /*Initialization of SectorError variable*/ - *SectorError = 0xFFFFFFFFU; - - if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ -#if defined (FLASH_OPTCR_nDBANK) - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); -#else - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); -#endif /* FLASH_OPTCR_nDBANK */ - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* if the erase operation is completed, disable the MER Bit */ - FLASH->CR &= (~FLASH_MER_BIT); - } - else - { - /* Check the parameters */ - assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); - - /* Erase by sector by sector to be done*/ - for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) - { - FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - /* If the erase operation is completed, disable the SER Bit and SNB Bits */ - CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); - - if(status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty sector*/ - *SectorError = index; - break; - } - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled - * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); - - if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) - { - /*Mass erase to be done*/ - pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; -#if defined (FLASH_OPTCR_nDBANK) - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); -#else - FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); -#endif /* FLASH_OPTCR_nDBANK */ - } - else - { - /* Erase by sector to be done*/ - - /* Check the parameters */ - assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); - - pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; - pFlash.NbSectorsToErase = pEraseInit->NbSectors; - pFlash.Sector = pEraseInit->Sector; - pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; - - /*Erase 1st sector and wait for IT*/ - FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); - } - - return status; -} - -/** - * @brief Program option bytes - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /* Write protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) - { - /*Enable of Write protection on the selected Sector*/ - status = FLASH_OB_EnableWRP(pOBInit->WRPSector); - } - else - { - /*Disable of Write protection on the selected Sector*/ - status = FLASH_OB_DisableWRP(pOBInit->WRPSector); - } - } - - /* Read protection configuration */ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); - } - - /* USER configuration */ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { -#if defined (FLASH_OPTCR_nDBANK) - status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, - pOBInit->USERConfig & OB_IWDG_SW, - pOBInit->USERConfig & OB_STOP_NO_RST, - pOBInit->USERConfig & OB_STDBY_NO_RST, - pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, - pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE, - pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK, - pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE); -#else - status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, - pOBInit->USERConfig & OB_IWDG_SW, - pOBInit->USERConfig & OB_STOP_NO_RST, - pOBInit->USERConfig & OB_STDBY_NO_RST, - pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, - pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); -#endif /* FLASH_OPTCR_nDBANK */ - } - - /* BOR Level configuration */ - if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) - { - status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); - } - - /* Boot 0 Address configuration */ - if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0) - { - status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0); - } - - /* Boot 1 Address configuration */ - if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1) - { - status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1); - } - -#if defined (FLASH_OPTCR2_PCROP) - /* PCROP configuration */ - if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) - { - status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector); - } - - /* PCROP_RDP configuration */ - if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP) - { - status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp); - } -#endif /* FLASH_OPTCR2_PCROP */ - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ - OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; - - /*Get WRP*/ - pOBInit->WRPSector = FLASH_OB_GetWRP(); - - /*Get RDP Level*/ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = FLASH_OB_GetUser(); - - /*Get BOR Level*/ - pOBInit->BORLevel = FLASH_OB_GetBOR(); - - /*Get Boot Address when Boot pin = 0 */ - pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0); - - /*Get Boot Address when Boot pin = 1 */ - pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); - -#if defined (FLASH_OPTCR2_PCROP) - /*Get PCROP Sectors */ - pOBInit->PCROPSector = FLASH_OB_GetPCROP(); - - /*Get PCROP_RDP Value */ - pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP(); -#endif /* FLASH_OPTCR2_PCROP */ -} -/** - * @} - */ - -#if defined (FLASH_OPTCR_nDBANK) -/** - * @brief Full erase of FLASH memory sectors - * @param VoltageRange The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * @param Banks Banks to be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be erased - * @arg FLASH_BANK_2: Bank2 to be erased - * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased - * - * @retval HAL Status - */ -static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) -{ - /* Check the parameters */ - assert_param(IS_VOLTAGERANGE(VoltageRange)); - assert_param(IS_FLASH_BANK(Banks)); - - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - if(Banks == FLASH_BANK_BOTH) - { - /* bank1 & bank2 will be erased*/ - FLASH->CR |= FLASH_MER_BIT; - } - else if(Banks == FLASH_BANK_2) - { - /*Only bank2 will be erased*/ - FLASH->CR |= FLASH_CR_MER2; - } - else - { - /*Only bank1 will be erased*/ - FLASH->CR |= FLASH_CR_MER1; - } - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Erase the specified FLASH memory sector - * @param Sector FLASH sector to erase - * The value of this parameter depend on device used within the same series - * @param VoltageRange The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval None - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == FLASH_VOLTAGE_RANGE_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - - /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ - if(Sector > FLASH_SECTOR_11) - { - Sector += 4; - } - - /* If the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); - FLASH->CR |= FLASH_CR_STRT; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval uint32_t FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000)); -} - -/** - * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_WWDG_SW: Software WWDG selected - * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg Selects the WWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NO_RST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop Independent watchdog counter freeze in Stop mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP - * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby Independent watchdog counter freeze in standby mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY - * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY - * @param NDBank Flash Single Bank mode enabled. - * This parameter can be one of the following values: - * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) - * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) - * @param NDBoot Flash Dual boot mode disable. - * This parameter can be one of the following values: - * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot - * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot - - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ - uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) -{ - uint32_t useroptionmask = 0x00; - uint32_t useroptionvalue = 0x00; - - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WWDG_SOURCE(Wwdg)); - assert_param(IS_OB_IWDG_SOURCE(Iwdg)); - assert_param(IS_OB_STOP_SOURCE(Stop)); - assert_param(IS_OB_STDBY_SOURCE(Stdby)); - assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); - assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); - assert_param(IS_OB_NDBANK(NDBank)); - assert_param(IS_OB_NDBOOT(NDBoot)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ - FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ - FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK); - - useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank); - - /* Update User Option Byte */ - MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); - } - - return status; -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), - * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). - */ -static uint32_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U)); -} -#else - -/** - * @brief Full erase of FLASH memory sectors - * @param VoltageRange The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval HAL Status - */ -static void FLASH_MassErase(uint8_t VoltageRange) -{ - /* Check the parameters */ - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - /* if the previous operation is completed, proceed to erase all sectors */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Erase the specified FLASH memory sector - * @param Sector FLASH sector to erase - * The value of this parameter depend on device used within the same series - * @param VoltageRange The device voltage range which defines the erase parallelism. - * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) - * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, - * the operation will be done by half word (16-bit) - * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, - * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, - * the operation will be done by double word (64-bit) - * - * @retval None - */ -void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) -{ - uint32_t tmp_psize = 0; - - /* Check the parameters */ - assert_param(IS_FLASH_SECTOR(Sector)); - assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == FLASH_VOLTAGE_RANGE_1) - { - tmp_psize = FLASH_PSIZE_BYTE; - } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) - { - tmp_psize = FLASH_PSIZE_HALF_WORD; - } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) - { - tmp_psize = FLASH_PSIZE_WORD; - } - else - { - tmp_psize = FLASH_PSIZE_DOUBLE_WORD; - } - - /* If the previous operation is completed, proceed to erase the sector */ - FLASH->CR &= CR_PSIZE_MASK; - FLASH->CR |= tmp_psize; - FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); - FLASH->CR |= FLASH_CR_STRT; - - /* Data synchronous Barrier (DSB) Just after the write operation - This will force the CPU to respect the sequence of instruction (no optimization).*/ - __DSB(); -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * @retval uint32_t FLASH Write Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetWRP(void) -{ - /* Return the FLASH write protection Register value */ - return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); -} - -/** - * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg Selects the IWDG mode - * This parameter can be one of the following values: - * @arg OB_WWDG_SW: Software WWDG selected - * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg Selects the WWDG mode - * This parameter can be one of the following values: - * @arg OB_IWDG_SW: Software IWDG selected - * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop Reset event when entering STOP mode. - * This parameter can be one of the following values: - * @arg OB_STOP_NO_RST: No reset generated when entering in STOP - * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby Reset event when entering Standby mode. - * This parameter can be one of the following values: - * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY - * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop Independent watchdog counter freeze in Stop mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP - * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby Independent watchdog counter freeze in standby mode. - * This parameter can be one of the following values: - * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY - * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby) -{ - uint32_t useroptionmask = 0x00; - uint32_t useroptionvalue = 0x00; - - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WWDG_SOURCE(Wwdg)); - assert_param(IS_OB_IWDG_SOURCE(Iwdg)); - assert_param(IS_OB_STOP_SOURCE(Stop)); - assert_param(IS_OB_STDBY_SOURCE(Stdby)); - assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); - assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ - FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); - - useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); - - /* Update User Option Byte */ - MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); - } - - return status; - -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), - * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). - */ -static uint32_t FLASH_OB_GetUser(void) -{ - /* Return the User Option Byte */ - return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U)); -} -#endif /* FLASH_OPTCR_nDBANK */ - -/** - * @brief Enable the write protection of the desired bank1 or bank2 sectors - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM7 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WRPSector specifies the sector(s) to be write protected. - * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) - * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) - * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) - * @arg OB_WRP_SECTOR_All - * - * @retval HAL FLASH State - */ -static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRP_SECTOR(WRPSector)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /*Write protection enabled on sectors */ - FLASH->OPTCR &= (~WRPSector); - } - - return status; -} - -/** - * @brief Disable the write protection of the desired bank1 or bank 2 sectors - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * - * @param WRPSector specifies the sector(s) to be write protected. - * This parameter can be one of the following values: - * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) - * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) - * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) - * @arg OB_WRP_Sector_All - * - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_WRP_SECTOR(WRPSector)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - /* Write protection disabled on sectors */ - FLASH->OPTCR |= (WRPSector); - } - - return status; -} - -/** - * @brief Set the read protection level. - * @param Level specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - * - * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(Level)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; - } - - return status; -} - -/** - * @brief Set the BOR Level. - * @param Level specifies the Option Bytes BOR Reset Level. - * This parameter can be one of the following values: - * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) -{ - /* Check the parameters */ - assert_param(IS_OB_BOR_LEVEL(Level)); - - /* Set the BOR Level */ - MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level); - - return HAL_OK; - -} - -/** - * @brief Configure Boot base address. - * - * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 - * This parameter can be one of the following values: - * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 - * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 - * @param Address specifies Boot base address - * This parameter can be one of the following values: - * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) - * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) - * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) - * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) - * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) - * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) - * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_BOOT_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - if(BootOption == OPTIONBYTE_BOOTADDR_0) - { - MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address); - } - else - { - MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16)); - } - } - - return status; -} - -/** - * @brief Returns the FLASH Read Protection level. - * @retval FlagStatus FLASH ReadOut Protection Status: - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - */ -static uint8_t FLASH_OB_GetRDP(void) -{ - uint8_t readstatus = OB_RDP_LEVEL_0; - - if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0) - { - readstatus = OB_RDP_LEVEL_0; - } - else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2) - { - readstatus = OB_RDP_LEVEL_2; - } - else - { - readstatus = OB_RDP_LEVEL_1; - } - - return readstatus; -} - -/** - * @brief Returns the FLASH BOR level. - * @retval uint32_t The FLASH BOR level: - * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V - * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V - * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V - */ -static uint32_t FLASH_OB_GetBOR(void) -{ - /* Return the FLASH BOR level */ - return ((uint32_t)(FLASH->OPTCR & 0x0C)); -} - -/** - * @brief Configure Boot base address. - * - * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 - * This parameter can be one of the following values: - * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 - * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 - * - * @retval uint32_t Boot Base Address: - * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) - * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) - * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) - * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) - * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) - * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) - * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) - */ -static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption) -{ - uint32_t Address = 0; - - /* Return the Boot base Address */ - if(BootOption == OPTIONBYTE_BOOTADDR_0) - { - Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0; - } - else - { - Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16); - } - - return Address; -} - -#if defined (FLASH_OPTCR2_PCROP) -/** - * @brief Set the PCROP protection for sectors. - * @param PCROPSector specifies the sector(s) to be PCROP protected. - * This parameter can be one of the following values: - * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7 - * @arg OB_PCROP_SECTOR_ALL - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_PCROP_SECTOR(PCROPSector)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector); - } - - return status; -} - -/** - * @brief Set the PCROP_RDP value - * @param Pcrop_Rdp specifies the PCROP_RDP bit value. - * - * @retval HAL Status - */ -static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp); - } - - return status; -} - -/** - * @brief Return the FLASH PCROP Protection Option Bytes value. - * @retval uint32_t FLASH PCROP Protection Option Bytes value - */ -static uint32_t FLASH_OB_GetPCROP(void) -{ - /* Return the FLASH write protection Register value */ - return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP)); -} - -/** - * @brief Return the FLASH PCROP_RDP option byte value. - * @retval uint32_t FLASH PCROP_RDP option byte value - */ -static uint32_t FLASH_OB_GetPCROPRDP(void) -{ - /* Return the FLASH write protection Register value */ - return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP)); -} -#endif /* FLASH_OPTCR2_PCROP */ - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_flash_ex.c + * @author MCD Application Team + * @brief Extended FLASH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the FLASH extension peripheral: + * + Extended programming operations functions + * + @verbatim + ============================================================================== + ##### Flash Extension features ##### + ============================================================================== + + [..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx + devices contains the following additional features + + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write + capability (RWW) + (+) Dual bank memory organization + (+) Dual boot mode + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F7xx devices. It includes + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + HAL_FLASH_Lock() functions + (++) Erase function: Erase sector, erase all sectors + (++) There are two modes of erase : + (+++) Polling Mode using HAL_FLASHEx_Erase() + (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() + + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : + (++) Set/Reset the write protection + (++) Set the Read protection Level + (++) Set the BOR level + (++) Program the user Option Bytes + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup FLASHEx FLASHEx + * @brief FLASH HAL Extension module driver + * @{ + */ + +#ifdef HAL_FLASH_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Constants + * @{ + */ +#define SECTOR_MASK 0xFFFFFF07U +#define FLASH_TIMEOUT_VALUE 50000U/* 50 s */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Variables + * @{ + */ +extern FLASH_ProcessTypeDef pFlash; +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup FLASHEx_Private_Functions + * @{ + */ +/* Option bytes control */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector); +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector); +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level); +static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address); +static uint32_t FLASH_OB_GetUser(void); +static uint32_t FLASH_OB_GetWRP(void); +static uint8_t FLASH_OB_GetRDP(void); +static uint32_t FLASH_OB_GetBOR(void); +static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption); + +#if defined (FLASH_OPTCR_nDBANK) +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot); +#else +static void FLASH_MassErase(uint8_t VoltageRange); +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby); +#endif /* FLASH_OPTCR_nDBANK */ + +#if defined (FLASH_OPTCR2_PCROP) +static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector); +static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp); +static uint32_t FLASH_OB_GetPCROP(void); +static uint32_t FLASH_OB_GetPCROPRDP(void); +#endif /* FLASH_OPTCR2_PCROP */ + +extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions + * @{ + */ + +/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions + * @brief Extended IO operation functions + * +@verbatim + =============================================================================== + ##### Extended programming operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the Extension FLASH + programming operations Operations. + +@endverbatim + * @{ + */ +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] SectorError pointer to variable that + * contains the configuration information on faulty sector in case of error + * (0xFFFFFFFF means that all the sectors have been correctly erased) + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) +{ + HAL_StatusTypeDef status; + uint32_t index = 0; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Initialization of SectorError variable*/ + *SectorError = 0xFFFFFFFFU; + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* if the erase operation is completed, disable the MER Bit */ + FLASH->CR &= (~FLASH_MER_BIT); + } + else + { + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + /* Erase by sector by sector to be done*/ + for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) + { + FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the SER Bit and SNB Bits */ + CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); + + if(status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector*/ + *SectorError = index; + break; + } + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR); + + if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + { + /*Mass erase to be done*/ + pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; +#if defined (FLASH_OPTCR_nDBANK) + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); +#else + FLASH_MassErase((uint8_t) pEraseInit->VoltageRange); +#endif /* FLASH_OPTCR_nDBANK */ + } + else + { + /* Erase by sector to be done*/ + + /* Check the parameters */ + assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); + + pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE; + pFlash.NbSectorsToErase = pEraseInit->NbSectors; + pFlash.Sector = pEraseInit->Sector; + pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange; + + /*Erase 1st sector and wait for IT*/ + FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange); + } + + return status; +} + +/** + * @brief Program option bytes + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&pFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); + if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + { + /*Enable of Write protection on the selected Sector*/ + status = FLASH_OB_EnableWRP(pOBInit->WRPSector); + } + else + { + /*Disable of Write protection on the selected Sector*/ + status = FLASH_OB_DisableWRP(pOBInit->WRPSector); + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { +#if defined (FLASH_OPTCR_nDBANK) + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST, + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE, + pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK, + pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE); +#else + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW, + pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST, + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); +#endif /* FLASH_OPTCR_nDBANK */ + } + + /* BOR Level configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); + } + + /* Boot 0 Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_0) == OPTIONBYTE_BOOTADDR_0) + { + status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_0, pOBInit->BootAddr0); + } + + /* Boot 1 Address configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOOTADDR_1) == OPTIONBYTE_BOOTADDR_1) + { + status = FLASH_OB_BootAddressConfig(OPTIONBYTE_BOOTADDR_1, pOBInit->BootAddr1); + } + +#if defined (FLASH_OPTCR2_PCROP) + /* PCROP configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + { + status = FLASH_OB_PCROP_Config(pOBInit->PCROPSector); + } + + /* PCROP_RDP configuration */ + if((pOBInit->OptionType & OPTIONBYTE_PCROP_RDP) == OPTIONBYTE_PCROP_RDP) + { + status = FLASH_OB_PCROP_RDP_Config(pOBInit->PCROPRdp); + } +#endif /* FLASH_OPTCR2_PCROP */ + + /* Process Unlocked */ + __HAL_UNLOCK(&pFlash); + + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\ + OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1; + + /*Get WRP*/ + pOBInit->WRPSector = FLASH_OB_GetWRP(); + + /*Get RDP Level*/ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /*Get USER*/ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /*Get BOR Level*/ + pOBInit->BORLevel = FLASH_OB_GetBOR(); + + /*Get Boot Address when Boot pin = 0 */ + pOBInit->BootAddr0 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_0); + + /*Get Boot Address when Boot pin = 1 */ + pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1); + +#if defined (FLASH_OPTCR2_PCROP) + /*Get PCROP Sectors */ + pOBInit->PCROPSector = FLASH_OB_GetPCROP(); + + /*Get PCROP_RDP Value */ + pOBInit->PCROPRdp = FLASH_OB_GetPCROPRDP(); +#endif /* FLASH_OPTCR2_PCROP */ +} +/** + * @} + */ + +#if defined (FLASH_OPTCR_nDBANK) +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * @param Banks Banks to be erased + * This parameter can be one of the following values: + * @arg FLASH_BANK_1: Bank1 to be erased + * @arg FLASH_BANK_2: Bank2 to be erased + * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + assert_param(IS_FLASH_BANK(Banks)); + + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + if(Banks == FLASH_BANK_BOTH) + { + /* bank1 & bank2 will be erased*/ + FLASH->CR |= FLASH_MER_BIT; + } + else if(Banks == FLASH_BANK_2) + { + /*Only bank2 will be erased*/ + FLASH->CR |= FLASH_CR_MER2; + } + else + { + /*Only bank1 will be erased*/ + FLASH->CR |= FLASH_CR_MER1; + } + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ + if(Sector > FLASH_SECTOR_11) + { + Sector += 4; + } + + /* If the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @param NDBank Flash Single Bank mode enabled. + * This parameter can be one of the following values: + * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) + * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) + * @param NDBoot Flash Dual boot mode disable. + * This parameter can be one of the following values: + * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot + * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot + + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \ + uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + assert_param(IS_OB_NDBANK(NDBank)); + assert_param(IS_OB_NDBOOT(NDBoot)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \ + FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U)); +} +#else + +/** + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval HAL Status + */ +static void FLASH_MassErase(uint8_t VoltageRange) +{ + /* Check the parameters */ + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + /* if the previous operation is completed, proceed to erase all sectors */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= FLASH_CR_MER; + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8); + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Erase the specified FLASH memory sector + * @param Sector FLASH sector to erase + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. + * This parameter can be one of the following values: + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, + * the operation will be done by half word (16-bit) + * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, + * the operation will be done by word (32-bit) + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * the operation will be done by double word (64-bit) + * + * @retval None + */ +void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) +{ + uint32_t tmp_psize = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_SECTOR(Sector)); + assert_param(IS_VOLTAGERANGE(VoltageRange)); + + if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + { + tmp_psize = FLASH_PSIZE_BYTE; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + { + tmp_psize = FLASH_PSIZE_HALF_WORD; + } + else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + { + tmp_psize = FLASH_PSIZE_WORD; + } + else + { + tmp_psize = FLASH_PSIZE_DOUBLE_WORD; + } + + /* If the previous operation is completed, proceed to erase the sector */ + FLASH->CR &= CR_PSIZE_MASK; + FLASH->CR |= tmp_psize; + FLASH->CR &= SECTOR_MASK; + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); + FLASH->CR |= FLASH_CR_STRT; + + /* Data synchronous Barrier (DSB) Just after the write operation + This will force the CPU to respect the sequence of instruction (no optimization).*/ + __DSB(); +} + +/** + * @brief Return the FLASH Write Protection Option Bytes value. + * @retval uint32_t FLASH Write Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR & 0x00FF0000)); +} + +/** + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @param Wwdg Selects the IWDG mode + * This parameter can be one of the following values: + * @arg OB_WWDG_SW: Software WWDG selected + * @arg OB_WWDG_HW: Hardware WWDG selected + * @param Iwdg Selects the WWDG mode + * This parameter can be one of the following values: + * @arg OB_IWDG_SW: Software IWDG selected + * @arg OB_IWDG_HW: Hardware IWDG selected + * @param Stop Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OB_STOP_NO_RST: No reset generated when entering in STOP + * @arg OB_STOP_RST: Reset generated when entering in STOP + * @param Stdby Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY + * @arg OB_STDBY_RST: Reset generated when entering in STANDBY + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP + * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. + * This parameter can be one of the following values: + * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY + * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby) +{ + uint32_t useroptionmask = 0x00; + uint32_t useroptionvalue = 0x00; + + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WWDG_SOURCE(Wwdg)); + assert_param(IS_OB_IWDG_SOURCE(Iwdg)); + assert_param(IS_OB_STOP_SOURCE(Stop)); + assert_param(IS_OB_STDBY_SOURCE(Stdby)); + assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop)); + assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \ + FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY); + + useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby); + + /* Update User Option Byte */ + MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue); + } + + return status; + +} + +/** + * @brief Return the FLASH User Option Byte value. + * @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6), + * nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31). + */ +static uint32_t FLASH_OB_GetUser(void) +{ + /* Return the User Option Byte */ + return ((uint32_t)(FLASH->OPTCR & 0xC00000F0U)); +} +#endif /* FLASH_OPTCR_nDBANK */ + +/** + * @brief Enable the write protection of the desired bank1 or bank2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM7 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) + * @arg OB_WRP_SECTOR_All + * + * @retval HAL FLASH State + */ +static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /*Write protection enabled on sectors */ + FLASH->OPTCR &= (~WRPSector); + } + + return status; +} + +/** + * @brief Disable the write protection of the desired bank1 or bank 2 sectors + * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * + * @param WRPSector specifies the sector(s) to be write protected. + * This parameter can be one of the following values: + * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) + * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) + * or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices) + * @arg OB_WRP_Sector_All + * + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_WRP_SECTOR(WRPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Write protection disabled on sectors */ + FLASH->OPTCR |= (WRPSector); + } + + return status; +} + +/** + * @brief Set the read protection level. + * @param Level specifies the read protection level. + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + * + * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_RDP_LEVEL(Level)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; + } + + return status; +} + +/** + * @brief Set the BOR Level. + * @param Level specifies the Option Bytes BOR Reset Level. + * This parameter can be one of the following values: + * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) +{ + /* Check the parameters */ + assert_param(IS_OB_BOR_LEVEL(Level)); + + /* Set the BOR Level */ + MODIFY_REG(FLASH->OPTCR, FLASH_OPTCR_BOR_LEV, Level); + + return HAL_OK; + +} + +/** + * @brief Configure Boot base address. + * + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 + * This parameter can be one of the following values: + * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 + * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 + * @param Address specifies Boot base address + * This parameter can be one of the following values: + * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) + * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) + * @arg OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) + * @arg OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) + * @arg OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) + * @arg OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) + * @arg OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_BOOT_ADDRESS(Address)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + if(BootOption == OPTIONBYTE_BOOTADDR_0) + { + MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD0, Address); + } + else + { + MODIFY_REG(FLASH->OPTCR1, FLASH_OPTCR1_BOOT_ADD1, (Address << 16)); + } + } + + return status; +} + +/** + * @brief Returns the FLASH Read Protection level. + * @retval FlagStatus FLASH ReadOut Protection Status: + * This parameter can be one of the following values: + * @arg OB_RDP_LEVEL_0: No protection + * @arg OB_RDP_LEVEL_1: Read protection of the memory + * @arg OB_RDP_LEVEL_2: Full chip protection + */ +static uint8_t FLASH_OB_GetRDP(void) +{ + uint8_t readstatus = OB_RDP_LEVEL_0; + + if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_0) + { + readstatus = OB_RDP_LEVEL_0; + } + else if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS)) == OB_RDP_LEVEL_2) + { + readstatus = OB_RDP_LEVEL_2; + } + else + { + readstatus = OB_RDP_LEVEL_1; + } + + return readstatus; +} + +/** + * @brief Returns the FLASH BOR level. + * @retval uint32_t The FLASH BOR level: + * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V + * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V + * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + */ +static uint32_t FLASH_OB_GetBOR(void) +{ + /* Return the FLASH BOR level */ + return ((uint32_t)(FLASH->OPTCR & 0x0C)); +} + +/** + * @brief Configure Boot base address. + * + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 + * This parameter can be one of the following values: + * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 + * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 + * + * @retval uint32_t Boot Base Address: + * - OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) + * - OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) + * - OB_BOOTADDR_ITCM_FLASH : Boot from Flash on ITCM interface (0x00200000) + * - OB_BOOTADDR_AXIM_FLASH : Boot from Flash on AXIM interface (0x08000000) + * - OB_BOOTADDR_DTCM_RAM : Boot from DTCM RAM (0x20000000) + * - OB_BOOTADDR_SRAM1 : Boot from SRAM1 (0x20010000) + * - OB_BOOTADDR_SRAM2 : Boot from SRAM2 (0x2004C000) + */ +static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption) +{ + uint32_t Address = 0; + + /* Return the Boot base Address */ + if(BootOption == OPTIONBYTE_BOOTADDR_0) + { + Address = FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD0; + } + else + { + Address = ((FLASH->OPTCR1 & FLASH_OPTCR1_BOOT_ADD1) >> 16); + } + + return Address; +} + +#if defined (FLASH_OPTCR2_PCROP) +/** + * @brief Set the PCROP protection for sectors. + * @param PCROPSector specifies the sector(s) to be PCROP protected. + * This parameter can be one of the following values: + * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7 + * @arg OB_PCROP_SECTOR_ALL + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_PCROP_Config(uint32_t PCROPSector) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_SECTOR(PCROPSector)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP, PCROPSector); + } + + return status; +} + +/** + * @brief Set the PCROP_RDP value + * @param Pcrop_Rdp specifies the PCROP_RDP bit value. + * + * @retval HAL Status + */ +static HAL_StatusTypeDef FLASH_OB_PCROP_RDP_Config(uint32_t Pcrop_Rdp) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_OB_PCROP_RDP_VALUE(Pcrop_Rdp)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + MODIFY_REG(FLASH->OPTCR2, FLASH_OPTCR2_PCROP_RDP, Pcrop_Rdp); + } + + return status; +} + +/** + * @brief Return the FLASH PCROP Protection Option Bytes value. + * @retval uint32_t FLASH PCROP Protection Option Bytes value + */ +static uint32_t FLASH_OB_GetPCROP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP)); +} + +/** + * @brief Return the FLASH PCROP_RDP option byte value. + * @retval uint32_t FLASH PCROP_RDP option byte value + */ +static uint32_t FLASH_OB_GetPCROPRDP(void) +{ + /* Return the FLASH write protection Register value */ + return ((uint32_t)(FLASH->OPTCR2 & FLASH_OPTCR2_PCROP_RDP)); +} +#endif /* FLASH_OPTCR2_PCROP */ + +/** + * @} + */ + +#endif /* HAL_FLASH_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c index 93738b9f..93f595f8 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_gpio.c @@ -1,528 +1,528 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_gpio.c - * @author MCD Application Team - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each - port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software - in several modes: - (+) Input mode - (+) Analog mode - (+) Output mode - (+) Alternate function mode - (+) External interrupt/event lines - - [..] - During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - [..] - All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - [..] - In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - [..] - All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - [..] - The external interrupt/event controller consists of up to 23 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure. - (++) In alternate mode is selection, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup GPIO_Private_Constants GPIO Private Constants - * @{ - */ - -#define GPIO_NUMBER ((uint32_t)16U) -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to initialize and de-initialize the GPIOs - to be ready for use. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) -{ - uint32_t position = 0x00; - uint32_t ioposition = 0x00; - uint32_t iocurrent = 0x00; - uint32_t temp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - - /* Configure the port pins */ - for (position = 0; position < GPIO_NUMBER; position++) - { - /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; - /* Get the current IO position */ - iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - - if (iocurrent == ioposition) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Output or Alternate function mode selection */ - if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); - /* Configure the IO Speed */ - temp = GPIOx->OSPEEDR; - temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - temp |= (GPIO_Init->Speed << (position * 2)); - GPIOx->OSPEEDR = temp; - - /* Configure the IO Output Type */ - temp = GPIOx->OTYPER; - temp &= ~(GPIO_OTYPER_OT_0 << position) ; - temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - GPIOx->OTYPER = temp; - } - - if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - { - /* Check the Pull parameter */ - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - - /* Activate the Pull-up or Pull down resistor for the current IO */ - temp = GPIOx->PUPDR; - temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - temp |= ((GPIO_Init->Pull) << (position * 2)); - GPIOx->PUPDR = temp; - } - - /* In case of Alternate function mode selection */ - if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - { - /* Check the Alternate function parameter */ - assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - temp = GPIOx->AFR[position >> 3]; - temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); - GPIOx->AFR[position >> 3] = temp; - } - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - temp = GPIOx->MODER; - temp &= ~(GPIO_MODER_MODER0 << (position * 2)); - temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); - GPIOx->MODER = temp; - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) - { - /* Enable SYSCFG Clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); - temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); - SYSCFG->EXTICR[position >> 2] = temp; - - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; - temp &= ~((uint32_t)iocurrent); - if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) - { - temp |= iocurrent; - } - EXTI->RTSR = temp; - - temp = EXTI->FTSR; - temp &= ~((uint32_t)iocurrent); - if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) - { - temp |= iocurrent; - } - EXTI->FTSR = temp; - - temp = EXTI->EMR; - temp &= ~((uint32_t)iocurrent); - if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) - { - temp |= iocurrent; - } - EXTI->EMR = temp; - - /* Clear EXTI line configuration */ - temp = EXTI->IMR; - temp &= ~((uint32_t)iocurrent); - if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) - { - temp |= iocurrent; - } - EXTI->IMR = temp; - } - } - } -} - -/** - * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t position; - uint32_t ioposition = 0x00; - uint32_t iocurrent = 0x00; - uint32_t tmp = 0x00; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Configure the port pins */ - for (position = 0; position < GPIO_NUMBER; position++) - { - /* Get the IO position */ - ioposition = ((uint32_t)0x01) << position; - /* Get the current IO position */ - iocurrent = (GPIO_Pin) & ioposition; - - if (iocurrent == ioposition) - { - /*------------------------- EXTI Mode Configuration --------------------*/ - tmp = SYSCFG->EXTICR[position >> 2]; - tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); - if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) - { - /* Clear EXTI line configuration */ - EXTI->IMR &= ~((uint32_t)iocurrent); - EXTI->EMR &= ~((uint32_t)iocurrent); - - /* Clear Rising Falling edge configuration */ - EXTI->FTSR &= ~((uint32_t)iocurrent); - EXTI->RTSR &= ~((uint32_t)iocurrent); - - /* Configure the External Interrupt or event for the current IO */ - tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); - SYSCFG->EXTICR[position >> 2] &= ~tmp; - } - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO Direction in Input Floating Mode */ - GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); - - /* Configure the default Alternate Function in current IO */ - GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; - - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); - - /* Configure the default value IO Output Type */ - GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; - - /* Configure the default value for IO Speed */ - GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); - } - } -} - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief GPIO Read and Write - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Reads the specified input port pin. - * @param GPIOx where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin specifies the port bit to read. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - return bitstatus; -} - -/** - * @brief Sets or clears the selected data port bit. - * - * @note This function uses GPIOx_BSRR register to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * - * @param GPIOx where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin specifies the port bit to be written. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). - * @param PinState specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if (PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = GPIO_Pin; - } - else - { - GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; - } -} - -/** - * @brief Toggles the specified GPIO pins. - * @param GPIOx Where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin Specifies the pins to be toggled. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t odr; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* get current Output Data Register value */ - odr = GPIOx->ODR; - - /* Set selected pins that were at low level, and reset ones that were high */ - GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); -} - -/** - * @brief Locks GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family - * @param GPIO_Pin specifies the port bit to be locked. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Apply lock key write sequence */ - tmp |= GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - GPIOx->LCKR = GPIO_Pin; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - GPIOx->LCKR = tmp; - /* Read LCKR register. This read is mandatory to complete key lock sequence */ - tmp = GPIOx->LCKR; - - /* Read again in order to confirm lock is active */ - if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) - { - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin Specifies the pins connected EXTI line - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) - { - __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); - HAL_GPIO_EXTI_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line detection callbacks. - * @param GPIO_Pin Specifies the pins connected EXTI line - * @retval None - */ -__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_gpio.c + * @author MCD Application Team + * @brief GPIO HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the General Purpose Input/Output (GPIO) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### GPIO Peripheral features ##### + ============================================================================== + [..] + Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each + port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software + in several modes: + (+) Input mode + (+) Analog mode + (+) Output mode + (+) Alternate function mode + (+) External interrupt/event lines + + [..] + During and just after reset, the alternate functions and external interrupt + lines are not active and the I/O ports are configured in input floating mode. + + [..] + All GPIO pins have weak internal pull-up and pull-down resistors, which can be + activated or not. + + [..] + In Output or Alternate mode, each IO can be configured on open-drain or push-pull + type and the IO speed can be selected depending on the VDD value. + + [..] + All ports have external interrupt/event capability. To use external interrupt + lines, the port must be configured in input mode. All available GPIO pins are + connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. + + [..] + The external interrupt/event controller consists of up to 23 edge detectors + (16 lines are connected to GPIO) for generating event/interrupt requests (each + input line can be independently configured to select the type (interrupt or event) + and the corresponding trigger event (rising or falling or both). Each line can + also be masked independently. + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). + (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure + (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef + structure. + (++) In case of Output or alternate function mode selection: the speed is + configured through "Speed" member from GPIO_InitTypeDef structure. + (++) In alternate mode is selection, the alternate function connected to the IO + is configured through "Alternate" member from GPIO_InitTypeDef structure. + (++) Analog mode is required when a pin is to be used as ADC channel + or DAC output. + (++) In case of external interrupt/event selection the "Mode" member from + GPIO_InitTypeDef structure select the type (interrupt or event) and + the corresponding trigger event (rising or falling or both). + + (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority + mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using + HAL_NVIC_EnableIRQ(). + + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). + + (#) To set/reset the level of a pin configured in output mode use + HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + + + (#) During and just after reset, the alternate functions are not + active and the GPIO pins are configured in input floating mode (except JTAG + pins). + + (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose + (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has + priority over the GPIO function. + + (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as + general purpose PH0 and PH1, respectively, when the HSE oscillator is off. + The HSE has priority over the GPIO function. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup GPIO GPIO + * @brief GPIO HAL module driver + * @{ + */ + +#ifdef HAL_GPIO_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup GPIO_Private_Constants GPIO Private Constants + * @{ + */ + +#define GPIO_NUMBER ((uint32_t)16U) +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to initialize and de-initialize the GPIOs + to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + uint32_t position = 0x00; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t temp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + + /* Configure the port pins */ + for (position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; + + if (iocurrent == ioposition) + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + temp |= (GPIO_Init->Speed << (position * 2)); + GPIOx->OSPEEDR = temp; + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + temp &= ~(GPIO_OTYPER_OT_0 << position) ; + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + GPIOx->OTYPER = temp; + } + + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + { + /* Check the Pull parameter */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Activate the Pull-up or Pull down resistor for the current IO */ + temp = GPIOx->PUPDR; + temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + temp |= ((GPIO_Init->Pull) << (position * 2)); + GPIOx->PUPDR = temp; + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + { + /* Check the Alternate function parameter */ + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3]; + temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); + GPIOx->AFR[position >> 3] = temp; + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + temp &= ~(GPIO_MODER_MODER0 << (position * 2)); + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); + GPIOx->MODER = temp; + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + { + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + temp = SYSCFG->EXTICR[position >> 2]; + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); + SYSCFG->EXTICR[position >> 2] = temp; + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; + temp &= ~((uint32_t)iocurrent); + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->RTSR = temp; + + temp = EXTI->FTSR; + temp &= ~((uint32_t)iocurrent); + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + { + temp |= iocurrent; + } + EXTI->FTSR = temp; + + temp = EXTI->EMR; + temp &= ~((uint32_t)iocurrent); + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->EMR = temp; + + /* Clear EXTI line configuration */ + temp = EXTI->IMR; + temp &= ~((uint32_t)iocurrent); + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + { + temp |= iocurrent; + } + EXTI->IMR = temp; + } + } + } +} + +/** + * @brief De-initializes the GPIOx peripheral registers to their default reset values. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + uint32_t position; + uint32_t ioposition = 0x00; + uint32_t iocurrent = 0x00; + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Configure the port pins */ + for (position = 0; position < GPIO_NUMBER; position++) + { + /* Get the IO position */ + ioposition = ((uint32_t)0x01) << position; + /* Get the current IO position */ + iocurrent = (GPIO_Pin) & ioposition; + + if (iocurrent == ioposition) + { + /*------------------------- EXTI Mode Configuration --------------------*/ + tmp = SYSCFG->EXTICR[position >> 2]; + tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03))); + if (tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)))) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~((uint32_t)iocurrent); + EXTI->EMR &= ~((uint32_t)iocurrent); + + /* Clear Rising Falling edge configuration */ + EXTI->FTSR &= ~((uint32_t)iocurrent); + EXTI->RTSR &= ~((uint32_t)iocurrent); + + /* Configure the External Interrupt or event for the current IO */ + tmp = ((uint32_t)0x0F) << (4 * (position & 0x03)); + SYSCFG->EXTICR[position >> 2] &= ~tmp; + } + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO Direction in Input Floating Mode */ + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2)); + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2)); + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2)); + } + } +} + +/** + * @} + */ + +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @brief GPIO Read and Write + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to read. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval The input port pin value. + */ +GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIO_PinState bitstatus; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) + { + bitstatus = GPIO_PIN_SET; + } + else + { + bitstatus = GPIO_PIN_RESET; + } + return bitstatus; +} + +/** + * @brief Sets or clears the selected data port bit. + * + * @note This function uses GPIOx_BSRR register to allow atomic read/modify + * accesses. In this way, there is no risk of an IRQ occurring between + * the read and the modify access. + * + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @param PinState specifies the value to be written to the selected bit. + * This parameter can be one of the GPIO_PinState enum values: + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16; + } +} + +/** + * @brief Toggles the specified GPIO pins. + * @param GPIOx Where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin Specifies the pins to be toggled. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t odr; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next reset. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family + * @param GPIO_Pin specifies the port bit to be locked. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = GPIO_LCKR_LCKK; + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Apply lock key write sequence */ + tmp |= GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ + GPIOx->LCKR = tmp; + /* Read LCKR register. This read is mandatory to complete key lock sequence */ + tmp = GPIOx->LCKR; + + /* Read again in order to confirm lock is active */ + if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET) + { + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief This function handles EXTI interrupt request. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) +{ + /* EXTI line interrupt detected */ + if (__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) + { + __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin); + HAL_GPIO_EXTI_Callback(GPIO_Pin); + } +} + +/** + * @brief EXTI line detection callbacks. + * @param GPIO_Pin Specifies the pins connected EXTI line + * @retval None + */ +__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(GPIO_Pin); + + /* NOTE: This function Should not be modified, when the callback is needed, + the HAL_GPIO_EXTI_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + + +/** + * @} + */ + +#endif /* HAL_GPIO_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c deleted file mode 100644 index 8d6682c4..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash.c +++ /dev/null @@ -1,3540 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hash.c - * @author MCD Application Team - * @brief HASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the HASH peripheral: - * + Initialization and de-initialization methods - * + HASH or HMAC processing in polling mode - * + HASH or HMAC processing in interrupt mode - * + HASH or HMAC processing in DMA mode - * + Peripheral State methods - * + HASH or HMAC processing suspension/resumption - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The HASH HAL driver can be used as follows: - - (#)Initialize the HASH low level resources by implementing the HAL_HASH_MspInit(): - (##) Enable the HASH interface clock using __HASH_CLK_ENABLE() - (##) When resorting to interrupt-based APIs (e.g. HAL_HASH_xxx_Start_IT()) - (+++) Configure the HASH interrupt priority using HAL_NVIC_SetPriority() - (+++) Enable the HASH IRQ handler using HAL_NVIC_EnableIRQ() - (+++) In HASH IRQ handler, call HAL_HASH_IRQHandler() API - (##) When resorting to DMA-based APIs (e.g. HAL_HASH_xxx_Start_DMA()) - (+++) Enable the DMAx interface clock using - __DMAx_CLK_ENABLE() - (+++) Configure and enable one DMA stream to manage data transfer from - memory to peripheral (input stream). Managing data transfer from - peripheral to memory can be performed only using CPU. - (+++) Associate the initialized DMA handle to the HASH DMA handle - using __HAL_LINKDMA() - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA stream: use - HAL_NVIC_SetPriority() and - HAL_NVIC_EnableIRQ() - - (#)Initialize the HASH HAL using HAL_HASH_Init(). This function: - (##) resorts to HAL_HASH_MspInit() for low-level initialization, - (##) configures the data type: 1-bit, 8-bit, 16-bit or 32-bit. - - (#)Three processing schemes are available: - (##) Polling mode: processing APIs are blocking functions - i.e. they process the data and wait till the digest computation is finished, - e.g. HAL_HASH_xxx_Start() for HASH or HAL_HMAC_xxx_Start() for HMAC - (##) Interrupt mode: processing APIs are not blocking functions - i.e. they process the data under interrupt, - e.g. HAL_HASH_xxx_Start_IT() for HASH or HAL_HMAC_xxx_Start_IT() for HMAC - (##) DMA mode: processing APIs are not blocking functions and the CPU is - not used for data transfer i.e. the data transfer is ensured by DMA, - e.g. HAL_HASH_xxx_Start_DMA() for HASH or HAL_HMAC_xxx_Start_DMA() - for HMAC. Note that in DMA mode, a call to HAL_HASH_xxx_Finish() - is then required to retrieve the digest. - - (#)When the processing function is called after HAL_HASH_Init(), the HASH peripheral is - initialized and processes the buffer fed in input. When the input data have all been - fed to the Peripheral, the digest computation can start. - - (#)Multi-buffer processing is possible in polling, interrupt and DMA modes. - (##) In polling mode, only multi-buffer HASH processing is possible. - API HAL_HASH_xxx_Accumulate() must be called for each input buffer, except for the last one. - User must resort to HAL_HASH_xxx_Accumulate_End() to enter the last one and retrieve as - well the computed digest. - - (##) In interrupt mode, API HAL_HASH_xxx_Accumulate_IT() must be called for each input buffer, - except for the last one. - User must resort to HAL_HASH_xxx_Accumulate_End_IT() to enter the last one and retrieve as - well the computed digest. - - (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - (+++) HASH processing: once initialization is done, MDMAT bit must be set - through __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the Peripheral through HAL_HASH_xxx_Start_DMA() API. - Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() - macro then wrap-up the HASH processing in feeding the last input buffer through the - same API HAL_HASH_xxx_Start_DMA(). The digest can then be retrieved with a call to - API HAL_HASH_xxx_Finish(). - (+++) HMAC processing (requires to resort to extended functions): - after initialization, the key and the first input buffer are entered - in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and - starts step 2. - The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this - point, the HMAC processing is still carrying out step 2. - Then, step 2 for the last input buffer and step 3 are carried out by a single call - to HAL_HMACEx_xxx_Step2_3_DMA(). - - The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish(). - - - (#)Context swapping. - (##) Two APIs are available to suspend HASH or HMAC processing: - (+++) HAL_HASH_SwFeed_ProcessSuspend() when data are entered by software (polling or IT mode), - (+++) HAL_HASH_DMAFeed_ProcessSuspend() when data are entered by DMA. - - (##) When HASH or HMAC processing is suspended, HAL_HASH_ContextSaving() allows - to save in memory the Peripheral context. This context can be restored afterwards - to resume the HASH processing thanks to HAL_HASH_ContextRestoring(). - - (##) Once the HASH Peripheral has been restored to the same configuration as that at suspension - time, processing can be restarted with the same API call (same API, same handle, - same parameters) as done before the suspension. Relevant parameters to restart at - the proper location are internally saved in the HASH handle. - - (#)Call HAL_HASH_DeInit() to deinitialize the HASH peripheral. - - *** Remarks on message length *** - =================================== - [..] - (#) HAL in interruption mode (interruptions driven) - - (##)Due to HASH peripheral hardware design, the peripheral interruption is triggered every 64 bytes. - This is why, for driver implementation simplicity s sake, user is requested to enter a message the - length of which is a multiple of 4 bytes. - - (##) When the message length (in bytes) is not a multiple of words, a specific field exists in HASH_STR - to specify which bits to discard at the end of the complete message to process only the message bits - and not extra bits. - - (##) If user needs to perform a hash computation of a large input buffer that is spread around various places - in memory and where each piece of this input buffer is not necessarily a multiple of 4 bytes in size, it becomes - necessary to use a temporary buffer to format the data accordingly before feeding them to the Peripheral. - It is advised to the user to - (+++) achieve the first formatting operation by software then enter the data - (+++) while the Peripheral is processing the first input set, carry out the second formatting - operation by software, to be ready when DINIS occurs. - (+++) repeat step 2 until the whole message is processed. - - [..] - (#) HAL in DMA mode - - (##) Again, due to hardware design, the DMA transfer to feed the data can only be done on a word-basis. - The same field described above in HASH_STR is used to specify which bits to discard at the end of the - DMA transfer to process only the message bits and not extra bits. Due to hardware implementation, - this is possible only at the end of the complete message. When several DMA transfers are needed to - enter the message, this is not applicable at the end of the intermediary transfers. - - (##) Similarly to the interruption-driven mode, it is suggested to the user to format the consecutive - chunks of data by software while the DMA transfer and processing is on-going for the first parts of - the message. Due to the 32-bit alignment required for the DMA transfer, it is underlined that the - software formatting operation is more complex than in the IT mode. - - *** Callback registration *** - =================================== - [..] - (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use function HAL_HASH_RegisterCallback() to register a user callback. - - (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks: - (+) InCpltCallback : callback for input completion. - (+) DgstCpltCallback : callback for digest computation completion. - (+) ErrorCallback : callback for error. - (+) MspInitCallback : HASH MspInit. - (+) MspDeInitCallback : HASH MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. - HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) InCpltCallback : callback for input completion. - (+) DgstCpltCallback : callback for digest computation completion. - (+) ErrorCallback : callback for error. - (+) MspInitCallback : HASH MspInit. - (+) MspDeInitCallback : HASH MspDeInit. - - (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback() - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_HASH_Init - and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit - or HAL_HASH_Init function. - - When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (HASH) - -/** @defgroup HASH HASH - * @brief HASH HAL module driver. - * @{ - */ - -#ifdef HAL_HASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup HASH_Private_Constants HASH Private Constants - * @{ - */ - -/** @defgroup HASH_Digest_Calculation_Status HASH Digest Calculation Status - * @{ - */ -#define HASH_DIGEST_CALCULATION_NOT_STARTED ((uint32_t)0x00000000U) /*!< DCAL not set after input data written in DIN register */ -#define HASH_DIGEST_CALCULATION_STARTED ((uint32_t)0x00000001U) /*!< DCAL set after input data written in DIN register */ -/** - * @} - */ - -/** @defgroup HASH_Number_Of_CSR_Registers HASH Number of Context Swap Registers - * @{ - */ -#define HASH_NUMBER_OF_CSR_REGISTERS 54U /*!< Number of Context Swap Registers */ -/** - * @} - */ - -/** @defgroup HASH_TimeOut_Value HASH TimeOut Value - * @{ - */ -#define HASH_TIMEOUTVALUE 1000U /*!< Time-out value */ -/** - * @} - */ - -/** @defgroup HASH_DMA_Suspension_Words_Limit HASH DMA suspension words limit - * @{ - */ -#define HASH_DMA_SUSPENSION_WORDS_LIMIT 20U /*!< Number of words below which DMA suspension is aborted */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup HASH_Private_Functions HASH Private Functions - * @{ - */ -static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); -static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); -static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, - uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); -static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); -static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions HASH Exported Functions - * @{ - */ - -/** @defgroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization, configuration and call-back functions. - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the HASH according to the specified parameters - in the HASH_InitTypeDef and create the associated handle - (+) DeInitialize the HASH peripheral - (+) Initialize the HASH MCU Specific Package (MSP) - (+) DeInitialize the HASH MSP - - [..] This section provides as well call back functions definitions for user - code to manage: - (+) Input data transfer to Peripheral completion - (+) Calculated digest retrieval completion - (+) Error management - - - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the HASH according to the specified parameters in the - HASH_HandleTypeDef and create the associated handle. - * @note Only MDMAT and DATATYPE bits of HASH Peripheral are set by HAL_HASH_Init(), - * other configuration bits are set by HASH or HMAC processing APIs. - * @note MDMAT bit is systematically reset by HAL_HASH_Init(). To set it for - * multi-buffer HASH processing, user needs to resort to - * __HAL_HASH_SET_MDMAT() macro. For HMAC multi-buffer processing, the - * relevant APIs manage themselves the MDMAT bit. - * @param hhash HASH handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) -{ - /* Check the hash handle allocation */ - if (hhash == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_HASH_DATATYPE(hhash->Init.DataType)); - -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - if (hhash->State == HAL_HASH_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hhash->Lock = HAL_UNLOCKED; - - /* Reset Callback pointers in HAL_HASH_STATE_RESET only */ - hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ - hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation - completion callback */ - hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ - if (hhash->MspInitCallback == NULL) - { - hhash->MspInitCallback = HAL_HASH_MspInit; - } - - /* Init the low level hardware */ - hhash->MspInitCallback(hhash); - } -#else - if (hhash->State == HAL_HASH_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hhash->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_HASH_MspInit(hhash); - } -#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Reset HashInCount, HashITCounter, HashBuffSize and NbWordsAlreadyPushed */ - hhash->HashInCount = 0; - hhash->HashBuffSize = 0; - hhash->HashITCounter = 0; - hhash->NbWordsAlreadyPushed = 0; - /* Reset digest calculation bridle (MDMAT bit control) */ - hhash->DigestCalculationDisable = RESET; - /* Set phase to READY */ - hhash->Phase = HAL_HASH_PHASE_READY; - /* Reset suspension request flag */ - hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; - - /* Set the data type bit */ - MODIFY_REG(HASH->CR, HASH_CR_DATATYPE, hhash->Init.DataType); - /* Reset MDMAT bit */ - __HAL_HASH_RESET_MDMAT(); - /* Reset HASH handle status */ - hhash->Status = HAL_OK; - - /* Set the HASH state to Ready */ - hhash->State = HAL_HASH_STATE_READY; - - /* Initialise the error code */ - hhash->ErrorCode = HAL_HASH_ERROR_NONE; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitialize the HASH peripheral. - * @param hhash HASH handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash) -{ - /* Check the HASH handle allocation */ - if (hhash == NULL) - { - return HAL_ERROR; - } - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Set the default HASH phase */ - hhash->Phase = HAL_HASH_PHASE_READY; - - /* Reset HashInCount, HashITCounter and HashBuffSize */ - hhash->HashInCount = 0; - hhash->HashBuffSize = 0; - hhash->HashITCounter = 0; - /* Reset digest calculation bridle (MDMAT bit control) */ - hhash->DigestCalculationDisable = RESET; - -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - if (hhash->MspDeInitCallback == NULL) - { - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; - } - - /* DeInit the low level hardware */ - hhash->MspDeInitCallback(hhash); -#else - /* DeInit the low level hardware: CLOCK, NVIC */ - HAL_HASH_MspDeInit(hhash); -#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */ - - - /* Reset HASH handle status */ - hhash->Status = HAL_OK; - - /* Set the HASH state to Ready */ - hhash->State = HAL_HASH_STATE_RESET; - - /* Initialise the error code */ - hhash->ErrorCode = HAL_HASH_ERROR_NONE; - - /* Reset multi buffers accumulation flag */ - hhash->Accumulation = 0U; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the HASH MSP. - * @param hhash HASH handle. - * @retval None - */ -__weak void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE : This function should not be modified; when the callback is needed, - HAL_HASH_MspInit() can be implemented in the user file. - */ -} - -/** - * @brief DeInitialize the HASH MSP. - * @param hhash HASH handle. - * @retval None - */ -__weak void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE : This function should not be modified; when the callback is needed, - HAL_HASH_MspDeInit() can be implemented in the user file. - */ -} - -/** - * @brief Input data transfer complete call back. - * @note HAL_HASH_InCpltCallback() is called when the complete input message - * has been fed to the Peripheral. This API is invoked only when input data are - * entered under interruption or through DMA. - * @note In case of HASH or HMAC multi-buffer DMA feeding case (MDMAT bit set), - * HAL_HASH_InCpltCallback() is called at the end of each buffer feeding - * to the Peripheral. - * @param hhash HASH handle. - * @retval None - */ -__weak void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE : This function should not be modified; when the callback is needed, - HAL_HASH_InCpltCallback() can be implemented in the user file. - */ -} - -/** - * @brief Digest computation complete call back. - * @note HAL_HASH_DgstCpltCallback() is used under interruption, is not - * relevant with DMA. - * @param hhash HASH handle. - * @retval None - */ -__weak void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE : This function should not be modified; when the callback is needed, - HAL_HASH_DgstCpltCallback() can be implemented in the user file. - */ -} - -/** - * @brief Error callback. - * @note Code user can resort to hhash->Status (HAL_ERROR, HAL_TIMEOUT,...) - * to retrieve the error type. - * @param hhash HASH handle. - * @retval None - */ -__weak void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* NOTE : This function should not be modified; when the callback is needed, - HAL_HASH_ErrorCallback() can be implemented in the user file. - */ -} - -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User HASH Callback - * To be used instead of the weak (surcharged) predefined callback - * @param hhash HASH handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID - * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID - * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID - * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID - * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, - pHASH_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hhash); - - if (HAL_HASH_STATE_READY == hhash->State) - { - switch (CallbackID) - { - case HAL_HASH_INPUTCPLT_CB_ID : - hhash->InCpltCallback = pCallback; - break; - - case HAL_HASH_DGSTCPLT_CB_ID : - hhash->DgstCpltCallback = pCallback; - break; - - case HAL_HASH_ERROR_CB_ID : - hhash->ErrorCallback = pCallback; - break; - - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = pCallback; - break; - - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_HASH_STATE_RESET == hhash->State) - { - switch (CallbackID) - { - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = pCallback; - break; - - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hhash); - return status; -} - -/** - * @brief Unregister a HASH Callback - * HASH Callback is redirected to the weak (surcharged) predefined callback - * @param hhash HASH handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_HASH_INPUTCPLT_CB_ID HASH input completion Callback ID - * @arg @ref HAL_HASH_DGSTCPLT_CB_ID HASH digest computation completion Callback ID - * @arg @ref HAL_HASH_ERROR_CB_ID HASH error Callback ID - * @arg @ref HAL_HASH_MSPINIT_CB_ID HASH MspInit callback ID - * @arg @ref HAL_HASH_MSPDEINIT_CB_ID HASH MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hhash); - - if (HAL_HASH_STATE_READY == hhash->State) - { - switch (CallbackID) - { - case HAL_HASH_INPUTCPLT_CB_ID : - hhash->InCpltCallback = HAL_HASH_InCpltCallback; /* Legacy weak (surcharged) input completion callback */ - break; - - case HAL_HASH_DGSTCPLT_CB_ID : - hhash->DgstCpltCallback = HAL_HASH_DgstCpltCallback; /* Legacy weak (surcharged) digest computation - completion callback */ - break; - - case HAL_HASH_ERROR_CB_ID : - hhash->ErrorCallback = HAL_HASH_ErrorCallback; /* Legacy weak (surcharged) error callback */ - break; - - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; - - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; - - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_HASH_STATE_RESET == hhash->State) - { - switch (CallbackID) - { - case HAL_HASH_MSPINIT_CB_ID : - hhash->MspInitCallback = HAL_HASH_MspInit; /* Legacy weak (surcharged) Msp Init */ - break; - - case HAL_HASH_MSPDEINIT_CB_ID : - hhash->MspDeInitCallback = HAL_HASH_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */ - break; - - default : - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hhash->ErrorCode |= HAL_HASH_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hhash); - return status; -} -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode - * @brief HASH processing functions using polling mode. - * -@verbatim - =============================================================================== - ##### Polling mode HASH processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in polling mode - the hash value using one of the following algorithms: - (+) MD5 - (++) HAL_HASH_MD5_Start() - (++) HAL_HASH_MD5_Accmlt() - (++) HAL_HASH_MD5_Accmlt_End() - (+) SHA1 - (++) HAL_HASH_SHA1_Start() - (++) HAL_HASH_SHA1_Accmlt() - (++) HAL_HASH_SHA1_Accmlt_End() - - [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start(). - - [..] In case of multi-buffer HASH processing (a single digest is computed while - several buffers are fed to the Peripheral), the user can resort to successive calls - to HAL_HASH_xxx_Accumulate() and wrap-up the digest computation by a call - to HAL_HASH_xxx_Accumulate_End(). - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout) -{ - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief If not already done, initialize the HASH peripheral in MD5 mode then - * processes pInBuffer. - * @note Consecutive calls to HAL_HASH_MD5_Accmlt() can be used to feed - * several input buffers back-to-back to the Peripheral that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_MD5_Accmlt_End(). - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note Digest is not retrieved by this API, user must resort to HAL_HASH_MD5_Accmlt_End() - * to read it, feeding at the same time the last input buffer to the Peripheral. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt() API. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout) -{ - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); -} - -/** - * @brief If not already done, initialize the HASH peripheral in SHA1 mode then - * processes pInBuffer. - * @note Consecutive calls to HAL_HASH_SHA1_Accmlt() can be used to feed - * several input buffers back-to-back to the Peripheral that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_SHA1_Accmlt_End(). - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note Digest is not retrieved by this API, user must resort to HAL_HASH_SHA1_Accmlt_End() - * to read it, feeding at the same time the last input buffer to the Peripheral. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); -} - -/** - * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt() API. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode - * @brief HASH processing functions using interrupt mode. - * -@verbatim - =============================================================================== - ##### Interruption mode HASH processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in interrupt mode - the hash value using one of the following algorithms: - (+) MD5 - (++) HAL_HASH_MD5_Start_IT() - (++) HAL_HASH_MD5_Accmlt_IT() - (++) HAL_HASH_MD5_Accmlt_End_IT() - (+) SHA1 - (++) HAL_HASH_SHA1_Start_IT() - (++) HAL_HASH_SHA1_Accmlt_IT() - (++) HAL_HASH_SHA1_Accmlt_End_IT() - - [..] API HAL_HASH_IRQHandler() manages each HASH interruption. - - [..] Note that HAL_HASH_IRQHandler() manages as well HASH Peripheral interruptions when in - HMAC processing mode. - - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the HASH peripheral in MD5 mode, next process pInBuffer then - * read the computed digest in interruption mode. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief If not already done, initialize the HASH peripheral in MD5 mode then - * processes pInBuffer in interruption mode. - * @note Consecutive calls to HAL_HASH_MD5_Accmlt_IT() can be used to feed - * several input buffers back-to-back to the Peripheral that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_MD5_Accmlt_End_IT(). - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASH_MD5_Accmlt_End_IT() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief End computation of a single HASH signature after several calls to HAL_HASH_MD5_Accmlt_IT() API. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief Initialize the HASH peripheral in SHA1 mode, next process pInBuffer then - * read the computed digest in interruption mode. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); -} - - -/** - * @brief If not already done, initialize the HASH peripheral in SHA1 mode then - * processes pInBuffer in interruption mode. - * @note Consecutive calls to HAL_HASH_SHA1_Accmlt_IT() can be used to feed - * several input buffers back-to-back to the Peripheral that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASH_SHA1_Accmlt_End_IT(). - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASH_SHA1_Accmlt_End_IT() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); -} - -/** - * @brief End computation of a single HASH signature after several calls to HAL_HASH_SHA1_Accmlt_IT() API. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); -} - -/** - * @brief Handle HASH interrupt request. - * @param hhash HASH handle. - * @note HAL_HASH_IRQHandler() handles interrupts in HMAC processing as well. - * @note In case of error reported during the HASH interruption processing, - * HAL_HASH_ErrorCallback() API is called so that user code can - * manage the error. The error type is available in hhash->Status field. - * @retval None - */ -void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) -{ - hhash->Status = HASH_IT(hhash); - if (hhash->Status != HAL_OK) - { - hhash->ErrorCode |= HAL_HASH_ERROR_IT; -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->ErrorCallback(hhash); -#else - HAL_HASH_ErrorCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - /* After error handling by code user, reset HASH handle HAL status */ - hhash->Status = HAL_OK; - } -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode - * @brief HASH processing functions using DMA mode. - * -@verbatim - =============================================================================== - ##### DMA mode HASH processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in DMA mode - the hash value using one of the following algorithms: - (+) MD5 - (++) HAL_HASH_MD5_Start_DMA() - (++) HAL_HASH_MD5_Finish() - (+) SHA1 - (++) HAL_HASH_SHA1_Start_DMA() - (++) HAL_HASH_SHA1_Finish() - - [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort - to HAL_HASH_xxx_Start_DMA() then read the resulting digest with - HAL_HASH_xxx_Finish(). - [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before - the successive calls to HAL_HASH_xxx_Start_DMA(). Then, MDMAT bit needs to be - reset before the last call to HAL_HASH_xxx_Start_DMA(). Digest is finally - retrieved thanks to HAL_HASH_xxx_Finish(). - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the HASH peripheral in MD5 mode then initiate a DMA transfer - * to feed the input buffer to the Peripheral. - * @note Once the DMA transfer is finished, HAL_HASH_MD5_Finish() API must - * be called to retrieve the computed digest. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief Return the computed digest in MD5 mode. - * @note The API waits for DCIS to be set then reads the computed digest. - * @note HAL_HASH_MD5_Finish() can be used as well to retrieve the digest in - * HMAC MD5 mode. - * @param hhash HASH handle. - * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); -} - -/** - * @brief Initialize the HASH peripheral in SHA1 mode then initiate a DMA transfer - * to feed the input buffer to the Peripheral. - * @note Once the DMA transfer is finished, HAL_HASH_SHA1_Finish() API must - * be called to retrieve the computed digest. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); -} - - -/** - * @brief Return the computed digest in SHA1 mode. - * @note The API waits for DCIS to be set then reads the computed digest. - * @note HAL_HASH_SHA1_Finish() can be used as well to retrieve the digest in - * HMAC SHA1 mode. - * @param hhash HASH handle. - * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode - * @brief HMAC processing functions using polling mode. - * -@verbatim - =============================================================================== - ##### Polling mode HMAC processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in polling mode - the HMAC value using one of the following algorithms: - (+) MD5 - (++) HAL_HMAC_MD5_Start() - (+) SHA1 - (++) HAL_HMAC_SHA1_Start() - - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout) -{ - return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout) -{ - return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); -} - -/** - * @} - */ - - -/** @defgroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode - * @brief HMAC processing functions using interrupt mode. - * -@verbatim - =============================================================================== - ##### Interrupt mode HMAC processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in interrupt mode - the HMAC value using one of the following algorithms: - (+) MD5 - (++) HAL_HMAC_MD5_Start_IT() - (+) SHA1 - (++) HAL_HMAC_SHA1_Start_IT() - -@endverbatim - * @{ - */ - - -/** - * @brief Initialize the HASH peripheral in HMAC MD5 mode, next process pInBuffer then - * read the computed digest in interrupt mode. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief Initialize the HASH peripheral in HMAC SHA1 mode, next process pInBuffer then - * read the computed digest in interrupt mode. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); -} - -/** - * @} - */ - - - -/** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode - * @brief HMAC processing functions using DMA modes. - * -@verbatim - =============================================================================== - ##### DMA mode HMAC processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in DMA mode - the HMAC value using one of the following algorithms: - (+) MD5 - (++) HAL_HMAC_MD5_Start_DMA() - (+) SHA1 - (++) HAL_HMAC_SHA1_Start_DMA() - - [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing, - user must resort to HAL_HMAC_xxx_Start_DMA() then read the resulting digest - with HAL_HASH_xxx_Finish(). - -@endverbatim - * @{ - */ - - -/** - * @brief Initialize the HASH peripheral in HMAC MD5 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the Peripheral. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASH_MD5_Finish() API must be called to retrieve - * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be - * a multiple of 4 otherwise, the HASH digest computation is corrupted. - * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); -} - - -/** - * @brief Initialize the HASH peripheral in HMAC SHA1 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the Peripheral. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASH_SHA1_Finish() API must be called to retrieve - * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be - * a multiple of 4 otherwise, the HASH digest computation is corrupted. - * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); -} - -/** - * @} - */ - -/** @defgroup HASH_Exported_Functions_Group8 Peripheral states functions - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State methods ##### - =============================================================================== - [..] - This section permits to get in run-time the state and the peripheral handle - status of the peripheral: - (+) HAL_HASH_GetState() - (+) HAL_HASH_GetStatus() - - [..] - Additionally, this subsection provides functions allowing to save and restore - the HASH or HMAC processing context in case of calculation suspension: - (+) HAL_HASH_ContextSaving() - (+) HAL_HASH_ContextRestoring() - - [..] - This subsection provides functions allowing to suspend the HASH processing - (+) when input are fed to the Peripheral by software - (++) HAL_HASH_SwFeed_ProcessSuspend() - (+) when input are fed to the Peripheral by DMA - (++) HAL_HASH_DMAFeed_ProcessSuspend() - - - -@endverbatim - * @{ - */ - -/** - * @brief Return the HASH handle state. - * @note The API yields the current state of the handle (BUSY, READY,...). - * @param hhash HASH handle. - * @retval HAL HASH state - */ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) -{ - return hhash->State; -} - - -/** - * @brief Return the HASH HAL status. - * @note The API yields the HAL status of the handle: it is the result of the - * latest HASH processing and allows to report any issue (e.g. HAL_TIMEOUT). - * @param hhash HASH handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) -{ - return hhash->Status; -} - -/** - * @brief Save the HASH context in case of processing suspension. - * @param hhash HASH handle. - * @param pMemBuffer pointer to the memory buffer where the HASH context - * is saved. - * @note The IMR, STR, CR then all the CSR registers are saved - * in that order. Only the r/w bits are read to be restored later on. - * @note By default, all the context swap registers (there are - * HASH_NUMBER_OF_CSR_REGISTERS of those) are saved. - * @note pMemBuffer points to a buffer allocated by the user. The buffer size - * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. - * @retval None - */ -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) -{ - uint32_t mem_ptr = (uint32_t)pMemBuffer; - uint32_t csr_ptr = (uint32_t)HASH->CSR; - uint32_t i; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* Save IMR register content */ - *(uint32_t *)(mem_ptr) = READ_BIT(HASH->IMR, HASH_IT_DINI | HASH_IT_DCI); - mem_ptr += 4U; - /* Save STR register content */ - *(uint32_t *)(mem_ptr) = READ_BIT(HASH->STR, HASH_STR_NBLW); - mem_ptr += 4U; - /* Save CR register content */ - *(uint32_t *)(mem_ptr) = READ_BIT(HASH->CR, HASH_CR_DMAE | HASH_CR_DATATYPE | HASH_CR_MODE | HASH_CR_ALGO | - HASH_CR_LKEY | HASH_CR_MDMAT); - mem_ptr += 4U; - /* By default, save all CSRs registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) - { - *(uint32_t *)(mem_ptr) = *(uint32_t *)(csr_ptr); - mem_ptr += 4U; - csr_ptr += 4U; - } -} - - -/** - * @brief Restore the HASH context in case of processing resumption. - * @param hhash HASH handle. - * @param pMemBuffer pointer to the memory buffer where the HASH context - * is stored. - * @note The IMR, STR, CR then all the CSR registers are restored - * in that order. Only the r/w bits are restored. - * @note By default, all the context swap registers (HASH_NUMBER_OF_CSR_REGISTERS - * of those) are restored (all of them have been saved by default - * beforehand). - * @retval None - */ -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) -{ - uint32_t mem_ptr = (uint32_t)pMemBuffer; - uint32_t csr_ptr = (uint32_t)HASH->CSR; - uint32_t i; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhash); - - /* Restore IMR register content */ - WRITE_REG(HASH->IMR, (*(uint32_t *)(mem_ptr))); - mem_ptr += 4U; - /* Restore STR register content */ - WRITE_REG(HASH->STR, (*(uint32_t *)(mem_ptr))); - mem_ptr += 4U; - /* Restore CR register content */ - WRITE_REG(HASH->CR, (*(uint32_t *)(mem_ptr))); - mem_ptr += 4U; - - /* Reset the HASH processor before restoring the Context - Swap Registers (CSR) */ - __HAL_HASH_INIT(); - - /* By default, restore all CSR registers */ - for (i = HASH_NUMBER_OF_CSR_REGISTERS; i > 0U; i--) - { - WRITE_REG((*(uint32_t *)(csr_ptr)), (*(uint32_t *)(mem_ptr))); - mem_ptr += 4U; - csr_ptr += 4U; - } -} - - -/** - * @brief Initiate HASH processing suspension when in polling or interruption mode. - * @param hhash HASH handle. - * @note Set the handle field SuspendRequest to the appropriate value so that - * the on-going HASH processing is suspended as soon as the required - * conditions are met. Note that the actual suspension is carried out - * by the functions HASH_WriteData() in polling mode and HASH_IT() in - * interruption mode. - * @retval None - */ -void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) -{ - /* Set Handle Suspend Request field */ - hhash->SuspendRequest = HAL_HASH_SUSPEND; -} - -/** - * @brief Suspend the HASH processing when in DMA mode. - * @param hhash HASH handle. - * @note When suspension attempt occurs at the very end of a DMA transfer and - * all the data have already been entered in the Peripheral, hhash->State is - * set to HAL_HASH_STATE_READY and the API returns HAL_ERROR. It is - * recommended to wrap-up the processing in reading the digest as usual. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) -{ - uint32_t tmp_remaining_DMATransferSize_inWords; - uint32_t tmp_initial_DMATransferSize_inWords; - uint32_t tmp_words_already_pushed; - - if (hhash->State == HAL_HASH_STATE_READY) - { - return HAL_ERROR; - } - else - { - - /* Make sure there is enough time to suspend the processing */ - tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR; - - if (tmp_remaining_DMATransferSize_inWords <= HASH_DMA_SUSPENSION_WORDS_LIMIT) - { - /* No suspension attempted since almost to the end of the transferred data. */ - /* Best option for user code is to wrap up low priority message hashing */ - return HAL_ERROR; - } - - /* Wait for BUSY flag to be reset */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) - { - return HAL_ERROR; - } - - /* Wait for BUSY flag to be set */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, RESET, HASH_TIMEOUTVALUE) != HAL_OK) - { - return HAL_TIMEOUT; - } - /* Disable DMA channel */ - /* Note that the Abort function will - - Clear the transfer error flags - - Unlock - - Set the State - */ - if (HAL_DMA_Abort(hhash->hdmain) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear DMAE bit */ - CLEAR_BIT(HASH->CR, HASH_CR_DMAE); - - /* Wait for BUSY flag to be reset */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS) != RESET) - { - return HAL_ERROR; - } - - /* At this point, DMA interface is disabled and no transfer is on-going */ - /* Retrieve from the DMA handle how many words remain to be written */ - tmp_remaining_DMATransferSize_inWords = ((DMA_Stream_TypeDef *)hhash->hdmain->Instance)->NDTR; - - if (tmp_remaining_DMATransferSize_inWords == 0U) - { - /* All the DMA transfer is actually done. Suspension occurred at the very end - of the transfer. Either the digest computation is about to start (HASH case) - or processing is about to move from one step to another (HMAC case). - In both cases, the processing can't be suspended at this point. It is - safer to - - retrieve the low priority block digest before starting the high - priority block processing (HASH case) - - re-attempt a new suspension (HMAC case) - */ - return HAL_ERROR; - } - else - { - - /* Compute how many words were supposed to be transferred by DMA */ - tmp_initial_DMATransferSize_inWords = (((hhash->HashInCount % 4U) != 0U) ? \ - ((hhash->HashInCount + 3U) / 4U) : (hhash->HashInCount / 4U)); - - /* If discrepancy between the number of words reported by DMA Peripheral and - the numbers of words entered as reported by HASH Peripheral, correct it */ - /* tmp_words_already_pushed reflects the number of words that were already pushed before - the start of DMA transfer (multi-buffer processing case) */ - tmp_words_already_pushed = hhash->NbWordsAlreadyPushed; - if (((tmp_words_already_pushed + tmp_initial_DMATransferSize_inWords - \ - tmp_remaining_DMATransferSize_inWords) % 16U) != HASH_NBW_PUSHED()) - { - tmp_remaining_DMATransferSize_inWords--; /* one less word to be transferred again */ - } - - /* Accordingly, update the input pointer that points at the next word to be - transferred to the Peripheral by DMA */ - hhash->pHashInBuffPtr += 4U * (tmp_initial_DMATransferSize_inWords - tmp_remaining_DMATransferSize_inWords) ; - - /* And store in HashInCount the remaining size to transfer (in bytes) */ - hhash->HashInCount = 4U * tmp_remaining_DMATransferSize_inWords; - - } - - /* Set State as suspended */ - hhash->State = HAL_HASH_STATE_SUSPENDED; - - return HAL_OK; - - } -} - -/** - * @brief Return the HASH handle error code. - * @param hhash pointer to a HASH_HandleTypeDef structure. - * @retval HASH Error Code - */ -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) -{ - /* Return HASH Error Code */ - return hhash->ErrorCode; -} -/** - * @} - */ - - -/** - * @} - */ - -/** @defgroup HASH_Private_Functions HASH Private Functions - * @{ - */ - -/** - * @brief DMA HASH Input Data transfer completion callback. - * @param hdma DMA handle. - * @note In case of HMAC processing, HASH_DMAXferCplt() initiates - * the next DMA transfer for the following HMAC step. - * @retval None - */ -static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) -{ - HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - uint32_t inputaddr; - uint32_t buffersize; - HAL_StatusTypeDef status; - - if (hhash->State != HAL_HASH_STATE_SUSPENDED) - { - - /* Disable the DMA transfer */ - CLEAR_BIT(HASH->CR, HASH_CR_DMAE); - - if (READ_BIT(HASH->CR, HASH_CR_MODE) == 0U) - { - /* If no HMAC processing, input data transfer is now over */ - - /* Change the HASH state to ready */ - hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete call back */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->InCpltCallback(hhash); -#else - HAL_HASH_InCpltCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - } - else - { - /* HMAC processing: depending on the current HMAC step and whether or - not multi-buffer processing is on-going, the next step is initiated - and MDMAT bit is set. */ - - - if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) - { - /* This is the end of HMAC processing */ - - /* Change the HASH state to ready */ - hhash->State = HAL_HASH_STATE_READY; - - /* Call Input data transfer complete call back - (note that the last DMA transfer was that of the key - for the outer HASH operation). */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->InCpltCallback(hhash); -#else - HAL_HASH_InCpltCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - return; - } - else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) - { - inputaddr = (uint32_t)hhash->pHashMsgBuffPtr; /* DMA transfer start address */ - buffersize = hhash->HashBuffSize; /* DMA transfer size (in bytes) */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ - - /* In case of suspension request, save the new starting parameters */ - hhash->HashInCount = hhash->HashBuffSize; /* Initial DMA transfer size (in bytes) */ - hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr ; /* DMA transfer start address */ - - hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */ - /* Check whether or not digest calculation must be disabled (in case of multi-buffer HMAC processing) */ - if (hhash->DigestCalculationDisable != RESET) - { - /* Digest calculation is disabled: Step 2 must start with MDMAT bit set, - no digest calculation will be triggered at the end of the input buffer feeding to the Peripheral */ - __HAL_HASH_SET_MDMAT(); - } - } - else /*case (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)*/ - { - if (hhash->DigestCalculationDisable != RESET) - { - /* No automatic move to Step 3 as a new message buffer will be fed to the Peripheral - (case of multi-buffer HMAC processing): - DCAL must not be set. - Phase remains in Step 2, MDMAT remains set at this point. - Change the HASH state to ready and call Input data transfer complete call back. */ - hhash->State = HAL_HASH_STATE_READY; -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->InCpltCallback(hhash); -#else - HAL_HASH_InCpltCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - return ; - } - else - { - /* Digest calculation is not disabled (case of single buffer input or last buffer - of multi-buffer HMAC processing) */ - inputaddr = (uint32_t)hhash->Init.pKey; /* DMA transfer start address */ - buffersize = hhash->Init.KeySize; /* DMA transfer size (in bytes) */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ - /* In case of suspension request, save the new starting parameters */ - hhash->HashInCount = hhash->Init.KeySize; /* Initial size for second DMA transfer (input data) */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* address passed to DMA, now entering data message */ - - hhash->NbWordsAlreadyPushed = 0U; /* Reset number of words already pushed */ - } - } - - /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(buffersize); - - /* Set the HASH DMA transfer completion call back */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - - /* Enable the DMA In DMA stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ - (((buffersize % 4U) != 0U) ? ((buffersize + (4U - (buffersize % 4U))) / 4U) : \ - (buffersize / 4U))); - - /* Enable DMA requests */ - SET_BIT(HASH->CR, HASH_CR_DMAE); - - /* Return function status */ - if (status != HAL_OK) - { - /* Update HASH state machine to error */ - hhash->State = HAL_HASH_STATE_ERROR; - } - else - { - /* Change HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - } - } - } - - return; -} - -/** - * @brief DMA HASH communication error callback. - * @param hdma DMA handle. - * @note HASH_DMAError() callback invokes HAL_HASH_ErrorCallback() that - * can contain user code to manage the error. - * @retval None - */ -static void HASH_DMAError(DMA_HandleTypeDef *hdma) -{ - HASH_HandleTypeDef *hhash = (HASH_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hhash->State != HAL_HASH_STATE_SUSPENDED) - { - hhash->ErrorCode |= HAL_HASH_ERROR_DMA; - /* Set HASH state to ready to prevent any blocking issue in user code - present in HAL_HASH_ErrorCallback() */ - hhash->State = HAL_HASH_STATE_READY; - /* Set HASH handle status to error */ - hhash->Status = HAL_ERROR; -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->ErrorCallback(hhash); -#else - HAL_HASH_ErrorCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - /* After error handling by code user, reset HASH handle HAL status */ - hhash->Status = HAL_OK; - - } -} - -/** - * @brief Feed the input buffer to the HASH Peripheral. - * @param hhash HASH handle. - * @param pInBuffer pointer to input buffer. - * @param Size the size of input buffer in bytes. - * @note HASH_WriteData() regularly reads hhash->SuspendRequest to check whether - * or not the HASH processing must be suspended. If this is the case, the - * processing is suspended when possible and the Peripheral feeding point reached at - * suspension time is stored in the handle for resumption later on. - * @retval HAL status - */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - uint32_t buffercounter; - __IO uint32_t inputaddr = (uint32_t) pInBuffer; - uint32_t tmp; - - for (buffercounter = 0U; buffercounter < Size / 4U; buffercounter++) - { - /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t *)inputaddr; - inputaddr += 4U; - - /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ - if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter * 4 + 4U) < Size)) - { - /* wait for flag BUSY not set before Wait for DINIS = 1*/ - if (buffercounter * 4 >= 64U) - { - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) - { - return HAL_TIMEOUT; - } - } - /* Wait for DINIS = 1, which occurs when 16 32-bit locations are free - in the input buffer */ - if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { - /* Reset SuspendRequest */ - hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; - - /* Depending whether the key or the input data were fed to the Peripheral, the feeding point - reached at suspension time is not saved in the same handle fields */ - if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2)) - { - /* Save current reading and writing locations of Input and Output buffers */ - hhash->pHashInBuffPtr = (uint8_t *)inputaddr; - /* Save the number of bytes that remain to be processed at this point */ - hhash->HashInCount = Size - (buffercounter * 4 + 4U); - } - else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) - { - /* Save current reading and writing locations of Input and Output buffers */ - hhash->pHashKeyBuffPtr = (uint8_t *)inputaddr; - /* Save the number of bytes that remain to be processed at this point */ - hhash->HashKeyCount = Size - (buffercounter * 4 + 4U); - } - else - { - /* Unexpected phase: unlock process and report error */ - hhash->State = HAL_HASH_STATE_READY; - __HAL_UNLOCK(hhash); - return HAL_ERROR; - } - - /* Set the HASH state to Suspended and exit to stop entering data */ - hhash->State = HAL_HASH_STATE_SUSPENDED; - - return HAL_OK; - } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) */ - } /* if ((hhash->SuspendRequest == HAL_HASH_SUSPEND) && ((buffercounter+4) < Size)) */ - } /* for(buffercounter = 0; buffercounter < Size; buffercounter+=4) */ - - /* At this point, all the data have been entered to the Peripheral: exit */ - - if (Size % 4U != 0U) - { - if (hhash->Init.DataType == HASH_DATATYPE_16B) - { - /* Write remaining input data */ - - if (Size % 4U <= 2) - { - HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; - } - if (Size % 4U == 3) - { - HASH->DIN = *(uint32_t *)inputaddr; - } - - } - else if ((hhash->Init.DataType == HASH_DATATYPE_8B) - || (hhash->Init.DataType == HASH_DATATYPE_1B)) /* byte swap or bit swap or */ - { - /* Write remaining input data */ - if (Size % 4U == 1) - { - HASH->DIN = (uint32_t) * (uint8_t *)inputaddr; - } - if (Size % 4U == 2) - { - HASH->DIN = (uint32_t) * (uint16_t *)inputaddr; - } - if (Size % 4U == 3) - { - tmp = *(uint8_t *)inputaddr; - tmp |= *(uint8_t *)(inputaddr + 1U) << 8U ; - tmp |= *(uint8_t *)(inputaddr + 2U) << 16U; - HASH->DIN = tmp; - } - - } - else - { - HASH->DIN = *(uint32_t *)inputaddr; - } - /*hhash->HashInCount += 4U;*/ - } - - - return HAL_OK; -} - -/** - * @brief Retrieve the message digest. - * @param pMsgDigest pointer to the computed digest. - * @param Size message digest size in bytes. - * @retval None - */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) -{ - uint32_t msgdigest = (uint32_t)pMsgDigest; - - switch (Size) - { - /* Read the message digest */ - case 16: /* MD5 */ - *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); - break; - case 20: /* SHA1 */ - *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); - break; - case 28: /* SHA224 */ - *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - break; - case 32: /* SHA256 */ - *(uint32_t *)(msgdigest) = __REV(HASH->HR[0]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[1]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[2]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[3]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH->HR[4]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[5]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[6]); - msgdigest += 4U; - *(uint32_t *)(msgdigest) = __REV(HASH_DIGEST->HR[7]); - break; - default: - break; - } -} - - - -/** - * @brief Handle HASH processing Timeout. - * @param hhash HASH handle. - * @param Flag specifies the HASH flag to check. - * @param Status the Flag status (SET or RESET). - * @param Timeout Timeout duration. - * @retval HAL status - */ -static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, - uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - if (Status == RESET) - { - while (__HAL_HASH_GET_FLAG(Flag) == RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Set State to Ready to be able to restart later on */ - hhash->State = HAL_HASH_STATE_READY; - /* Store time out issue in handle status */ - hhash->Status = HAL_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - } - else - { - while (__HAL_HASH_GET_FLAG(Flag) != RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Set State to Ready to be able to restart later on */ - hhash->State = HAL_HASH_STATE_READY; - /* Store time out issue in handle status */ - hhash->Status = HAL_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - - -/** - * @brief HASH processing in interruption mode. - * @param hhash HASH handle. - * @note HASH_IT() regularly reads hhash->SuspendRequest to check whether - * or not the HASH processing must be suspended. If this is the case, the - * processing is suspended when possible and the Peripheral feeding point reached at - * suspension time is stored in the handle for resumption later on. - * @retval HAL status - */ -static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash) -{ - if (hhash->State == HAL_HASH_STATE_BUSY) - { - /* ITCounter must not be equal to 0 at this point. Report an error if this is the case. */ - if (hhash->HashITCounter == 0U) - { - /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); - /* HASH state set back to Ready to prevent any issue in user code - present in HAL_HASH_ErrorCallback() */ - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - else if (hhash->HashITCounter == 1U) - { - /* This is the first call to HASH_IT, the first input data are about to be - entered in the Peripheral. A specific processing is carried out at this point to - start-up the processing. */ - hhash->HashITCounter = 2U; - } - else - { - /* Cruise speed reached, HashITCounter remains equal to 3 until the end of - the HASH processing or the end of the current step for HMAC processing. */ - hhash->HashITCounter = 3U; - } - - /* If digest is ready */ - if (__HAL_HASH_GET_FLAG(HASH_FLAG_DCIS)) - { - /* Read the digest */ - HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); - - /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - /* Reset HASH state machine */ - hhash->Phase = HAL_HASH_PHASE_READY; - /* Call digest computation complete call back */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->DgstCpltCallback(hhash); -#else - HAL_HASH_DgstCpltCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - return HAL_OK; - } - - /* If Peripheral ready to accept new data */ - if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { - - /* If the suspension flag has been raised and if the processing is not about - to end, suspend processing */ - if ((hhash->HashInCount != 0U) && (hhash->SuspendRequest == HAL_HASH_SUSPEND)) - { - /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); - - /* Reset SuspendRequest */ - hhash->SuspendRequest = HAL_HASH_SUSPEND_NONE; - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_SUSPENDED; - - return HAL_OK; - } - - /* Enter input data in the Peripheral through HASH_Write_Block_Data() call and - check whether the digest calculation has been triggered */ - if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) - { - /* Call Input data transfer complete call back - (called at the end of each step for HMAC) */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->InCpltCallback(hhash); -#else - HAL_HASH_InCpltCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - - if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) - { - /* Wait until Peripheral is not busy anymore */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) - { - /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); - return HAL_TIMEOUT; - } - /* Initialization start for HMAC STEP 2 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; /* Move phase from Step 1 to Step 2 */ - __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); /* Set NBLW for the input message */ - hhash->HashInCount = hhash->HashBuffSize; /* Set the input data size (in bytes) */ - hhash->pHashInBuffPtr = hhash->pHashMsgBuffPtr; /* Set the input data address */ - hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start - of a new phase */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ - } - else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) - { - /* Wait until Peripheral is not busy anymore */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, HASH_TIMEOUTVALUE) != HAL_OK) - { - /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI | HASH_IT_DCI); - return HAL_TIMEOUT; - } - /* Initialization start for HMAC STEP 3 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; /* Move phase from Step 2 to Step 3 */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); /* Set NBLW for the key */ - hhash->HashInCount = hhash->Init.KeySize; /* Set the key size (in bytes) */ - hhash->pHashInBuffPtr = hhash->Init.pKey; /* Set the key address */ - hhash->HashITCounter = 1; /* Set ITCounter to 1 to indicate the start - of a new phase */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI); /* Enable IT (was disabled in HASH_Write_Block_Data) */ - } - else - { - /* Nothing to do */ - } - } /* if (HASH_Write_Block_Data(hhash) == HASH_DIGEST_CALCULATION_STARTED) */ - } /* if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))*/ - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Write a block of data in HASH Peripheral in interruption mode. - * @param hhash HASH handle. - * @note HASH_Write_Block_Data() is called under interruption by HASH_IT(). - * @retval HAL status - */ -static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash) -{ - uint32_t inputaddr; - uint32_t buffercounter; - uint32_t inputcounter; - uint32_t ret = HASH_DIGEST_CALCULATION_NOT_STARTED; - - /* If there are more than 64 bytes remaining to be entered */ - if (hhash->HashInCount > 64U) - { - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Write the Input block in the Data IN register - (16 32-bit words, or 64 bytes are entered) */ - for (buffercounter = 0U; buffercounter < 64U; buffercounter += 4U) - { - HASH->DIN = *(uint32_t *)inputaddr; - inputaddr += 4U; - } - /* If this is the start of input data entering, an additional word - must be entered to start up the HASH processing */ - if (hhash->HashITCounter == 2U) - { - HASH->DIN = *(uint32_t *)inputaddr; - if (hhash->HashInCount >= 68U) - { - /* There are still data waiting to be entered in the Peripheral. - Decrement buffer counter and set pointer to the proper - memory location for the next data entering round. */ - hhash->HashInCount -= 68U; - hhash->pHashInBuffPtr += 68U; - } - else - { - /* All the input buffer has been fed to the HW. */ - hhash->HashInCount = 0U; - } - } - else - { - /* 64 bytes have been entered and there are still some remaining: - Decrement buffer counter and set pointer to the proper - memory location for the next data entering round.*/ - hhash->HashInCount -= 64U; - hhash->pHashInBuffPtr += 64U; - } - } - else - { - /* 64 or less bytes remain to be entered. This is the last - data entering round. */ - - /* Get the buffer address */ - inputaddr = (uint32_t)hhash->pHashInBuffPtr; - /* Get the buffer counter */ - inputcounter = hhash->HashInCount; - /* Disable Interrupts */ - __HAL_HASH_DISABLE_IT(HASH_IT_DINI); - - /* Write the Input block in the Data IN register */ - for (buffercounter = 0U; buffercounter < ((inputcounter + 3U) / 4U); buffercounter++) - { - HASH->DIN = *(uint32_t *)inputaddr; - inputaddr += 4U; - } - - if (hhash->Accumulation == 1U) - { - /* Field accumulation is set, API only feeds data to the Peripheral and under interruption. - The digest computation will be started when the last buffer data are entered. */ - - /* Reset multi buffers accumulation flag */ - hhash->Accumulation = 0U; - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - /* Call Input data transfer complete call back */ -#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1) - hhash->InCpltCallback(hhash); -#else - HAL_HASH_InCpltCallback(hhash); -#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */ - } - else - { - /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); - /* Return indication that digest calculation has started: - this return value triggers the call to Input data transfer - complete call back as well as the proper transition from - one step to another in HMAC mode. */ - ret = HASH_DIGEST_CALCULATION_STARTED; - } - /* Reset buffer counter */ - hhash->HashInCount = 0; - } - - /* Return whether or digest calculation has started */ - return ret; -} - -/** - * @brief HMAC processing in polling mode. - * @param hhash HASH handle. - * @param Timeout Timeout value. - * @retval HAL status - */ -static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout) -{ - /* Ensure first that Phase is correct */ - if ((hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_1) && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_2) - && (hhash->Phase != HAL_HASH_PHASE_HMAC_STEP_3)) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_ERROR; - } - - /* HMAC Step 1 processing */ - if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) - { - /************************** STEP 1 ******************************************/ - /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in Data register */ - hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount); - if (hhash->Status != HAL_OK) - { - return hhash->Status; - } - - /* Check whether or not key entering process has been suspended */ - if (hhash->State == HAL_HASH_STATE_SUSPENDED) - { - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Stop right there and return function status */ - return HAL_OK; - } - - /* No processing suspension at this point: set DCAL bit. */ - __HAL_HASH_START_DIGEST(); - - /* Wait for BUSY flag to be cleared */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Move from Step 1 to Step 2 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_2; - - } - - /* HMAC Step 2 processing. - After phase check, HMAC_Processing() may - - directly start up from this point in resumption case - if the same Step 2 processing was suspended previously - - or fall through from the Step 1 processing carried out hereabove */ - if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) - { - /************************** STEP 2 ******************************************/ - /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->HashBuffSize); - - /* Write input buffer in Data register */ - hhash->Status = HASH_WriteData(hhash, hhash->pHashInBuffPtr, hhash->HashInCount); - if (hhash->Status != HAL_OK) - { - return hhash->Status; - } - - /* Check whether or not data entering process has been suspended */ - if (hhash->State == HAL_HASH_STATE_SUSPENDED) - { - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Stop right there and return function status */ - return HAL_OK; - } - - /* No processing suspension at this point: set DCAL bit. */ - __HAL_HASH_START_DIGEST(); - - /* Wait for BUSY flag to be cleared */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_BUSY, SET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Move from Step 2 to Step 3 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_3; - /* In case Step 1 phase was suspended then resumed, - set again Key input buffers and size before moving to - next step */ - hhash->pHashKeyBuffPtr = hhash->Init.pKey; - hhash->HashKeyCount = hhash->Init.KeySize; - } - - - /* HMAC Step 3 processing. - After phase check, HMAC_Processing() may - - directly start up from this point in resumption case - if the same Step 3 processing was suspended previously - - or fall through from the Step 2 processing carried out hereabove */ - if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3) - { - /************************** STEP 3 ******************************************/ - /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Write input buffer in Data register */ - hhash->Status = HASH_WriteData(hhash, hhash->pHashKeyBuffPtr, hhash->HashKeyCount); - if (hhash->Status != HAL_OK) - { - return hhash->Status; - } - - /* Check whether or not key entering process has been suspended */ - if (hhash->State == HAL_HASH_STATE_SUSPENDED) - { - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Stop right there and return function status */ - return HAL_OK; - } - - /* No processing suspension at this point: start the Digest calculation. */ - __HAL_HASH_START_DIGEST(); - - /* Wait for DCIS flag to be set */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read the message digest */ - HASH_GetDigest(hhash->pHashOutBuffPtr, HASH_DIGEST_LENGTH()); - - /* Reset HASH state machine */ - hhash->Phase = HAL_HASH_PHASE_READY; - } - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Initialize the HASH peripheral, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. - * @param Timeout Timeout value. - * @param Algorithm HASH algorithm. - * @retval HAL status - */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout, uint32_t Algorithm) -{ - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ - uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ - HAL_HASH_StateTypeDef State_tmp = hhash->State; - - - /* Initiate HASH processing in case of start or resumption */ - if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) - { - /* Check input parameters */ - if ((pInBuffer == NULL) || (pOutBuffer == NULL)) - { - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Check if initialization phase has not been already performed */ - if (hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ - Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - } - else if (hhash->Phase == HAL_HASH_PHASE_PROCESS) - { - /* if the Peripheral has already been initialized, two cases are possible */ - - /* Process resumption time ... */ - if (hhash->State == HAL_HASH_STATE_SUSPENDED) - { - /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set - to the API input parameters but to those saved beforehand by HASH_WriteData() - when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; - Size_tmp = hhash->HashInCount; - } - /* ... or multi-buffer HASH processing end */ - else - { - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; - Size_tmp = Size; - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - } - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - } - else - { - /* Phase error */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_ERROR; - } - - - /* Write input buffer in Data register */ - hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp); - if (hhash->Status != HAL_OK) - { - return hhash->Status; - } - - /* If the process has not been suspended, carry on to digest calculation */ - if (hhash->State != HAL_HASH_STATE_SUSPENDED) - { - /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); - - /* Wait for DCIS flag to be set */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Reset HASH state machine */ - hhash->Phase = HAL_HASH_PHASE_READY; - - } - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief If not already done, initialize the HASH peripheral then - * processes pInBuffer. - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @param Algorithm HASH algorithm. - * @retval HAL status - */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) -{ - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ - uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ - HAL_HASH_StateTypeDef State_tmp = hhash->State; - - /* Make sure the input buffer size (in bytes) is a multiple of 4 */ - if ((Size % 4U) != 0U) - { - return HAL_ERROR; - } - - /* Initiate HASH processing in case of start or resumption */ - if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) - { - /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U)) - { - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* If resuming the HASH processing */ - if (hhash->State == HAL_HASH_STATE_SUSPENDED) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set - to the API input parameters but to those saved beforehand by HASH_WriteData() - when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ - Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ - - } - else - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as - input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ - Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ - - /* Check if initialization phase has already be performed */ - if (hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - } - - /* Write input buffer in Data register */ - hhash->Status = HASH_WriteData(hhash, pInBuffer_tmp, Size_tmp); - if (hhash->Status != HAL_OK) - { - return hhash->Status; - } - - /* If the process has not been suspended, move the state to Ready */ - if (hhash->State != HAL_HASH_STATE_SUSPENDED) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - - } - else - { - return HAL_BUSY; - } - - -} - - -/** - * @brief If not already done, initialize the HASH peripheral then - * processes pInBuffer in interruption mode. - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @param Algorithm HASH algorithm. - * @retval HAL status - */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) -{ - HAL_HASH_StateTypeDef State_tmp = hhash->State; - __IO uint32_t inputaddr = (uint32_t) pInBuffer; - uint32_t SizeVar = Size; - - /* Make sure the input buffer size (in bytes) is a multiple of 4 */ - if ((Size % 4U) != 0U) - { - return HAL_ERROR; - } - - /* Initiate HASH processing in case of start or resumption */ - if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) - { - /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U)) - { - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* If resuming the HASH processing */ - if (hhash->State == HAL_HASH_STATE_SUSPENDED) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - } - else - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already be performed */ - if (hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); - hhash->HashITCounter = 1; - } - else - { - hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* If DINIS is equal to 0 (for example if an incomplete block has been previously - fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. - Therefore, first words are manually entered until DINIS raises, or until there - is not more data to enter. */ - while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 0U)) - { - - /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t *)inputaddr; - inputaddr += 4U; - SizeVar -= 4U; - } - - /* If DINIS is still not set or if all the data have been fed, stop here */ - if ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) || (SizeVar == 0U)) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_READY; - - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - } - - /* otherwise, carry on in interrupt-mode */ - hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data - to be fed to the Peripheral */ - hhash->pHashInBuffPtr = (uint8_t *)inputaddr; /* Points at data which will be fed to the Peripheral at - the next interruption */ - /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain - the information describing where the HASH process is stopped. - These variables are used later on to resume the HASH processing at the - correct location. */ - - } - - /* Set multi buffers accumulation flag */ - hhash->Accumulation = 1U; - - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Enable Data Input interrupt */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI); - - /* Return function status */ - return HAL_OK; - - } - else - { - return HAL_BUSY; - } - -} - - - -/** - * @brief Initialize the HASH peripheral, next process pInBuffer then - * read the computed digest in interruption mode. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. - * @param Algorithm HASH algorithm. - * @retval HAL status - */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Algorithm) -{ - HAL_HASH_StateTypeDef State_tmp = hhash->State; - __IO uint32_t inputaddr = (uint32_t) pInBuffer; - uint32_t polling_step = 0U; - uint32_t initialization_skipped = 0U; - uint32_t SizeVar = Size; - - /* If State is ready or suspended, start or resume IT-based HASH processing */ - if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) - { - /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (pOutBuffer == NULL)) - { - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Initialize IT counter */ - hhash->HashITCounter = 1; - - /* Check if initialization phase has already be performed */ - if (hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); - - /* Configure the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(SizeVar); - - - hhash->HashInCount = SizeVar; /* Counter used to keep track of number of data - to be fed to the Peripheral */ - hhash->pHashInBuffPtr = pInBuffer; /* Points at data which will be fed to the Peripheral at - the next interruption */ - /* In case of suspension, hhash->HashInCount and hhash->pHashInBuffPtr contain - the information describing where the HASH process is stopped. - These variables are used later on to resume the HASH processing at the - correct location. */ - - hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ - } - else - { - initialization_skipped = 1; /* info user later on in case of multi-buffer */ - } - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - - /* If DINIS is equal to 0 (for example if an incomplete block has been previously - fed to the Peripheral), the DINIE interruption won't be triggered when DINIE is set. - Therefore, first words are manually entered until DINIS raises. */ - while ((!(__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS))) && (SizeVar > 3U)) - { - polling_step = 1U; /* note that some words are entered before enabling the interrupt */ - - /* Write input data 4 bytes at a time */ - HASH->DIN = *(uint32_t *)inputaddr; - inputaddr += 4U; - SizeVar -= 4U; - } - - if (polling_step == 1U) - { - if (SizeVar == 0U) - { - /* If all the data have been entered at this point, it only remains to - read the digest */ - hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ - - /* Start the Digest calculation */ - __HAL_HASH_START_DIGEST(); - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Enable Interrupts */ - __HAL_HASH_ENABLE_IT(HASH_IT_DCI); - - /* Return function status */ - return HAL_OK; - } - else if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) - { - /* It remains data to enter and the Peripheral is ready to trigger DINIE, - carry on as usual. - Update HashInCount and pHashInBuffPtr accordingly. */ - hhash->HashInCount = SizeVar; - hhash->pHashInBuffPtr = (uint8_t *)inputaddr; - /* Update the configuration of the number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(SizeVar); - hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ - if (initialization_skipped == 1U) - { - hhash->HashITCounter = 3; /* 'cruise-speed' reached during a previous buffer processing */ - } - } - else - { - /* DINIS is not set but it remains a few data to enter (not enough for a full word). - Manually enter the last bytes before enabling DCIE. */ - __HAL_HASH_SET_NBVALIDBITS(SizeVar); - HASH->DIN = *(uint32_t *)inputaddr; - - /* Start the Digest calculation */ - hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ - __HAL_HASH_START_DIGEST(); - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Enable Interrupts */ - __HAL_HASH_ENABLE_IT(HASH_IT_DCI); - - /* Return function status */ - return HAL_OK; - } - } /* if (polling_step == 1) */ - - - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Enable Interrupts */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_BUSY; - } - -} - - -/** - * @brief Initialize the HASH peripheral then initiate a DMA transfer - * to feed the input buffer to the Peripheral. - * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be - * a multiple of 4 otherwise, the HASH digest computation is corrupted. - * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param Algorithm HASH algorithm. - * @retval HAL status - */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) -{ - uint32_t inputaddr; - uint32_t inputSize; - HAL_StatusTypeDef status ; - HAL_HASH_StateTypeDef State_tmp = hhash->State; - - - /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set - (case of multi-buffer HASH processing) */ - assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); - - /* If State is ready or suspended, start or resume polling-based HASH processing */ - if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) - { - /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || - /* Check phase coherency. Phase must be - either READY (fresh start) - or PROCESS (multi-buffer HASH management) */ - ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HASH_PROCESSING(hhash))))) - { - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* If not a resumption case */ - if (hhash->State == HAL_HASH_STATE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already been performed. - If Phase is already set to HAL_HASH_PHASE_PROCESS, this means the - API is processing a new input data message in case of multi-buffer HASH - computation. */ - if (hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Select the HASH algorithm, clear HMAC mode and long key selection bit, reset the HASH processor core */ - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, Algorithm | HASH_CR_INIT); - - /* Set the phase */ - hhash->Phase = HAL_HASH_PHASE_PROCESS; - } - - /* Configure the Number of valid bits in last word of the message */ - __HAL_HASH_SET_NBVALIDBITS(Size); - - inputaddr = (uint32_t)pInBuffer; /* DMA transfer start address */ - inputSize = Size; /* DMA transfer size (in bytes) */ - - /* In case of suspension request, save the starting parameters */ - hhash->pHashInBuffPtr = pInBuffer; /* DMA transfer start address */ - hhash->HashInCount = Size; /* DMA transfer size (in bytes) */ - - } - /* If resumption case */ - else - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Resumption case, inputaddr and inputSize are not set to the API input parameters - but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the - processing was suspended */ - inputaddr = (uint32_t)hhash->pHashInBuffPtr; /* DMA transfer start address */ - inputSize = hhash->HashInCount; /* DMA transfer size (in bytes) */ - - } - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASH_DMAError; - - /* Store number of words already pushed to manage proper DMA processing suspension */ - hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - - /* Enable the DMA In DMA stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ - (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) : \ - (inputSize / 4U))); - - /* Enable DMA requests */ - SET_BIT(HASH->CR, HASH_CR_DMAE); - - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - if (status != HAL_OK) - { - /* Update HASH state machine to error */ - hhash->State = HAL_HASH_STATE_ERROR; - } - - return status; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Return the computed digest. - * @note The API waits for DCIS to be set then reads the computed digest. - * @param hhash HASH handle. - * @param pOutBuffer pointer to the computed digest. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) -{ - - if (hhash->State == HAL_HASH_STATE_READY) - { - /* Check parameter */ - if (pOutBuffer == NULL) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state to busy */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Wait for DCIS flag to be set */ - if (HASH_WaitOnFlagUntilTimeout(hhash, HASH_FLAG_DCIS, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Read the message digest */ - HASH_GetDigest(pOutBuffer, HASH_DIGEST_LENGTH()); - - /* Change the HASH state to ready */ - hhash->State = HAL_HASH_STATE_READY; - - /* Reset HASH state machine */ - hhash->Phase = HAL_HASH_PHASE_READY; - - /* Process UnLock */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - return HAL_OK; - - } - else - { - return HAL_BUSY; - } - -} - - -/** - * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. - * @param Timeout Timeout value. - * @param Algorithm HASH algorithm. - * @retval HAL status - */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Timeout, uint32_t Algorithm) -{ - HAL_HASH_StateTypeDef State_tmp = hhash->State; - - /* If State is ready or suspended, start or resume polling-based HASH processing */ - if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) - { - /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) - || (pOutBuffer == NULL)) - { - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Check if initialization phase has already be performed */ - if (hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if (hhash->Init.KeySize > 64U) - { - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, - Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, - Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - /* Set the phase to Step 1 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - /* Resort to hhash internal fields to feed the Peripheral. - Parameters will be updated in case of suspension to contain the proper - information at resumption time. */ - hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ - hhash->pHashInBuffPtr = pInBuffer; /* Input data address, HMAC_Processing input - parameter for Step 2 */ - hhash->HashInCount = Size; /* Input data size, HMAC_Processing input - parameter for Step 2 */ - hhash->HashBuffSize = Size; /* Store the input buffer size for the whole HMAC process*/ - hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address, HMAC_Processing input parameter for Step - 1 and Step 3 */ - hhash->HashKeyCount = hhash->Init.KeySize; /* Key size, HMAC_Processing input parameter for Step 1 - and Step 3 */ - } - - /* Carry out HMAC processing */ - return HMAC_Processing(hhash, Timeout); - - } - else - { - return HAL_BUSY; - } -} - - - -/** - * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then - * read the computed digest in interruption mode. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. - * @param Algorithm HASH algorithm. - * @retval HAL status - */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, - uint32_t Algorithm) -{ - HAL_HASH_StateTypeDef State_tmp = hhash->State; - - /* If State is ready or suspended, start or resume IT-based HASH processing */ - if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) - { - /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) - || (pOutBuffer == NULL)) - { - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Initialize IT counter */ - hhash->HashITCounter = 1; - - /* Check if initialization phase has already be performed */ - if (hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits */ - if (hhash->Init.KeySize > 64U) - { - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, - Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - MODIFY_REG(HASH->CR, HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, - Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - - /* Resort to hhash internal fields hhash->pHashInBuffPtr and hhash->HashInCount - to feed the Peripheral whatever the HMAC step. - Lines below are set to start HMAC Step 1 processing where key is entered first. */ - hhash->HashInCount = hhash->Init.KeySize; /* Key size */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* Key address */ - - /* Store input and output parameters in handle fields to manage steps transition - or possible HMAC suspension/resumption */ - hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ - hhash->pHashMsgBuffPtr = pInBuffer; /* Input message address */ - hhash->HashBuffSize = Size; /* Input message size (in bytes) */ - hhash->pHashOutBuffPtr = pOutBuffer; /* Output digest address */ - - /* Configure the number of valid bits in last word of the key */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Set the phase to Step 1 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - } - else if ((hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_3)) - { - /* Restart IT-based HASH processing after Step 1 or Step 3 suspension */ - - } - else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) - { - /* Restart IT-based HASH processing after Step 2 suspension */ - - } - else - { - /* Error report as phase incorrect */ - /* Process Unlock */ - __HAL_UNLOCK(hhash); - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - /* Process Unlock */ - __HAL_UNLOCK(hhash); - - /* Enable Interrupts */ - __HAL_HASH_ENABLE_IT(HASH_IT_DINI | HASH_IT_DCI); - - /* Return function status */ - return HAL_OK; - } - else - { - return HAL_BUSY; - } - -} - - - -/** - * @brief Initialize the HASH peripheral in HMAC mode then initiate the required - * DMA transfers to feed the key and the input buffer to the Peripheral. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note In case of multi-buffer HMAC processing, the input buffer size (in bytes) must - * be a multiple of 4 otherwise, the HASH digest computation is corrupted. - * Only the length of the last buffer of the thread doesn't have to be a - * multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param Algorithm HASH algorithm. - * @retval HAL status - */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) -{ - uint32_t inputaddr; - uint32_t inputSize; - HAL_StatusTypeDef status ; - HAL_HASH_StateTypeDef State_tmp = hhash->State; - /* Make sure the input buffer size (in bytes) is a multiple of 4 when digest calculation - is disabled (multi-buffer HMAC processing, MDMAT bit to be set) */ - assert_param(IS_HMAC_DMA_MULTIBUFFER_SIZE(hhash, Size)); - /* If State is ready or suspended, start or resume DMA-based HASH processing */ - if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) - { - /* Check input parameters */ - if ((pInBuffer == NULL) || (Size == 0U) || (hhash->Init.pKey == NULL) || (hhash->Init.KeySize == 0U) || - /* Check phase coherency. Phase must be - either READY (fresh start) - or one of HMAC PROCESS steps (multi-buffer HASH management) */ - ((hhash->Phase != HAL_HASH_PHASE_READY) && (!(IS_HMAC_PROCESSING(hhash))))) - { - hhash->State = HAL_HASH_STATE_READY; - return HAL_ERROR; - } - - - /* Process Locked */ - __HAL_LOCK(hhash); - - /* If not a case of resumption after suspension */ - if (hhash->State == HAL_HASH_STATE_READY) - { - /* Check whether or not initialization phase has already be performed */ - if (hhash->Phase == HAL_HASH_PHASE_READY) - { - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - /* Check if key size is larger than 64 bytes, accordingly set LKEY and the other setting bits. - At the same time, ensure MDMAT bit is cleared. */ - if (hhash->Init.KeySize > 64U) - { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, - Algorithm | HASH_ALGOMODE_HMAC | HASH_HMAC_KEYTYPE_LONGKEY | HASH_CR_INIT); - } - else - { - MODIFY_REG(HASH->CR, HASH_CR_MDMAT | HASH_CR_LKEY | HASH_CR_ALGO | HASH_CR_MODE | HASH_CR_INIT, - Algorithm | HASH_ALGOMODE_HMAC | HASH_CR_INIT); - } - /* Store input aparameters in handle fields to manage steps transition - or possible HMAC suspension/resumption */ - hhash->HashInCount = hhash->Init.KeySize; /* Initial size for first DMA transfer (key size) */ - hhash->pHashKeyBuffPtr = hhash->Init.pKey; /* Key address */ - hhash->pHashInBuffPtr = hhash->Init.pKey ; /* First address passed to DMA (key address at Step 1) */ - hhash->pHashMsgBuffPtr = pInBuffer; /* Input data address */ - hhash->HashBuffSize = Size; /* input data size (in bytes) */ - - /* Set DMA input parameters */ - inputaddr = (uint32_t)(hhash->Init.pKey); /* Address passed to DMA (start by entering Key message) */ - inputSize = hhash->Init.KeySize; /* Size for first DMA transfer (in bytes) */ - - /* Configure the number of valid bits in last word of the key */ - __HAL_HASH_SET_NBVALIDBITS(hhash->Init.KeySize); - - /* Set the phase to Step 1 */ - hhash->Phase = HAL_HASH_PHASE_HMAC_STEP_1; - - } - else if (hhash->Phase == HAL_HASH_PHASE_HMAC_STEP_2) - { - /* Process a new input data message in case of multi-buffer HMAC processing - (this is not a resumption case) */ - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Save input parameters to be able to manage possible suspension/resumption */ - hhash->HashInCount = Size; /* Input message address */ - hhash->pHashInBuffPtr = pInBuffer; /* Input message size in bytes */ - - /* Set DMA input parameters */ - inputaddr = (uint32_t)pInBuffer; /* Input message address */ - inputSize = Size; /* Input message size in bytes */ - - if (hhash->DigestCalculationDisable == RESET) - { - /* This means this is the last buffer of the multi-buffer sequence: DCAL needs to be set. */ - __HAL_HASH_RESET_MDMAT(); - __HAL_HASH_SET_NBVALIDBITS(inputSize); - } - } - else - { - /* Phase not aligned with handle READY state */ - __HAL_UNLOCK(hhash); - /* Return function status */ - return HAL_ERROR; - } - } - else - { - /* Resumption case (phase may be Step 1, 2 or 3) */ - - /* Change the HASH state */ - hhash->State = HAL_HASH_STATE_BUSY; - - /* Set DMA input parameters at resumption location; - inputaddr and inputSize are not set to the API input parameters - but to those saved beforehand by HAL_HASH_DMAFeed_ProcessSuspend() when the - processing was suspended. */ - inputaddr = (uint32_t)(hhash->pHashInBuffPtr); /* Input message address */ - inputSize = hhash->HashInCount; /* Input message size in bytes */ - } - - - /* Set the HASH DMA transfer complete callback */ - hhash->hdmain->XferCpltCallback = HASH_DMAXferCplt; - /* Set the DMA error callback */ - hhash->hdmain->XferErrorCallback = HASH_DMAError; - - /* Store number of words already pushed to manage proper DMA processing suspension */ - hhash->NbWordsAlreadyPushed = HASH_NBW_PUSHED(); - - /* Enable the DMA In DMA stream */ - status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ - (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \ - : (inputSize / 4U))); - - /* Enable DMA requests */ - SET_BIT(HASH->CR, HASH_CR_DMAE); - - /* Process Unlocked */ - __HAL_UNLOCK(hhash); - - /* Return function status */ - if (status != HAL_OK) - { - /* Update HASH state machine to error */ - hhash->State = HAL_HASH_STATE_ERROR; - } - - /* Return function status */ - return status; - } - else - { - return HAL_BUSY; - } -} -/** - * @} - */ - -#endif /* HAL_HASH_MODULE_ENABLED */ - -/** - * @} - */ -#endif /* HASH*/ -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c deleted file mode 100644 index 16a5b2cb..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hash_ex.c +++ /dev/null @@ -1,1040 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hash_ex.c - * @author MCD Application Team - * @brief Extended HASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the HASH peripheral for SHA-224 and SHA-256 - * algorithms: - * + HASH or HMAC processing in polling mode - * + HASH or HMAC processing in interrupt mode - * + HASH or HMAC processing in DMA mode - * Additionally, this file provides functions to manage HMAC - * multi-buffer DMA-based processing for MD-5, SHA-1, SHA-224 - * and SHA-256. - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### HASH peripheral extended features ##### - =============================================================================== - [..] - The SHA-224 and SHA-256 HASH and HMAC processing can be carried out exactly - the same way as for SHA-1 or MD-5 algorithms. - (#) Three modes are available. - (##) Polling mode: processing APIs are blocking functions - i.e. they process the data and wait till the digest computation is finished, - e.g. HAL_HASHEx_xxx_Start() - (##) Interrupt mode: processing APIs are not blocking functions - i.e. they process the data under interrupt, - e.g. HAL_HASHEx_xxx_Start_IT() - (##) DMA mode: processing APIs are not blocking functions and the CPU is - not used for data transfer i.e. the data transfer is ensured by DMA, - e.g. HAL_HASHEx_xxx_Start_DMA(). Note that in DMA mode, a call to - HAL_HASHEx_xxx_Finish() is then required to retrieve the digest. - - (#)Multi-buffer processing is possible in polling, interrupt and DMA modes. - (##) In polling mode, only multi-buffer HASH processing is possible. - API HAL_HASHEx_xxx_Accumulate() must be called for each input buffer, except for the last one. - User must resort to HAL_HASHEx_xxx_Accumulate_End() to enter the last one and retrieve as - well the computed digest. - - (##) In interrupt mode, API HAL_HASHEx_xxx_Accumulate_IT() must be called for each input buffer, - except for the last one. - User must resort to HAL_HASHEx_xxx_Accumulate_End_IT() to enter the last one and retrieve as - well the computed digest. - - (##) In DMA mode, multi-buffer HASH and HMAC processing are possible. - - (+++) HASH processing: once initialization is done, MDMAT bit must be set through - __HAL_HASH_SET_MDMAT() macro. - From that point, each buffer can be fed to the Peripheral through HAL_HASHEx_xxx_Start_DMA() API. - Before entering the last buffer, reset the MDMAT bit with __HAL_HASH_RESET_MDMAT() - macro then wrap-up the HASH processing in feeding the last input buffer through the - same API HAL_HASHEx_xxx_Start_DMA(). The digest can then be retrieved with a call to - API HAL_HASHEx_xxx_Finish(). - - (+++) HMAC processing (MD-5, SHA-1, SHA-224 and SHA-256 must all resort to - extended functions): after initialization, the key and the first input buffer are entered - in the Peripheral with the API HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and - starts step 2. - The following buffers are next entered with the API HAL_HMACEx_xxx_Step2_DMA(). At this - point, the HMAC processing is still carrying out step 2. - Then, step 2 for the last input buffer and step 3 are carried out by a single call - to HAL_HMACEx_xxx_Step2_3_DMA(). - - The digest can finally be retrieved with a call to API HAL_HASH_xxx_Finish() for - MD-5 and SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 and SHA-256. - - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - - - - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined (HASH) - -/** @defgroup HASHEx HASHEx - * @brief HASH HAL extended module driver. - * @{ - */ -#ifdef HAL_HASH_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - -/** @defgroup HASHEx_Exported_Functions HASH Extended Exported Functions - * @{ - */ - -/** @defgroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode - * @brief HASH extended processing functions using polling mode. - * -@verbatim - =============================================================================== - ##### Polling mode HASH extended processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in polling mode - the hash value using one of the following algorithms: - (+) SHA224 - (++) HAL_HASHEx_SHA224_Start() - (++) HAL_HASHEx_SHA224_Accmlt() - (++) HAL_HASHEx_SHA224_Accmlt_End() - (+) SHA256 - (++) HAL_HASHEx_SHA256_Start() - (++) HAL_HASHEx_SHA256_Accmlt() - (++) HAL_HASHEx_SHA256_Accmlt_End() - - [..] For a single buffer to be hashed, user can resort to HAL_HASH_xxx_Start(). - - [..] In case of multi-buffer HASH processing (a single digest is computed while - several buffers are fed to the Peripheral), the user can resort to successive calls - to HAL_HASHEx_xxx_Accumulate() and wrap-up the digest computation by a call - to HAL_HASHEx_xxx_Accumulate_End(). - -@endverbatim - * @{ - */ - - -/** - * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief If not already done, initialize the HASH peripheral in SHA224 mode then - * processes pInBuffer. - * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt() can be used to feed - * several input buffers back-to-back to the Peripheral that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA224_Accmlt_End(). - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA224_Accmlt_End() - * to read it, feeding at the same time the last input buffer to the Peripheral. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt() API. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); -} - -/** - * @brief If not already done, initialize the HASH peripheral in SHA256 mode then - * processes pInBuffer. - * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt() can be used to feed - * several input buffers back-to-back to the Peripheral that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA256_Accmlt_End(). - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note Digest is not retrieved by this API, user must resort to HAL_HASHEx_SHA256_Accmlt_End() - * to read it, feeding at the same time the last input buffer to the Peripheral. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); -} - -/** - * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt() API. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); -} - -/** - * @} - */ - -/** @defgroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode - * @brief HASH extended processing functions using interrupt mode. - * -@verbatim - =============================================================================== - ##### Interruption mode HASH extended processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in interrupt mode - the hash value using one of the following algorithms: - (+) SHA224 - (++) HAL_HASHEx_SHA224_Start_IT() - (++) HAL_HASHEx_SHA224_Accmlt_IT() - (++) HAL_HASHEx_SHA224_Accmlt_End_IT() - (+) SHA256 - (++) HAL_HASHEx_SHA256_Start_IT() - (++) HAL_HASHEx_SHA256_Accmlt_IT() - (++) HAL_HASHEx_SHA256_Accmlt_End_IT() - -@endverbatim - * @{ - */ - - -/** - * @brief Initialize the HASH peripheral in SHA224 mode, next process pInBuffer then - * read the computed digest in interruption mode. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief If not already done, initialize the HASH peripheral in SHA224 mode then - * processes pInBuffer in interruption mode. - * @note Consecutive calls to HAL_HASHEx_SHA224_Accmlt_IT() can be used to feed - * several input buffers back-to-back to the Peripheral that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA224_Accmlt_End_IT(). - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASHEx_SHA224_Accmlt_End_IT() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA224_Accmlt_IT() API. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief Initialize the HASH peripheral in SHA256 mode, next process pInBuffer then - * read the computed digest in interruption mode. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); -} - -/** - * @brief If not already done, initialize the HASH peripheral in SHA256 mode then - * processes pInBuffer in interruption mode. - * @note Consecutive calls to HAL_HASHEx_SHA256_Accmlt_IT() can be used to feed - * several input buffers back-to-back to the Peripheral that will yield a single - * HASH signature once all buffers have been entered. Wrap-up of input - * buffers feeding and retrieval of digest is done by a call to - * HAL_HASHEx_SHA256_Accmlt_End_IT(). - * @note Field hhash->Phase of HASH handle is tested to check whether or not - * the Peripheral has already been initialized. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. Only HAL_HASHEx_SHA256_Accmlt_End_IT() is able - * to manage the ending buffer with a length in bytes not a multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes, must be a multiple of 4. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); -} - -/** - * @brief End computation of a single HASH signature after several calls to HAL_HASHEx_SHA256_Accmlt_IT() API. - * @note Digest is available in pOutBuffer. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); -} - -/** - * @} - */ - -/** @defgroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode - * @brief HASH extended processing functions using DMA mode. - * -@verbatim - =============================================================================== - ##### DMA mode HASH extended processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in DMA mode - the hash value using one of the following algorithms: - (+) SHA224 - (++) HAL_HASHEx_SHA224_Start_DMA() - (++) HAL_HASHEx_SHA224_Finish() - (+) SHA256 - (++) HAL_HASHEx_SHA256_Start_DMA() - (++) HAL_HASHEx_SHA256_Finish() - - [..] When resorting to DMA mode to enter the data in the Peripheral, user must resort - to HAL_HASHEx_xxx_Start_DMA() then read the resulting digest with - HAL_HASHEx_xxx_Finish(). - - [..] In case of multi-buffer HASH processing, MDMAT bit must first be set before - the successive calls to HAL_HASHEx_xxx_Start_DMA(). Then, MDMAT bit needs to be - reset before the last call to HAL_HASHEx_xxx_Start_DMA(). Digest is finally - retrieved thanks to HAL_HASHEx_xxx_Finish(). - -@endverbatim - * @{ - */ - - - - -/** - * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer - * to feed the input buffer to the Peripheral. - * @note Once the DMA transfer is finished, HAL_HASHEx_SHA224_Finish() API must - * be called to retrieve the computed digest. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief Return the computed digest in SHA224 mode. - * @note The API waits for DCIS to be set then reads the computed digest. - * @note HAL_HASHEx_SHA224_Finish() can be used as well to retrieve the digest in - * HMAC SHA224 mode. - * @param hhash HASH handle. - * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); -} - -/** - * @brief Initialize the HASH peripheral in SHA256 mode then initiate a DMA transfer - * to feed the input buffer to the Peripheral. - * @note Once the DMA transfer is finished, HAL_HASHEx_SHA256_Finish() API must - * be called to retrieve the computed digest. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); -} - -/** - * @brief Return the computed digest in SHA256 mode. - * @note The API waits for DCIS to be set then reads the computed digest. - * @note HAL_HASHEx_SHA256_Finish() can be used as well to retrieve the digest in - * HMAC SHA256 mode. - * @param hhash HASH handle. - * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HASH_Finish(hhash, pOutBuffer, Timeout); -} - -/** - * @} - */ - -/** @defgroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode - * @brief HMAC extended processing functions using polling mode. - * -@verbatim - =============================================================================== - ##### Polling mode HMAC extended processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in polling mode - the HMAC value using one of the following algorithms: - (+) SHA224 - (++) HAL_HMACEx_SHA224_Start() - (+) SHA256 - (++) HAL_HMACEx_SHA256_Start() - -@endverbatim - * @{ - */ - - - -/** - * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then - * read the computed digest. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. - * @param Timeout Timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer, uint32_t Timeout) -{ - return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); -} - -/** - * @} - */ - - -/** @defgroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode - * @brief HMAC extended processing functions using interruption mode. - * -@verbatim - =============================================================================== - ##### Interrupt mode HMAC extended processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in interrupt mode - the HMAC value using one of the following algorithms: - (+) SHA224 - (++) HAL_HMACEx_SHA224_Start_IT() - (+) SHA256 - (++) HAL_HMACEx_SHA256_Start_IT() - -@endverbatim - * @{ - */ - - - -/** - * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then - * read the computed digest in interrupt mode. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief Initialize the HASH peripheral in HMAC SHA256 mode, next process pInBuffer then - * read the computed digest in interrupt mode. - * @note Digest is available in pOutBuffer. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, - uint8_t *pOutBuffer) -{ - return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); -} - - - - -/** - * @} - */ - - -/** @defgroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions using DMA mode. - * -@verbatim - =============================================================================== - ##### DMA mode HMAC extended processing functions ##### - =============================================================================== - [..] This section provides functions allowing to calculate in DMA mode - the HMAC value using one of the following algorithms: - (+) SHA224 - (++) HAL_HMACEx_SHA224_Start_DMA() - (+) SHA256 - (++) HAL_HMACEx_SHA256_Start_DMA() - - [..] When resorting to DMA mode to enter the data in the Peripheral for HMAC processing, - user must resort to HAL_HMACEx_xxx_Start_DMA() then read the resulting digest - with HAL_HASHEx_xxx_Finish(). - - -@endverbatim - * @{ - */ - - - -/** - * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the Peripheral. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA224_Finish() API must be called to retrieve - * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be - * a multiple of 4 otherwise, the HASH digest computation is corrupted. - * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required - * DMA transfers to feed the key and the input buffer to the Peripheral. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note If MDMAT bit is set before calling this function (multi-buffer - * HASH processing case), the input buffer size (in bytes) must be - * a multiple of 4 otherwise, the HASH digest computation is corrupted. - * For the processing of the last buffer of the thread, MDMAT bit must - * be reset and the buffer length (in bytes) doesn't have to be a - * multiple of 4. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (buffer to be hashed). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); -} - - -/** - * @} - */ - -/** @defgroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode - * @brief HMAC extended processing functions in multi-buffer DMA mode. - * -@verbatim - =============================================================================== - ##### Multi-buffer DMA mode HMAC extended processing functions ##### - =============================================================================== - [..] This section provides functions to manage HMAC multi-buffer - DMA-based processing for MD5, SHA1, SHA224 and SHA256 algorithms. - (+) MD5 - (++) HAL_HMACEx_MD5_Step1_2_DMA() - (++) HAL_HMACEx_MD5_Step2_DMA() - (++) HAL_HMACEx_MD5_Step2_3_DMA() - (+) SHA1 - (++) HAL_HMACEx_SHA1_Step1_2_DMA() - (++) HAL_HMACEx_SHA1_Step2_DMA() - (++) HAL_HMACEx_SHA1_Step2_3_DMA() - - (+) SHA256 - (++) HAL_HMACEx_SHA224_Step1_2_DMA() - (++) HAL_HMACEx_SHA224_Step2_DMA() - (++) HAL_HMACEx_SHA224_Step2_3_DMA() - (+) SHA256 - (++) HAL_HMACEx_SHA256_Step1_2_DMA() - (++) HAL_HMACEx_SHA256_Step2_DMA() - (++) HAL_HMACEx_SHA256_Step2_3_DMA() - - [..] User must first start-up the multi-buffer DMA-based HMAC computation in - calling HAL_HMACEx_xxx_Step1_2_DMA(). This carries out HMAC step 1 and - intiates step 2 with the first input buffer. - - [..] The following buffers are next fed to the Peripheral with a call to the API - HAL_HMACEx_xxx_Step2_DMA(). There may be several consecutive calls - to this API. - - [..] Multi-buffer DMA-based HMAC computation is wrapped up by a call to - HAL_HMACEx_xxx_Step2_3_DMA(). This finishes step 2 in feeding the last input - buffer to the Peripheral then carries out step 3. - - [..] Digest is retrieved by a call to HAL_HASH_xxx_Finish() for MD-5 or - SHA-1, to HAL_HASHEx_xxx_Finish() for SHA-224 or SHA-256. - - [..] If only two buffers need to be consecutively processed, a call to - HAL_HMACEx_xxx_Step1_2_DMA() followed by a call to HAL_HMACEx_xxx_Step2_3_DMA() - is sufficient. - -@endverbatim - * @{ - */ - -/** - * @brief MD5 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the Peripheral, - * step 2 consists in writing the message text. - * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the Peripheral. DCAL bit is not automatically set after - * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - hhash->DigestCalculationDisable = SET; - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief MD5 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the Peripheral. - * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, - * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - if (hhash->DigestCalculationDisable != SET) - { - return HAL_ERROR; - } - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); -} - -/** - * @brief MD5 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the Peripheral, - * step 3 consists in writing the outer hash function key. - * @note The API wraps up the HMAC step 2 in processing the buffer entered as input - * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - hhash->DigestCalculationDisable = RESET; - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); -} - - -/** - * @brief SHA1 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the Peripheral, - * step 2 consists in writing the message text. - * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the Peripheral. DCAL bit is not automatically set after - * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - hhash->DigestCalculationDisable = SET; - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); -} - -/** - * @brief SHA1 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the Peripheral. - * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, - * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - if (hhash->DigestCalculationDisable != SET) - { - return HAL_ERROR; - } - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); -} - -/** - * @brief SHA1 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the Peripheral, - * step 3 consists in writing the outer hash function key. - * @note The API wraps up the HMAC step 2 in processing the buffer entered as input - * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - hhash->DigestCalculationDisable = RESET; - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); -} - -/** - * @brief SHA224 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the Peripheral, - * step 2 consists in writing the message text. - * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the Peripheral. DCAL bit is not automatically set after - * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - hhash->DigestCalculationDisable = SET; - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief SHA224 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the Peripheral. - * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, - * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - if (hhash->DigestCalculationDisable != SET) - { - return HAL_ERROR; - } - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief SHA224 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the Peripheral, - * step 3 consists in writing the outer hash function key. - * @note The API wraps up the HMAC step 2 in processing the buffer entered as input - * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - hhash->DigestCalculationDisable = RESET; - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); -} - -/** - * @brief SHA256 HMAC step 1 completion and step 2 start in multi-buffer DMA mode. - * @note Step 1 consists in writing the inner hash function key in the Peripheral, - * step 2 consists in writing the message text. - * @note The API carries out the HMAC step 1 then starts step 2 with - * the first buffer entered to the Peripheral. DCAL bit is not automatically set after - * the message buffer feeding, allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - hhash->DigestCalculationDisable = SET; - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); -} - -/** - * @brief SHA256 HMAC step 2 in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the Peripheral. - * @note The API carries on the HMAC step 2, applied to the buffer entered as input - * parameter. DCAL bit is not automatically set after the message buffer feeding, - * allowing other messages DMA transfers to occur. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note The input buffer size (in bytes) must be a multiple of 4 otherwise, the - * HASH digest computation is corrupted. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - if (hhash->DigestCalculationDisable != SET) - { - return HAL_ERROR; - } - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); -} - -/** - * @brief SHA256 HMAC step 2 wrap-up and step 3 completion in multi-buffer DMA mode. - * @note Step 2 consists in writing the message text in the Peripheral, - * step 3 consists in writing the outer hash function key. - * @note The API wraps up the HMAC step 2 in processing the buffer entered as input - * parameter (the input buffer must be the last one of the multi-buffer thread) - * then carries out HMAC step 3. - * @note Same key is used for the inner and the outer hash functions; pointer to key and - * key size are respectively stored in hhash->Init.pKey and hhash->Init.KeySize. - * @note Once the DMA transfers are finished (indicated by hhash->State set back - * to HAL_HASH_STATE_READY), HAL_HASHEx_SHA256_Finish() API must be called to retrieve - * the computed digest. - * @param hhash HASH handle. - * @param pInBuffer pointer to the input buffer (message buffer). - * @param Size length of the input buffer in bytes. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) -{ - hhash->DigestCalculationDisable = RESET; - return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); -} - -/** - * @} - */ - - -/** - * @} - */ -#endif /* HAL_HASH_MODULE_ENABLED */ - -/** - * @} - */ -#endif /* HASH*/ -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c deleted file mode 100644 index 10ba0165..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_hcd.c +++ /dev/null @@ -1,1997 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_hcd.c - * @author MCD Application Team - * @brief HCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#)Declare a HCD_HandleTypeDef handle structure, for example: - HCD_HandleTypeDef hhcd; - - (#)Fill parameters of Init structure in HCD handle - - (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...) - - (#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API: - (##) Enable the HCD/USB Low Level interface clock using the following macros - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) - (+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode) - - (##) Initialize the related GPIO clocks - (##) Configure HCD pin-out - (##) Configure HCD NVIC interrupt - - (#)Associate the Upper USB Host stack to the HAL HCD Driver: - (##) hhcd.pData = phost; - - (#)Enable HCD transmission and reception: - (##) HAL_HCD_Start(); - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_HCD_MODULE_ENABLED -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - -/** @defgroup HCD HCD - * @brief HCD HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup HCD_Private_Functions HCD Private Functions - * @{ - */ -static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); -static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum); -static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd); -static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup HCD_Exported_Functions HCD Exported Functions - * @{ - */ - -/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the host driver. - * @param hhcd HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd) -{ -#if defined (USB_OTG_FS) - const USB_OTG_GlobalTypeDef *USBx; -#endif /* defined (USB_OTG_FS) */ - - /* Check the HCD handle allocation */ - if (hhcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance)); - -#if defined (USB_OTG_FS) - USBx = hhcd->Instance; -#endif /* defined (USB_OTG_FS) */ - - if (hhcd->State == HAL_HCD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hhcd->Lock = HAL_UNLOCKED; - -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->SOFCallback = HAL_HCD_SOF_Callback; - hhcd->ConnectCallback = HAL_HCD_Connect_Callback; - hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; - hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; - hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; - hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; - - if (hhcd->MspInitCallback == NULL) - { - hhcd->MspInitCallback = HAL_HCD_MspInit; - } - - /* Init the low level hardware */ - hhcd->MspInitCallback(hhcd); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_HCD_MspInit(hhcd); -#endif /* (USE_HAL_HCD_REGISTER_CALLBACKS) */ - } - - hhcd->State = HAL_HCD_STATE_BUSY; - -#if defined (USB_OTG_FS) - /* Disable DMA mode for FS instance */ - if (USBx == USB_OTG_FS) - { - hhcd->Init.dma_enable = 0U; - } -#endif /* defined (USB_OTG_FS) */ - - /* Disable the Interrupts */ - __HAL_HCD_DISABLE(hhcd); - - /* Init the Core (common init.) */ - if (USB_CoreInit(hhcd->Instance, hhcd->Init) != HAL_OK) - { - hhcd->State = HAL_HCD_STATE_ERROR; - return HAL_ERROR; - } - - /* Force Host Mode */ - if (USB_SetCurrentMode(hhcd->Instance, USB_HOST_MODE) != HAL_OK) - { - hhcd->State = HAL_HCD_STATE_ERROR; - return HAL_ERROR; - } - - /* Init Host */ - if (USB_HostInit(hhcd->Instance, hhcd->Init) != HAL_OK) - { - hhcd->State = HAL_HCD_STATE_ERROR; - return HAL_ERROR; - } - - hhcd->State = HAL_HCD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initialize a host channel. - * @param hhcd HCD handle - * @param ch_num Channel number. - * This parameter can be a value from 1 to 15 - * @param epnum Endpoint number. - * This parameter can be a value from 1 to 15 - * @param dev_address Current device address - * This parameter can be a value from 0 to 255 - * @param speed Current device speed. - * This parameter can be one of these values: - * HCD_DEVICE_SPEED_HIGH: High speed mode, - * HCD_DEVICE_SPEED_FULL: Full speed mode, - * HCD_DEVICE_SPEED_LOW: Low speed mode - * @param ep_type Endpoint Type. - * This parameter can be one of these values: - * EP_TYPE_CTRL: Control type, - * EP_TYPE_ISOC: Isochronous type, - * EP_TYPE_BULK: Bulk type, - * EP_TYPE_INTR: Interrupt type - * @param mps Max Packet Size. - * This parameter can be a value from 0 to32K - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t epnum, - uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps) -{ - HAL_StatusTypeDef status; - uint32_t HostCoreSpeed; - uint32_t HCcharMps = mps; - - __HAL_LOCK(hhcd); - hhcd->hc[ch_num].do_ping = 0U; - hhcd->hc[ch_num].dev_addr = dev_address; - hhcd->hc[ch_num].ch_num = ch_num; - hhcd->hc[ch_num].ep_type = ep_type; - hhcd->hc[ch_num].ep_num = epnum & 0x7FU; - - (void)HAL_HCD_HC_ClearHubInfo(hhcd, ch_num); - - if ((epnum & 0x80U) == 0x80U) - { - hhcd->hc[ch_num].ep_is_in = 1U; - } - else - { - hhcd->hc[ch_num].ep_is_in = 0U; - } - - HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); - - if (ep_type == EP_TYPE_ISOC) - { - /* FS device plugged to HS HUB */ - if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) - { - if (HCcharMps > ISO_SPLT_MPS) - { - /* ISO Max Packet Size for Split mode */ - HCcharMps = ISO_SPLT_MPS; - } - } - } - - hhcd->hc[ch_num].speed = speed; - hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps; - - status = USB_HC_Init(hhcd->Instance, ch_num, epnum, - dev_address, speed, ep_type, (uint16_t)HCcharMps); - - __HAL_UNLOCK(hhcd); - - return status; -} - -/** - * @brief Halt a host channel. - * @param hhcd HCD handle - * @param ch_num Channel number. - * This parameter can be a value from 1 to 15 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num) -{ - HAL_StatusTypeDef status = HAL_OK; - - __HAL_LOCK(hhcd); - (void)USB_HC_Halt(hhcd->Instance, ch_num); - __HAL_UNLOCK(hhcd); - - return status; -} - -/** - * @brief DeInitialize the host driver. - * @param hhcd HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd) -{ - /* Check the HCD handle allocation */ - if (hhcd == NULL) - { - return HAL_ERROR; - } - - hhcd->State = HAL_HCD_STATE_BUSY; - -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - if (hhcd->MspDeInitCallback == NULL) - { - hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hhcd->MspDeInitCallback(hhcd); -#else - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_HCD_MspDeInit(hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - __HAL_HCD_DISABLE(hhcd); - - hhcd->State = HAL_HCD_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initialize the HCD MSP. - * @param hhcd HCD handle - * @retval None - */ -__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HCD_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the HCD MSP. - * @param hhcd HCD handle - * @retval None - */ -__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HCD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions - * @brief HCD IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USB Host Data - Transfer - -@endverbatim - * @{ - */ - -/** - * @brief Submit a new URB for processing. - * @param hhcd HCD handle - * @param ch_num Channel number. - * This parameter can be a value from 1 to 15 - * @param direction Channel number. - * This parameter can be one of these values: - * 0 : Output / 1 : Input - * @param ep_type Endpoint Type. - * This parameter can be one of these values: - * EP_TYPE_CTRL: Control type/ - * EP_TYPE_ISOC: Isochronous type/ - * EP_TYPE_BULK: Bulk type/ - * EP_TYPE_INTR: Interrupt type/ - * @param token Endpoint Type. - * This parameter can be one of these values: - * 0: HC_PID_SETUP / 1: HC_PID_DATA1 - * @param pbuff pointer to URB data - * @param length Length of URB data - * @param do_ping activate do ping protocol (for high speed only). - * This parameter can be one of these values: - * 0 : do ping inactive / 1 : do ping active - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd, - uint8_t ch_num, - uint8_t direction, - uint8_t ep_type, - uint8_t token, - uint8_t *pbuff, - uint16_t length, - uint8_t do_ping) -{ - hhcd->hc[ch_num].ep_is_in = direction; - hhcd->hc[ch_num].ep_type = ep_type; - - if (token == 0U) - { - hhcd->hc[ch_num].data_pid = HC_PID_SETUP; - hhcd->hc[ch_num].do_ping = do_ping; - } - else - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - - /* Manage Data Toggle */ - switch (ep_type) - { - case EP_TYPE_CTRL: - if (token == 1U) /* send data */ - { - if (direction == 0U) - { - if (length == 0U) - { - /* For Status OUT stage, Length == 0U, Status Out PID = 1 */ - hhcd->hc[ch_num].toggle_out = 1U; - } - - /* Set the Data Toggle bit as per the Flag */ - if (hhcd->hc[ch_num].toggle_out == 0U) - { - /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - else - { - if (hhcd->hc[ch_num].do_ssplit == 1U) - { - if (hhcd->hc[ch_num].toggle_in == 0U) - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - } - } - break; - - case EP_TYPE_BULK: - if (direction == 0U) - { - /* Set the Data Toggle bit as per the Flag */ - if (hhcd->hc[ch_num].toggle_out == 0U) - { - /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - else - { - if (hhcd->hc[ch_num].toggle_in == 0U) - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - - break; - case EP_TYPE_INTR: - if (direction == 0U) - { - /* Set the Data Toggle bit as per the Flag */ - if (hhcd->hc[ch_num].toggle_out == 0U) - { - /* Put the PID 0 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - /* Put the PID 1 */ - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - else - { - if (hhcd->hc[ch_num].toggle_in == 0U) - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - } - else - { - hhcd->hc[ch_num].data_pid = HC_PID_DATA1; - } - } - break; - - case EP_TYPE_ISOC: - hhcd->hc[ch_num].data_pid = HC_PID_DATA0; - break; - - default: - break; - } - - hhcd->hc[ch_num].xfer_buff = pbuff; - hhcd->hc[ch_num].xfer_len = length; - hhcd->hc[ch_num].urb_state = URB_IDLE; - hhcd->hc[ch_num].xfer_count = 0U; - hhcd->hc[ch_num].ch_num = ch_num; - hhcd->hc[ch_num].state = HC_IDLE; - - return USB_HC_StartXfer(hhcd->Instance, &hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); -} - -/** - * @brief Handle HCD interrupt request. - * @param hhcd HCD handle - * @retval None - */ -void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) -{ - USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i; - uint32_t interrupt; - - /* Ensure that we are in device mode */ - if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) - { - /* Avoid spurious interrupt */ - if (__HAL_HCD_IS_INVALID_INTERRUPT(hhcd)) - { - return; - } - - if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) - { - /* Incorrect mode, acknowledge the interrupt */ - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - - if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR)) - { - /* Incorrect mode, acknowledge the interrupt */ - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR); - } - - if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE)) - { - /* Incorrect mode, acknowledge the interrupt */ - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE); - } - - if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS)) - { - /* Incorrect mode, acknowledge the interrupt */ - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS); - } - - /* Handle Host Disconnect Interrupts */ - if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT)) - { - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT); - - if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) - { - /* Flush USB Fifo */ - (void)USB_FlushTxFifo(USBx, 0x10U); - (void)USB_FlushRxFifo(USBx); - - if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) - { - /* Restore FS Clock */ - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); - } - - /* Handle Host Port Disconnect Interrupt */ -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->DisconnectCallback(hhcd); -#else - HAL_HCD_Disconnect_Callback(hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - } - - /* Handle Host Port Interrupts */ - if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT)) - { - HCD_Port_IRQHandler(hhcd); - } - - /* Handle Host SOF Interrupt */ - if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF)) - { -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->SOFCallback(hhcd); -#else - HAL_HCD_SOF_Callback(hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF); - } - - /* Handle Host channel Interrupt */ - if (__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT)) - { - interrupt = USB_HC_ReadInterrupt(hhcd->Instance); - for (i = 0U; i < hhcd->Init.Host_channels; i++) - { - if ((interrupt & (1UL << (i & 0xFU))) != 0U) - { - if ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) - { - HCD_HC_IN_IRQHandler(hhcd, (uint8_t)i); - } - else - { - HCD_HC_OUT_IRQHandler(hhcd, (uint8_t)i); - } - } - } - __HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT); - } - - /* Handle Rx Queue Level Interrupts */ - if ((__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL)) != 0U) - { - USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - HCD_RXQLVL_IRQHandler(hhcd); - - USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - } -} - - -/** - * @brief Handles HCD Wakeup interrupt request. - * @param hhcd HCD handle - * @retval HAL status - */ -void HAL_HCD_WKUP_IRQHandler(HCD_HandleTypeDef *hhcd) -{ - UNUSED(hhcd); -} - - -/** - * @brief SOF callback. - * @param hhcd HCD handle - * @retval None - */ -__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HCD_SOF_Callback could be implemented in the user file - */ -} - -/** - * @brief Connection Event callback. - * @param hhcd HCD handle - * @retval None - */ -__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HCD_Connect_Callback could be implemented in the user file - */ -} - -/** - * @brief Disconnection Event callback. - * @param hhcd HCD handle - * @retval None - */ -__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HCD_Disconnect_Callback could be implemented in the user file - */ -} - -/** - * @brief Port Enabled Event callback. - * @param hhcd HCD handle - * @retval None - */ -__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HCD_Disconnect_Callback could be implemented in the user file - */ -} - -/** - * @brief Port Disabled Event callback. - * @param hhcd HCD handle - * @retval None - */ -__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HCD_Disconnect_Callback could be implemented in the user file - */ -} - -/** - * @brief Notify URB state change callback. - * @param hhcd HCD handle - * @param chnum Channel number. - * This parameter can be a value from 1 to 15 - * @param urb_state: - * This parameter can be one of these values: - * URB_IDLE/ - * URB_DONE/ - * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL/ - * @retval None - */ -__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hhcd); - UNUSED(chnum); - UNUSED(urb_state); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file - */ -} - -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User USB HCD Callback - * To be used instead of the weak predefined callback - * @param hhcd USB HCD handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID - * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID - * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID - * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enable callback ID - * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disable callback ID - * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID - * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, - HAL_HCD_CallbackIDTypeDef CallbackID, - pHCD_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hhcd); - - if (hhcd->State == HAL_HCD_STATE_READY) - { - switch (CallbackID) - { - case HAL_HCD_SOF_CB_ID : - hhcd->SOFCallback = pCallback; - break; - - case HAL_HCD_CONNECT_CB_ID : - hhcd->ConnectCallback = pCallback; - break; - - case HAL_HCD_DISCONNECT_CB_ID : - hhcd->DisconnectCallback = pCallback; - break; - - case HAL_HCD_PORT_ENABLED_CB_ID : - hhcd->PortEnabledCallback = pCallback; - break; - - case HAL_HCD_PORT_DISABLED_CB_ID : - hhcd->PortDisabledCallback = pCallback; - break; - - case HAL_HCD_MSPINIT_CB_ID : - hhcd->MspInitCallback = pCallback; - break; - - case HAL_HCD_MSPDEINIT_CB_ID : - hhcd->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hhcd->State == HAL_HCD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_HCD_MSPINIT_CB_ID : - hhcd->MspInitCallback = pCallback; - break; - - case HAL_HCD_MSPDEINIT_CB_ID : - hhcd->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; -} - -/** - * @brief Unregister an USB HCD Callback - * USB HCD callback is redirected to the weak predefined callback - * @param hhcd USB HCD handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_HCD_SOF_CB_ID USB HCD SOF callback ID - * @arg @ref HAL_HCD_CONNECT_CB_ID USB HCD Connect callback ID - * @arg @ref HAL_HCD_DISCONNECT_CB_ID OTG HCD Disconnect callback ID - * @arg @ref HAL_HCD_PORT_ENABLED_CB_ID USB HCD Port Enabled callback ID - * @arg @ref HAL_HCD_PORT_DISABLED_CB_ID USB HCD Port Disabled callback ID - * @arg @ref HAL_HCD_MSPINIT_CB_ID MspDeInit callback ID - * @arg @ref HAL_HCD_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hhcd); - - /* Setup Legacy weak Callbacks */ - if (hhcd->State == HAL_HCD_STATE_READY) - { - switch (CallbackID) - { - case HAL_HCD_SOF_CB_ID : - hhcd->SOFCallback = HAL_HCD_SOF_Callback; - break; - - case HAL_HCD_CONNECT_CB_ID : - hhcd->ConnectCallback = HAL_HCD_Connect_Callback; - break; - - case HAL_HCD_DISCONNECT_CB_ID : - hhcd->DisconnectCallback = HAL_HCD_Disconnect_Callback; - break; - - case HAL_HCD_PORT_ENABLED_CB_ID : - hhcd->PortEnabledCallback = HAL_HCD_PortEnabled_Callback; - break; - - case HAL_HCD_PORT_DISABLED_CB_ID : - hhcd->PortDisabledCallback = HAL_HCD_PortDisabled_Callback; - break; - - case HAL_HCD_MSPINIT_CB_ID : - hhcd->MspInitCallback = HAL_HCD_MspInit; - break; - - case HAL_HCD_MSPDEINIT_CB_ID : - hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; - break; - - default : - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hhcd->State == HAL_HCD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_HCD_MSPINIT_CB_ID : - hhcd->MspInitCallback = HAL_HCD_MspInit; - break; - - case HAL_HCD_MSPDEINIT_CB_ID : - hhcd->MspDeInitCallback = HAL_HCD_MspDeInit; - break; - - default : - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hhcd); - return status; -} - -/** - * @brief Register USB HCD Host Channel Notify URB Change Callback - * To be used instead of the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback - * @param hhcd HCD handle - * @param pCallback pointer to the USB HCD Host Channel Notify URB Change Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, - pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hhcd); - - if (hhcd->State == HAL_HCD_STATE_READY) - { - hhcd->HC_NotifyURBChangeCallback = pCallback; - } - else - { - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hhcd); - - return status; -} - -/** - * @brief Unregister the USB HCD Host Channel Notify URB Change Callback - * USB HCD Host Channel Notify URB Change Callback is redirected - * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback - * @param hhcd HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hhcd); - - if (hhcd->State == HAL_HCD_STATE_READY) - { - hhcd->HC_NotifyURBChangeCallback = HAL_HCD_HC_NotifyURBChange_Callback; /* Legacy weak DataOutStageCallback */ - } - else - { - /* Update the error code */ - hhcd->ErrorCode |= HAL_HCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hhcd); - - return status; -} -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions - * @brief Management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the HCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start the host driver. - * @param hhcd HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); - /* Enable port power */ - (void)USB_DriveVbus(hhcd->Instance, 1U); - - /* Enable global interrupt */ - __HAL_HCD_ENABLE(hhcd); - __HAL_UNLOCK(hhcd); - - return HAL_OK; -} - -/** - * @brief Stop the host driver. - * @param hhcd HCD handle - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd) -{ - __HAL_LOCK(hhcd); - (void)USB_StopHost(hhcd->Instance); - __HAL_UNLOCK(hhcd); - - return HAL_OK; -} - -/** - * @brief Reset the host port. - * @param hhcd HCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd) -{ - return (USB_ResetPort(hhcd->Instance)); -} - -/** - * @} - */ - -/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the HCD handle state. - * @param hhcd HCD handle - * @retval HAL state - */ -HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef const *hhcd) -{ - return hhcd->State; -} - -/** - * @brief Return URB state for a channel. - * @param hhcd HCD handle - * @param chnum Channel number. - * This parameter can be a value from 1 to 15 - * @retval URB state. - * This parameter can be one of these values: - * URB_IDLE/ - * URB_DONE/ - * URB_NOTREADY/ - * URB_NYET/ - * URB_ERROR/ - * URB_STALL - */ -HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) -{ - return hhcd->hc[chnum].urb_state; -} - - -/** - * @brief Return the last host transfer size. - * @param hhcd HCD handle - * @param chnum Channel number. - * This parameter can be a value from 1 to 15 - * @retval last transfer size in byte - */ -uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef const *hhcd, uint8_t chnum) -{ - return hhcd->hc[chnum].xfer_count; -} - -/** - * @brief Return the Host Channel state. - * @param hhcd HCD handle - * @param chnum Channel number. - * This parameter can be a value from 1 to 15 - * @retval Host channel state - * This parameter can be one of these values: - * HC_IDLE/ - * HC_XFRC/ - * HC_HALTED/ - * HC_NYET/ - * HC_NAK/ - * HC_STALL/ - * HC_XACTERR/ - * HC_BBLERR/ - * HC_DATATGLERR - */ -HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef const *hhcd, uint8_t chnum) -{ - return hhcd->hc[chnum].state; -} - -/** - * @brief Return the current Host frame number. - * @param hhcd HCD handle - * @retval Current Host frame number - */ -uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd) -{ - return (USB_GetCurrentFrame(hhcd->Instance)); -} - -/** - * @brief Return the Host enumeration speed. - * @param hhcd HCD handle - * @retval Enumeration speed - */ -uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd) -{ - return (USB_GetHostSpeed(hhcd->Instance)); -} - -/** - * @brief Set host channel Hub information. - * @param hhcd HCD handle - * @param ch_num Channel number. - * This parameter can be a value from 1 to 15 - * @param addr Hub address - * @param PortNbr Hub port number - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_HC_SetHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num, - uint8_t addr, uint8_t PortNbr) -{ - uint32_t HostCoreSpeed = USB_GetHostSpeed(hhcd->Instance); - - /* LS/FS device plugged to HS HUB */ - if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) - { - hhcd->hc[ch_num].do_ssplit = 1U; - - if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U)) - { - hhcd->hc[ch_num].toggle_in = 1U; - } - } - - hhcd->hc[ch_num].hub_addr = addr; - hhcd->hc[ch_num].hub_port_nbr = PortNbr; - - return HAL_OK; -} - - -/** - * @brief Clear host channel hub information. - * @param hhcd HCD handle - * @param ch_num Channel number. - * This parameter can be a value from 1 to 15 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HCD_HC_ClearHubInfo(HCD_HandleTypeDef *hhcd, uint8_t ch_num) -{ - hhcd->hc[ch_num].do_ssplit = 0U; - hhcd->hc[ch_num].do_csplit = 0U; - hhcd->hc[ch_num].hub_addr = 0U; - hhcd->hc[ch_num].hub_port_nbr = 0U; - - return HAL_OK; -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup HCD_Private_Functions - * @{ - */ -/** - * @brief Handle Host Channel IN interrupt requests. - * @param hhcd HCD handle - * @param chnum Channel number. - * This parameter can be a value from 1 to 15 - * @retval none - */ -static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) -{ - const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - hhcd->hc[chnum].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_BBERR)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_BBERR); - hhcd->hc[chnum].state = HC_BBLERR; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - hhcd->hc[chnum].state = HC_STALL; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - hhcd->hc[chnum].state = HC_DATATGLERR; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); - hhcd->hc[chnum].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else - { - /* ... */ - } - - if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) - { - (void)USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) - { - /* Clear any pending ACK IT */ - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - - if (hhcd->hc[chnum].do_csplit == 1U) - { - hhcd->hc[chnum].do_csplit = 0U; - __HAL_HCD_CLEAR_HC_CSPLT(chnum); - } - - if (hhcd->Init.dma_enable != 0U) - { - hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); - } - - hhcd->hc[chnum].state = HC_XFRC; - hhcd->hc[chnum].ErrCnt = 0U; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - (void)USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - } - else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || - (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) - { - USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - hhcd->hc[chnum].urb_state = URB_DONE; - -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); -#else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - else - { - /* ... */ - } - - if (hhcd->Init.dma_enable == 1U) - { - if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) - { - hhcd->hc[chnum].toggle_in ^= 1U; - } - } - else - { - hhcd->hc[chnum].toggle_in ^= 1U; - } - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - - if (hhcd->hc[chnum].do_ssplit == 1U) - { - hhcd->hc[chnum].do_csplit = 1U; - hhcd->hc[chnum].state = HC_ACK; - - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - - if (hhcd->hc[chnum].state == HC_XFRC) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].urb_state = URB_DONE; - } - else if (hhcd->hc[chnum].state == HC_STALL) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].urb_state = URB_STALL; - } - else if ((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].ErrCnt > 2U) - { - hhcd->hc[chnum].ErrCnt = 0U; - - if (hhcd->hc[chnum].do_ssplit == 1U) - { - hhcd->hc[chnum].do_csplit = 0U; - hhcd->hc[chnum].ep_ss_schedule = 0U; - __HAL_HCD_CLEAR_HC_CSPLT(chnum); - } - - hhcd->hc[chnum].urb_state = URB_ERROR; - } - else - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - } - } - } - else if (hhcd->hc[chnum].state == HC_NYET) - { - hhcd->hc[chnum].state = HC_HALTED; - - if (hhcd->hc[chnum].do_csplit == 1U) - { - if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) - { - hhcd->hc[chnum].NyetErrCnt++; - if (hhcd->hc[chnum].NyetErrCnt > 2U) - { - hhcd->hc[chnum].NyetErrCnt = 0U; - hhcd->hc[chnum].do_csplit = 0U; - - if (hhcd->hc[chnum].ErrCnt < 3U) - { - hhcd->hc[chnum].ep_ss_schedule = 1U; - } - __HAL_HCD_CLEAR_HC_CSPLT(chnum); - hhcd->hc[chnum].urb_state = URB_ERROR; - } - else - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - } - else - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - } - } - } - else if (hhcd->hc[chnum].state == HC_ACK) - { - hhcd->hc[chnum].state = HC_HALTED; - - if (hhcd->hc[chnum].do_csplit == 1U) - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - - /* Set Complete split and re-activate the channel */ - USBx_HC(chnum)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; - USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; - USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINT_ACK; - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - } - } - } - else if (hhcd->hc[chnum].state == HC_NAK) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].urb_state = URB_NOTREADY; - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - } - } - else if (hhcd->hc[chnum].state == HC_BBLERR) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].ErrCnt++; - hhcd->hc[chnum].urb_state = URB_ERROR; - } - else - { - if (hhcd->hc[chnum].state == HC_HALTED) - { - return; - } - } - -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); -#else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); - hhcd->hc[chnum].state = HC_NYET; - - if (hhcd->hc[chnum].do_ssplit == 0U) - { - hhcd->hc[chnum].ErrCnt = 0U; - } - - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) - { - if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) - { - hhcd->hc[chnum].ErrCnt = 0U; - hhcd->hc[chnum].state = HC_NAK; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) - { - hhcd->hc[chnum].ErrCnt = 0U; - - if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) - { - hhcd->hc[chnum].state = HC_NAK; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - } - else - { - /* ... */ - } - - if (hhcd->hc[chnum].do_csplit == 1U) - { - hhcd->hc[chnum].do_csplit = 0U; - __HAL_HCD_CLEAR_HC_CSPLT(chnum); - __HAL_HCD_UNMASK_ACK_HC_INT(chnum); - } - - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - } - else - { - /* ... */ - } -} - -/** - * @brief Handle Host Channel OUT interrupt requests. - * @param hhcd HCD handle - * @param chnum Channel number. - * This parameter can be a value from 1 to 15 - * @retval none - */ -static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) -{ - const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - uint32_t num_packets; - - if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_AHBERR)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR); - hhcd->hc[chnum].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_ACK)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK); - - if (hhcd->hc[chnum].do_ping == 1U) - { - hhcd->hc[chnum].do_ping = 0U; - hhcd->hc[chnum].urb_state = URB_NOTREADY; - hhcd->hc[chnum].state = HC_ACK; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - - if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) - { - if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) - { - hhcd->hc[chnum].do_csplit = 1U; - } - - hhcd->hc[chnum].state = HC_ACK; - (void)USB_HC_Halt(hhcd->Instance, chnum); - - /* reset error_count */ - hhcd->hc[chnum].ErrCnt = 0U; - } - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_FRMOR)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR); - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_XFRC)) - { - hhcd->hc[chnum].ErrCnt = 0U; - - /* transaction completed with NYET state, update do ping state */ - if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) - { - hhcd->hc[chnum].do_ping = 1U; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); - } - - if (hhcd->hc[chnum].do_csplit != 0U) - { - hhcd->hc[chnum].do_csplit = 0U; - __HAL_HCD_CLEAR_HC_CSPLT(chnum); - } - - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC); - hhcd->hc[chnum].state = HC_XFRC; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NYET)) - { - hhcd->hc[chnum].state = HC_NYET; - - if (hhcd->hc[chnum].do_ssplit == 0U) - { - hhcd->hc[chnum].do_ping = 1U; - } - - hhcd->hc[chnum].ErrCnt = 0U; - (void)USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_STALL)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL); - hhcd->hc[chnum].state = HC_STALL; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_NAK)) - { - hhcd->hc[chnum].ErrCnt = 0U; - hhcd->hc[chnum].state = HC_NAK; - - if (hhcd->hc[chnum].do_ping == 0U) - { - if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) - { - hhcd->hc[chnum].do_ping = 1U; - } - } - - (void)USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_TXERR)) - { - if (hhcd->Init.dma_enable == 0U) - { - hhcd->hc[chnum].state = HC_XACTERR; - (void)USB_HC_Halt(hhcd->Instance, chnum); - } - else - { - hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].ErrCnt > 2U) - { - hhcd->hc[chnum].ErrCnt = 0U; - hhcd->hc[chnum].urb_state = URB_ERROR; - -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); -#else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - else - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - } - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_DTERR)) - { - hhcd->hc[chnum].state = HC_DATATGLERR; - (void)USB_HC_Halt(hhcd->Instance, chnum); - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR); - } - else if (__HAL_HCD_GET_CH_FLAG(hhcd, chnum, USB_OTG_HCINT_CHH)) - { - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH); - - if (hhcd->hc[chnum].state == HC_XFRC) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].urb_state = URB_DONE; - - if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || - (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) - { - if (hhcd->Init.dma_enable == 0U) - { - hhcd->hc[chnum].toggle_out ^= 1U; - } - - if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) - { - num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; - - if ((num_packets & 1U) != 0U) - { - hhcd->hc[chnum].toggle_out ^= 1U; - } - } - } - } - else if (hhcd->hc[chnum].state == HC_ACK) - { - hhcd->hc[chnum].state = HC_HALTED; - - if (hhcd->hc[chnum].do_csplit == 1U) - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - } - else if (hhcd->hc[chnum].state == HC_NAK) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].urb_state = URB_NOTREADY; - - if (hhcd->hc[chnum].do_csplit == 1U) - { - hhcd->hc[chnum].do_csplit = 0U; - __HAL_HCD_CLEAR_HC_CSPLT(chnum); - } - } - else if (hhcd->hc[chnum].state == HC_NYET) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].urb_state = URB_NOTREADY; - } - else if (hhcd->hc[chnum].state == HC_STALL) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].urb_state = URB_STALL; - } - else if ((hhcd->hc[chnum].state == HC_XACTERR) || - (hhcd->hc[chnum].state == HC_DATATGLERR)) - { - hhcd->hc[chnum].state = HC_HALTED; - hhcd->hc[chnum].ErrCnt++; - if (hhcd->hc[chnum].ErrCnt > 2U) - { - hhcd->hc[chnum].ErrCnt = 0U; - hhcd->hc[chnum].urb_state = URB_ERROR; - } - else - { - hhcd->hc[chnum].urb_state = URB_NOTREADY; - - /* re-activate the channel */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - } - } - else - { - return; - } - -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, chnum, hhcd->hc[chnum].urb_state); -#else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - else - { - return; - } -} - -/** - * @brief Handle Rx Queue Level interrupt requests. - * @param hhcd HCD handle - * @retval none - */ -static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd) -{ - const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t pktsts; - uint32_t pktcnt; - uint32_t GrxstspReg; - uint32_t xferSizePktCnt; - uint32_t tmpreg; - uint32_t chnum; - - GrxstspReg = hhcd->Instance->GRXSTSP; - chnum = GrxstspReg & USB_OTG_GRXSTSP_EPNUM; - pktsts = (GrxstspReg & USB_OTG_GRXSTSP_PKTSTS) >> 17; - pktcnt = (GrxstspReg & USB_OTG_GRXSTSP_BCNT) >> 4; - - switch (pktsts) - { - case GRXSTS_PKTSTS_IN: - /* Read the data into the host buffer. */ - if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) - { - if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) - { - (void)USB_ReadPacket(hhcd->Instance, - hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); - - /* manage multiple Xfer */ - hhcd->hc[chnum].xfer_buff += pktcnt; - hhcd->hc[chnum].xfer_count += pktcnt; - - /* get transfer size packet count */ - xferSizePktCnt = (USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19; - - if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) - { - /* re-activate the channel when more packets are expected */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - hhcd->hc[chnum].toggle_in ^= 1U; - } - } - else - { - hhcd->hc[chnum].urb_state = URB_ERROR; - } - } - break; - - case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: - break; - - case GRXSTS_PKTSTS_IN_XFER_COMP: - case GRXSTS_PKTSTS_CH_HALTED: - default: - break; - } -} - -/** - * @brief Handle Host Port interrupt requests. - * @param hhcd HCD handle - * @retval None - */ -static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) -{ - const USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t hprt0; - __IO uint32_t hprt0_dup; - - /* Handle Host Port Interrupts */ - hprt0 = USBx_HPRT0; - hprt0_dup = USBx_HPRT0; - - hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | \ - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - /* Check whether Port Connect detected */ - if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) - { - if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) - { -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->ConnectCallback(hhcd); -#else - HAL_HCD_Connect_Callback(hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - hprt0_dup |= USB_OTG_HPRT_PCDET; - } - - /* Check whether Port Enable Changed */ - if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) - { - hprt0_dup |= USB_OTG_HPRT_PENCHNG; - - if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) - { - if (hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY) - { - if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) - { - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_6_MHZ); - } - else - { - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); - } - } - else - { - if (hhcd->Init.speed == HCD_SPEED_FULL) - { - USBx_HOST->HFIR = HFIR_60_MHZ; - } - } -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->PortEnabledCallback(hhcd); -#else - HAL_HCD_PortEnabled_Callback(hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - } - else - { -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->PortDisabledCallback(hhcd); -#else - HAL_HCD_PortDisabled_Callback(hhcd); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - } - - /* Check for an overcurrent */ - if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) - { - hprt0_dup |= USB_OTG_HPRT_POCCHNG; - } - - /* Clear Port Interrupts */ - USBx_HPRT0 = hprt0_dup; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#endif /* HAL_HCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c index 4e4fbbf6..67a712c2 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c.c @@ -1,7569 +1,7600 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2c.c - * @author MCD Application Team - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for - the transmit or receive stream - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx stream - (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx stream - - (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, - Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - - *** Interrupt mode or DMA mode IO sequential operation *** - ========================================================== - [..] - (@) These interfaces allow to manage a sequential transfer with a repeated start condition - when a direction change during transfer - [..] - (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in - no sequential mode - (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with - start condition, address and data to transfer without a final stop condition, - an then permit a call the same master sequential interface several times - (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() - or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) - (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to - transfer - if no direction change and without a final stop condition in both cases - (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to - transfer - if no direction change and with a final stop condition in both cases - (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition - after several call of the same master sequential interface several times - (link with option I2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using - HAL_I2C_Master_Seq_Transmit_IT - or HAL_I2C_Master_Seq_Receive_IT - or HAL_I2C_Master_Seq_Transmit_DMA - or HAL_I2C_Master_Seq_Receive_DMA - with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or - Receive sequence permit to call the opposite interface Receive or Transmit - without stopping the communication and so generate a restart condition. - (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after - each call of the same master sequential - interface. - Usage can, transfer several bytes one by one with a restart with slave address between - each bytes using - HAL_I2C_Master_Seq_Transmit_IT - or HAL_I2C_Master_Seq_Receive_IT - or HAL_I2C_Master_Seq_Transmit_DMA - or HAL_I2C_Master_Seq_Receive_DMA - with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. - Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic - generation of STOP condition. - - (+) Different sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using - HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and - users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using - HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() - HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can - add their own code to check the Address Match Code and the transmission direction request by master - (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using - HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and - users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using - HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - *** Callback registration *** - ============================================= - [..] - The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() - to register an interrupt callback. - [..] - Function HAL_I2C_RegisterCallback() allows to register following callbacks: - (+) MasterTxCpltCallback : callback for Master transmission end of transfer. - (+) MasterRxCpltCallback : callback for Master reception end of transfer. - (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. - (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. - (+) ListenCpltCallback : callback for end of listen mode. - (+) MemTxCpltCallback : callback for Memory transmission end of transfer. - (+) MemRxCpltCallback : callback for Memory reception end of transfer. - (+) ErrorCallback : callback for error detection. - (+) AbortCpltCallback : callback for abort completion process. - (+) MspInitCallback : callback for Msp Init. - (+) MspDeInitCallback : callback for Msp DeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - [..] - For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). - [..] - Use function HAL_I2C_UnRegisterCallback to reset a callback to the default - weak function. - HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) MasterTxCpltCallback : callback for Master transmission end of transfer. - (+) MasterRxCpltCallback : callback for Master reception end of transfer. - (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. - (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. - (+) ListenCpltCallback : callback for end of listen mode. - (+) MemTxCpltCallback : callback for Memory transmission end of transfer. - (+) MemRxCpltCallback : callback for Memory reception end of transfer. - (+) ErrorCallback : callback for error detection. - (+) AbortCpltCallback : callback for abort completion process. - (+) MspInitCallback : callback for Msp Init. - (+) MspDeInitCallback : callback for Msp DeInit. - [..] - For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). - [..] - By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when - these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - [..] - Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() - or HAL_I2C_Init() function. - [..] - When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup I2C_Private_Define I2C Private Define - * @{ - */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ - -#define MAX_NBYTE_SIZE 255U -#define SLAVE_ADDR_SHIFT 7U -#define SLAVE_ADDR_MSK 0x06U - -/* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ - (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ - (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) -/*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) -/*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_MASTER)) -/*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_MASTER)) -/*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_SLAVE)) -/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_SLAVE)) -/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_MEM)) -/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_MEM)) -/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ - - -/* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with - @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with - @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT - and @ref I2C_XFER_RX_IT */ - -#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error - and NACK treatment */ -#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ -#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ - -/* Private define Sequential Transfer Options default/reset value */ -#define I2C_NO_OPTION_FRAME (0xFFFF0000U) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup I2C_Private_Macro - * @{ - */ -/* Macro to get remaining data to transfer on DMA side */ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions to handle DMA transfer */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); - - -/* Private functions to handle IT transfer */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); - -/* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); - -/* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); - -/* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); - -/* Private functions to centralize the enable/disable of Interrupts */ -static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); - -/* Private function to treat different error callback */ -static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); - -/* Private function to flush TXDR register */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); - -/* Private function to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); - -/* Private function to Convert Specific options */ -static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Clock Timing - (++) Own Address 1 - (++) Addressing mode (Master, Slave) - (++) Dual Addressing mode - (++) Own Address 2 - (++) Own Address 2 Mask - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if (hi2c->State == HAL_I2C_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2c->Lock = HAL_UNLOCKED; - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - /* Init the I2C Callback settings */ - hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ - hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ - hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ - hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ - hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ - hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ - hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ - hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ - hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ - - if (hi2c->MspInitCallback == NULL) - { - hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - hi2c->MspInitCallback(hi2c); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2C_MspInit(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ - /* Configure I2Cx: Frequency range */ - hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Disable Own Address1 before set the Own Address1 configuration */ - hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Addressing Master mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); - } - else - { - /* Clear the I2C ADD10 bit */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); - } - /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ - hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Disable Own Address2 before set the Own Address2 configuration */ - hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; - - /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ - (hi2c->Init.OwnAddress2Masks << 8)); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - return HAL_OK; -} - -/** - * @brief DeInitialize the I2C peripheral. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - if (hi2c->MspDeInitCallback == NULL) - { - hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - hi2c->MspDeInitCallback(hi2c); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Initialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User I2C Callback - * To be used instead of the weak predefined callback - * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET - * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID - * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID - * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID - * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID - * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID - * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID - * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID - * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID - * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID - * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, - pI2C_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (HAL_I2C_STATE_READY == hi2c->State) - { - switch (CallbackID) - { - case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : - hi2c->MasterTxCpltCallback = pCallback; - break; - - case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : - hi2c->MasterRxCpltCallback = pCallback; - break; - - case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : - hi2c->SlaveTxCpltCallback = pCallback; - break; - - case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : - hi2c->SlaveRxCpltCallback = pCallback; - break; - - case HAL_I2C_LISTEN_COMPLETE_CB_ID : - hi2c->ListenCpltCallback = pCallback; - break; - - case HAL_I2C_MEM_TX_COMPLETE_CB_ID : - hi2c->MemTxCpltCallback = pCallback; - break; - - case HAL_I2C_MEM_RX_COMPLETE_CB_ID : - hi2c->MemRxCpltCallback = pCallback; - break; - - case HAL_I2C_ERROR_CB_ID : - hi2c->ErrorCallback = pCallback; - break; - - case HAL_I2C_ABORT_CB_ID : - hi2c->AbortCpltCallback = pCallback; - break; - - case HAL_I2C_MSPINIT_CB_ID : - hi2c->MspInitCallback = pCallback; - break; - - case HAL_I2C_MSPDEINIT_CB_ID : - hi2c->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_I2C_STATE_RESET == hi2c->State) - { - switch (CallbackID) - { - case HAL_I2C_MSPINIT_CB_ID : - hi2c->MspInitCallback = pCallback; - break; - - case HAL_I2C_MSPDEINIT_CB_ID : - hi2c->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an I2C Callback - * I2C callback is redirected to the weak predefined callback - * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET - * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * This parameter can be one of the following values: - * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID - * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID - * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID - * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID - * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID - * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID - * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID - * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID - * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID - * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_I2C_STATE_READY == hi2c->State) - { - switch (CallbackID) - { - case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : - hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ - break; - - case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : - hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ - break; - - case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : - hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ - break; - - case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : - hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ - break; - - case HAL_I2C_LISTEN_COMPLETE_CB_ID : - hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ - break; - - case HAL_I2C_MEM_TX_COMPLETE_CB_ID : - hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ - break; - - case HAL_I2C_MEM_RX_COMPLETE_CB_ID : - hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ - break; - - case HAL_I2C_ERROR_CB_ID : - hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_I2C_ABORT_CB_ID : - hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_I2C_MSPINIT_CB_ID : - hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_I2C_MSPDEINIT_CB_ID : - hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_I2C_STATE_RESET == hi2c->State) - { - switch (CallbackID) - { - case HAL_I2C_MSPINIT_CB_ID : - hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_I2C_MSPDEINIT_CB_ID : - hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Register the Slave Address Match I2C Callback - * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pCallback pointer to the Address Match Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (HAL_I2C_STATE_READY == hi2c->State) - { - hi2c->AddrCallback = pCallback; - } - else - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief UnRegister the Slave Address Match I2C Callback - * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_I2C_STATE_READY == hi2c->State) - { - hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ - } - else - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - (++) HAL_I2C_Master_Seq_Transmit_IT() - (++) HAL_I2C_Master_Seq_Receive_IT() - (++) HAL_I2C_Slave_Seq_Transmit_IT() - (++) HAL_I2C_Slave_Seq_Receive_IT() - (++) HAL_I2C_EnableListen_IT() - (++) HAL_I2C_DisableListen_IT() - (++) HAL_I2C_Master_Abort_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - (++) HAL_I2C_Master_Seq_Transmit_DMA() - (++) HAL_I2C_Master_Seq_Receive_DMA() - (++) HAL_I2C_Slave_Seq_Transmit_DMA() - (++) HAL_I2C_Slave_Seq_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_AddrCallback() - (++) HAL_I2C_ListenCpltCallback() - (++) HAL_I2C_ErrorCallback() - (++) HAL_I2C_AbortCpltCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t xfermode; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, - I2C_GENERATE_START_WRITE); - } - else - { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, - I2C_GENERATE_START_WRITE); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = 1U; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_READ); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) -{ - uint32_t tickstart; - uint16_t tmpXferCount; - HAL_StatusTypeDef error; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Preload TX data if no stretch enable */ - if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - } - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - return HAL_ERROR; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* If 10bit addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - return HAL_ERROR; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - return HAL_ERROR; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - } - - /* Wait until AF flag is set */ - error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); - - if (error != HAL_OK) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - - tmpXferCount = hi2c->XferCount; - if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) - { - /* Reset ErrorCode to NONE */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - } - else - { - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - return HAL_ERROR; - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) -{ - uint32_t tickstart; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Wait until DIR flag is reset Receiver mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Store Last receive data if any */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - - return HAL_ERROR; - } - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) -{ - uint32_t xfermode; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if (hi2c->XferSize > 0U) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, - I2C_GENERATE_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, - I2C_GENERATE_START_WRITE); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) -{ - uint32_t xfermode; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = 1U; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Preload TX data if no stretch enable */ - if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) -{ - uint32_t xfermode; - HAL_StatusTypeDef dmaxferstatus; - uint32_t sizetoxfer = 0U; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - sizetoxfer = hi2c->XferSize; - hi2c->XferCount--; - hi2c->XferSize--; - } - - if (hi2c->XferSize > 0U) - { - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, - (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), - xfermode, I2C_GENERATE_START_WRITE); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, - I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) -{ - uint32_t xfermode; - HAL_StatusTypeDef dmaxferstatus; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = 1U; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address */ - /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef dmaxferstatus; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Preload TX data if no stretch enable */ - if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - - if (hi2c->XferCount != 0U) - { - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, - (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef dmaxferstatus; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - do - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_NO_STARTSTOP); - } - } - - } while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = 1U; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_READ); - } - - do - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = 1U; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, - I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_NO_STARTSTOP); - } - } - } while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->XferSize = 0U; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Mem_ISR_IT; - hi2c->Devaddress = DevAddress; - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Prefetch Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - /* If Memory address size is 16Bit */ - else - { - /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Prepare Memaddress buffer for LSB part */ - hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); - } - /* Send Slave Address and Memory Address */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Mem_ISR_IT; - hi2c->Devaddress = DevAddress; - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Prefetch Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - /* If Memory address size is 16Bit */ - else - { - /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Prepare Memaddress buffer for LSB part */ - hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); - } - /* Send Slave Address and Memory Address */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Mem_ISR_DMA; - hi2c->Devaddress = DevAddress; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Prefetch Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - /* If Memory address size is 16Bit */ - else - { - /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Prepare Memaddress buffer for LSB part */ - hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); - } - - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address and Memory Address */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Mem_ISR_DMA; - hi2c->Devaddress = DevAddress; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Prefetch Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - /* If Memory address size is 16Bit */ - else - { - /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Prepare Memaddress buffer for LSB part */ - hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); - } - - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address and Memory Address */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param Trials Number of trials - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout) -{ - uint32_t tickstart; - - __IO uint32_t I2C_Trials = 0UL; - - FlagStatus tmp1; - FlagStatus tmp2; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - do - { - /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - tickstart = HAL_GetTick(); - - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); - tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); - - while ((tmp1 == RESET) && (tmp2 == RESET)) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); - tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); - } - - /* Check if the NACKF flag has not been set */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Increment Trials */ - I2C_Trials++; - } while (I2C_Trials < Trials); - - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - uint32_t sizetoxfer = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ - (XferOptions == I2C_FIRST_AND_LAST_FRAME))) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - sizetoxfer = hi2c->XferSize; - hi2c->XferCount--; - hi2c->XferSize--; - } - - /* If transfer direction not change and there is no request to start another frame, - do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ - (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) - { - xferrequest = I2C_NO_STARTSTOP; - } - else - { - /* Convert OTHER_xxx XferOptions if any */ - I2C_ConvertOtherXferOptions(hi2c); - - /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount <= MAX_NBYTE_SIZE) - { - xfermode = hi2c->XferOptions; - } - } - - /* Send Slave Address and set NBYTES to write */ - if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - HAL_StatusTypeDef dmaxferstatus; - uint32_t sizetoxfer = 0U; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_DMA; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ - (XferOptions == I2C_FIRST_AND_LAST_FRAME))) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - sizetoxfer = hi2c->XferSize; - hi2c->XferCount--; - hi2c->XferSize--; - } - - /* If transfer direction not change and there is no request to start another frame, - do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ - (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) - { - xferrequest = I2C_NO_STARTSTOP; - } - else - { - /* Convert OTHER_xxx XferOptions if any */ - I2C_ConvertOtherXferOptions(hi2c); - - /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount <= MAX_NBYTE_SIZE) - { - xfermode = hi2c->XferOptions; - } - } - - if (hi2c->XferSize > 0U) - { - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, - (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address and set NBYTES to write */ - if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - } - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode; - uint32_t xferrequest = I2C_GENERATE_START_READ; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change and there is no request to start another frame, - do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ - (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) - { - xferrequest = I2C_NO_STARTSTOP; - } - else - { - /* Convert OTHER_xxx XferOptions if any */ - I2C_ConvertOtherXferOptions(hi2c); - - /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount <= MAX_NBYTE_SIZE) - { - xfermode = hi2c->XferOptions; - } - } - - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode; - uint32_t xferrequest = I2C_GENERATE_START_READ; - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_DMA; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change and there is no request to start another frame, - do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ - (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) - { - xferrequest = I2C_NO_STARTSTOP; - } - else - { - /* Convert OTHER_xxx XferOptions if any */ - I2C_ConvertOtherXferOptions(hi2c); - - /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount <= MAX_NBYTE_SIZE) - { - xfermode = hi2c->XferOptions; - } - } - - if (hi2c->XferSize > 0U) - { - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - FlagStatus tmp; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Abort DMA Xfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - } - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - FlagStatus tmp; - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - /* Abort DMA Xfer if any */ - if (hi2c->hdmarx != NULL) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - } - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - } - } - else - { - /* Nothing to do */ - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Reset XferSize */ - hi2c->XferSize = 0; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - FlagStatus tmp; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave TX state to RX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - } - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - FlagStatus tmp; - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave TX state to RX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - } - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Abort DMA Xfer if any */ - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - } - } - else - { - /* Nothing to do */ - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, - (uint32_t)pData, hi2c->XferSize); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Reset XferSize */ - hi2c->XferSize = 0; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Enable the Address Match interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp; - - /* Disable Address listen mode only if a transfer is not ongoing */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; - hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Disable the Address Match interrupt */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -{ - HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; - - if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts and Store Previous state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - } - else - { - /* Do nothing */ - } - - /* Set State at HAL_I2C_STATE_ABORT */ - hi2c->State = HAL_I2C_STATE_ABORT; - - /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ - /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - return HAL_OK; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Get current IT Flags and IT sources value */ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C events treatment -------------------------------------*/ - if (hi2c->XferISR != NULL) - { - hi2c->XferISR(hi2c, itflags, itsources); - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - uint32_t tmperror; - - /* I2C Bus error interrupt occurred ------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ - (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* Store current volatile hi2c->ErrorCode, misra rule */ - tmperror = hi2c->ErrorCode; - - /* Call the Error Callback in case of Error detected */ - if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) - { - I2C_ITError(hi2c, tmperror); - } -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback could be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode Address Match Code - * @retval None - */ -__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AddrCallback() could be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ListenCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2C error callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief I2C abort callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * -@verbatim - =============================================================================== - ##### Peripheral State, Mode and Error functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2C handle state. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) -{ - /* Return I2C handle state */ - return hi2c->State; -} - -/** - * @brief Returns the I2C Master, Slave, Memory or no mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL mode - */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) -{ - return hi2c->Mode; -} - -/** - * @brief Return the I2C error code. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval I2C Error Code - */ -uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint16_t devaddress; - uint32_t tmpITFlags = ITFlags; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) - { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ - ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) - { - /* Write data to TXDR */ - if (hi2c->XferCount != 0U) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - /* Errata workaround 170323 */ - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - hi2c->XferSize = 1U; - } - else - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, - hi2c->XferOptions, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSeqCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - if (hi2c->XferCount == 0U) - { - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate a stop condition in case of no transfer option */ - if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSeqCplt(hi2c); - } - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else - { - /* Nothing to do */ - } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, tmpITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint32_t direction = I2C_GENERATE_START_WRITE; - uint32_t tmpITFlags = ITFlags; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) - { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) - { - if (hi2c->Memaddress == 0xFFFFFFFFU) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - else - { - /* Write LSB part of Memory Address */ - hi2c->Instance->TXDR = hi2c->Memaddress; - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - /* Errata workaround 170323 */ - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - hi2c->XferSize = 1U; - } - else - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - /* Disable Interrupt related to address step */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - direction = I2C_GENERATE_START_READ; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - /* Errata workaround 170323 */ - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - hi2c->XferSize = 1U; - } - else - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_RELOAD_MODE, direction); - } - else - { - hi2c->XferSize = hi2c->XferCount; - - /* Set NBYTES to write and generate RESTART */ - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, direction); - } - } - else - { - /* Nothing to do */ - } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, tmpITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint32_t tmpoptions = hi2c->XferOptions; - uint32_t tmpITFlags = ITFlags; - - /* Process locked */ - __HAL_LOCK(hi2c); - - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, tmpITFlags); - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, tmpITFlags); - } - else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) - { - if (hi2c->XferCount > 0U) - { - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - - if ((hi2c->XferCount == 0U) && \ - (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, tmpITFlags); - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Data have already been sent */ - /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if (hi2c->XferCount > 0U) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - else - { - if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) - { - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - } - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint16_t devaddress; - uint32_t xfermode; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - /* Disable TC interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if (hi2c->XferCount != 0U) - { - /* Recover Slave address */ - devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Prepare the new XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - /* Errata workaround 170323 */ - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - hi2c->XferSize = 1U; - } - else - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - xfermode = hi2c->XferOptions; - } - else - { - xfermode = I2C_AUTOEND_MODE; - } - } - - /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSeqCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - if (hi2c->XferCount == 0U) - { - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate a stop condition in case of no transfer option */ - if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSeqCplt(hi2c); - } - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint32_t direction = I2C_GENERATE_START_WRITE; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) - { - /* Write LSB part of Memory Address */ - hi2c->Instance->TXDR = hi2c->Memaddress; - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - /* Disable Interrupt related to address step */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Enable only Error interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - if (hi2c->XferCount != 0U) - { - /* Prepare the new XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - /* Errata workaround 170323 */ - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - hi2c->XferSize = 1U; - } - else - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - /* Disable Interrupt related to address step */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Enable only Error and NACK interrupt for data transfer */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - direction = I2C_GENERATE_START_READ; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - /* Errata workaround 170323 */ - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - hi2c->XferSize = 1U; - } - else - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_RELOAD_MODE, direction); - } - else - { - hi2c->XferSize = hi2c->XferCount; - - /* Set NBYTES to write and generate RESTART */ - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, direction); - } - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint32_t tmpoptions = hi2c->XferOptions; - uint32_t treatdmanack = 0U; - HAL_I2C_StateTypeDef tmpstate; - - /* Process locked */ - __HAL_LOCK(hi2c); - - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - /* So clear Flag NACKF only */ - if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || - (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) - { - /* Split check of hdmarx, for MISRA compliance */ - if (hi2c->hdmarx != NULL) - { - if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) - { - if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) - { - treatdmanack = 1U; - } - } - } - - /* Split check of hdmatx, for MISRA compliance */ - if (hi2c->hdmatx != NULL) - { - if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) - { - if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) - { - treatdmanack = 1U; - } - } - } - - if (treatdmanack == 1U) - { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ - tmpstate = hi2c->State; - - if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) - { - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - } - else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - } - else - { - /* Do nothing */ - } - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - } - } - else - { - /* Only Clear NACK Flag, no DMA treatment is pending */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, ITFlags); - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TC flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief I2C Address complete process callback. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint8_t transferdirection; - uint16_t slaveaddrcode; - uint16_t ownadd1code; - uint16_t ownadd2code; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(ITFlags); - - /* In case of Listen state, need to inform upper layer of address match code event */ - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - transferdirection = I2C_GET_DIR(hi2c); - slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); - ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); - ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - - /* If 10bits addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) - { - slaveaddrcode = ownadd1code; - hi2c->AddrEventCount++; - if (hi2c->AddrEventCount == 2U) - { - /* Reset Address Event counter */ - hi2c->AddrEventCount = 0U; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); -#else - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - else - { - slaveaddrcode = ownadd2code; - - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); -#else - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - /* else 7 bits addressing mode is selected */ - else - { - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); -#else - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - /* Else clear address flag only */ - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } -} - -/** - * @brief I2C Master sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* No Generate Stop, to permit restart mode */ - /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterTxCpltCallback(hi2c); -#else - HAL_I2C_MasterTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterRxCpltCallback(hi2c); -#else - HAL_I2C_MasterRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } -} - -/** - * @brief I2C Slave sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) -{ - uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); - - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* If a DMA is ongoing, Update handle size context */ - if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - } - else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - } - else - { - /* Do nothing */ - } - - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->SlaveTxCpltCallback(hi2c); -#else - HAL_I2C_SlaveTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->SlaveRxCpltCallback(hi2c); -#else - HAL_I2C_SlaveRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief I2C Master complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint32_t tmperror; - uint32_t tmpITFlags = ITFlags; - __IO uint32_t tmpreg; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Disable Interrupts and Store Previous state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - } - else - { - /* Do nothing */ - } - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Reset handle parameters */ - hi2c->XferISR = NULL; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set acknowledge error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Fetch Last receive data if any */ - if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - tmpreg = (uint8_t)hi2c->Instance->RXDR; - UNUSED(tmpreg); - } - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Store current volatile hi2c->ErrorCode, misra rule */ - tmperror = hi2c->ErrorCode; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MemTxCpltCallback(hi2c); -#else - HAL_I2C_MemTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterTxCpltCallback(hi2c); -#else - HAL_I2C_MasterTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MemRxCpltCallback(hi2c); -#else - HAL_I2C_MemRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterRxCpltCallback(hi2c); -#else - HAL_I2C_MasterRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief I2C Slave complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); - uint32_t tmpITFlags = ITFlags; - uint32_t tmpoptions = hi2c->XferOptions; - HAL_I2C_StateTypeDef tmpstate = hi2c->State; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Disable Interrupts and Store Previous state */ - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - } - else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - } - else if (tmpstate == HAL_I2C_STATE_LISTEN) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); - hi2c->PreviousState = I2C_STATE_NONE; - } - else - { - /* Do nothing */ - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* If a DMA is ongoing, Update handle size context */ - if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - if (hi2c->hdmatx != NULL) - { - hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); - } - } - else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - if (hi2c->hdmarx != NULL) - { - hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); - } - } - else - { - /* Do nothing */ - } - - /* Store Last receive data if any */ - if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) - { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - } - } - - /* All data are not transferred, so set error code accordingly */ - if (hi2c->XferCount != 0U) - { - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, tmpITFlags); - } - else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - } - } - - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, tmpITFlags); - } - } - else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ - I2C_ITSlaveSeqCplt(hi2c); - - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ListenCpltCallback(hi2c); -#else - HAL_I2C_ListenCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->SlaveRxCpltCallback(hi2c); -#else - HAL_I2C_SlaveRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->SlaveTxCpltCallback(hi2c); -#else - HAL_I2C_SlaveTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } -} - -/** - * @brief I2C Listen complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Reset handle parameters */ - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Store Last receive data if any */ - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) - { - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - /* Disable all Interrupts*/ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ListenCpltCallback(hi2c); -#else - HAL_I2C_ListenCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -} - -/** - * @brief I2C interrupts error process. - * @param hi2c I2C handle. - * @param ErrorCode Error code to handle. - * @retval None - */ -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) -{ - HAL_I2C_StateTypeDef tmpstate = hi2c->State; - - uint32_t tmppreviousstate; - - /* Reset handle parameters */ - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferCount = 0U; - - /* Set new error code */ - hi2c->ErrorCode |= ErrorCode; - - /* Disable Interrupts */ - if ((tmpstate == HAL_I2C_STATE_LISTEN) || - (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* Disable all interrupts, except interrupts related to LISTEN state */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* keep HAL_I2C_STATE_LISTEN if set */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - } - else - { - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* If state is an abort treatment on going, don't change state */ - /* This change will be do later */ - if (hi2c->State != HAL_I2C_STATE_ABORT) - { - /* Set HAL_I2C_STATE_READY */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - } - hi2c->XferISR = NULL; - } - - /* Abort DMA TX transfer if any */ - tmppreviousstate = hi2c->PreviousState; - - if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ - (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) - { - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - } - - if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - else - { - I2C_TreatErrorCallback(hi2c); - } - } - /* Abort DMA RX transfer if any */ - else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ - (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) - { - if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - } - - if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - else - { - I2C_TreatErrorCallback(hi2c); - } - } - else - { - I2C_TreatErrorCallback(hi2c); - } -} - -/** - * @brief I2C Error callback treatment. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } -} - -/** - * @brief I2C Tx data register flush process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) -{ - /* If a pending TXIS flag is set */ - /* Write a dummy data in TXDR to clear it */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) - { - hi2c->Instance->TXDR = 0x00U; - } - - /* Flush TX register if not empty */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } -} - -/** - * @brief DMA I2C master transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize) != HAL_OK) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); - } - else - { - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } - } -} - - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - uint32_t tmpoptions = hi2c->XferOptions; - - if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ - } -} - - -/** - * @brief DMA I2C master receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - /* Errata workaround 170323 */ - if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) - { - hi2c->XferSize = 1U; - } - else - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, - hi2c->XferSize) != HAL_OK) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); - } - else - { - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } - } -} - - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - uint32_t tmpoptions = hi2c->XferOptions; - - if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ - (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ - } -} - - -/** - * @brief DMA I2C communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - uint32_t treatdmaerror = 0U; - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - - if (hi2c->hdmatx != NULL) - { - if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) - { - treatdmaerror = 1U; - } - } - - if (hi2c->hdmarx != NULL) - { - if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) - { - treatdmaerror = 1U; - } - } - - /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */ - if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) - { - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); - } -} - - -/** - * @brief DMA I2C communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma DMA handle. - * @retval None - */ -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - - /* Reset AbortCpltCallback */ - if (hi2c->hdmatx != NULL) - { - hi2c->hdmatx->XferAbortCallback = NULL; - } - if (hi2c->hdmarx != NULL) - { - hi2c->hdmarx->XferAbortCallback = NULL; - } - - I2C_TreatErrorCallback(hi2c); -} - - -/** - * @brief This function handles I2C Communication Timeout. It waits - * until a flag is no longer in the specified status. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag Specifies the I2C flag to check. - * @param Status The actual Flag status (SET or RESET). - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) - { - /* Check if an error is detected */ - if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - { - /* Check if an error is detected */ - if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check if an error is detected */ - if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart) -{ - HAL_StatusTypeDef status = HAL_OK; - - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) - { - /* Check if an error is detected */ - if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - { - status = HAL_ERROR; - } - - /* Check if a STOPF is detected */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) - { - /* Check if an RXNE is pending */ - /* Store Last receive data if any */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) - { - /* Return HAL_OK */ - /* The Reading of data from RXDR will be done in caller function */ - status = HAL_OK; - } - - /* Check a no-acknowledge have been detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - status = HAL_ERROR; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - } - - /* Check for the Timeout */ - if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) - { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - status = HAL_ERROR; - } - } - } - return status; -} - -/** - * @brief This function handles errors detection during an I2C Communication. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t itflag = hi2c->Instance->ISR; - uint32_t error_code = 0; - uint32_t tickstart = Tickstart; - uint32_t tmp1; - HAL_I2C_ModeTypeDef tmp2; - - if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) - { - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Wait until STOP Flag is set or timeout occurred */ - /* AutoEnd should be initiate after AF */ - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); - tmp2 = hi2c->Mode; - - /* In case of I2C still busy, try to regenerate a STOP manually */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ - (tmp1 != I2C_CR2_STOP) && \ - (tmp2 != HAL_I2C_MODE_SLAVE)) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Update Tick with new reference */ - tickstart = HAL_GetTick(); - } - - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) - { - error_code |= HAL_I2C_ERROR_TIMEOUT; - - status = HAL_ERROR; - - break; - } - } - } - } - } - - /* In case STOP Flag is detected, clear it */ - if (status == HAL_OK) - { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - error_code |= HAL_I2C_ERROR_AF; - - status = HAL_ERROR; - } - - /* Refresh Content of Status register */ - itflag = hi2c->Instance->ISR; - - /* Then verify if an additional errors occurs */ - /* Check if a Bus error occurred */ - if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) - { - error_code |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - - status = HAL_ERROR; - } - - /* Check if an Over-Run/Under-Run error occurred */ - if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) - { - error_code |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - - status = HAL_ERROR; - } - - /* Check if an Arbitration Loss error occurred */ - if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) - { - error_code |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - - status = HAL_ERROR; - } - - if (status != HAL_OK) - { - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode |= error_code; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } - - return status; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hi2c I2C handle. - * @param DevAddress Specifies the slave address to be programmed. - * @param Size Specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param Mode New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_RELOAD_MODE Enable Reload mode . - * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. - * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. - * @param Request New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. - * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). - * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. - * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. - * @retval None - */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_TRANSFER_MODE(Mode)); - assert_param(IS_TRANSFER_REQUEST(Request)); - - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); - - /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, \ - ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP)), tmp); -} - -/** - * @brief Manage the enabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval None - */ -static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ - (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ - (hi2c->XferISR != I2C_Mem_ISR_DMA)) - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if (InterruptRequest == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if (InterruptRequest == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - } - - else - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if (InterruptRequest == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if (InterruptRequest == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); - } - - if (InterruptRequest == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - } - - /* Enable interrupts only at the end */ - /* to avoid the risk of I2C interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_I2C_ENABLE_IT(hi2c, tmpisr); -} - -/** - * @brief Manage the disabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval None - */ -static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Disable TC and TXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Disable TC and RXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Disable ADDR, NACK and STOP interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if (InterruptRequest == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if (InterruptRequest == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if (InterruptRequest == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - - /* Disable interrupts only at the end */ - /* to avoid a breaking situation like at "t" time */ - /* all disable interrupts request are not done */ - __HAL_I2C_DISABLE_IT(hi2c, tmpisr); -} - -/** - * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) -{ - /* if user set XferOptions to I2C_OTHER_FRAME */ - /* it request implicitly to generate a restart condition */ - /* set XferOptions to I2C_FIRST_FRAME */ - if (hi2c->XferOptions == I2C_OTHER_FRAME) - { - hi2c->XferOptions = I2C_FIRST_FRAME; - } - /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ - /* it request implicitly to generate a restart condition */ - /* then generate a stop condition at the end of transfer */ - /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ - else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) - { - hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; - } - else - { - /* Nothing to do */ - } -} - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c.c + * @author MCD Application Team + * @brief I2C HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Inter Integrated Circuit (I2C) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The I2C HAL driver can be used as follows: + + (#) Declare a I2C_HandleTypeDef handle structure, for example: + I2C_HandleTypeDef hi2c; + + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: + (##) Enable the I2Cx interface clock + (##) I2C pins configuration + (+++) Enable the clock for the I2C GPIOs + (+++) Configure I2C pins as alternate function open-drain + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the I2Cx interrupt priority + (+++) Enable the NVIC I2C IRQ Channel + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive stream + (+++) Enable the DMAx interface clock using + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx stream + (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx stream + + (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, + Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. + + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. + + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() + + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() + + *** Polling mode IO MEM operation *** + ===================================== + [..] + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() + + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + + *** Interrupt mode or DMA mode IO sequential operation *** + ========================================================== + [..] + (@) These interfaces allow to manage a sequential transfer with a repeated start condition + when a direction change during transfer + [..] + (+) A specific option field manage the different steps of a sequential transfer + (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: + (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode + (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address + and data to transfer without a final stop condition + (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) + (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and without a final stop condition in both cases + (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address + and with new data to transfer if the direction change or manage only the new data to + transfer + if no direction change and with a final stop condition in both cases + (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option I2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. + Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit + without stopping the communication and so generate a restart condition. + (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential + interface. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_I2C_Master_Seq_Transmit_IT + or HAL_I2C_Master_Seq_Receive_IT + or HAL_I2C_Master_Seq_Transmit_DMA + or HAL_I2C_Master_Seq_Receive_DMA + with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. + Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. + + (+) Different sequential I2C interfaces are listed below: + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using + HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() + HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using + HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** Interrupt mode IO MEM operation *** + ======================================= + [..] + (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. + This action will inform Master to generate a Stop condition to discard the communication. + + *** DMA mode IO MEM operation *** + ================================= + [..] + (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() + (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_I2C_ErrorCallback() + + + *** I2C HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in I2C HAL driver. + + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode + (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + + *** Callback registration *** + ============================================= + [..] + The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() + to register an interrupt callback. + [..] + Function HAL_I2C_RegisterCallback() allows to register following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). + [..] + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default + weak function. + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) MasterTxCpltCallback : callback for Master transmission end of transfer. + (+) MasterRxCpltCallback : callback for Master reception end of transfer. + (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. + (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. + (+) ListenCpltCallback : callback for end of listen mode. + (+) MemTxCpltCallback : callback for Memory transmission end of transfer. + (+) MemRxCpltCallback : callback for Memory reception end of transfer. + (+) ErrorCallback : callback for error detection. + (+) AbortCpltCallback : callback for abort completion process. + (+) MspInitCallback : callback for Msp Init. + (+) MspDeInitCallback : callback for Msp DeInit. + [..] + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). + [..] + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. + [..] + When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + [..] + (@) You can refer to the I2C HAL driver header file for more useful macros + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2C I2C + * @brief I2C HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup I2C_Private_Define I2C Private Define + * @{ + */ +#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ +#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ +#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ +#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ + +#define MAX_NBYTE_SIZE 255U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U + +/* Private define for @ref PreviousState usage */ +#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ + (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) +/*!< Default Value */ +#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ + (uint32_t)HAL_I2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ + + +/* Private define to centralize the enable/disable of Interrupts */ +#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref I2C_XFER_LISTEN_IT */ +#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT + and @ref I2C_XFER_RX_IT */ + +#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ + +/* Private define Sequential Transfer Options default/reset value */ +#define I2C_NO_OPTION_FRAME (0xFFFF0000U) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_Private_Macro + * @{ + */ +/* Macro to get remaining data to transfer on DMA side */ +#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions to handle DMA transfer */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); +static void I2C_DMAError(DMA_HandleTypeDef *hdma); +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); + + +/* Private functions to handle IT transfer */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); + +/* Private functions to handle IT transfer */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions for I2C transfer IRQ handler */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources); + +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart); + +/* Private functions to centralize the enable/disable of Interrupts */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); + +/* Private function to treat different error callback */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); + +/* Private function to flush TXDR register */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); + +/* Private function to handle start, restart or stop a transfer */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request); + +/* Private function to Convert Specific options */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the I2Cx peripheral: + + (+) User must Implement HAL_I2C_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_I2C_Init() to configure the selected device with + the selected configuration: + (++) Clock Timing + (++) Own Address 1 + (++) Addressing mode (Master, Slave) + (++) Dual Addressing mode + (++) Own Address 2 + (++) Own Address 2 Mask + (++) General call mode + (++) Nostretch mode + + (+) Call the function HAL_I2C_DeInit() to restore the default configuration + of the selected I2Cx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the I2C according to the specified parameters + * in the I2C_InitTypeDef and initialize the associated handle. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); + assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); + assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); + assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); + assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); + assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); + + if (hi2c->State == HAL_I2C_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + /* Init the I2C Callback settings */ + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + + if (hi2c->MspInitCallback == NULL) + { + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + hi2c->MspInitCallback(hi2c); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2C_MspInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ + /* Configure I2Cx: Frequency range */ + hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Disable Own Address1 before set the Own Address1 configuration */ + hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; + + /* Configure I2Cx: Own Address1 and ack own address1 mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); + } + else /* I2C_ADDRESSINGMODE_10BIT */ + { + hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); + } + + /*---------------------------- I2Cx CR2 Configuration ----------------------*/ + /* Configure I2Cx: Addressing Master mode */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + else + { + /* Clear the I2C ADD10 bit */ + CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); + } + /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ + hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); + + /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ + /* Disable Own Address2 before set the Own Address2 configuration */ + hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; + + /* Configure I2Cx: Dual mode and Own Address2 */ + hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ + (hi2c->Init.OwnAddress2Masks << 8)); + + /*---------------------------- I2Cx CR1 Configuration ----------------------*/ + /* Configure I2Cx: Generalcall and NoStretch mode */ + hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); + + /* Enable the selected I2C peripheral */ + __HAL_I2C_ENABLE(hi2c); + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + return HAL_OK; +} + +/** + * @brief DeInitialize the I2C peripheral. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) +{ + /* Check the I2C handle allocation */ + if (hi2c == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the I2C Peripheral Clock */ + __HAL_I2C_DISABLE(hi2c); + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + if (hi2c->MspDeInitCallback == NULL) + { + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + hi2c->MspDeInitCallback(hi2c); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_I2C_MspDeInit(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Release Lock */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Initialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitialize the I2C MSP. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User I2C Callback + * To be used instead of the weak predefined callback + * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, + pI2C_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = pCallback; + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = pCallback; + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = pCallback; + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = pCallback; + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = pCallback; + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = pCallback; + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = pCallback; + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = pCallback; + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an I2C Callback + * I2C callback is redirected to the weak predefined callback + * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET + * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * This parameter can be one of the following values: + * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID + * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID + * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID + * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID + * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID + * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID + * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID + * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID + * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : + hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ + break; + + case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : + hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ + break; + + case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : + hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ + break; + + case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : + hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ + break; + + case HAL_I2C_LISTEN_COMPLETE_CB_ID : + hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ + break; + + case HAL_I2C_MEM_TX_COMPLETE_CB_ID : + hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ + break; + + case HAL_I2C_MEM_RX_COMPLETE_CB_ID : + hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ + break; + + case HAL_I2C_ERROR_CB_ID : + hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_I2C_ABORT_CB_ID : + hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_I2C_STATE_RESET == hi2c->State) + { + switch (CallbackID) + { + case HAL_I2C_MSPINIT_CB_ID : + hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_I2C_MSPDEINIT_CB_ID : + hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register the Slave Address Match I2C Callback + * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pCallback pointer to the Address Match Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = pCallback; + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the Slave Address Match I2C Callback + * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_I2C_STATE_READY == hi2c->State) + { + hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ + } + else + { + /* Update the error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the I2C data + transfers. + + (#) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (#) Blocking mode functions are : + (++) HAL_I2C_Master_Transmit() + (++) HAL_I2C_Master_Receive() + (++) HAL_I2C_Slave_Transmit() + (++) HAL_I2C_Slave_Receive() + (++) HAL_I2C_Mem_Write() + (++) HAL_I2C_Mem_Read() + (++) HAL_I2C_IsDeviceReady() + + (#) No-Blocking mode functions with Interrupt are : + (++) HAL_I2C_Master_Transmit_IT() + (++) HAL_I2C_Master_Receive_IT() + (++) HAL_I2C_Slave_Transmit_IT() + (++) HAL_I2C_Slave_Receive_IT() + (++) HAL_I2C_Mem_Write_IT() + (++) HAL_I2C_Mem_Read_IT() + (++) HAL_I2C_Master_Seq_Transmit_IT() + (++) HAL_I2C_Master_Seq_Receive_IT() + (++) HAL_I2C_Slave_Seq_Transmit_IT() + (++) HAL_I2C_Slave_Seq_Receive_IT() + (++) HAL_I2C_EnableListen_IT() + (++) HAL_I2C_DisableListen_IT() + (++) HAL_I2C_Master_Abort_IT() + + (#) No-Blocking mode functions with DMA are : + (++) HAL_I2C_Master_Transmit_DMA() + (++) HAL_I2C_Master_Receive_DMA() + (++) HAL_I2C_Slave_Transmit_DMA() + (++) HAL_I2C_Slave_Receive_DMA() + (++) HAL_I2C_Mem_Write_DMA() + (++) HAL_I2C_Mem_Read_DMA() + (++) HAL_I2C_Master_Seq_Transmit_DMA() + (++) HAL_I2C_Master_Seq_Receive_DMA() + (++) HAL_I2C_Slave_Seq_Transmit_DMA() + (++) HAL_I2C_Slave_Seq_Receive_DMA() + + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: + (++) HAL_I2C_MasterTxCpltCallback() + (++) HAL_I2C_MasterRxCpltCallback() + (++) HAL_I2C_SlaveTxCpltCallback() + (++) HAL_I2C_SlaveRxCpltCallback() + (++) HAL_I2C_MemTxCpltCallback() + (++) HAL_I2C_MemRxCpltCallback() + (++) HAL_I2C_AddrCallback() + (++) HAL_I2C_ListenCpltCallback() + (++) HAL_I2C_ErrorCallback() + (++) HAL_I2C_AbortCpltCallback() + +@endverbatim + * @{ + */ + +/** + * @brief Transmits in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_START_WRITE); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receives in master mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = 1U; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmits in slave mode an amount of data in blocking mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t tmpXferCount; + HAL_StatusTypeDef error; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* If 10bit addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Wait until DIR flag is set Transmitter mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + } + + /* Wait until AF flag is set */ + error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); + + if (error != HAL_OK) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + + tmpXferCount = hi2c->XferCount; + if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) + { + /* Reset ErrorCode to NONE */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + } + else + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear AF flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in blocking mode + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferISR = NULL; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Wait until ADDR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Wait until DIR flag is reset Receiver mode */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + while (hi2c->XferCount > 0U) + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Store Last receive data if any */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Wait until STOP flag is set */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Clear STOP flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Wait until BUSY flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + return HAL_ERROR; + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode, + I2C_GENERATE_START_WRITE); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, + I2C_GENERATE_START_WRITE); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_IT; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = 1U; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), + xfermode, I2C_GENERATE_START_WRITE); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE, + I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in master mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) +{ + uint32_t xfermode; + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Master_ISR_DMA; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = 1U; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = I2C_AUTOEND_MODE; + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address */ + /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + /* Preload TX data if no stretch enable */ + if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + + if (hi2c->XferCount != 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, + (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive in slave mode an amount of data in non-blocking mode with DMA + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in blocking mode to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + do + { + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in blocking mode from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferISR = NULL; + + /* Send Slave Address and Memory Address */ + if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = 1U; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, + I2C_GENERATE_START_READ); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + } + + do + { + /* Wait until RXNE flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = 1U; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, + I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_NO_STARTSTOP); + } + } + } while (hi2c->XferCount > 0U); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->XferSize = 0U; + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_IT; + hi2c->Devaddress = DevAddress; + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param pData Pointer to data buffer + * @param Size Amount of data to be read + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, + uint16_t MemAddSize, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MEM; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferISR = I2C_Mem_ISR_DMA; + hi2c->Devaddress = DevAddress; + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Prefetch Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); + } + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and Memory Address */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Checks if target device is ready for communication. + * @note This function is used with Memory devices + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param Trials Number of trials + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) +{ + uint32_t tickstart; + + __IO uint32_t I2C_Trials = 0UL; + + HAL_StatusTypeDef status = HAL_OK; + + FlagStatus tmp1; + FlagStatus tmp2; + + if (hi2c->State == HAL_I2C_STATE_READY) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + do + { + /* Generate Start */ + hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); + + /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ + /* Wait until STOPF flag is set or a NACK flag is set*/ + tickstart = HAL_GetTick(); + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + + while ((tmp1 == RESET) && (tmp2 == RESET)) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + + tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); + tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); + } + + /* Check if the NACKF flag has not been set */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) + { + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + else + { + status = HAL_ERROR; + } + } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + } + else + { + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + else + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + } + + /* Increment Trials */ + I2C_Trials++; + + if ((I2C_Trials < Trials) && (status == HAL_ERROR)) + { + status = HAL_OK; + } + + } while (I2C_Trials < Trials); + + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to write */ + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_WRITE; + HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_TX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \ + (XferOptions == I2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + sizetoxfer = hi2c->XferSize; + hi2c->XferCount--; + hi2c->XferSize--; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, + (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to write */ + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to write and generate START condition */ + if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME)) + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_IT; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t XferOptions) +{ + uint32_t xfermode; + uint32_t xferrequest = I2C_GENERATE_START_READ; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY_RX; + hi2c->Mode = HAL_I2C_MODE_MASTER; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Master_ISR_DMA; + + /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + xfermode = hi2c->XferOptions; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ + /* Mean Previous state is same as current state */ + if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ + (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + { + xferrequest = I2C_NO_STARTSTOP; + } + else + { + /* Convert OTHER_xxx XferOptions if any */ + I2C_ConvertOtherXferOptions(hi2c); + + /* Update xfermode accordingly if no reload is necessary */ + if (hi2c->XferCount <= MAX_NBYTE_SIZE) + { + xfermode = hi2c->XferOptions; + } + } + + if (hi2c->XferSize > 0U) + { + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Send Slave Address and set NBYTES to read */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR and NACK interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + else + { + /* Update Transfer ISR function pointer */ + hi2c->XferISR = I2C_Master_ISR_IT; + + /* Send Slave Address */ + /* Set NBYTES to read and generate START condition */ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, + I2C_GENERATE_START_READ); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, TC, STOP, NACK, RXI interrupt */ + /* possible to enable all of these */ + /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | + I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Abort DMA Xfer if any */ + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave RX state to TX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; + + /* Set the DMA error callback */ + hi2c->hdmatx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmatx->XferHalfCpltCallback = NULL; + hi2c->hdmatx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* Enable ERR, STOP, NACK, ADDR interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_IT; + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA + * @note This interface allow to manage repeated start condition when a direction change during transfer + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, + uint32_t XferOptions) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + HAL_StatusTypeDef dmaxferstatus; + + /* Check the parameters */ + assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + if ((pData == NULL) || (Size == 0U)) + { + hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; + return HAL_ERROR; + } + + /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ + /* and then toggle the HAL slave TX state to RX state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Disable associated Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + /* Abort DMA Xfer if any */ + if (hi2c->hdmatx != NULL) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + } + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Abort DMA Xfer if any */ + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + } + } + else + { + /* Nothing to do */ + } + + hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; + hi2c->Mode = HAL_I2C_MODE_SLAVE; + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + + /* Enable Address Acknowledge */ + hi2c->Instance->CR2 &= ~I2C_CR2_NACK; + + /* Prepare transfer parameters */ + hi2c->pBuffPtr = pData; + hi2c->XferCount = Size; + hi2c->XferSize = hi2c->XferCount; + hi2c->XferOptions = XferOptions; + hi2c->XferISR = I2C_Slave_ISR_DMA; + + if (hi2c->hdmarx != NULL) + { + /* Set the I2C DMA transfer complete callback */ + hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; + + /* Set the DMA error callback */ + hi2c->hdmarx->XferErrorCallback = I2C_DMAError; + + /* Set the unused DMA callbacks to NULL */ + hi2c->hdmarx->XferHalfCpltCallback = NULL; + hi2c->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA stream */ + dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, + (uint32_t)pData, hi2c->XferSize); + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + if (dmaxferstatus == HAL_OK) + { + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Reset XferSize */ + hi2c->XferSize = 0; + } + else + { + /* Update I2C state */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Update I2C error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + + tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); + if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) + { + /* Clear ADDR flag after prepare the transfer parameters */ + /* This action will generate an acknowledge to the Master */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Enable DMA Request */ + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + /* REnable ADDR interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_READY) + { + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + + /* Enable the Address Match interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the Address listen mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) +{ + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp; + + /* Disable Address listen mode only if a transfer is not ongoing */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; + hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Disable the Address Match interrupt */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) +{ + HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; + + if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Set State at HAL_I2C_STATE_ABORT */ + hi2c->State = HAL_I2C_STATE_ABORT; + + /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ + /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ + I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Note : The I2C interrupts must be enabled after unlocking current process + to avoid the risk of I2C interrupt handle execution before current + process unlock */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + return HAL_OK; + } + else + { + /* Wrong usage of abort function */ + /* This function should be used only in case of abort monitored by master device */ + return HAL_ERROR; + } +} + +/** + * @} + */ + +/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ + +/** + * @brief This function handles I2C event interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ +{ + /* Get current IT Flags and IT sources value */ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + + /* I2C events treatment -------------------------------------*/ + if (hi2c->XferISR != NULL) + { + hi2c->XferISR(hi2c, itflags, itsources); + } +} + +/** + * @brief This function handles I2C error interrupt request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) +{ + uint32_t itflags = READ_REG(hi2c->Instance->ISR); + uint32_t itsources = READ_REG(hi2c->Instance->CR1); + uint32_t tmperror; + + /* I2C Bus error interrupt occurred ------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + } + + /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + } + + /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ + if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ + (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + } + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the Error Callback in case of Error detected */ + if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) + { + I2C_ITError(hi2c, tmperror); + } +} + +/** + * @brief Master Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Master Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MasterRxCpltCallback could be implemented in the user file + */ +} + +/** @brief Slave Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Slave Address Match callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION + * @param AddrMatchCode Address Match Code + * @retval None + */ +__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + UNUSED(TransferDirection); + UNUSED(AddrMatchCode); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AddrCallback() could be implemented in the user file + */ +} + +/** + * @brief Listen Complete callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ListenCpltCallback() could be implemented in the user file + */ +} + +/** + * @brief Memory Tx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemTxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Memory Rx Transfer completed callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_MemRxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief I2C error callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief I2C abort callback. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval None + */ +__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hi2c); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_I2C_AbortCpltCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions + * @brief Peripheral State, Mode and Error functions + * +@verbatim + =============================================================================== + ##### Peripheral State, Mode and Error functions ##### + =============================================================================== + [..] + This subsection permit to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the I2C handle state. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval HAL state + */ +HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) +{ + /* Return I2C handle state */ + return hi2c->State; +} + +/** + * @brief Returns the I2C Master, Slave, Memory or no mode. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for I2C module + * @retval HAL mode + */ +HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->Mode; +} + +/** + * @brief Return the I2C error code. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @retval I2C Error Code + */ +uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) +{ + return hi2c->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \ + ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))) + { + /* Write data to TXDR */ + if (hi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + hi2c->XferOptions, I2C_NO_STARTSTOP); + } + else + { + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + if (hi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) + { + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t tmpITFlags = ITFlags; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) + { + if (hi2c->XferCount > 0U) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferSize--; + hi2c->XferCount--; + } + + if ((hi2c->XferCount == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, tmpITFlags); + } + else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write data to TXDR only if XferCount not reach "0" */ + /* A TXIS flag can be set, during STOP treatment */ + /* Check if all Data have already been sent */ + /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ + if (hi2c->XferCount > 0U) + { + /* Write data to TXDR */ + hi2c->Instance->TXDR = *hi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + hi2c->XferCount--; + hi2c->XferSize--; + } + else + { + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint16_t devaddress; + uint32_t xfermode; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable TC interrupt */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); + + if (hi2c->XferCount != 0U) + { + /* Recover Slave address */ + devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); + + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + xfermode = I2C_RELOAD_MODE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + xfermode = hi2c->XferOptions; + } + else + { + xfermode = I2C_AUTOEND_MODE; + } + } + + /* Set the new XferSize in Nbytes register */ + I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Call TxCpltCallback() if no stop mode is set */ + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + if (hi2c->XferCount == 0U) + { + if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) + { + /* Generate a stop condition in case of no transfer option */ + if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + } + else + { + /* Call I2C Master Sequential complete process */ + I2C_ITMasterSeqCplt(hi2c); + } + } + } + else + { + /* Wrong size Status regarding TC flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = I2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hi2c); + + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set corresponding Error Code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hi2c->Instance->TXDR = hi2c->Memaddress; + + /* Reset Memaddress content */ + hi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, I2C_NO_STARTSTOP); + } + else + { + hi2c->XferSize = hi2c->XferCount; + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) + { + /* Disable Interrupt related to address step */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Enable only Error and NACK interrupt for data transfer */ + I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); + + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + direction = I2C_GENERATE_START_READ; + } + + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + + /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_RELOAD_MODE, direction); + } + else + { + hi2c->XferSize = hi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, + I2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hi2c->XferCount -= hi2c->XferSize; + + /* Enable DMA Request */ + if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; + } + else + { + hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Master complete process */ + I2C_ITMasterCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t tmpoptions = hi2c->XferOptions; + uint32_t treatdmanack = 0U; + HAL_I2C_StateTypeDef tmpstate; + + /* Process locked */ + __HAL_LOCK(hi2c); + + /* Check if STOPF is set */ + if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) + { + /* Call I2C Slave complete process */ + I2C_ITSlaveCplt(hi2c, ITFlags); + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0 */ + /* So clear Flag NACKF only */ + if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || + (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) + { + /* Split check of hdmarx, for MISRA compliance */ + if (hi2c->hdmarx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmanack = 1U; + } + } + } + + /* Split check of hdmatx, for MISRA compliance */ + if (hi2c->hdmatx != NULL) + { + if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmanack = 1U; + } + } + } + + if (treatdmanack == 1U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, ITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ + tmpstate = hi2c->State; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + else + { + /* Only Clear NACK Flag, no DMA treatment is pending */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ + (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) + { + I2C_ITAddrCplt(hi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for write request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TCR flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Master sends target device address followed by internal memory address for read request. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param DevAddress Target device address: The device 7 bits address value + * in datasheet must be shifted to the left before calling the interface + * @param MemAddress Internal memory address + * @param MemAddSize Size of internal memory address + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) +{ + I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* If Memory address size is 8Bit */ + if (MemAddSize == I2C_MEMADD_SIZE_8BIT) + { + /* Send Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + /* If Memory address size is 16Bit */ + else + { + /* Send MSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); + + /* Wait until TXIS flag is set */ + if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Send LSB of Memory Address */ + hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); + } + + /* Wait until TC flag is set */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief I2C Address complete process callback. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint8_t transferdirection; + uint16_t slaveaddrcode; + uint16_t ownadd1code; + uint16_t ownadd2code; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(ITFlags); + + /* In case of Listen state, need to inform upper layer of address match code event */ + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) + { + transferdirection = I2C_GET_DIR(hi2c); + slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); + ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); + ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); + + /* If 10bits addressing mode is selected */ + if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) + { + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) + { + slaveaddrcode = ownadd1code; + hi2c->AddrEventCount++; + if (hi2c->AddrEventCount == 2U) + { + /* Reset Address Event counter */ + hi2c->AddrEventCount = 0U; + + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + slaveaddrcode = ownadd2code; + + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* else 7 bits addressing mode is selected */ + else + { + /* Disable ADDR Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call Slave Addr callback */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); +#else + HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* Else clear address flag only */ + else + { + /* Clear ADDR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } +} + +/** + * @brief I2C Master sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) +{ + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* No Generate Stop, to permit restart mode */ + /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + hi2c->XferISR = NULL; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Slave sequential complete process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + + /* Reset I2C handle mode */ + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + else + { + /* Do nothing */ + } + + if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) + { + /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + + /* Disable Interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Master complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmperror; + uint32_t tmpITFlags = ITFlags; + __IO uint32_t tmpreg; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; + } + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; + } + else + { + /* Do nothing */ + } + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Reset handle parameters */ + hi2c->XferISR = NULL; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set acknowledge error code */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Fetch Last receive data if any */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) + { + /* Read data from RXDR */ + tmpreg = (uint8_t)hi2c->Instance->RXDR; + UNUSED(tmpreg); + } + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Store current volatile hi2c->ErrorCode, misra rule */ + tmperror = hi2c->ErrorCode; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterTxCpltCallback(hi2c); +#else + HAL_I2C_MasterTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemRxCpltCallback(hi2c); +#else + HAL_I2C_MemRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MasterRxCpltCallback(hi2c); +#else + HAL_I2C_MasterRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief I2C Slave complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); + uint32_t tmpITFlags = ITFlags; + uint32_t tmpoptions = hi2c->XferOptions; + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Disable Interrupts and Store Previous state */ + if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; + } + else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; + } + else if (tmpstate == HAL_I2C_STATE_LISTEN) + { + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); + hi2c->PreviousState = I2C_STATE_NONE; + } + else + { + /* Do nothing */ + } + + /* Disable Address Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If a DMA is ongoing, Update handle size context */ + if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + if (hi2c->hdmatx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); + } + } + else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + if (hi2c->hdmarx != NULL) + { + hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); + } + } + else + { + /* Do nothing */ + } + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~I2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if (hi2c->XferSize > 0U) + { + hi2c->XferSize--; + hi2c->XferCount--; + } + } + + /* All data are not transferred, so set error code accordingly */ + if (hi2c->XferCount != 0U) + { + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ + (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) + { + /* Check that I2C transfer finished */ + /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ + /* Mean XferCount == 0*/ + /* So clear Flag NACKF only */ + if (hi2c->XferCount == 0U) + { + if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + } + } + else + { + /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + + if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + } + } + } + + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, hi2c->ErrorCode); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ + if (hi2c->State == HAL_I2C_STATE_LISTEN) + { + /* Call I2C Listen complete process */ + I2C_ITListenCplt(hi2c, tmpITFlags); + } + } + else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) + { + /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ + I2C_ITSlaveSeqCplt(hi2c); + + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + /* Call the corresponding callback to inform upper layer of End of Transfer */ + else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveRxCpltCallback(hi2c); +#else + HAL_I2C_SlaveRxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->SlaveTxCpltCallback(hi2c); +#else + HAL_I2C_SlaveTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Listen complete process. + * @param hi2c I2C handle. + * @param ITFlags Interrupt flags to handle. + * @retval None + */ +static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) +{ + /* Reset handle parameters */ + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferISR = NULL; + + /* Store Last receive data if any */ + if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) + { + /* Read data from RXDR */ + *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hi2c->pBuffPtr++; + + if (hi2c->XferSize > 0U) + { + hi2c->XferSize--; + hi2c->XferCount--; + + /* Set ErrorCode corresponding to a Non-Acknowledge */ + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + } + + /* Disable all Interrupts*/ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Clear NACK Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ListenCpltCallback(hi2c); +#else + HAL_I2C_ListenCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +} + +/** + * @brief I2C interrupts error process. + * @param hi2c I2C handle. + * @param ErrorCode Error code to handle. + * @retval None + */ +static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) +{ + HAL_I2C_StateTypeDef tmpstate = hi2c->State; + + uint32_t tmppreviousstate; + + /* Reset handle parameters */ + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->XferCount = 0U; + + /* Set new error code */ + hi2c->ErrorCode |= ErrorCode; + + /* Disable Interrupts */ + if ((tmpstate == HAL_I2C_STATE_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || + (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) + { + /* Disable all interrupts, except interrupts related to LISTEN state */ + I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* keep HAL_I2C_STATE_LISTEN if set */ + hi2c->State = HAL_I2C_STATE_LISTEN; + hi2c->XferISR = I2C_Slave_ISR_IT; + } + else + { + /* Disable all interrupts */ + I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); + + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* If state is an abort treatment on going, don't change state */ + /* This change will be do later */ + if (hi2c->State != HAL_I2C_STATE_ABORT) + { + /* Set HAL_I2C_STATE_READY */ + hi2c->State = HAL_I2C_STATE_READY; + + /* Check if a STOPF is detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode |= HAL_I2C_ERROR_AF; + } + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + } + hi2c->XferISR = NULL; + } + + /* Abort DMA TX transfer if any */ + tmppreviousstate = hi2c->PreviousState; + + if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) + { + /* Call Directly XferAbortCallback function in case of error */ + hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + /* Abort DMA RX transfer if any */ + else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ + (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) + { + if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) + { + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + } + + if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) + { + /* Set the I2C DMA Abort callback : + will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ + hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) + { + /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ + hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } + } + else + { + I2C_TreatErrorCallback(hi2c); + } +} + +/** + * @brief I2C Error callback treatment. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) +{ + if (hi2c->State == HAL_I2C_STATE_ABORT) + { + hi2c->State = HAL_I2C_STATE_READY; + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->AbortCpltCallback(hi2c); +#else + HAL_I2C_AbortCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->PreviousState = I2C_STATE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + /* Call the corresponding callback to inform upper layer of End of Transfer */ +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->ErrorCallback(hi2c); +#else + HAL_I2C_ErrorCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } +} + +/** + * @brief I2C Tx data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) + { + hi2c->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); + } +} + +/** + * @brief DMA I2C master transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave transmit process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; + + /* Last Byte is Transmitted */ + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C master receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* If last transfer, enable STOP interrupt */ + if (hi2c->XferCount == 0U) + { + /* Enable STOP interrupt */ + I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); + } + /* else prepare a new DMA transfer and enable TCReload interrupt */ + else + { + /* Update Buffer pointer */ + hi2c->pBuffPtr += hi2c->XferSize; + + /* Set the XferSize to transfer */ + if (hi2c->XferCount > MAX_NBYTE_SIZE) + { + /* Errata workaround 170323 */ + if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) + { + hi2c->XferSize = 1U; + } + else + { + hi2c->XferSize = MAX_NBYTE_SIZE; + } + } + else + { + hi2c->XferSize = hi2c->XferCount; + } + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, + hi2c->XferSize) != HAL_OK) + { + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } + else + { + /* Enable TC interrupts */ + I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); + } + } +} + + +/** + * @brief DMA I2C slave receive process complete callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tmpoptions = hi2c->XferOptions; + + if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ + (tmpoptions != I2C_NO_OPTION_FRAME)) + { + /* Disable DMA Request */ + hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; + + /* Call I2C Slave Sequential complete process */ + I2C_ITSlaveSeqCplt(hi2c); + } + else + { + /* No specific action, Master fully manage the generation of STOP condition */ + /* Mean that this generation can arrive at any time, at the end or during DMA process */ + /* So STOP condition should be manage through Interrupt treatment */ + } +} + + +/** + * @brief DMA I2C communication error callback. + * @param hdma DMA handle + * @retval None + */ +static void I2C_DMAError(DMA_HandleTypeDef *hdma) +{ + uint32_t treatdmaerror = 0U; + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + if (hi2c->hdmatx != NULL) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) + { + treatdmaerror = 1U; + } + } + + if (hi2c->hdmarx != NULL) + { + if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) + { + treatdmaerror = 1U; + } + } + + /* Check if a FIFO error is detected, if true normal use case, so no specific action to perform */ + if (!((HAL_DMA_GetError(hdma) == HAL_DMA_ERROR_FE)) && (treatdmaerror != 0U)) + { + /* Disable Acknowledge */ + hi2c->Instance->CR2 |= I2C_CR2_NACK; + + /* Call the corresponding callback to inform upper layer of End of Transfer */ + I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); + } +} + + +/** + * @brief DMA I2C communication abort callback + * (To be called at end of DMA Abort procedure). + * @param hdma DMA handle. + * @retval None + */ +static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) +{ + /* Derogation MISRAC2012-Rule-11.5 */ + I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Reset AbortCpltCallback */ + if (hi2c->hdmatx != NULL) + { + hi2c->hdmatx->XferAbortCallback = NULL; + } + if (hi2c->hdmarx != NULL) + { + hi2c->hdmarx->XferAbortCallback = NULL; + } + + I2C_TreatErrorCallback(hi2c); +} + + +/** + * @brief This function handles I2C Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Flag Specifies the I2C flag to check. + * @param Status The actual Flag status (SET or RESET). + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, + uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) + { + /* Check if an error is detected */ + if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) + { + status = HAL_ERROR; + } + + /* Check if a STOPF is detected */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) + { + /* Check if an RXNE is pending */ + /* Store Last receive data if any */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) + { + /* Return HAL_OK */ + /* The Reading of data from RXDR will be done in caller function */ + status = HAL_OK; + } + + /* Check a no-acknowledge have been detected */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) + { + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + hi2c->ErrorCode = HAL_I2C_ERROR_AF; + + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + else + { + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } + } + + /* Check for the Timeout */ + if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) + { + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) + { + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + status = HAL_ERROR; + } + } + } + return status; +} + +/** + * @brief This function handles errors detection during an I2C Communication. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param Timeout Timeout duration + * @param Tickstart Tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_I2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) + { + /* Clear NACKF Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ + /* AutoEnd should be initiate after AF */ + while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); + tmp2 = hi2c->Mode; + + /* In case of I2C still busy, try to regenerate a STOP manually */ + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ + (tmp1 != I2C_CR2_STOP) && \ + (tmp2 != HAL_I2C_MODE_SLAVE)) + { + /* Generate Stop */ + hi2c->Instance->CR2 |= I2C_CR2_STOP; + + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) + { + error_code |= HAL_I2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } + } + } + } + + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } + + error_code |= HAL_I2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) + { + error_code |= HAL_I2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); + + status = HAL_ERROR; + } + + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) + { + error_code |= HAL_I2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) + { + error_code |= HAL_I2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { + /* Flush TX register */ + I2C_Flush_TXDR(hi2c); + + /* Clear Configuration Register 2 */ + I2C_RESET_CR2(hi2c); + + hi2c->ErrorCode |= error_code; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + } + + return status; +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param hi2c I2C handle. + * @param DevAddress Specifies the slave address to be programmed. + * @param Size Specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param Mode New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_RELOAD_MODE Enable Reload mode . + * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. + * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. + * @param Request New state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. + * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). + * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. + * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. + * @retval None + */ +static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, + uint32_t Request) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_TRANSFER_MODE(Mode)); + assert_param(IS_TRANSFER_REQUEST(Request)); + + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + + /* update CR2 register */ + MODIFY_REG(hi2c->Instance->CR2, \ + ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ + (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ + I2C_CR2_START | I2C_CR2_STOP)), tmp); +} + +/** + * @brief Manage the enabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ + (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ + (hi2c->XferISR != I2C_Mem_ISR_DMA)) + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + } + + else + { + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Enable ERR, STOP, NACK and ADDR interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Enable ERR, TC, STOP, NACK and TXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Enable ERR, TC, STOP, NACK and RXI interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + } + + /* Enable interrupts only at the end */ + /* to avoid the risk of I2C interrupt handle execution before */ + /* all interrupts requested done */ + __HAL_I2C_ENABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Manage the disabling of Interrupts. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. + * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. + * @retval None + */ +static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) +{ + uint32_t tmpisr = 0U; + + if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) + { + /* Disable TC and TXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_TXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) + { + /* Disable TC and RXI interrupts */ + tmpisr |= I2C_IT_TCI | I2C_IT_RXI; + + if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) + { + /* Disable NACK and STOP interrupts */ + tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + } + + if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) + { + /* Disable ADDR, NACK and STOP interrupts */ + tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; + } + + if (InterruptRequest == I2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; + } + + if (InterruptRequest == I2C_XFER_CPLT_IT) + { + /* Enable STOP interrupts */ + tmpisr |= I2C_IT_STOPI; + } + + if (InterruptRequest == I2C_XFER_RELOAD_IT) + { + /* Enable TC interrupts */ + tmpisr |= I2C_IT_TCI; + } + + /* Disable interrupts only at the end */ + /* to avoid a breaking situation like at "t" time */ + /* all disable interrupts request are not done */ + __HAL_I2C_DISABLE_IT(hi2c, tmpisr); +} + +/** + * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) +{ + /* if user set XferOptions to I2C_OTHER_FRAME */ + /* it request implicitly to generate a restart condition */ + /* set XferOptions to I2C_FIRST_FRAME */ + if (hi2c->XferOptions == I2C_OTHER_FRAME) + { + hi2c->XferOptions = I2C_FIRST_FRAME; + } + /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ + /* it request implicitly to generate a restart condition */ + /* then generate a stop condition at the end of transfer */ + /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ + else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) + { + hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; + } + else + { + /* Nothing to do */ + } +} + +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c index 035731f4..9c8450ed 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2c_ex.c @@ -1,270 +1,270 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2c_ex.c - * @author MCD Application Team - * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of I2C Extended peripheral: - * + Filter Mode Functions - * + FastModePlus Functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### I2C peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32F7xx - devices contains the following additional features - - (+) Possibility to disable or enable Analog Noise Filter - (+) Use of a configured Digital Noise Filter - (+) Disable or enable Fast Mode Plus - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to: - (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() - (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() - (#) Configure the enable or disable of fast mode plus driving capability using the functions : - (++) HAL_I2CEx_EnableFastModePlus() - (++) HAL_I2CEx_DisableFastModePlus() - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup I2CEx I2CEx - * @brief I2C Extended HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions - * @brief Filter Mode Functions - * -@verbatim - =============================================================================== - ##### Filter Mode Functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Noise Filters - -@endverbatim - * @{ - */ - -/** - * @brief Configure I2C Analog noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter New state of the Analog filter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hi2c->Instance->CR1 |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure I2C Digital noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->CR1; - - /* Reset I2Cx DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8U; - - /* Store the new register value */ - hi2c->Instance->CR1 = tmpreg; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @} - */ -#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) - -/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions - * @brief Fast Mode Plus Functions - * -@verbatim - =============================================================================== - ##### Fast Mode Plus Functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Fast Mode Plus - -@endverbatim - * @{ - */ - -/** - * @brief Enable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @note For all I2C3 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C3 parameter. - * @note For all I2C4 pins fast mode plus driving capability can be enabled - * only by using I2C_FASTMODEPLUS_I2C4 parameter. - * @retval None - */ -void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Enable fast mode plus driving capability for selected pin */ - SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); -} - -/** - * @brief Disable the I2C fast mode plus driving capability. - * @param ConfigFastModePlus Selects the pin. - * This parameter can be one of the @ref I2CEx_FastModePlus values - * @note For I2C1, fast mode plus driving capability can be disabled on all selected - * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C2 parameter. - * @note For all I2C3 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C3 parameter. - * @note For all I2C4 pins fast mode plus driving capability can be disabled - * only by using I2C_FASTMODEPLUS_I2C4 parameter. - * @retval None - */ -void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - /* Check the parameter */ - assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); - - /* Enable SYSCFG clock */ - __HAL_RCC_SYSCFG_CLK_ENABLE(); - - /* Disable fast mode plus driving capability for selected pin */ - CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); -} -/** - * @} - */ -#endif /* Fast Mode Plus Availability */ -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_i2c_ex.c + * @author MCD Application Team + * @brief I2C Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of I2C Extended peripheral: + * + Filter Mode Functions + * + FastModePlus Functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### I2C peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the I2C interface for STM32F7xx + devices contains the following additional features + + (+) Possibility to disable or enable Analog Noise Filter + (+) Use of a configured Digital Noise Filter + (+) Disable or enable Fast Mode Plus + + ##### How to use this driver ##### + ============================================================================== + [..] This driver provides functions to: + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + (++) HAL_I2CEx_EnableFastModePlus() + (++) HAL_I2CEx_DisableFastModePlus() + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup I2CEx I2CEx + * @brief I2C Extended HAL module driver + * @{ + */ + +#ifdef HAL_I2C_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions + * @{ + */ + +/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions + * +@verbatim + =============================================================================== + ##### Filter Mode Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Noise Filters + +@endverbatim + * @{ + */ + +/** + * @brief Configure I2C Analog noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param AnalogFilter New state of the Analog filter. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Reset I2Cx ANOFF bit */ + hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); + + /* Set analog filter bit*/ + hi2c->Instance->CR1 |= AnalogFilter; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Configure I2C Digital noise filter. + * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2Cx peripheral. + * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); + assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); + + if (hi2c->State == HAL_I2C_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hi2c); + + hi2c->State = HAL_I2C_STATE_BUSY; + + /* Disable the selected I2C peripheral */ + __HAL_I2C_DISABLE(hi2c); + + /* Get the old register value */ + tmpreg = hi2c->Instance->CR1; + + /* Reset I2Cx DNF bits [11:8] */ + tmpreg &= ~(I2C_CR1_DNF); + + /* Set I2Cx DNF coefficient */ + tmpreg |= DigitalFilter << 8U; + + /* Store the new register value */ + hi2c->Instance->CR1 = tmpreg; + + __HAL_I2C_ENABLE(hi2c); + + hi2c->State = HAL_I2C_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} +/** + * @} + */ +#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP) + +/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ + +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus Selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @note For all I2C4 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C4 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus); +} +/** + * @} + */ +#endif /* Fast Mode Plus Availability */ +/** + * @} + */ + +#endif /* HAL_I2C_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c deleted file mode 100644 index 5538c4b3..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_i2s.c +++ /dev/null @@ -1,1924 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_i2s.c - * @author MCD Application Team - * @brief I2S HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Integrated Interchip Sound (I2S) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The I2S HAL driver can be used as follow: - - (#) Declare a I2S_HandleTypeDef handle structure. - (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: - (##) Enable the SPIx interface clock. - (##) I2S pins configuration: - (+++) Enable the clock for the I2S GPIOs. - (+++) Configure these I2S pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() - and HAL_I2S_Receive_IT() APIs). - (+++) Configure the I2Sx interrupt priority. - (+++) Enable the NVIC I2S IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() - and HAL_I2S_Receive_DMA() APIs: - (+++) Declare a DMA handle structure for the Tx/Rx Stream/Channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream/Channel. - (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA Tx/Rx Stream/Channel. - - (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity - using HAL_I2S_Init() function. - - -@- The specific I2S interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. - -@- Make sure that either: - (+@) I2S clock is configured based on SYSCLK or - (+@) External clock source is configured after setting correctly - the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file. - - (#) Three mode of operations are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() - (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2S_ErrorCallback - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() - (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() - (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_I2S_ErrorCallback - (+) Pause the DMA Transfer using HAL_I2S_DMAPause() - (+) Resume the DMA Transfer using HAL_I2S_DMAResume() - (+) Stop the DMA Transfer using HAL_I2S_DMAStop() - In Slave mode, if HAL_I2S_DMAStop is used to stop the communication, an error - HAL_I2S_ERROR_BUSY_LINE_RX is raised as the master continue to transmit data. - In this case __HAL_I2S_FLUSH_RX_DR macro must be used to flush the remaining data - inside DR register and avoid using DeInit/Init process for the next transfer. - - *** I2S HAL driver macros list *** - =================================== - [..] - Below the list of most used macros in I2S HAL driver. - - (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) - (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts - (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts - (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not - (+) __HAL_I2S_FLUSH_RX_DR: Read DR Register to Flush RX Data - - [..] - (@) You can refer to the I2S HAL driver header file for more useful macros - - *** I2S HAL driver macros list *** - =================================== - [..] - Callback registration: - - (#) The compilation flag USE_HAL_I2S_REGISTER_CALLBACKS when set to 1U - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_I2S_RegisterCallback() to register an interrupt callback. - - Function HAL_I2S_RegisterCallback() allows to register following callbacks: - (++) TxCpltCallback : I2S Tx Completed callback - (++) RxCpltCallback : I2S Rx Completed callback - (++) TxHalfCpltCallback : I2S Tx Half Completed callback - (++) RxHalfCpltCallback : I2S Rx Half Completed callback - (++) ErrorCallback : I2S Error callback - (++) MspInitCallback : I2S Msp Init callback - (++) MspDeInitCallback : I2S Msp DeInit callback - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - - (#) Use function HAL_I2S_UnRegisterCallback to reset a callback to the default - weak function. - HAL_I2S_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (++) TxCpltCallback : I2S Tx Completed callback - (++) RxCpltCallback : I2S Rx Completed callback - (++) TxHalfCpltCallback : I2S Tx Half Completed callback - (++) RxHalfCpltCallback : I2S Rx Half Completed callback - (++) ErrorCallback : I2S Error callback - (++) MspInitCallback : I2S Msp Init callback - (++) MspDeInitCallback : I2S Msp DeInit callback - - [..] - By default, after the HAL_I2S_Init() and when the state is HAL_I2S_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_I2S_MasterTxCpltCallback(), HAL_I2S_MasterRxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_I2S_Init()/ HAL_I2S_DeInit() only when - these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the HAL_I2S_Init()/ HAL_I2S_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - - [..] - Callbacks can be registered/unregistered in HAL_I2S_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_I2S_STATE_READY or HAL_I2S_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_I2S_RegisterCallback() before calling HAL_I2S_DeInit() - or HAL_I2S_Init() function. - - [..] - When the compilation define USE_HAL_I2S_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. - - @endverbatim - - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -#ifdef HAL_I2S_MODULE_ENABLED - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup I2S I2S - * @brief I2S HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define I2S_TIMEOUT_FLAG 100U /*!< Timeout 100 ms */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup I2S_Private_Functions I2S Private Functions - * @{ - */ -static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void I2S_DMAError(DMA_HandleTypeDef *hdma); -static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); -static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); -static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s); -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, - uint32_t Timeout); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup I2S_Exported_Functions I2S Exported Functions - * @{ - */ - -/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the I2Sx peripheral in simplex mode: - - (+) User must Implement HAL_I2S_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2S_Init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Standard - (++) Data Format - (++) MCLK Output - (++) Audio frequency - (++) Polarity - - (+) Call the function HAL_I2S_DeInit() to restore the default configuration - of the selected I2Sx peripheral. - @endverbatim - * @{ - */ - -/** - * @brief Initializes the I2S according to the specified parameters - * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) -{ - uint32_t i2sdiv; - uint32_t i2sodd; - uint32_t packetlength; - uint32_t tmp; - uint32_t i2sclk; - - /* Check the I2S handle allocation */ - if (hi2s == NULL) - { - return HAL_ERROR; - } - - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); - assert_param(IS_I2S_MODE(hi2s->Init.Mode)); - assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); - assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); - assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); - assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); - assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); - assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource)); - - if (hi2s->State == HAL_I2S_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2s->Lock = HAL_UNLOCKED; - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - /* Init the I2S Callback settings */ - hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hi2s->MspInitCallback == NULL) - { - hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - hi2s->MspInitCallback(hi2s); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2S_MspInit(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - } - - hi2s->State = HAL_I2S_STATE_BUSY; - - /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - CLEAR_BIT(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ - SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ - SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); - hi2s->Instance->I2SPR = 0x0002U; - - /*----------------------- I2SPR: I2SDIV and ODD Calculation -----------------*/ - /* If the requested audio frequency is not the default, compute the prescaler */ - if (hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) - { - /* Check the frame length (For the Prescaler computing) ********************/ - if (hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) - { - /* Packet length is 16 bits */ - packetlength = 16U; - } - else - { - /* Packet length is 32 bits */ - packetlength = 32U; - } - - /* I2S standard */ - if (hi2s->Init.Standard <= I2S_STANDARD_LSB) - { - /* In I2S standard packet length is multiplied by 2 */ - packetlength = packetlength * 2U; - } - - /* If an external I2S clock has to be used, the specific define should be set - in the project configuration or in the stm32f3xx_conf.h file */ - if (hi2s->Init.ClockSource == I2S_CLOCK_EXTERNAL) - { - /* Set the I2S clock to the external clock value */ - i2sclk = EXTERNAL_CLOCK_VALUE; - } - else - { - /* Get the I2S source clock value */ - i2sclk = I2S_GetClockFreq(hi2s); - } - - /* Compute the Real divider depending on the MCLK output state, with a floating point */ - if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) - { - /* MCLK output is enabled */ - if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) - { - tmp = (uint32_t)(((((i2sclk / (packetlength * 4U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); - } - else - { - tmp = (uint32_t)(((((i2sclk / (packetlength * 8U)) * 10U) / hi2s->Init.AudioFreq)) + 5U); - } - } - else - { - /* MCLK output is disabled */ - tmp = (uint32_t)(((((i2sclk / packetlength) * 10U) / hi2s->Init.AudioFreq)) + 5U); - } - - /* Remove the flatting point */ - tmp = tmp / 10U; - - /* Check the parity of the divider */ - i2sodd = (uint32_t)(tmp & (uint32_t)1U); - - /* Compute the i2sdiv prescaler */ - i2sdiv = (uint32_t)((tmp - i2sodd) / 2U); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (uint32_t)(i2sodd << 8U); - } - else - { - /* Set the default values */ - i2sdiv = 2U; - i2sodd = 0U; - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) - { - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); - return HAL_ERROR; - } - - /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ - - /* Write to SPIx I2SPR register the computed value */ - hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); - - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - /* And configure the I2S with the I2S_InitStruct values */ - MODIFY_REG(hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ - SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ - SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ - SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD), \ - (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | \ - hi2s->Init.Standard | hi2s->Init.DataFormat | \ - hi2s->Init.CPOL)); - -#if defined(SPI_I2SCFGR_ASTRTEN) - if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) || ((hi2s->Init.Standard == I2S_STANDARD_PCM_LONG))) - { - /* Write to SPIx I2SCFGR */ - SET_BIT(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_ASTRTEN); - } -#endif /* SPI_I2SCFGR_ASTRTEN */ - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the I2S peripheral - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) -{ - /* Check the I2S handle allocation */ - if (hi2s == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); - - hi2s->State = HAL_I2S_STATE_BUSY; - - /* Disable the I2S Peripheral Clock */ - __HAL_I2S_DISABLE(hi2s); - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - if (hi2s->MspDeInitCallback == NULL) - { - hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - hi2s->MspDeInitCallback(hi2s); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_I2S_MspDeInit(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->State = HAL_I2S_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief I2S MSP Init - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspInit could be implemented in the user file - */ -} - -/** - * @brief I2S MSP DeInit - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User I2S Callback - * To be used instead of the weak predefined callback - * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for the specified I2S. - * @param CallbackID ID of the callback to be registered - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, - pI2S_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hi2s->ErrorCode |= HAL_I2S_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hi2s); - - if (HAL_I2S_STATE_READY == hi2s->State) - { - switch (CallbackID) - { - case HAL_I2S_TX_COMPLETE_CB_ID : - hi2s->TxCpltCallback = pCallback; - break; - - case HAL_I2S_RX_COMPLETE_CB_ID : - hi2s->RxCpltCallback = pCallback; - break; - - case HAL_I2S_TX_HALF_COMPLETE_CB_ID : - hi2s->TxHalfCpltCallback = pCallback; - break; - - case HAL_I2S_RX_HALF_COMPLETE_CB_ID : - hi2s->RxHalfCpltCallback = pCallback; - break; - - case HAL_I2S_ERROR_CB_ID : - hi2s->ErrorCallback = pCallback; - break; - - case HAL_I2S_MSPINIT_CB_ID : - hi2s->MspInitCallback = pCallback; - break; - - case HAL_I2S_MSPDEINIT_CB_ID : - hi2s->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_I2S_STATE_RESET == hi2s->State) - { - switch (CallbackID) - { - case HAL_I2S_MSPINIT_CB_ID : - hi2s->MspInitCallback = pCallback; - break; - - case HAL_I2S_MSPDEINIT_CB_ID : - hi2s->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hi2s); - return status; -} - -/** - * @brief Unregister an I2S Callback - * I2S callback is redirected to the weak predefined callback - * @param hi2s Pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for the specified I2S. - * @param CallbackID ID of the callback to be unregistered - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hi2s); - - if (HAL_I2S_STATE_READY == hi2s->State) - { - switch (CallbackID) - { - case HAL_I2S_TX_COMPLETE_CB_ID : - hi2s->TxCpltCallback = HAL_I2S_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_I2S_RX_COMPLETE_CB_ID : - hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_I2S_TX_HALF_COMPLETE_CB_ID : - hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_I2S_RX_HALF_COMPLETE_CB_ID : - hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_I2S_ERROR_CB_ID : - hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_I2S_MSPINIT_CB_ID : - hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_I2S_MSPDEINIT_CB_ID : - hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_I2S_STATE_RESET == hi2s->State) - { - switch (CallbackID) - { - case HAL_I2S_MSPINIT_CB_ID : - hi2s->MspInitCallback = HAL_I2S_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_I2S_MSPDEINIT_CB_ID : - hi2s->MspDeInitCallback = HAL_I2S_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hi2s); - return status; -} -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup I2S_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2S data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2S_Transmit() - (++) HAL_I2S_Receive() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2S_Transmit_IT() - (++) HAL_I2S_Receive_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2S_Transmit_DMA() - (++) HAL_I2S_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2S_TxCpltCallback() - (++) HAL_I2S_RxCpltCallback() - (++) HAL_I2S_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 24-bit or 32-bit data length. - * @param Timeout Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1U); - hi2s->TxXferCount = (Size << 1U); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - tmpreg_cfgr = hi2s->Instance->I2SCFGR; - - /* Check if the I2S is already enabled */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Wait until TXE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - while (hi2s->TxXferCount > 0U) - { - hi2s->Instance->DR = (*hi2s->pTxBuffPtr); - hi2s->pTxBuffPtr++; - hi2s->TxXferCount--; - - /* Wait until TXE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - /* Check if an underrun occurs */ - if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) - { - /* Clear underrun flag */ - __HAL_I2S_CLEAR_UDRFLAG(hi2s); - - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); - } - } - - /* Check if Slave mode is selected */ - if (((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX) - || ((tmpreg_cfgr & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_RX)) - { - /* Wait until Busy flag is reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, Timeout) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - } - - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Receive an amount of data in blocking mode - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 24-bit or 32-bit data length. - * @param Timeout Timeout duration - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate - * in continuous way and as the I2S is not disabled at the end of the I2S transaction. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pRxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1U); - hi2s->RxXferCount = (Size << 1U); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - /* Check if the I2S is already enabled */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if Master Receiver mode is selected */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) - { - /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read - access to the SPI_SR register. */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - } - - /* Receive data */ - while (hi2s->RxXferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; - hi2s->pRxBuffPtr++; - hi2s->RxXferCount--; - - /* Check if an overrun occurs */ - if (__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) - { - /* Clear overrun flag */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); - } - } - - hi2s->State = HAL_I2S_STATE_READY; - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 24-bit or 32-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1U); - hi2s->TxXferCount = (Size << 1U); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Enable TXE and ERR interrupt */ - __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to the Receive data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 24-bit or 32-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronization - * between Master and Slave otherwise the I2S interrupt should be optimized. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pRxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1U); - hi2s->RxXferCount = (Size << 1U); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - /* Enable RXNE and ERR interrupt */ - __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Check if the I2S is already enabled */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to the Transmit data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 24-bit or 32-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pTxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->TxXferSize = (Size << 1U); - hi2s->TxXferCount = (Size << 1U); - } - else - { - hi2s->TxXferSize = Size; - hi2s->TxXferCount = Size; - } - - /* Set the I2S Tx DMA Half transfer complete callback */ - hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; - - /* Set the I2S Tx DMA transfer complete callback */ - hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; - - /* Set the DMA error callback */ - hi2s->hdmatx->XferErrorCallback = I2S_DMAError; - - /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmatx, - (uint32_t)hi2s->pTxBuffPtr, - (uint32_t)&hi2s->Instance->DR, - hi2s->TxXferSize)) - { - /* Update SPI error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - hi2s->State = HAL_I2S_STATE_READY; - - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if the I2S Tx request is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) - { - /* Enable Tx DMA Request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param pData a 16-bit pointer to the Receive data buffer. - * @param Size number of data sample to be sent: - * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S - * configuration phase, the Size parameter means the number of 16-bit data length - * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected - * the Size parameter means the number of 24-bit or 32-bit data length. - * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization - * between Master and Slave(example: audio streaming). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) -{ - uint32_t tmpreg_cfgr; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State != HAL_I2S_STATE_READY) - { - __HAL_UNLOCK(hi2s); - return HAL_BUSY; - } - - /* Set state and reset error code */ - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - hi2s->pRxBuffPtr = pData; - - tmpreg_cfgr = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - - if ((tmpreg_cfgr == I2S_DATAFORMAT_24B) || (tmpreg_cfgr == I2S_DATAFORMAT_32B)) - { - hi2s->RxXferSize = (Size << 1U); - hi2s->RxXferCount = (Size << 1U); - } - else - { - hi2s->RxXferSize = Size; - hi2s->RxXferCount = Size; - } - - /* Set the I2S Rx DMA Half transfer complete callback */ - hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; - - /* Set the I2S Rx DMA transfer complete callback */ - hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; - - /* Set the DMA error callback */ - hi2s->hdmarx->XferErrorCallback = I2S_DMAError; - - /* Check if Master Receiver mode is selected */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) - { - /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read - access to the SPI_SR register. */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - } - - /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, - hi2s->RxXferSize)) - { - /* Update SPI error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - hi2s->State = HAL_I2S_STATE_READY; - - __HAL_UNLOCK(hi2s); - return HAL_ERROR; - } - - /* Check if the I2S is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Check if the I2S Rx request is already enabled */ - if (HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) - { - /* Enable Rx DMA Request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - - __HAL_UNLOCK(hi2s); - return HAL_OK; -} - -/** - * @brief Pauses the audio DMA Stream/Channel playing from the Media. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Disable the I2S DMA Tx request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* Disable the I2S DMA Rx request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - else - { - /* nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief Resumes the audio DMA Stream/Channel playing from the Media. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) -{ - /* Process Locked */ - __HAL_LOCK(hi2s); - - if (hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Enable the I2S DMA Tx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - } - else if (hi2s->State == HAL_I2S_STATE_BUSY_RX) - { - /* Enable the I2S DMA Rx request */ - SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - } - else - { - /* nothing to do */ - } - - /* If the I2S peripheral is still not enabled, enable it */ - if (HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) - { - /* Enable I2S peripheral */ - __HAL_I2S_ENABLE(hi2s); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_OK; -} - -/** - * @brief Stops the audio DMA Stream/Channel playing from the Media. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() - when calling HAL_DMA_Abort() API the DMA TX or RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_I2S_TxCpltCallback() or HAL_I2S_RxCpltCallback() - */ - - if ((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) - { - /* Abort the I2S DMA tx Stream/Channel */ - if (hi2s->hdmatx != NULL) - { - /* Disable the I2S DMA tx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmatx)) - { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; - } - } - - /* Wait until TXE flag is set */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, I2S_TIMEOUT_FLAG) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - errorcode = HAL_ERROR; - } - - /* Wait until BSY flag is Reset */ - if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, RESET, I2S_TIMEOUT_FLAG) != HAL_OK) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); - hi2s->State = HAL_I2S_STATE_READY; - errorcode = HAL_ERROR; - } - - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); - - /* Clear UDR flag */ - __HAL_I2S_CLEAR_UDRFLAG(hi2s); - - /* Disable the I2S Tx DMA requests */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - - } - - else if ((hi2s->Init.Mode == I2S_MODE_MASTER_RX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_RX)) - { - /* Abort the I2S DMA rx Stream/Channel */ - if (hi2s->hdmarx != NULL) - { - /* Disable the I2S DMA rx Stream/Channel */ - if (HAL_OK != HAL_DMA_Abort(hi2s->hdmarx)) - { - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - errorcode = HAL_ERROR; - } - } - - /* Disable I2S peripheral */ - __HAL_I2S_DISABLE(hi2s); - - /* Clear OVR flag */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - - /* Disable the I2S Rx DMA request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - - if (hi2s->Init.Mode == I2S_MODE_SLAVE_RX) - { - /* Set the error code */ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_BUSY_LINE_RX); - - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - errorcode = HAL_ERROR; - } - else - { - /* Read DR to Flush RX Data */ - READ_REG((hi2s->Instance)->DR); - } - } - - hi2s->State = HAL_I2S_STATE_READY; - - return errorcode; -} - -/** - * @brief This function handles I2S interrupt request. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) -{ - uint32_t itsource = hi2s->Instance->CR2; - uint32_t itflag = hi2s->Instance->SR; - - /* I2S in mode Receiver ------------------------------------------------*/ - if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) == RESET) && - (I2S_CHECK_FLAG(itflag, I2S_FLAG_RXNE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_RXNE) != RESET)) - { - I2S_Receive_IT(hi2s); - return; - } - - /* I2S in mode Tramitter -----------------------------------------------*/ - if ((I2S_CHECK_FLAG(itflag, I2S_FLAG_TXE) != RESET) && (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_TXE) != RESET)) - { - I2S_Transmit_IT(hi2s); - return; - } - - /* I2S interrupt error -------------------------------------------------*/ - if (I2S_CHECK_IT_SOURCE(itsource, I2S_IT_ERR) != RESET) - { - /* I2S Overrun error interrupt occurred ---------------------------------*/ - if (I2S_CHECK_FLAG(itflag, I2S_FLAG_OVR) != RESET) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); - } - - /* I2S Underrun error interrupt occurred --------------------------------*/ - if (I2S_CHECK_FLAG(itflag, I2S_FLAG_UDR) != RESET) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); - } - - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - - /* Call user error callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->ErrorCallback(hi2s); -#else - HAL_I2S_ErrorCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Tx Transfer Half completed callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer completed callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer half completed callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2S error callbacks - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -__weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2s); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2S state - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL state - */ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) -{ - return hi2s->State; -} - -/** - * @brief Return the I2S error code - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval I2S Error Code - */ -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) -{ - return hi2s->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2S_Private_Functions I2S Private Functions - * @{ - */ -/** - * @brief Get I2S Input Clock based on I2S source clock selection - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module. - * @retval I2S Clock Input - */ -static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s) -{ - uint32_t tmpreg; - /* This variable used to store the VCO Input (value in Hz) */ - uint32_t vcoinput; - /* This variable used to store the I2S_CK_x (value in Hz) */ - uint32_t i2sclocksource; - - /* Configure I2S Clock based on I2S source clock selection */ - - /* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */ - switch (hi2s->Init.ClockSource) - { - case I2S_CLOCK_PLL : - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */ - if ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* I2S_CLK(first level) = PLLI2S_VCO Output/PLLI2SR */ - tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U; - i2sclocksource = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U)) / (tmpreg); - - break; - } - case I2S_CLOCK_EXTERNAL : - { - i2sclocksource = EXTERNAL_CLOCK_VALUE; - break; - } - default : - { - i2sclocksource = 0U; - break; - } - } - - /* the return result is the value of I2S clock */ - return i2sclocksource; -} - -/** - * @brief DMA I2S transmit process complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* if DMA is configured in DMA_NORMAL Mode */ - if (hdma->Init.Mode == DMA_NORMAL) - { - /* Disable Tx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - - hi2s->TxXferCount = 0U; - hi2s->State = HAL_I2S_STATE_READY; - } - /* Call user Tx complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->TxCpltCallback(hi2s); -#else - HAL_I2S_TxCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA I2S transmit process half complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* Call user Tx half complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->TxHalfCpltCallback(hi2s); -#else - HAL_I2S_TxHalfCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA I2S receive process complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* if DMA is configured in DMA_NORMAL Mode */ - if (hdma->Init.Mode == DMA_NORMAL) - { - /* Disable Rx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - hi2s->RxXferCount = 0U; - hi2s->State = HAL_I2S_STATE_READY; - } - /* Call user Rx complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->RxCpltCallback(hi2s); -#else - HAL_I2S_RxCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA I2S receive process half complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* Call user Rx half complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->RxHalfCpltCallback(hi2s); -#else - HAL_I2S_RxHalfCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA I2S communication error callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void I2S_DMAError(DMA_HandleTypeDef *hdma) -{ - I2S_HandleTypeDef *hi2s = (I2S_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ - - /* Disable Rx and Tx DMA Request */ - CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); - hi2s->TxXferCount = 0U; - hi2s->RxXferCount = 0U; - - hi2s->State = HAL_I2S_STATE_READY; - - /* Set the error code and execute error callback*/ - SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); - /* Call user error callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->ErrorCallback(hi2s); -#else - HAL_I2S_ErrorCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) -{ - /* Transmit data */ - hi2s->Instance->DR = (*hi2s->pTxBuffPtr); - hi2s->pTxBuffPtr++; - hi2s->TxXferCount--; - - if (hi2s->TxXferCount == 0U) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - /* Call user Tx complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->TxCpltCallback(hi2s); -#else - HAL_I2S_TxCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval None - */ -static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) -{ - /* Receive data */ - (*hi2s->pRxBuffPtr) = (uint16_t)hi2s->Instance->DR; - hi2s->pRxBuffPtr++; - hi2s->RxXferCount--; - - if (hi2s->RxXferCount == 0U) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - /* Call user Rx complete callback */ -#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) - hi2s->RxCpltCallback(hi2s); -#else - HAL_I2S_RxCpltCallback(hi2s); -#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ - } -} - -/** - * @brief This function handles I2S Communication Timeout. - * @param hi2s pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @param Flag Flag checked - * @param State Value of the flag expected - * @param Timeout Duration of the timeout - * @retval HAL status - */ -static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, FlagStatus State, - uint32_t Timeout) -{ - uint32_t tickstart; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until flag is set to status*/ - while (((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Set the I2S State ready */ - hi2s->State = HAL_I2S_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2s); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_I2S_MODULE_ENABLED */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c deleted file mode 100644 index 9e791a7f..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_irda.c +++ /dev/null @@ -1,2897 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_irda.c - * @author MCD Application Team - * @brief IRDA HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the IrDA (Infrared Data Association) Peripheral - * (IRDA) - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The IRDA HAL driver can be used as follows: - - (#) Declare a IRDA_HandleTypeDef handle structure (eg. IRDA_HandleTypeDef hirda). - (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API - in setting the associated USART or UART in IRDA mode: - (++) Enable the USARTx/UARTx interface clock. - (++) USARTx/UARTx pins configuration: - (+++) Enable the clock for the USARTx/UARTx GPIOs. - (+++) Configure these USARTx/UARTx pins (TX as alternate function pull-up, RX as alternate function Input). - (++) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT() - and HAL_IRDA_Receive_IT() APIs): - (+++) Configure the USARTx/UARTx interrupt priority. - (+++) Enable the NVIC USARTx/UARTx IRQ handle. - (+++) The specific IRDA interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - - (++) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA() - and HAL_IRDA_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the IRDA DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer - complete interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length and Parity and Mode(Receiver/Transmitter), - the normal or low power mode and the clock prescaler in the hirda handle Init structure. - - (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_IRDA_MspInit() API. - - -@@- The specific IRDA interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process. - - (#) Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() - (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non-blocking mode using HAL_IRDA_Transmit_IT() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() - (+) Receive an amount of data in non-blocking mode using HAL_IRDA_Receive_IT() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non-blocking mode (DMA) using HAL_IRDA_Transmit_DMA() - (+) At transmission half of transfer HAL_IRDA_TxHalfCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxHalfCpltCallback() - (+) At transmission end of transfer HAL_IRDA_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_IRDA_TxCpltCallback() - (+) Receive an amount of data in non-blocking mode (DMA) using HAL_IRDA_Receive_DMA() - (+) At reception half of transfer HAL_IRDA_RxHalfCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxHalfCpltCallback() - (+) At reception end of transfer HAL_IRDA_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_IRDA_RxCpltCallback() - (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_IRDA_ErrorCallback() - - *** IRDA HAL driver macros list *** - ==================================== - [..] - Below the list of most used macros in IRDA HAL driver. - - (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral - (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral - (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not - (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag - (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt - (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt - (+) __HAL_IRDA_GET_IT_SOURCE: Check whether or not the specified IRDA interrupt is enabled - - [..] - (@) You can refer to the IRDA HAL driver header file for more useful macros - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_IRDA_RegisterCallback() to register a user callback. - Function HAL_IRDA_RegisterCallback() allows to register following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) MspInitCallback : IRDA MspInit. - (+) MspDeInitCallback : IRDA MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) MspInitCallback : IRDA MspInit. - (+) MspDeInitCallback : IRDA MspDeInit. - - [..] - By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak functions in the HAL_IRDA_Init() - and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_IRDA_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() - or HAL_IRDA_Init() function. - - [..] - When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup IRDA IRDA - * @brief HAL IRDA module driver - * @{ - */ - -#ifdef HAL_IRDA_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup IRDA_Private_Constants IRDA Private Constants - * @{ - */ -#define IRDA_TEACK_REACK_TIMEOUT 1000U /*!< IRDA TX or RX enable acknowledge time-out value */ - -#define IRDA_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE \ - | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) /*!< UART or USART CR1 fields of parameters set by IRDA_SetConfig API */ - -#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ - -#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup IRDA_Private_Macros IRDA Private Macros - * @{ - */ -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__ IRDA clock source. - * @param __BAUD__ Baud rate set by the user. - * @retval Division result - */ -#define IRDA_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2U)) / (__BAUD__)) -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup IRDA_Private_Functions - * @{ - */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout); -static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda); -static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda); -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma); -static void IRDA_DMAError(DMA_HandleTypeDef *hdma); -static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); -static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); -static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup IRDA_Exported_Functions IRDA Exported Functions - * @{ - */ - -/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx - in asynchronous IRDA mode. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Power mode - (++) Prescaler setting - (++) Receiver/transmitter modes - - [..] - The HAL_IRDA_Init() API follows the USART asynchronous configuration procedures - (details for the procedures are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible IRDA frame formats are listed in the - following table. - - Table 1. IRDA frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | IRDA frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the IRDA mode according to the specified - * parameters in the IRDA_InitTypeDef and initialize the associated handle. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) -{ - /* Check the IRDA handle allocation */ - if (hirda == NULL) - { - return HAL_ERROR; - } - - /* Check the USART/UART associated to the IRDA handle */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - - if (hirda->gState == HAL_IRDA_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hirda->Lock = HAL_UNLOCKED; - -#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 - IRDA_InitCallbacksToDefault(hirda); - - if (hirda->MspInitCallback == NULL) - { - hirda->MspInitCallback = HAL_IRDA_MspInit; - } - - /* Init the low level hardware */ - hirda->MspInitCallback(hirda); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_IRDA_MspInit(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - } - - hirda->gState = HAL_IRDA_STATE_BUSY; - - /* Disable the Peripheral to update the configuration registers */ - __HAL_IRDA_DISABLE(hirda); - - /* Set the IRDA Communication parameters */ - if (IRDA_SetConfig(hirda) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In IRDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); - CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); - - /* set the UART/USART in IRDA mode */ - hirda->Instance->CR3 |= USART_CR3_IREN; - - /* Enable the Peripheral */ - __HAL_IRDA_ENABLE(hirda); - - /* TEACK and/or REACK to check before moving hirda->gState and hirda->RxState to Ready */ - return (IRDA_CheckIdleState(hirda)); -} - -/** - * @brief DeInitialize the IRDA peripheral. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) -{ - /* Check the IRDA handle allocation */ - if (hirda == NULL) - { - return HAL_ERROR; - } - - /* Check the USART/UART associated to the IRDA handle */ - assert_param(IS_IRDA_INSTANCE(hirda->Instance)); - - hirda->gState = HAL_IRDA_STATE_BUSY; - - /* DeInit the low level hardware */ -#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1 - if (hirda->MspDeInitCallback == NULL) - { - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; - } - /* DeInit the low level hardware */ - hirda->MspDeInitCallback(hirda); -#else - HAL_IRDA_MspDeInit(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - /* Disable the Peripheral */ - __HAL_IRDA_DISABLE(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_RESET; - hirda->RxState = HAL_IRDA_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief Initialize the IRDA MSP. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the IRDA MSP. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_IRDA_MspDeInit can be implemented in the user file - */ -} - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User IRDA Callback - * To be used to override the weak predefined callback - * @note The HAL_IRDA_RegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET - * to register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID - * @param hirda irda handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, - pIRDA_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (hirda->gState == HAL_IRDA_STATE_READY) - { - switch (CallbackID) - { - case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : - hirda->TxHalfCpltCallback = pCallback; - break; - - case HAL_IRDA_TX_COMPLETE_CB_ID : - hirda->TxCpltCallback = pCallback; - break; - - case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : - hirda->RxHalfCpltCallback = pCallback; - break; - - case HAL_IRDA_RX_COMPLETE_CB_ID : - hirda->RxCpltCallback = pCallback; - break; - - case HAL_IRDA_ERROR_CB_ID : - hirda->ErrorCallback = pCallback; - break; - - case HAL_IRDA_ABORT_COMPLETE_CB_ID : - hirda->AbortCpltCallback = pCallback; - break; - - case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : - hirda->AbortTransmitCpltCallback = pCallback; - break; - - case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : - hirda->AbortReceiveCpltCallback = pCallback; - break; - - case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = pCallback; - break; - - case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hirda->gState == HAL_IRDA_STATE_RESET) - { - switch (CallbackID) - { - case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = pCallback; - break; - - case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an IRDA callback - * IRDA callback is redirected to the weak predefined callback - * @note The HAL_IRDA_UnRegisterCallback() may be called before HAL_IRDA_Init() in HAL_IRDA_STATE_RESET - * to un-register callbacks for HAL_IRDA_MSPINIT_CB_ID and HAL_IRDA_MSPDEINIT_CB_ID - * @param hirda irda handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_IRDA_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_IRDA_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_IRDA_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_IRDA_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_IRDA_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_IRDA_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_IRDA_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_IRDA_MSPDEINIT_CB_ID MspDeInit Callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_IRDA_STATE_READY == hirda->gState) - { - switch (CallbackID) - { - case HAL_IRDA_TX_HALFCOMPLETE_CB_ID : - hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_IRDA_TX_COMPLETE_CB_ID : - hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_IRDA_RX_HALFCOMPLETE_CB_ID : - hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_IRDA_RX_COMPLETE_CB_ID : - hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_IRDA_ERROR_CB_ID : - hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_IRDA_ABORT_COMPLETE_CB_ID : - hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID : - hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak - AbortTransmitCpltCallback */ - break; - - case HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID : - hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak - AbortReceiveCpltCallback */ - break; - - case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = HAL_IRDA_MspInit; /* Legacy weak MspInitCallback */ - break; - - case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; /* Legacy weak MspDeInitCallback */ - break; - - default : - /* Update the error code */ - hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_IRDA_STATE_RESET == hirda->gState) - { - switch (CallbackID) - { - case HAL_IRDA_MSPINIT_CB_ID : - hirda->MspInitCallback = HAL_IRDA_MspInit; - break; - - case HAL_IRDA_MSPDEINIT_CB_ID : - hirda->MspDeInitCallback = HAL_IRDA_MspDeInit; - break; - - default : - /* Update the error code */ - hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hirda->ErrorCode |= HAL_IRDA_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions - * @brief IRDA Transmit and Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the IRDA data transfers. - - [..] - IrDA is a half duplex communication protocol. If the Transmitter is busy, any data - on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver - is busy, data on the TX from the USART to IrDA will not be encoded by IrDA. - While receiving data, transmission should be avoided as the data to be transmitted - could be corrupted. - - [..] - (#) There are two modes of transfer: - (++) Blocking mode: the communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) Non-Blocking mode: the communication is performed using Interrupts - or DMA, these API's return the HAL status. - The end of the data processing will be indicated through the - dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks - will be executed respectively at the end of the Transmit or Receive process - The HAL_IRDA_ErrorCallback() user callback will be executed when a communication error is detected - - (#) Blocking mode APIs are : - (++) HAL_IRDA_Transmit() - (++) HAL_IRDA_Receive() - - (#) Non Blocking mode APIs with Interrupt are : - (++) HAL_IRDA_Transmit_IT() - (++) HAL_IRDA_Receive_IT() - (++) HAL_IRDA_IRQHandler() - - (#) Non Blocking mode functions with DMA are : - (++) HAL_IRDA_Transmit_DMA() - (++) HAL_IRDA_Receive_DMA() - (++) HAL_IRDA_DMAPause() - (++) HAL_IRDA_DMAResume() - (++) HAL_IRDA_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non Blocking mode: - (++) HAL_IRDA_TxHalfCpltCallback() - (++) HAL_IRDA_TxCpltCallback() - (++) HAL_IRDA_RxHalfCpltCallback() - (++) HAL_IRDA_RxCpltCallback() - (++) HAL_IRDA_ErrorCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (++) HAL_IRDA_Abort() - (++) HAL_IRDA_AbortTransmit() - (++) HAL_IRDA_AbortReceive() - (++) HAL_IRDA_Abort_IT() - (++) HAL_IRDA_AbortTransmit_IT() - (++) HAL_IRDA_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_IRDA_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (++) HAL_IRDA_AbortCpltCallback() - (++) HAL_IRDA_AbortTransmitCpltCallback() - (++) HAL_IRDA_AbortReceiveCpltCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_IRDA_ErrorCallback() user callback is executed. - Transfer is kept ongoing on IRDA side. - If user wants to abort it, Abort services should be called by user. - (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and - HAL_IRDA_ErrorCallback() user callback is executed. - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must reflect the number - * of u16 available through pData. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @param Timeout Specify timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - const uint8_t *pdata8bits; - const uint16_t *pdata16bits; - uint32_t tickstart; - - /* Check that a Tx process is not already ongoing */ - if (hirda->gState == HAL_IRDA_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (const uint16_t *) pData; /* Derogation R.11.3 */ - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - while (hirda->TxXferCount > 0U) - { - hirda->TxXferCount--; - - if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - hirda->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); - pdata16bits++; - } - else - { - hirda->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); - pdata8bits++; - } - } - - if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must reflect the number - * of u16 available through pData. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @param Timeout Specify timeout value. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint16_t uhMask; - uint32_t tickstart; - - /* Check that a Rx process is not already ongoing */ - if (hirda->RxState == HAL_IRDA_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - hirda->RxXferSize = Size; - hirda->RxXferCount = Size; - - /* Computation of the mask to apply to RDR register - of the UART associated to the IRDA */ - IRDA_MASK_COMPUTATION(hirda); - uhMask = hirda->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; /* Derogation R.11.3 */ - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - /* Check data remaining to be received */ - while (hirda->RxXferCount > 0U) - { - hirda->RxXferCount--; - - if (IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(hirda->Instance->RDR & uhMask); - pdata16bits++; - } - else - { - *pdata8bits = (uint8_t)(hirda->Instance->RDR & (uint8_t)uhMask); - pdata8bits++; - } - } - - /* At end of Rx process, restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must reflect the number - * of u16 available through pData. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (hirda->gState == HAL_IRDA_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pTxBuffPtr = pData; - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the IRDA Transmit Data Register Empty Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must reflect the number - * of u16 available through pData. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (hirda->RxState == HAL_IRDA_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pRxBuffPtr = pData; - hirda->RxXferSize = Size; - hirda->RxXferCount = Size; - - /* Computation of the mask to apply to the RDR register - of the UART associated to the IRDA */ - IRDA_MASK_COMPUTATION(hirda); - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - if (hirda->Init.Parity != IRDA_PARITY_NONE) - { - /* Enable the IRDA Parity Error and Data Register not empty Interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - } - else - { - /* Enable the IRDA Data Register not empty Interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE); - } - - /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must reflect the number - * of u16 available through pData. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (hirda->gState == HAL_IRDA_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pTxBuffPtr = pData; - hirda->TxXferSize = Size; - hirda->TxXferCount = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->gState = HAL_IRDA_STATE_BUSY_TX; - - /* Set the IRDA DMA transfer complete callback */ - hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt; - - /* Set the IRDA DMA half transfer complete callback */ - hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt; - - /* Set the DMA error callback */ - hirda->hdmatx->XferErrorCallback = IRDA_DMAError; - - /* Set the DMA abort callback */ - hirda->hdmatx->XferAbortCallback = NULL; - - /* Enable the IRDA transmit DMA channel */ - if (HAL_DMA_Start_IT(hirda->hdmatx, (uint32_t)hirda->pTxBuffPtr, (uint32_t)&hirda->Instance->TDR, Size) == HAL_OK) - { - /* Clear the TC flag in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_TCF); - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - /* Set error code to DMA */ - hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Restore hirda->gState to ready */ - hirda->gState = HAL_IRDA_STATE_READY; - - return HAL_ERROR; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must reflect the number - * of u16 available through pData. - * @note When the IRDA parity is enabled (PCE = 1), the received data contains - * the parity bit (MSB position). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (hirda->RxState == HAL_IRDA_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hirda); - - hirda->pRxBuffPtr = pData; - hirda->RxXferSize = Size; - - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - - /* Set the IRDA DMA transfer complete callback */ - hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt; - - /* Set the IRDA DMA half transfer complete callback */ - hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt; - - /* Set the DMA error callback */ - hirda->hdmarx->XferErrorCallback = IRDA_DMAError; - - /* Set the DMA abort callback */ - hirda->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->RDR, (uint32_t)hirda->pRxBuffPtr, Size) == HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - if (hirda->Init.Parity != IRDA_PARITY_NONE) - { - /* Enable the UART Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - } - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; - } - else - { - /* Set error code to DMA */ - hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - /* Restore hirda->RxState to ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - - return HAL_ERROR; - } - } - else - { - return HAL_BUSY; - } -} - - -/** - * @brief Pause the DMA Transfer. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda) -{ - /* Process Locked */ - __HAL_LOCK(hirda); - - if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) - { - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable the IRDA DMA Tx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - } - } - if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - { - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Disable the IRDA DMA Rx request */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) -{ - /* Process Locked */ - __HAL_LOCK(hirda); - - if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) - { - /* Enable the IRDA DMA Tx request */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - } - if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_IRDA_CLEAR_OREFLAG(hirda); - - /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - if (hirda->Init.Parity != IRDA_PARITY_NONE) - { - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - } - SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Enable the IRDA DMA Rx request */ - SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL IRDA API under callbacks HAL_IRDA_TxCpltCallback() / HAL_IRDA_RxCpltCallback() / - HAL_IRDA_TxHalfCpltCallback / HAL_IRDA_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - /* Stop IRDA DMA Tx request if ongoing */ - if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) - { - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Abort the IRDA DMA Tx channel */ - if (hirda->hdmatx != NULL) - { - if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - IRDA_EndTxTransfer(hirda); - } - } - - /* Stop IRDA DMA Rx request if ongoing */ - if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - { - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel */ - if (hirda->hdmarx != NULL) - { - if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - IRDA_EndRxTransfer(hirda); - } - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable IRDA Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda) -{ - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Disable the IRDA DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (hirda->hdmatx != NULL) - { - /* Set the IRDA DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - hirda->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Disable the IRDA DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (hirda->hdmarx != NULL) - { - /* Set the IRDA DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - hirda->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx and Rx transfer counters */ - hirda->TxXferCount = 0U; - hirda->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); - - /* Restore hirda->gState and hirda->RxState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - hirda->RxState = HAL_IRDA_STATE_READY; - - /* Reset Handle ErrorCode to No Error */ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable IRDA Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Disable the IRDA DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Abort the IRDA DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (hirda->hdmatx != NULL) - { - /* Set the IRDA DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - hirda->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(hirda->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(hirda->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx transfer counter */ - hirda->TxXferCount = 0U; - - /* Restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable IRDA Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Disable the IRDA DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (hirda->hdmarx != NULL) - { - /* Set the IRDA DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - hirda->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(hirda->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(hirda->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hirda->ErrorCode = HAL_IRDA_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Rx transfer counter */ - hirda->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); - - /* Restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable IRDA Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda) -{ - uint32_t abortcplt = 1U; - - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* If DMA Tx and/or DMA Rx Handles are associated to IRDA Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (hirda->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if IRDA DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) - { - hirda->hdmatx->XferAbortCallback = IRDA_DMATxAbortCallback; - } - else - { - hirda->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (hirda->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if IRDA DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - hirda->hdmarx->XferAbortCallback = IRDA_DMARxAbortCallback; - } - else - { - hirda->hdmarx->XferAbortCallback = NULL; - } - } - - /* Disable the IRDA DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at UART level */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (hirda->hdmatx != NULL) - { - /* IRDA Tx DMA Abort callback has already been initialised : - will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) - { - hirda->hdmatx->XferAbortCallback = NULL; - } - else - { - abortcplt = 0U; - } - } - } - - /* Disable the IRDA DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (hirda->hdmarx != NULL) - { - /* IRDA Rx DMA Abort callback has already been initialised : - will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) - { - hirda->hdmarx->XferAbortCallback = NULL; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - hirda->TxXferCount = 0U; - hirda->RxXferCount = 0U; - - /* Reset errorCode */ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); - - /* Restore hirda->gState and hirda->RxState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - hirda->RxState = HAL_IRDA_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - hirda->AbortCpltCallback(hirda); -#else - /* Call legacy weak Abort complete callback */ - HAL_IRDA_AbortCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable IRDA Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Disable the IRDA DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Abort the IRDA DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (hirda->hdmatx != NULL) - { - /* Set the IRDA DMA Abort callback : - will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ - hirda->hdmatx->XferAbortCallback = IRDA_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hirda->hdmatx) != HAL_OK) - { - /* Call Directly hirda->hdmatx->XferAbortCallback function in case of error */ - hirda->hdmatx->XferAbortCallback(hirda->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - hirda->TxXferCount = 0U; - - /* Restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - hirda->AbortTransmitCpltCallback(hirda); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_IRDA_AbortTransmitCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - } - } - else - { - /* Reset Tx transfer counter */ - hirda->TxXferCount = 0U; - - /* Restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - hirda->AbortTransmitCpltCallback(hirda); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_IRDA_AbortTransmitCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable IRDA Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Disable the IRDA DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (hirda->hdmarx != NULL) - { - /* Set the IRDA DMA Abort callback : - will lead to call HAL_IRDA_AbortCpltCallback() at end of DMA abort procedure */ - hirda->hdmarx->XferAbortCallback = IRDA_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) - { - /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ - hirda->hdmarx->XferAbortCallback(hirda->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - hirda->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); - - /* Restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - hirda->AbortReceiveCpltCallback(hirda); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_IRDA_AbortReceiveCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - } - } - else - { - /* Reset Rx transfer counter */ - hirda->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); - - /* Restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - hirda->AbortReceiveCpltCallback(hirda); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_IRDA_AbortReceiveCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - } - - return HAL_OK; -} - -/** - * @brief Handle IRDA interrupt request. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) -{ - uint32_t isrflags = READ_REG(hirda->Instance->ISR); - uint32_t cr1its = READ_REG(hirda->Instance->CR1); - uint32_t cr3its; - uint32_t errorflags; - uint32_t errorcode; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE)); - if (errorflags == 0U) - { - /* IRDA in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - IRDA_Receive_IT(hirda); - return; - } - } - - /* If some errors occur */ - cr3its = READ_REG(hirda->Instance->CR3); - if ((errorflags != 0U) - && (((cr3its & USART_CR3_EIE) != 0U) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) - { - /* IRDA parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); - - hirda->ErrorCode |= HAL_IRDA_ERROR_PE; - } - - /* IRDA frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); - - hirda->ErrorCode |= HAL_IRDA_ERROR_FE; - } - - /* IRDA noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); - - hirda->ErrorCode |= HAL_IRDA_ERROR_NE; - } - - /* IRDA Over-Run interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_ORE) != 0U) && - (((cr1its & USART_CR1_RXNEIE) != 0U) || ((cr3its & USART_CR3_EIE) != 0U))) - { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); - - hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; - } - - /* Call IRDA Error Call back function if need be --------------------------*/ - if (hirda->ErrorCode != HAL_IRDA_ERROR_NONE) - { - /* IRDA in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - IRDA_Receive_IT(hirda); - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - errorcode = hirda->ErrorCode; - if ((HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & HAL_IRDA_ERROR_ORE) != 0U)) - { - /* Blocking error : transfer is aborted - Set the IRDA state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - IRDA_EndRxTransfer(hirda); - - /* Disable the IRDA DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* Abort the IRDA DMA Rx channel */ - if (hirda->hdmarx != NULL) - { - /* Set the IRDA DMA Abort callback : - will lead to call HAL_IRDA_ErrorCallback() at end of DMA abort procedure */ - hirda->hdmarx->XferAbortCallback = IRDA_DMAAbortOnError; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hirda->hdmarx) != HAL_OK) - { - /* Call Directly hirda->hdmarx->XferAbortCallback function in case of error */ - hirda->hdmarx->XferAbortCallback(hirda->hdmarx); - } - } - else - { -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hirda->ErrorCallback(hirda); -#else - /* Call legacy weak user error callback */ - HAL_IRDA_ErrorCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - } - } - else - { -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hirda->ErrorCallback(hirda); -#else - /* Call legacy weak user error callback */ - HAL_IRDA_ErrorCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hirda->ErrorCallback(hirda); -#else - /* Call legacy weak user error callback */ - HAL_IRDA_ErrorCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* IRDA in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_ISR_TXE) != 0U) && ((cr1its & USART_CR1_TXEIE) != 0U)) - { - IRDA_Transmit_IT(hirda); - return; - } - - /* IRDA in mode Transmitter (transmission end) -----------------------------*/ - if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) - { - IRDA_EndTransmit_IT(hirda); - return; - } - -} - -/** - * @brief Tx Transfer completed callback. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_TxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -__weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_RxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Half Transfer complete callback. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief IRDA error callback. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_ErrorCallback can be implemented in the user file. - */ -} - -/** - * @brief IRDA Abort Complete callback. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief IRDA Abort Complete callback. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief IRDA Abort Receive Complete callback. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -__weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hirda); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_IRDA_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions - * @brief IRDA State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of IrDA - communication process and also return Peripheral Errors occurred during communication process - (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state - of the IRDA peripheral handle. - (+) HAL_IRDA_GetError() checks in run-time errors that could occur during - communication. - -@endverbatim - * @{ - */ - -/** - * @brief Return the IRDA handle state. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL state - */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) -{ - /* Return IRDA handle state */ - uint32_t temp1; - uint32_t temp2; - temp1 = (uint32_t)hirda->gState; - temp2 = (uint32_t)hirda->RxState; - - return (HAL_IRDA_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the IRDA handle error code. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval IRDA Error Code - */ -uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) -{ - return hirda->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup IRDA_Private_Functions IRDA Private Functions - * @{ - */ - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -/** - * @brief Initialize the callbacks to their default values. - * @param hirda IRDA handle. - * @retval none - */ -void IRDA_InitCallbacksToDefault(IRDA_HandleTypeDef *hirda) -{ - /* Init the IRDA Callback settings */ - hirda->TxHalfCpltCallback = HAL_IRDA_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - hirda->TxCpltCallback = HAL_IRDA_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hirda->RxHalfCpltCallback = HAL_IRDA_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - hirda->RxCpltCallback = HAL_IRDA_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hirda->ErrorCallback = HAL_IRDA_ErrorCallback; /* Legacy weak ErrorCallback */ - hirda->AbortCpltCallback = HAL_IRDA_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hirda->AbortTransmitCpltCallback = HAL_IRDA_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - hirda->AbortReceiveCpltCallback = HAL_IRDA_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - -} -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - -/** - * @brief Configure the IRDA peripheral. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda) -{ - uint32_t tmpreg; - IRDA_ClockSourceTypeDef clocksource; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t pclk; - - /* Check the communication parameters */ - assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); - assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength)); - assert_param(IS_IRDA_PARITY(hirda->Init.Parity)); - assert_param(IS_IRDA_TX_RX_MODE(hirda->Init.Mode)); - assert_param(IS_IRDA_PRESCALER(hirda->Init.Prescaler)); - assert_param(IS_IRDA_POWERMODE(hirda->Init.PowerMode)); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Configure the IRDA Word Length, Parity and transfer Mode: - Set the M bits according to hirda->Init.WordLength value - Set PCE and PS bits according to hirda->Init.Parity value - Set TE and RE bits according to hirda->Init.Mode value */ - tmpreg = (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode ; - - MODIFY_REG(hirda->Instance->CR1, IRDA_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.PowerMode); - - - /*-------------------------- USART GTPR Configuration ----------------------*/ - MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler); - - /*-------------------------- USART BRR Configuration -----------------------*/ - IRDA_GETCLOCKSOURCE(hirda, clocksource); - tmpreg = 0U; - switch (clocksource) - { - case IRDA_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate)); - break; - case IRDA_CLOCKSOURCE_PCLK2: - pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate)); - break; - case IRDA_CLOCKSOURCE_HSI: - tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate)); - break; - case IRDA_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate)); - break; - case IRDA_CLOCKSOURCE_LSE: - tmpreg = (uint32_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate)); - break; - default: - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 */ - if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) - { - hirda->Instance->BRR = (uint16_t)tmpreg; - } - else - { - ret = HAL_ERROR; - } - - return ret; -} - -/** - * @brief Check the IRDA Idle State. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda) -{ - uint32_t tickstart; - - /* Initialize the IRDA ErrorCode */ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if ((hirda->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_TEACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } -#if defined(USART_ISR_REACK) - /* Check if the Receiver is enabled */ - if ((hirda->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if (IRDA_WaitOnFlagUntilTimeout(hirda, USART_ISR_REACK, RESET, tickstart, IRDA_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } -#endif /* USART_ISR_REACK */ - - /* Initialize the IRDA state*/ - hirda->gState = HAL_IRDA_STATE_READY; - hirda->RxState = HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - - return HAL_OK; -} - -/** - * @brief Handle IRDA Communication Timeout. It waits - * until a flag is no longer in the specified status. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @param Flag Specifies the IRDA flag to check. - * @param Status The actual Flag status (SET or RESET) - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while ((__HAL_IRDA_GET_FLAG(hirda, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - hirda->gState = HAL_IRDA_STATE_READY; - hirda->RxState = HAL_IRDA_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hirda); - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - - -/** - * @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* At end of Tx process, restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; -} - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* At end of Rx process, restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; -} - - -/** - * @brief DMA IRDA transmit process complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - - /* DMA Normal mode */ - if (hdma->Init.Mode != DMA_CIRCULAR) - { - hirda->TxXferCount = 0U; - - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the IRDA CR3 register */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT); - - /* Enable the IRDA Transmit Complete Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - } - /* DMA Circular mode */ - else - { -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Tx complete callback */ - hirda->TxCpltCallback(hirda); -#else - /* Call legacy weak Tx complete callback */ - HAL_IRDA_TxCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ - } - -} - -/** - * @brief DMA IRDA transmit process half complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Tx Half complete callback */ - hirda->TxHalfCpltCallback(hirda); -#else - /* Call legacy weak Tx complete callback */ - HAL_IRDA_TxHalfCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - -/** - * @brief DMA IRDA receive process complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - - /* DMA Normal mode */ - if (hdma->Init.Mode != DMA_CIRCULAR) - { - hirda->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the IRDA CR3 register */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - } - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Rx complete callback */ - hirda->RxCpltCallback(hirda); -#else - /* Call legacy weak Rx complete callback */ - HAL_IRDA_RxCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA IRDA receive process half complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - hirda->RxHalfCpltCallback(hirda); -#else - /* Call legacy weak Rx Half complete callback */ - HAL_IRDA_RxHalfCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - -/** - * @brief DMA IRDA communication error callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void IRDA_DMAError(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - - /* Stop IRDA DMA Tx request if ongoing */ - if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) - { - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAT)) - { - hirda->TxXferCount = 0U; - IRDA_EndTxTransfer(hirda); - } - } - - /* Stop IRDA DMA Rx request if ongoing */ - if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - { - if (HAL_IS_BIT_SET(hirda->Instance->CR3, USART_CR3_DMAR)) - { - hirda->RxXferCount = 0U; - IRDA_EndRxTransfer(hirda); - } - } - - hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hirda->ErrorCallback(hirda); -#else - /* Call legacy weak user error callback */ - HAL_IRDA_ErrorCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - -/** - * @brief DMA IRDA communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void IRDA_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - hirda->RxXferCount = 0U; - hirda->TxXferCount = 0U; - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hirda->ErrorCallback(hirda); -#else - /* Call legacy weak user error callback */ - HAL_IRDA_ErrorCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - -/** - * @brief DMA IRDA Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void IRDA_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - - hirda->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (hirda->hdmarx != NULL) - { - if (hirda->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hirda->TxXferCount = 0U; - hirda->RxXferCount = 0U; - - /* Reset errorCode */ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); - - /* Restore hirda->gState and hirda->RxState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - hirda->RxState = HAL_IRDA_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - hirda->AbortCpltCallback(hirda); -#else - /* Call legacy weak Abort complete callback */ - HAL_IRDA_AbortCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - - -/** - * @brief DMA IRDA Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void IRDA_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - - hirda->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (hirda->hdmatx != NULL) - { - if (hirda->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hirda->TxXferCount = 0U; - hirda->RxXferCount = 0U; - - /* Reset errorCode */ - hirda->ErrorCode = HAL_IRDA_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); - - /* Restore hirda->gState and hirda->RxState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - hirda->RxState = HAL_IRDA_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - hirda->AbortCpltCallback(hirda); -#else - /* Call legacy weak Abort complete callback */ - HAL_IRDA_AbortCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - - -/** - * @brief DMA IRDA Tx communication abort callback, when initiated by user by a call to - * HAL_IRDA_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void IRDA_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)(hdma->Parent); - - hirda->TxXferCount = 0U; - - /* Restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - hirda->AbortTransmitCpltCallback(hirda); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_IRDA_AbortTransmitCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - -/** - * @brief DMA IRDA Rx communication abort callback, when initiated by user by a call to - * HAL_IRDA_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - IRDA_HandleTypeDef *hirda = (IRDA_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - hirda->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_CLEAR_OREF | IRDA_CLEAR_NEF | IRDA_CLEAR_PEF | IRDA_CLEAR_FEF); - - /* Restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - hirda->AbortReceiveCpltCallback(hirda); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_IRDA_AbortReceiveCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - -/** - * @brief Send an amount of data in interrupt mode. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_IRDA_Transmit_IT(). - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -static void IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) -{ - const uint16_t *tmp; - - /* Check that a Tx process is ongoing */ - if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) - { - if (hirda->TxXferCount == 0U) - { - /* Disable the IRDA Transmit Data Register Empty Interrupt */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TXEIE); - - /* Enable the IRDA Transmit Complete Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - } - else - { - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (const uint16_t *) hirda->pTxBuffPtr; /* Derogation R.11.3 */ - hirda->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); - hirda->pTxBuffPtr += 2U; - } - else - { - hirda->Instance->TDR = (uint8_t)(*hirda->pTxBuffPtr & 0xFFU); - hirda->pTxBuffPtr++; - } - hirda->TxXferCount--; - } - } -} - -/** - * @brief Wrap up transmission in non-blocking mode. - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -static void IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) -{ - /* Disable the IRDA Transmit Complete Interrupt */ - CLEAR_BIT(hirda->Instance->CR1, USART_CR1_TCIE); - - /* Tx process is ended, restore hirda->gState to Ready */ - hirda->gState = HAL_IRDA_STATE_READY; - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Tx complete callback */ - hirda->TxCpltCallback(hirda); -#else - /* Call legacy weak Tx complete callback */ - HAL_IRDA_TxCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACK */ -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_IRDA_Receive_IT() - * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. - * @retval None - */ -static void IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) -{ - uint16_t *tmp; - uint16_t uhMask = hirda->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if (hirda->RxState == HAL_IRDA_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(hirda->Instance->RDR); - if ((hirda->Init.WordLength == IRDA_WORDLENGTH_9B) && (hirda->Init.Parity == IRDA_PARITY_NONE)) - { - tmp = (uint16_t *) hirda->pRxBuffPtr; /* Derogation R.11.3 */ - *tmp = (uint16_t)(uhdata & uhMask); - hirda->pRxBuffPtr += 2U; - } - else - { - *hirda->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); - hirda->pRxBuffPtr++; - } - - hirda->RxXferCount--; - if (hirda->RxXferCount == 0U) - { - /* Disable the IRDA Parity Error Interrupt and RXNE interrupt */ - CLEAR_BIT(hirda->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(hirda->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore hirda->RxState to Ready */ - hirda->RxState = HAL_IRDA_STATE_READY; - -#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) - /* Call registered Rx complete callback */ - hirda->RxCpltCallback(hirda); -#else - /* Call legacy weak Rx complete callback */ - HAL_IRDA_RxCpltCallback(hirda); -#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_IRDA_SEND_REQ(hirda, IRDA_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @} - */ - -#endif /* HAL_IRDA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c deleted file mode 100644 index b9f93417..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_iwdg.c +++ /dev/null @@ -1,282 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_iwdg.c - * @author MCD Application Team - * @brief IWDG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Independent Watchdog (IWDG) peripheral: - * + Initialization and Start functions - * + IO operation functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### IWDG Generic features ##### - ============================================================================== - [..] - (+) The IWDG can be started by either software or hardware (configurable - through option byte). - - (+) The IWDG is clocked by the Low-Speed Internal clock (LSI) and thus stays - active even if the main clock fails. - - (+) Once the IWDG is started, the LSI is forced ON and both cannot be - disabled. The counter starts counting down from the reset value (0xFFF). - When it reaches the end of count value (0x000) a reset signal is - generated (IWDG reset). - - (+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, - the IWDG_RLR value is reloaded into the counter and the watchdog reset - is prevented. - - (+) The IWDG is implemented in the VDD voltage domain that is still functional - in STOP and STANDBY mode (IWDG reset can wake up the CPU from STANDBY). - IWDGRST flag in RCC_CSR register can be used to inform when an IWDG - reset occurs. - - (+) Debug mode: When the microcontroller enters debug mode (core halted), - the IWDG counter either continues to work normally or stops, depending - on DBG_IWDG_STOP configuration bit in DBG module, accessible through - __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros. - - [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s - The IWDG timeout may vary due to LSI clock frequency dispersion. - STM32F7xx devices provide the capability to measure the LSI clock - frequency (LSI clock is internally connected to TIM16 CH1 input capture). - The measured value can be used to have an IWDG timeout with an - acceptable accuracy. - - [..] Default timeout value (necessary for IWDG_SR status register update): - Constant LSI_VALUE is defined based on the nominal LSI clock frequency. - This frequency being subject to variations as mentioned above, the - default timeout value (defined through constant HAL_IWDG_DEFAULT_TIMEOUT - below) may become too short or too long. - In such cases, this default timeout value can be tuned by redefining - the constant LSI_VALUE at user-application level (based, for instance, - on the measured LSI clock frequency as explained above). - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Use IWDG using HAL_IWDG_Init() function to : - (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI - clock is forced ON and IWDG counter starts counting down. - (++) Enable write access to configuration registers: - IWDG_PR, IWDG_RLR and IWDG_WINR. - (++) Configure the IWDG prescaler and counter reload value. This reload - value will be loaded in the IWDG counter each time the watchdog is - reloaded, then the IWDG will start counting down from this value. - (++) Depending on window parameter: - (+++) If Window Init parameter is same as Window register value, - nothing more is done but reload counter value in order to exit - function with exact time base. - (+++) Else modify Window register. This will automatically reload - watchdog counter. - (++) Wait for status flags to be reset. - - (#) Then the application program must refresh the IWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_IWDG_Refresh() function. - - *** IWDG HAL driver macros list *** - ==================================== - [..] - Below the list of most used macros in IWDG HAL driver: - (+) __HAL_IWDG_START: Enable the IWDG peripheral - (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in - the reload register - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_IWDG_MODULE_ENABLED -/** @addtogroup IWDG - * @brief IWDG HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup IWDG_Private_Defines IWDG Private Defines - * @{ - */ -/* Status register needs up to 5 LSI clock periods divided by the clock - prescaler to be updated. The number of LSI clock periods is upper-rounded to - 6 for the timeout value calculation. - The timeout value is calculated using the highest prescaler (256) and - the LSI_VALUE constant. The value of this constant can be changed by the user - to take into account possible LSI clock period variations. - The timeout value is multiplied by 1000 to be converted in milliseconds. - LSI startup time is also considered here by adding LSI_STARTUP_TIME - converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) -#define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_WVU | IWDG_SR_RVU | IWDG_SR_PVU) -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup IWDG_Exported_Functions - * @{ - */ - -/** @addtogroup IWDG_Exported_Functions_Group1 - * @brief Initialization and Start functions. - * -@verbatim - =============================================================================== - ##### Initialization and Start functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the IWDG according to the specified parameters in the - IWDG_InitTypeDef of associated handle. - (+) Manage Window option. - (+) Once initialization is performed in HAL_IWDG_Init function, Watchdog - is reloaded in order to exit function with correct time base. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the IWDG according to the specified parameters in the - * IWDG_InitTypeDef and start watchdog. Before exiting function, - * watchdog is refreshed in order to have correct time base. - * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) -{ - uint32_t tickstart; - - /* Check the IWDG handle allocation */ - if (hiwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance)); - assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler)); - assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); - assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); - - /* Enable IWDG. LSI is turned on automatically */ - __HAL_IWDG_START(hiwdg); - - /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing - 0x5555 in KR */ - IWDG_ENABLE_WRITE_ACCESS(hiwdg); - - /* Write to IWDG registers the Prescaler & Reload values to work with */ - hiwdg->Instance->PR = hiwdg->Init.Prescaler; - hiwdg->Instance->RLR = hiwdg->Init.Reload; - - /* Check pending flag, if previous update not done, return timeout */ - tickstart = HAL_GetTick(); - - /* Wait for register to be updated */ - while ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) - { - if ((HAL_GetTick() - tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) - { - if ((hiwdg->Instance->SR & IWDG_KERNEL_UPDATE_FLAGS) != 0x00u) - { - return HAL_TIMEOUT; - } - } - } - - /* If window parameter is different than current value, modify window - register */ - if (hiwdg->Instance->WINR != hiwdg->Init.Window) - { - /* Write to IWDG WINR the IWDG_Window value to compare with. In any case, - even if window feature is disabled, Watchdog will be reloaded by writing - windows register */ - hiwdg->Instance->WINR = hiwdg->Init.Window; - } - else - { - /* Reload IWDG counter with value defined in the reload register */ - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - } - - /* Return function status */ - return HAL_OK; -} - - -/** - * @} - */ - - -/** @addtogroup IWDG_Exported_Functions_Group2 - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Refresh the IWDG. - -@endverbatim - * @{ - */ - -/** - * @brief Refresh the IWDG. - * @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) -{ - /* Reload IWDG counter with value defined in the reload register */ - __HAL_IWDG_RELOAD_COUNTER(hiwdg); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_IWDG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c deleted file mode 100644 index 10c5a03f..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_jpeg.c +++ /dev/null @@ -1,4166 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_jpeg.c - * @author MCD Application Team - * @brief JPEG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the JPEG encoder/decoder peripheral: - * + Initialization and de-initialization functions - * + JPEG processing functions encoding and decoding - * + JPEG decoding Getting Info and encoding configuration setting - * + JPEG enable/disable header parsing functions (for decoding) - * + JPEG Input/Output Buffer configuration. - * + JPEG callback functions - * + JPEG Abort/Pause/Resume functions - * + JPEG custom quantization tables setting functions - * + IRQ handler management - * + Peripheral State and Error functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the JPEG peripheral using HAL_JPEG_Init : No initialization parameters are required. - Only the call to HAL_JPEG_Init is necessary to initialize the JPEG peripheral. - - (#) If operation is JPEG encoding use function HAL_JPEG_ConfigEncoding to set - the encoding parameters (mandatory before calling the encoding function). - the application can change the encoding parameter ImageQuality from - 1 to 100 to obtain a more or less quality (visual quality vs the original row image), - and inversely more or less jpg file size. - - (#) Note that for decoding operation the JPEG peripheral output data are organized in - YCbCr blocks called MCU (Minimum Coded Unit) as defioned in the JPEG specification - ISO/IEC 10918-1 standard. - It is up to the application to transform these YCbCr blocks to RGB data that can be display. - - Respectively, for Encoding operation the JPEG peripheral input should be organized - in YCbCr MCU blocks. It is up to the application to perform the necessary RGB to YCbCr - MCU blocks transformation before feeding the JPEG peripheral with data. - - (#) Use functions HAL_JPEG_Encode and HAL_JPEG_Decode to start respectively - a JPEG encoding/decoding operation in polling method (blocking). - - (#) Use functions HAL_JPEG_Encode_IT and HAL_JPEG_Decode_IT to start respectively - a JPEG encoding/decoding operation with Interrupt method (not blocking). - - (#) Use functions HAL_JPEG_Encode_DMA and HAL_JPEG_Decode_DMA to start respectively - a JPEG encoding/decoding operation with DMA method (not blocking). - - (#) Callback HAL_JPEG_InfoReadyCallback is asserted if the current operation - is a JPEG decoding to provide the application with JPEG image parameters. - This callback is asserted when the JPEG peripheral successfully parse the - JPEG header. - - (#) Callback HAL_JPEG_GetDataCallback is asserted for both encoding and decoding - operations to inform the application that the input buffer has been - consumed by the peripheral and to ask for a new data chunk if the operation - (encoding/decoding) has not been complete yet. - - (++) This CallBack should be implemented in the application side. It should - call the function HAL_JPEG_ConfigInputBuffer if new input data are available, - or call HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_INPUT - to inform the JPEG HAL driver that the ongoing operation shall pause waiting for the - application to provide a new input data chunk. - Once the application succeed getting new data and if the input has been paused, - the application can call the function HAL_JPEG_ConfigInputBuffer to set the new - input buffer and size, then resume the JPEG HAL input by calling new function HAL_JPEG_Resume. - If the application has ended feeding the HAL JPEG with input data (no more input data), the application - Should call the function HAL_JPEG_ConfigInputBuffer (within the callback HAL_JPEG_GetDataCallback) - with the parameter InDataLength set to zero. - - (++) The mechanism of HAL_JPEG_ConfigInputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows - to the application to provide the input data (for encoding or decoding) by chunks. - If the new input data chunk is not available (because data should be read from an input file - for example) the application can pause the JPEG input (using function HAL_JPEG_Pause) - Once the new input data chunk is available ( read from a file for example), the application - can call the function HAL_JPEG_ConfigInputBuffer to provide the HAL with the new chunk - then resume the JPEG HAL input by calling function HAL_JPEG_Resume. - - (++) The application can call functions HAL_JPEG_ConfigInputBuffer then HAL_JPEG_Resume. - any time (outside the HAL_JPEG_GetDataCallback) Once the new input chunk data available. - However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called - (if necessary) within the callback HAL_JPEG_GetDataCallback, i.e when the HAL JPEG has ended - Transferring the previous chunk buffer to the JPEG peripheral. - - (#) Callback HAL_JPEG_DataReadyCallback is asserted when the HAL JPEG driver - has filled the given output buffer with the given size. - - (++) This CallBack should be implemented in the application side. It should - call the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver - with the new output buffer location and size to be used to store next data chunk. - if the application is not ready to provide the output chunk location then it can - call the function HAL_JPEG_Pause with parameter XferSelection set to JPEG_PAUSE_RESUME_OUTPUT - to inform the JPEG HAL driver that it shall pause output data. Once the application - is ready to receive the new data chunk (output buffer location free or available) it should call - the function HAL_JPEG_ConfigOutputBuffer to provide the HAL JPEG driver - with the new output chunk buffer location and size, then call HAL_JPEG_Resume - to inform the HAL that it shall resume outputting data in the given output buffer. - - (++) The mechanism of HAL_JPEG_ConfigOutputBuffer/HAL_JPEG_Pause/HAL_JPEG_Resume allows - the application to receive data from the JPEG peripheral by chunks. when a chunk - is received, the application can pause the HAL JPEG output data to be able to process - these received data (YCbCr to RGB conversion in case of decoding or data storage in case - of encoding). - - (++) The application can call functions HAL_JPEG_ ConfigOutputBuffer then HAL_JPEG_Resume. - any time (outside the HAL_JPEG_DataReadyCallback) Once the output data buffer is free to use. - However, to keep data coherency, the function HAL_JPEG_Pause must be imperatively called - (if necessary) within the callback HAL_JPEG_ DataReadyCallback, i.e when the HAL JPEG has ended - Transferring the previous chunk buffer from the JPEG peripheral to the application. - - (#) Callback HAL_JPEG_EncodeCpltCallback is asserted when the HAL JPEG driver has - ended the current JPEG encoding operation, and all output data has been transmitted - to the application. - - (#) Callback HAL_JPEG_DecodeCpltCallback is asserted when the HAL JPEG driver has - ended the current JPEG decoding operation. and all output data has been transmitted - to the application. - - (#) Callback HAL_JPEG_ErrorCallback is asserted when an error occurred during - the current operation. the application can call the function HAL_JPEG_GetError() - to retrieve the error codes. - - (#) By default the HAL JPEG driver uses the default quantization tables - as provide in the JPEG specification (ISO/IEC 10918-1 standard) for encoding. - User can change these default tables if necessary using the function HAL_JPEG_SetUserQuantTables - Note that for decoding the quantization tables are automatically extracted from - the JPEG header. - - (#) To control JPEG state you can use the following function: HAL_JPEG_GetState() - - *** JPEG HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in JPEG HAL driver. - - (+) __HAL_JPEG_RESET_HANDLE_STATE : Reset JPEG handle state. - (+) __HAL_JPEG_ENABLE : Enable the JPEG peripheral. - (+) __HAL_JPEG_DISABLE : Disable the JPEG peripheral. - (+) __HAL_JPEG_GET_FLAG : Check the specified JPEG status flag. - (+) __HAL_JPEG_CLEAR_FLAG : Clear the specified JPEG status flag. - (+) __HAL_JPEG_ENABLE_IT : Enable the specified JPEG Interrupt. - (+) __HAL_JPEG_DISABLE_IT : Disable the specified JPEG Interrupt. - (+) __HAL_JPEG_GET_IT_SOURCE : returns the state of the specified JPEG Interrupt (Enabled or disabled). - - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_JPEG_RegisterCallback() or HAL_JPEG_RegisterXXXCallback() - to register an interrupt callback. - - Function HAL_JPEG_RegisterCallback() allows to register following callbacks: - (+) EncodeCpltCallback : callback for end of encoding operation. - (+) DecodeCpltCallback : callback for end of decoding operation. - (+) ErrorCallback : callback for error detection. - (+) MspInitCallback : JPEG MspInit. - (+) MspDeInitCallback : JPEG MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - For specific callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated - register callbacks : respectively HAL_JPEG_RegisterInfoReadyCallback(), - HAL_JPEG_RegisterGetDataCallback() and HAL_JPEG_RegisterDataReadyCallback(). - - Use function HAL_JPEG_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_JPEG_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) EncodeCpltCallback : callback for end of encoding operation. - (+) DecodeCpltCallback : callback for end of decoding operation. - (+) ErrorCallback : callback for error detection. - (+) MspInitCallback : JPEG MspInit. - (+) MspDeInitCallback : JPEG MspDeInit. - - For callbacks InfoReadyCallback, GetDataCallback and DataReadyCallback use dedicated - unregister callbacks : respectively HAL_JPEG_UnRegisterInfoReadyCallback(), - HAL_JPEG_UnRegisterGetDataCallback() and HAL_JPEG_UnRegisterDataReadyCallback(). - - By default, after the HAL_JPEG_Init() and when the state is HAL_JPEG_STATE_RESET - all callbacks are set to the corresponding weak functions : - examples HAL_JPEG_DecodeCpltCallback() , HAL_JPEG_GetDataCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_JPEG_Init()/ HAL_JPEG_DeInit() only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_JPEG_Init() / HAL_JPEG_DeInit() - keep and use the user MspInit/MspDeInit functions (registered beforehand) - - Callbacks can be registered/unregistered in HAL_JPEG_STATE_READY state only. - Exception done MspInit/MspDeInit callbacks that can be registered/unregistered - in HAL_JPEG_STATE_READY or HAL_JPEG_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_JPEG_RegisterCallback() before calling HAL_JPEG_DeInit() - or HAL_JPEG_Init() function. - - When The compilation define USE_HAL_JPEG_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_JPEG_MODULE_ENABLED - -#if defined (JPEG) - -/** @defgroup JPEG JPEG - * @brief JPEG HAL module driver. - * @{ - */ - -/* Private define ------------------------------------------------------------*/ -/** @addtogroup JPEG_Private_Constants - * @{ - */ -#define JPEG_TIMEOUT_VALUE ((uint32_t)1000) /* 1s */ -#define JPEG_AC_HUFF_TABLE_SIZE ((uint32_t)162) /* Huffman AC table size : 162 codes*/ -#define JPEG_DC_HUFF_TABLE_SIZE ((uint32_t)12) /* Huffman AC table size : 12 codes*/ - -#define JPEG_FIFO_SIZE ((uint32_t)16U) /* JPEG Input/Output HW FIFO size in words*/ - -#define JPEG_FIFO_TH_SIZE ((uint32_t)4U) /* JPEG Input/Output HW FIFO Threshold in words*/ - -#define JPEG_DMA_MASK ((uint32_t)0x00001800) /* JPEG DMA request Mask*/ -#define JPEG_DMA_IDMA ((uint32_t)JPEG_CR_IDMAEN) /* DMA request for the input FIFO */ -#define JPEG_DMA_ODMA ((uint32_t)JPEG_CR_ODMAEN) /* DMA request for the output FIFO */ - -#define JPEG_INTERRUPT_MASK ((uint32_t)0x0000007EU) /* JPEG Interrupt Mask*/ - -#define JPEG_CONTEXT_ENCODE ((uint32_t)0x00000001) /* JPEG context : operation is encoding*/ -#define JPEG_CONTEXT_DECODE ((uint32_t)0x00000002) /* JPEG context : operation is decoding*/ -#define JPEG_CONTEXT_OPERATION_MASK ((uint32_t)0x00000003) /* JPEG context : operation Mask */ - -#define JPEG_CONTEXT_POLLING ((uint32_t)0x00000004) /* JPEG context : Transfer use Polling */ -#define JPEG_CONTEXT_IT ((uint32_t)0x00000008) /* JPEG context : Transfer use Interrupt */ -#define JPEG_CONTEXT_DMA ((uint32_t)0x0000000C) /* JPEG context : Transfer use DMA */ -#define JPEG_CONTEXT_METHOD_MASK ((uint32_t)0x0000000C) /* JPEG context : Transfer Mask */ - - -#define JPEG_CONTEXT_CONF_ENCODING ((uint32_t)0x00000100) /* JPEG context : encoding config done */ - -#define JPEG_CONTEXT_PAUSE_INPUT ((uint32_t)0x00001000) /* JPEG context : Pause Input */ -#define JPEG_CONTEXT_PAUSE_OUTPUT ((uint32_t)0x00002000) /* JPEG context : Pause Output */ - -#define JPEG_CONTEXT_CUSTOM_TABLES ((uint32_t)0x00004000) /* JPEG context : Use custom quantization tables */ - -#define JPEG_CONTEXT_ENDING_DMA ((uint32_t)0x00008000) /* JPEG context : ending with DMA in progress */ - -#define JPEG_PROCESS_ONGOING ((uint32_t)0x00000000) /* Process is on going */ -#define JPEG_PROCESS_DONE ((uint32_t)0x00000001) /* Process is done (ends) */ -/** - * @} - */ - -/* Private typedef -----------------------------------------------------------*/ -/** @addtogroup JPEG_Private_Types - * @{ - */ - -/* - JPEG Huffman Table Structure definition : - This implementation of Huffman table structure is compliant with ISO/IEC 10918-1 standard , Annex C Huffman Table specification - */ -typedef struct -{ - /* These two fields directly represent the contents of a JPEG DHT marker */ - uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */ - - uint8_t HuffVal[162]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */ - - -} JPEG_ACHuffTableTypeDef; - -typedef struct -{ - /* These two fields directly represent the contents of a JPEG DHT marker */ - uint8_t Bits[16]; /*!< bits[k] = # of symbols with codes of length k bits, this parameter corresponds to BITS list in the Annex C */ - - uint8_t HuffVal[12]; /*!< The symbols, in order of incremented code length, this parameter corresponds to HUFFVAL list in the Annex C */ - - -} JPEG_DCHuffTableTypeDef; - -typedef struct -{ - uint8_t CodeLength[JPEG_AC_HUFF_TABLE_SIZE]; /*!< Code length */ - - uint32_t HuffmanCode[JPEG_AC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ - -} JPEG_AC_HuffCodeTableTypeDef; - -typedef struct -{ - uint8_t CodeLength[JPEG_DC_HUFF_TABLE_SIZE]; /*!< Code length */ - - uint32_t HuffmanCode[JPEG_DC_HUFF_TABLE_SIZE]; /*!< HuffmanCode */ - -} JPEG_DC_HuffCodeTableTypeDef; -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @addtogroup JPEG_Private_Macros - * @{ - */ -#define JPEG_ENABLE_DMA(__HANDLE__,__DMA__) ((__HANDLE__)->Instance->CR |= ((__DMA__) & JPEG_DMA_MASK)) -/*note : To disable a DMA request we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits - located in the same DMA request enable register (CR register). */ -#define JPEG_DISABLE_DMA(__HANDLE__,__DMA__) MODIFY_REG((__HANDLE__)->Instance->CR, ((__DMA__) & JPEG_DMA_MASK), 0UL) -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup JPEG_Private_Variables - * @{ - */ - -static const JPEG_DCHuffTableTypeDef JPEG_DCLUM_HuffTable = -{ - { 0, 1, 5, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 }, /*Bits*/ - - { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ - -}; - -static const JPEG_DCHuffTableTypeDef JPEG_DCCHROM_HuffTable = -{ - { 0, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 }, /*Bits*/ - - { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xa, 0xb } /*HUFFVAL */ -}; - -static const JPEG_ACHuffTableTypeDef JPEG_ACLUM_HuffTable = -{ - { 0, 2, 1, 3, 3, 2, 4, 3, 5, 5, 4, 4, 0, 0, 1, 0x7d }, /*Bits*/ - - { - 0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12, /*HUFFVAL */ - 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, - 0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08, - 0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0, - 0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16, - 0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28, - 0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, - 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, - 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, - 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, - 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, - 0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, - 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, - 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, - 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, - 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5, - 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4, - 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2, - 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea, - 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, - 0xf9, 0xfa - } -}; - -static const JPEG_ACHuffTableTypeDef JPEG_ACCHROM_HuffTable = -{ - { 0, 2, 1, 2, 4, 4, 3, 4, 7, 5, 4, 4, 0, 1, 2, 0x77 }, /*Bits*/ - - { - 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, /*HUFFVAL */ - 0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71, - 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, - 0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0, - 0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34, - 0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26, - 0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38, - 0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, - 0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, - 0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, - 0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, - 0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, - 0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, - 0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, - 0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, - 0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, - 0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, - 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, - 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, - 0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, - 0xf9, 0xfa - } -}; - -static const uint8_t JPEG_ZIGZAG_ORDER[JPEG_QUANT_TABLE_SIZE] = -{ - 0, 1, 8, 16, 9, 2, 3, 10, - 17, 24, 32, 25, 18, 11, 4, 5, - 12, 19, 26, 33, 40, 48, 41, 34, - 27, 20, 13, 6, 7, 14, 21, 28, - 35, 42, 49, 56, 57, 50, 43, 36, - 29, 22, 15, 23, 30, 37, 44, 51, - 58, 59, 52, 45, 38, 31, 39, 46, - 53, 60, 61, 54, 47, 55, 62, 63 -}; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup JPEG_Private_Functions_Prototypes - * @{ - */ - -static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK); -static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, - JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable); -static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, - JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable); -static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, - const __IO uint32_t *DCTableAddress); -static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, - const __IO uint32_t *ACTableAddress); -static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg); -static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg); -static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, - __IO uint32_t *QTableAddress); -static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg); -static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg); -static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg); - -static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg); -static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg); -static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords); -static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords); -static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg); - -static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg); -static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg); -static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg); -static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg); -static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma); -static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma); -static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma); -static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) ; - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions JPEG Exported Functions - * @{ - */ - -/** @defgroup JPEG_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions. - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the JPEG peripheral and creates the associated handle - (+) DeInitialize the JPEG peripheral - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the JPEG according to the specified - * parameters in the JPEG_InitTypeDef and creates the associated handle. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg) -{ - /* These are the sample quantization tables given in JPEG spec ISO/IEC 10918-1 standard , section K.1. */ - static const uint8_t JPEG_LUM_QuantTable[JPEG_QUANT_TABLE_SIZE] = - { - 16, 11, 10, 16, 24, 40, 51, 61, - 12, 12, 14, 19, 26, 58, 60, 55, - 14, 13, 16, 24, 40, 57, 69, 56, - 14, 17, 22, 29, 51, 87, 80, 62, - 18, 22, 37, 56, 68, 109, 103, 77, - 24, 35, 55, 64, 81, 104, 113, 92, - 49, 64, 78, 87, 103, 121, 120, 101, - 72, 92, 95, 98, 112, 100, 103, 99 - }; - static const uint8_t JPEG_CHROM_QuantTable[JPEG_QUANT_TABLE_SIZE] = - { - 17, 18, 24, 47, 99, 99, 99, 99, - 18, 21, 26, 66, 99, 99, 99, 99, - 24, 26, 56, 99, 99, 99, 99, 99, - 47, 66, 99, 99, 99, 99, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99, - 99, 99, 99, 99, 99, 99, 99, 99 - }; - - /* Check the JPEG handle allocation */ - if (hjpeg == NULL) - { - return HAL_ERROR; - } - -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - if (hjpeg->State == HAL_JPEG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hjpeg->Lock = HAL_UNLOCKED; - - hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback */ - hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */ - hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */ - hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback; /* Legacy weak ErrorCallback */ - hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback; /* Legacy weak GetDataCallback */ - hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback; /* Legacy weak DataReadyCallback */ - - if (hjpeg->MspInitCallback == NULL) - { - hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hjpeg->MspInitCallback(hjpeg); - } -#else - if (hjpeg->State == HAL_JPEG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hjpeg->Lock = HAL_UNLOCKED; - - /* Init the low level hardware : GPIO, CLOCK */ - HAL_JPEG_MspInit(hjpeg); - } -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - /* Start the JPEG Core*/ - __HAL_JPEG_ENABLE(hjpeg); - - /* Stop the JPEG encoding/decoding process*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); - - /* Disable All DMA requests */ - JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK); - - /* Flush input and output FIFOs*/ - hjpeg->Instance->CR |= JPEG_CR_IFF; - hjpeg->Instance->CR |= JPEG_CR_OFF; - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); - - /* init default quantization tables*/ - hjpeg->QuantTable0 = (uint8_t *)((uint32_t)JPEG_LUM_QuantTable); - hjpeg->QuantTable1 = (uint8_t *)((uint32_t)JPEG_CHROM_QuantTable); - hjpeg->QuantTable2 = NULL; - hjpeg->QuantTable3 = NULL; - - /* init the default Huffman tables*/ - if (JPEG_Set_HuffEnc_Mem(hjpeg) != HAL_OK) - { - hjpeg->ErrorCode = HAL_JPEG_ERROR_HUFF_TABLE; - - return HAL_ERROR; - } - - /* Enable header processing*/ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; - - /* Reset JpegInCount and JpegOutCount */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /* Reset the JPEG ErrorCode */ - hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; - - /*Clear the context filelds*/ - hjpeg->Context = 0; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the JPEG peripheral. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg) -{ - /* Check the JPEG handle allocation */ - if (hjpeg == NULL) - { - return HAL_ERROR; - } - -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - if (hjpeg->MspDeInitCallback == NULL) - { - hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hjpeg->MspDeInitCallback(hjpeg); - -#else - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_JPEG_MspDeInit(hjpeg); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - /* Reset the JPEG ErrorCode */ - hjpeg->ErrorCode = HAL_JPEG_ERROR_NONE; - - /* Reset JpegInCount and JpegOutCount */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_RESET; - - /*Clear the context fields*/ - hjpeg->Context = 0; - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the JPEG MSP. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes JPEG MSP. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User JPEG Callback - * To be used instead of the weak predefined callback - * @param hjpeg JPEG handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID - * @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID - * @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID - * @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID, - pJPEG_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (HAL_JPEG_STATE_READY == hjpeg->State) - { - switch (CallbackID) - { - case HAL_JPEG_ENCODE_CPLT_CB_ID : - hjpeg->EncodeCpltCallback = pCallback; - break; - - case HAL_JPEG_DECODE_CPLT_CB_ID : - hjpeg->DecodeCpltCallback = pCallback; - break; - - case HAL_JPEG_ERROR_CB_ID : - hjpeg->ErrorCallback = pCallback; - break; - - case HAL_JPEG_MSPINIT_CB_ID : - hjpeg->MspInitCallback = pCallback; - break; - - case HAL_JPEG_MSPDEINIT_CB_ID : - hjpeg->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_JPEG_STATE_RESET == hjpeg->State) - { - switch (CallbackID) - { - case HAL_JPEG_MSPINIT_CB_ID : - hjpeg->MspInitCallback = pCallback; - break; - - case HAL_JPEG_MSPDEINIT_CB_ID : - hjpeg->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - return status; -} - -/** - * @brief Unregister a JPEG Callback - * JPEG callabck is redirected to the weak predefined callback - * @param hjpeg JPEG handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * This parameter can be one of the following values: - * @arg @ref HAL_JPEG_ENCODE_CPLT_CB_ID Encode Complete callback ID - * @arg @ref HAL_JPEG_DECODE_CPLT_CB_ID Decode Complete callback ID - * @arg @ref HAL_JPEG_ERROR_CB_ID Error callback ID - * @arg @ref HAL_JPEG_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_JPEG_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (HAL_JPEG_STATE_READY == hjpeg->State) - { - switch (CallbackID) - { - case HAL_JPEG_ENCODE_CPLT_CB_ID : - hjpeg->EncodeCpltCallback = HAL_JPEG_EncodeCpltCallback; /* Legacy weak EncodeCpltCallback */ - break; - - case HAL_JPEG_DECODE_CPLT_CB_ID : - hjpeg->DecodeCpltCallback = HAL_JPEG_DecodeCpltCallback; /* Legacy weak DecodeCpltCallback */ - break; - - case HAL_JPEG_ERROR_CB_ID : - hjpeg->ErrorCallback = HAL_JPEG_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_JPEG_MSPINIT_CB_ID : - hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_JPEG_MSPDEINIT_CB_ID : - hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_JPEG_STATE_RESET == hjpeg->State) - { - switch (CallbackID) - { - case HAL_JPEG_MSPINIT_CB_ID : - hjpeg->MspInitCallback = HAL_JPEG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_JPEG_MSPDEINIT_CB_ID : - hjpeg->MspDeInitCallback = HAL_JPEG_MspDeInit; /* Legacy weak MspInit */ - break; - - default : - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - return status; -} - -/** - * @brief Register Info Ready JPEG Callback - * To be used instead of the weak HAL_JPEG_InfoReadyCallback() predefined callback - * @param hjpeg JPEG handle - * @param pCallback pointer to the Info Ready Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg, - pJPEG_InfoReadyCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (HAL_JPEG_STATE_READY == hjpeg->State) - { - hjpeg->InfoReadyCallback = pCallback; - } - else - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - return status; -} - -/** - * @brief UnRegister the Info Ready JPEG Callback - * Info Ready JPEG Callback is redirected to the weak HAL_JPEG_InfoReadyCallback() predefined callback - * @param hjpeg JPEG handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (HAL_JPEG_STATE_READY == hjpeg->State) - { - hjpeg->InfoReadyCallback = HAL_JPEG_InfoReadyCallback; /* Legacy weak InfoReadyCallback */ - } - else - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - return status; -} - -/** - * @brief Register Get Data JPEG Callback - * To be used instead of the weak HAL_JPEG_GetDataCallback() predefined callback - * @param hjpeg JPEG handle - * @param pCallback pointer to the Get Data Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (HAL_JPEG_STATE_READY == hjpeg->State) - { - hjpeg->GetDataCallback = pCallback; - } - else - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - return status; -} - -/** - * @brief UnRegister the Get Data JPEG Callback - * Get Data JPEG Callback is redirected to the weak HAL_JPEG_GetDataCallback() predefined callback - * @param hjpeg JPEG handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (HAL_JPEG_STATE_READY == hjpeg->State) - { - hjpeg->GetDataCallback = HAL_JPEG_GetDataCallback; /* Legacy weak GetDataCallback */ - } - else - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - return status; -} - -/** - * @brief Register Data Ready JPEG Callback - * To be used instead of the weak HAL_JPEG_DataReadyCallback() predefined callback - * @param hjpeg JPEG handle - * @param pCallback pointer to the Get Data Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg, - pJPEG_DataReadyCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (HAL_JPEG_STATE_READY == hjpeg->State) - { - hjpeg->DataReadyCallback = pCallback; - } - else - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - return status; -} - -/** - * @brief UnRegister the Data Ready JPEG Callback - * Get Data Ready Callback is redirected to the weak HAL_JPEG_DataReadyCallback() predefined callback - * @param hjpeg JPEG handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (HAL_JPEG_STATE_READY == hjpeg->State) - { - hjpeg->DataReadyCallback = HAL_JPEG_DataReadyCallback; /* Legacy weak DataReadyCallback */ - } - else - { - /* Update the error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hjpeg); - return status; -} - -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions_Group2 Configuration functions - * @brief JPEG Configuration functions. - * -@verbatim - ============================================================================== - ##### Configuration functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_JPEG_ConfigEncoding() : JPEG encoding configuration - (+) HAL_JPEG_GetInfo() : Extract the image configuration from the JPEG header during the decoding - (+) HAL_JPEG_EnableHeaderParsing() : Enable JPEG Header parsing for decoding - (+) HAL_JPEG_DisableHeaderParsing() : Disable JPEG Header parsing for decoding - (+) HAL_JPEG_SetUserQuantTables : Modify the default Quantization tables used for JPEG encoding. - -@endverbatim - * @{ - */ - -/** - * @brief Set the JPEG encoding configuration. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pConf pointer to a JPEG_ConfTypeDef structure that contains - * the encoding configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf) -{ - uint32_t error; - uint32_t numberMCU; - uint32_t hfactor; - uint32_t vfactor; - uint32_t hMCU; - uint32_t vMCU; - - /* Check the JPEG handle allocation */ - if ((hjpeg == NULL) || (pConf == NULL)) - { - return HAL_ERROR; - } - else - { - /* Check the parameters */ - assert_param(IS_JPEG_COLORSPACE(pConf->ColorSpace)); - assert_param(IS_JPEG_CHROMASUBSAMPLING(pConf->ChromaSubsampling)); - assert_param(IS_JPEG_IMAGE_QUALITY(pConf->ImageQuality)); - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State == HAL_JPEG_STATE_READY) - { - hjpeg->State = HAL_JPEG_STATE_BUSY; - - hjpeg->Conf.ColorSpace = pConf->ColorSpace; - hjpeg->Conf.ChromaSubsampling = pConf->ChromaSubsampling; - hjpeg->Conf.ImageHeight = pConf->ImageHeight; - hjpeg->Conf.ImageWidth = pConf->ImageWidth; - hjpeg->Conf.ImageQuality = pConf->ImageQuality; - - /* Reset the Color Space : by default only one quantization table is used*/ - hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_COLORSPACE; - - /* Set Number of color components*/ - if (hjpeg->Conf.ColorSpace == JPEG_GRAYSCALE_COLORSPACE) - { - /*Gray Scale is only one component 8x8 blocks i.e 4:4:4*/ - hjpeg->Conf.ChromaSubsampling = JPEG_444_SUBSAMPLING; - - JPEG_SetColorGrayScale(hjpeg); - /* Set quantization table 0*/ - error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); - } - else if (hjpeg->Conf.ColorSpace == JPEG_YCBCR_COLORSPACE) - { - /* - Set the Color Space for YCbCr : 2 quantization tables are used - one for Luminance(Y) and one for both Chrominances (Cb & Cr) - */ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_0; - - JPEG_SetColorYCBCR(hjpeg); - - /* Set quantization table 0*/ - error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); - /*By default quantization table 0 for component 0 and quantization table 1 for both components 1 and 2*/ - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1)); - - if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL) - { - /*Use user customized quantization tables , 1 table per component*/ - /* use 3 quantization tables , one for each component*/ - hjpeg->Instance->CONFR1 &= (~JPEG_CONFR1_COLORSPACE); - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE_1; - - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2)); - - /*Use Quantization 1 table for component 1*/ - hjpeg->Instance->CONFR5 &= (~JPEG_CONFR5_QT); - hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; - - /*Use Quantization 2 table for component 2*/ - hjpeg->Instance->CONFR6 &= (~JPEG_CONFR6_QT); - hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; - } - } - else /* ColorSpace == JPEG_CMYK_COLORSPACE */ - { - JPEG_SetColorCMYK(hjpeg); - - /* Set quantization table 0*/ - error = JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable0, (hjpeg->Instance->QMEM0)); - /*By default quantization table 0 for All components*/ - - if ((hjpeg->Context & JPEG_CONTEXT_CUSTOM_TABLES) != 0UL) - { - /*Use user customized quantization tables , 1 table per component*/ - /* use 4 quantization tables , one for each component*/ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_COLORSPACE; - - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable1, (hjpeg->Instance->QMEM1)); - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable2, (hjpeg->Instance->QMEM2)); - error |= JPEG_Set_Quantization_Mem(hjpeg, hjpeg->QuantTable3, (hjpeg->Instance->QMEM3)); - - /*Use Quantization 1 table for component 1*/ - hjpeg->Instance->CONFR5 |= JPEG_CONFR5_QT_0; - - /*Use Quantization 2 table for component 2*/ - hjpeg->Instance->CONFR6 |= JPEG_CONFR6_QT_1; - - /*Use Quantization 3 table for component 3*/ - hjpeg->Instance->CONFR7 |= JPEG_CONFR7_QT; - } - } - - if (error != 0UL) - { - hjpeg->ErrorCode = HAL_JPEG_ERROR_QUANT_TABLE; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Set the JPEG State to ready */ - hjpeg->State = HAL_JPEG_STATE_READY; - - return HAL_ERROR; - } - /* Set the image size*/ - /* set the number of lines*/ - MODIFY_REG(hjpeg->Instance->CONFR1, JPEG_CONFR1_YSIZE, ((hjpeg->Conf.ImageHeight & 0x0000FFFFUL) << 16)); - /* set the number of pixels per line*/ - MODIFY_REG(hjpeg->Instance->CONFR3, JPEG_CONFR3_XSIZE, ((hjpeg->Conf.ImageWidth & 0x0000FFFFUL) << 16)); - - - if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) /* 4:2:0*/ - { - hfactor = 16; - vfactor = 16; - } - else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) /* 4:2:2*/ - { - hfactor = 16; - vfactor = 8; - } - else /* Default is 8x8 MCU, 4:4:4*/ - { - hfactor = 8; - vfactor = 8; - } - - hMCU = (hjpeg->Conf.ImageWidth / hfactor); - if ((hjpeg->Conf.ImageWidth % hfactor) != 0UL) - { - hMCU++; /*+1 for horizontal incomplete MCU */ - } - - vMCU = (hjpeg->Conf.ImageHeight / vfactor); - if ((hjpeg->Conf.ImageHeight % vfactor) != 0UL) - { - vMCU++; /*+1 for vertical incomplete MCU */ - } - - numberMCU = (hMCU * vMCU) - 1UL; /* Bit Field JPEG_CONFR2_NMCU shall be set to NB_MCU - 1*/ - /* Set the number of MCU*/ - hjpeg->Instance->CONFR2 = (numberMCU & JPEG_CONFR2_NMCU); - - hjpeg->Context |= JPEG_CONTEXT_CONF_ENCODING; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Set the JPEG State to ready */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Return function status */ - return HAL_BUSY; - } - } -} - -/** - * @brief Extract the image configuration from the JPEG header during the decoding - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains - * The JPEG decoded header information - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) -{ - uint32_t yblockNb; - uint32_t cBblockNb; - uint32_t cRblockNb; - - /* Check the JPEG handle allocation */ - if ((hjpeg == NULL) || (pInfo == NULL)) - { - return HAL_ERROR; - } - - /*Read the conf parameters */ - if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF_1) - { - pInfo->ColorSpace = JPEG_YCBCR_COLORSPACE; - } - else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == 0UL) - { - pInfo->ColorSpace = JPEG_GRAYSCALE_COLORSPACE; - } - else if ((hjpeg->Instance->CONFR1 & JPEG_CONFR1_NF) == JPEG_CONFR1_NF) - { - pInfo->ColorSpace = JPEG_CMYK_COLORSPACE; - } - else - { - return HAL_ERROR; - } - - pInfo->ImageHeight = (hjpeg->Instance->CONFR1 & 0xFFFF0000UL) >> 16; - pInfo->ImageWidth = (hjpeg->Instance->CONFR3 & 0xFFFF0000UL) >> 16; - - if ((pInfo->ColorSpace == JPEG_YCBCR_COLORSPACE) || (pInfo->ColorSpace == JPEG_CMYK_COLORSPACE)) - { - yblockNb = (hjpeg->Instance->CONFR4 & JPEG_CONFR4_NB) >> 4; - cBblockNb = (hjpeg->Instance->CONFR5 & JPEG_CONFR5_NB) >> 4; - cRblockNb = (hjpeg->Instance->CONFR6 & JPEG_CONFR6_NB) >> 4; - - if ((yblockNb == 1UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) - { - pInfo->ChromaSubsampling = JPEG_422_SUBSAMPLING; /*16x8 block*/ - } - else if ((yblockNb == 0UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) - { - pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; - } - else if ((yblockNb == 3UL) && (cBblockNb == 0UL) && (cRblockNb == 0UL)) - { - pInfo->ChromaSubsampling = JPEG_420_SUBSAMPLING; - } - else /*Default is 4:4:4*/ - { - pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; - } - } - else - { - pInfo->ChromaSubsampling = JPEG_444_SUBSAMPLING; - } - - pInfo->ImageQuality = JPEG_GetQuality(hjpeg); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enable JPEG Header parsing for decoding - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for the JPEG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg) -{ - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State == HAL_JPEG_STATE_READY) - { - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - /* Enable header processing*/ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_HDR; - - /* Process unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - return HAL_OK; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } -} - -/** - * @brief Disable JPEG Header parsing for decoding - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for the JPEG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg) -{ - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State == HAL_JPEG_STATE_READY) - { - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - /* Disable header processing*/ - hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_HDR; - - /* Process unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - return HAL_OK; - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } -} - -/** - * @brief Modify the default Quantization tables used for JPEG encoding. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param QTable0 pointer to uint8_t , define the user quantification table for color component 1. - * If NULL assume no need to update the table and no error return - * @param QTable1 pointer to uint8_t , define the user quantification table for color component 2. - * If NULL assume no need to update the table and no error return. - * @param QTable2 pointer to uint8_t , define the user quantification table for color component 3, - * If NULL assume no need to update the table and no error return. - * @param QTable3 pointer to uint8_t , define the user quantification table for color component 4. - * If NULL assume no need to update the table and no error return. - * - * @retval HAL status - */ - - -HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, - uint8_t *QTable2, uint8_t *QTable3) -{ - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State == HAL_JPEG_STATE_READY) - { - /* Change the DMA state */ - hjpeg->State = HAL_JPEG_STATE_BUSY; - - hjpeg->Context |= JPEG_CONTEXT_CUSTOM_TABLES; - - hjpeg->QuantTable0 = QTable0; - hjpeg->QuantTable1 = QTable1; - hjpeg->QuantTable2 = QTable2; - hjpeg->QuantTable3 = QTable3; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the DMA state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } -} - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions_Group3 encoding/decoding processing functions - * @brief processing functions. - * -@verbatim - ============================================================================== - ##### JPEG processing functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) HAL_JPEG_Encode() : JPEG encoding with polling process - (+) HAL_JPEG_Decode() : JPEG decoding with polling process - (+) HAL_JPEG_Encode_IT() : JPEG encoding with interrupt process - (+) HAL_JPEG_Decode_IT() : JPEG decoding with interrupt process - (+) HAL_JPEG_Encode_DMA() : JPEG encoding with DMA process - (+) HAL_JPEG_Decode_DMA() : JPEG decoding with DMA process - (+) HAL_JPEG_Pause() : Pause the Input/Output processing - (+) HAL_JPEG_Resume() : Resume the JPEG Input/Output processing - (+) HAL_JPEG_ConfigInputBuffer() : Config Encoding/Decoding Input Buffer - (+) HAL_JPEG_ConfigOutputBuffer() : Config Encoding/Decoding Output Buffer - (+) HAL_JPEG_Abort() : Aborts the JPEG Encoding/Decoding - -@endverbatim - * @{ - */ - -/** - * @brief Starts JPEG encoding with polling processing - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataInMCU Pointer to the Input buffer - * @param InDataLength size in bytes Input buffer - * @param pDataOut Pointer to the jpeg output data buffer - * @param OutDataLength size in bytes of the Output buffer - * @param Timeout Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, - uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param((InDataLength >= 4UL)); - assert_param((OutDataLength >= 4UL)); - - /* Check In/out buffer allocation and size */ - if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) - { - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State != HAL_JPEG_STATE_READY) - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - - if (hjpeg->State == HAL_JPEG_STATE_READY) - { - if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; - - /*Set the Context to Encode with Polling*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_POLLING); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataInMCU; - hjpeg->pJpegOutBuffPtr = pDataOut; - hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /* In Data length must be multiple of 4 Bytes (1 word)*/ - hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /* Out Data length must be multiple of 4 Bytes (1 word)*/ - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - /*JPEG data processing : In/Out FIFO transfer*/ - while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - - /* Update error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_READY; - - return HAL_TIMEOUT; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_READY; - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_ERROR; - } - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG decoding with polling processing - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataIn Pointer to the input data buffer - * @param InDataLength size in bytes Input buffer - * @param pDataOutMCU Pointer to the Output data buffer - * @param OutDataLength size in bytes of the Output buffer - * @param Timeout Specify Timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, - uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param((InDataLength >= 4UL)); - assert_param((OutDataLength >= 4UL)); - - /* Check In/out buffer allocation and size */ - if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - /* Get tick */ - tickstart = HAL_GetTick(); - - if (hjpeg->State == HAL_JPEG_STATE_READY) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; - - /*Set the Context to Decode with Polling*/ - /*Set the Context to Encode with Polling*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_POLLING); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataIn; - hjpeg->pJpegOutBuffPtr = pDataOutMCU; - hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/ - hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/ - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - /*JPEG data processing : In/Out FIFO transfer*/ - while ((JPEG_Process(hjpeg) == JPEG_PROCESS_ONGOING)) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - - /* Update error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_READY; - - return HAL_TIMEOUT; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_READY; - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG encoding with interrupt processing - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataInMCU Pointer to the Input buffer - * @param InDataLength size in bytes Input buffer - * @param pDataOut Pointer to the jpeg output data buffer - * @param OutDataLength size in bytes of the Output buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, - uint8_t *pDataOut, uint32_t OutDataLength) -{ - /* Check the parameters */ - assert_param((InDataLength >= 4UL)); - assert_param((OutDataLength >= 4UL)); - - /* Check In/out buffer allocation and size */ - if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State != HAL_JPEG_STATE_READY) - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - else - { - if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; - - /*Set the Context to Encode with IT*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_IT); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataInMCU; - hjpeg->pJpegOutBuffPtr = pDataOut; - hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/ - hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/ - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_ERROR; - } - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG decoding with interrupt processing - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataIn Pointer to the input data buffer - * @param InDataLength size in bytes Input buffer - * @param pDataOutMCU Pointer to the Output data buffer - * @param OutDataLength size in bytes of the Output buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, - uint8_t *pDataOutMCU, uint32_t OutDataLength) -{ - /* Check the parameters */ - assert_param((InDataLength >= 4UL)); - assert_param((OutDataLength >= 4UL)); - - /* Check In/out buffer allocation and size */ - if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State == HAL_JPEG_STATE_READY) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; - - /*Set the Context to Decode with IT*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_IT); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataIn; - hjpeg->pJpegOutBuffPtr = pDataOutMCU; - hjpeg->InDataLength = InDataLength - (InDataLength % 4UL); /*In Data length must be multiple of 4 Bytes (1 word)*/ - hjpeg->OutDataLength = OutDataLength - (OutDataLength % 4UL); /*Out Data length must be multiple of 4 Bytes (1 word)*/ - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG encoding with DMA processing - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataInMCU Pointer to the Input buffer - * @param InDataLength size in bytes Input buffer - * @param pDataOut Pointer to the jpeg output data buffer - * @param OutDataLength size in bytes of the Output buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, - uint8_t *pDataOut, uint32_t OutDataLength) -{ - /* Check the parameters */ - assert_param((InDataLength >= 4UL)); - assert_param((OutDataLength >= 4UL)); - - /* Check In/out buffer allocation and size */ - if ((hjpeg == NULL) || (pDataInMCU == NULL) || (pDataOut == NULL)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State != HAL_JPEG_STATE_READY) - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - else - { - if ((hjpeg->Context & JPEG_CONTEXT_CONF_ENCODING) == JPEG_CONTEXT_CONF_ENCODING) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_ENCODING; - - /*Set the Context to Encode with DMA*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_ENCODE | JPEG_CONTEXT_DMA); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataInMCU; - hjpeg->pJpegOutBuffPtr = pDataOut; - hjpeg->InDataLength = InDataLength; - hjpeg->OutDataLength = OutDataLength; - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - /* JPEG encoding process using DMA */ - if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK) - { - /* Update State */ - hjpeg->State = HAL_JPEG_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_ERROR; - } - - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_ERROR; - } - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts JPEG decoding with DMA processing - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataIn Pointer to the input data buffer - * @param InDataLength size in bytes Input buffer - * @param pDataOutMCU Pointer to the Output data buffer - * @param OutDataLength size in bytes of the Output buffer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength, - uint8_t *pDataOutMCU, uint32_t OutDataLength) -{ - /* Check the parameters */ - assert_param((InDataLength >= 4UL)); - assert_param((OutDataLength >= 4UL)); - - /* Check In/out buffer allocation and size */ - if ((hjpeg == NULL) || (pDataIn == NULL) || (pDataOutMCU == NULL)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hjpeg); - - if (hjpeg->State == HAL_JPEG_STATE_READY) - { - /*Change JPEG state*/ - hjpeg->State = HAL_JPEG_STATE_BUSY_DECODING; - - /*Set the Context to Decode with DMA*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK); - hjpeg->Context |= (JPEG_CONTEXT_DECODE | JPEG_CONTEXT_DMA); - - /*Store In/out buffers pointers and size*/ - hjpeg->pJpegInBuffPtr = pDataIn; - hjpeg->pJpegOutBuffPtr = pDataOutMCU; - hjpeg->InDataLength = InDataLength; - hjpeg->OutDataLength = OutDataLength; - - /*Reset In/out data counter */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Init decoding process*/ - JPEG_Init_Process(hjpeg); - - /* JPEG decoding process using DMA */ - if (JPEG_DMA_StartProcess(hjpeg) != HAL_OK) - { - /* Update State */ - hjpeg->State = HAL_JPEG_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_ERROR; - } - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - return HAL_BUSY; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Pause the JPEG Input/Output processing - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param XferSelection This parameter can be one of the following values : - * JPEG_PAUSE_RESUME_INPUT : Pause Input processing - * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing - * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) -{ - uint32_t mask = 0; - - assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); - - if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) - { - hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; - mask |= JPEG_DMA_IDMA; - } - if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) - { - hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; - mask |= JPEG_DMA_ODMA; - } - JPEG_DISABLE_DMA(hjpeg, mask); - - } - else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - - if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) - { - hjpeg->Context |= JPEG_CONTEXT_PAUSE_INPUT; - mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); - } - if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) - { - hjpeg->Context |= JPEG_CONTEXT_PAUSE_OUTPUT; - mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); - } - __HAL_JPEG_DISABLE_IT(hjpeg, mask); - - } - else - { - /* Nothing to do */ - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Resume the JPEG Input/Output processing - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param XferSelection This parameter can be one of the following values : - * JPEG_PAUSE_RESUME_INPUT : Resume Input processing - * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing - * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection) -{ - uint32_t mask = 0; - - assert_param(IS_JPEG_PAUSE_RESUME_STATE(XferSelection)); - - if ((hjpeg->Context & (JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)) == 0UL) - { - /* if nothing paused to resume return error*/ - return HAL_ERROR; - } - - if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - - if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) - { - hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); - mask |= JPEG_DMA_IDMA; - - /*JPEG Input DMA transfer data number must be multiple of DMA buffer size - as the destination is a 32 bits register */ - hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); - - if (hjpeg->InDataLength > 0UL) - { - /* Start DMA FIFO In transfer */ - if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, - hjpeg->InDataLength >> 2) != HAL_OK) - { - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - hjpeg->State = HAL_JPEG_STATE_ERROR; - return HAL_ERROR; - } - } - } - if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) - { - hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); - - if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL) - { - JPEG_DMA_PollResidualData(hjpeg); - } - else - { - mask |= JPEG_DMA_ODMA; - - /* Start DMA FIFO Out transfer */ - if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, - hjpeg->OutDataLength >> 2) != HAL_OK) - { - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - hjpeg->State = HAL_JPEG_STATE_ERROR; - return HAL_ERROR; - } - } - - } - JPEG_ENABLE_DMA(hjpeg, mask); - - } - else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - if ((XferSelection & JPEG_PAUSE_RESUME_INPUT) == JPEG_PAUSE_RESUME_INPUT) - { - hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_INPUT); - mask |= (JPEG_IT_IFT | JPEG_IT_IFNF); - } - if ((XferSelection & JPEG_PAUSE_RESUME_OUTPUT) == JPEG_PAUSE_RESUME_OUTPUT) - { - hjpeg->Context &= (~JPEG_CONTEXT_PAUSE_OUTPUT); - mask |= (JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC); - } - __HAL_JPEG_ENABLE_IT(hjpeg, mask); - - } - else - { - /* Nothing to do */ - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Config Encoding/Decoding Input Buffer. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module. - * @param pNewInputBuffer Pointer to the new input data buffer - * @param InDataLength Size in bytes of the new Input data buffer - * @retval HAL status - */ -void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength) -{ - hjpeg->pJpegInBuffPtr = pNewInputBuffer; - hjpeg->InDataLength = InDataLength; -} - -/** - * @brief Config Encoding/Decoding Output Buffer. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module. - * @param pNewOutputBuffer Pointer to the new output data buffer - * @param OutDataLength Size in bytes of the new Output data buffer - * @retval HAL status - */ -void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength) -{ - hjpeg->pJpegOutBuffPtr = pNewOutputBuffer; - hjpeg->OutDataLength = OutDataLength; -} - -/** - * @brief Aborts the JPEG Encoding/Decoding. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t tickstart; - uint32_t tmpContext; - tmpContext = hjpeg->Context; - - /*Reset the Context operation and method*/ - hjpeg->Context &= ~(JPEG_CONTEXT_OPERATION_MASK | JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA); - - if ((tmpContext & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - /* Stop the DMA In/out Xfer*/ - if (HAL_DMA_Abort(hjpeg->hdmaout) != HAL_OK) - { - if (hjpeg->hdmaout->ErrorCode == HAL_DMA_ERROR_TIMEOUT) - { - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - } - } - if (HAL_DMA_Abort(hjpeg->hdmain) != HAL_OK) - { - if (hjpeg->hdmain->ErrorCode == HAL_DMA_ERROR_TIMEOUT) - { - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - } - } - - } - - /* Stop the JPEG encoding/decoding process*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if the JPEG Codec is effectively disabled */ - while (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_COF) != 0UL) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > JPEG_TIMEOUT_VALUE) - { - /* Update error code */ - hjpeg->ErrorCode |= HAL_JPEG_ERROR_TIMEOUT; - - /* Change the DMA state */ - hjpeg->State = HAL_JPEG_STATE_ERROR; - break; - } - } - - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); - - /* Disable All DMA requests */ - JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK); - - /* Flush input and output FIFOs*/ - hjpeg->Instance->CR |= JPEG_CR_IFF; - hjpeg->Instance->CR |= JPEG_CR_OFF; - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); - - /* Reset JpegInCount and JpegOutCount */ - hjpeg->JpegInCount = 0; - hjpeg->JpegOutCount = 0; - - /*Reset the Context Pause*/ - hjpeg->Context &= ~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT); - - /* Change the DMA state*/ - if (hjpeg->ErrorCode != HAL_JPEG_ERROR_NONE) - { - hjpeg->State = HAL_JPEG_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - /* Return function status */ - return HAL_ERROR; - } - else - { - hjpeg->State = HAL_JPEG_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - /* Return function status */ - return HAL_OK; - } - -} - - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions_Group4 JPEG Decode/Encode callback functions - * @brief JPEG process callback functions. - * -@verbatim - ============================================================================== - ##### JPEG Decode and Encode callback functions ##### - ============================================================================== - [..] This section provides callback functions: - (+) HAL_JPEG_InfoReadyCallback() : Decoding JPEG Info ready callback - (+) HAL_JPEG_EncodeCpltCallback() : Encoding complete callback. - (+) HAL_JPEG_DecodeCpltCallback() : Decoding complete callback. - (+) HAL_JPEG_ErrorCallback() : JPEG error callback. - (+) HAL_JPEG_GetDataCallback() : Get New Data chunk callback. - (+) HAL_JPEG_DataReadyCallback() : Decoded/Encoded Data ready callback. - -@endverbatim - * @{ - */ - -/** - * @brief Decoding JPEG Info ready callback. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains - * The JPEG decoded header information - * @retval None - */ -__weak void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - UNUSED(pInfo); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_HeaderParsingCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Encoding complete callback. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_EncodeCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Decoding complete callback. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_EncodeCpltCallback could be implemented in the user file - */ -} - -/** - * @brief JPEG error callback. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -__weak void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Get New Data chunk callback. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param NbDecodedData Number of consummed data in the previous chunk in bytes - * @retval None - */ -__weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - UNUSED(NbDecodedData); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_GetDataCallback could be implemented in the user file - */ -} - -/** - * @brief Decoded/Encoded Data ready callback. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param pDataOut pointer to the output data buffer - * @param OutDataLength number in bytes of data available in the specified output buffer - * @retval None - */ -__weak void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hjpeg); - UNUSED(pDataOut); - UNUSED(OutDataLength); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_JPEG_DataReadyCallback could be implemented in the user file - */ -} - -/** - * @} - */ - - -/** @defgroup JPEG_Exported_Functions_Group5 JPEG IRQ handler management - * @brief JPEG IRQ handler. - * -@verbatim - ============================================================================== - ##### JPEG IRQ handler management ##### - ============================================================================== - [..] This section provides JPEG IRQ handler function. - (+) HAL_JPEG_IRQHandler() : handles JPEG interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief This function handles JPEG interrupt request. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg) -{ - switch (hjpeg->State) - { - case HAL_JPEG_STATE_BUSY_ENCODING: - case HAL_JPEG_STATE_BUSY_DECODING: - /* continue JPEG data encoding/Decoding*/ - /* JPEG data processing : In/Out FIFO transfer*/ - if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - (void) JPEG_Process(hjpeg); - } - else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - JPEG_DMA_ContinueProcess(hjpeg); - } - else - { - /* Nothing to do */ - } - break; - - default: - break; - } -} - -/** - * @} - */ - -/** @defgroup JPEG_Exported_Functions_Group6 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] This section provides JPEG State and Errors function. - (+) HAL_JPEG_GetState() : permits to get in run-time the JPEG state. - (+) HAL_JPEG_GetError() : Returns the JPEG error code if any. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the JPEG state. - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG state - */ -HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg) -{ - return hjpeg->State; -} - -/** - * @brief Return the JPEG error code - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for the specified JPEG. - * @retval JPEG Error Code - */ -uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg) -{ - return hjpeg->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - - -/** @addtogroup JPEG_Private_Functions - * @{ - */ - -/** - * @brief Generates Huffman sizes/Codes Table from Bits/vals Table - * @param Bits pointer to bits table - * @param Huffsize pointer to sizes table - * @param Huffcode pointer to codes table - * @param LastK pointer to last Coeff (table dimension) - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) -{ - uint32_t i; - uint32_t p; - uint32_t l; - uint32_t code; - uint32_t si; - - /* Figure C.1: Generation of table of Huffman code sizes */ - p = 0; - for (l = 0; l < 16UL; l++) - { - i = (uint32_t)Bits[l]; - if ((p + i) > 256UL) - { - /* check for table overflow */ - return HAL_ERROR; - } - while (i != 0UL) - { - Huffsize[p] = (uint8_t) l + 1U; - p++; - i--; - } - } - Huffsize[p] = 0; - *LastK = p; - - /* Figure C.2: Generation of table of Huffman codes */ - code = 0; - si = Huffsize[0]; - p = 0; - while (Huffsize[p] != 0U) - { - while (((uint32_t) Huffsize[p]) == si) - { - Huffcode[p] = code; - p++; - code++; - } - /* code must fit in "size" bits (si), no code is allowed to be all ones*/ - if(si > 31UL) - { - return HAL_ERROR; - } - if (((uint32_t) code) >= (((uint32_t) 1) << si)) - { - return HAL_ERROR; - } - code <<= 1; - si++; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table - * that can programmed to the JPEG encoder registers - * @param AC_BitsValsTable pointer to AC huffman bits/vals table - * @param AC_SizeCodesTable pointer to AC huffman Sizes/Codes table - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, - JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable) -{ - HAL_StatusTypeDef error; - uint8_t huffsize[257]; - uint32_t huffcode[257]; - uint32_t k; - uint32_t l, lsb, msb; - uint32_t lastK; - - error = JPEG_Bits_To_SizeCodes(AC_BitsValsTable->Bits, huffsize, huffcode, &lastK); - if (error != HAL_OK) - { - return error; - } - - /* Figure C.3: Ordering procedure for encoding procedure code tables */ - k = 0; - - while (k < lastK) - { - l = AC_BitsValsTable->HuffVal[k]; - if (l == 0UL) - { - l = 160; /*l = 0x00 EOB code*/ - } - else if (l == 0xF0UL) /* l = 0xF0 ZRL code*/ - { - l = 161; - } - else - { - msb = (l & 0xF0UL) >> 4; - lsb = (l & 0x0FUL); - l = (msb * 10UL) + lsb - 1UL; - } - if (l >= JPEG_AC_HUFF_TABLE_SIZE) - { - return HAL_ERROR; /* Huffman Table overflow error*/ - } - else - { - AC_SizeCodesTable->HuffmanCode[l] = huffcode[k]; - AC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1U; - k++; - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table - * that can programmed to the JPEG encoder registers - * @param DC_BitsValsTable pointer to DC huffman bits/vals table - * @param DC_SizeCodesTable pointer to DC huffman Sizes/Codes table - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, - JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable) -{ - HAL_StatusTypeDef error; - - uint32_t k; - uint32_t l; - uint32_t lastK; - uint8_t huffsize[257]; - uint32_t huffcode[257]; - error = JPEG_Bits_To_SizeCodes(DC_BitsValsTable->Bits, huffsize, huffcode, &lastK); - if (error != HAL_OK) - { - return error; - } - /* Figure C.3: ordering procedure for encoding procedure code tables */ - k = 0; - - while (k < lastK) - { - l = DC_BitsValsTable->HuffVal[k]; - if (l >= JPEG_DC_HUFF_TABLE_SIZE) - { - return HAL_ERROR; /* Huffman Table overflow error*/ - } - else - { - DC_SizeCodesTable->HuffmanCode[l] = huffcode[k]; - DC_SizeCodesTable->CodeLength[l] = huffsize[k] - 1U; - k++; - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the JPEG register with an DC huffman table at the given DC table address - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param HuffTableDC pointer to DC huffman table - * @param DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, - const __IO uint32_t *DCTableAddress) -{ - HAL_StatusTypeDef error; - JPEG_DC_HuffCodeTableTypeDef dcSizeCodesTable; - uint32_t i; - uint32_t lsb; - uint32_t msb; - __IO uint32_t *address, *addressDef; - - if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC0)) - { - address = (hjpeg->Instance->HUFFENC_DC0 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL)); - } - else if (DCTableAddress == (hjpeg->Instance->HUFFENC_DC1)) - { - address = (hjpeg->Instance->HUFFENC_DC1 + (JPEG_DC_HUFF_TABLE_SIZE / 2UL)); - } - else - { - return HAL_ERROR; - } - - if (HuffTableDC != NULL) - { - error = JPEG_DCHuff_BitsVals_To_SizeCodes(HuffTableDC, &dcSizeCodesTable); - if (error != HAL_OK) - { - return error; - } - addressDef = address; - *addressDef = 0x0FFF0FFF; - addressDef++; - *addressDef = 0x0FFF0FFF; - - i = JPEG_DC_HUFF_TABLE_SIZE; - while (i > 1UL) - { - i--; - address --; - msb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & - 0xFFUL); - i--; - lsb = ((uint32_t)(((uint32_t)dcSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)dcSizeCodesTable.HuffmanCode[i] & - 0xFFUL); - - *address = lsb | (msb << 16); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Set the JPEG register with an AC huffman table at the given AC table address - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param HuffTableAC pointer to AC huffman table - * @param ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. - * @retval HAL status - */ -static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, - const __IO uint32_t *ACTableAddress) -{ - HAL_StatusTypeDef error; - JPEG_AC_HuffCodeTableTypeDef acSizeCodesTable; - uint32_t i, lsb, msb; - __IO uint32_t *address, *addressDef; - - if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC0)) - { - address = (hjpeg->Instance->HUFFENC_AC0 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL)); - } - else if (ACTableAddress == (hjpeg->Instance->HUFFENC_AC1)) - { - address = (hjpeg->Instance->HUFFENC_AC1 + (JPEG_AC_HUFF_TABLE_SIZE / 2UL)); - } - else - { - return HAL_ERROR; - } - - if (HuffTableAC != NULL) - { - error = JPEG_ACHuff_BitsVals_To_SizeCodes(HuffTableAC, &acSizeCodesTable); - if (error != HAL_OK) - { - return error; - } - /* Default values settings: 162:167 FFFh , 168:175 FD0h_FD7h */ - /* Locations 162:175 of each AC table contain information used internally by the core */ - - addressDef = address; - for (i = 0; i < 3UL; i++) - { - *addressDef = 0x0FFF0FFF; - addressDef++; - } - *addressDef = 0x0FD10FD0; - addressDef++; - *addressDef = 0x0FD30FD2; - addressDef++; - *addressDef = 0x0FD50FD4; - addressDef++; - *addressDef = 0x0FD70FD6; - /* end of Locations 162:175 */ - - - i = JPEG_AC_HUFF_TABLE_SIZE; - while (i > 1UL) - { - i--; - address--; - msb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & - 0xFFUL); - i--; - lsb = ((uint32_t)(((uint32_t)acSizeCodesTable.CodeLength[i] & 0xFU) << 8)) | ((uint32_t)acSizeCodesTable.HuffmanCode[i] & - 0xFFUL); - - *address = lsb | (msb << 16); - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the JPEG encoder register huffman tables to used during - * the encdoing operation - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg) -{ - HAL_StatusTypeDef error; - - JPEG_Set_Huff_DHTMem(hjpeg); - error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable, - (hjpeg->Instance->HUFFENC_AC0)); - if (error != HAL_OK) - { - return error; - } - - error = JPEG_Set_HuffAC_Mem(hjpeg, (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable, - (hjpeg->Instance->HUFFENC_AC1)); - if (error != HAL_OK) - { - return error; - } - - error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable, - hjpeg->Instance->HUFFENC_DC0); - if (error != HAL_OK) - { - return error; - } - - error = JPEG_Set_HuffDC_Mem(hjpeg, (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable, - hjpeg->Instance->HUFFENC_DC1); - if (error != HAL_OK) - { - return error; - } - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configure the JPEG register huffman tables to be included in the JPEG - * file header (used for encoding only) - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg) -{ - JPEG_ACHuffTableTypeDef *HuffTableAC0 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACLUM_HuffTable; - JPEG_ACHuffTableTypeDef *HuffTableAC1 = (JPEG_ACHuffTableTypeDef *)(uint32_t)&JPEG_ACCHROM_HuffTable; - JPEG_DCHuffTableTypeDef *HuffTableDC0 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCLUM_HuffTable; - JPEG_DCHuffTableTypeDef *HuffTableDC1 = (JPEG_DCHuffTableTypeDef *)(uint32_t)&JPEG_DCCHROM_HuffTable; - uint32_t value, index; - __IO uint32_t *address; - - /* DC0 Huffman Table : BITS*/ - /* DC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address to DHTMEM + 3*/ - address = (hjpeg->Instance->DHTMEM + 3); - index = 16; - while (index > 3UL) - { - - *address = (((uint32_t)HuffTableDC0->Bits[index - 1UL] & 0xFFUL) << 24) | - (((uint32_t)HuffTableDC0->Bits[index - 2UL] & 0xFFUL) << 16) | - (((uint32_t)HuffTableDC0->Bits[index - 3UL] & 0xFFUL) << 8) | - ((uint32_t)HuffTableDC0->Bits[index - 4UL] & 0xFFUL); - address--; - index -= 4UL; - - } - /* DC0 Huffman Table : Val*/ - /* DC0 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +4 to DHTMEM + 6 */ - address = (hjpeg->Instance->DHTMEM + 6); - index = 12; - while (index > 3UL) - { - *address = (((uint32_t)HuffTableDC0->HuffVal[index - 1UL] & 0xFFUL) << 24) | - (((uint32_t)HuffTableDC0->HuffVal[index - 2UL] & 0xFFUL) << 16) | - (((uint32_t)HuffTableDC0->HuffVal[index - 3UL] & 0xFFUL) << 8) | - ((uint32_t)HuffTableDC0->HuffVal[index - 4UL] & 0xFFUL); - address--; - index -= 4UL; - } - - /* AC0 Huffman Table : BITS*/ - /* AC0 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 7 to DHTMEM + 10*/ - address = (hjpeg->Instance->DHTMEM + 10UL); - index = 16; - while (index > 3UL) - { - - *address = (((uint32_t)HuffTableAC0->Bits[index - 1UL] & 0xFFUL) << 24) | - (((uint32_t)HuffTableAC0->Bits[index - 2UL] & 0xFFUL) << 16) | - (((uint32_t)HuffTableAC0->Bits[index - 3UL] & 0xFFUL) << 8) | - ((uint32_t)HuffTableAC0->Bits[index - 4UL] & 0xFFUL); - address--; - index -= 4UL; - - } - /* AC0 Huffman Table : Val*/ - /* AC0 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 11 to DHTMEM + 51 */ - /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 51) belong to AC0 VALS table */ - address = (hjpeg->Instance->DHTMEM + 51); - value = *address & 0xFFFF0000U; - value = value | (((uint32_t)HuffTableAC0->HuffVal[161] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC0->HuffVal[160] & 0xFFUL); - *address = value; - - /*continue setting 160 AC0 huffman values */ - address--; /* address = hjpeg->Instance->DHTMEM + 50*/ - index = 160; - while (index > 3UL) - { - *address = (((uint32_t)HuffTableAC0->HuffVal[index - 1UL] & 0xFFUL) << 24) | - (((uint32_t)HuffTableAC0->HuffVal[index - 2UL] & 0xFFUL) << 16) | - (((uint32_t)HuffTableAC0->HuffVal[index - 3UL] & 0xFFUL) << 8) | - ((uint32_t)HuffTableAC0->HuffVal[index - 4UL] & 0xFFUL); - address--; - index -= 4UL; - } - - /* DC1 Huffman Table : BITS*/ - /* DC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM + 51 base address to DHTMEM + 55*/ - /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 51) belong to DC1 Bits table */ - address = (hjpeg->Instance->DHTMEM + 51); - value = *address & 0x0000FFFFU; - value = value | (((uint32_t)HuffTableDC1->Bits[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableDC1->Bits[0] & 0xFFUL) << 16); - *address = value; - - /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 55) belong to DC1 Bits table */ - address = (hjpeg->Instance->DHTMEM + 55); - value = *address & 0xFFFF0000U; - value = value | (((uint32_t)HuffTableDC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableDC1->Bits[14] & 0xFFUL); - *address = value; - - /*continue setting 12 DC1 huffman Bits from DHTMEM + 54 down to DHTMEM + 52*/ - address--; - index = 12; - while (index > 3UL) - { - - *address = (((uint32_t)HuffTableDC1->Bits[index + 1UL] & 0xFFUL) << 24) | - (((uint32_t)HuffTableDC1->Bits[index] & 0xFFUL) << 16) | - (((uint32_t)HuffTableDC1->Bits[index - 1UL] & 0xFFUL) << 8) | - ((uint32_t)HuffTableDC1->Bits[index - 2UL] & 0xFFUL); - address--; - index -= 4UL; - - } - /* DC1 Huffman Table : Val*/ - /* DC1 VALS is a 12 Bytes table i.e 3x32bits words from DHTMEM base address +55 to DHTMEM + 58 */ - /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 55) belong to DC1 Val table */ - address = (hjpeg->Instance->DHTMEM + 55); - value = *address & 0x0000FFFFUL; - value = value | (((uint32_t)HuffTableDC1->HuffVal[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableDC1->HuffVal[0] & 0xFFUL) << - 16); - *address = value; - - /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 58) belong to DC1 Val table */ - address = (hjpeg->Instance->DHTMEM + 58); - value = *address & 0xFFFF0000UL; - value = value | (((uint32_t)HuffTableDC1->HuffVal[11] & 0xFFUL) << 8) | ((uint32_t)HuffTableDC1->HuffVal[10] & 0xFFUL); - *address = value; - - /*continue setting 8 DC1 huffman val from DHTMEM + 57 down to DHTMEM + 56*/ - address--; - index = 8; - while (index > 3UL) - { - *address = (((uint32_t)HuffTableDC1->HuffVal[index + 1UL] & 0xFFUL) << 24) | - (((uint32_t)HuffTableDC1->HuffVal[index] & 0xFFUL) << 16) | - (((uint32_t)HuffTableDC1->HuffVal[index - 1UL] & 0xFFUL) << 8) | - ((uint32_t)HuffTableDC1->HuffVal[index - 2UL] & 0xFFUL); - address--; - index -= 4UL; - } - - /* AC1 Huffman Table : BITS*/ - /* AC1 BITS is a 16 Bytes table i.e 4x32bits words from DHTMEM base address + 58 to DHTMEM + 62*/ - /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 58) belong to AC1 Bits table */ - address = (hjpeg->Instance->DHTMEM + 58); - value = *address & 0x0000FFFFU; - value = value | (((uint32_t)HuffTableAC1->Bits[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableAC1->Bits[0] & 0xFFUL) << 16); - *address = value; - - /* only Byte 0 and Byte 1 of the last word (@ DHTMEM + 62) belong to Bits Val table */ - address = (hjpeg->Instance->DHTMEM + 62); - value = *address & 0xFFFF0000U; - value = value | (((uint32_t)HuffTableAC1->Bits[15] & 0xFFUL) << 8) | ((uint32_t)HuffTableAC1->Bits[14] & 0xFFUL); - *address = value; - - /*continue setting 12 AC1 huffman Bits from DHTMEM + 61 down to DHTMEM + 59*/ - address--; - index = 12; - while (index > 3UL) - { - - *address = (((uint32_t)HuffTableAC1->Bits[index + 1UL] & 0xFFUL) << 24) | - (((uint32_t)HuffTableAC1->Bits[index] & 0xFFUL) << 16) | - (((uint32_t)HuffTableAC1->Bits[index - 1UL] & 0xFFUL) << 8) | - ((uint32_t)HuffTableAC1->Bits[index - 2UL] & 0xFFUL); - address--; - index -= 4UL; - - } - /* AC1 Huffman Table : Val*/ - /* AC1 VALS is a 162 Bytes table i.e 41x32bits words from DHTMEM base address + 62 to DHTMEM + 102 */ - /* only Byte 2 and Byte 3 of the first word (@ DHTMEM + 62) belong to AC1 VALS table */ - address = (hjpeg->Instance->DHTMEM + 62); - value = *address & 0x0000FFFFUL; - value = value | (((uint32_t)HuffTableAC1->HuffVal[1] & 0xFFUL) << 24) | (((uint32_t)HuffTableAC1->HuffVal[0] & 0xFFUL) << - 16); - *address = value; - - /*continue setting 160 AC1 huffman values from DHTMEM + 63 to DHTMEM+102 */ - address = (hjpeg->Instance->DHTMEM + 102); - index = 160; - while (index > 3UL) - { - *address = (((uint32_t)HuffTableAC1->HuffVal[index + 1UL] & 0xFFUL) << 24) | - (((uint32_t)HuffTableAC1->HuffVal[index] & 0xFFUL) << 16) | - (((uint32_t)HuffTableAC1->HuffVal[index - 1UL] & 0xFFUL) << 8) | - ((uint32_t)HuffTableAC1->HuffVal[index - 2UL] & 0xFFUL); - address--; - index -= 4UL; - } - -} - -/** - * @brief Configure the JPEG registers with a given quantization table - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param QTable pointer to an array of 64 bytes giving the quantization table - * @param QTableAddress destination quantization address in the JPEG peripheral - * it could be QMEM0, QMEM1, QMEM2 or QMEM3 - * @retval 0 if no error, 1 if error - */ -static uint32_t JPEG_Set_Quantization_Mem(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable, - __IO uint32_t *QTableAddress) -{ - uint32_t i; - uint32_t j; - uint32_t quantRow; - uint32_t quantVal; - uint32_t ScaleFactor; - __IO uint32_t *tableAddress; - - tableAddress = QTableAddress; - - if ((hjpeg->Conf.ImageQuality >= 50UL) && (hjpeg->Conf.ImageQuality <= 100UL)) - { - ScaleFactor = 200UL - (hjpeg->Conf.ImageQuality * 2UL); - } - else if (hjpeg->Conf.ImageQuality > 0UL) - { - ScaleFactor = ((uint32_t) 5000) / ((uint32_t) hjpeg->Conf.ImageQuality); - } - else - { - return 1UL; - } - - /*Quantization_table = (Standard_quanization_table * ScaleFactor + 50) / 100*/ - i = 0; - while (i < (JPEG_QUANT_TABLE_SIZE - 3UL)) - { - quantRow = 0; - for (j = 0; j < 4UL; j++) - { - /* Note that the quantization coefficients must be specified in the table in zigzag order */ - quantVal = ((((uint32_t) QTable[JPEG_ZIGZAG_ORDER[i + j]]) * ScaleFactor) + 50UL) / 100UL; - - if (quantVal == 0UL) - { - quantVal = 1UL; - } - else if (quantVal > 255UL) - { - quantVal = 255UL; - } - else - { - /* Nothing to do, keep same value of quantVal */ - } - - quantRow |= ((quantVal & 0xFFUL) << (8UL * j)); - } - - i += 4UL; - *tableAddress = quantRow; - tableAddress ++; - } - - /* Return function status */ - return 0UL; -} - -/** - * @brief Configure the JPEG registers for YCbCr color space - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_SetColorYCBCR(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t ySamplingH; - uint32_t ySamplingV; - uint32_t yblockNb; - - /*Set Number of color components to 3*/ - hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_NF; - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_NF_1; - - /* compute MCU block size and Y, Cb ,Cr sampling factors*/ - if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) - { - ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ - ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ - - yblockNb = 0x30; /* 4 blocks of 8x8*/ - } - else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) - { - ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ - ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ - - yblockNb = 0x10; /* 2 blocks of 8x8*/ - } - else /*JPEG_444_SUBSAMPLING and default*/ - { - ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ - ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ - - yblockNb = 0; /* 1 block of 8x8*/ - } - - hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); - hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF_1 | JPEG_CONFR1_NS_1); - - /*Reset CONFR4 register*/ - hjpeg->Instance->CONFR4 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ - hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB)); - - /*Reset CONFR5 register*/ - hjpeg->Instance->CONFR5 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/ - hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0 | JPEG_CONFR5_QT_0 | JPEG_CONFR5_HA | JPEG_CONFR5_HD); - - /*Reset CONFR6 register*/ - hjpeg->Instance->CONFR6 = 0; - /*Set Horizental and Vertical sampling factor and number of blocks for component 2*/ - /* In YCBCR , by default, both chrominance components (component 1 and component 2) use the same Quantization table (table 1) */ - /* In YCBCR , both chrominance components (component 1 and component 2) use the same Huffman tables (table 1) */ - hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0 | JPEG_CONFR6_QT_0 | JPEG_CONFR6_HA | JPEG_CONFR6_HD); - -} - -/** - * @brief Configure the JPEG registers for GrayScale color space - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_SetColorGrayScale(JPEG_HandleTypeDef *hjpeg) -{ - /*Set Number of color components to 1*/ - hjpeg->Instance->CONFR1 &= ~(JPEG_CONFR1_NF | JPEG_CONFR1_NS); - - /*in GrayScale use 1 single Quantization table (Table 0)*/ - /*in GrayScale use only one couple of AC/DC huffman table (table 0)*/ - - /*Reset CONFR4 register*/ - hjpeg->Instance->CONFR4 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ - hjpeg->Instance->CONFR4 |= JPEG_CONFR4_HSF_0 | JPEG_CONFR4_VSF_0 ; -} - -/** - * @brief Configure the JPEG registers for CMYK color space - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_SetColorCMYK(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t ySamplingH; - uint32_t ySamplingV; - uint32_t yblockNb; - - /*Set Number of color components to 4*/ - hjpeg->Instance->CONFR1 |= (JPEG_CONFR1_NF | JPEG_CONFR1_NS); - - /* compute MCU block size and Y, Cb ,Cr sampling factors*/ - if (hjpeg->Conf.ChromaSubsampling == JPEG_420_SUBSAMPLING) - { - ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ - ySamplingV = JPEG_CONFR4_VSF_1; /* Vs = 2*/ - - yblockNb = 0x30; /* 4 blocks of 8x8*/ - } - else if (hjpeg->Conf.ChromaSubsampling == JPEG_422_SUBSAMPLING) - { - ySamplingH = JPEG_CONFR4_HSF_1; /* Hs = 2*/ - ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ - - yblockNb = 0x10; /* 2 blocks of 8x8*/ - } - else /*JPEG_444_SUBSAMPLING and default*/ - { - ySamplingH = JPEG_CONFR4_HSF_0; /* Hs = 1*/ - ySamplingV = JPEG_CONFR4_VSF_0; /* Vs = 1*/ - - yblockNb = 0; /* 1 block of 8x8*/ - } - - /*Reset CONFR4 register*/ - hjpeg->Instance->CONFR4 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 0*/ - hjpeg->Instance->CONFR4 |= (ySamplingH | ySamplingV | (yblockNb & JPEG_CONFR4_NB)); - - /*Reset CONFR5 register*/ - hjpeg->Instance->CONFR5 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 1*/ - hjpeg->Instance->CONFR5 |= (JPEG_CONFR5_HSF_0 | JPEG_CONFR5_VSF_0); - - /*Reset CONFR6 register*/ - hjpeg->Instance->CONFR6 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 2*/ - hjpeg->Instance->CONFR6 |= (JPEG_CONFR6_HSF_0 | JPEG_CONFR6_VSF_0); - - /*Reset CONFR7 register*/ - hjpeg->Instance->CONFR7 = 0; - /*Set Horizental and Vertical sampling factor , number of blocks , Quantization table and Huffman AC/DC tables for component 3*/ - hjpeg->Instance->CONFR7 |= (JPEG_CONFR7_HSF_0 | JPEG_CONFR7_VSF_0); -} - -/** - * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None - */ -static void JPEG_Init_Process(JPEG_HandleTypeDef *hjpeg) -{ - /*Reset pause*/ - hjpeg->Context &= (~(JPEG_CONTEXT_PAUSE_INPUT | JPEG_CONTEXT_PAUSE_OUTPUT)); - - if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { - /*Set JPEG Codec to Decoding mode */ - hjpeg->Instance->CONFR1 |= JPEG_CONFR1_DE; - } - else /* JPEG_CONTEXT_ENCODE */ - { - /*Set JPEG Codec to Encoding mode */ - hjpeg->Instance->CONFR1 &= ~JPEG_CONFR1_DE; - } - - /*Stop JPEG processing */ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); - - /* Disable All DMA requests */ - JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK); - /* Flush input and output FIFOs*/ - hjpeg->Instance->CR |= JPEG_CR_IFF; - hjpeg->Instance->CR |= JPEG_CR_OFF; - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); - - /*Start Encoding/Decoding*/ - hjpeg->Instance->CONFR0 |= JPEG_CONFR0_START; - - if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - /*Enable IN/OUT, end of Conversation, and end of header parsing interruptions*/ - __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_IFT | JPEG_IT_IFNF | JPEG_IT_OFT | JPEG_IT_OFNE | JPEG_IT_EOC | JPEG_IT_HPD); - } - else if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_DMA) - { - /*Enable End Of Conversation, and End Of Header parsing interruptions*/ - __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); - - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief JPEG encoding/decoding process in case of Polling or Interrupt - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING - */ -static uint32_t JPEG_Process(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t tmpContext; - - /*End of header processing flag */ - if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) - { - /*Call Header parsing complete callback */ - (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); - /* Reset the ImageQuality */ - hjpeg->Conf.ImageQuality = 0; - /* Note : the image quality is only available at the end of the decoding operation */ - /* at the current stage the calculated image quality is not correct so reset it */ - - /*Call Info Ready callback */ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf); -#else - HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD); - - /* Clear header processing done flag */ - __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF); - } - } - - /*Input FIFO status handling*/ - if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) - { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFTF) != 0UL) - { - /*Input FIFO threshold flag */ - /*JPEG_FIFO_TH_SIZE words can be written in */ - JPEG_ReadInputData(hjpeg, JPEG_FIFO_TH_SIZE); - } - else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_IFNFF) != 0UL) - { - /*Input FIFO Not Full flag */ - /*32-bit value can be written in */ - JPEG_ReadInputData(hjpeg, 1); - } - else - { - /* Nothing to do */ - } - } - - - /*Output FIFO flag handling*/ - if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) - { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFTF) != 0UL) - { - /*Output FIFO threshold flag */ - /*JPEG_FIFO_TH_SIZE words can be read out */ - JPEG_StoreOutputData(hjpeg, JPEG_FIFO_TH_SIZE); - } - else if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) - { - /*Output FIFO Not Empty flag */ - /*32-bit value can be read out */ - JPEG_StoreOutputData(hjpeg, 1); - } - else - { - /* Nothing to do */ - } - } - - /*End of Conversion handling :i.e EOC flag is high and OFTF low and OFNEF low*/ - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF | JPEG_FLAG_OFTF | JPEG_FLAG_OFNEF) == JPEG_FLAG_EOCF) - { - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - if ((hjpeg->Context & JPEG_CONTEXT_METHOD_MASK) == JPEG_CONTEXT_IT) - { - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); - } - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); - - /*Call End of conversion callback */ - if (hjpeg->JpegOutCount > 0UL) - { - /*Output Buffer is not empty, call DecodedDataReadyCallback*/ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - hjpeg->JpegOutCount = 0; - } - - /*Reset Context Operation*/ - tmpContext = hjpeg->Context; - /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ - hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /*Call End of Encoding/Decoding callback */ - if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DecodeCpltCallback(hjpeg); -#else - HAL_JPEG_DecodeCpltCallback(hjpeg); -#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ - } - else /* JPEG_CONTEXT_ENCODE */ - { -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->EncodeCpltCallback(hjpeg); -#else - HAL_JPEG_EncodeCpltCallback(hjpeg); -#endif - } - - return JPEG_PROCESS_DONE; - } - - - return JPEG_PROCESS_ONGOING; -} - -/** - * @brief Store some output data from the JPEG peripheral to the output buffer. - * This function is used when the JPEG peripheral has new data to output - * in case of Polling or Interrupt process - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param nbOutputWords Number of output words (of 32 bits) ready from the JPEG peripheral - * @retval None - */ -static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) -{ - uint32_t index; - uint32_t nb_words; - uint32_t nb_bytes; - uint32_t dataword; - - if (hjpeg->OutDataLength >= (hjpeg->JpegOutCount + (nbOutputWords * 4UL))) - { - for (index = 0; index < nbOutputWords; index++) - { - /*Transfer 32 bits from the JPEG output FIFO*/ - dataword = hjpeg->Instance->DOR; - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24); - hjpeg->JpegOutCount += 4UL; - } - if (hjpeg->OutDataLength == hjpeg->JpegOutCount) - { - /*Output Buffer is full, call DecodedDataReadyCallback*/ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ - hjpeg->JpegOutCount = 0; - } - } - else if (hjpeg->OutDataLength > hjpeg->JpegOutCount) - { - nb_words = (hjpeg->OutDataLength - hjpeg->JpegOutCount) / 4UL; - for (index = 0; index < nb_words; index++) - { - /*Transfer 32 bits from the JPEG output FIFO*/ - dataword = hjpeg->Instance->DOR; - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataword & 0x000000FFUL); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataword & 0x0000FF00UL) >> 8); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataword & 0x00FF0000UL) >> 16); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataword & 0xFF000000UL) >> 24); - hjpeg->JpegOutCount += 4UL; - } - if (hjpeg->OutDataLength == hjpeg->JpegOutCount) - { - /*Output Buffer is full, call DecodedDataReadyCallback*/ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - hjpeg->JpegOutCount = 0; - } - else - { - nb_bytes = hjpeg->OutDataLength - hjpeg->JpegOutCount; - dataword = hjpeg->Instance->DOR; - for (index = 0; index < nb_bytes; index++) - { - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * (index & 0x3UL))) & 0xFFUL); - hjpeg->JpegOutCount++; - } - /*Output Buffer is full, call DecodedDataReadyCallback*/ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - hjpeg->JpegOutCount = 0; - - nb_bytes = 4UL - nb_bytes; - for (index = nb_bytes; index < 4UL; index++) - { - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)((dataword >> (8UL * index)) & 0xFFUL); - hjpeg->JpegOutCount++; - } - } - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief Read some input Data from the input buffer. - * This function is used when the JPEG peripheral needs new data - * in case of Polling or Interrupt process - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @param nbRequestWords Number of input words (of 32 bits) that the JPE peripheral request - * @retval None - */ -static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) -{ - uint32_t nb_bytes = 0; - uint32_t nb_words; - uint32_t index; - uint32_t dataword; - uint32_t input_count; - - if ((hjpeg->InDataLength == 0UL) || (nbRequestWords == 0UL)) - { - /* No more Input data : nothing to do*/ - (void) HAL_JPEG_Pause(hjpeg, JPEG_PAUSE_RESUME_INPUT); - } - else if (hjpeg->InDataLength > hjpeg->JpegInCount) - { - nb_bytes = hjpeg->InDataLength - hjpeg->JpegInCount; - } - else if (hjpeg->InDataLength == hjpeg->JpegInCount) - { - /*Call HAL_JPEG_GetDataCallback to get new data */ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount); -#else - HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); -#endif /*USE_HAL_JPEG_REGISTER_CALLBACKS*/ - - if (hjpeg->InDataLength > 4UL) - { - hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); - } - hjpeg->JpegInCount = 0; - nb_bytes = hjpeg->InDataLength; - } - else - { - /* Nothing to do */ - } - if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (nb_bytes > 0UL)) - { - nb_words = nb_bytes / 4UL; - if (nb_words >= nbRequestWords) - { - for (index = 0; index < nbRequestWords; index++) - { - input_count = hjpeg->JpegInCount; - hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); - - hjpeg->JpegInCount += 4UL; - } - } - else /*nb_words < nbRequestWords*/ - { - if (nb_words > 0UL) - { - for (index = 0; index < nb_words; index++) - { - input_count = hjpeg->JpegInCount; - hjpeg->Instance->DIR = (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count])) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 1UL])) << 8) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 2UL])) << 16) | \ - (((uint32_t)(hjpeg->pJpegInBuffPtr[input_count + 3UL])) << 24)); - - hjpeg->JpegInCount += 4UL; - } - } - else - { - /* end of file*/ - dataword = 0; - for (index = 0; index < nb_bytes; index++) - { - dataword |= (uint32_t)hjpeg->pJpegInBuffPtr[hjpeg->JpegInCount] << (8UL * (index & 0x03UL)); - hjpeg->JpegInCount++; - } - hjpeg->Instance->DIR = dataword; - } - } - } -} - -/** - * @brief Start the JPEG DMA process (encoding/decoding) - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING - */ -static HAL_StatusTypeDef JPEG_DMA_StartProcess(JPEG_HandleTypeDef *hjpeg) -{ - if ((hjpeg->InDataLength < 4UL) || (hjpeg->OutDataLength < 4UL)) - { - return HAL_ERROR; - } - /* Reset Ending DMA internal context flag*/ - hjpeg->Context &= ~JPEG_CONTEXT_ENDING_DMA; - - /* Disable DMA In/Out Request*/ - JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA); - - /* Set the JPEG DMA In transfer complete callback */ - hjpeg->hdmain->XferCpltCallback = JPEG_DMAInCpltCallback; - /* Set the DMA In error callback */ - hjpeg->hdmain->XferErrorCallback = JPEG_DMAErrorCallback; - - /* Set the JPEG DMA Out transfer complete callback */ - hjpeg->hdmaout->XferCpltCallback = JPEG_DMAOutCpltCallback; - /* Set the DMA Out error callback */ - hjpeg->hdmaout->XferErrorCallback = JPEG_DMAErrorCallback; - /* Set the DMA Out Abort callback */ - hjpeg->hdmaout->XferAbortCallback = JPEG_DMAOutAbortCallback; - - /*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/ - hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); - - /*DMA transfer size must be a multiple of 4 bytes i.e multiple of 32bits words*/ - hjpeg->OutDataLength = hjpeg->OutDataLength - (hjpeg->OutDataLength % 4UL); - - /* Start DMA FIFO In transfer */ - if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, - hjpeg->InDataLength >> 2) != HAL_OK) - { - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - return HAL_ERROR; - } - - /* Start DMA FIFO Out transfer */ - if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, - hjpeg->OutDataLength >> 2) != HAL_OK) - { - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - return HAL_ERROR; - } - - /* Enable JPEG In/Out DMA requests*/ - JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_IDMA | JPEG_DMA_ODMA); - - return HAL_OK; -} - -/** - * @brief Continue the current JPEG DMA process (encoding/decoding) - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING - */ -static void JPEG_DMA_ContinueProcess(JPEG_HandleTypeDef *hjpeg) -{ - /*End of header processing flag rises*/ - if ((hjpeg->Context & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_HPDF) != 0UL) - { - /*Call Header parsing complete callback */ - (void) HAL_JPEG_GetInfo(hjpeg, &hjpeg->Conf); - - /* Reset the ImageQuality */ - hjpeg->Conf.ImageQuality = 0; - /* Note : the image quality is only available at the end of the decoding operation */ - /* at the current stage the calculated image quality is not correct so reset it */ - - /*Call Info Ready callback */ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->InfoReadyCallback(hjpeg, &hjpeg->Conf); -#else - HAL_JPEG_InfoReadyCallback(hjpeg, &hjpeg->Conf); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_IT_HPD); - - /* Clear header processing done flag */ - __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_HPDF); - } - } - - /*End of Conversion handling*/ - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) != 0UL) - { - /*Disabkle JPEG In/Out DMA Requests*/ - JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA | JPEG_DMA_IDMA); - - hjpeg->Context |= JPEG_CONTEXT_ENDING_DMA; - - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); - - /* Clear all flags */ - __HAL_JPEG_CLEAR_FLAG(hjpeg, JPEG_FLAG_ALL); - - if (hjpeg->hdmain->State == HAL_DMA_STATE_BUSY) - { - /* Stop the DMA In Xfer*/ - (void) HAL_DMA_Abort_IT(hjpeg->hdmain); - } - - if (hjpeg->hdmaout->State == HAL_DMA_STATE_BUSY) - { - /* Stop the DMA out Xfer*/ - (void) HAL_DMA_Abort_IT(hjpeg->hdmaout); - } - else - { - JPEG_DMA_EndProcess(hjpeg); - } - } - - -} - -/** - * @brief Finalize the current JPEG DMA process (encoding/decoding) - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG_PROCESS_DONE - */ -static void JPEG_DMA_EndProcess(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t tmpContext; - hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hjpeg->hdmaout->Instance->NDTR & DMA_SxNDT) << 2); - - /*if Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ - if (hjpeg->JpegOutCount == hjpeg->OutDataLength) - { -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - hjpeg->JpegOutCount = 0; - } - - /*Check if remaining data in the output FIFO*/ - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) - { - if (hjpeg->JpegOutCount > 0UL) - { - /*Output Buffer is not empty, call DecodedDataReadyCallback*/ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - hjpeg->JpegOutCount = 0; - } - - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - tmpContext = hjpeg->Context; - /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ - hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /*Call End of Encoding/Decoding callback */ - if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DecodeCpltCallback(hjpeg); -#else - HAL_JPEG_DecodeCpltCallback(hjpeg); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - } - else /* JPEG_CONTEXT_ENCODE */ - { -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->EncodeCpltCallback(hjpeg); -#else - HAL_JPEG_EncodeCpltCallback(hjpeg); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - } - } - else if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) - { - JPEG_DMA_PollResidualData(hjpeg); - } - else - { - /* Nothing to do */ - } - -} - -/** - * @brief Poll residual output data when DMA process (encoding/decoding) - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval None. - */ -static void JPEG_DMA_PollResidualData(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t tmpContext; - uint32_t count; - uint32_t dataOut; - - for (count = JPEG_FIFO_SIZE; count > 0UL; count--) - { - if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) - { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) != 0UL) - { - dataOut = hjpeg->Instance->DOR; - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount] = (uint8_t)(dataOut & 0x000000FFUL); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 1UL] = (uint8_t)((dataOut & 0x0000FF00UL) >> 8); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 2UL] = (uint8_t)((dataOut & 0x00FF0000UL) >> 16); - hjpeg->pJpegOutBuffPtr[hjpeg->JpegOutCount + 3UL] = (uint8_t)((dataOut & 0xFF000000UL) >> 24); - hjpeg->JpegOutCount += 4UL; - - if (hjpeg->JpegOutCount == hjpeg->OutDataLength) - { - /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - hjpeg->JpegOutCount = 0; - } - - } - } - } - - tmpContext = hjpeg->Context; - - if ((__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_OFNEF) == 0UL) || ((tmpContext & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL)) - { - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - if (hjpeg->JpegOutCount > 0UL) - { - /*Output Buffer is not empty, call DecodedDataReadyCallback*/ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - hjpeg->JpegOutCount = 0; - } - - tmpContext = hjpeg->Context; - /*Clear all context fields execpt JPEG_CONTEXT_CONF_ENCODING and JPEG_CONTEXT_CUSTOM_TABLES*/ - hjpeg->Context &= (JPEG_CONTEXT_CONF_ENCODING | JPEG_CONTEXT_CUSTOM_TABLES); - - /* Process Unlocked */ - __HAL_UNLOCK(hjpeg); - - /* Change the JPEG state */ - hjpeg->State = HAL_JPEG_STATE_READY; - - /*Call End of Encoding/Decoding callback */ - if ((tmpContext & JPEG_CONTEXT_OPERATION_MASK) == JPEG_CONTEXT_DECODE) - { -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DecodeCpltCallback(hjpeg); -#else - HAL_JPEG_DecodeCpltCallback(hjpeg); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - } - else /* JPEG_CONTEXT_ENCODE */ - { -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->EncodeCpltCallback(hjpeg); -#else - HAL_JPEG_EncodeCpltCallback(hjpeg); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - } - } -} - -/** - * @brief DMA input transfer complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure. - * @retval None - */ -static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma) -{ - JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable The JPEG IT so the DMA Input Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); - - if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) == - JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */ - { - JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_IDMA); - - hjpeg->JpegInCount = hjpeg->InDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2); - - /*Call HAL_JPEG_GetDataCallback to get new data */ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->GetDataCallback(hjpeg, hjpeg->JpegInCount); -#else - HAL_JPEG_GetDataCallback(hjpeg, hjpeg->JpegInCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - if (hjpeg->InDataLength >= 4UL) - { - /*JPEG Input DMA transfer data number must be multiple of 32 bits word - as the destination is a 32 bits (4 bytes) register */ - hjpeg->InDataLength = hjpeg->InDataLength - (hjpeg->InDataLength % 4UL); - } - else if (hjpeg->InDataLength > 0UL) - { - /*Transfer last data word (i.e last 4 bytes)*/ - hjpeg->InDataLength = 4; - } - - if (((hjpeg->Context & JPEG_CONTEXT_PAUSE_INPUT) == 0UL) && (hjpeg->InDataLength > 0UL)) - { - /* Start DMA FIFO In transfer */ - if (HAL_DMA_Start_IT(hjpeg->hdmain, (uint32_t)hjpeg->pJpegInBuffPtr, (uint32_t)&hjpeg->Instance->DIR, - hjpeg->InDataLength >> 2) != HAL_OK) - { - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - hjpeg->State = HAL_JPEG_STATE_ERROR; -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->ErrorCallback(hjpeg); -#else - HAL_JPEG_ErrorCallback(hjpeg); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - return; - } - JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_IDMA); - } - - /* JPEG Conversion still on going : Enable the JPEG IT */ - __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); - } -} - -/** - * @brief DMA output transfer complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure. - * @retval None - */ -static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma) -{ - JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable The JPEG IT so the DMA Output Callback can not be interrupted by the JPEG EOC IT or JPEG HPD IT */ - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); - - if ((hjpeg->Context & (JPEG_CONTEXT_METHOD_MASK | JPEG_CONTEXT_ENDING_DMA)) == - JPEG_CONTEXT_DMA) /* Check if context method is DMA and we are not in ending DMA stage */ - { - if (__HAL_JPEG_GET_FLAG(hjpeg, JPEG_FLAG_EOCF) == 0UL) - { - JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_ODMA); - hjpeg->JpegOutCount = hjpeg->OutDataLength - ((hdma->Instance->NDTR & DMA_SxNDT) << 2); - - /*Output Buffer is full, call HAL_JPEG_DataReadyCallback*/ -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#else - HAL_JPEG_DataReadyCallback(hjpeg, hjpeg->pJpegOutBuffPtr, hjpeg->JpegOutCount); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - - if ((hjpeg->Context & JPEG_CONTEXT_PAUSE_OUTPUT) == 0UL) - { - /* Start DMA FIFO Out transfer */ - if (HAL_DMA_Start_IT(hjpeg->hdmaout, (uint32_t)&hjpeg->Instance->DOR, (uint32_t)hjpeg->pJpegOutBuffPtr, - hjpeg->OutDataLength >> 2) != HAL_OK) - { - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; - hjpeg->State = HAL_JPEG_STATE_ERROR; -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->ErrorCallback(hjpeg); -#else - HAL_JPEG_ErrorCallback(hjpeg); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - return; - } - JPEG_ENABLE_DMA(hjpeg, JPEG_DMA_ODMA); - } - } - - /* JPEG Conversion still on going : Enable the JPEG IT */ - __HAL_JPEG_ENABLE_IT(hjpeg, JPEG_IT_EOC | JPEG_IT_HPD); - } -} - - -/** - * @brief DMA Transfer error callback - * @param hdma pointer to a DMA_HandleTypeDef structure. - * @retval None - */ -static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma) -{ - JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* if DMA error is FIFO error ignore it */ - if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) - { - /*Stop Encoding/Decoding*/ - hjpeg->Instance->CONFR0 &= ~JPEG_CONFR0_START; - - /* Disable All Interrupts */ - __HAL_JPEG_DISABLE_IT(hjpeg, JPEG_INTERRUPT_MASK); - - /* Disable All DMA requests */ - JPEG_DISABLE_DMA(hjpeg, JPEG_DMA_MASK); - - hjpeg->State = HAL_JPEG_STATE_READY; - hjpeg->ErrorCode |= HAL_JPEG_ERROR_DMA; -#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1) - hjpeg->ErrorCallback(hjpeg); -#else - HAL_JPEG_ErrorCallback(hjpeg); -#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA output Abort callback - * @param hdma pointer to a DMA_HandleTypeDef structure. - * @retval None - */ -static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) -{ - JPEG_HandleTypeDef *hjpeg = (JPEG_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if ((hjpeg->Context & JPEG_CONTEXT_ENDING_DMA) != 0UL) - { - JPEG_DMA_EndProcess(hjpeg); - } -} - - -/** - * @brief Calculate the decoded image quality (from 1 to 100) - * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains - * the configuration information for JPEG module - * @retval JPEG image quality from 1 to 100. - */ -static uint32_t JPEG_GetQuality(JPEG_HandleTypeDef *hjpeg) -{ - uint32_t quality = 0; - uint32_t quantRow, quantVal, scale, i, j; - __IO uint32_t *tableAddress = hjpeg->Instance->QMEM0; - - i = 0; - while (i < (JPEG_QUANT_TABLE_SIZE - 3UL)) - { - quantRow = *tableAddress; - for (j = 0; j < 4UL; j++) - { - quantVal = (quantRow >> (8UL * j)) & 0xFFUL; - if (quantVal == 1UL) - { - /* if Quantization value = 1 then quality is 100%*/ - quality += 100UL; - } - else - { - /* Note that the quantization coefficients must be specified in the table in zigzag order */ - scale = (quantVal * 100UL) / ((uint32_t) hjpeg->QuantTable0[JPEG_ZIGZAG_ORDER[i + j]]); - - if (scale <= 100UL) - { - quality += (200UL - scale) / 2UL; - } - else - { - quality += 5000UL / scale; - } - } - } - - i += 4UL; - tableAddress ++; - } - - return (quality / 64UL); -} -/** - * @} - */ - -/** - * @} - */ -#endif /* JPEG */ -#endif /* HAL_JPEG_MODULE_ENABLED */ - - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c deleted file mode 100644 index c8b7b2ef..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_lptim.c +++ /dev/null @@ -1,2459 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_lptim.c - * @author MCD Application Team - * @brief LPTIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Low Power Timer (LPTIM) peripheral: - * + Initialization and de-initialization functions. - * + Start/Stop operation functions in polling mode. - * + Start/Stop operation functions in interrupt mode. - * + Reading operation functions. - * + Peripheral State functions. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LPTIM HAL driver can be used as follows: - - (#)Initialize the LPTIM low level resources by implementing the - HAL_LPTIM_MspInit(): - (++) Enable the LPTIM interface clock using __HAL_RCC_LPTIMx_CLK_ENABLE(). - (++) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()): - (+++) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). - (+++) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). - (+++) In LPTIM IRQ handler, call HAL_LPTIM_IRQHandler(). - - (#)Initialize the LPTIM HAL using HAL_LPTIM_Init(). This function - configures mainly: - (++) The instance: LPTIM1. - (++) Clock: the counter clock. - (+++) Source : it can be either the ULPTIM input (IN1) or one of - the internal clock; (APB, LSE, LSI or MSI). - (+++) Prescaler: select the clock divider. - (++) UltraLowPowerClock : To be used only if the ULPTIM is selected - as counter clock source. - (+++) Polarity: polarity of the active edge for the counter unit - if the ULPTIM input is selected. - (+++) SampleTime: clock sampling time to configure the clock glitch - filter. - (++) Trigger: How the counter start. - (+++) Source: trigger can be software or one of the hardware triggers. - (+++) ActiveEdge : only for hardware trigger. - (+++) SampleTime : trigger sampling time to configure the trigger - glitch filter. - (++) OutputPolarity : 2 opposite polarities are possible. - (++) UpdateMode: specifies whether the update of the autoreload and - the compare values is done immediately or after the end of current - period. - - (#)Six modes are available: - - (++) PWM Mode: To generate a PWM signal with specified period and pulse, - call HAL_LPTIM_PWM_Start() or HAL_LPTIM_PWM_Start_IT() for interruption - mode. - - (++) One Pulse Mode: To generate pulse with specified width in response - to a stimulus, call HAL_LPTIM_OnePulse_Start() or - HAL_LPTIM_OnePulse_Start_IT() for interruption mode. - - (++) Set once Mode: In this mode, the output changes the level (from - low level to high level if the output polarity is configured high, else - the opposite) when a compare match occurs. To start this mode, call - HAL_LPTIM_SetOnce_Start() or HAL_LPTIM_SetOnce_Start_IT() for - interruption mode. - - (++) Encoder Mode: To use the encoder interface call - HAL_LPTIM_Encoder_Start() or HAL_LPTIM_Encoder_Start_IT() for - interruption mode. Only available for LPTIM1 instance. - - (++) Time out Mode: an active edge on one selected trigger input rests - the counter. The first trigger event will start the timer, any - successive trigger event will reset the counter and the timer will - restart. To start this mode call HAL_LPTIM_TimeOut_Start_IT() or - HAL_LPTIM_TimeOut_Start_IT() for interruption mode. - - (++) Counter Mode: counter can be used to count external events on - the LPTIM Input1 or it can be used to count internal clock cycles. - To start this mode, call HAL_LPTIM_Counter_Start() or - HAL_LPTIM_Counter_Start_IT() for interruption mode. - - - (#) User can stop any process by calling the corresponding API: - HAL_LPTIM_Xxx_Stop() or HAL_LPTIM_Xxx_Stop_IT() if the process is - already started in interruption mode. - - (#) De-initialize the LPTIM peripheral using HAL_LPTIM_DeInit(). - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - [..] - Use Function HAL_LPTIM_RegisterCallback() to register a callback. - HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, - the Callback ID and a pointer to the user callback function. - [..] - Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the - default weak function. - HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - [..] - These functions allow to register/unregister following callbacks: - - (+) MspInitCallback : LPTIM Base Msp Init Callback. - (+) MspDeInitCallback : LPTIM Base Msp DeInit Callback. - (+) CompareMatchCallback : Compare match Callback. - (+) AutoReloadMatchCallback : Auto-reload match Callback. - (+) TriggerCallback : External trigger event detection Callback. - (+) CompareWriteCallback : Compare register write complete Callback. - (+) AutoReloadWriteCallback : Auto-reload register write complete Callback. - (+) DirectionUpCallback : Up-counting direction change Callback. - (+) DirectionDownCallback : Down-counting direction change Callback. - - [..] - By default, after the Init and when the state is HAL_LPTIM_STATE_RESET - all interrupt callbacks are set to the corresponding weak functions: - examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback(). - - [..] - Exception done for MspInit and MspDeInit functions that are reset to the legacy weak - functionalities in the Init/DeInit only when these callbacks are null - (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - [..] - Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. - - [..] - When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup LPTIM LPTIM - * @brief LPTIM HAL module driver. - * @{ - */ - -#ifdef HAL_LPTIM_MODULE_ENABLED - -#if defined (LPTIM1) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup LPTIM_Private_Constants - * @{ - */ -#define TIMEOUT 1000UL /* Timeout is 1s */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag); - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions - * @{ - */ - -/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions. - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the LPTIM according to the specified parameters in the - LPTIM_InitTypeDef and initialize the associated handle. - (+) DeInitialize the LPTIM peripheral. - (+) Initialize the LPTIM MSP. - (+) DeInitialize the LPTIM MSP. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the LPTIM according to the specified parameters in the - * LPTIM_InitTypeDef and initialize the associated handle. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) -{ - uint32_t tmpcfgr; - - /* Check the LPTIM handle allocation */ - if (hlptim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); - assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) - { - assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); - } - assert_param(IS_LPTIM_TRG_SOURCE(hlptim->Init.Trigger.Source)); - if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) - { - assert_param(IS_LPTIM_EXT_TRG_POLARITY(hlptim->Init.Trigger.ActiveEdge)); - assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(hlptim->Init.Trigger.SampleTime)); - } - assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity)); - assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode)); - assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource)); - - if (hlptim->State == HAL_LPTIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hlptim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - LPTIM_ResetCallback(hlptim); - - if (hlptim->MspInitCallback == NULL) - { - hlptim->MspInitCallback = HAL_LPTIM_MspInit; - } - - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - hlptim->MspInitCallback(hlptim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_LPTIM_MspInit(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Get the LPTIMx CFGR value */ - tmpcfgr = hlptim->Instance->CFGR; - - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); - } - if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) - { - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGSEL)); - } - - /* Clear CKSEL, PRESC, TRIGEN, TRGFLT, WAVPOL, PRELOAD & COUNTMODE bits */ - tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKSEL | LPTIM_CFGR_TRIGEN | LPTIM_CFGR_PRELOAD | - LPTIM_CFGR_WAVPOL | LPTIM_CFGR_PRESC | LPTIM_CFGR_COUNTMODE)); - - /* Set initialization parameters */ - tmpcfgr |= (hlptim->Init.Clock.Source | - hlptim->Init.Clock.Prescaler | - hlptim->Init.OutputPolarity | - hlptim->Init.UpdateMode | - hlptim->Init.CounterSource); - - /* Glitch filters for internal triggers and external inputs are configured - * only if an internal clock source is provided to the LPTIM - */ - if (hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC) - { - tmpcfgr |= (hlptim->Init.Trigger.SampleTime | - hlptim->Init.UltraLowPowerClock.SampleTime); - } - - /* Configure LPTIM external clock polarity and digital filter */ - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) - { - tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | - hlptim->Init.UltraLowPowerClock.SampleTime); - } - - /* Configure LPTIM external trigger */ - if (hlptim->Init.Trigger.Source != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Enable External trigger and set the trigger source */ - tmpcfgr |= (hlptim->Init.Trigger.Source | - hlptim->Init.Trigger.ActiveEdge | - hlptim->Init.Trigger.SampleTime); - } - - /* Write to LPTIMx CFGR */ - hlptim->Instance->CFGR = tmpcfgr; - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitialize the LPTIM peripheral. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the LPTIM handle allocation */ - if (hlptim == NULL) - { - return HAL_ERROR; - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the LPTIM Peripheral Clock */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - if (hlptim->MspDeInitCallback == NULL) - { - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; - } - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - hlptim->MspDeInitCallback(hlptim); -#else - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_LPTIM_MspDeInit(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hlptim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initialize the LPTIM MSP. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize LPTIM MSP. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions - * @brief Start-Stop operation functions. - * -@verbatim - ============================================================================== - ##### LPTIM Start Stop operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Start the PWM mode. - (+) Stop the PWM mode. - (+) Start the One pulse mode. - (+) Stop the One pulse mode. - (+) Start the Set once mode. - (+) Stop the Set once mode. - (+) Start the Encoder mode. - (+) Stop the Encoder mode. - (+) Start the Timeout mode. - (+) Stop the Timeout mode. - (+) Start the Counter mode. - (+) Stop the Counter mode. - - -@endverbatim - * @{ - */ - -/** - * @brief Start the LPTIM PWM generation. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @param Pulse Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Reset WAVE bit to set PWM mode */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the LPTIM PWM generation. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the LPTIM PWM generation in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF - * @param Pulse Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Reset WAVE bit to set PWM mode */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the LPTIM PWM generation in interrupt mode. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the LPTIM One pulse generation. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @param Pulse Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Reset WAVE bit to set one pulse mode */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Start timer in single (one shot) mode */ - __HAL_LPTIM_START_SINGLE(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the LPTIM One pulse generation. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the LPTIM One pulse generation in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @param Pulse Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Reset WAVE bit to set one pulse mode */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Start timer in single (one shot) mode */ - __HAL_LPTIM_START_SINGLE(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the LPTIM One pulse generation in interrupt mode. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the LPTIM in Set once mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @param Pulse Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Set WAVE bit to enable the set once mode */ - hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Start timer in single (one shot) mode */ - __HAL_LPTIM_START_SINGLE(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the LPTIM Set once mode. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the LPTIM Set once mode in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @param Pulse Specifies the compare value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Pulse)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Set WAVE bit to enable the set once mode */ - hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Load the pulse value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then enable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Start timer in single (one shot) mode */ - __HAL_LPTIM_START_SINGLE(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the LPTIM Set once mode in interrupt mode. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); - - /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* If external trigger source is used, then disable external trigger interrupt */ - if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) - { - /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the Encoder interface. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) -{ - uint32_t tmpcfgr; - - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); - assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); - assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Get the LPTIMx CFGR value */ - tmpcfgr = hlptim->Instance->CFGR; - - /* Clear CKPOL bits */ - tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); - - /* Set Input polarity */ - tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; - - /* Write to LPTIMx CFGR */ - hlptim->Instance->CFGR = tmpcfgr; - - /* Set ENC bit to enable the encoder interface */ - hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the Encoder interface. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Reset ENC bit to disable the encoder interface */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the Encoder interface in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) -{ - uint32_t tmpcfgr; - - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC); - assert_param(hlptim->Init.Clock.Prescaler == LPTIM_PRESCALER_DIV1); - assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Configure edge sensitivity for encoder mode */ - /* Get the LPTIMx CFGR value */ - tmpcfgr = hlptim->Instance->CFGR; - - /* Clear CKPOL bits */ - tmpcfgr &= (uint32_t)(~LPTIM_CFGR_CKPOL); - - /* Set Input polarity */ - tmpcfgr |= hlptim->Init.UltraLowPowerClock.Polarity; - - /* Write to LPTIMx CFGR */ - hlptim->Instance->CFGR = tmpcfgr; - - /* Set ENC bit to enable the encoder interface */ - hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Enable "switch to down direction" interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); - - /* Enable "switch to up direction" interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the Encoder interface in interrupt mode. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Reset ENC bit to disable the encoder interface */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - - /* Disable "switch to down direction" interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN); - - /* Disable "switch to up direction" interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the Timeout function. - * @note The first trigger event will start the timer, any successive - * trigger event will reset the counter and the timer restarts. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @param Timeout Specifies the TimeOut value to reset the counter. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Timeout)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Set TIMOUT bit to enable the timeout function */ - hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Load the Timeout value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the Timeout function. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Reset TIMOUT bit to enable the timeout function */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the Timeout function in interrupt mode. - * @note The first trigger event will start the timer, any successive - * trigger event will reset the counter and the timer restarts. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @param Timeout Specifies the TimeOut value to reset the counter. - * This parameter must be a value between 0x0000 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - assert_param(IS_LPTIM_PULSE(Timeout)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); - /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* Set TIMOUT bit to enable the timeout function */ - hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Load the Timeout value in the compare register */ - __HAL_LPTIM_COMPARE_SET(hlptim, Timeout); - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the Timeout function in interrupt mode. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); - - /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Reset TIMOUT bit to enable the timeout function */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - - /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the Counter mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) - && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) - { - /* Check if clock is prescaled */ - assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); - /* Set clock prescaler to 0 */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the Counter mode. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Start the Counter mode in interrupt mode. - * @param hlptim LPTIM handle - * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0001 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - assert_param(IS_LPTIM_PERIOD(Period)); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT(); - /* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ - if ((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) - && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) - { - /* Check if clock is prescaled */ - assert_param(IS_LPTIM_CLOCK_PRESCALERDIV1(hlptim->Init.Clock.Prescaler)); - /* Set clock prescaler to 0 */ - hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; - } - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Clear flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Load the period value in the autoreload register */ - __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); - - /* Enable the Peripheral */ - __HAL_LPTIM_ENABLE(hlptim); - - /* Start timer in continuous mode */ - __HAL_LPTIM_START_CONTINUOUS(hlptim); - - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stop the Counter mode in interrupt mode. - * @param hlptim LPTIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); - - /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ - __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); - - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_LPTIM_DISABLE(hlptim); - - if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT) - { - return HAL_TIMEOUT; - } - - /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); - - /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions - * @brief Read operation functions. - * -@verbatim - ============================================================================== - ##### LPTIM Read operation functions ##### - ============================================================================== -[..] This section provides LPTIM Reading functions. - (+) Read the counter value. - (+) Read the period (Auto-reload) value. - (+) Read the pulse (Compare)value. -@endverbatim - * @{ - */ - -/** - * @brief Return the current counter value. - * @param hlptim LPTIM handle - * @retval Counter value. - */ -uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - return (hlptim->Instance->CNT); -} - -/** - * @brief Return the current Autoreload (Period) value. - * @param hlptim LPTIM handle - * @retval Autoreload value. - */ -uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - return (hlptim->Instance->ARR); -} - -/** - * @brief Return the current Compare (Pulse) value. - * @param hlptim LPTIM handle - * @retval Compare value. - */ -uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim) -{ - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - - return (hlptim->Instance->CMP); -} - -/** - * @} - */ - -/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler and callbacks - * @brief LPTIM IRQ handler. - * -@verbatim - ============================================================================== - ##### LPTIM IRQ handler and callbacks ##### - ============================================================================== -[..] This section provides LPTIM IRQ handler and callback functions called within - the IRQ handler: - (+) LPTIM interrupt request handler - (+) Compare match Callback - (+) Auto-reload match Callback - (+) External trigger event detection Callback - (+) Compare register write complete Callback - (+) Auto-reload register write complete Callback - (+) Up-counting direction change Callback - (+) Down-counting direction change Callback - -@endverbatim - * @{ - */ - -/** - * @brief Handle LPTIM interrupt request. - * @param hlptim LPTIM handle - * @retval None - */ -void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) -{ - /* Compare match interrupt */ - if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET) - { - if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) != RESET) - { - /* Clear Compare match flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); - - /* Compare match Callback */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - hlptim->CompareMatchCallback(hlptim); -#else - HAL_LPTIM_CompareMatchCallback(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - } - } - - /* Autoreload match interrupt */ - if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) - { - if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) != RESET) - { - /* Clear Autoreload match flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); - - /* Autoreload match Callback */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - hlptim->AutoReloadMatchCallback(hlptim); -#else - HAL_LPTIM_AutoReloadMatchCallback(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - } - } - - /* Trigger detected interrupt */ - if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) - { - if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) != RESET) - { - /* Clear Trigger detected flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); - - /* Trigger detected callback */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - hlptim->TriggerCallback(hlptim); -#else - HAL_LPTIM_TriggerCallback(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - } - } - - /* Compare write interrupt */ - if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) - { - if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) != RESET) - { - /* Clear Compare write flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - - /* Compare write Callback */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - hlptim->CompareWriteCallback(hlptim); -#else - HAL_LPTIM_CompareWriteCallback(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - } - } - - /* Autoreload write interrupt */ - if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) - { - if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) != RESET) - { - /* Clear Autoreload write flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - - /* Autoreload write Callback */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - hlptim->AutoReloadWriteCallback(hlptim); -#else - HAL_LPTIM_AutoReloadWriteCallback(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - } - } - - /* Direction counter changed from Down to Up interrupt */ - if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) - { - if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) != RESET) - { - /* Clear Direction counter changed from Down to Up flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); - - /* Direction counter changed from Down to Up Callback */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - hlptim->DirectionUpCallback(hlptim); -#else - HAL_LPTIM_DirectionUpCallback(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - } - } - - /* Direction counter changed from Up to Down interrupt */ - if (__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) - { - if (__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) != RESET) - { - /* Clear Direction counter changed from Up to Down flag */ - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); - - /* Direction counter changed from Up to Down Callback */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) - hlptim->DirectionDownCallback(hlptim); -#else - HAL_LPTIM_DirectionDownCallback(hlptim); -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - } - } - __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG(); -} - -/** - * @brief Compare match callback in non-blocking mode. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_CompareMatchCallback could be implemented in the user file - */ -} - -/** - * @brief Autoreload match callback in non-blocking mode. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_AutoReloadMatchCallback could be implemented in the user file - */ -} - -/** - * @brief Trigger detected callback in non-blocking mode. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Compare write callback in non-blocking mode. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_CompareWriteCallback could be implemented in the user file - */ -} - -/** - * @brief Autoreload write callback in non-blocking mode. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_AutoReloadWriteCallback could be implemented in the user file - */ -} - -/** - * @brief Direction counter changed from Down to Up callback in non-blocking mode. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_DirectionUpCallback could be implemented in the user file - */ -} - -/** - * @brief Direction counter changed from Up to Down callback in non-blocking mode. - * @param hlptim LPTIM handle - * @retval None - */ -__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hlptim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LPTIM_DirectionDownCallback could be implemented in the user file - */ -} - -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User LPTIM callback to be used instead of the weak predefined callback - * @param hlptim LPTIM handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID - * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID - * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID - * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID - * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID - * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID - * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID - * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID - * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID - * @param pCallback pointer to the callback function - * @retval status - */ -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, - HAL_LPTIM_CallbackIDTypeDef CallbackID, - pLPTIM_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - if (hlptim->State == HAL_LPTIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = pCallback; - break; - - case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = pCallback; - break; - - case HAL_LPTIM_COMPARE_MATCH_CB_ID : - hlptim->CompareMatchCallback = pCallback; - break; - - case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : - hlptim->AutoReloadMatchCallback = pCallback; - break; - - case HAL_LPTIM_TRIGGER_CB_ID : - hlptim->TriggerCallback = pCallback; - break; - - case HAL_LPTIM_COMPARE_WRITE_CB_ID : - hlptim->CompareWriteCallback = pCallback; - break; - - case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : - hlptim->AutoReloadWriteCallback = pCallback; - break; - - case HAL_LPTIM_DIRECTION_UP_CB_ID : - hlptim->DirectionUpCallback = pCallback; - break; - - case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - hlptim->DirectionDownCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hlptim->State == HAL_LPTIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = pCallback; - break; - - case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a LPTIM callback - * LLPTIM callback is redirected to the weak predefined callback - * @param hlptim LPTIM handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_LPTIM_MSPINIT_CB_ID LPTIM Base Msp Init Callback ID - * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID LPTIM Base Msp DeInit Callback ID - * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare match Callback ID - * @arg @ref HAL_LPTIM_AUTORELOAD_MATCH_CB_ID Auto-reload match Callback ID - * @arg @ref HAL_LPTIM_TRIGGER_CB_ID External trigger event detection Callback ID - * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare register write complete Callback ID - * @arg @ref HAL_LPTIM_AUTORELOAD_WRITE_CB_ID Auto-reload register write complete Callback ID - * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Up-counting direction change Callback ID - * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Down-counting direction change Callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, - HAL_LPTIM_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hlptim->State == HAL_LPTIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_LPTIM_MSPINIT_CB_ID : - /* Legacy weak MspInit Callback */ - hlptim->MspInitCallback = HAL_LPTIM_MspInit; - break; - - case HAL_LPTIM_MSPDEINIT_CB_ID : - /* Legacy weak Msp DeInit Callback */ - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; - break; - - case HAL_LPTIM_COMPARE_MATCH_CB_ID : - /* Legacy weak Compare match Callback */ - hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; - break; - - case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : - /* Legacy weak Auto-reload match Callback */ - hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; - break; - - case HAL_LPTIM_TRIGGER_CB_ID : - /* Legacy weak External trigger event detection Callback */ - hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; - break; - - case HAL_LPTIM_COMPARE_WRITE_CB_ID : - /* Legacy weak Compare register write complete Callback */ - hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; - break; - - case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : - /* Legacy weak Auto-reload register write complete Callback */ - hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; - break; - - case HAL_LPTIM_DIRECTION_UP_CB_ID : - /* Legacy weak Up-counting direction change Callback */ - hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; - break; - - case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - /* Legacy weak Down-counting direction change Callback */ - hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hlptim->State == HAL_LPTIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_LPTIM_MSPINIT_CB_ID : - /* Legacy weak MspInit Callback */ - hlptim->MspInitCallback = HAL_LPTIM_MspInit; - break; - - case HAL_LPTIM_MSPDEINIT_CB_ID : - /* Legacy weak Msp DeInit Callback */ - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup LPTIM_Group5 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Return the LPTIM handle state. - * @param hlptim LPTIM handle - * @retval HAL state - */ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim) -{ - /* Return LPTIM handle state */ - return hlptim->State; -} - -/** - * @} - */ - - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup LPTIM_Private_Functions LPTIM Private Functions - * @{ - */ -#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -/** - * @brief Reset interrupt callbacks to the legacy weak callbacks. - * @param lptim pointer to a LPTIM_HandleTypeDef structure that contains - * the configuration information for LPTIM module. - * @retval None - */ -static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) -{ - /* Reset the LPTIM callback to the legacy weak callbacks */ - lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; - lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; - lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; - lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; - lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; - lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; - lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; -} -#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ - -/** - * @brief LPTimer Wait for flag set - * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains - * the configuration information for LPTIM module. - * @param flag The lptim flag - * @retval HAL status - */ -static HAL_StatusTypeDef LPTIM_WaitForFlag(const LPTIM_HandleTypeDef *hlptim, uint32_t flag) -{ - HAL_StatusTypeDef result = HAL_OK; - uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL); - do - { - count--; - if (count == 0UL) - { - result = HAL_TIMEOUT; - } - } while ((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL)); - - return result; -} - -/** - * @brief Disable LPTIM HW instance. - * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains - * the configuration information for LPTIM module. - * @note The following sequence is required to solve LPTIM disable HW limitation. - * Please check Errata Sheet ES0335 for more details under "MCU may remain - * stuck in LPTIM interrupt when entering Stop mode" section. - * @retval None - */ -void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) -{ - uint32_t tmpclksource = 0; - uint32_t tmpIER; - uint32_t tmpCFGR; - uint32_t tmpCMP; - uint32_t tmpARR; - uint32_t primask_bit; - - /* Enter critical section */ - primask_bit = __get_PRIMASK(); - __set_PRIMASK(1) ; - - /*********** Save LPTIM Config ***********/ - /* Save LPTIM source clock */ - switch ((uint32_t)hlptim->Instance) - { - case LPTIM1_BASE: - tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); - break; - default: - break; - } - - /* Save LPTIM configuration registers */ - tmpIER = hlptim->Instance->IER; - tmpCFGR = hlptim->Instance->CFGR; - tmpCMP = hlptim->Instance->CMP; - tmpARR = hlptim->Instance->ARR; - - /*********** Reset LPTIM ***********/ - switch ((uint32_t)hlptim->Instance) - { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_FORCE_RESET(); - __HAL_RCC_LPTIM1_RELEASE_RESET(); - break; - default: - break; - } - - /*********** Restore LPTIM Config ***********/ - if ((tmpCMP != 0UL) || (tmpARR != 0UL)) - { - /* Force LPTIM source kernel clock from APB */ - switch ((uint32_t)hlptim->Instance) - { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); - break; - default: - break; - } - - if (tmpCMP != 0UL) - { - /* Restore CMP register (LPTIM should be enabled first) */ - hlptim->Instance->CR |= LPTIM_CR_ENABLE; - hlptim->Instance->CMP = tmpCMP; - - /* Wait for the completion of the write operation to the LPTIM_CMP register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT) - { - hlptim->State = HAL_LPTIM_STATE_TIMEOUT; - } - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); - } - - if (tmpARR != 0UL) - { - /* Restore ARR register (LPTIM should be enabled first) */ - hlptim->Instance->CR |= LPTIM_CR_ENABLE; - hlptim->Instance->ARR = tmpARR; - - /* Wait for the completion of the write operation to the LPTIM_ARR register */ - if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT) - { - hlptim->State = HAL_LPTIM_STATE_TIMEOUT; - } - - __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); - } - - /* Restore LPTIM source kernel clock */ - switch ((uint32_t)hlptim->Instance) - { - case LPTIM1_BASE: - __HAL_RCC_LPTIM1_CONFIG(tmpclksource); - break; - default: - break; - } - } - - /* Restore configuration registers (LPTIM should be disabled first) */ - hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE); - hlptim->Instance->IER = tmpIER; - hlptim->Instance->CFGR = tmpCFGR; - - /* Exit critical section: restore previous priority mask */ - __set_PRIMASK(primask_bit); -} -/** - * @} - */ -#endif /* LPTIM1 */ - -#endif /* HAL_LPTIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c deleted file mode 100644 index 7a5c78ab..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc.c +++ /dev/null @@ -1,2221 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_ltdc.c - * @author MCD Application Team - * @brief LTDC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the LTDC peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Errors functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LTDC HAL driver can be used as follows: - - (#) Declare a LTDC_HandleTypeDef handle structure, for example: LTDC_HandleTypeDef hltdc; - - (#) Initialize the LTDC low level resources by implementing the HAL_LTDC_MspInit() API: - (##) Enable the LTDC interface clock - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the LTDC interrupt priority - (+++) Enable the NVIC LTDC IRQ Channel - - (#) Initialize the required configuration through the following parameters: - the LTDC timing, the horizontal and vertical polarity, the pixel clock polarity, - Data Enable polarity and the LTDC background color value using HAL_LTDC_Init() function - - *** Configuration *** - ========================= - [..] - (#) Program the required configuration through the following parameters: - the pixel format, the blending factors, input alpha value, the window size - and the image size using HAL_LTDC_ConfigLayer() function for foreground - or/and background layer. - - (#) Optionally, configure and enable the CLUT using HAL_LTDC_ConfigCLUT() and - HAL_LTDC_EnableCLUT functions. - - (#) Optionally, enable the Dither using HAL_LTDC_EnableDither(). - - (#) Optionally, configure and enable the Color keying using HAL_LTDC_ConfigColorKeying() - and HAL_LTDC_EnableColorKeying functions. - - (#) Optionally, configure LineInterrupt using HAL_LTDC_ProgramLineEvent() - function - - (#) If needed, reconfigure and change the pixel format value, the alpha value - value, the window size, the window position and the layer start address - for foreground or/and background layer using respectively the following - functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(), - HAL_LTDC_SetWindowPosition() and HAL_LTDC_SetAddress(). - - (#) Variant functions with _NoReload suffix allows to set the LTDC configuration/settings without immediate reload. - This is useful in case when the program requires to modify serval LTDC settings (on one or both layers) - then applying(reload) these settings in one shot by calling the function HAL_LTDC_Reload(). - - After calling the _NoReload functions to set different color/format/layer settings, - the program shall call the function HAL_LTDC_Reload() to apply(reload) these settings. - Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_IMMEDIATE if - an immediate reload is required. - Function HAL_LTDC_Reload() can be called with the parameter ReloadType set to LTDC_RELOAD_VERTICAL_BLANKING if - the reload should be done in the next vertical blanking period, - this option allows to avoid display flicker by applying the new settings during the vertical blanking period. - - - (#) To control LTDC state you can use the following function: HAL_LTDC_GetState() - - *** LTDC HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in LTDC HAL driver. - - (+) __HAL_LTDC_ENABLE: Enable the LTDC. - (+) __HAL_LTDC_DISABLE: Disable the LTDC. - (+) __HAL_LTDC_LAYER_ENABLE: Enable an LTDC Layer. - (+) __HAL_LTDC_LAYER_DISABLE: Disable an LTDC Layer. - (+) __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG: Reload Layer Configuration. - (+) __HAL_LTDC_GET_FLAG: Get the LTDC pending flags. - (+) __HAL_LTDC_CLEAR_FLAG: Clear the LTDC pending flags. - (+) __HAL_LTDC_ENABLE_IT: Enable the specified LTDC interrupts. - (+) __HAL_LTDC_DISABLE_IT: Disable the specified LTDC interrupts. - (+) __HAL_LTDC_GET_IT_SOURCE: Check whether the specified LTDC interrupt has occurred or not. - - [..] - (@) You can refer to the LTDC HAL driver header file for more useful macros - - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_LTDC_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use function HAL_LTDC_RegisterCallback() to register a callback. - - [..] - Function HAL_LTDC_RegisterCallback() allows to register following callbacks: - (+) LineEventCallback : LTDC Line Event Callback. - (+) ReloadEventCallback : LTDC Reload Event Callback. - (+) ErrorCallback : LTDC Error Callback - (+) MspInitCallback : LTDC MspInit. - (+) MspDeInitCallback : LTDC MspDeInit. - [..] - This function takes as parameters the HAL peripheral handle, the callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_LTDC_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_LTDC_UnRegisterCallback() takes as parameters the HAL peripheral handle - and the callback ID. - [..] - This function allows to reset following callbacks: - (+) LineEventCallback : LTDC Line Event Callback - (+) ReloadEventCallback : LTDC Reload Event Callback - (+) ErrorCallback : LTDC Error Callback - (+) MspInitCallback : LTDC MspInit - (+) MspDeInitCallback : LTDC MspDeInit. - - [..] - By default, after the HAL_LTDC_Init and when the state is HAL_LTDC_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_LTDC_LineEventCallback(), HAL_LTDC_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak (surcharged) functions in the HAL_LTDC_Init() and HAL_LTDC_DeInit() - only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_LTDC_Init() and HAL_LTDC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_LTDC_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_LTDC_STATE_READY or HAL_LTDC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_LTDC_RegisterCallback() before calling HAL_LTDC_DeInit() - or HAL_LTDC_Init() function. - - [..] - When the compilation define USE_HAL_LTDC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_LTDC_MODULE_ENABLED - -#if defined (LTDC) - -/** @defgroup LTDC LTDC - * @brief LTDC HAL module driver - * @{ - */ - - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup LTDC_Private_Define LTDC Private Define - * @{ - */ -#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup LTDC_Exported_Functions LTDC Exported Functions - * @{ - */ - -/** @defgroup LTDC_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the LTDC - (+) De-initialize the LTDC - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the LTDC according to the specified parameters in the LTDC_InitTypeDef. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) -{ - uint32_t tmp; - uint32_t tmp1; - - /* Check the LTDC peripheral state */ - if (hltdc == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); - assert_param(IS_LTDC_HSYNC(hltdc->Init.HorizontalSync)); - assert_param(IS_LTDC_VSYNC(hltdc->Init.VerticalSync)); - assert_param(IS_LTDC_AHBP(hltdc->Init.AccumulatedHBP)); - assert_param(IS_LTDC_AVBP(hltdc->Init.AccumulatedVBP)); - assert_param(IS_LTDC_AAH(hltdc->Init.AccumulatedActiveH)); - assert_param(IS_LTDC_AAW(hltdc->Init.AccumulatedActiveW)); - assert_param(IS_LTDC_TOTALH(hltdc->Init.TotalHeigh)); - assert_param(IS_LTDC_TOTALW(hltdc->Init.TotalWidth)); - assert_param(IS_LTDC_HSPOL(hltdc->Init.HSPolarity)); - assert_param(IS_LTDC_VSPOL(hltdc->Init.VSPolarity)); - assert_param(IS_LTDC_DEPOL(hltdc->Init.DEPolarity)); - assert_param(IS_LTDC_PCPOL(hltdc->Init.PCPolarity)); - -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) - if (hltdc->State == HAL_LTDC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hltdc->Lock = HAL_UNLOCKED; - - /* Reset the LTDC callback to the legacy weak callbacks */ - hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ - hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ - hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hltdc->MspInitCallback == NULL) - { - hltdc->MspInitCallback = HAL_LTDC_MspInit; - } - /* Init the low level hardware */ - hltdc->MspInitCallback(hltdc); - } -#else - if (hltdc->State == HAL_LTDC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hltdc->Lock = HAL_UNLOCKED; - /* Init the low level hardware */ - HAL_LTDC_MspInit(hltdc); - } -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Configure the HS, VS, DE and PC polarity */ - hltdc->Instance->GCR &= ~(LTDC_GCR_HSPOL | LTDC_GCR_VSPOL | LTDC_GCR_DEPOL | LTDC_GCR_PCPOL); - hltdc->Instance->GCR |= (uint32_t)(hltdc->Init.HSPolarity | hltdc->Init.VSPolarity | \ - hltdc->Init.DEPolarity | hltdc->Init.PCPolarity); - - /* Set Synchronization size */ - hltdc->Instance->SSCR &= ~(LTDC_SSCR_VSH | LTDC_SSCR_HSW); - tmp = (hltdc->Init.HorizontalSync << 16U); - hltdc->Instance->SSCR |= (tmp | hltdc->Init.VerticalSync); - - /* Set Accumulated Back porch */ - hltdc->Instance->BPCR &= ~(LTDC_BPCR_AVBP | LTDC_BPCR_AHBP); - tmp = (hltdc->Init.AccumulatedHBP << 16U); - hltdc->Instance->BPCR |= (tmp | hltdc->Init.AccumulatedVBP); - - /* Set Accumulated Active Width */ - hltdc->Instance->AWCR &= ~(LTDC_AWCR_AAH | LTDC_AWCR_AAW); - tmp = (hltdc->Init.AccumulatedActiveW << 16U); - hltdc->Instance->AWCR |= (tmp | hltdc->Init.AccumulatedActiveH); - - /* Set Total Width */ - hltdc->Instance->TWCR &= ~(LTDC_TWCR_TOTALH | LTDC_TWCR_TOTALW); - tmp = (hltdc->Init.TotalWidth << 16U); - hltdc->Instance->TWCR |= (tmp | hltdc->Init.TotalHeigh); - - /* Set the background color value */ - tmp = ((uint32_t)(hltdc->Init.Backcolor.Green) << 8U); - tmp1 = ((uint32_t)(hltdc->Init.Backcolor.Red) << 16U); - hltdc->Instance->BCCR &= ~(LTDC_BCCR_BCBLUE | LTDC_BCCR_BCGREEN | LTDC_BCCR_BCRED); - hltdc->Instance->BCCR |= (tmp1 | tmp | hltdc->Init.Backcolor.Blue); - - /* Enable the Transfer Error and FIFO underrun interrupts */ - __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_TE | LTDC_IT_FU); - - /* Enable LTDC by setting LTDCEN bit */ - __HAL_LTDC_ENABLE(hltdc); - - /* Initialize the error code */ - hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; - - /* Initialize the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief De-initialize the LTDC peripheral. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ - -HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) -{ - uint32_t tickstart; - - /* Check the LTDC peripheral state */ - if (hltdc == NULL) - { - return HAL_ERROR; - } - - /* Check function parameters */ - assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); - - /* Disable LTDC Layer 1 */ - __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1); - -#if defined(LTDC_Layer2_BASE) - /* Disable LTDC Layer 2 */ - __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2); -#endif /* LTDC_Layer2_BASE */ - - /* Reload during vertical blanking period */ - __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for VSYNC Interrupt */ - while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE) - { - break; - } - } - - /* Disable LTDC */ - __HAL_LTDC_DISABLE(hltdc); - -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) - if (hltdc->MspDeInitCallback == NULL) - { - hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; - } - /* DeInit the low level hardware */ - hltdc->MspDeInitCallback(hltdc); -#else - /* DeInit the low level hardware */ - HAL_LTDC_MspDeInit(hltdc); -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - - /* Initialize the error code */ - hltdc->ErrorCode = HAL_LTDC_ERROR_NONE; - - /* Initialize the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Initialize the LTDC MSP. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LTDC_MspInit could be implemented in the user file - */ -} - -/** - * @brief De-initialize the LTDC MSP. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LTDC_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User LTDC Callback - * To be used instead of the weak predefined callback - * @param hltdc ltdc handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID - * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID - * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, - pLTDC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hltdc); - - if (hltdc->State == HAL_LTDC_STATE_READY) - { - switch (CallbackID) - { - case HAL_LTDC_LINE_EVENT_CB_ID : - hltdc->LineEventCallback = pCallback; - break; - - case HAL_LTDC_RELOAD_EVENT_CB_ID : - hltdc->ReloadEventCallback = pCallback; - break; - - case HAL_LTDC_ERROR_CB_ID : - hltdc->ErrorCallback = pCallback; - break; - - case HAL_LTDC_MSPINIT_CB_ID : - hltdc->MspInitCallback = pCallback; - break; - - case HAL_LTDC_MSPDEINIT_CB_ID : - hltdc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hltdc->State == HAL_LTDC_STATE_RESET) - { - switch (CallbackID) - { - case HAL_LTDC_MSPINIT_CB_ID : - hltdc->MspInitCallback = pCallback; - break; - - case HAL_LTDC_MSPDEINIT_CB_ID : - hltdc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hltdc); - - return status; -} - -/** - * @brief Unregister an LTDC Callback - * LTDC callback is redirected to the weak predefined callback - * @param hltdc ltdc handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_LTDC_LINE_EVENT_CB_ID Line Event Callback ID - * @arg @ref HAL_LTDC_RELOAD_EVENT_CB_ID Reload Event Callback ID - * @arg @ref HAL_LTDC_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_LTDC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_LTDC_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hltdc); - - if (hltdc->State == HAL_LTDC_STATE_READY) - { - switch (CallbackID) - { - case HAL_LTDC_LINE_EVENT_CB_ID : - hltdc->LineEventCallback = HAL_LTDC_LineEventCallback; /* Legacy weak LineEventCallback */ - break; - - case HAL_LTDC_RELOAD_EVENT_CB_ID : - hltdc->ReloadEventCallback = HAL_LTDC_ReloadEventCallback; /* Legacy weak ReloadEventCallback */ - break; - - case HAL_LTDC_ERROR_CB_ID : - hltdc->ErrorCallback = HAL_LTDC_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_LTDC_MSPINIT_CB_ID : - hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ - break; - - case HAL_LTDC_MSPDEINIT_CB_ID : - hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ - break; - - default : - /* Update the error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hltdc->State == HAL_LTDC_STATE_RESET) - { - switch (CallbackID) - { - case HAL_LTDC_MSPINIT_CB_ID : - hltdc->MspInitCallback = HAL_LTDC_MspInit; /* Legcay weak MspInit Callback */ - break; - - case HAL_LTDC_MSPDEINIT_CB_ID : - hltdc->MspDeInitCallback = HAL_LTDC_MspDeInit; /* Legcay weak MspDeInit Callback */ - break; - - default : - /* Update the error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hltdc); - - return status; -} -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup LTDC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides function allowing to: - (+) Handle LTDC interrupt request - -@endverbatim - * @{ - */ -/** - * @brief Handle LTDC interrupt request. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL status - */ -void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc) -{ - uint32_t isrflags = READ_REG(hltdc->Instance->ISR); - uint32_t itsources = READ_REG(hltdc->Instance->IER); - - /* Transfer Error Interrupt management ***************************************/ - if (((isrflags & LTDC_ISR_TERRIF) != 0U) && ((itsources & LTDC_IER_TERRIE) != 0U)) - { - /* Disable the transfer Error interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_TE); - - /* Clear the transfer error flag */ - __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_TE); - - /* Update error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_TE; - - /* Change LTDC state */ - hltdc->State = HAL_LTDC_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - /* Transfer error Callback */ -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hltdc->ErrorCallback(hltdc); -#else - /* Call legacy error callback*/ - HAL_LTDC_ErrorCallback(hltdc); -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - } - - /* FIFO underrun Interrupt management ***************************************/ - if (((isrflags & LTDC_ISR_FUIF) != 0U) && ((itsources & LTDC_IER_FUIE) != 0U)) - { - /* Disable the FIFO underrun interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_FU); - - /* Clear the FIFO underrun flag */ - __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_FU); - - /* Update error code */ - hltdc->ErrorCode |= HAL_LTDC_ERROR_FU; - - /* Change LTDC state */ - hltdc->State = HAL_LTDC_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - /* Transfer error Callback */ -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - hltdc->ErrorCallback(hltdc); -#else - /* Call legacy error callback*/ - HAL_LTDC_ErrorCallback(hltdc); -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - } - - /* Line Interrupt management ************************************************/ - if (((isrflags & LTDC_ISR_LIF) != 0U) && ((itsources & LTDC_IER_LIE) != 0U)) - { - /* Disable the Line interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); - - /* Clear the Line interrupt flag */ - __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_LI); - - /* Change LTDC state */ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - /* Line interrupt Callback */ -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) - /*Call registered Line Event callback */ - hltdc->LineEventCallback(hltdc); -#else - /*Call Legacy Line Event callback */ - HAL_LTDC_LineEventCallback(hltdc); -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - } - - /* Register reload Interrupt management ***************************************/ - if (((isrflags & LTDC_ISR_RRIF) != 0U) && ((itsources & LTDC_IER_RRIE) != 0U)) - { - /* Disable the register reload interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR); - - /* Clear the register reload flag */ - __HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR); - - /* Change LTDC state */ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - /* Reload interrupt Callback */ -#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) - /*Call registered reload Event callback */ - hltdc->ReloadEventCallback(hltdc); -#else - /*Call Legacy Reload Event callback */ - HAL_LTDC_ReloadEventCallback(hltdc); -#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Error LTDC callback. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LTDC_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Line Event callback. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LTDC_LineEventCallback could be implemented in the user file - */ -} - -/** - * @brief Reload Event callback. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval None - */ -__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hltdc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_LTDC_ReloadEvenCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup LTDC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the LTDC foreground or/and background parameters. - (+) Set the active layer. - (+) Configure the color keying. - (+) Configure the C-LUT. - (+) Enable / Disable the color keying. - (+) Enable / Disable the C-LUT. - (+) Update the layer position. - (+) Update the layer size. - (+) Update pixel format on the fly. - (+) Update transparency on the fly. - (+) Update address on the fly. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the LTDC Layer according to the specified - * parameters in the LTDC_InitTypeDef and create the associated handle. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains - * the configuration information for the Layer. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); - assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); - assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); - assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); - assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); - assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); - assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); - assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); - assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); - assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); - assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Copy new layer configuration into handle structure */ - hltdc->LayerCfg[LayerIdx] = *pLayerCfg; - - /* Configure the LTDC Layer */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Initialize the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Configure the color keying. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param RGBValue the color key value - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Configure the default color values */ - LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); - LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Load the color lookup table. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param pCLUT pointer to the color lookup table address. - * @param CLUTSize the color lookup table size. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx) -{ - uint32_t tmp; - uint32_t counter; - uint32_t *pcolorlut = pCLUT; - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - for (counter = 0U; (counter < CLUTSize); counter++) - { - if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) - { - tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ - ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); - } - else - { - tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ - ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); - } - - pcolorlut++; - - /* Specifies the C-LUT address and RGB value */ - LTDC_LAYER(hltdc, LayerIdx)->CLUTWR = tmp; - } - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable the color keying. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable LTDC color keying by setting COLKEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable the color keying. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Disable LTDC color keying by setting COLKEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable the color lookup table. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable LTDC color lookup table by setting CLUTEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable the color lookup table. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Disable LTDC color lookup table by setting CLUTEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable Dither. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable Dither by setting DTEN bit */ - LTDC->GCR |= (uint32_t)LTDC_GCR_DEN; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable Dither. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc) -{ - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Disable Dither by setting DTEN bit */ - LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Set the LTDC window size. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param XSize LTDC Pixel per line - * @param YSize LTDC Line number - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters (Layers parameters)*/ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_CFBLL(XSize)); - assert_param(IS_LTDC_CFBLNBR(YSize)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* update horizontal stop */ - pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; - - /* update vertical stop */ - pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; - - /* Reconfigures the color frame buffer pitch in byte */ - pLayerCfg->ImageWidth = XSize; - - /* Reconfigures the frame buffer line number */ - pLayerCfg->ImageHeight = YSize; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Set the LTDC window position. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param X0 LTDC window X offset - * @param Y0 LTDC window Y offset - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_CFBLL(X0)); - assert_param(IS_LTDC_CFBLNBR(Y0)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* update horizontal start/stop */ - pLayerCfg->WindowX0 = X0; - pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; - - /* update vertical start/stop */ - pLayerCfg->WindowY0 = Y0; - pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the pixel format. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Pixelformat new pixel format value. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters */ - assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the pixel format */ - pLayerCfg->PixelFormat = Pixelformat; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the layer alpha value. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Alpha new alpha value. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters */ - assert_param(IS_LTDC_ALPHA(Alpha)); - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the Alpha value */ - pLayerCfg->Alpha = Alpha; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} -/** - * @brief Reconfigure the frame buffer Address. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Address new address value. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the Address */ - pLayerCfg->FBStartAdress = Address; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Set the Immediate Reload type */ - hltdc->Instance->SRCR = LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width - * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to - * layer for which we want to read and display on screen only a portion 320x240 taken in the center - * of the buffer. - * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous - * call to HAL_LTDC_ConfigLayer(). - * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default - * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. - * @param LayerIdx LTDC layer index concerned by the modification of line pitch. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) -{ - uint32_t tmp; - uint32_t pitchUpdate; - uint32_t pixelFormat; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* get LayerIdx used pixel format */ - pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; - - if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) - { - tmp = 4U; - } - else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) - { - tmp = 3U; - } - else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) - { - tmp = 2U; - } - else - { - tmp = 1U; - } - - pitchUpdate = ((LinePitchInPixels * tmp) << 16U); - - /* Clear previously set standard pitch */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; - - /* Set the Reload type as immediate update of LTDC pitch configured above */ - LTDC->SRCR |= LTDC_SRCR_IMR; - - /* Set new line pitch value */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; - - /* Set the Reload type as immediate update of LTDC pitch configured above */ - LTDC->SRCR |= LTDC_SRCR_IMR; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Define the position of the line interrupt. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Line Line Interrupt Position. - * @note User application may resort to HAL_LTDC_LineEventCallback() at line interrupt generation. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LIPOS(Line)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Disable the Line interrupt */ - __HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_LI); - - /* Set the Line Interrupt position */ - LTDC->LIPCR = (uint32_t)Line; - - /* Enable the Line interrupt */ - __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_LI); - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reload LTDC Layers configuration. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param ReloadType This parameter can be one of the following values : - * LTDC_RELOAD_IMMEDIATE : Immediate Reload - * LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking - * @note User application may resort to HAL_LTDC_ReloadEventCallback() at reload interrupt generation. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType) -{ - /* Check the parameters */ - assert_param(IS_LTDC_RELOAD(ReloadType)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable the Reload interrupt */ - __HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR); - - /* Apply Reload type */ - hltdc->Instance->SRCR = ReloadType; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Configure the LTDC Layer according to the specified without reloading - * parameters in the LTDC_InitTypeDef and create the associated handle. - * Variant of the function HAL_LTDC_ConfigLayer without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains - * the configuration information for the Layer. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, - uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0)); - assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1)); - assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0)); - assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1)); - assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat)); - assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha)); - assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0)); - assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1)); - assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2)); - assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth)); - assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Copy new layer configuration into handle structure */ - hltdc->LayerCfg[LayerIdx] = *pLayerCfg; - - /* Configure the LTDC Layer */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Initialize the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Set the LTDC window size without reloading. - * Variant of the function HAL_LTDC_SetWindowSize without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param XSize LTDC Pixel per line - * @param YSize LTDC Line number - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, - uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters (Layers parameters)*/ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_CFBLL(XSize)); - assert_param(IS_LTDC_CFBLNBR(YSize)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* update horizontal stop */ - pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0; - - /* update vertical stop */ - pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0; - - /* Reconfigures the color frame buffer pitch in byte */ - pLayerCfg->ImageWidth = XSize; - - /* Reconfigures the frame buffer line number */ - pLayerCfg->ImageHeight = YSize; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Set the LTDC window position without reloading. - * Variant of the function HAL_LTDC_SetWindowPosition without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param X0 LTDC window X offset - * @param Y0 LTDC window Y offset - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, - uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - assert_param(IS_LTDC_CFBLL(X0)); - assert_param(IS_LTDC_CFBLNBR(Y0)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* update horizontal start/stop */ - pLayerCfg->WindowX0 = X0; - pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth; - - /* update vertical start/stop */ - pLayerCfg->WindowY0 = Y0; - pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the pixel format without reloading. - * Variant of the function HAL_LTDC_SetPixelFormat without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains - * the configuration information for the LTDC. - * @param Pixelformat new pixel format value. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters */ - assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat)); - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the pixel format */ - pLayerCfg->PixelFormat = Pixelformat; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the layer alpha value without reloading. - * Variant of the function HAL_LTDC_SetAlpha without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Alpha new alpha value. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters */ - assert_param(IS_LTDC_ALPHA(Alpha)); - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the Alpha value */ - pLayerCfg->Alpha = Alpha; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Reconfigure the frame buffer Address without reloading. - * Variant of the function HAL_LTDC_SetAddress without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param Address new address value. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx) -{ - LTDC_LayerCfgTypeDef *pLayerCfg; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Get layer configuration from handle structure */ - pLayerCfg = &hltdc->LayerCfg[LayerIdx]; - - /* Reconfigure the Address */ - pLayerCfg->FBStartAdress = Address; - - /* Set LTDC parameters */ - LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx); - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width - * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to - * layer for which we want to read and display on screen only a portion 320x240 taken in the center - * of the buffer. - * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by - * previous call to HAL_LTDC_ConfigLayer(). - * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default - * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). - * Variant of the function HAL_LTDC_SetPitch without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. - * @param LayerIdx LTDC layer index concerned by the modification of line pitch. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx) -{ - uint32_t tmp; - uint32_t pitchUpdate; - uint32_t pixelFormat; - - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* get LayerIdx used pixel format */ - pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat; - - if (pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) - { - tmp = 4U; - } - else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888) - { - tmp = 3U; - } - else if ((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pixelFormat == LTDC_PIXEL_FORMAT_AL88)) - { - tmp = 2U; - } - else - { - tmp = 1U; - } - - pitchUpdate = ((LinePitchInPixels * tmp) << 16U); - - /* Clear previously set standard pitch */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP; - - /* Set new line pitch value */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - - -/** - * @brief Configure the color keying without reloading. - * Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param RGBValue the color key value - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Configure the default color values */ - LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED); - LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable the color keying without reloading. - * Variant of the function HAL_LTDC_EnableColorKeying without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Enable LTDC color keying by setting COLKEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable the color keying without reloading. - * Variant of the function HAL_LTDC_DisableColorKeying without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Disable LTDC color keying by setting COLKEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Enable the color lookup table without reloading. - * Variant of the function HAL_LTDC_EnableCLUT without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Disable LTDC color lookup table by setting CLUTEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @brief Disable the color lookup table without reloading. - * Variant of the function HAL_LTDC_DisableCLUT without immediate reload. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: - * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LTDC_LAYER(LayerIdx)); - - /* Process locked */ - __HAL_LOCK(hltdc); - - /* Change LTDC peripheral state */ - hltdc->State = HAL_LTDC_STATE_BUSY; - - /* Disable LTDC color lookup table by setting CLUTEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN; - - /* Change the LTDC state*/ - hltdc->State = HAL_LTDC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hltdc); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup LTDC_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Check the LTDC handle state. - (+) Get the LTDC handle error code. - -@endverbatim - * @{ - */ - -/** - * @brief Return the LTDC handle state. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval HAL state - */ -HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc) -{ - return hltdc->State; -} - -/** - * @brief Return the LTDC handle error code. - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @retval LTDC Error Code - */ -uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc) -{ - return hltdc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup LTDC_Private_Functions LTDC Private Functions - * @{ - */ - -/** - * @brief Configure the LTDC peripheral - * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param pLayerCfg Pointer LTDC Layer Configuration structure - * @param LayerIdx LTDC Layer index. - * This parameter can be one of the following values: LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) - * @retval None - */ -static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) -{ - uint32_t tmp; - uint32_t tmp1; - uint32_t tmp2; - - /* Configure the horizontal start and stop position */ - tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ - ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); - - /* Configure the vertical start and stop position */ - tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); - LTDC_LAYER(hltdc, LayerIdx)->WVPCR &= ~(LTDC_LxWVPCR_WVSTPOS | LTDC_LxWVPCR_WVSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WVPCR = ((pLayerCfg->WindowY0 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP) + 1U) | tmp); - - /* Specifies the pixel format */ - LTDC_LAYER(hltdc, LayerIdx)->PFCR &= ~(LTDC_LxPFCR_PF); - LTDC_LAYER(hltdc, LayerIdx)->PFCR = (pLayerCfg->PixelFormat); - - /* Configure the default color values */ - tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); - tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); - tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | - LTDC_LxDCCR_DCALPHA); - LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); - - /* Specifies the constant alpha value */ - LTDC_LAYER(hltdc, LayerIdx)->CACR &= ~(LTDC_LxCACR_CONSTA); - LTDC_LAYER(hltdc, LayerIdx)->CACR = (pLayerCfg->Alpha); - - /* Specifies the blending factors */ - LTDC_LAYER(hltdc, LayerIdx)->BFCR &= ~(LTDC_LxBFCR_BF2 | LTDC_LxBFCR_BF1); - LTDC_LAYER(hltdc, LayerIdx)->BFCR = (pLayerCfg->BlendingFactor1 | pLayerCfg->BlendingFactor2); - - /* Configure the color frame buffer start address */ - LTDC_LAYER(hltdc, LayerIdx)->CFBAR &= ~(LTDC_LxCFBAR_CFBADD); - LTDC_LAYER(hltdc, LayerIdx)->CFBAR = (pLayerCfg->FBStartAdress); - - if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB8888) - { - tmp = 4U; - } - else if (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB888) - { - tmp = 3U; - } - else if ((pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \ - (pLayerCfg->PixelFormat == LTDC_PIXEL_FORMAT_AL88)) - { - tmp = 2U; - } - else - { - tmp = 1U; - } - - /* Configure the color frame buffer pitch in byte */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); - LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ - (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); - /* Configure the frame buffer line number */ - LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); - LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); - - /* Enable LTDC_Layer by setting LEN bit */ - LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_LEN; -} - -/** - * @} - */ - - -/** - * @} - */ - -#endif /* LTDC */ - -#endif /* HAL_LTDC_MODULE_ENABLED */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c deleted file mode 100644 index 3aa97d4b..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_ltdc_ex.c +++ /dev/null @@ -1,154 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_ltdc_ex.c - * @author MCD Application Team - * @brief LTDC Extension HAL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined(HAL_LTDC_MODULE_ENABLED) && defined(HAL_DSI_MODULE_ENABLED) - -#if defined (LTDC) && defined (DSI) - -/** @defgroup LTDCEx LTDCEx - * @brief LTDC HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions - * @{ - */ - -/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the LTDC - -@endverbatim - * @{ - */ - -/** - * @brief Retrieve common parameters from DSI Video mode configuration structure - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains - * the DSI video mode configuration parameters - * @note The implementation of this function is taking into account the LTDC - * polarities inversion as described in the current LTDC specification - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg) -{ - /* Retrieve signal polarities from DSI */ - - /* The following polarity is inverted: - LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ - -#if !defined(POLARITIES_INVERSION_UPDATED) - /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ - DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; - hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; - hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; -#else - /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ - hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29; - hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29; - hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; -#endif /* POLARITIES_INVERSION_UPDATED */ - - /* Retrieve vertical timing parameters from DSI */ - hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; - hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; - hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ - VidCfg->VerticalActive - 1U; - hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ - VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; - - return HAL_OK; -} - -/** - * @brief Retrieve common parameters from DSI Adapted command mode configuration structure - * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains - * the configuration information for the LTDC. - * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains - * the DSI command mode configuration parameters - * @note The implementation of this function is taking into account the LTDC - * polarities inversion as described in the current LTDC specification - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg) -{ - /* Retrieve signal polarities from DSI */ - - /* The following polarities are inverted: - LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH - LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH - LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ - -#if !defined(POLARITIES_INVERSION_UPDATED) - /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ - DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; - hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; - hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; -#else - /* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */ - hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29; - hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29; - hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; -#endif /* POLARITIES_INVERSION_UPDATED */ - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* LTDC && DSI */ - -#endif /* HAL_LTCD_MODULE_ENABLED && HAL_DSI_MODULE_ENABLED */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c deleted file mode 100644 index eb5d2d96..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c +++ /dev/null @@ -1,898 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_mdios.c - * @author MCD Application Team - * @brief MDIOS HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the MDIOS Peripheral. - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The MDIOS HAL driver can be used as follows: - - (#) Declare a MDIOS_HandleTypeDef handle structure. - - (#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API: - (##) Enable the MDIOS interface clock. - (##) MDIOS pins configuration: - (+++) Enable clocks for the MDIOS GPIOs. - (+++) Configure the MDIOS pins as alternate function. - (##) NVIC configuration if you need to use interrupt process: - (+++) Configure the MDIOS interrupt priority. - (+++) Enable the NVIC MDIOS IRQ handle. - - (#) Program the Port Address and the Preamble Check in the Init structure. - - (#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API. - - (#) Perform direct slave read/write operations using the following APIs: - (##) Read the value of a DINn register: HAL_MDIOS_ReadReg() - (##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg() - - (#) Get the Master read/write operations flags using the following APIs: - (##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress() - (##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress() - - (#) Clear the read/write flags using the following APIs: - (##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress() - (##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress() - - (#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called - the MDIOS will generate an interrupt in the following cases: - (##) a DINn register written by the Master - (##) a DOUTn register read by the Master - (##) an error occur - - -@@- A callback is executed for each genereted interrupt, so the driver provides the following - HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback() - -@@- HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt - and execute the previous callbacks - - (#) Reset the MDIOS peripheral and all related resources by calling the HAL_MDIOS_DeInit() API. - (##) HAL_MDIOS_MspDeInit() must be implemented to reset low level resources - (GPIO, Clocks, NVIC configuration ...) - - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_MDIOS_RegisterCallback() to register an interrupt callback. - - Function @ref HAL_MDIOS_RegisterCallback() allows to register following callbacks: - (+) WriteCpltCallback : Write Complete Callback. - (+) ReadCpltCallback : Read Complete Callback. - (+) ErrorCallback : Error Callback. - (+) WakeUpCallback : Wake UP Callback - (+) MspInitCallback : MspInit Callback. - (+) MspDeInitCallback : MspDeInit Callback. - - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function @ref HAL_MDIOS_UnRegisterCallback() to reset a callback to the default - weak function. - @ref HAL_MDIOS_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) WriteCpltCallback : Write Complete Callback. - (+) ReadCpltCallback : Read Complete Callback. - (+) ErrorCallback : Error Callback. - (+) WakeUpCallback : Wake UP Callback - (+) MspInitCallback : MspInit Callback. - (+) MspDeInitCallback : MspDeInit Callback. - - By default, after the HAL_MDIOS_Init and when the state is HAL_MDIOS_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples @ref HAL_MDIOS_WriteCpltCallback(), @ref HAL_MDIOS_ReadCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit only when - these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_MDIOS_Init/ @ref HAL_MDIOS_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in HAL_MDIOS_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_MDIOS_STATE_READY or HAL_MDIOS_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_MDIOS_RegisterCallback() before calling @ref HAL_MDIOS_DeInit - or HAL_MDIOS_Init function. - - When The compilation define USE_HAL_MDIOS_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup MDIOS MDIOS - * @brief HAL MDIOS module driver - * @{ - */ -#ifdef HAL_MDIOS_MODULE_ENABLED - -#if defined (MDIOS) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8) -#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU) -#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF)) - -#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100) -#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180) - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) -static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios); -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions - * @{ - */ - -/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the MDIOS - (+) The following parameters can be configured: - (++) Port Address - (++) Preamble Check - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the MDIOS according to the specified parameters in - * the MDIOS_InitTypeDef and creates the associated handle . - * @param hmdios pointer to a MDIOS_HandleTypeDef structure that contains - * the configuration information for MDIOS module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios) -{ - uint32_t tmpcr = 0; - - /* Check the MDIOS handle allocation */ - if(hmdios == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance)); - assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress)); - assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - if(hmdios->State == HAL_MDIOS_STATE_RESET) - { -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) - - MDIOS_InitCallbacksToDefault(hmdios); - - if(hmdios->MspInitCallback == NULL) - { - hmdios->MspInitCallback = HAL_MDIOS_MspInit; - } - - /* Init the low level hardware */ - hmdios->MspInitCallback(hmdios); - -#else - /* Init the low level hardware */ - HAL_MDIOS_MspInit(hmdios); - -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - } - - /* Change the MDIOS state */ - hmdios->State = HAL_MDIOS_STATE_BUSY; - - /* Get the MDIOS CR value */ - tmpcr = hmdios->Instance->CR; - - /* Clear PORT_ADDRESS, DPC and EN bits */ - tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS)); - - /* Set MDIOS control parametrs and enable the peripheral */ - tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\ - (hmdios->Init.PreambleCheck) | \ - (MDIOS_CR_EN)); - - /* Write the MDIOS CR */ - hmdios->Instance->CR = tmpcr; - - /* Change the MDIOS state */ - hmdios->State = HAL_MDIOS_STATE_READY; - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - /* Return function status */ - return HAL_OK; - -} - -/** - * @brief DeInitializes the MDIOS peripheral. - * @param hmdios MDIOS handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios) -{ - /* Check the MDIOS handle allocation */ - if(hmdios == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance)); - - /* Change the MDIOS state */ - hmdios->State = HAL_MDIOS_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_MDIOS_DISABLE(hmdios); - -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) - - if(hmdios->MspDeInitCallback == NULL) - { - hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit; - } - /* DeInit the low level hardware */ - hmdios->MspDeInitCallback(hmdios); - -#else - - /* DeInit the low level hardware */ - HAL_MDIOS_MspDeInit(hmdios); - -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - - /* Change the MDIOS state */ - hmdios->State = HAL_MDIOS_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief MDIOS MSP Init - * @param hmdios mdios handle - * @retval None - */ - __weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_MspInit can be implemented in the user file - */ -} - -/** - * @brief MDIOS MSP DeInit - * @param hmdios mdios handle - * @retval None - */ - __weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_MspDeInit can be implemented in the user file - */ -} - -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) -/** -* @brief Register a User MDIOS Callback -* To be used instead of the weak predefined callback -* @param hmdios mdios handle -* @param CallbackID ID of the callback to be registered -* This parameter can be one of the following values: -* @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID -* @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID -* @arg @ref HAL_MDIOS_ERROR_CB_ID Error Callback ID -* @arg @ref HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID -* @arg @ref HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID -* @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID -* @param pCallback pointer to the Callback function -* @retval status -*/ -HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(pCallback == NULL) - { - /* Return error status */ - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hmdios); - - if(hmdios->State == HAL_MDIOS_STATE_READY) - { - switch (CallbackID) - { - case HAL_MDIOS_WRITE_COMPLETE_CB_ID : - hmdios->WriteCpltCallback = pCallback; - break; - - case HAL_MDIOS_READ_COMPLETE_CB_ID : - hmdios->ReadCpltCallback = pCallback; - break; - - case HAL_MDIOS_ERROR_CB_ID : - hmdios->ErrorCallback = pCallback; - break; - - case HAL_MDIOS_WAKEUP_CB_ID : - hmdios->WakeUpCallback = pCallback; - break; - - case HAL_MDIOS_MSPINIT_CB_ID : - hmdios->MspInitCallback = pCallback; - break; - - case HAL_MDIOS_MSPDEINIT_CB_ID : - hmdios->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if(hmdios->State == HAL_MDIOS_STATE_RESET) - { - switch (CallbackID) - { - case HAL_MDIOS_MSPINIT_CB_ID : - hmdios->MspInitCallback = pCallback; - break; - - case HAL_MDIOS_MSPDEINIT_CB_ID : - hmdios->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - return status; -} - -/** -* @brief Unregister an MDIOS Callback -* MDIOS callabck is redirected to the weak predefined callback -* @param hmdios mdios handle -* @param CallbackID ID of the callback to be unregistered -* This parameter can be one of the following values: -* @arg @ref HAL_MDIOS_WRITE_COMPLETE_CB_ID Write Complete Callback ID -* @arg @ref HAL_MDIOS_READ_COMPLETE_CB_ID Read Complete Callback ID -* @arg @ref HAL_MDIOS_ERROR_CB_ID Error Callback ID -* @arg @ref HAL_MDIOS_WAKEUP_CB_ID Wake Up Callback ID -* @arg @ref HAL_MDIOS_MSPINIT_CB_ID MspInit callback ID -* @arg @ref HAL_MDIOS_MSPDEINIT_CB_ID MspDeInit callback ID -* @retval status -*/ -HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hmdios); - - if(hmdios->State == HAL_MDIOS_STATE_READY) - { - switch (CallbackID) - { - case HAL_MDIOS_WRITE_COMPLETE_CB_ID : - hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback; - break; - - case HAL_MDIOS_READ_COMPLETE_CB_ID : - hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback; - break; - - case HAL_MDIOS_ERROR_CB_ID : - hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback; - break; - - case HAL_MDIOS_WAKEUP_CB_ID : - hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback; - break; - - case HAL_MDIOS_MSPINIT_CB_ID : - hmdios->MspInitCallback = HAL_MDIOS_MspInit; - break; - - case HAL_MDIOS_MSPDEINIT_CB_ID : - hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if(hmdios->State == HAL_MDIOS_STATE_RESET) - { - switch (CallbackID) - { - case HAL_MDIOS_MSPINIT_CB_ID : - hmdios->MspInitCallback = HAL_MDIOS_MspInit; - break; - - case HAL_MDIOS_MSPDEINIT_CB_ID : - hmdios->MspDeInitCallback = HAL_MDIOS_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - return status; -} - -static void MDIOS_InitCallbacksToDefault(MDIOS_HandleTypeDef *hmdios) -{ - /* Init the MDIOS Callback settings */ - hmdios->WriteCpltCallback = HAL_MDIOS_WriteCpltCallback; /* Legacy weak WriteCpltCallback */ - hmdios->ReadCpltCallback = HAL_MDIOS_ReadCpltCallback; /* Legacy weak ReadCpltCallback */ - hmdios->ErrorCallback = HAL_MDIOS_ErrorCallback; /* Legacy weak ErrorCallback */ - hmdios->WakeUpCallback = HAL_MDIOS_WakeUpCallback; /* Legacy weak WakeUpCallback */ -} -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions - * @brief MDIOS Read/Write functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the MDIOS - read and write operations. - - (#) APIs that allow to the MDIOS to read/write from/to the - values of one of the DINn/DOUTn registers: - (+) Read the value of a DINn register: HAL_MDIOS_ReadReg() - (+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg() - - (#) APIs that provide if there are some Slave registres have been - read or written by the Master: - (+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress() - (+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress() - - (#) APIs that Clear the read/write flags: - (+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress() - (+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress() - - (#) A set of Callbacks are provided: - (+) HAL_MDIOS_WriteCpltCallback() - (+) HAL_MDIOS_ReadCpltCallback() - (+) HAL_MDIOS_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Writes to an MDIOS output register - * @param hmdios mdios handle - * @param RegNum MDIOS input register number - * @param Data Data to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_MDIOS_REGISTER(RegNum)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Get the addr of output register to be written by the MDIOS */ - tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum); - - /* Write to DOUTn register */ - *((uint32_t *)tmpreg) = Data; - - /* Process Unlocked */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief Reads an MDIOS input register - * @param hmdios mdios handle - * @param RegNum MDIOS input register number - * @param pData pointer to Data - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_MDIOS_REGISTER(RegNum)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Get the addr of input register to be read by the MDIOS */ - tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum); - - /* Read DINn register */ - *pData = (uint16_t)(*((uint32_t *)tmpreg)); - - /* Process Unlocked */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief Gets Written registers by MDIO master - * @param hmdios mdios handle - * @retval bit map of written registers addresses - */ -uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios) -{ - return hmdios->Instance->WRFR; -} - -/** - * @brief Gets Read registers by MDIO master - * @param hmdios mdios handle - * @retval bit map of read registers addresses - */ -uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios) -{ - return hmdios->Instance->RDFR; -} - -/** - * @brief Clears Write registers flag - * @param hmdios mdios handle - * @param RegNum registers addresses to be cleared - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) -{ - /* Check the parameters */ - assert_param(IS_MDIOS_REGISTER(RegNum)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Clear write registers flags */ - hmdios->Instance->CWRFR |= (RegNum); - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief Clears Read register flag - * @param hmdios mdios handle - * @param RegNum registers addresses to be cleared - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum) -{ - /* Check the parameters */ - assert_param(IS_MDIOS_REGISTER(RegNum)); - - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Clear read registers flags */ - hmdios->Instance->CRDFR |= (RegNum); - - /* Release Lock */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief Enables Events for MDIOS peripheral - * @param hmdios mdios handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios) -{ - /* Process Locked */ - __HAL_LOCK(hmdios); - - /* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */ - __HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR)); - - /* Process Unlocked */ - __HAL_UNLOCK(hmdios); - - return HAL_OK; -} - -/** - * @brief This function handles MDIOS interrupt request. - * @param hmdios MDIOS handle - * @retval None - */ -void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios) -{ - /* Write Register Interrupt enabled ? */ - if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET) - { - /* Write register flag */ - if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET) - { -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) - /* Call registered Write complete callback */ - hmdios->WriteCpltCallback(hmdios); -#else - /* Write callback function */ - HAL_MDIOS_WriteCpltCallback(hmdios); -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - - /* Clear write register flag */ - HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG); - } - } - - /* Read Register Interrupt enabled ? */ - if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET) - { - /* Read register flag */ - if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET) - { -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) - /* Call registered Read complete callback */ - hmdios->ReadCpltCallback(hmdios); -#else - /* Read callback function */ - HAL_MDIOS_ReadCpltCallback(hmdios); -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - - /* Clear read register flag */ - HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG); - } - } - - /* Error Interrupt enabled ? */ - if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET) - { - /* All Errors Flag */ - if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET) - { -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) - /* Call registered Error callback */ - hmdios->ErrorCallback(hmdios); -#else - /* Error Callback */ - HAL_MDIOS_ErrorCallback(hmdios); -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - - /* Clear errors flag */ - __HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG); - } - } - - /* check MDIOS WAKEUP exti flag */ - if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() != RESET) - { -#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1) - /* Call registered WakeUp callback */ - hmdios->WakeUpCallback(hmdios); -#else - /* MDIOS WAKEUP interrupt user callback */ - HAL_MDIOS_WakeUpCallback(hmdios); -#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */ - - /* Clear MDIOS WAKEUP Exti pending bit */ - __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief Write Complete Callback - * @param hmdios mdios handle - * @retval None - */ - __weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_WriteCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Read Complete Callback - * @param hmdios mdios handle - * @retval None - */ - __weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_ReadCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Error Callback - * @param hmdios mdios handle - * @retval None - */ - __weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MDIOS_ErrorCallback can be implemented in the user file - */ -} - -/** - * @brief MDIOS WAKEUP interrupt callback - * @param hmdios mdios handle - * @retval None - */ -__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdios); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MDIOS_WakeUpCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions - * @brief MDIOS control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the MDIOS. - (+) HAL_MDIOS_GetState() API, helpful to check in run-time the state. - (+) HAL_MDIOS_GetError() API, returns the errors occurred during data transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Gets MDIOS error flags - * @param hmdios mdios handle - * @retval bit map of occurred errors - */ -uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios) -{ - /* return errors flags on status register */ - return hmdios->Instance->SR; -} - -/** - * @brief Return the MDIOS HAL state - * @param hmdios mdios handle - * @retval MDIOS state - */ -HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios) -{ - /* Return MDIOS state */ - return hmdios->State; -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* MDIOS */ -#endif /* HAL_MDIOS_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c index 58ca6e0b..d6971953 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c @@ -1,3153 +1,3159 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_mmc.c - * @author MCD Application Team - * @brief MMC card HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Secure Digital (MMC) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + MMC card Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver implements a high level communication layer for read and write from/to - this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by - the user in HAL_MMC_MspInit() function (MSP layer). - Basically, the MSP layer configuration should be the same as we provide in the - examples. - You can easily tailor this configuration according to hardware resources. - - [..] - This driver is a generic layered driver for SDMMC memories which uses the HAL - SDMMC driver functions to interface with MMC and eMMC cards devices. - It is used as follows: - - (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API: - (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); - (##) SDMMC pins configuration for MMC card - (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() - and according to your pin assignment; - (##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA() - and HAL_MMC_WriteBlocks_DMA() APIs). - (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); - (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. - (##) NVIC configuration if you need to use interrupt process when using DMA transfer. - (+++) Configure the SDMMC and DMA interrupt priorities using function HAL_NVIC_SetPriority(); - DMA priority is superior to SDMMC's priority - (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() - and __HAL_MMC_DISABLE_IT() inside the communication process. - (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() - and __HAL_MMC_CLEAR_IT() - (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() - and HAL_MMC_WriteBlocks_IT() APIs). - (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); - (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() - and __HAL_MMC_DISABLE_IT() inside the communication process. - (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() - and __HAL_MMC_CLEAR_IT() - (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization - - - *** MMC Card Initialization and configuration *** - ================================================ - [..] - To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes - SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). - This function provide the following operations: - - (#) Initialize the SDMMC peripheral interface with default configuration. - The initialization process is done at 400KHz. You can change or adapt - this frequency by adjusting the "ClockDiv" field. - The MMC Card frequency (SDMMC_CK) is computed as follows: - - SDMMC_CK = SDMMCCLK / (ClockDiv + 2) - - In initialization mode and according to the MMC Card standard, - make sure that the SDMMC_CK frequency doesn't exceed 400KHz. - - This phase of initialization is done through SDMMC_Init() and - SDMMC_PowerState_ON() SDMMC low level APIs. - - (#) Initialize the MMC card. The API used is HAL_MMC_InitCard(). - This phase allows the card initialization and identification - and check the MMC Card type (Standard Capacity or High Capacity) - The initialization flow is compatible with MMC standard. - - This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case - of plug-off plug-in. - - (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer - frequency is set to 24MHz. You can change or adapt this frequency by adjusting - the "ClockDiv" field. - In transfer mode and according to the MMC Card standard, make sure that the - SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. - To be able to use a frequency higher than 24MHz, you should use the SDMMC - peripheral in bypass mode. Refer to the corresponding reference manual - for more details. - - (#) Select the corresponding MMC Card according to the address read with the step 2. - - (#) Configure the MMC Card in wide bus mode: 4-bits data. - - *** MMC Card Read operation *** - ============================== - [..] - (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_MMC_GetCardState() function for MMC card state. - - (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_MMC_GetCardState() function for MMC card state. - You could also check the DMA transfer process through the MMC Rx interrupt event. - - (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). - This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_MMC_GetCardState() function for MMC card state. - You could also check the IT transfer process through the MMC Rx interrupt event. - - *** MMC Card Write operation *** - =============================== - [..] - (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_MMC_GetCardState() function for MMC card state. - - (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 byte). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_MMC_GetCardState() function for MMC card state. - You could also check the DMA transfer process through the MMC Tx interrupt event. - - (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). - This function allows the read of 512 bytes blocks. - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_MMC_GetCardState() function for MMC card state. - You could also check the IT transfer process through the MMC Tx interrupt event. - - *** MMC card information *** - =========================== - [..] - (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). - It returns useful information about the MMC card such as block size, card type, - block number ... - - *** MMC card CSD register *** - ============================ - [..] - (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register. - Some of the CSD parameters are useful for card initialization and identification. - - *** MMC card CID register *** - ============================ - [..] - (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. - Some of the CID parameters are useful for card initialization and identification. - - *** MMC HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in MMC HAL driver. - - (+) __HAL_MMC_ENABLE : Enable the MMC device - (+) __HAL_MMC_DISABLE : Disable the MMC device - (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer - (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer - (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt - (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt - (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not - (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags - - [..] - (@) You can refer to the MMC HAL driver header file for more useful macros - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - Use Functions HAL_MMC_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) MspInitCallback : MMC MspInit. - (+) MspDeInitCallback : MMC MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) MspInitCallback : MMC MspInit. - (+) MspDeInitCallback : MMC MspDeInit. - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_MMC_Init - and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit - or HAL_MMC_Init function. - - When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup MMC MMC - * @brief MMC HAL module driver - * @{ - */ - -#ifdef HAL_MMC_MODULE_ENABLED - -#if defined(SDMMC1) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup MMC_Private_Defines - * @{ - */ -#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) -#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE - -#define MMC_EXT_CSD_PWR_CL_26_INDEX 201 -#define MMC_EXT_CSD_PWR_CL_52_INDEX 200 -#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238 - -#define MMC_EXT_CSD_PWR_CL_26_POS 8 -#define MMC_EXT_CSD_PWR_CL_52_POS 0 -#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 -#else -#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE - -#define MMC_EXT_CSD_PWR_CL_26_INDEX 203 -#define MMC_EXT_CSD_PWR_CL_52_INDEX 202 -#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239 - -#define MMC_EXT_CSD_PWR_CL_26_POS 24 -#define MMC_EXT_CSD_PWR_CL_52_POS 16 -#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 -#endif - -/* Frequencies used in the driver for clock divider calculation */ -#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup MMC_Private_Functions MMC Private Functions - * @{ - */ -static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); -static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); -static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); -static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout); -static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc); -static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); -static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); -static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void MMC_DMAError(DMA_HandleTypeDef *hdma); -static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); -static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); -static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup MMC_Exported_Functions - * @{ - */ - -/** @addtogroup MMC_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize the MMC - card device to be ready for use. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the MMC according to the specified parameters in the - MMC_HandleTypeDef and create the associated handle. - * @param hmmc: Pointer to the MMC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) -{ - /* Check the MMC handle allocation */ - if(hmmc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); - assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge)); - assert_param(IS_SDMMC_CLOCK_BYPASS(hmmc->Init.ClockBypass)); - assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave)); - assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide)); - assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); - assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv)); - - if(hmmc->State == HAL_MMC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hmmc->Lock = HAL_UNLOCKED; -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - /* Reset Callback pointers in HAL_MMC_STATE_RESET only */ - hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; - hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; - hmmc->ErrorCallback = HAL_MMC_ErrorCallback; - hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; - - if(hmmc->MspInitCallback == NULL) - { - hmmc->MspInitCallback = HAL_MMC_MspInit; - } - - /* Init the low level hardware */ - hmmc->MspInitCallback(hmmc); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_MMC_MspInit(hmmc); -#endif - } - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Initialize the Card parameters */ - if(HAL_MMC_InitCard(hmmc) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* Initialize the error code */ - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - /* Initialize the MMC operation */ - hmmc->Context = MMC_CONTEXT_NONE; - - /* Initialize the MMC state */ - hmmc->State = HAL_MMC_STATE_READY; - - /* Configure bus width */ - if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B) - { - if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK) - { - return HAL_ERROR; - } - } - - return HAL_OK; -} - -/** - * @brief Initializes the MMC Card. - * @param hmmc: Pointer to MMC handle - * @note This function initializes the MMC card. It could be used when a card - re-initialization is needed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) -{ - uint32_t errorstate; - MMC_InitTypeDef Init; - HAL_StatusTypeDef status; - - /* Default SDMMC peripheral configuration for MMC card initialization */ - Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; - Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; - Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; - Init.BusWide = SDMMC_BUS_WIDE_1B; - Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; - Init.ClockDiv = SDMMC_INIT_CLK_DIV; - - /* Initialize SDMMC peripheral interface with default configuration */ - status = SDMMC_Init(hmmc->Instance, Init); - if(status == HAL_ERROR) - { - return HAL_ERROR; - } - - /* Disable SDMMC Clock */ - __HAL_MMC_DISABLE(hmmc); - - /* Set Power State to ON */ - status = SDMMC_PowerState_ON(hmmc->Instance); - if(status == HAL_ERROR) - { - return HAL_ERROR; - } - - /* Enable MMC Clock */ - __HAL_MMC_ENABLE(hmmc); - - /* Required power up waiting time before starting the MMC initialization sequence */ - HAL_Delay(2); - - /* Identify card operating voltage */ - errorstate = MMC_PowerON(hmmc); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->State = HAL_MMC_STATE_READY; - hmmc->ErrorCode |= errorstate; - return HAL_ERROR; - } - - /* Card initialization */ - errorstate = MMC_InitCard(hmmc); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->State = HAL_MMC_STATE_READY; - hmmc->ErrorCode |= errorstate; - return HAL_ERROR; - } - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief De-Initializes the MMC card. - * @param hmmc: Pointer to MMC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) -{ - /* Check the MMC handle allocation */ - if(hmmc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Set MMC power state to off */ - MMC_PowerOFF(hmmc); - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - if(hmmc->MspDeInitCallback == NULL) - { - hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; - } - - /* DeInit the low level hardware */ - hmmc->MspDeInitCallback(hmmc); -#else - /* De-Initialize the MSP layer */ - HAL_MMC_MspDeInit(hmmc); -#endif - - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - hmmc->State = HAL_MMC_STATE_RESET; - - return HAL_OK; -} - - -/** - * @brief Initializes the MMC MSP. - * @param hmmc: Pointer to MMC handle - * @retval None - */ -__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmmc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MMC_MspInit could be implemented in the user file - */ -} - -/** - * @brief De-Initialize MMC MSP. - * @param hmmc: Pointer to MMC handle - * @retval None - */ -__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmmc); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MMC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @addtogroup MMC_Exported_Functions_Group2 - * @brief Data transfer functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the data - transfer from/to MMC card. - -@endverbatim - * @{ - */ - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by polling mode. - * @note This API should be followed by a check on the card state through - * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param pData: pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of MMC blocks to read - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; - uint32_t add = BlockAdd; - uint8_t *tempbuff = pData; - - if(NULL == pData) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - return HAL_ERROR; - } - - if(hmmc->State == HAL_MMC_STATE_READY) - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Initialize data control register */ - hmmc->Instance->DCTRL = 0U; - - if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) - { - add *= 512U; - } - - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1U) - { - hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); - } - else - { - hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK; - - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); - } - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - /* Poll on SDMMC flags */ - dataremaining = config.DataLength; - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) - { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) - { - /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) - { - data = SDMMC_ReadFIFO(hmmc->Instance); - *tempbuff = (uint8_t)(data & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); - tempbuff++; - dataremaining--; - } - } - - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } - } - - /* Send stop transmission command in case of multiblock read */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) - { - /* Send stop transmission command */ - errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - - /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else - { - /* Nothing to do */ - } - - /* Empty FIFO if there is still any data */ - while ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) - { - data = SDMMC_ReadFIFO(hmmc->Instance); - *tempbuff = (uint8_t)(data & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); - tempbuff++; - dataremaining--; - - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - - hmmc->State = HAL_MMC_STATE_READY; - - return HAL_OK; - } - else - { - hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; - return HAL_ERROR; - } -} - -/** - * @brief Allows to write block(s) to a specified address in a card. The Data - * transfer is managed by polling mode. - * @note This API should be followed by a check on the card state through - * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param pData: pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of MMC blocks to write - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; - uint32_t add = BlockAdd; - uint8_t *tempbuff = pData; - - if(NULL == pData) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - return HAL_ERROR; - } - - if(hmmc->State == HAL_MMC_STATE_READY) - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Initialize data control register */ - hmmc->Instance->DCTRL = 0U; - - if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) - { - add *= 512U; - } - - /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) - { - hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); - } - else - { - hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK; - - /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); - } - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - /* Write block(s) in polling mode */ - dataremaining = config.DataLength; - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) - { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) - { - /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) - { - data = (uint32_t)(*tempbuff); - tempbuff++; - dataremaining--; - data |= ((uint32_t)(*tempbuff) << 8U); - tempbuff++; - dataremaining--; - data |= ((uint32_t)(*tempbuff) << 16U); - tempbuff++; - dataremaining--; - data |= ((uint32_t)(*tempbuff) << 24U); - tempbuff++; - dataremaining--; - (void)SDMMC_WriteFIFO(hmmc->Instance, &data); - } - } - - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } - } - - /* Send stop transmission command in case of multiblock write */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) - { - /* Send stop transmission command */ - errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - } - - /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else - { - /* Nothing to do */ - } - - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - - hmmc->State = HAL_MMC_STATE_READY; - - return HAL_OK; - } - else - { - hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; - return HAL_ERROR; - } -} - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed in interrupt mode. - * @note This API should be followed by a check on the card state through - * HAL_MMC_GetCardState(). - * @note You could also check the IT transfer process through the MMC Rx - * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t add = BlockAdd; - - if(NULL == pData) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - return HAL_ERROR; - } - - if(hmmc->State == HAL_MMC_STATE_READY) - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Initialize data control register */ - hmmc->Instance->DCTRL = 0U; - - hmmc->pRxBuffPtr = pData; - hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; - - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); - - if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) - { - add *= 512U; - } - - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - /* Read Blocks in IT mode */ - if(NumberOfBlocks > 1U) - { - hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); - } - else - { - hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT); - - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); - } - - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed in interrupt mode. - * @note This API should be followed by a check on the card state through - * HAL_MMC_GetCardState(). - * @note You could also check the IT transfer process through the MMC Tx - * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t add = BlockAdd; - - if(NULL == pData) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - return HAL_ERROR; - } - - if(hmmc->State == HAL_MMC_STATE_READY) - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Initialize data control register */ - hmmc->Instance->DCTRL = 0U; - - hmmc->pTxBuffPtr = pData; - hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; - - /* Enable transfer interrupts */ - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); - - if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) - { - add *= 512U; - } - - /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) - { - hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); - } - else - { - hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT); - - /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); - } - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by a check on the card state through - * HAL_MMC_GetCardState(). - * @note You could also check the DMA transfer process through the MMC Rx - * interrupt event. - * @param hmmc: Pointer MMC handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t add = BlockAdd; - - if(NULL == pData) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - return HAL_ERROR; - } - - if(hmmc->State == HAL_MMC_STATE_READY) - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Initialize data control register */ - hmmc->Instance->DCTRL = 0U; - - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - - /* Set the DMA transfer complete callback */ - hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt; - - /* Set the DMA error callback */ - hmmc->hdmarx->XferErrorCallback = MMC_DMAError; - - /* Set the DMA Abort callback */ - hmmc->hdmarx->XferAbortCallback = NULL; - - if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) - { - add *= 512U; - } - - /* Force DMA Direction */ - hmmc->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; - MODIFY_REG(hmmc->hdmarx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmarx->Init.Direction); - - /* Enable the DMA Channel */ - if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) - { - __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode = HAL_MMC_ERROR_DMA; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else - { - /* Enable MMC DMA transfer */ - __HAL_MMC_DMA_ENABLE(hmmc); - - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) - { - hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); - } - else - { - hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); - - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); - } - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - hmmc->ErrorCode = errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by a check on the card state through - * HAL_MMC_GetCardState(). - * @note You could also check the DMA transfer process through the MMC Tx - * interrupt event. - * @param hmmc: Pointer to MMC handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t add = BlockAdd; - - if(NULL == pData) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - return HAL_ERROR; - } - - if(hmmc->State == HAL_MMC_STATE_READY) - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Initialize data control register */ - hmmc->Instance->DCTRL = 0U; - - /* Enable MMC Error interrupts */ - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); - - /* Set the DMA transfer complete callback */ - hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt; - - /* Set the DMA error callback */ - hmmc->hdmatx->XferErrorCallback = MMC_DMAError; - - /* Set the DMA Abort callback */ - hmmc->hdmatx->XferAbortCallback = NULL; - - if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) - { - add *= 512U; - } - - - /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) - { - hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); - } - else - { - hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA); - - /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); - } - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - /* Enable SDMMC DMA transfer */ - __HAL_MMC_DMA_ENABLE(hmmc); - - /* Force DMA Direction */ - hmmc->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; - MODIFY_REG(hmmc->hdmatx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmatx->Init.Direction); - - /* Enable the DMA Channel */ - if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) - { - __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else - { - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Erases the specified memory area of the given MMC card. - * @note This API should be followed by a check on the card state through - * HAL_MMC_GetCardState(). - * @param hmmc: Pointer to MMC handle - * @param BlockStartAdd: Start Block address - * @param BlockEndAdd: End Block address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) -{ - uint32_t errorstate; - uint32_t start_add = BlockStartAdd; - uint32_t end_add = BlockEndAdd; - - if(hmmc->State == HAL_MMC_STATE_READY) - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - if(end_add < start_add) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - return HAL_ERROR; - } - - if(end_add > (hmmc->MmcCard.LogBlockNbr)) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Check if the card command class supports erase command */ - if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) - { - start_add *= 512U; - end_add *= 512U; - } - - /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ - errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ - errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - /* Send CMD38 ERASE */ - errorstate = SDMMC_CmdErase(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - hmmc->State = HAL_MMC_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief This function handles MMC card interrupt request. - * @param hmmc: Pointer to MMC handle - * @retval None - */ -void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) -{ - uint32_t errorstate; - uint32_t context = hmmc->Context; - - /* Check for SDMMC interrupt flags */ - if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) - { - MMC_Read_IT(hmmc); - } - - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) - { - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); - - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ - SDMMC_IT_RXFIFOHF); - - hmmc->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); - - if((context & MMC_CONTEXT_DMA) != 0U) - { - if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) - { - errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->ErrorCallback(hmmc); -#else - HAL_MMC_ErrorCallback(hmmc); -#endif - } - } - if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) - { - /* Disable the DMA transfer for transmit request by setting the DMAEN bit - in the MMC DCTRL register */ - hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - - hmmc->State = HAL_MMC_STATE_READY; - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->TxCpltCallback(hmmc); -#else - HAL_MMC_TxCpltCallback(hmmc); -#endif - } - } - else if((context & MMC_CONTEXT_IT) != 0U) - { - /* Stop Transfer for Write Multi blocks or Read Multi blocks */ - if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) - { - errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->ErrorCallback(hmmc); -#else - HAL_MMC_ErrorCallback(hmmc); -#endif - } - } - - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - - hmmc->State = HAL_MMC_STATE_READY; - if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) - { -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->RxCpltCallback(hmmc); -#else - HAL_MMC_RxCpltCallback(hmmc); -#endif - } - else - { -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->TxCpltCallback(hmmc); -#else - HAL_MMC_TxCpltCallback(hmmc); -#endif - } - } - else - { - /* Nothing to do */ - } - } - - else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) - { - MMC_Write_IT(hmmc); - } - - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) - { - /* Set Error code */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL) != RESET) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; - } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT) != RESET) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; - } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR) != RESET) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; - } - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR) != RESET) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; - } - - /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - - /* Disable all interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); - - if((context & MMC_CONTEXT_IT) != 0U) - { - /* Set the MMC state to ready to be able to start again the process */ - hmmc->State = HAL_MMC_STATE_READY; -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->ErrorCallback(hmmc); -#else - HAL_MMC_ErrorCallback(hmmc); -#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ - } - else if((context & MMC_CONTEXT_DMA) != 0U) - { - /* Abort the MMC DMA Streams */ - if(hmmc->hdmatx != NULL) - { - /* Set the DMA Tx abort callback */ - hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; - /* Abort DMA in IT mode */ - if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) - { - MMC_DMATxAbort(hmmc->hdmatx); - } - } - else if(hmmc->hdmarx != NULL) - { - /* Set the DMA Rx abort callback */ - hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; - /* Abort DMA in IT mode */ - if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) - { - MMC_DMARxAbort(hmmc->hdmarx); - } - } - else - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - hmmc->State = HAL_MMC_STATE_READY; -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->AbortCpltCallback(hmmc); -#else - HAL_MMC_AbortCallback(hmmc); -#endif - } - } - else - { - /* Nothing to do */ - } - } - - else - { - /* Nothing to do */ - } -} - -/** - * @brief return the MMC state - * @param hmmc: Pointer to mmc handle - * @retval HAL state - */ -HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) -{ - return hmmc->State; -} - -/** -* @brief Return the MMC error code -* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains - * the configuration information. -* @retval MMC Error Code -*/ -uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) -{ - return hmmc->ErrorCode; -} - -/** - * @brief Tx Transfer completed callbacks - * @param hmmc: Pointer to MMC handle - * @retval None - */ -__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmmc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MMC_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param hmmc: Pointer MMC handle - * @retval None - */ -__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmmc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MMC_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief MMC error callbacks - * @param hmmc: Pointer MMC handle - * @retval None - */ -__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmmc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MMC_ErrorCallback can be implemented in the user file - */ -} - -/** - * @brief MMC Abort callbacks - * @param hmmc: Pointer MMC handle - * @retval None - */ -__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmmc); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_MMC_AbortCallback can be implemented in the user file - */ -} - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User MMC Callback - * To be used instead of the weak (surcharged) predefined callback - * @param hmmc : MMC handle - * @param CallbackId : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID - * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID - * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID - * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID - * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID - * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(pCallback == NULL) - { - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hmmc); - - if(hmmc->State == HAL_MMC_STATE_READY) - { - switch (CallbackId) - { - case HAL_MMC_TX_CPLT_CB_ID : - hmmc->TxCpltCallback = pCallback; - break; - case HAL_MMC_RX_CPLT_CB_ID : - hmmc->RxCpltCallback = pCallback; - break; - case HAL_MMC_ERROR_CB_ID : - hmmc->ErrorCallback = pCallback; - break; - case HAL_MMC_ABORT_CB_ID : - hmmc->AbortCpltCallback = pCallback; - break; - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = pCallback; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hmmc->State == HAL_MMC_STATE_RESET) - { - switch (CallbackId) - { - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = pCallback; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hmmc); - return status; -} - -/** - * @brief Unregister a User MMC Callback - * MMC Callback is redirected to the weak (surcharged) predefined callback - * @param hmmc : MMC handle - * @param CallbackId : ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID - * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID - * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID - * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID - * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID - * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hmmc); - - if(hmmc->State == HAL_MMC_STATE_READY) - { - switch (CallbackId) - { - case HAL_MMC_TX_CPLT_CB_ID : - hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; - break; - case HAL_MMC_RX_CPLT_CB_ID : - hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; - break; - case HAL_MMC_ERROR_CB_ID : - hmmc->ErrorCallback = HAL_MMC_ErrorCallback; - break; - case HAL_MMC_ABORT_CB_ID : - hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; - break; - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = HAL_MMC_MspInit; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hmmc->State == HAL_MMC_STATE_RESET) - { - switch (CallbackId) - { - case HAL_MMC_MSP_INIT_CB_ID : - hmmc->MspInitCallback = HAL_MMC_MspInit; - break; - case HAL_MMC_MSP_DEINIT_CB_ID : - hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; - break; - default : - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hmmc); - return status; -} -#endif - -/** - * @} - */ - -/** @addtogroup MMC_Exported_Functions_Group3 - * @brief management functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the MMC card - operations and get the related information - -@endverbatim - * @{ - */ - -/** - * @brief Returns information the information of the card which are stored on - * the CID register. - * @param hmmc: Pointer to MMC handle - * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that - * contains all CID register parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) -{ - pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); - - pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U); - - pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U)); - - pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU); - - pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U); - - pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U)); - - pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U); - - pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U); - - pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U); - - pCID->Reserved2 = 1U; - - return HAL_OK; -} - -/** - * @brief Returns information the information of the card which are stored on - * the CSD register. - * @param hmmc: Pointer to MMC handle - * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that - * contains all CSD register parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) -{ - uint32_t block_nbr = 0; - - pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U); - - pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U); - - pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U); - - pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U); - - pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U); - - pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU); - - pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U); - - pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U); - - pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U); - - pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U); - - pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U); - - pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U); - - pCSD->Reserved2 = 0U; /*!< Reserved */ - - pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U)); - - pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U); - - pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U); - - pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U); - - pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U); - - pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U); - - if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ - { - return HAL_ERROR; - } - - if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) - { - hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; - hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); - hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); - hmmc->MmcCard.LogBlockSize = 512U; - } - else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) - { - hmmc->MmcCard.BlockNbr = block_nbr; - hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; - hmmc->MmcCard.BlockSize = 512U; - hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; - } - else - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U); - - pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U); - - pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU); - - pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U); - - pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U); - - pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U); - - pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); - - pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U); - - pCSD->Reserved3 = 0; - - pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U); - - pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U); - - pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U); - - pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U); - - pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U); - - pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U); - - pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); - - pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U); - - pCSD->Reserved4 = 1; - - return HAL_OK; -} - -/** - * @brief Gets the MMC card info. - * @param hmmc: Pointer to MMC handle - * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that - * will contain the MMC card status information - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) -{ - pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); - pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); - pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd); - pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr); - pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize); - pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr); - pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize); - - return HAL_OK; -} - -/** - * @brief Returns information the information of the card which are stored on - * the Extended CSD register. - * @param hmmc Pointer to MMC handle - * @param pExtCSD Pointer to a memory area (512 bytes) that contains all - * Extended CSD register parameters - * @param Timeout Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t tickstart = HAL_GetTick(); - uint32_t count; - uint32_t *tmp_buf; - - if(NULL == pExtCSD) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - return HAL_ERROR; - } - - if(hmmc->State == HAL_MMC_STATE_READY) - { - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - hmmc->State = HAL_MMC_STATE_BUSY; - - /* Initialize data control register */ - hmmc->Instance->DCTRL = 0; - - /* Initiaize the destination pointer */ - tmp_buf = pExtCSD; - - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - /* Send ExtCSD Read command to Card */ - errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - /* Poll on SDMMC flags */ - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) - { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) - { - /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) - { - *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance); - tmp_buf++; - } - } - - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } - } - - /* Get error state */ - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - else - { - /* Nothing to do */ - } - - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - hmmc->State = HAL_MMC_STATE_READY; - } - - return HAL_OK; -} - -/** - * @brief Enables wide bus operation for the requested card if supported by - * card. - * @param hmmc: Pointer to MMC handle - * @param WideMode: Specifies the MMC card wide bus mode - * This parameter can be one of the following values: - * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer - * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer - * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) -{ - uint32_t count; - SDMMC_InitTypeDef Init; - uint32_t errorstate; - uint32_t response = 0U; - - /* Check the parameters */ - assert_param(IS_SDMMC_BUS_WIDE(WideMode)); - - /* Change State */ - hmmc->State = HAL_MMC_STATE_BUSY; - - errorstate = MMC_PwrClassUpdate(hmmc, WideMode); - - if(errorstate == HAL_MMC_ERROR_NONE) - { - if(WideMode == SDMMC_BUS_WIDE_8B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); - } - else if(WideMode == SDMMC_BUS_WIDE_4B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); - } - else if(WideMode == SDMMC_BUS_WIDE_1B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); - } - else - { - /* WideMode is not a valid argument*/ - errorstate = HAL_MMC_ERROR_PARAM; - } - - /* Check for switch error and violation of the trial number of sending CMD 13 */ - if(errorstate == HAL_MMC_ERROR_NONE) - { - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - count = SDMMC_MAX_TRIAL; - do - { - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - break; - } - - /* Get command response */ - response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); - - /* Check the status after the switch command execution */ - if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) - { - /* Check the bit SWITCH_ERROR of the device status */ - if ((response & 0x80U) != 0U) - { - errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; - } - else - { - /* Configure the SDMMC peripheral */ - Init = hmmc->Init; - Init.BusWide = WideMode; - (void)SDMMC_Init(hmmc->Instance, Init); - } - } - else if (count == 0U) - { - errorstate = SDMMC_ERROR_TIMEOUT; - } - else - { - /* Nothing to do */ - } - } - } - - /* Change State */ - hmmc->State = HAL_MMC_STATE_READY; - - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Gets the current mmc card data state. - * @param hmmc: pointer to MMC handle - * @retval Card state - */ -HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) -{ - uint32_t cardstate; - uint32_t errorstate; - uint32_t resp1 = 0U; - - errorstate = MMC_SendStatus(hmmc, &resp1); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; - } - - cardstate = ((resp1 >> 9U) & 0x0FU); - - return (HAL_MMC_CardStateTypeDef)cardstate; -} - -/** - * @brief Abort the current transfer and disable the MMC. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains - * the configuration information for MMC module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) -{ - HAL_MMC_CardStateTypeDef CardState; - - /* DIsable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - - if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) - { - /* Disable the MMC DMA request */ - hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - - /* Abort the MMC DMA Tx Stream */ - if(hmmc->hdmatx != NULL) - { - if(HAL_DMA_Abort(hmmc->hdmatx) != HAL_OK) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; - } - } - /* Abort the MMC DMA Rx Stream */ - if(hmmc->hdmarx != NULL) - { - if(HAL_DMA_Abort(hmmc->hdmarx) != HAL_OK) - { - hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; - } - } - } - - hmmc->State = HAL_MMC_STATE_READY; - - /* Initialize the MMC operation */ - hmmc->Context = MMC_CONTEXT_NONE; - - CardState = HAL_MMC_GetCardState(hmmc); - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) - { - hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); - } - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) - { - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Abort the current transfer and disable the MMC (IT mode). - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains - * the configuration information for MMC module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) -{ - HAL_MMC_CardStateTypeDef CardState; - - /* DIsable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - - if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) - { - /* Disable the MMC DMA request */ - hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - - /* Abort the MMC DMA Tx Stream */ - if(hmmc->hdmatx != NULL) - { - hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; - if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) - { - hmmc->hdmatx = NULL; - } - } - /* Abort the MMC DMA Rx Stream */ - if(hmmc->hdmarx != NULL) - { - hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; - if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) - { - hmmc->hdmarx = NULL; - } - } - } - - /* No transfer ongoing on both DMA channels*/ - if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL)) - { - CardState = HAL_MMC_GetCardState(hmmc); - hmmc->State = HAL_MMC_STATE_READY; - - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) - { - hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); - } - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) - { - return HAL_ERROR; - } - else - { -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->AbortCpltCallback(hmmc); -#else - HAL_MMC_AbortCallback(hmmc); -#endif - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private function ----------------------------------------------------------*/ -/** @addtogroup MMC_Private_Functions - * @{ - */ - -/** - * @brief DMA MMC transmit process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); - - /* Enable DATAEND Interrupt */ - __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DATAEND)); -} - -/** - * @brief DMA MMC receive process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); - uint32_t errorstate; - - /* Send stop command in multiblock write */ - if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA)) - { - errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->ErrorCallback(hmmc); -#else - HAL_MMC_ErrorCallback(hmmc); -#endif - } - } - - /* Disable the DMA transfer for transmit request by setting the DMAEN bit - in the MMC DCTRL register */ - hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - - hmmc->State = HAL_MMC_STATE_READY; - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->RxCpltCallback(hmmc); -#else - HAL_MMC_RxCpltCallback(hmmc); -#endif -} - -/** - * @brief DMA MMC communication error callback - * @param hdma: DMA handle - * @retval None - */ -static void MMC_DMAError(DMA_HandleTypeDef *hdma) -{ - MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); - HAL_MMC_CardStateTypeDef CardState; - uint32_t RxErrorCode, TxErrorCode; - - /* if DMA error is FIFO error ignore it */ - if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) - { - RxErrorCode = hmmc->hdmarx->ErrorCode; - TxErrorCode = hmmc->hdmatx->ErrorCode; - if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) - { - /* Clear All flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - - /* Disable All interrupts */ - __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; - CardState = HAL_MMC_GetCardState(hmmc); - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) - { - hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); - } - - hmmc->State= HAL_MMC_STATE_READY; - } - -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->ErrorCallback(hmmc); -#else - HAL_MMC_ErrorCallback(hmmc); -#endif - } -} - -/** - * @brief DMA MMC Tx Abort callback - * @param hdma: DMA handle - * @retval None - */ -static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) -{ - MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); - HAL_MMC_CardStateTypeDef CardState; - - if(hmmc->hdmatx != NULL) - { - hmmc->hdmatx = NULL; - } - - /* All DMA channels are aborted */ - if(hmmc->hdmarx == NULL) - { - CardState = HAL_MMC_GetCardState(hmmc); - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - hmmc->State = HAL_MMC_STATE_READY; - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) - { - hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); - - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) - { -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->AbortCpltCallback(hmmc); -#else - HAL_MMC_AbortCallback(hmmc); -#endif - } - else - { -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->ErrorCallback(hmmc); -#else - HAL_MMC_ErrorCallback(hmmc); -#endif - } - } - } -} - -/** - * @brief DMA MMC Rx Abort callback - * @param hdma: DMA handle - * @retval None - */ -static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) -{ - MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); - HAL_MMC_CardStateTypeDef CardState; - - if(hmmc->hdmarx != NULL) - { - hmmc->hdmarx = NULL; - } - - /* All DMA channels are aborted */ - if(hmmc->hdmatx == NULL) - { - CardState = HAL_MMC_GetCardState(hmmc); - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - hmmc->State = HAL_MMC_STATE_READY; - if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) - { - hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); - - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) - { -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->AbortCpltCallback(hmmc); -#else - HAL_MMC_AbortCallback(hmmc); -#endif - } - else - { -#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) - hmmc->ErrorCallback(hmmc); -#else - HAL_MMC_ErrorCallback(hmmc); -#endif - } - } - } -} - -/** - * @brief Initializes the mmc card. - * @param hmmc: Pointer to MMC handle - * @retval MMC Card error state - */ -static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) -{ - HAL_MMC_CardCSDTypeDef CSD; - uint32_t errorstate; - uint16_t mmc_rca = 2U; - MMC_InitTypeDef Init; - - /* Check the power State */ - if(SDMMC_GetPowerState(hmmc->Instance) == 0U) - { - /* Power off */ - return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; - } - - /* Send CMD2 ALL_SEND_CID */ - errorstate = SDMMC_CmdSendCID(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return errorstate; - } - else - { - /* Get Card identification number data */ - hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); - hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); - hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); - } - - /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */ - /* MMC Card publishes its RCA. */ - errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return errorstate; - } - - /* Get the MMC card RCA */ - hmmc->MmcCard.RelCardAdd = mmc_rca; - - /* Send CMD9 SEND_CSD with argument as card's RCA */ - errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return errorstate; - } - else - { - /* Get Card Specific Data */ - hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); - hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); - hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); - } - - /* Get the Card Class */ - hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); - - /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return errorstate; - } - - /* Get CSD parameters */ - if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) - { - return hmmc->ErrorCode; - } - - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; - } - - /* Get Extended CSD parameters */ - if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) - { - return hmmc->ErrorCode; - } - - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; - } - - /* Configure the SDMMC peripheral */ - Init = hmmc->Init; - Init.BusWide = SDMMC_BUS_WIDE_1B; - (void)SDMMC_Init(hmmc->Instance, Init); - - /* All cards are initialized */ - return HAL_MMC_ERROR_NONE; -} - -/** - * @brief Enquires cards about their operating voltage and configures clock - * controls and stores MMC information that will be needed in future - * in the MMC handle. - * @param hmmc: Pointer to MMC handle - * @retval error state - */ -static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) -{ - __IO uint32_t count = 0U; - uint32_t response = 0U, validvoltage = 0U; - uint32_t errorstate; - - /* CMD0: GO_IDLE_STATE */ - errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return errorstate; - } - - while(validvoltage == 0U) - { - if(count++ == SDMMC_MAX_VOLT_TRIAL) - { - return HAL_MMC_ERROR_INVALID_VOLTRANGE; - } - - /* SEND CMD1 APP_CMD with voltage range as argument */ - errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; - } - - /* Get command response */ - response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); - } - - /* When power routine is finished and command returns valid voltage */ - if (((response & (0xFF000000U)) >> 24U) == 0xC0U) - { - hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD; - } - else - { - hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD; - } - - return HAL_MMC_ERROR_NONE; -} - -/** - * @brief Turns the SDMMC output signals off. - * @param hmmc: Pointer to MMC handle - * @retval None - */ -static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc) -{ - /* Set Power State to OFF */ - (void)SDMMC_PowerState_OFF(hmmc->Instance); -} - -/** - * @brief Returns the current card's status. - * @param hmmc: Pointer to MMC handle - * @param pCardStatus: pointer to the buffer that will contain the MMC card - * status (Card Status register) - * @retval error state - */ -static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) -{ - uint32_t errorstate; - - if(pCardStatus == NULL) - { - return HAL_MMC_ERROR_PARAM; - } - - /* Send Status command */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - return errorstate; - } - - /* Get MMC card status */ - *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - - return HAL_MMC_ERROR_NONE; -} - -/** - * @brief Reads extended CSD register to get the sectors number of the device - * @param hmmc: Pointer to MMC handle - * @param pFieldData: Pointer to the read buffer - * @param FieldIndex: Index of the field to be read - * @param Timeout: Specify timeout value - * @retval HAL status - */ -static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t tickstart = HAL_GetTick(); - uint32_t count; - uint32_t i = 0; - uint32_t tmp_data; - - hmmc->ErrorCode = HAL_MMC_ERROR_NONE; - - /* Initialize data control register */ - hmmc->Instance->DCTRL = 0; - - /* Configure the MMC DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 512; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hmmc->Instance, &config); - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); - if(errorstate != HAL_MMC_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= errorstate; - hmmc->State = HAL_MMC_STATE_READY; - return HAL_ERROR; - } - - /* Poll on SDMMC flags */ - while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) - { - if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) - { - /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) - { - tmp_data = SDMMC_ReadFIFO(hmmc->Instance); - /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ - /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ - if ((i + count) == ((uint32_t)FieldIndex/4U)) - { - *pFieldData = tmp_data; - } - } - i += 8U; - } - - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); - hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; - hmmc->State= HAL_MMC_STATE_READY; - return HAL_TIMEOUT; - } - } - - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; - } - - /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); - - hmmc->State = HAL_MMC_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief Wrap up reading in non-blocking mode. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains - * the configuration information. - * @retval None - */ -static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) -{ - uint32_t count, data, dataremaining; - uint8_t* tmp; - - tmp = hmmc->pRxBuffPtr; - dataremaining = hmmc->RxXferSize; - - if (dataremaining > 0U) - { - /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) - { - data = SDMMC_ReadFIFO(hmmc->Instance); - *tmp = (uint8_t)(data & 0xFFU); - tmp++; - dataremaining--; - *tmp = (uint8_t)((data >> 8U) & 0xFFU); - tmp++; - dataremaining--; - *tmp = (uint8_t)((data >> 16U) & 0xFFU); - tmp++; - dataremaining--; - *tmp = (uint8_t)((data >> 24U) & 0xFFU); - tmp++; - dataremaining--; - } - - hmmc->pRxBuffPtr = tmp; - hmmc->RxXferSize = dataremaining; - } -} - -/** - * @brief Wrap up writing in non-blocking mode. - * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains - * the configuration information. - * @retval None - */ -static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) -{ - uint32_t count, data, dataremaining; - uint8_t* tmp; - - tmp = hmmc->pTxBuffPtr; - dataremaining = hmmc->TxXferSize; - - if (dataremaining > 0U) - { - /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) - { - data = (uint32_t)(*tmp); - tmp++; - dataremaining--; - data |= ((uint32_t)(*tmp) << 8U); - tmp++; - dataremaining--; - data |= ((uint32_t)(*tmp) << 16U); - tmp++; - dataremaining--; - data |= ((uint32_t)(*tmp) << 24U); - tmp++; - dataremaining--; - (void)SDMMC_WriteFIFO(hmmc->Instance, &data); - } - - hmmc->pTxBuffPtr = tmp; - hmmc->TxXferSize = dataremaining; - } -} - -/** - * @brief Update the power class of the device. - * @param hmmc MMC handle - * @param Wide Wide of MMC bus - * @param Speed Speed of the MMC bus - * @retval MMC Card error state - */ -static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide) -{ - uint32_t count; - uint32_t response = 0U; - uint32_t errorstate = HAL_MMC_ERROR_NONE; - uint32_t power_class, supported_pwr_class; - - if((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B)) - { - power_class = 0U; /* Default value after power-on or software reset */ - - /* Read the PowerClass field of the Extended CSD register */ - if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ - { - errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; - } - else - { - power_class = ((power_class >> 24U) & 0x000000FFU); - } - - /* Get the supported PowerClass field of the Extended CSD register */ - /* Field PWR_CL_26_xxx [201 or 203] */ - supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU); - - if(errorstate == HAL_MMC_ERROR_NONE) - { - if(Wide == SDMMC_BUS_WIDE_8B) - { - /* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */ - supported_pwr_class = (supported_pwr_class >> 4U); - } - - if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU)) - { - /* Need to change current power class */ - errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U))); - - if(errorstate == HAL_MMC_ERROR_NONE) - { - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - count = SDMMC_MAX_TRIAL; - do - { - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - break; - } - - /* Get command response */ - response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); - count--; - }while(((response & 0x100U) == 0U) && (count != 0U)); - - /* Check the status after the switch command execution */ - if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) - { - /* Check the bit SWITCH_ERROR of the device status */ - if ((response & 0x80U) != 0U) - { - errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; - } - } - else if (count == 0U) - { - errorstate = SDMMC_ERROR_TIMEOUT; - } - else - { - /* Nothing to do */ - } - } - } - } - } - - return errorstate; -} - -/** - * @} - */ - -#endif /* SDMMC1 */ - -#endif /* HAL_MMC_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_mmc.c + * @author MCD Application Team + * @brief MMC card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (MMC) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + MMC card Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_MMC_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with MMC and eMMC cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implement the HAL_MMC_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for MMC card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) DMA Configuration if you need to use DMA process (HAL_MMC_ReadBlocks_DMA() + and HAL_MMC_WriteBlocks_DMA() APIs). + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + (+++) Configure the SDMMC and DMA interrupt priorities using function HAL_NVIC_SetPriority(); + DMA priority is superior to SDMMC's priority + (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_MMC_ReadBlocks_IT() + and HAL_MMC_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_MMC_ENABLE_IT() + and __HAL_MMC_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_MMC_GET_IT() + and __HAL_MMC_CLEAR_IT() + (#) At this stage, you can perform MMC read/write/erase operations after MMC card initialization + + + *** MMC Card Initialization and configuration *** + ================================================ + [..] + To initialize the MMC Card, use the HAL_MMC_Init() function. It Initializes + SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Initialize the SDMMC peripheral interface with default configuration. + The initialization process is done at 400KHz. You can change or adapt + this frequency by adjusting the "ClockDiv" field. + The MMC Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (ClockDiv + 2) + + In initialization mode and according to the MMC Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the MMC card. The API used is HAL_MMC_InitCard(). + This phase allows the card initialization and identification + and check the MMC Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with MMC standard. + + This API (HAL_MMC_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the MMC Card Data transfer frequency. By Default, the card transfer + frequency is set to 24MHz. You can change or adapt this frequency by adjusting + the "ClockDiv" field. + In transfer mode and according to the MMC Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + To be able to use a frequency higher than 24MHz, you should use the SDMMC + peripheral in bypass mode. Refer to the corresponding reference manual + for more details. + + (#) Select the corresponding MMC Card according to the address read with the step 2. + + (#) Configure the MMC Card in wide bus mode: 4-bits data. + + *** MMC Card Read operation *** + ============================== + [..] + (+) You can read from MMC card in polling mode by using function HAL_MMC_ReadBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can read from MMC card in DMA mode by using function HAL_MMC_ReadBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Rx interrupt event. + + (+) You can read from MMC card in Interrupt mode by using function HAL_MMC_ReadBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Rx interrupt event. + + *** MMC Card Write operation *** + =============================== + [..] + (+) You can write to MMC card in polling mode by using function HAL_MMC_WriteBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + + (+) You can write to MMC card in DMA mode by using function HAL_MMC_WriteBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 byte). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the DMA transfer process through the MMC Tx interrupt event. + + (+) You can write to MMC card in Interrupt mode by using function HAL_MMC_WriteBlocks_IT(). + This function allows the read of 512 bytes blocks. + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_MMC_GetCardState() function for MMC card state. + You could also check the IT transfer process through the MMC Tx interrupt event. + + *** MMC card information *** + =========================== + [..] + (+) To get MMC card information, you can use the function HAL_MMC_GetCardInfo(). + It returns useful information about the MMC card such as block size, card type, + block number ... + + *** MMC card CSD register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** MMC card CID register *** + ============================ + [..] + (+) The HAL_MMC_GetCardCID() API allows to get the parameters of the CID register. + Some of the CID parameters are useful for card initialization and identification. + + *** MMC HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in MMC HAL driver. + + (+) __HAL_MMC_ENABLE : Enable the MMC device + (+) __HAL_MMC_DISABLE : Disable the MMC device + (+) __HAL_MMC_DMA_ENABLE: Enable the SDMMC DMA transfer + (+) __HAL_MMC_DMA_DISABLE: Disable the SDMMC DMA transfer + (+) __HAL_MMC_ENABLE_IT: Enable the MMC device interrupt + (+) __HAL_MMC_DISABLE_IT: Disable the MMC device interrupt + (+) __HAL_MMC_GET_FLAG:Check whether the specified MMC flag is set or not + (+) __HAL_MMC_CLEAR_FLAG: Clear the MMC's pending flags + + [..] + (@) You can refer to the MMC HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_MMC_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) MspInitCallback : MMC MspInit. + (+) MspDeInitCallback : MMC MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) MspInitCallback : MMC MspInit. + (+) MspDeInitCallback : MMC MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit + or HAL_MMC_Init function. + + When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup MMC MMC + * @brief MMC HAL module driver + * @{ + */ + +#ifdef HAL_MMC_MODULE_ENABLED + +#if defined(SDMMC1) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup MMC_Private_Defines + * @{ + */ +#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) +#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 201 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 200 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238 + +#define MMC_EXT_CSD_PWR_CL_26_POS 8 +#define MMC_EXT_CSD_PWR_CL_52_POS 0 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 +#else +#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 203 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 202 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239 + +#define MMC_EXT_CSD_PWR_CL_26_POS 24 +#define MMC_EXT_CSD_PWR_CL_52_POS 16 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 +#endif + +/* Frequencies used in the driver for clock divider calculation */ +#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup MMC_Private_Functions MMC Private Functions + * @{ + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc); +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus); +static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout); +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc); +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc); +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc); +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void MMC_DMAError(DMA_HandleTypeDef *hdma); +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup MMC_Exported_Functions + * @{ + */ + +/** @addtogroup MMC_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the MMC + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the MMC according to the specified parameters in the + MMC_HandleTypeDef and create the associated handle. + * @param hmmc: Pointer to the MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hmmc->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_BYPASS(hmmc->Init.ClockBypass)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hmmc->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hmmc->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hmmc->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hmmc->Init.ClockDiv)); + + if(hmmc->State == HAL_MMC_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hmmc->Lock = HAL_UNLOCKED; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_MMC_STATE_RESET only */ + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + + if(hmmc->MspInitCallback == NULL) + { + hmmc->MspInitCallback = HAL_MMC_MspInit; + } + + /* Init the low level hardware */ + hmmc->MspInitCallback(hmmc); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_MMC_MspInit(hmmc); +#endif + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize the Card parameters */ + if(HAL_MMC_InitCard(hmmc) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Initialize the error code */ + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + /* Initialize the MMC state */ + hmmc->State = HAL_MMC_STATE_READY; + + /* Configure bus width */ + if (hmmc->Init.BusWide != SDMMC_BUS_WIDE_1B) + { + if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + } + + return HAL_OK; +} + +/** + * @brief Initializes the MMC Card. + * @param hmmc: Pointer to MMC handle + * @note This function initializes the MMC card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + MMC_InitTypeDef Init; + HAL_StatusTypeDef status; + + /* Default SDMMC peripheral configuration for MMC card initialization */ + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDMMC_INIT_CLK_DIV; + + /* Initialize SDMMC peripheral interface with default configuration */ + status = SDMMC_Init(hmmc->Instance, Init); + if(status == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Disable SDMMC Clock */ + __HAL_MMC_DISABLE(hmmc); + + /* Set Power State to ON */ + status = SDMMC_PowerState_ON(hmmc->Instance); + if(status == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable MMC Clock */ + __HAL_MMC_ENABLE(hmmc); + + /* Required power up waiting time before starting the MMC initialization sequence */ + HAL_Delay(2); + + /* Identify card operating voltage */ + errorstate = MMC_PowerON(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = MMC_InitCard(hmmc); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->State = HAL_MMC_STATE_READY; + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hmmc->Instance, MMC_BLOCKSIZE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the MMC card. + * @param hmmc: Pointer to MMC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc) +{ + /* Check the MMC handle allocation */ + if(hmmc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hmmc->Instance)); + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Set MMC power state to off */ + MMC_PowerOFF(hmmc); + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + if(hmmc->MspDeInitCallback == NULL) + { + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + } + + /* DeInit the low level hardware */ + hmmc->MspDeInitCallback(hmmc); +#else + /* De-Initialize the MSP layer */ + HAL_MMC_MspDeInit(hmmc); +#endif + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_RESET; + + return HAL_OK; +} + + +/** + * @brief Initializes the MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize MMC MSP. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_MMC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to MMC card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of MMC blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = MMC_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock read */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Empty FIFO if there is still any data */ + while ((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of MMC blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = MMC_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = MMC_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * MMC_BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) + { + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + dataremaining--; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + hmmc->ErrorCode |= HAL_MMC_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pRxBuffPtr = pData; + hmmc->RxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the IT transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + hmmc->pTxBuffPtr = pData; + hmmc->TxXferSize = MMC_BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK| MMC_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Rx + * interrupt event. + * @param hmmc: Pointer MMC handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + /* Set the DMA transfer complete callback */ + hmmc->hdmarx->XferCpltCallback = MMC_DMAReceiveCplt; + + /* Set the DMA error callback */ + hmmc->hdmarx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmarx->XferAbortCallback = NULL; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + /* Force DMA Direction */ + hmmc->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hmmc->hdmarx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmarx->Init.Direction); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hmmc->hdmarx, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)pData, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) + { + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode = HAL_MMC_ERROR_DMA; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Enable MMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_READ_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + hmmc->ErrorCode = errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @note You could also check the DMA transfer process through the MMC Tx + * interrupt event. + * @param hmmc: Pointer to MMC handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0U; + + /* Enable MMC Error interrupts */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + + /* Set the DMA transfer complete callback */ + hmmc->hdmatx->XferCpltCallback = MMC_DMATransmitCplt; + + /* Set the DMA error callback */ + hmmc->hdmatx->XferErrorCallback = MMC_DMAError; + + /* Set the DMA Abort callback */ + hmmc->hdmatx->XferAbortCallback = NULL; + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + add *= 512U; + } + + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hmmc->Context = (MMC_CONTEXT_WRITE_MULTIPLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hmmc->Instance, add); + } + else + { + hmmc->Context = (MMC_CONTEXT_WRITE_SINGLE_BLOCK | MMC_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hmmc->Instance, add); + } + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Enable SDMMC DMA transfer */ + __HAL_MMC_DMA_ENABLE(hmmc); + + /* Force DMA Direction */ + hmmc->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hmmc->hdmatx->Instance->CR, DMA_SxCR_DIR, hmmc->hdmatx->Init.Direction); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hmmc->hdmatx, (uint32_t)pData, (uint32_t)&hmmc->Instance->FIFO, (uint32_t)(MMC_BLOCKSIZE * NumberOfBlocks)/4) != HAL_OK) + { + __HAL_MMC_DISABLE_IT(hmmc, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND)); + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = MMC_BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given MMC card. + * @note This API should be followed by a check on the card state through + * HAL_MMC_GetCardState(). + * @param hmmc: Pointer to MMC handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + if(end_add < start_add) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(end_add > (hmmc->MmcCard.LogBlockNbr)) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if(((hmmc->MmcCard.Class) & SDMMC_CCCC_ERASE) == 0U) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if((SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_LOCK_UNLOCK_FAILED; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + if ((hmmc->MmcCard.CardType) != MMC_HIGH_CAPACITY_CARD) + { + start_add *= 512U; + end_add *= 512U; + } + + /* Send CMD35 MMC_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdEraseStartAdd(hmmc->Instance, start_add); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD36 MMC_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdEraseEndAdd(hmmc->Instance, end_add); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles MMC card interrupt request. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc) +{ + uint32_t errorstate; + uint32_t context = hmmc->Context; + + /* Check for SDMMC interrupt flags */ + if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Read_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DATAEND) != RESET) + { + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_FLAG_DATAEND); + + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT |\ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + SDMMC_IT_RXFIFOHF); + + hmmc->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); + + if((context & MMC_CONTEXT_DMA) != 0U) + { + if((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + hmmc->State = HAL_MMC_STATE_READY; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif + } + } + else if((context & MMC_CONTEXT_IT) != 0U) + { + /* Stop Transfer for Write Multi blocks or Read Multi blocks */ + if(((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->TxCpltCallback(hmmc); +#else + HAL_MMC_TxCpltCallback(hmmc); +#endif + } + } + else + { + /* Nothing to do */ + } + } + + else if((__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & MMC_CONTEXT_IT) != 0U)) + { + MMC_Write_IT(hmmc); + } + + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) + { + /* Set Error code */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + } + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_TXUNDERR) != RESET) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_TX_UNDERRUN; + } + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + /* Disable all interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if((context & MMC_CONTEXT_IT) != 0U) + { + /* Set the MMC state to ready to be able to start again the process */ + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */ + } + else if((context & MMC_CONTEXT_DMA) != 0U) + { + /* Abort the MMC DMA Streams */ + if(((context & MMC_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + if(hmmc->hdmatx != NULL) + { + /* Set the DMA Tx abort callback */ + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + MMC_DMATxAbort(hmmc->hdmatx); + } + } + } + else if(((context & MMC_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & MMC_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + if(hmmc->hdmarx != NULL) + { + /* Set the DMA Rx abort callback */ + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + MMC_DMARxAbort(hmmc->hdmarx); + } + } + } + else + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + } + else + { + /* Nothing to do */ + } + } + + else + { + /* Nothing to do */ + } +} + +/** + * @brief return the MMC state + * @param hmmc: Pointer to mmc handle + * @retval HAL state + */ +HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc) +{ + return hmmc->State; +} + +/** +* @brief Return the MMC error code +* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. +* @retval MMC Error Code +*/ +uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc) +{ + return hmmc->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hmmc: Pointer to MMC handle + * @retval None + */ +__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief MMC error callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief MMC Abort callbacks + * @param hmmc: Pointer MMC handle + * @retval None + */ +__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hmmc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_MMC_AbortCallback can be implemented in the user file + */ +} + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User MMC Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hmmc : MMC handle + * @param CallbackId : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID + * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID + * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID + * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID + * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID + * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_MMC_RegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hmmc); + + if(hmmc->State == HAL_MMC_STATE_READY) + { + switch (CallbackId) + { + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = pCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = pCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = pCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = pCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hmmc->State == HAL_MMC_STATE_RESET) + { + switch (CallbackId) + { + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = pCallback; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmmc); + return status; +} + +/** + * @brief Unregister a User MMC Callback + * MMC Callback is redirected to the weak (surcharged) predefined callback + * @param hmmc : MMC handle + * @param CallbackId : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_MMC_TX_CPLT_CB_ID MMC Tx Complete Callback ID + * @arg @ref HAL_MMC_RX_CPLT_CB_ID MMC Rx Complete Callback ID + * @arg @ref HAL_MMC_ERROR_CB_ID MMC Error Callback ID + * @arg @ref HAL_MMC_ABORT_CB_ID MMC Abort Callback ID + * @arg @ref HAL_MMC_MSP_INIT_CB_ID MMC MspInit Callback ID + * @arg @ref HAL_MMC_MSP_DEINIT_CB_ID MMC MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hmmc); + + if(hmmc->State == HAL_MMC_STATE_READY) + { + switch (CallbackId) + { + case HAL_MMC_TX_CPLT_CB_ID : + hmmc->TxCpltCallback = HAL_MMC_TxCpltCallback; + break; + case HAL_MMC_RX_CPLT_CB_ID : + hmmc->RxCpltCallback = HAL_MMC_RxCpltCallback; + break; + case HAL_MMC_ERROR_CB_ID : + hmmc->ErrorCallback = HAL_MMC_ErrorCallback; + break; + case HAL_MMC_ABORT_CB_ID : + hmmc->AbortCpltCallback = HAL_MMC_AbortCallback; + break; + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hmmc->State == HAL_MMC_STATE_RESET) + { + switch (CallbackId) + { + case HAL_MMC_MSP_INIT_CB_ID : + hmmc->MspInitCallback = HAL_MMC_MspInit; + break; + case HAL_MMC_MSP_DEINIT_CB_ID : + hmmc->MspDeInitCallback = HAL_MMC_MspDeInit; + break; + default : + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hmmc->ErrorCode |= HAL_MMC_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hmmc); + return status; +} +#endif + +/** + * @} + */ + +/** @addtogroup MMC_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the MMC card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hmmc: Pointer to MMC handle + * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +{ + pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); + + pCID->OEM_AppliID = (uint16_t)((hmmc->CID[0] & 0x00FFFF00U) >> 8U); + + pCID->ProdName1 = (((hmmc->CID[0] & 0x000000FFU) << 24U) | ((hmmc->CID[1] & 0xFFFFFF00U) >> 8U)); + + pCID->ProdName2 = (uint8_t)(hmmc->CID[1] & 0x000000FFU); + + pCID->ProdRev = (uint8_t)((hmmc->CID[2] & 0xFF000000U) >> 24U); + + pCID->ProdSN = (((hmmc->CID[2] & 0x00FFFFFFU) << 8U) | ((hmmc->CID[3] & 0xFF000000U) >> 24U)); + + pCID->Reserved1 = (uint8_t)((hmmc->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hmmc->CID[3] & 0x000FFF00U) >> 8U); + + pCID->CID_CRC = (uint8_t)((hmmc->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hmmc: Pointer to MMC handle + * @param pCSD: Pointer to a HAL_MMC_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD) +{ + uint32_t block_nbr = 0; + + pCSD->CSDStruct = (uint8_t)((hmmc->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hmmc->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hmmc->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hmmc->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hmmc->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hmmc->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hmmc->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hmmc->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hmmc->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hmmc->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hmmc->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + + pCSD->DeviceSize = (((hmmc->CSD[1] & 0x000003FFU) << 2U) | ((hmmc->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hmmc->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hmmc->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hmmc->CSD[2] & 0x00038000U) >> 15U); + + if(MMC_ReadExtCSD(hmmc, &block_nbr, 212, 0x0FFFFFFFU) != HAL_OK) /* Field SEC_COUNT [215:212] */ + { + return HAL_ERROR; + } + + if(hmmc->MmcCard.CardType == MMC_LOW_CAPACITY_CARD) + { + hmmc->MmcCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hmmc->MmcCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hmmc->MmcCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + hmmc->MmcCard.LogBlockNbr = (hmmc->MmcCard.BlockNbr) * ((hmmc->MmcCard.BlockSize) / 512U); + hmmc->MmcCard.LogBlockSize = 512U; + } + else if(hmmc->MmcCard.CardType == MMC_HIGH_CAPACITY_CARD) + { + hmmc->MmcCard.BlockNbr = block_nbr; + hmmc->MmcCard.LogBlockNbr = hmmc->MmcCard.BlockNbr; + hmmc->MmcCard.BlockSize = 512U; + hmmc->MmcCard.LogBlockSize = hmmc->MmcCard.BlockSize; + } + else + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + pCSD->EraseGrSize = (uint8_t)((hmmc->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hmmc->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hmmc->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hmmc->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hmmc->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hmmc->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hmmc->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hmmc->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hmmc->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hmmc->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hmmc->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hmmc->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hmmc->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hmmc->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hmmc->CSD[3] & 0x000000FEU) >> 1U); + + pCSD->Reserved4 = 1; + + return HAL_OK; +} + +/** + * @brief Gets the MMC card info. + * @param hmmc: Pointer to MMC handle + * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that + * will contain the MMC card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); + pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hmmc->MmcCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hmmc->MmcCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hmmc->MmcCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hmmc->MmcCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hmmc->MmcCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the Extended CSD register. + * @param hmmc Pointer to MMC handle + * @param pExtCSD Pointer to a memory area (512 bytes) that contains all + * Extended CSD register parameters + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *tmp_buf; + + if(NULL == pExtCSD) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Initiaize the destination pointer */ + tmp_buf = pExtCSD; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Send ExtCSD Read command to Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + *tmp_buf = SDMMC_ReadFIFO(hmmc->Instance); + tmp_buf++; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + } + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hmmc: Pointer to MMC handle + * @param WideMode: Specifies the MMC card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) +{ + uint32_t count; + SDMMC_InitTypeDef Init; + uint32_t errorstate; + uint32_t response = 0U; + + /* Check the parameters */ + assert_param(IS_SDMMC_BUS_WIDE(WideMode)); + + /* Change State */ + hmmc->State = HAL_MMC_STATE_BUSY; + + errorstate = MMC_PwrClassUpdate(hmmc, WideMode); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + if(WideMode == SDMMC_BUS_WIDE_8B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); + } + else if(WideMode == SDMMC_BUS_WIDE_4B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); + } + else if(WideMode == SDMMC_BUS_WIDE_1B) + { + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); + } + else + { + /* WideMode is not a valid argument*/ + errorstate = HAL_MMC_ERROR_PARAM; + } + + /* Check for switch error and violation of the trial number of sending CMD 13 */ + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + }while(((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + /* Configure the SDMMC peripheral */ + Init = hmmc->Init; + Init.BusWide = WideMode; + (void)SDMMC_Init(hmmc->Instance, Init); + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief Gets the current mmc card data state. + * @param hmmc: pointer to MMC handle + * @retval Card state + */ +HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc) +{ + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0U; + + errorstate = MMC_SendStatus(hmmc, &resp1); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + cardstate = ((resp1 >> 9U) & 0x0FU); + + return (HAL_MMC_CardStateTypeDef)cardstate; +} + +/** + * @brief Abort the current transfer and disable the MMC. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + if(HAL_DMA_Abort(hmmc->hdmatx) != HAL_OK) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + } + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + if(HAL_DMA_Abort(hmmc->hdmarx) != HAL_OK) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + } + } + } + + hmmc->State = HAL_MMC_STATE_READY; + + /* Initialize the MMC operation */ + hmmc->Context = MMC_CONTEXT_NONE; + + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Abort the current transfer and disable the MMC (IT mode). + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information for MMC module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardStateTypeDef CardState; + + /* DIsable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + if((hmmc->hdmatx != NULL) || (hmmc->hdmarx != NULL)) + { + /* Disable the MMC DMA request */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Abort the MMC DMA Tx Stream */ + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx->XferAbortCallback = MMC_DMATxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmatx) != HAL_OK) + { + hmmc->hdmatx = NULL; + } + } + /* Abort the MMC DMA Rx Stream */ + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx->XferAbortCallback = MMC_DMARxAbort; + if(HAL_DMA_Abort_IT(hmmc->hdmarx) != HAL_OK) + { + hmmc->hdmarx = NULL; + } + } + } + + /* No transfer ongoing on both DMA channels*/ + if((hmmc->hdmatx == NULL) && (hmmc->hdmarx == NULL)) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->State = HAL_MMC_STATE_READY; + + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode = SDMMC_CmdStopTransfer(hmmc->Instance); + } + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { + return HAL_ERROR; + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup MMC_Private_Functions + * @{ + */ + +/** + * @brief DMA MMC transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + + /* Enable DATAEND Interrupt */ + __HAL_MMC_ENABLE_IT(hmmc, (SDMMC_IT_DATAEND)); +} + +/** + * @brief DMA MMC receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate; + + /* Send stop command in multiblock write */ + if(hmmc->Context == (MMC_CONTEXT_READ_MULTIPLE_BLOCK | MMC_CONTEXT_DMA)) + { + errorstate = SDMMC_CmdStopTransfer(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the MMC DCTRL register */ + hmmc->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->RxCpltCallback(hmmc); +#else + HAL_MMC_RxCpltCallback(hmmc); +#endif +} + +/** + * @brief DMA MMC communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMAError(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + uint32_t RxErrorCode, TxErrorCode; + + /* if DMA error is FIFO error ignore it */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + RxErrorCode = hmmc->hdmarx->ErrorCode; + TxErrorCode = hmmc->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) + { + /* Clear All flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_MMC_DISABLE_IT(hmmc, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + hmmc->ErrorCode |= HAL_MMC_ERROR_DMA; + CardState = HAL_MMC_GetCardState(hmmc); + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + } + + hmmc->State= HAL_MMC_STATE_READY; + } + +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } +} + +/** + * @brief DMA MMC Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmatx != NULL) + { + hmmc->hdmatx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmarx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + } +} + +/** + * @brief DMA MMC Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent); + HAL_MMC_CardStateTypeDef CardState; + + if(hmmc->hdmarx != NULL) + { + hmmc->hdmarx = NULL; + } + + /* All DMA channels are aborted */ + if(hmmc->hdmatx == NULL) + { + CardState = HAL_MMC_GetCardState(hmmc); + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + hmmc->State = HAL_MMC_STATE_READY; + if((CardState == HAL_MMC_CARD_RECEIVING) || (CardState == HAL_MMC_CARD_SENDING)) + { + hmmc->ErrorCode |= SDMMC_CmdStopTransfer(hmmc->Instance); + + if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->AbortCpltCallback(hmmc); +#else + HAL_MMC_AbortCallback(hmmc); +#endif + } + else + { +#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) + hmmc->ErrorCallback(hmmc); +#else + HAL_MMC_ErrorCallback(hmmc); +#endif + } + } + } +} + +/** + * @brief Initializes the mmc card. + * @param hmmc: Pointer to MMC handle + * @retval MMC Card error state + */ +static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) +{ + HAL_MMC_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t mmc_rca = 2U; + MMC_InitTypeDef Init; + + /* Check the power State */ + if(SDMMC_GetPowerState(hmmc->Instance) == 0U) + { + /* Power off */ + return HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; + } + + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hmmc->CID[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CID[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CID[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CID[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + } + + /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */ + /* MMC Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get the MMC card RCA */ + hmmc->MmcCard.RelCardAdd = mmc_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hmmc->CSD[0U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + hmmc->CSD[1U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2); + hmmc->CSD[2U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP3); + hmmc->CSD[3U] = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP4); + } + + /* Get the Card Class */ + hmmc->MmcCard.Class = (SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP2) >> 20U); + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get CSD parameters */ + if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Get Extended CSD parameters */ + if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Configure the SDMMC peripheral */ + Init = hmmc->Init; + Init.BusWide = SDMMC_BUS_WIDE_1B; + (void)SDMMC_Init(hmmc->Instance, Init); + + /* All cards are initialized */ + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores MMC information that will be needed in future + * in the MMC handle. + * @param hmmc: Pointer to MMC handle + * @retval error state + */ +static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hmmc->Instance); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + while(validvoltage == 0U) + { + if(count++ == SDMMC_MAX_VOLT_TRIAL) + { + return HAL_MMC_ERROR_INVALID_VOLTRANGE; + } + + /* SEND CMD1 APP_CMD with voltage range as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + } + + /* When power routine is finished and command returns valid voltage */ + if (((response & (0xFF000000U)) >> 24U) == 0xC0U) + { + hmmc->MmcCard.CardType = MMC_HIGH_CAPACITY_CARD; + } + else + { + hmmc->MmcCard.CardType = MMC_LOW_CAPACITY_CARD; + } + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Turns the SDMMC output signals off. + * @param hmmc: Pointer to MMC handle + * @retval None + */ +static void MMC_PowerOFF(MMC_HandleTypeDef *hmmc) +{ + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hmmc->Instance); +} + +/** + * @brief Returns the current card's status. + * @param hmmc: Pointer to MMC handle + * @param pCardStatus: pointer to the buffer that will contain the MMC card + * status (Card Status register) + * @retval error state + */ +static uint32_t MMC_SendStatus(MMC_HandleTypeDef *hmmc, uint32_t *pCardStatus) +{ + uint32_t errorstate; + + if(pCardStatus == NULL) + { + return HAL_MMC_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(hmmc->MmcCard.RelCardAdd << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + + /* Get MMC card status */ + *pCardStatus = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + + return HAL_MMC_ERROR_NONE; +} + +/** + * @brief Reads extended CSD register to get the sectors number of the device + * @param hmmc: Pointer to MMC handle + * @param pFieldData: Pointer to the read buffer + * @param FieldIndex: Index of the field to be read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +static uint32_t MMC_ReadExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pFieldData, uint16_t FieldIndex, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t i = 0; + uint32_t tmp_data; + + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hmmc->Instance, &config); + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDMMC_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + tmp_data = SDMMC_ReadFIFO(hmmc->Instance); + /* eg : SEC_COUNT : FieldIndex = 212 => i+count = 53 */ + /* DEVICE_TYPE : FieldIndex = 196 => i+count = 49 */ + if ((i + count) == ((uint32_t)FieldIndex/4U)) + { + *pFieldData = tmp_data; + } + } + i += 8U; + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_DATA_FLAGS); + + hmmc->State = HAL_MMC_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void MMC_Read_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hmmc->pRxBuffPtr; + dataremaining = hmmc->RxXferSize; + + if (dataremaining > 0U) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hmmc->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + dataremaining--; + } + + hmmc->pRxBuffPtr = tmp; + hmmc->RxXferSize = dataremaining; + } +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hmmc->pTxBuffPtr; + dataremaining = hmmc->TxXferSize; + + if (dataremaining > 0U) + { + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + dataremaining--; + (void)SDMMC_WriteFIFO(hmmc->Instance, &data); + } + + hmmc->pTxBuffPtr = tmp; + hmmc->TxXferSize = dataremaining; + } +} + +/** + * @brief Update the power class of the device. + * @param hmmc MMC handle + * @param Wide Wide of MMC bus + * @param Speed Speed of the MMC bus + * @retval MMC Card error state + */ +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide) +{ + uint32_t count; + uint32_t response = 0U; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t power_class, supported_pwr_class; + + if((Wide == SDMMC_BUS_WIDE_8B) || (Wide == SDMMC_BUS_WIDE_4B)) + { + power_class = 0U; /* Default value after power-on or software reset */ + + /* Read the PowerClass field of the Extended CSD register */ + if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + power_class = ((power_class >> 24U) & 0x000000FFU); + } + + /* Get the supported PowerClass field of the Extended CSD register */ + /* Field PWR_CL_26_xxx [201 or 203] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + if(Wide == SDMMC_BUS_WIDE_8B) + { + /* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */ + supported_pwr_class = (supported_pwr_class >> 4U); + } + + if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU)) + { + /* Need to change current power class */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U))); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDMMC_GetResponse(hmmc->Instance, SDMMC_RESP1); + count--; + }while(((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + } + } + + return errorstate; +} + +/** + * @} + */ + +#endif /* SDMMC1 */ + +#endif /* HAL_MMC_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_msp_template.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_msp_template.c deleted file mode 100644 index 2f4b2a04..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_msp_template.c +++ /dev/null @@ -1,101 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_msp_template.c - * @author MCD Application Team - * @brief HAL MSP module. - * This file template is located in the HAL folder and should be copied - * to the user folder. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL_MSP HAL MSP - * @brief HAL MSP module. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions - * @{ - */ - -/** - * @brief Initializes the Global MSP. - * @retval None - */ -void HAL_MspInit(void) -{ - -} - -/** - * @brief DeInitializes the Global MSP. - * @retval None - */ -void HAL_MspDeInit(void) -{ - -} - -/** - * @brief Initializes the PPP MSP. - * @retval None - */ -void HAL_PPP_MspInit(void) -{ - -} - -/** - * @brief DeInitializes the PPP MSP. - * @retval None - */ -void HAL_PPP_MspDeInit(void) -{ - -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c deleted file mode 100644 index 481e9c05..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nand.c +++ /dev/null @@ -1,2229 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_nand.c - * @author MCD Application Team - * @brief NAND HAL module driver. - * This file provides a generic firmware to drive NAND memories mounted - * as external device. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control NAND flash memories. It uses the FMC layer functions to interface - with NAND devices. This driver is used as follows: - - (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() - with control and timing parameters for both common and attribute spaces. - - (+) Read NAND flash memory maker and device IDs using the function - HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef - structure declared by the function caller. - - (+) Access NAND flash memory by read/write operations using the functions - HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(), - HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(), - HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), - HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b() - to read/write page(s)/spare area(s). These functions use specific device - information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef - structure. The read/write address information is contained by the Nand_Address_Typedef - structure passed as parameter. - - (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). - - (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). - The erase block address information is contained in the Nand_Address_Typedef - structure passed as parameter. - - (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). - - (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ - HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction - feature or the function HAL_NAND_GetECC() to get the ECC correction code. - - (+) You can monitor the NAND device HAL state by calling the function - HAL_NAND_GetState() - - [..] - (@) This driver is a set of generic APIs which handle standard NAND flash operations. - If a NAND flash device contains different operations and/or implementations, - it should be implemented separately. - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - Use Functions HAL_NAND_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) MspInitCallback : NAND MspInit. - (+) MspDeInitCallback : NAND MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. It allows to reset following callbacks: - (+) MspInitCallback : NAND MspInit. - (+) MspDeInitCallback : NAND MspDeInit. - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the HAL_NAND_Init - and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit - or HAL_NAND_Init function. - - When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_NAND_MODULE_ENABLED - -/** @defgroup NAND NAND - * @brief NAND HAL module driver - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private Constants ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup NAND_Exported_Functions NAND Exported Functions - * @{ - */ - -/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### NAND Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize - the NAND memory - -@endverbatim - * @{ - */ - -/** - * @brief Perform NAND memory Initialization sequence - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param ComSpace_Timing pointer to Common space timing structure - * @param AttSpace_Timing pointer to Attribute space timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, - FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) -{ - /* Check the NAND handle state */ - if (hnand == NULL) - { - return HAL_ERROR; - } - - if (hnand->State == HAL_NAND_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hnand->Lock = HAL_UNLOCKED; - -#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if (hnand->MspInitCallback == NULL) - { - hnand->MspInitCallback = HAL_NAND_MspInit; - } - hnand->ItCallback = HAL_NAND_ITCallback; - - /* Init the low level hardware */ - hnand->MspInitCallback(hnand); -#else - /* Initialize the low level hardware (MSP) */ - HAL_NAND_MspInit(hnand); -#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ - } - - /* Initialize NAND control Interface */ - (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init)); - - /* Initialize NAND common space timing Interface */ - (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); - - /* Initialize NAND attribute space timing Interface */ - (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); - - /* Enable the NAND device */ - __FMC_NAND_ENABLE(hnand->Instance); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Perform NAND memory De-Initialization sequence - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) -{ -#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if (hnand->MspDeInitCallback == NULL) - { - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - } - - /* DeInit the low level hardware */ - hnand->MspDeInitCallback(hnand); -#else - /* Initialize the low level hardware (MSP) */ - HAL_NAND_MspDeInit(hnand); -#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ - - /* Configure the NAND registers with their reset values */ - (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); - - /* Reset the NAND controller state */ - hnand->State = HAL_NAND_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} - -/** - * @brief NAND MSP Init - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval None - */ -__weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnand); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NAND_MspInit could be implemented in the user file - */ -} - -/** - * @brief NAND MSP DeInit - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval None - */ -__weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnand); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NAND_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief This function handles NAND device interrupt request. - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) -{ - /* Check NAND interrupt Rising edge flag */ - if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) - { - /* NAND interrupt callback*/ -#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - hnand->ItCallback(hnand); -#else - HAL_NAND_ITCallback(hnand); -#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ - - /* Clear NAND interrupt Rising edge pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); - } - - /* Check NAND interrupt Level flag */ - if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) - { - /* NAND interrupt callback*/ -#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - hnand->ItCallback(hnand); -#else - HAL_NAND_ITCallback(hnand); -#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ - - /* Clear NAND interrupt Level pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); - } - - /* Check NAND interrupt Falling edge flag */ - if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) - { - /* NAND interrupt callback*/ -#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - hnand->ItCallback(hnand); -#else - HAL_NAND_ITCallback(hnand); -#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ - - /* Clear NAND interrupt Falling edge pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); - } - - /* Check NAND interrupt FIFO empty flag */ - if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) - { - /* NAND interrupt callback*/ -#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - hnand->ItCallback(hnand); -#else - HAL_NAND_ITCallback(hnand); -#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ - - /* Clear NAND interrupt FIFO empty pending bit */ - __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); - } - -} - -/** - * @brief NAND interrupt feature callback - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval None - */ -__weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnand); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NAND_ITCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### NAND Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the NAND - memory - -@endverbatim - * @{ - */ - -/** - * @brief Read the NAND memory electronic signature - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pNAND_ID NAND ID structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) -{ - __IO uint32_t data = 0; - __IO uint32_t data1 = 0; - uint32_t deviceaddress; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - __DSB(); - - /* Read the electronic signature from NAND flash */ - if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) - { - data = *(__IO uint32_t *)deviceaddress; - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); - } - else - { - data = *(__IO uint32_t *)deviceaddress; - data1 = *((__IO uint32_t *)deviceaddress + 4); - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); - pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief NAND memory reset - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) -{ - uint32_t deviceaddress; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; - -} - -/** - * @brief Configure the device: Enter the physical parameters of the device - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) -{ - hnand->Config.PageSize = pDeviceConfig->PageSize; - hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; - hnand->Config.BlockSize = pDeviceConfig->BlockSize; - hnand->Config.BlockNbr = pDeviceConfig->BlockNbr; - hnand->Config.PlaneSize = pDeviceConfig->PlaneSize; - hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr; - hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable; - - return HAL_OK; -} - -/** - * @brief Read Page(s) from NAND memory block (8-bits addressing) - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to destination read buffer - * @param NumPageToRead number of pages to read from block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumPageToRead) -{ - uint32_t index; - uint32_t tickstart; - uint32_t deviceaddress; - uint32_t numpagesread = 0U; - uint32_t nandaddress; - uint32_t nbpages = NumPageToRead; - uint8_t *buff = pBuffer; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) read loop */ - while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - - /* Cards with page size <= 512 bytes */ - if ((hnand->Config.PageSize) <= 512U) - { - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - __DSB(); - - - if (hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) - { - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - __DSB(); - } - - /* Get Data into Buffer */ - for (index = 0U; index < hnand->Config.PageSize; index++) - { - *buff = *(uint8_t *)deviceaddress; - buff++; - } - - /* Increment read pages number */ - numpagesread++; - - /* Decrement pages to read */ - nbpages--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Read Page(s) from NAND memory block (16-bits addressing) - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned - * @param NumPageToRead number of pages to read from block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumPageToRead) -{ - uint32_t index; - uint32_t tickstart; - uint32_t deviceaddress; - uint32_t numpagesread = 0U; - uint32_t nandaddress; - uint32_t nbpages = NumPageToRead; - uint16_t *buff = pBuffer; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) read loop */ - while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - - /* Cards with page size <= 512 bytes */ - if ((hnand->Config.PageSize) <= 512U) - { - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - __DSB(); - - if (hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) - { - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - __DSB(); - } - - /* Calculate PageSize */ - if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) - { - hnand->Config.PageSize = hnand->Config.PageSize / 2U; - } - else - { - /* Do nothing */ - /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ - } - - /* Get Data into Buffer */ - for (index = 0U; index < hnand->Config.PageSize; index++) - { - *buff = *(uint16_t *)deviceaddress; - buff++; - } - - /* Increment read pages number */ - numpagesread++; - - /* Decrement pages to read */ - nbpages--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Write Page(s) to NAND memory block (8-bits addressing) - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write - * @param NumPageToWrite number of pages to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - const uint8_t *pBuffer, uint32_t NumPageToWrite) -{ - uint32_t index; - uint32_t tickstart; - uint32_t deviceaddress; - uint32_t numpageswritten = 0U; - uint32_t nandaddress; - uint32_t nbpages = NumPageToWrite; - const uint8_t *buff = pBuffer; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) write loop */ - while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - - /* Cards with page size <= 512 bytes */ - if ((hnand->Config.PageSize) <= 512U) - { - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - - /* Write data to memory */ - for (index = 0U; index < hnand->Config.PageSize; index++) - { - *(__IO uint8_t *)deviceaddress = *buff; - buff++; - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - __DSB(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) - { - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Increment written pages number */ - numpageswritten++; - - /* Decrement pages to write */ - nbpages--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Write Page(s) to NAND memory block (16-bits addressing) - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned - * @param NumPageToWrite number of pages to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - const uint16_t *pBuffer, uint32_t NumPageToWrite) -{ - uint32_t index; - uint32_t tickstart; - uint32_t deviceaddress; - uint32_t numpageswritten = 0U; - uint32_t nandaddress; - uint32_t nbpages = NumPageToWrite; - const uint16_t *buff = pBuffer; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) write loop */ - while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - - /* Cards with page size <= 512 bytes */ - if ((hnand->Config.PageSize) <= 512U) - { - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - - /* Calculate PageSize */ - if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8) - { - hnand->Config.PageSize = hnand->Config.PageSize / 2U; - } - else - { - /* Do nothing */ - /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ - } - - /* Write data to memory */ - for (index = 0U; index < hnand->Config.PageSize; index++) - { - *(__IO uint16_t *)deviceaddress = *buff; - buff++; - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - __DSB(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) - { - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Increment written pages number */ - numpageswritten++; - - /* Decrement pages to write */ - nbpages--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Read Spare area(s) from NAND memory (8-bits addressing) - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write - * @param NumSpareAreaToRead Number of spare area to read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - uint8_t *pBuffer, uint32_t NumSpareAreaToRead) -{ - uint32_t index; - uint32_t tickstart; - uint32_t deviceaddress; - uint32_t numsparearearead = 0U; - uint32_t nandaddress; - uint32_t columnaddress; - uint32_t nbspare = NumSpareAreaToRead; - uint8_t *buff = pBuffer; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Column in page address */ - columnaddress = COLUMN_ADDRESS(hnand); - - /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* Cards with page size <= 512 bytes */ - if ((hnand->Config.PageSize) <= 512U) - { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - __DSB(); - - if (hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) - { - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - __DSB(); - } - - /* Get Data into Buffer */ - for (index = 0U; index < hnand->Config.SpareAreaSize; index++) - { - *buff = *(uint8_t *)deviceaddress; - buff++; - } - - /* Increment read spare areas number */ - numsparearearead++; - - /* Decrement spare areas to read */ - nbspare--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Read Spare area(s) from NAND memory (16-bits addressing) - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. - * @param NumSpareAreaToRead Number of spare area to read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - uint16_t *pBuffer, uint32_t NumSpareAreaToRead) -{ - uint32_t index; - uint32_t tickstart; - uint32_t deviceaddress; - uint32_t numsparearearead = 0U; - uint32_t nandaddress; - uint32_t columnaddress; - uint32_t nbspare = NumSpareAreaToRead; - uint16_t *buff = pBuffer; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Column in page address */ - columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); - - /* Spare area(s) read loop */ - while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* Cards with page size <= 512 bytes */ - if ((hnand->Config.PageSize) <= 512U) - { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - __DSB(); - - if (hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) - { - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - __DSB(); - } - - /* Get Data into Buffer */ - for (index = 0U; index < hnand->Config.SpareAreaSize; index++) - { - *buff = *(uint16_t *)deviceaddress; - buff++; - } - - /* Increment read spare areas number */ - numsparearearead++; - - /* Decrement spare areas to read */ - nbspare--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Write Spare area(s) to NAND memory (8-bits addressing) - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write - * @param NumSpareAreaTowrite number of spare areas to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - const uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) -{ - uint32_t index; - uint32_t tickstart; - uint32_t deviceaddress; - uint32_t numspareareawritten = 0U; - uint32_t nandaddress; - uint32_t columnaddress; - uint32_t nbspare = NumSpareAreaTowrite; - const uint8_t *buff = pBuffer; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Page address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Column in page address */ - columnaddress = COLUMN_ADDRESS(hnand); - - /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* Cards with page size <= 512 bytes */ - if ((hnand->Config.PageSize) <= 512U) - { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - - /* Write data to memory */ - for (index = 0U; index < hnand->Config.SpareAreaSize; index++) - { - *(__IO uint8_t *)deviceaddress = *buff; - buff++; - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - __DSB(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) - { - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Increment written spare areas number */ - numspareareawritten++; - - /* Decrement spare areas to write */ - nbspare--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Write Spare area(s) to NAND memory (16-bits addressing) - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. - * @param NumSpareAreaTowrite number of spare areas to write to block - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress, - const uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) -{ - uint32_t index; - uint32_t tickstart; - uint32_t deviceaddress; - uint32_t numspareareawritten = 0U; - uint32_t nandaddress; - uint32_t columnaddress; - uint32_t nbspare = NumSpareAreaTowrite; - const uint16_t *buff = pBuffer; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Column in page address */ - columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); - - /* Spare area(s) write loop */ - while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* Cards with page size <= 512 bytes */ - if ((hnand->Config.PageSize) <= 512U) - { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); - - if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - __DSB(); - } - } - - /* Write data to memory */ - for (index = 0U; index < hnand->Config.SpareAreaSize; index++) - { - *(__IO uint16_t *)deviceaddress = *buff; - buff++; - __DSB(); - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - __DSB(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while (HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) - { - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Increment written spare areas number */ - numspareareawritten++; - - /* Decrement spare areas to write */ - nbspare--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief NAND memory Block erase - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, const NAND_AddressTypeDef *pAddress) -{ - uint32_t deviceaddress; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnand); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - __DSB(); - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; - __DSB(); - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Increment the NAND memory address - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param pAddress pointer to NAND address structure - * @retval The new status of the increment address operation. It can be: - * - NAND_VALID_ADDRESS: When the new address is valid address - * - NAND_INVALID_ADDRESS: When the new address is invalid address - */ -uint32_t HAL_NAND_Address_Inc(const NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) -{ - uint32_t status = NAND_VALID_ADDRESS; - - /* Increment page address */ - pAddress->Page++; - - /* Check NAND address is valid */ - if (pAddress->Page == hnand->Config.BlockSize) - { - pAddress->Page = 0; - pAddress->Block++; - - if (pAddress->Block == hnand->Config.PlaneSize) - { - pAddress->Block = 0; - pAddress->Plane++; - - if (pAddress->Plane == (hnand->Config.PlaneNbr)) - { - status = NAND_INVALID_ADDRESS; - } - } - } - - return (status); -} - -#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User NAND Callback - * To be used to override the weak predefined callback - * @param hnand : NAND handle - * @param CallbackId : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID - * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID - * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, - pNAND_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - if (hnand->State == HAL_NAND_STATE_READY) - { - switch (CallbackId) - { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hnand->State == HAL_NAND_STATE_RESET) - { - switch (CallbackId) - { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a User NAND Callback - * NAND Callback is redirected to the weak predefined callback - * @param hnand : NAND handle - * @param CallbackId : ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_NAND_MSP_INIT_CB_ID NAND MspInit callback ID - * @arg @ref HAL_NAND_MSP_DEINIT_CB_ID NAND MspDeInit callback ID - * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hnand->State == HAL_NAND_STATE_READY) - { - switch (CallbackId) - { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = HAL_NAND_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hnand->State == HAL_NAND_STATE_RESET) - { - switch (CallbackId) - { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the NAND interface. - -@endverbatim - * @{ - */ - - -/** - * @brief Enables dynamically NAND ECC feature. - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) -{ - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Enable ECC feature */ - (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) -{ - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Disable ECC feature */ - (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Disables dynamically NAND ECC feature. - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @param ECCval pointer to ECC value - * @param Timeout maximum timeout to wait - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - - /* Check the NAND controller state */ - if (hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnand->State == HAL_NAND_STATE_READY) - { - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Get NAND ECC value */ - status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - } - else - { - return HAL_ERROR; - } - - return status; -} - -/** - * @} - */ - - -/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### NAND State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the NAND controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief return the NAND state - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval HAL state - */ -HAL_NAND_StateTypeDef HAL_NAND_GetState(const NAND_HandleTypeDef *hnand) -{ - return hnand->State; -} - -/** - * @brief NAND memory read status - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval NAND status - */ -uint32_t HAL_NAND_Read_Status(const NAND_HandleTypeDef *hnand) -{ - uint32_t data; - uint32_t deviceaddress; - UNUSED(hnand); - - /* Identify the device address */ - deviceaddress = NAND_DEVICE; - - /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; - - /* Read status register data */ - data = *(__IO uint8_t *)deviceaddress; - - /* Return the status */ - if ((data & NAND_ERROR) == NAND_ERROR) - { - return NAND_ERROR; - } - else if ((data & NAND_READY) == NAND_READY) - { - return NAND_READY; - } - else - { - return NAND_BUSY; - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_NAND_MODULE_ENABLED */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c deleted file mode 100644 index fcff3589..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_nor.c +++ /dev/null @@ -1,1639 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_nor.c - * @author MCD Application Team - * @brief NOR HAL module driver. - * This file provides a generic firmware to drive NOR memories mounted - * as external device. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control NOR flash memories. It uses the FMC layer functions to interface - with NOR devices. This driver is used as follows: - - (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() - with control and timing parameters for both normal and extended mode. - - (+) Read NOR flash memory manufacturer code and device IDs using the function - HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef - structure declared by the function caller. - - (+) Access NOR flash memory by read/write data unit operations using the functions - HAL_NOR_Read(), HAL_NOR_Program(). - - (+) Perform NOR flash erase block/chip operations using the functions - HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). - - (+) Read the NOR flash CFI (common flash interface) IDs using the function - HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef - structure declared by the function caller. - - (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ - HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation - - (+) You can monitor the NOR device HAL state by calling the function - HAL_NOR_GetState() - [..] - (@) This driver is a set of generic APIs which handle standard NOR flash operations. - If a NOR flash device contains different operations and/or implementations, - it should be implemented separately. - - *** NOR HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in NOR HAL driver. - - (+) NOR_WRITE : NOR memory write data to specified address - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - Use Functions HAL_NOR_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) MspInitCallback : NOR MspInit. - (+) MspDeInitCallback : NOR MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. It allows to reset following callbacks: - (+) MspInitCallback : NOR MspInit. - (+) MspDeInitCallback : NOR MspDeInit. - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the HAL_NOR_Init - and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit - or HAL_NOR_Init function. - - When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_NOR_MODULE_ENABLED - -/** @defgroup NOR NOR - * @brief NOR driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup NOR_Private_Defines NOR Private Defines - * @{ - */ - -/* Constants to define address to set to write a command */ -#define NOR_CMD_ADDRESS_FIRST_BYTE (uint16_t)0x0AAA -#define NOR_CMD_ADDRESS_FIRST_CFI_BYTE (uint16_t)0x00AA -#define NOR_CMD_ADDRESS_SECOND_BYTE (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_THIRD_BYTE (uint16_t)0x0AAA - -#define NOR_CMD_ADDRESS_FIRST (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FIRST_CFI (uint16_t)0x0055 -#define NOR_CMD_ADDRESS_SECOND (uint16_t)0x02AA -#define NOR_CMD_ADDRESS_THIRD (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FOURTH (uint16_t)0x0555 -#define NOR_CMD_ADDRESS_FIFTH (uint16_t)0x02AA -#define NOR_CMD_ADDRESS_SIXTH (uint16_t)0x0555 - -/* Constants to define data to program a command */ -#define NOR_CMD_DATA_READ_RESET (uint16_t)0x00F0 -#define NOR_CMD_DATA_FIRST (uint16_t)0x00AA -#define NOR_CMD_DATA_SECOND (uint16_t)0x0055 -#define NOR_CMD_DATA_AUTO_SELECT (uint16_t)0x0090 -#define NOR_CMD_DATA_PROGRAM (uint16_t)0x00A0 -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD (uint16_t)0x0080 -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH (uint16_t)0x00AA -#define NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH (uint16_t)0x0055 -#define NOR_CMD_DATA_CHIP_ERASE (uint16_t)0x0010 -#define NOR_CMD_DATA_CFI (uint16_t)0x0098 - -#define NOR_CMD_DATA_BUFFER_AND_PROG (uint8_t)0x25 -#define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 -#define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 - -#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF -#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040 -#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8 -#define NOR_CMD_CONFIRM (uint16_t)0x00D0 -#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020 -#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060 -#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070 -#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050 - -/* Mask on NOR STATUS REGISTER */ -#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010 -#define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 -#define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 -#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080 - -/* Address of the primary command set */ -#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013 - -/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */ -#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */ -#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */ -#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */ -#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */ -#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */ -#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */ -#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */ -#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */ -#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */ -#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup NOR_Private_Variables NOR Private Variables - * @{ - */ - -static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup NOR_Exported_Functions NOR Exported Functions - * @{ - */ - -/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### NOR Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize - the NOR memory - -@endverbatim - * @{ - */ - -/** - * @brief Perform the NOR memory Initialization sequence - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Timing pointer to NOR control timing structure - * @param ExtTiming pointer to NOR extended mode timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, - FMC_NORSRAM_TimingTypeDef *ExtTiming) -{ - uint32_t deviceaddress; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NOR handle parameter */ - if (hnor == NULL) - { - return HAL_ERROR; - } - - if (hnor->State == HAL_NOR_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hnor->Lock = HAL_UNLOCKED; - -#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if (hnor->MspInitCallback == NULL) - { - hnor->MspInitCallback = HAL_NOR_MspInit; - } - - /* Init the low level hardware */ - hnor->MspInitCallback(hnor); -#else - /* Initialize the low level hardware (MSP) */ - HAL_NOR_MspInit(hnor); -#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ - } - - /* Initialize NOR control Interface */ - (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); - - /* Initialize NOR timing Interface */ - (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); - - /* Initialize NOR extended mode timing Interface */ - (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, - hnor->Init.NSBank, hnor->Init.ExtendedMode); - - /* Enable the NORSRAM device */ - __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); - - /* Initialize NOR Memory Data Width*/ - if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8) - { - uwNORMemoryDataWidth = NOR_MEMORY_8B; - } - else - { - uwNORMemoryDataWidth = NOR_MEMORY_16B; - } - - /* Initialize the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE) - { - (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_PROTECTED; - } - else - { - /* Get the value of the command set */ - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), - NOR_CMD_DATA_CFI); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - } - - hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); - - status = HAL_NOR_ReturnToReadMode(hnor); - } - - return status; -} - -/** - * @brief Perform NOR memory De-Initialization sequence - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) -{ -#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if (hnor->MspDeInitCallback == NULL) - { - hnor->MspDeInitCallback = HAL_NOR_MspDeInit; - } - - /* DeInit the low level hardware */ - hnor->MspDeInitCallback(hnor); -#else - /* De-Initialize the low level hardware (MSP) */ - HAL_NOR_MspDeInit(hnor); -#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ - - /* Configure the NOR registers with their reset values */ - (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); - - /* Reset the NOR controller state */ - hnor->State = HAL_NOR_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hnor); - - return HAL_OK; -} - -/** - * @brief NOR MSP Init - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval None - */ -__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnor); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_MspInit could be implemented in the user file - */ -} - -/** - * @brief NOR MSP DeInit - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval None - */ -__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnor); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief NOR MSP Wait for Ready/Busy signal - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Timeout Maximum timeout value - * @retval None - */ -__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hnor); - UNUSED(Timeout); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_NOR_MspWait could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### NOR Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the NOR memory - -@endverbatim - * @{ - */ - -/** - * @brief Read NOR flash IDs - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pNOR_ID pointer to NOR ID structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) -{ - uint32_t deviceaddress; - HAL_NOR_StateTypeDef state; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NOR controller state */ - state = hnor->State; - if (state == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (state == HAL_NOR_STATE_PROTECTED) - { - return HAL_ERROR; - } - else if (state == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Send read ID command */ - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_AUTO_SELECT); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_AUTO_SELECT); - } - } - else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) - { - NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT); - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_ERROR; - } - - if (status != HAL_ERROR) - { - /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, - DEVICE_CODE3_ADDR); - } - - /* Check the NOR controller state */ - hnor->State = state; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return status; -} - -/** - * @brief Returns the NOR memory to Read mode. - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) -{ - uint32_t deviceaddress; - HAL_NOR_StateTypeDef state; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NOR controller state */ - state = hnor->State; - if (state == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (state == HAL_NOR_STATE_PROTECTED) - { - return HAL_ERROR; - } - else if (state == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); - } - else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) - { - NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_ERROR; - } - - /* Check the NOR controller state */ - hnor->State = state; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return status; -} - -/** - * @brief Read data from NOR memory - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pAddress pointer to Device address - * @param pData pointer to read data - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) -{ - uint32_t deviceaddress; - HAL_NOR_StateTypeDef state; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NOR controller state */ - state = hnor->State; - if (state == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (state == HAL_NOR_STATE_PROTECTED) - { - return HAL_ERROR; - } - else if (state == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Send read data command */ - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_READ_RESET); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_READ_RESET); - } - } - else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) - { - NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY); - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_ERROR; - } - - if (status != HAL_ERROR) - { - /* Read the data */ - *pData = (uint16_t)(*(__IO uint32_t *)pAddress); - } - - /* Check the NOR controller state */ - hnor->State = state; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return status; -} - -/** - * @brief Program data to NOR memory - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pAddress Device address - * @param pData pointer to the data to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) -{ - uint32_t deviceaddress; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NOR controller state */ - if (hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnor->State == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Send program data command */ - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_PROGRAM); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); - } - } - else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) - { - NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM); - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_ERROR; - } - - if (status != HAL_ERROR) - { - /* Write the data */ - NOR_WRITE(pAddress, *pData); - } - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return status; -} - -/** - * @brief Reads a half-word buffer from the NOR memory. - * @param hnor pointer to the NOR handle - * @param uwAddress NOR memory internal address to read from. - * @param pData pointer to the buffer that receives the data read from the - * NOR memory. - * @param uwBufferSize number of Half word to read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, - uint32_t uwBufferSize) -{ - uint32_t deviceaddress; - uint32_t size = uwBufferSize; - uint32_t address = uwAddress; - uint16_t *data = pData; - HAL_NOR_StateTypeDef state; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NOR controller state */ - state = hnor->State; - if (state == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (state == HAL_NOR_STATE_PROTECTED) - { - return HAL_ERROR; - } - else if (state == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Send read data command */ - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_READ_RESET); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_READ_RESET); - } - } - else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) - { - NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_ERROR; - } - - if (status != HAL_ERROR) - { - /* Read buffer */ - while (size > 0U) - { - *data = *(__IO uint16_t *)address; - data++; - address += 2U; - size--; - } - } - - /* Check the NOR controller state */ - hnor->State = state; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return status; -} - -/** - * @brief Writes a half-word buffer to the NOR memory. This function must be used - only with S29GL128P NOR memory. - * @param hnor pointer to the NOR handle - * @param uwAddress NOR memory internal start write address - * @param pData pointer to source data buffer. - * @param uwBufferSize Size of the buffer to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, - uint32_t uwBufferSize) -{ - uint16_t *p_currentaddress; - const uint16_t *p_endaddress; - uint16_t *data = pData; - uint32_t deviceaddress; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NOR controller state */ - if (hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnor->State == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Initialize variables */ - p_currentaddress = (uint16_t *)(deviceaddress + uwAddress); - p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U))); - - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - } - else - { - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - } - /* Write Buffer Load Command */ - NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); - } - else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) - { - /* Write Buffer Load Command */ - NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM); - NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_ERROR; - } - - if (status != HAL_ERROR) - { - /* Load Data into NOR Buffer */ - while (p_currentaddress <= p_endaddress) - { - NOR_WRITE(p_currentaddress, *data); - - data++; - p_currentaddress ++; - } - - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); - } - else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */ - { - NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM); - } - } - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return status; - -} - -/** - * @brief Erase the specified block of the NOR memory - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param BlockAddress Block to erase address - * @param Address Device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) -{ - uint32_t deviceaddress; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the NOR controller state */ - if (hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnor->State == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Send block erase command sequence */ - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - } - NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); - } - else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) - { - NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK); - NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); - NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE); - NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_ERROR; - } - - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return status; - -} - -/** - * @brief Erase the entire NOR chip. - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Address Device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) -{ - uint32_t deviceaddress; - HAL_StatusTypeDef status = HAL_OK; - UNUSED(Address); - - /* Check the NOR controller state */ - if (hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hnor->State == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Send NOR chip erase command sequence */ - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_BYTE), - NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND_BYTE), - NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD_BYTE), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), - NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), - NOR_CMD_DATA_CHIP_ERASE); - } - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_ERROR; - } - - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return status; -} - -/** - * @brief Read NOR flash CFI IDs - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param pNOR_CFI pointer to NOR CFI IDs structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) -{ - uint32_t deviceaddress; - HAL_NOR_StateTypeDef state; - - /* Check the NOR controller state */ - state = hnor->State; - if (state == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - else if (state == HAL_NOR_STATE_PROTECTED) - { - return HAL_ERROR; - } - else if (state == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) - { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; - } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Send read CFI query command */ - if (uwNORMemoryDataWidth == NOR_MEMORY_8B) - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI_BYTE), - NOR_CMD_DATA_CFI); - } - else - { - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - } - /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); - - /* Check the NOR controller state */ - hnor->State = state; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User NOR Callback - * To be used to override the weak predefined callback - * @param hnor : NOR handle - * @param CallbackId : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID - * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, - pNOR_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_NOR_StateTypeDef state; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - state = hnor->State; - if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) - { - switch (CallbackId) - { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = pCallback; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a User NOR Callback - * NOR Callback is redirected to the weak predefined callback - * @param hnor : NOR handle - * @param CallbackId : ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_NOR_MSP_INIT_CB_ID NOR MspInit callback ID - * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_NOR_StateTypeDef state; - - state = hnor->State; - if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) - { - switch (CallbackId) - { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = HAL_NOR_MspInit; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = HAL_NOR_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### NOR Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the NOR interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically NOR write operation. - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) -{ - /* Check the NOR controller state */ - if (hnor->State == HAL_NOR_STATE_PROTECTED) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Enable write operation */ - (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Disables dynamically NOR write operation. - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) -{ - /* Check the NOR controller state */ - if (hnor->State == HAL_NOR_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hnor); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Disable write operation */ - (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup NOR_Exported_Functions_Group4 NOR State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### NOR State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the NOR controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief return the NOR controller state - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @retval NOR controller state - */ -HAL_NOR_StateTypeDef HAL_NOR_GetState(const NOR_HandleTypeDef *hnor) -{ - return hnor->State; -} - -/** - * @brief Returns the NOR operation status. - * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. - * @param Address Device address - * @param Timeout NOR programming Timeout - * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR - * or HAL_NOR_STATUS_TIMEOUT - */ -HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) -{ - HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmpsr1; - uint16_t tmpsr2; - uint32_t tickstart; - - /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ - HAL_NOR_MspWait(hnor, Timeout); - - /* Get the NOR memory operation status -------------------------------------*/ - - /* Get tick */ - tickstart = HAL_GetTick(); - - if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) - { - while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - status = HAL_NOR_STATUS_TIMEOUT; - } - } - - /* Read NOR status register (DQ6 and DQ5) */ - tmpsr1 = *(__IO uint16_t *)Address; - tmpsr2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) - { - return HAL_NOR_STATUS_SUCCESS ; - } - - if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) - { - status = HAL_NOR_STATUS_ONGOING; - } - - tmpsr1 = *(__IO uint16_t *)Address; - tmpsr2 = *(__IO uint16_t *)Address; - - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) - { - return HAL_NOR_STATUS_SUCCESS; - } - if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) - { - return HAL_NOR_STATUS_ERROR; - } - } - } - else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) - { - do - { - NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); - tmpsr2 = *(__IO uint16_t *)(Address); - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - return HAL_NOR_STATUS_TIMEOUT; - } - } - } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U); - - NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); - tmpsr1 = *(__IO uint16_t *)(Address); - if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) - { - /* Clear the Status Register */ - NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); - status = HAL_NOR_STATUS_ERROR; - } - else - { - status = HAL_NOR_STATUS_SUCCESS; - } - } - else - { - /* Primary command set not supported by the driver */ - status = HAL_NOR_STATUS_ERROR; - } - - /* Return the operation status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_NOR_MODULE_ENABLED */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c index 7a656d15..1ba42aa1 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd.c @@ -1,2274 +1,2273 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pcd.c - * @author MCD Application Team - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The PCD HAL driver can be used as follows: - - (#) Declare a PCD_HandleTypeDef handle structure, for example: - PCD_HandleTypeDef hpcd; - - (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) - - (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) - - (##) Initialize the related GPIO clocks - (##) Configure PCD pin-out - (##) Configure PCD NVIC interrupt - - (#)Associate the Upper USB device stack to the HAL PCD Driver: - (##) hpcd.pData = pdev; - - (#)Enable PCD transmission and reception: - (##) HAL_PCD_Start(); - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup PCD PCD - * @brief PCD HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ -#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) -/** - * @} - */ - -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup PCD_Private_Functions PCD Private Functions - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); -static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); -static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and initialize the associated handle. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) -{ -#if defined (USB_OTG_FS) - const USB_OTG_GlobalTypeDef *USBx; -#endif /* defined (USB_OTG_FS) */ - uint8_t i; - - /* Check the PCD handle allocation */ - if (hpcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - -#if defined (USB_OTG_FS) - USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) */ - - if (hpcd->State == HAL_PCD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hpcd->Lock = HAL_UNLOCKED; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SOFCallback = HAL_PCD_SOFCallback; - hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; - hpcd->ResetCallback = HAL_PCD_ResetCallback; - hpcd->SuspendCallback = HAL_PCD_SuspendCallback; - hpcd->ResumeCallback = HAL_PCD_ResumeCallback; - hpcd->ConnectCallback = HAL_PCD_ConnectCallback; - hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; - hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; - hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; - hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; - hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; - - if (hpcd->MspInitCallback == NULL) - { - hpcd->MspInitCallback = HAL_PCD_MspInit; - } - - /* Init the low level hardware */ - hpcd->MspInitCallback(hpcd); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); -#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ - } - - hpcd->State = HAL_PCD_STATE_BUSY; - -#if defined (USB_OTG_FS) - /* Disable DMA mode for FS instance */ - if (USBx == USB_OTG_FS) - { - hpcd->Init.dma_enable = 0U; - } -#endif /* defined (USB_OTG_FS) */ - - /* Disable the Interrupts */ - __HAL_PCD_DISABLE(hpcd); - - /*Init the Core (common init.) */ - if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) - { - hpcd->State = HAL_PCD_STATE_ERROR; - return HAL_ERROR; - } - - /* Force Device Mode */ - if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) - { - hpcd->State = HAL_PCD_STATE_ERROR; - return HAL_ERROR; - } - - /* Init endpoints structures */ - for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - { - /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1U; - hpcd->IN_ep[i].num = i; - hpcd->IN_ep[i].tx_fifo_num = i; - /* Control until ep is activated */ - hpcd->IN_ep[i].type = EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0U; - hpcd->IN_ep[i].xfer_buff = 0U; - hpcd->IN_ep[i].xfer_len = 0U; - } - - for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - { - hpcd->OUT_ep[i].is_in = 0U; - hpcd->OUT_ep[i].num = i; - /* Control until ep is activated */ - hpcd->OUT_ep[i].type = EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0U; - hpcd->OUT_ep[i].xfer_buff = 0U; - hpcd->OUT_ep[i].xfer_len = 0U; - } - - /* Init Device */ - if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) - { - hpcd->State = HAL_PCD_STATE_ERROR; - return HAL_ERROR; - } - - hpcd->USB_Address = 0U; - hpcd->State = HAL_PCD_STATE_READY; - - /* Activate LPM */ - if (hpcd->Init.lpm_enable == 1U) - { - (void)HAL_PCDEx_ActivateLPM(hpcd); - } - - (void)USB_DevDisconnect(hpcd->Instance); - - return HAL_OK; -} - -/** - * @brief DeInitializes the PCD peripheral. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) -{ - /* Check the PCD handle allocation */ - if (hpcd == NULL) - { - return HAL_ERROR; - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Stop Device */ - if (USB_StopDevice(hpcd->Instance) != HAL_OK) - { - return HAL_ERROR; - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - if (hpcd->MspDeInitCallback == NULL) - { - hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hpcd->MspDeInitCallback(hpcd); -#else - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_PCD_MspDeInit(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - hpcd->State = HAL_PCD_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the PCD MSP. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes PCD MSP. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User USB PCD Callback - * To be used instead of the weak predefined callback - * @param hpcd USB PCD handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID - * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID - * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID - * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID - * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID - * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID - * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID - * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID, - pPCD_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - switch (CallbackID) - { - case HAL_PCD_SOF_CB_ID : - hpcd->SOFCallback = pCallback; - break; - - case HAL_PCD_SETUPSTAGE_CB_ID : - hpcd->SetupStageCallback = pCallback; - break; - - case HAL_PCD_RESET_CB_ID : - hpcd->ResetCallback = pCallback; - break; - - case HAL_PCD_SUSPEND_CB_ID : - hpcd->SuspendCallback = pCallback; - break; - - case HAL_PCD_RESUME_CB_ID : - hpcd->ResumeCallback = pCallback; - break; - - case HAL_PCD_CONNECT_CB_ID : - hpcd->ConnectCallback = pCallback; - break; - - case HAL_PCD_DISCONNECT_CB_ID : - hpcd->DisconnectCallback = pCallback; - break; - - case HAL_PCD_MSPINIT_CB_ID : - hpcd->MspInitCallback = pCallback; - break; - - case HAL_PCD_MSPDEINIT_CB_ID : - hpcd->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hpcd->State == HAL_PCD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_PCD_MSPINIT_CB_ID : - hpcd->MspInitCallback = pCallback; - break; - - case HAL_PCD_MSPDEINIT_CB_ID : - hpcd->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; -} - -/** - * @brief Unregister an USB PCD Callback - * USB PCD callback is redirected to the weak predefined callback - * @param hpcd USB PCD handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID - * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID - * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID - * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID - * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID - * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID - * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID - * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - /* Setup Legacy weak Callbacks */ - if (hpcd->State == HAL_PCD_STATE_READY) - { - switch (CallbackID) - { - case HAL_PCD_SOF_CB_ID : - hpcd->SOFCallback = HAL_PCD_SOFCallback; - break; - - case HAL_PCD_SETUPSTAGE_CB_ID : - hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; - break; - - case HAL_PCD_RESET_CB_ID : - hpcd->ResetCallback = HAL_PCD_ResetCallback; - break; - - case HAL_PCD_SUSPEND_CB_ID : - hpcd->SuspendCallback = HAL_PCD_SuspendCallback; - break; - - case HAL_PCD_RESUME_CB_ID : - hpcd->ResumeCallback = HAL_PCD_ResumeCallback; - break; - - case HAL_PCD_CONNECT_CB_ID : - hpcd->ConnectCallback = HAL_PCD_ConnectCallback; - break; - - case HAL_PCD_DISCONNECT_CB_ID : - hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; - break; - - case HAL_PCD_MSPINIT_CB_ID : - hpcd->MspInitCallback = HAL_PCD_MspInit; - break; - - case HAL_PCD_MSPDEINIT_CB_ID : - hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; - break; - - default : - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hpcd->State == HAL_PCD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_PCD_MSPINIT_CB_ID : - hpcd->MspInitCallback = HAL_PCD_MspInit; - break; - - case HAL_PCD_MSPDEINIT_CB_ID : - hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; - break; - - default : - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; -} - -/** - * @brief Register USB PCD Data OUT Stage Callback - * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD Data OUT Stage Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, - pPCD_DataOutStageCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->DataOutStageCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD Data OUT Stage Callback - * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD Data IN Stage Callback - * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD Data IN Stage Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, - pPCD_DataInStageCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->DataInStageCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD Data IN Stage Callback - * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD Iso OUT incomplete Callback - * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, - pPCD_IsoOutIncpltCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->ISOOUTIncompleteCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD Iso OUT incomplete Callback - * USB PCD Iso OUT incomplete Callback is redirected - * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD Iso IN incomplete Callback - * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, - pPCD_IsoInIncpltCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->ISOINIncompleteCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD Iso IN incomplete Callback - * USB PCD Iso IN incomplete Callback is redirected - * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD LPM Callback - * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD LPM Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->LPMCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD LPM Callback - * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start the USB device - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - __HAL_PCD_ENABLE(hpcd); - (void)USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Stop the USB device. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - __HAL_PCD_DISABLE(hpcd); - (void)USB_DevDisconnect(hpcd->Instance); - - (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** - * @brief Handles PCD interrupt request. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - USB_OTG_EPTypeDef *ep; - uint32_t i; - uint32_t ep_intr; - uint32_t epint; - uint32_t epnum; - uint32_t fifoemptymsk; - uint32_t RegVal; - - /* ensure that we are in device mode */ - if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) - { - /* avoid spurious interrupt */ - if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) - { - return; - } - - /* store current frame number */ - hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; - - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); - } - - /* Handle RxQLevel Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - RegVal = USBx->GRXSTSP; - - ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; - - if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) - { - if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) - { - (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); - - ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; - } - } - else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) - { - (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; - } - else - { - /* ... */ - } - - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) - { - epnum = 0U; - - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - - while (ep_intr != 0U) - { - if ((ep_intr & 0x1U) != 0U) - { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); - - if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); - } - - if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); - /* Class B setup phase done for previous decoded setup */ - (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); - } - - if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); - } - - /* Clear OUT Endpoint disable interrupt */ - if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) - { - if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) - { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; - } - - ep = &hpcd->OUT_ep[epnum]; - - if (ep->is_iso_incomplete == 1U) - { - ep->is_iso_incomplete = 0U; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); - } - - /* Clear Status Phase Received interrupt */ - if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } - - /* Clear OUT NAK interrupt */ - if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); - } - } - epnum++; - ep_intr >>= 1U; - } - } - - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) - { - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - - epnum = 0U; - - while (ep_intr != 0U) - { - if ((ep_intr & 0x1U) != 0U) /* In ITR */ - { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); - - if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) - { - fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - - if (hpcd->Init.dma_enable == 1U) - { - hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - - /* this is ZLP, so prepare EP0 for next setup */ - if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) - { - /* prepare to rx more setup packets */ - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); - } - if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); - } - if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); - } - if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) - { - (void)USB_FlushTxFifo(USBx, epnum); - - ep = &hpcd->IN_ep[epnum]; - - if (ep->is_iso_incomplete == 1U) - { - ep->is_iso_incomplete = 0U; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); - } - if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) - { - (void)PCD_WriteEmptyTxFifo(hpcd, epnum); - } - } - epnum++; - ep_intr >>= 1U; - } - } - - /* Handle Resume Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) - { - /* Clear the Remote Wake-up Signaling */ - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - - if (hpcd->LPM_State == LPM_L1) - { - hpcd->LPM_State = LPM_L0; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); -#else - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ResumeCallback(hpcd); -#else - HAL_PCD_ResumeCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); - } - - /* Handle Suspend Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) - { - if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); -#else - HAL_PCD_SuspendCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); - } - - /* Handle LPM Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); - - if (hpcd->LPM_State == LPM_L0) - { - hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); -#else - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); -#else - HAL_PCD_SuspendCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - - /* Handle Reset Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) - { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); - - for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - { - USBx_INEP(i)->DIEPINT = 0xFB7FU; - USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - USBx_OUTEP(i)->DOEPINT = 0xFB7FU; - USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - } - USBx_DEVICE->DAINTMSK |= 0x10001U; - - if (hpcd->Init.use_dedicated_ep1 != 0U) - { - USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | - USB_OTG_DOEPMSK_XFRCM | - USB_OTG_DOEPMSK_EPDM; - - USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | - USB_OTG_DIEPMSK_XFRCM | - USB_OTG_DIEPMSK_EPDM; - } - else - { - USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | - USB_OTG_DOEPMSK_XFRCM | - USB_OTG_DOEPMSK_EPDM | - USB_OTG_DOEPMSK_OTEPSPRM | - USB_OTG_DOEPMSK_NAKM; - - USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | - USB_OTG_DIEPMSK_XFRCM | - USB_OTG_DIEPMSK_EPDM; - } - - /* Set Default Address to 0 */ - USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - - /* setup EP0 to receive SETUP packets */ - (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, - (uint8_t *)hpcd->Setup); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); - } - - /* Handle Enumeration done Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) - { - (void)USB_ActivateSetup(hpcd->Instance); - hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); - - /* Set USB Turnaround time */ - (void)USB_SetTurnaroundTime(hpcd->Instance, - HAL_RCC_GetHCLKFreq(), - (uint8_t)hpcd->Init.speed); - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ResetCallback(hpcd); -#else - HAL_PCD_ResetCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); - } - - /* Handle SOF Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SOFCallback(hpcd); -#else - HAL_PCD_SOFCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); - } - - /* Handle Global OUT NAK effective Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) - { - USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; - - for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) - { - if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) - { - /* Abort current transaction and disable the EP */ - (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); - } - } - } - - /* Handle Incomplete ISO IN Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) - { - for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) - { - RegVal = USBx_INEP(epnum)->DIEPCTL; - - if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && - ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) - { - hpcd->IN_ep[epnum].is_iso_incomplete = 1U; - - /* Abort current transaction and disable the EP */ - (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); - } - } - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); - } - - /* Handle Incomplete ISO OUT Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) - { - for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) - { - RegVal = USBx_OUTEP(epnum)->DOEPCTL; - - if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && - ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) - { - hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; - - USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; - - if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) - { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; - break; - } - } - } - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - - /* Handle Connection event Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ConnectCallback(hpcd); -#else - HAL_PCD_ConnectCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); - } - - /* Handle Disconnection event Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) - { - RegVal = hpcd->Instance->GOTGINT; - - if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DisconnectCallback(hpcd); -#else - HAL_PCD_DisconnectCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - hpcd->Instance->GOTGINT |= RegVal; - } - } -} - - -/** - * @brief Handles PCD Wakeup interrupt request. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd) -{ -#if defined (USB_OTG_FS) - USB_OTG_GlobalTypeDef *USBx; - USBx = hpcd->Instance; - - if (USBx == USB_OTG_FS) - { - /* Clear EXTI pending Bit */ - __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); - } - else -#endif /* defined (USB_OTG_FS) */ - { - /* Clear EXTI pending Bit */ - __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); - } -} -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - -/** - * @brief Data OUT stage callback. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ -__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DataOutStageCallback could be implemented in the user file - */ -} - -/** - * @brief Data IN stage callback - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ -__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DataInStageCallback could be implemented in the user file - */ -} -/** - * @brief Setup stage callback - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SetupStageCallback could be implemented in the user file - */ -} - -/** - * @brief USB Start Of Frame callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SOFCallback could be implemented in the user file - */ -} - -/** - * @brief USB Reset callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ResetCallback could be implemented in the user file - */ -} - -/** - * @brief Suspend event callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SuspendCallback could be implemented in the user file - */ -} - -/** - * @brief Resume event callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ResumeCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO OUT callback. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ -__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO IN callback. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ -__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Connection event callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ConnectCallback could be implemented in the user file - */ -} - -/** - * @brief Disconnection event callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DisconnectCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Connect the USB device - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - (void)USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Disconnect the USB device. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) -{ - __HAL_LOCK(hpcd); - (void)USB_DevDisconnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Set the USB Device address. - * @param hpcd PCD handle - * @param address new device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) -{ - __HAL_LOCK(hpcd); - hpcd->USB_Address = address; - (void)USB_SetDevAddress(hpcd->Instance, address); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} -/** - * @brief Open and configure an endpoint. - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param ep_mps endpoint max packet size - * @param ep_type endpoint type - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint16_t ep_mps, uint8_t ep_type) -{ - HAL_StatusTypeDef ret = HAL_OK; - PCD_EPTypeDef *ep; - - if ((ep_addr & 0x80U) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 1U; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 0U; - } - - ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; - ep->type = ep_type; - - if (ep->is_in != 0U) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } - - /* Set initial data PID. */ - if (ep_type == EP_TYPE_BULK) - { - ep->data_pid_start = 0U; - } - - __HAL_LOCK(hpcd); - (void)USB_ActivateEndpoint(hpcd->Instance, ep); - __HAL_UNLOCK(hpcd); - - return ret; -} - -/** - * @brief Deactivate an endpoint. - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if ((ep_addr & 0x80U) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 1U; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 0U; - } - ep->num = ep_addr & EP_ADDR_MSK; - - __HAL_LOCK(hpcd); - (void)USB_DeactivateEndpoint(hpcd->Instance, ep); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - - -/** - * @brief Receive an amount of data. - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param pBuf pointer to the reception buffer - * @param len amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep; - - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0U; - ep->is_in = 0U; - ep->num = ep_addr & EP_ADDR_MSK; - - if (hpcd->Init.dma_enable == 1U) - { - ep->dma_addr = (uint32_t)pBuf; - } - - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - - return HAL_OK; -} - -/** - * @brief Get Received Data Size - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval Data Size - */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) -{ - return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; -} -/** - * @brief Send an amount of data - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param pBuf pointer to the transmission buffer - * @param len amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep; - - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0U; - ep->is_in = 1U; - ep->num = ep_addr & EP_ADDR_MSK; - - if (hpcd->Init.dma_enable == 1U) - { - ep->dma_addr = (uint32_t)pBuf; - } - - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); - - return HAL_OK; -} - -/** - * @brief Set a STALL condition over an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) - { - return HAL_ERROR; - } - - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 1U; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - ep->is_in = 0U; - } - - ep->is_stall = 1U; - ep->num = ep_addr & EP_ADDR_MSK; - - __HAL_LOCK(hpcd); - - (void)USB_EPSetStall(hpcd->Instance, ep); - - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - } - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Clear a STALL condition over in an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) - { - return HAL_ERROR; - } - - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 1U; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 0U; - } - - ep->is_stall = 0U; - ep->num = ep_addr & EP_ADDR_MSK; - - __HAL_LOCK(hpcd); - (void)USB_EPClearStall(hpcd->Instance, ep); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Abort an USB EP transaction. - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - HAL_StatusTypeDef ret; - PCD_EPTypeDef *ep; - - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - } - - /* Stop Xfer */ - ret = USB_EPStopXfer(hpcd->Instance, ep); - - return ret; -} - -/** - * @brief Flush an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x80U) == 0x80U) - { - (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); - } - else - { - (void)USB_FlushRxFifo(hpcd->Instance); - } - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Activate remote wakeup signalling - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - return (USB_ActivateRemoteWakeup(hpcd->Instance)); -} - -/** - * @brief De-activate remote wakeup signalling. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - return (USB_DeActivateRemoteWakeup(hpcd->Instance)); -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the PCD handle state. - * @param hpcd PCD handle - * @retval HAL state - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) -{ - return hpcd->State; -} - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** - * @brief Set the USB Device high speed test mode. - * @param hpcd PCD handle - * @param testmode USB Device high speed test mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) -{ - const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - - switch (testmode) - { - case TEST_J: - case TEST_K: - case TEST_SE0_NAK: - case TEST_PACKET: - case TEST_FORCE_EN: - USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; - break; - - default: - break; - } - - return HAL_OK; -} -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup PCD_Private_Functions - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** - * @brief Check FIFO for the next packet to be loaded. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - USB_OTG_EPTypeDef *ep; - uint32_t len; - uint32_t len32b; - uint32_t fifoemptymsk; - - ep = &hpcd->IN_ep[epnum]; - - if (ep->xfer_count > ep->xfer_len) - { - return HAL_ERROR; - } - - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - len32b = (len + 3U) / 4U; - - while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && - (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3U) / 4U; - - (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, - (uint8_t)hpcd->Init.dma_enable); - - ep->xfer_buff += len; - ep->xfer_count += len; - } - - if (ep->xfer_len <= ep->xfer_count) - { - fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - } - - return HAL_OK; -} - - -/** - * @brief process EP OUT transfer complete interrupt. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - USB_OTG_EPTypeDef *ep; - const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); - uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; - - if (hpcd->Init.dma_enable == 1U) - { - if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ - { - /* StupPktRcvd = 1 this is a setup packet */ - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - } - else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } - else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) - { - /* StupPktRcvd = 1 this is a setup packet */ - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - else - { - ep = &hpcd->OUT_ep[epnum]; - - /* out data packet received over EP */ - ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - - if (epnum == 0U) - { - if (ep->xfer_len == 0U) - { - /* this is ZLP, so prepare EP0 for next setup */ - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } - else - { - ep->xfer_buff += ep->xfer_count; - } - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - else - { - /* ... */ - } - } - else - { - if (gSNPSiD == USB_OTG_CORE_ID_310A) - { - /* StupPktRcvd = 1 this is a setup packet */ - if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - else - { - if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - else - { - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) - { - /* this is ZLP, so prepare EP0 for next setup */ - (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - - return HAL_OK; -} - - -/** - * @brief process EP OUT setup packet received interrupt. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); - uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; - - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - - /* Inform the upper layer that a setup packet is available */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SetupStageCallback(hpcd); -#else - HAL_PCD_SetupStageCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) - { - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } - - return HAL_OK; -} -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pcd.c + * @author MCD Application Team + * @brief PCD HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The PCD HAL driver can be used as follows: + + (#) Declare a PCD_HandleTypeDef handle structure, for example: + PCD_HandleTypeDef hpcd; + + (#) Fill parameters of Init structure in HCD handle + + (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) + + (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using + (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); + (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) + + (##) Initialize the related GPIO clocks + (##) Configure PCD pin-out + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB device stack to the HAL PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable PCD transmission and reception: + (##) HAL_PCD_Start(); + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup PCD PCD + * @brief PCD HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Macros + * @{ + */ +#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) +/** + * @} + */ + +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup PCD_Private_Functions PCD Private Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) +{ +#if defined (USB_OTG_FS) + const USB_OTG_GlobalTypeDef *USBx; +#endif /* defined (USB_OTG_FS) */ + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); + +#if defined (USB_OTG_FS) + USBx = hpcd->Instance; +#endif /* defined (USB_OTG_FS) */ + + if (hpcd->State == HAL_PCD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = HAL_UNLOCKED; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback = HAL_PCD_SOFCallback; + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + hpcd->ResetCallback = HAL_PCD_ResetCallback; + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; + + if (hpcd->MspInitCallback == NULL) + { + hpcd->MspInitCallback = HAL_PCD_MspInit; + } + + /* Init the low level hardware */ + hpcd->MspInitCallback(hpcd); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_PCD_MspInit(hpcd); +#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ + } + + hpcd->State = HAL_PCD_STATE_BUSY; + +#if defined (USB_OTG_FS) + /* Disable DMA mode for FS instance */ + if (USBx == USB_OTG_FS) + { + hpcd->Init.dma_enable = 0U; + } +#endif /* defined (USB_OTG_FS) */ + + /* Disable the Interrupts */ + __HAL_PCD_DISABLE(hpcd); + + /*Init the Core (common init.) */ + if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Force Device Mode */ + if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) + { + hpcd->State = HAL_PCD_STATE_ERROR; + return HAL_ERROR; + } + + hpcd->USB_Address = 0U; + hpcd->State = HAL_PCD_STATE_READY; + + /* Activate LPM */ + if (hpcd->Init.lpm_enable == 1U) + { + (void)HAL_PCDEx_ActivateLPM(hpcd); + } + + (void)USB_DevDisconnect(hpcd->Instance); + + return HAL_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return HAL_ERROR; + } + + hpcd->State = HAL_PCD_STATE_BUSY; + + /* Stop Device */ + if (USB_StopDevice(hpcd->Instance) != HAL_OK) + { + return HAL_ERROR; + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + if (hpcd->MspDeInitCallback == NULL) + { + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware */ + hpcd->MspDeInitCallback(hpcd); +#else + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HAL_PCD_MspDeInit(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + hpcd->State = HAL_PCD_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User USB PCD Callback + * To be used instead of the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, + HAL_PCD_CallbackIDTypeDef CallbackID, + pPCD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = pCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = pCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = pCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = pCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = pCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = pCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = pCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = pCallback; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Unregister an USB PCD Callback + * USB PCD callback is redirected to the weak predefined callback + * @param hpcd USB PCD handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID + * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID + * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID + * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID + * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID + * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID + * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID + * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID + * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + /* Setup Legacy weak Callbacks */ + if (hpcd->State == HAL_PCD_STATE_READY) + { + switch (CallbackID) + { + case HAL_PCD_SOF_CB_ID : + hpcd->SOFCallback = HAL_PCD_SOFCallback; + break; + + case HAL_PCD_SETUPSTAGE_CB_ID : + hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; + break; + + case HAL_PCD_RESET_CB_ID : + hpcd->ResetCallback = HAL_PCD_ResetCallback; + break; + + case HAL_PCD_SUSPEND_CB_ID : + hpcd->SuspendCallback = HAL_PCD_SuspendCallback; + break; + + case HAL_PCD_RESUME_CB_ID : + hpcd->ResumeCallback = HAL_PCD_ResumeCallback; + break; + + case HAL_PCD_CONNECT_CB_ID : + hpcd->ConnectCallback = HAL_PCD_ConnectCallback; + break; + + case HAL_PCD_DISCONNECT_CB_ID : + hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; + break; + + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (hpcd->State == HAL_PCD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_PCD_MSPINIT_CB_ID : + hpcd->MspInitCallback = HAL_PCD_MspInit; + break; + + case HAL_PCD_MSPDEINIT_CB_ID : + hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; + break; + + default : + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + return status; +} + +/** + * @brief Register USB PCD Data OUT Stage Callback + * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data OUT Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataOutStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Data OUT Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Data IN Stage Callback + * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Data IN Stage Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, + pPCD_DataInStageCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Data IN Stage Callback + * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso OUT incomplete Callback + * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoOutIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Iso OUT incomplete Callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD Iso IN incomplete Callback + * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, + pPCD_IsoInIncpltCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD Iso IN incomplete Callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Register USB PCD LPM Callback + * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @param pCallback pointer to the USB PCD LPM Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = pCallback; + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} + +/** + * @brief Unregister the USB PCD LPM Callback + * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hpcd); + + if (hpcd->State == HAL_PCD_STATE_READY) + { + hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ + } + else + { + /* Update the error code */ + hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hpcd); + + return status; +} +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + __HAL_PCD_ENABLE(hpcd); + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + __HAL_PCD_DISABLE(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; + + /* ensure that we are in device mode */ + if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) + { + return; + } + + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) + { + /* incorrect mode, acknowledge the interrupt */ + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); + } + + /* Handle RxQLevel Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) + { + USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + + RegVal = USBx->GRXSTSP; + + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; + + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) + { + (void)USB_ReadPacket(USBx, ep->xfer_buff, + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + } + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); + (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); + /* Class B setup phase done for previous decoded setup */ + (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); + } + + if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); + } + + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) + { + /* Read in the device interrupt bits */ + ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); + + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); + + if (hpcd->Init.dma_enable == 1U) + { + hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; + + /* this is ZLP, so prepare EP0 for next setup */ + if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) + { + /* prepare to rx more setup packets */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); + } + if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); + } + if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); + } + if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) + { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) + { + (void)PCD_WriteEmptyTxFifo(hpcd, epnum); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) + { + /* Clear the Remote Wake-up Signaling */ + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + + if (hpcd->LPM_State == LPM_L1) + { + hpcd->LPM_State = LPM_L0; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResumeCallback(hpcd); +#else + HAL_PCD_ResumeCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); + } + + /* Handle Suspend Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) + { + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); + } + + /* Handle LPM Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) + { + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); + + if (hpcd->LPM_State == LPM_L0) + { + hpcd->LPM_State = LPM_L1; + hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); +#else + HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SuspendCallback(hpcd); +#else + HAL_PCD_SuspendCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + /* Handle Reset Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) + { + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; + (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + } + USBx_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) + { + USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM; + + USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + else + { + USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM | + USB_OTG_DOEPMSK_EPDM | + USB_OTG_DOEPMSK_OTEPSPRM | + USB_OTG_DOEPMSK_NAKM; + + USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | + USB_OTG_DIEPMSK_XFRCM | + USB_OTG_DIEPMSK_EPDM; + } + + /* Set Default Address to 0 */ + USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; + + /* setup EP0 to receive SETUP packets */ + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, + (uint8_t *)hpcd->Setup); + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) + { + (void)USB_ActivateSetup(hpcd->Instance); + hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); + + /* Set USB Turnaround time */ + (void)USB_SetTurnaroundTime(hpcd->Instance, + HAL_RCC_GetHCLKFreq(), + (uint8_t)hpcd->Init.speed); + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ResetCallback(hpcd); +#else + HAL_PCD_ResetCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); + } + + /* Handle SOF Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SOFCallback(hpcd); +#else + HAL_PCD_SOFCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); + } + + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + + /* Handle Incomplete ISO IN Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; + + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); + } + + /* Handle Incomplete ISO OUT Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; + + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + (((RegVal & (0x1U << 16)) >> 16U) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); + } + + /* Handle Connection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ConnectCallback(hpcd); +#else + HAL_PCD_ConnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); + } + + /* Handle Disconnection event Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) + { + RegVal = hpcd->Instance->GOTGINT; + + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DisconnectCallback(hpcd); +#else + HAL_PCD_DisconnectCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + hpcd->Instance->GOTGINT |= RegVal; + } + } +} + + +/** + * @brief Handles PCD Wakeup interrupt request. + * @param hpcd PCD handle + * @retval HAL status + */ +void HAL_PCD_WKUP_IRQHandler(PCD_HandleTypeDef *hpcd) +{ +#if defined (USB_OTG_FS) + USB_OTG_GlobalTypeDef *USBx; + USBx = hpcd->Instance; + + if (USBx == USB_OTG_FS) + { + /* Clear EXTI pending Bit */ + __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); + } + else +#endif /* defined (USB_OTG_FS) */ + { + /* Clear EXTI pending Bit */ + __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); + } +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResetCallback could be implemented in the user file + */ +} + +/** + * @brief Suspend event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callback. + * @param hpcd PCD handle + * @retval None + */ +__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCD_DisconnectCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + (void)USB_DevConnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) +{ + __HAL_LOCK(hpcd); + (void)USB_DevDisconnect(hpcd->Instance); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) +{ + __HAL_LOCK(hpcd); + hpcd->USB_Address = address; + (void)USB_SetDevAddress(hpcd->Instance, address); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) +{ + HAL_StatusTypeDef ret = HAL_OK; + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->num = ep_addr & EP_ADDR_MSK; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; + ep->type = ep_type; + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __HAL_LOCK(hpcd); + (void)USB_ActivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return ret; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_DeactivateEndpoint(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + return HAL_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + + return HAL_OK; +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); + + return HAL_OK; +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; + } + + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + + (void)USB_EPSetStall(hpcd->Instance, ep); + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + { + return HAL_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + __HAL_LOCK(hpcd); + (void)USB_EPClearStall(hpcd->Instance, ep); + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + __HAL_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FlushRxFifo(hpcd->Instance); + } + + __HAL_UNLOCK(hpcd); + + return HAL_OK; +} + +/** + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_ActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @brief De-activate remote wakeup signalling. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) +{ + return (USB_DeActivateRemoteWakeup(hpcd->Instance)); +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval HAL state + */ +PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) +{ + return hpcd->State; +} + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL &= ~(0x7U << 4); + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + USB_OTG_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return HAL_ERROR; + } + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, + (uint8_t)hpcd->Init.dma_enable); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_EPTypeDef *ep; + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if (hpcd->Init.dma_enable == 1U) + { + if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + } + else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + ep = &hpcd->OUT_ep[epnum]; + + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + + if (epnum == 0U) + { + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + /* ... */ + } + } + else + { + if (gSNPSiD == USB_OTG_CORE_ID_310A) + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + else + { + if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + else + { + if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); + } + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval HAL status + */ +static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) +{ + const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && + ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) + { + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); + } + + /* Inform the upper layer that a setup packet is available */ +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->SetupStageCallback(hpcd); +#else + HAL_PCD_SetupStageCallback(hpcd); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + + if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) + { + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c index b9eb434f..2aa9d96b 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pcd_ex.c @@ -1,204 +1,204 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pcd_ex.c - * @author MCD Application Team - * @brief PCD Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Extended features functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup PCDEx PCDEx - * @brief PCD Extended HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ - -/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Update FIFO configuration - -@endverbatim - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** - * @brief Set Tx FIFO - * @param hpcd PCD handle - * @param fifo The number of Tx fifo - * @param size Fifo size - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) -{ - uint8_t i; - uint32_t Tx_Offset; - - /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: - case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txm can use the space allocated for Txn. - case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top - of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. - When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - - Tx_Offset = hpcd->Instance->GRXFSIZ; - - if (fifo == 0U) - { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; - } - else - { - Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (i = 0U; i < (fifo - 1U); i++) - { - Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); - } - - /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; - } - - return HAL_OK; -} - -/** - * @brief Set Rx FIFO - * @param hpcd PCD handle - * @param size Size of Rx fifo - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) -{ - hpcd->Instance->GRXFSIZ = size; - - return HAL_OK; -} - -/** - * @brief Activate LPM feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = 1U; - hpcd->LPM_State = LPM_L0; - USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -/** - * @brief Deactivate LPM feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = 0U; - USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -/** - * @brief Send LPM message to user layer callback. - * @param hpcd PCD handle - * @param msg LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ -} - -/** - * @brief Send BatteryCharging message to user layer callback. - * @param hpcd PCD handle - * @param msg LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_BCD_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_pcd_ex.c + * @author MCD Application Team + * @brief PCD Extended HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup PCDEx PCDEx + * @brief PCD Extended HAL module driver + * @{ + */ + +#ifdef HAL_PCD_MODULE_ENABLED + +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update FIFO configuration + +@endverbatim + * @{ + */ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/** + * @brief Set Tx FIFO + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = hpcd->Instance->GRXFSIZ; + + if (fifo == 0U) + { + hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + + return HAL_OK; +} + +/** + * @brief Set Rx FIFO + * @param hpcd PCD handle + * @param size Size of Rx fifo + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) +{ + hpcd->Instance->GRXFSIZ = size; + + return HAL_OK; +} + +/** + * @brief Activate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 1U; + hpcd->LPM_State = LPM_L0; + USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +/** + * @brief Deactivate LPM feature. + * @param hpcd PCD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + + hpcd->lpm_active = 0U; + USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; + USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); + + return HAL_OK; +} + +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @brief Send LPM message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_LPM_Callback could be implemented in the user file + */ +} + +/** + * @brief Send BatteryCharging message to user layer callback. + * @param hpcd PCD handle + * @param msg LPM message + * @retval HAL status + */ +__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(msg); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_PCDEx_BCD_Callback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* HAL_PCD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c index eb548e06..bf35d046 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr.c @@ -1,600 +1,600 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup PWR_Private_Constants - * @{ - */ - -/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask - * @{ - */ -#define PVD_MODE_IT ((uint32_t)0x00010000U) -#define PVD_MODE_EVT ((uint32_t)0x00020000U) -#define PVD_RISING_EDGE ((uint32_t)0x00000001U) -#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) -/** - * @} - */ - -/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask - * @{ - */ -#define PWR_EWUP_MASK ((uint32_t)0x00003F00) -/** - * @} - */ - -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. - * @retval None - */ -void HAL_PWR_DeInit(void) -{ - __HAL_RCC_PWR_FORCE_RESET(); - __HAL_RCC_PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - /* Enable access to RTC and backup registers */ - SET_BIT(PWR->CR1, PWR_CR1_DBP); -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers and backup SRAM). - * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - /* Disable access to RTC and backup registers */ - CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); -} - -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions - * -@verbatim - - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - - *** PVD configuration *** - ========================= - [..] - (+) The PVD is used to monitor the VDD power supply by comparing it to a - threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). - (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower - than the PVD threshold. This event is internally connected to the EXTI - line16 and can generate an interrupt if enabled. This is done through - __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. - (+) The PVD is stopped in Standby mode. - - *** Wake-up pin configuration *** - ================================ - [..] - (+) Wake-up pin is used to wake up the system from Standby mode. This pin is - forced in input pull-down configuration and is active on rising edges. - (+) There are up to 6 Wake-up pin in the STM32F7 devices family - - *** Low Power modes configuration *** - ===================================== - [..] - The devices feature 3 low-power modes: - (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running. - (+) Stop mode: all clocks are stopped, regulator running, regulator - in low power mode - (+) Standby mode: 1.2V domain powered off. - - *** Sleep mode *** - ================== - [..] - (+) Entry: - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) - functions with - (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - - -@@- The Regulator parameter is not used for the STM32F7 family - and is kept as parameter just to maintain compatibility with the - lower power families (STM32L). - (+) Exit: - Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. - - *** Stop mode *** - ================= - [..] - In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, - and the HSE RC oscillators are disabled. Internal SRAM and register contents - are preserved. - The voltage regulator can be configured either in normal or low-power mode. - To minimize the consumption In Stop mode, FLASH can be powered off before - entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. - It can be switched on again by software after exiting the Stop mode using - the HAL_PWREx_DisableFlashPowerDown() function. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) - function with: - (++) Main regulator ON. - (++) Low Power regulator ON. - (+) Exit: - Any EXTI Line (Internal or External) configured in Interrupt/Event mode. - - *** Standby mode *** - ==================== - [..] - (+) - The Standby mode allows to achieve the lowest power consumption. It is based - on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. - The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and - the HSE oscillator are also switched off. SRAM and register contents are lost - except for the RTC registers, RTC backup registers, backup SRAM and Standby - circuitry. - - The voltage regulator is OFF. - - (++) Entry: - (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. - (++) Exit: - (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC - wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. - - *** Auto-wakeup (AWU) from low-power mode *** - ============================================= - [..] - - (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC - Wakeup event, a tamper event or a time-stamp event, without depending on - an external interrupt (Auto-wakeup mode). - - (+) RTC auto-wakeup (AWU) from the Stop and Standby modes - - (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to - configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. - - (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it - is necessary to configure the RTC to detect the tamper or time stamp event using the - HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. - - (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to - configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. - -@endverbatim - * @{ - */ - -/** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for - * more details about the voltage threshold corresponding to each - * detection level. - * @retval None - */ -void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) -{ - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); - - /* Set PLS[7:5] bits according to PVDLevel value */ - MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); - - /* Clear any previous config. Keep it clear if no event or IT mode is selected */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure interrupt mode */ - if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure event mode */ - if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the edge */ - if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } -} - -/** - * @brief Enables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_EnablePVD(void) -{ - /* Enable the power voltage detector */ - SET_BIT(PWR->CR1, PWR_CR1_PVDE); -} - -/** - * @brief Disables the Power Voltage Detector(PVD). - * @retval None - */ -void HAL_PWR_DisablePVD(void) -{ - /* Disable the power voltage detector */ - CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); -} - -/** - * @brief Enable the WakeUp PINx functionality. - * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. - * This parameter can be one of the following legacy values, which sets the default polarity: - * detection on high level (rising edge): - * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 - * or one of the following value where the user can explicitly states the enabled pin and - * the chosen polarity - * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW - * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW - * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW - * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW - * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW - * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW - * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. - * @retval None - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); - - /* Enable wake-up pin */ - SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity)); - - /* Specifies the Wake-Up pin polarity for the event detection - (rising or falling edge) */ - MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06)); -} - -/** - * @brief Disables the WakeUp PINx functionality. - * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. - * This parameter can be one of the following values: - * @arg PWR_WAKEUP_PIN1 - * @arg PWR_WAKEUP_PIN2 - * @arg PWR_WAKEUP_PIN3 - * @arg PWR_WAKEUP_PIN4 - * @arg PWR_WAKEUP_PIN5 - * @arg PWR_WAKEUP_PIN6 - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) -{ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); - - CLEAR_BIT(PWR->CSR2, WakeUpPinx); -} - -/** - * @brief Enters Sleep mode. - * - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * - * @note In Sleep mode, the systick is stopped to avoid exit from this mode with - * systick interrupt when used as time base for Timeout - * - * @param Regulator Specifies the regulator state in SLEEP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON - * @note This parameter is not used for the STM32F7 family and is kept as parameter - * just to maintain compatibility with the lower power families. - * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(Regulator); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Ensure that all instructions done before entering SLEEP mode */ - __DSB(); - __ISB(); - - /* Select SLEEP mode entry -------------------------------------------------*/ - if(SLEEPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } -} - -/** - * @brief Enters Stop mode. - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * @param Regulator Specifies the regulator state in Stop mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON - * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON - * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction - * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction - * @retval None - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Select the regulator state in Stop mode ---------------------------------*/ - tmpreg = PWR->CR1; - /* Clear PDDS and LPDS bits */ - tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS); - - /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */ - tmpreg |= Regulator; - - /* Store the new value */ - PWR->CR1 = tmpreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Ensure that all instructions done before entering STOP mode */ - __DSB(); - __ISB(); - - /* Select Stop mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); -} - -/** - * @brief Enters Standby mode. - * @note In Standby mode, all I/O pins are high impedance except for: - * - Reset pad (still available) - * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC - * Alarm out, or RTC clock calibration out. - * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. - * - WKUP pins if enabled. - * @retval None - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select Standby mode */ - PWR->CR1 |= PWR_CR1_PDDS; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* This option is used to ensure that store operations are completed */ -#if defined ( __CC_ARM) - __force_stores(); -#endif - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_IRQHandler(). - * @retval None - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - /* Check PWR Exti flag */ - if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PWR Exti pending bit */ - __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); - } -} - -/** - * @brief PWR PVD interrupt callback - * @retval None - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback could be implemented in the user file - */ -} - -/** - * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run only on - * interruptions handling. - * @retval None - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor - * re-enters SLEEP mode when an interruption handling is over. - * @retval None - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enables CORTEX M4 SEVONPEND bit. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Disables CORTEX M4 SEVONPEND bit. - * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes - * WFE to wake up when an interrupt moves from inactive to pended. - * @retval None - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr.c + * @author MCD Application Team + * @brief PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWR PWR + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWR_Private_Constants + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT ((uint32_t)0x00010000U) +#define PVD_MODE_EVT ((uint32_t)0x00020000U) +#define PVD_RISING_EDGE ((uint32_t)0x00000001U) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002U) +/** + * @} + */ + +/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask + * @{ + */ +#define PWR_EWUP_MASK ((uint32_t)0x00003F00) +/** + * @} + */ + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers and backup SRAM) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + +@endverbatim + * @{ + */ + +/** + * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. + * @retval None + */ +void HAL_PWR_DeInit(void) +{ + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); +} + +/** + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + SET_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @brief Disables access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); +} + +/** + * @} + */ + +/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions + * @brief Low Power modes configuration functions + * +@verbatim + + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + + *** PVD configuration *** + ========================= + [..] + (+) The PVD is used to monitor the VDD power supply by comparing it to a + threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). + (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower + than the PVD threshold. This event is internally connected to the EXTI + line16 and can generate an interrupt if enabled. This is done through + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. + (+) The PVD is stopped in Standby mode. + + *** Wake-up pin configuration *** + ================================ + [..] + (+) Wake-up pin is used to wake up the system from Standby mode. This pin is + forced in input pull-down configuration and is active on rising edges. + (+) There are up to 6 Wake-up pin in the STM32F7 devices family + + *** Low Power modes configuration *** + ===================================== + [..] + The devices feature 3 low-power modes: + (+) Sleep mode: Cortex-M7 core stopped, peripherals kept running. + (+) Stop mode: all clocks are stopped, regulator running, regulator + in low power mode + (+) Standby mode: 1.2V domain powered off. + + *** Sleep mode *** + ================== + [..] + (+) Entry: + The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) + functions with + (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + + -@@- The Regulator parameter is not used for the STM32F7 family + and is kept as parameter just to maintain compatibility with the + lower power families (STM32L). + (+) Exit: + Any peripheral interrupt acknowledged by the nested vectored interrupt + controller (NVIC) can wake up the device from Sleep mode. + + *** Stop mode *** + ================= + [..] + In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, + and the HSE RC oscillators are disabled. Internal SRAM and register contents + are preserved. + The voltage regulator can be configured either in normal or low-power mode. + To minimize the consumption In Stop mode, FLASH can be powered off before + entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. + It can be switched on again by software after exiting the Stop mode using + the HAL_PWREx_DisableFlashPowerDown() function. + + (+) Entry: + The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) + function with: + (++) Main regulator ON. + (++) Low Power regulator ON. + (+) Exit: + Any EXTI Line (Internal or External) configured in Interrupt/Event mode. + + *** Standby mode *** + ==================== + [..] + (+) + The Standby mode allows to achieve the lowest power consumption. It is based + on the Cortex-M7 deep sleep mode, with the voltage regulator disabled. + The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and + the HSE oscillator are also switched off. SRAM and register contents are lost + except for the RTC registers, RTC backup registers, backup SRAM and Standby + circuitry. + + The voltage regulator is OFF. + + (++) Entry: + (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. + (++) Exit: + (+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC + wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset. + + *** Auto-wakeup (AWU) from low-power mode *** + ============================================= + [..] + + (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC + Wakeup event, a tamper event or a time-stamp event, without depending on + an external interrupt (Auto-wakeup mode). + + (+) RTC auto-wakeup (AWU) from the Stop and Standby modes + + (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to + configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. + + (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it + is necessary to configure the RTC to detect the tamper or time stamp event using the + HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. + + (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to + configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function. + +@endverbatim + * @{ + */ + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +{ + /* Check the parameters */ + assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); + + /* Set PLS[7:5] bits according to PVDLevel value */ + MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) + { + __HAL_PWR_PVD_EXTI_ENABLE_IT(); + } + + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) + { + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); + } + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + } +} + +/** + * @brief Enables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_EnablePVD(void) +{ + /* Enable the power voltage detector */ + SET_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Disables the Power Voltage Detector(PVD). + * @retval None + */ +void HAL_PWR_DisablePVD(void) +{ + /* Disable the power voltage detector */ + CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); +} + +/** + * @brief Enable the WakeUp PINx functionality. + * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable. + * This parameter can be one of the following legacy values, which sets the default polarity: + * detection on high level (rising edge): + * @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6 + * or one of the following value where the user can explicitly states the enabled pin and + * the chosen polarity + * @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW + * @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW + * @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW + * @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW + * @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW + * @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW + * @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent. + * @retval None + */ +void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); + + /* Enable wake-up pin */ + SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity)); + + /* Specifies the Wake-Up pin polarity for the event detection + (rising or falling edge) */ + MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06)); +} + +/** + * @brief Disables the WakeUp PINx functionality. + * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. + * This parameter can be one of the following values: + * @arg PWR_WAKEUP_PIN1 + * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3 + * @arg PWR_WAKEUP_PIN4 + * @arg PWR_WAKEUP_PIN5 + * @arg PWR_WAKEUP_PIN6 + * @retval None + */ +void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) +{ + assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); + + CLEAR_BIT(PWR->CSR2, WakeUpPinx); +} + +/** + * @brief Enters Sleep mode. + * + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * + * @note In Sleep mode, the systick is stopped to avoid exit from this mode with + * systick interrupt when used as time base for Timeout + * + * @param Regulator Specifies the regulator state in SLEEP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON + * @note This parameter is not used for the STM32F7 family and is kept as parameter + * just to maintain compatibility with the lower power families. + * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + + /* Ensure that all instructions done before entering SLEEP mode */ + __DSB(); + __ISB(); + + /* Select SLEEP mode entry -------------------------------------------------*/ + if(SLEEPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters Stop mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param Regulator Specifies the regulator state in Stop mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON + * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON + * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction + * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Select the regulator state in Stop mode ---------------------------------*/ + tmpreg = PWR->CR1; + /* Clear PDDS and LPDS bits */ + tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS); + + /* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */ + tmpreg |= Regulator; + + /* Store the new value */ + PWR->CR1 = tmpreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Ensure that all instructions done before entering STOP mode */ + __DSB(); + __ISB(); + + /* Select Stop mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_STOPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); +} + +/** + * @brief Enters Standby mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC + * Alarm out, or RTC clock calibration out. + * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. + * - WKUP pins if enabled. + * @retval None + */ +void HAL_PWR_EnterSTANDBYMode(void) +{ + /* Select Standby mode */ + PWR->CR1 |= PWR_CR1_PDDS; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* This option is used to ensure that store operations are completed */ +#if defined ( __CC_ARM) + __force_stores(); +#endif + /* Request Wait For Interrupt */ + __WFI(); +} + +/** + * @brief This function handles the PWR PVD interrupt request. + * @note This API should be called under the PVD_IRQHandler(). + * @retval None + */ +void HAL_PWR_PVD_IRQHandler(void) +{ + /* Check PWR Exti flag */ + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) + { + /* PWR PVD interrupt user callback */ + HAL_PWR_PVDCallback(); + + /* Clear PWR Exti pending bit */ + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); + } +} + +/** + * @brief PWR PVD interrupt callback + * @retval None + */ +__weak void HAL_PWR_PVDCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_PWR_PVDCallback could be implemented in the user file + */ +} + +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enables CORTEX M4 SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Disables CORTEX M4 SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c index f426aaa2..3e3a0168 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c @@ -1,552 +1,552 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_pwr_ex.c - * @author MCD Application Team - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of PWR extension peripheral: - * + Peripheral Extended features functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWR HAL module driver - * @{ - */ - -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup PWREx_Private_Constants - * @{ - */ -#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 -#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 -#define PWR_BKPREG_TIMEOUT_VALUE 1000 -#define PWR_VOSRDY_TIMEOUT_VALUE 1000 -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup PWREx_Exported_Functions PWREx Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions - * @brief Peripheral Extended features functions - * -@verbatim - - =============================================================================== - ##### Peripheral extended features functions ##### - =============================================================================== - - *** Main and Backup Regulators configuration *** - ================================================ - [..] - (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from - the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is - retained even in Standby or VBAT mode when the low power backup regulator - is enabled. It can be considered as an internal EEPROM when VBAT is - always present. You can use the HAL_PWREx_EnableBkUpReg() function to - enable the low power backup regulator. - - (+) When the backup domain is supplied by VDD (analog switch connected to VDD) - the backup SRAM is powered from VDD which replaces the VBAT power supply to - save battery life. - - (+) The backup SRAM is not mass erased by a tamper event. It is read - protected to prevent confidential data, such as cryptographic private - key, from being accessed. The backup SRAM can be erased only through - the Flash interface when a protection level change from level 1 to - level 0 is requested. - -@- Refer to the description of Read protection (RDP) in the Flash - programming manual. - - (+) The main internal regulator can be configured to have a tradeoff between - performance and power consumption when the device does not operate at - the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() - macro which configure VOS bit in PWR_CR register - - Refer to the product datasheets for more details. - - *** FLASH Power Down configuration **** - ======================================= - [..] - (+) By setting the FPDS bit in the PWR_CR register by using the - HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power - down mode when the device enters Stop mode. When the Flash memory - is in power down mode, an additional startup delay is incurred when - waking up from Stop mode. - - *** Over-Drive and Under-Drive configuration **** - ================================================= - [..] - (+) In Run mode: the main regulator has 2 operating modes available: - (++) Normal mode: The CPU and core logic operate at maximum frequency at a given - voltage scaling (scale 1, scale 2 or scale 3) - (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a - higher frequency than the normal mode for a given voltage scaling (scale 1, - scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and - disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow - the sequence described in Reference manual. - - (+) In Stop mode: the main regulator or low power regulator supplies a low power - voltage to the 1.2V domain, thus preserving the content of registers - and internal SRAM. 2 operating modes are available: - (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only - available when the main regulator or the low power regulator is used in Scale 3 or - low voltage mode. - (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only - available when the main regulator or the low power regulator is in low voltage mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enables the Backup Regulator. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) -{ - uint32_t tickstart = 0; - - /* Enable Backup regulator */ - PWR->CSR1 |= PWR_CSR1_BRE; - - /* Workaround for the following hardware bug: */ - /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ - PWR->CSR1 |= PWR_CSR1_EIWUP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till Backup regulator ready flag is set */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) - { - if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Disables the Backup Regulator. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) -{ - uint32_t tickstart = 0; - - /* Disable Backup regulator */ - PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); - - /* Workaround for the following hardware bug: */ - /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ - PWR->CSR1 |= PWR_CSR1_EIWUP; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till Backup regulator ready flag is set */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) - { - if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Enables the Flash Power Down in Stop mode. - * @retval None - */ -void HAL_PWREx_EnableFlashPowerDown(void) -{ - /* Enable the Flash Power Down */ - PWR->CR1 |= PWR_CR1_FPDS; -} - -/** - * @brief Disables the Flash Power Down in Stop mode. - * @retval None - */ -void HAL_PWREx_DisableFlashPowerDown(void) -{ - /* Disable the Flash Power Down */ - PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS); -} - -/** - * @brief Enables Main Regulator low voltage mode. - * @retval None - */ -void HAL_PWREx_EnableMainRegulatorLowVoltage(void) -{ - /* Enable Main regulator low voltage */ - PWR->CR1 |= PWR_CR1_MRUDS; -} - -/** - * @brief Disables Main Regulator low voltage mode. - * @retval None - */ -void HAL_PWREx_DisableMainRegulatorLowVoltage(void) -{ - /* Disable Main regulator low voltage */ - PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS); -} - -/** - * @brief Enables Low Power Regulator low voltage mode. - * @retval None - */ -void HAL_PWREx_EnableLowRegulatorLowVoltage(void) -{ - /* Enable low power regulator */ - PWR->CR1 |= PWR_CR1_LPUDS; -} - -/** - * @brief Disables Low Power Regulator low voltage mode. - * @retval None - */ -void HAL_PWREx_DisableLowRegulatorLowVoltage(void) -{ - /* Disable low power regulator */ - PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS); -} - -/** - * @brief Activates the Over-Drive mode. - * @note This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) -{ - uint32_t tickstart = 0; - - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable the Over-drive to extend the clock frequency to 216 MHz */ - __HAL_PWR_OVERDRIVE_ENABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Enable the Over-drive switch */ - __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Deactivates the Over-Drive mode. - * @note This mode allows the CPU and the core logic to operate at a higher frequency - * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). - * @note It is recommended to enter or exit Over-drive mode when the application is not running - * critical tasks and when the system clock source is either HSI or HSE. - * During the Over-drive switch activation, no peripheral clocks should be enabled. - * The peripheral clocks must be enabled once the Over-drive mode is activated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) -{ - uint32_t tickstart = 0; - - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Disable the Over-drive switch */ - __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Disable the Over-drive */ - __HAL_PWR_OVERDRIVE_DISABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Enters in Under-Drive STOP mode. - * - * @note This mode can be selected only when the Under-Drive is already active - * - * @note This mode is enabled only with STOP low power mode. - * In this mode, the 1.2V domain is preserved in reduced leakage mode. This - * mode is only available when the main regulator or the low power regulator - * is in low voltage mode - * - * @note If the Under-drive mode was enabled, it is automatically disabled after - * exiting Stop mode. - * When the voltage regulator operates in Under-drive mode, an additional - * startup delay is induced when waking up from Stop mode. - * - * @note In Stop mode, all I/O pins keep the same state as in Run mode. - * - * @note When exiting Stop mode by issuing an interrupt or a wakeup event, - * the HSI RC oscillator is selected as system clock. - * - * @note When the voltage regulator operates in low power mode, an additional - * startup delay is incurred when waking up from Stop mode. - * By keeping the internal regulator ON during Stop mode, the consumption - * is higher although the startup time is reduced. - * - * @param Regulator specifies the regulator state in STOP mode. - * This parameter can be one of the following values: - * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode - * and Flash memory in power-down when the device is in Stop under-drive mode - * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. - * This parameter can be one of the following values: - * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction - * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction - * @retval None - */ -HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) -{ - uint32_t tempreg = 0; - uint32_t tickstart = 0; - - /* Check the parameters */ - assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - /* Enable the Under-drive Mode ---------------------------------------------*/ - /* Clear Under-drive flag */ - __HAL_PWR_CLEAR_ODRUDR_FLAG(); - - /* Enable the Under-drive */ - __HAL_PWR_UNDERDRIVE_ENABLE(); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for UnderDrive mode is ready */ - while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) - { - if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Select the regulator state in STOP mode ---------------------------------*/ - tempreg = PWR->CR1; - /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ - tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS); - - /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ - tempreg |= Regulator; - - /* Store the new value */ - PWR->CR1 = tempreg; - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - - /* Select STOP mode entry --------------------------------------------------*/ - if(STOPEntry == PWR_SLEEPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __WFE(); - } - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); - - return HAL_OK; -} - -/** - * @brief Returns Voltage Scaling Range. - * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or - * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1 - */ -uint32_t HAL_PWREx_GetVoltageRange(void) -{ - return (PWR->CR1 & PWR_CR1_VOS); -} - -/** - * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling specifies the regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * This parameter can be one of the following values: - * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, - * typical output voltage at 1.4 V, - * system frequency up to 216 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, - * typical output voltage at 1.2 V, - * system frequency up to 180 MHz. - * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode, - * typical output voltage at 1.00 V, - * system frequency up to 151 MHz. - * @note To update the system clock frequency(SYSCLK): - * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). - * - Call the HAL_RCC_OscConfig() to configure the PLL. - * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. - * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). - * @note The scale can be modified only when the HSI or HSE clock source is selected - * as system clock source, otherwise the API returns HAL_ERROR. - * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits - * value in the PWR_CR1 register are not taken in account. - * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. - * @note The new voltage scale is active only when the PLL is ON. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) -{ - uint32_t tickstart = 0; - - assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); - - /* Enable Power ctrl clock */ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - { - /* Disable the main PLL */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - /* Wait till PLL is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set Range */ - __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); - - /* Enable the main PLL */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) - { - if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_pwr_ex.c + * @author MCD Application Team + * @brief Extended PWR HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of PWR extension peripheral: + * + Peripheral Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup PWREx PWREx + * @brief PWR HAL module driver + * @{ + */ + +#ifdef HAL_PWR_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup PWREx_Private_Constants + * @{ + */ +#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000 +#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000 +#define PWR_BKPREG_TIMEOUT_VALUE 1000 +#define PWR_VOSRDY_TIMEOUT_VALUE 1000 +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup PWREx_Exported_Functions PWREx Exported Functions + * @{ + */ + +/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions + * @brief Peripheral Extended features functions + * +@verbatim + + =============================================================================== + ##### Peripheral extended features functions ##### + =============================================================================== + + *** Main and Backup Regulators configuration *** + ================================================ + [..] + (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from + the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is + retained even in Standby or VBAT mode when the low power backup regulator + is enabled. It can be considered as an internal EEPROM when VBAT is + always present. You can use the HAL_PWREx_EnableBkUpReg() function to + enable the low power backup regulator. + + (+) When the backup domain is supplied by VDD (analog switch connected to VDD) + the backup SRAM is powered from VDD which replaces the VBAT power supply to + save battery life. + + (+) The backup SRAM is not mass erased by a tamper event. It is read + protected to prevent confidential data, such as cryptographic private + key, from being accessed. The backup SRAM can be erased only through + the Flash interface when a protection level change from level 1 to + level 0 is requested. + -@- Refer to the description of Read protection (RDP) in the Flash + programming manual. + + (+) The main internal regulator can be configured to have a tradeoff between + performance and power consumption when the device does not operate at + the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() + macro which configure VOS bit in PWR_CR register + + Refer to the product datasheets for more details. + + *** FLASH Power Down configuration **** + ======================================= + [..] + (+) By setting the FPDS bit in the PWR_CR register by using the + HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power + down mode when the device enters Stop mode. When the Flash memory + is in power down mode, an additional startup delay is incurred when + waking up from Stop mode. + + *** Over-Drive and Under-Drive configuration **** + ================================================= + [..] + (+) In Run mode: the main regulator has 2 operating modes available: + (++) Normal mode: The CPU and core logic operate at maximum frequency at a given + voltage scaling (scale 1, scale 2 or scale 3) + (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a + higher frequency than the normal mode for a given voltage scaling (scale 1, + scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and + disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow + the sequence described in Reference manual. + + (+) In Stop mode: the main regulator or low power regulator supplies a low power + voltage to the 1.2V domain, thus preserving the content of registers + and internal SRAM. 2 operating modes are available: + (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only + available when the main regulator or the low power regulator is used in Scale 3 or + low voltage mode. + (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only + available when the main regulator or the low power regulator is in low voltage mode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) +{ + uint32_t tickstart = 0; + + /* Enable Backup regulator */ + PWR->CSR1 |= PWR_CSR1_BRE; + + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Disables the Backup Regulator. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) +{ + uint32_t tickstart = 0; + + /* Disable Backup regulator */ + PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE); + + /* Workaround for the following hardware bug: */ + /* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */ + PWR->CSR1 |= PWR_CSR1_EIWUP; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait till Backup regulator ready flag is set */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) + { + if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Enables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_EnableFlashPowerDown(void) +{ + /* Enable the Flash Power Down */ + PWR->CR1 |= PWR_CR1_FPDS; +} + +/** + * @brief Disables the Flash Power Down in Stop mode. + * @retval None + */ +void HAL_PWREx_DisableFlashPowerDown(void) +{ + /* Disable the Flash Power Down */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS); +} + +/** + * @brief Enables Main Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_EnableMainRegulatorLowVoltage(void) +{ + /* Enable Main regulator low voltage */ + PWR->CR1 |= PWR_CR1_MRUDS; +} + +/** + * @brief Disables Main Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_DisableMainRegulatorLowVoltage(void) +{ + /* Disable Main regulator low voltage */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS); +} + +/** + * @brief Enables Low Power Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_EnableLowRegulatorLowVoltage(void) +{ + /* Enable low power regulator */ + PWR->CR1 |= PWR_CR1_LPUDS; +} + +/** + * @brief Disables Low Power Regulator low voltage mode. + * @retval None + */ +void HAL_PWREx_DisableLowRegulatorLowVoltage(void) +{ + /* Disable low power regulator */ + PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS); +} + +/** + * @brief Activates the Over-Drive mode. + * @note This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) +{ + uint32_t tickstart = 0; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable the Over-drive to extend the clock frequency to 216 MHz */ + __HAL_PWR_OVERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Enable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Deactivates the Over-Drive mode. + * @note This mode allows the CPU and the core logic to operate at a higher frequency + * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). + * @note It is recommended to enter or exit Over-drive mode when the application is not running + * critical tasks and when the system clock source is either HSI or HSE. + * During the Over-drive switch activation, no peripheral clocks should be enabled. + * The peripheral clocks must be enabled once the Over-drive mode is activated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) +{ + uint32_t tickstart = 0; + + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Disable the Over-drive switch */ + __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Disable the Over-drive */ + __HAL_PWR_OVERDRIVE_DISABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enters in Under-Drive STOP mode. + * + * @note This mode can be selected only when the Under-Drive is already active + * + * @note This mode is enabled only with STOP low power mode. + * In this mode, the 1.2V domain is preserved in reduced leakage mode. This + * mode is only available when the main regulator or the low power regulator + * is in low voltage mode + * + * @note If the Under-drive mode was enabled, it is automatically disabled after + * exiting Stop mode. + * When the voltage regulator operates in Under-drive mode, an additional + * startup delay is induced when waking up from Stop mode. + * + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * + * @param Regulator specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode + * and Flash memory in power-down when the device is in Stop under-drive mode + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction + * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction + * @retval None + */ +HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + uint32_t tempreg = 0; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); + assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + /* Enable the Under-drive Mode ---------------------------------------------*/ + /* Clear Under-drive flag */ + __HAL_PWR_CLEAR_ODRUDR_FLAG(); + + /* Enable the Under-drive */ + __HAL_PWR_UNDERDRIVE_ENABLE(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for UnderDrive mode is ready */ + while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY)) + { + if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Select the regulator state in STOP mode ---------------------------------*/ + tempreg = PWR->CR1; + /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ + tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS); + + /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ + tempreg |= Regulator; + + /* Store the new value */ + PWR->CR1 = tempreg; + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Select STOP mode entry --------------------------------------------------*/ + if(STOPEntry == PWR_SLEEPENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + + return HAL_OK; +} + +/** + * @brief Returns Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or + * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1 + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + return (PWR->CR1 & PWR_CR1_VOS); +} + +/** + * @brief Configures the main internal regulator output voltage. + * @param VoltageScaling specifies the regulator output voltage to achieve + * a tradeoff between performance and power consumption. + * This parameter can be one of the following values: + * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, + * typical output voltage at 1.4 V, + * system frequency up to 216 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, + * typical output voltage at 1.2 V, + * system frequency up to 180 MHz. + * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode, + * typical output voltage at 1.00 V, + * system frequency up to 151 MHz. + * @note To update the system clock frequency(SYSCLK): + * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). + * - Call the HAL_RCC_OscConfig() to configure the PLL. + * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. + * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). + * @note The scale can be modified only when the HSI or HSE clock source is selected + * as system clock source, otherwise the API returns HAL_ERROR. + * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits + * value in the PWR_CR1 register are not taken in account. + * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. + * @note The new voltage scale is active only when the PLL is ON. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) +{ + uint32_t tickstart = 0; + + assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling)); + + /* Enable Power ctrl clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Check if the PLL is used as system clock or not */ + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + { + /* Disable the main PLL */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set Range */ + __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); + + /* Enable the main PLL */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + /* Wait till PLL is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) + { + if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_PWR_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c deleted file mode 100644 index f4d28f77..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c +++ /dev/null @@ -1,2840 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_qspi.c - * @author MCD Application Team - * @brief QSPI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the QuadSPI interface (QSPI). - * + Initialization and de-initialization functions - * + Indirect functional mode management - * + Memory-mapped functional mode management - * + Auto-polling functional mode management - * + Interrupts and flags management - * + DMA channel configuration for indirect functional mode - * + Errors management and abort functionality - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - *** Initialization *** - ====================== - [..] - (#) As prerequisite, fill in the HAL_QSPI_MspInit() : - (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE(). - (++) Reset QuadSPI Peripheral with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET(). - (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). - (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init(). - (++) If interrupt mode is used, enable and configure QuadSPI global - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel - with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), - link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure - DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (#) Configure the flash size, the clock prescaler, the fifo threshold, the - clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function. - - *** Indirect functional mode *** - ================================ - [..] - (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT() - functions : - (++) Instruction phase : the mode used and if present the instruction opcode. - (++) Address phase : the mode used and if present the size and the address value. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate - bytes values. - (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). - (++) Data phase : the mode used and if present the number of bytes. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay - if activated. - (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. - (#) If no data is required for the command, it is sent directly to the memory : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete. - (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or - HAL_QSPI_Transmit_IT() after the command configuration : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold - is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and - HAL_QSPI_TxCpltCallback() will be called when the transfer is complete. - (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or - HAL_QSPI_Receive_IT() after the command configuration : - (++) In polling mode, the output of the function is done when the transfer is complete. - (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold - is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. - (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and - HAL_QSPI_RxCpltCallback() will be called when the transfer is complete. - - *** Auto-polling functional mode *** - ==================================== - [..] - (#) Configure the command sequence and the auto-polling functional mode using the - HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions : - (++) Instruction phase : the mode used and if present the instruction opcode. - (++) Address phase : the mode used and if present the size and the address value. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate - bytes values. - (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). - (++) Data phase : the mode used. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay - if activated. - (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. - (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), - the polling interval and the automatic stop activation. - (#) After the configuration : - (++) In polling mode, the output of the function is done when the status match is reached. The - automatic stop is activated to avoid an infinite loop. - (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached. - - *** Memory-mapped functional mode *** - ===================================== - [..] - (#) Configure the command sequence and the memory-mapped functional mode using the - HAL_QSPI_MemoryMapped() functions : - (++) Instruction phase : the mode used and if present the instruction opcode. - (++) Address phase : the mode used and the size. - (++) Alternate-bytes phase : the mode used and if present the size and the alternate - bytes values. - (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). - (++) Data phase : the mode used. - (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay - if activated. - (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. - (++) The timeout activation and the timeout period. - (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on - the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires. - - *** Errors management and abort functionality *** - ================================================= - [..] - (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and - flushes the fifo : - (++) In polling mode, the output of the function is done when the transfer - complete bit is set and the busy bit cleared. - (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when - the transfer complete bit is set. - - *** Control functions *** - ========================= - [..] - (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver. - (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver. - (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP. - (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold - (#) HAL_QSPI_SetFlashID() function configures the index of the flash memory to be accessed. - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - Use Functions HAL_QSPI_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) FifoThresholdCallback : callback when the fifo threshold is reached. - (+) CmdCpltCallback : callback when a command without data is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. - (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. - (+) StatusMatchCallback : callback when a status match occurs. - (+) TimeOutCallback : callback when the timeout perioed expires. - (+) MspInitCallback : QSPI MspInit. - (+) MspDeInitCallback : QSPI MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. It allows to reset following callbacks: - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) FifoThresholdCallback : callback when the fifo threshold is reached. - (+) CmdCpltCallback : callback when a command without data is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. - (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. - (+) StatusMatchCallback : callback when a status match occurs. - (+) TimeOutCallback : callback when the timeout perioed expires. - (+) MspInitCallback : QSPI MspInit. - (+) MspDeInitCallback : QSPI MspDeInit. - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the HAL_QSPI_Init - and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit - or HAL_QSPI_Init function. - - When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. - - *** Workarounds linked to Silicon Limitation *** - ==================================================== - [..] - (#) Workarounds Implemented inside HAL Driver - (++) Extra data written in the FIFO at the end of a read transfer - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -#if defined(QUADSPI) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup QSPI QSPI - * @brief QSPI HAL module driver - * @{ - */ -#ifdef HAL_QSPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ - -/* Private define ------------------------------------------------------------*/ -/** @defgroup QSPI_Private_Constants QSPI Private Constants - * @{ - */ -#define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!Instance)); - assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); - assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); - assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); - assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); - assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); - assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); - assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); - - if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) - { - assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); - } - - if(hqspi->State == HAL_QSPI_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hqspi->Lock = HAL_UNLOCKED; - -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - /* Reset Callback pointers in HAL_QSPI_STATE_RESET only */ - hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; - hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; - hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; - hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; - hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; - hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; - hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; - hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; - hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; - hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; - - if(hqspi->MspInitCallback == NULL) - { - hqspi->MspInitCallback = HAL_QSPI_MspInit; - } - - /* Init the low level hardware */ - hqspi->MspInitCallback(hqspi); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_QSPI_MspInit(hqspi); -#endif - - /* Configure the default timeout for the QSPI memory access */ - HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); - } - - /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - - if(status == HAL_OK) - { - /* Configure QSPI Clock Prescaler and Sample Shift */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), - ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | - hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); - - /* Configure QSPI Flash Size, CS High Time and Clock Mode */ - MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), - ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | - hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); - - /* Enable the QSPI peripheral */ - __HAL_QSPI_ENABLE(hqspi); - - /* Set QSPI error code to none */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Initialize the QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - - /* Release Lock */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @brief De-Initialize the QSPI peripheral. - * @param hqspi QSPI handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) -{ - /* Check the QSPI handle allocation */ - if(hqspi == NULL) - { - return HAL_ERROR; - } - - /* Disable the QSPI Peripheral Clock */ - __HAL_QSPI_DISABLE(hqspi); - -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - if(hqspi->MspDeInitCallback == NULL) - { - hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; - } - - /* DeInit the low level hardware */ - hqspi->MspDeInitCallback(hqspi); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_QSPI_MspDeInit(hqspi); -#endif - - /* Set QSPI error code to none */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Initialize the QSPI state */ - hqspi->State = HAL_QSPI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hqspi); - - return HAL_OK; -} - -/** - * @brief Initialize the QSPI MSP. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_QSPI_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the QSPI MSP. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_QSPI_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup QSPI_Exported_Functions_Group2 Input and Output operation functions - * @brief QSPI Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Handle the interrupts. - (+) Handle the command sequence. - (+) Transmit data in blocking, interrupt or DMA mode. - (+) Receive data in blocking, interrupt or DMA mode. - (+) Manage the auto-polling functional mode. - (+) Manage the memory-mapped functional mode. - -@endverbatim - * @{ - */ - -/** - * @brief Handle QSPI interrupt request. - * @param hqspi QSPI handle - * @retval None - */ -void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) -{ - __IO uint32_t *data_reg; - uint32_t flag = READ_REG(hqspi->Instance->SR); - uint32_t itsource = READ_REG(hqspi->Instance->CR); - - /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/ - if(((flag & QSPI_FLAG_FT) != 0U) && ((itsource & QSPI_IT_FT) != 0U)) - { - data_reg = &hqspi->Instance->DR; - - if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) - { - /* Transmission process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) - { - if (hqspi->TxXferCount > 0U) - { - /* Fill the FIFO until the threshold is reached */ - *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; - hqspi->pTxBuffPtr++; - hqspi->TxXferCount--; - } - else - { - /* No more data available for the transfer */ - /* Disable the QSPI FIFO Threshold Interrupt */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); - break; - } - } - } - else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) - { - /* Receiving Process */ - while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) - { - if (hqspi->RxXferCount > 0U) - { - /* Read the FIFO until the threshold is reached */ - *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); - hqspi->pRxBuffPtr++; - hqspi->RxXferCount--; - } - else - { - /* All data have been received for the transfer */ - /* Disable the QSPI FIFO Threshold Interrupt */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); - break; - } - } - } - else - { - /* Nothing to do */ - } - - /* FIFO Threshold callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->FifoThresholdCallback(hqspi); -#else - HAL_QSPI_FifoThresholdCallback(hqspi); -#endif - } - - /* QSPI Transfer Complete interrupt occurred -------------------------------*/ - else if(((flag & QSPI_FLAG_TC) != 0U) && ((itsource & QSPI_IT_TC) != 0U)) - { - /* Clear interrupt */ - WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); - - /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); - - /* Transfer complete callback */ - if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) - { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hqspi->hdma); - } - -#if defined(QSPI1_V1_0) - /* Clear Busy bit */ - HAL_QSPI_Abort_IT(hqspi); -#endif - - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* TX Complete callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->TxCpltCallback(hqspi); -#else - HAL_QSPI_TxCpltCallback(hqspi); -#endif - } - else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) - { - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hqspi->hdma); - } - else - { - data_reg = &hqspi->Instance->DR; - while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) - { - if (hqspi->RxXferCount > 0U) - { - /* Read the last data received in the FIFO until it is empty */ - *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); - hqspi->pRxBuffPtr++; - hqspi->RxXferCount--; - } - else - { - /* All data have been received for the transfer */ - break; - } - } - } - -#if defined(QSPI1_V1_0) - /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - HAL_QSPI_Abort_IT(hqspi); -#endif - - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* RX Complete callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->RxCpltCallback(hqspi); -#else - HAL_QSPI_RxCpltCallback(hqspi); -#endif - } - else if(hqspi->State == HAL_QSPI_STATE_BUSY) - { - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Command Complete callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->CmdCpltCallback(hqspi); -#else - HAL_QSPI_CmdCpltCallback(hqspi); -#endif - } - else if(hqspi->State == HAL_QSPI_STATE_ABORT) - { - /* Reset functional mode configuration to indirect write mode by default */ - CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); - - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) - { - /* Abort called by the user */ - - /* Abort Complete callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->AbortCpltCallback(hqspi); -#else - HAL_QSPI_AbortCpltCallback(hqspi); -#endif - } - else - { - /* Abort due to an error (eg : DMA error) */ - - /* Error callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->ErrorCallback(hqspi); -#else - HAL_QSPI_ErrorCallback(hqspi); -#endif - } - } - else - { - /* Nothing to do */ - } - } - - /* QSPI Status Match interrupt occurred ------------------------------------*/ - else if(((flag & QSPI_FLAG_SM) != 0U) && ((itsource & QSPI_IT_SM) != 0U)) - { - /* Clear interrupt */ - WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); - - /* Check if the automatic poll mode stop is activated */ - if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) - { - /* Disable the QSPI Transfer Error and Status Match Interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); - - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - } - - /* Status match callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->StatusMatchCallback(hqspi); -#else - HAL_QSPI_StatusMatchCallback(hqspi); -#endif - } - - /* QSPI Transfer Error interrupt occurred ----------------------------------*/ - else if(((flag & QSPI_FLAG_TE) != 0U) && ((itsource & QSPI_IT_TE) != 0U)) - { - /* Clear interrupt */ - WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); - - /* Disable all the QSPI Interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); - - /* Set error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Disable the DMA channel */ - hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; - if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) - { - /* Set error code to DMA */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Error callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->ErrorCallback(hqspi); -#else - HAL_QSPI_ErrorCallback(hqspi); -#endif - } - } - else - { - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Error callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->ErrorCallback(hqspi); -#else - HAL_QSPI_ErrorCallback(hqspi); -#endif - } - } - - /* QSPI Timeout interrupt occurred -----------------------------------------*/ - else if(((flag & QSPI_FLAG_TO) != 0U) && ((itsource & QSPI_IT_TO) != 0U)) - { - /* Clear interrupt */ - WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); - - /* Timeout callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->TimeOutCallback(hqspi); -#else - HAL_QSPI_TimeOutCallback(hqspi); -#endif - } - - else - { - /* Nothing to do */ - } -} - -/** - * @brief Set the command configuration. - * @param hqspi QSPI handle - * @param cmd : structure that contains the command configuration information - * @param Timeout Timeout duration - * @note This function is used only in Indirect Read or Write Modes - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_BUSY; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Call the configuration function */ - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - if (cmd->DataMode == QSPI_DATA_NONE) - { - /* When there is no data phase, the transfer start as soon as the configuration is done - so wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - else - { - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @brief Set the command configuration in interrupt mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information - * @note This function is used only in Indirect Read or Write Modes - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) -{ - HAL_StatusTypeDef status; - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_BUSY; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); - - if (status == HAL_OK) - { - if (cmd->DataMode == QSPI_DATA_NONE) - { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - } - - /* Call the configuration function */ - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - if (cmd->DataMode == QSPI_DATA_NONE) - { - /* When there is no data phase, the transfer start as soon as the configuration is done - so activate TC and TE interrupts */ - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI Transfer Error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); - } - else - { - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - /* Return function status */ - return status; -} - -/** - * @brief Transmit an amount of data in blocking mode. - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @param Timeout Timeout duration - * @note This function is used only in Indirect Write Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = HAL_GetTick(); - __IO uint32_t *data_reg = &hqspi->Instance->DR; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - - /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->pTxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - while(hqspi->TxXferCount > 0U) - { - /* Wait until FT flag is set to send data */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); - - if (status != HAL_OK) - { - break; - } - - *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; - hqspi->pTxBuffPtr++; - hqspi->TxXferCount--; - } - - if (status == HAL_OK) - { - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Clear Transfer Complete bit */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - -#if defined(QSPI1_V1_0) - /* Clear Busy bit */ - status = HAL_QSPI_Abort(hqspi); -#endif - } - } - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - return status; -} - - -/** - * @brief Receive an amount of data in blocking mode. - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @param Timeout Timeout duration - * @note This function is used only in Indirect Read Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = HAL_GetTick(); - uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - __IO uint32_t *data_reg = &hqspi->Instance->DR; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - - /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->pRxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - - while(hqspi->RxXferCount > 0U) - { - /* Wait until FT or TC flag is set to read received data */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout); - - if (status != HAL_OK) - { - break; - } - - *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); - hqspi->pRxBuffPtr++; - hqspi->RxXferCount--; - } - - if (status == HAL_OK) - { - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Clear Transfer Complete bit */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - -#if defined(QSPI1_V1_0) - /* Workaround - Extra data written in the FIFO at the end of a read transfer */ - status = HAL_QSPI_Abort(hqspi); -#endif - } - } - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - return status; -} - -/** - * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @note This function is used only in Indirect Write Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - - /* Configure counters and size of the handle */ - hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->pTxBuffPtr = pData; - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - - /* Configure QSPI: CCR register with functional as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - return status; -} - -/** - * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @note This function is used only in Indirect Read Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - - /* Configure counters and size of the handle */ - hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; - hqspi->pRxBuffPtr = pData; - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); - - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - return status; -} - -/** - * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi QSPI handle - * @param pData pointer to data buffer - * @note This function is used only in Indirect Write Mode - * @note If DMA peripheral access is configured as halfword, the number - * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number - * of data and the fifo threshold should be aligned on word - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - /* Clear the error code */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Configure counters of the handle */ - if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) - { - hqspi->TxXferCount = data_size; - } - else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) - { - if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) - { - /* The number of data or the fifo threshold is not aligned on halfword - => no transfer possible with DMA peripheral access configured as halfword */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - else - { - hqspi->TxXferCount = (data_size >> 1U); - } - } - else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) - { - if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) - { - /* The number of data or the fifo threshold is not aligned on word - => no transfer possible with DMA peripheral access configured as word */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - else - { - hqspi->TxXferCount = (data_size >> 2U); - } - } - else - { - /* Nothing to do */ - } - - if (status == HAL_OK) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - - /* Configure size and pointer of the handle */ - hqspi->TxXferSize = hqspi->TxXferCount; - hqspi->pTxBuffPtr = pData; - - /* Configure QSPI: CCR register with functional mode as indirect write */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - /* Set the QSPI DMA transfer complete callback */ - hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; - - /* Set the QSPI DMA Half transfer complete callback */ - hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; - - /* Set the DMA error callback */ - hqspi->hdma->XferErrorCallback = QSPI_DMAError; - - /* Clear the DMA abort callback */ - hqspi->hdma->XferAbortCallback = NULL; - - /* Configure the direction of the DMA */ - hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; - MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); - - /* Enable the QSPI transmit DMA Channel */ - if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize) == HAL_OK) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - } - else - { - status = HAL_ERROR; - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - hqspi->State = HAL_QSPI_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - return status; -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi QSPI handle - * @param pData pointer to data buffer. - * @note This function is used only in Indirect Read Mode - * @note If DMA peripheral access is configured as halfword, the number - * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number - * of data and the fifo threshold should be aligned on word - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t addr_reg = READ_REG(hqspi->Instance->AR); - uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - /* Clear the error code */ - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - if(pData != NULL ) - { - /* Configure counters of the handle */ - if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) - { - hqspi->RxXferCount = data_size; - } - else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) - { - if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) - { - /* The number of data or the fifo threshold is not aligned on halfword - => no transfer possible with DMA peripheral access configured as halfword */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - else - { - hqspi->RxXferCount = (data_size >> 1U); - } - } - else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) - { - if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) - { - /* The number of data or the fifo threshold is not aligned on word - => no transfer possible with DMA peripheral access configured as word */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - else - { - hqspi->RxXferCount = (data_size >> 2U); - } - } - else - { - /* Nothing to do */ - } - - if (status == HAL_OK) - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); - - /* Configure size and pointer of the handle */ - hqspi->RxXferSize = hqspi->RxXferCount; - hqspi->pRxBuffPtr = pData; - - /* Set the QSPI DMA transfer complete callback */ - hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; - - /* Set the QSPI DMA Half transfer complete callback */ - hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; - - /* Set the DMA error callback */ - hqspi->hdma->XferErrorCallback = QSPI_DMAError; - - /* Clear the DMA abort callback */ - hqspi->hdma->XferAbortCallback = NULL; - - /* Configure the direction of the DMA */ - hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; - MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); - - /* Enable the DMA Channel */ - if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) - { - /* Configure QSPI: CCR register with functional as indirect read */ - MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Start the transfer by re-writing the address in AR register */ - WRITE_REG(hqspi->Instance->AR, addr_reg); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI transfer error Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - - /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - } - else - { - status = HAL_ERROR; - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - hqspi->State = HAL_QSPI_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - } - else - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - return status; -} - -/** - * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the polling configuration information. - * @param Timeout Timeout duration - * @note This function is used only in Automatic Polling Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - assert_param(IS_QSPI_INTERVAL(cfg->Interval)); - assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); - assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Configure QSPI: PSMAR register with the status match value */ - WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - - /* Configure QSPI: PSMKR register with the status mask value */ - WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - - /* Configure QSPI: PIR register with the interval value */ - WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - - /* Configure QSPI: CR register with Match mode and Automatic stop enabled - (otherwise there will be an infinite loop in blocking mode) */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), - (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE)); - - /* Call the configuration function */ - cmd->NbData = cfg->StatusBytesSize; - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); - - /* Wait until SM flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the polling configuration information. - * @note This function is used only in Automatic Polling Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) -{ - HAL_StatusTypeDef status; - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - assert_param(IS_QSPI_INTERVAL(cfg->Interval)); - assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize)); - assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode)); - assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); - - if (status == HAL_OK) - { - /* Configure QSPI: PSMAR register with the status match value */ - WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); - - /* Configure QSPI: PSMKR register with the status mask value */ - WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); - - /* Configure QSPI: PIR register with the interval value */ - WRITE_REG(hqspi->Instance->PIR, cfg->Interval); - - /* Configure QSPI: CR register with Match mode and Automatic stop mode */ - MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), - (cfg->MatchMode | cfg->AutomaticStop)); - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); - - /* Call the configuration function */ - cmd->NbData = cfg->StatusBytesSize; - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Enable the QSPI Transfer Error and status match Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); - - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - } - else - { - status = HAL_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the Memory Mapped mode. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information. - * @param cfg structure that contains the memory mapped configuration information. - * @note This function is used only in Memory mapped Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters */ - assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction)); - } - - assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize)); - } - - assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode)); - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize)); - } - - assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles)); - assert_param(IS_QSPI_DATA_MODE(cmd->DataMode)); - - assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode)); - assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle)); - assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode)); - - assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; - - /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - - if (status == HAL_OK) - { - /* Configure QSPI: CR register with timeout counter enable */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); - - if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE) - { - assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); - - /* Configure QSPI: LPTR register with the low-power timeout value */ - WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); - - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); - - /* Enable the QSPI TimeOut Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); - } - - /* Call the configuration function */ - QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); - } - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @brief Transfer Error callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_QSPI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Abort completed callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_QSPI_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Command completed callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_QSPI_CmdCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_QSPI_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer completed callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_QSPI_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief FIFO Threshold callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file - */ -} - -/** - * @brief Status Match callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_QSPI_StatusMatchCallback could be implemented in the user file - */ -} - -/** - * @brief Timeout callback. - * @param hqspi QSPI handle - * @retval None - */ -__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hqspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_QSPI_TimeOutCallback could be implemented in the user file - */ -} -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User QSPI Callback - * To be used to override the weak predefined callback - * @param hqspi QSPI handle - * @param CallbackId ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID - * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID - * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID - * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID - * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID - * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID - * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID - * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID - * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID - * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID - * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID - * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(pCallback == NULL) - { - /* Update the error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - switch (CallbackId) - { - case HAL_QSPI_ERROR_CB_ID : - hqspi->ErrorCallback = pCallback; - break; - case HAL_QSPI_ABORT_CB_ID : - hqspi->AbortCpltCallback = pCallback; - break; - case HAL_QSPI_FIFO_THRESHOLD_CB_ID : - hqspi->FifoThresholdCallback = pCallback; - break; - case HAL_QSPI_CMD_CPLT_CB_ID : - hqspi->CmdCpltCallback = pCallback; - break; - case HAL_QSPI_RX_CPLT_CB_ID : - hqspi->RxCpltCallback = pCallback; - break; - case HAL_QSPI_TX_CPLT_CB_ID : - hqspi->TxCpltCallback = pCallback; - break; - case HAL_QSPI_RX_HALF_CPLT_CB_ID : - hqspi->RxHalfCpltCallback = pCallback; - break; - case HAL_QSPI_TX_HALF_CPLT_CB_ID : - hqspi->TxHalfCpltCallback = pCallback; - break; - case HAL_QSPI_STATUS_MATCH_CB_ID : - hqspi->StatusMatchCallback = pCallback; - break; - case HAL_QSPI_TIMEOUT_CB_ID : - hqspi->TimeOutCallback = pCallback; - break; - case HAL_QSPI_MSP_INIT_CB_ID : - hqspi->MspInitCallback = pCallback; - break; - case HAL_QSPI_MSP_DEINIT_CB_ID : - hqspi->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hqspi->State == HAL_QSPI_STATE_RESET) - { - switch (CallbackId) - { - case HAL_QSPI_MSP_INIT_CB_ID : - hqspi->MspInitCallback = pCallback; - break; - case HAL_QSPI_MSP_DEINIT_CB_ID : - hqspi->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hqspi); - return status; -} - -/** - * @brief Unregister a User QSPI Callback - * QSPI Callback is redirected to the weak predefined callback - * @param hqspi QSPI handle - * @param CallbackId ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID - * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID - * @arg @ref HAL_QSPI_FIFO_THRESHOLD_CB_ID QSPI FIFO Threshold Callback ID - * @arg @ref HAL_QSPI_CMD_CPLT_CB_ID QSPI Command Complete Callback ID - * @arg @ref HAL_QSPI_RX_CPLT_CB_ID QSPI Rx Complete Callback ID - * @arg @ref HAL_QSPI_TX_CPLT_CB_ID QSPI Tx Complete Callback ID - * @arg @ref HAL_QSPI_RX_HALF_CPLT_CB_ID QSPI Rx Half Complete Callback ID - * @arg @ref HAL_QSPI_TX_HALF_CPLT_CB_ID QSPI Tx Half Complete Callback ID - * @arg @ref HAL_QSPI_STATUS_MATCH_CB_ID QSPI Status Match Callback ID - * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID - * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID - * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - switch (CallbackId) - { - case HAL_QSPI_ERROR_CB_ID : - hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; - break; - case HAL_QSPI_ABORT_CB_ID : - hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; - break; - case HAL_QSPI_FIFO_THRESHOLD_CB_ID : - hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; - break; - case HAL_QSPI_CMD_CPLT_CB_ID : - hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; - break; - case HAL_QSPI_RX_CPLT_CB_ID : - hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; - break; - case HAL_QSPI_TX_CPLT_CB_ID : - hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; - break; - case HAL_QSPI_RX_HALF_CPLT_CB_ID : - hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; - break; - case HAL_QSPI_TX_HALF_CPLT_CB_ID : - hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; - break; - case HAL_QSPI_STATUS_MATCH_CB_ID : - hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; - break; - case HAL_QSPI_TIMEOUT_CB_ID : - hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; - break; - case HAL_QSPI_MSP_INIT_CB_ID : - hqspi->MspInitCallback = HAL_QSPI_MspInit; - break; - case HAL_QSPI_MSP_DEINIT_CB_ID : - hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; - break; - default : - /* Update the error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hqspi->State == HAL_QSPI_STATE_RESET) - { - switch (CallbackId) - { - case HAL_QSPI_MSP_INIT_CB_ID : - hqspi->MspInitCallback = HAL_QSPI_MspInit; - break; - case HAL_QSPI_MSP_DEINIT_CB_ID : - hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; - break; - default : - /* Update the error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hqspi); - return status; -} -#endif - -/** - * @} - */ - -/** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions - * @brief QSPI control and State functions - * -@verbatim - =============================================================================== - ##### Peripheral Control and State functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Check in run-time the state of the driver. - (+) Check the error code set during last operation. - (+) Abort any operation. - - -@endverbatim - * @{ - */ - -/** - * @brief Return the QSPI handle state. - * @param hqspi QSPI handle - * @retval HAL state - */ -HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) -{ - /* Return QSPI handle state */ - return hqspi->State; -} - -/** -* @brief Return the QSPI error code. -* @param hqspi QSPI handle -* @retval QSPI Error Code -*/ -uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) -{ - return hqspi->ErrorCode; -} - -/** -* @brief Abort the current transmission. -* @param hqspi QSPI handle -* @retval HAL status -*/ -HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = HAL_GetTick(); - - /* Check if the state is in one of the busy states */ - if (((uint32_t)hqspi->State & 0x2U) != 0U) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Abort DMA channel */ - status = HAL_DMA_Abort(hqspi->hdma); - if(status != HAL_OK) - { - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - } - } - - if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) - { - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - - if (status == HAL_OK) - { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); - } - - if (status == HAL_OK) - { - /* Reset functional mode configuration to indirect write mode by default */ - CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); - - /* Update state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - else - { - /* Update state */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - - return status; -} - -/** -* @brief Abort the current transmission (non-blocking function) -* @param hqspi QSPI handle -* @retval HAL status -*/ -HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check if the state is in one of the busy states */ - if (((uint32_t)hqspi->State & 0x2U) != 0U) - { - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Update QSPI state */ - hqspi->State = HAL_QSPI_STATE_ABORT; - - /* Disable all interrupts */ - __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); - - if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) - { - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Abort DMA channel */ - hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; - if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) - { - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Abort Complete callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->AbortCpltCallback(hqspi); -#else - HAL_QSPI_AbortCpltCallback(hqspi); -#endif - } - } - else - { - if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) - { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - } - else - { - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - } - } - } - return status; -} - -/** @brief Set QSPI timeout. - * @param hqspi QSPI handle. - * @param Timeout Timeout for the QSPI memory access. - * @retval None - */ -void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) -{ - hqspi->Timeout = Timeout; -} - -/** @brief Set QSPI Fifo threshold. - * @param hqspi QSPI handle. - * @param Threshold Threshold of the Fifo (value between 1 and 16). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - /* Synchronize init structure with new FIFO threshold value */ - hqspi->Init.FifoThreshold = Threshold; - - /* Configure QSPI FIFO Threshold */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, - ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** @brief Get QSPI Fifo threshold. - * @param hqspi QSPI handle. - * @retval Fifo threshold (value between 1 and 16) - */ -uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) -{ - return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); -} - -/** @brief Set FlashID. - * @param hqspi QSPI handle. - * @param FlashID Index of the flash memory to be accessed. - * This parameter can be a value of @ref QSPI_Flash_Select. - * @note The FlashID is ignored when dual flash mode is enabled. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameter */ - assert_param(IS_QSPI_FLASH_ID(FlashID)); - - /* Process locked */ - __HAL_LOCK(hqspi); - - if(hqspi->State == HAL_QSPI_STATE_READY) - { - /* Synchronize init structure with new FlashID value */ - hqspi->Init.FlashID = FlashID; - - /* Configure QSPI FlashID */ - MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); - } - else - { - status = HAL_BUSY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hqspi); - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup QSPI_Private_Functions QSPI Private Functions - * @{ - */ - -/** - * @brief DMA QSPI receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); - hqspi->RxXferCount = 0U; - - /* Enable the QSPI transfer complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); -} - -/** - * @brief DMA QSPI transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); - hqspi->TxXferCount = 0U; - - /* Enable the QSPI transfer complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); -} - -/** - * @brief DMA QSPI receive process half complete callback. - * @param hdma DMA handle - * @retval None - */ -static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); - -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->RxHalfCpltCallback(hqspi); -#else - HAL_QSPI_RxHalfCpltCallback(hqspi); -#endif -} - -/** - * @brief DMA QSPI transmit process half complete callback. - * @param hdma DMA handle - * @retval None - */ -static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); - -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->TxHalfCpltCallback(hqspi); -#else - HAL_QSPI_TxHalfCpltCallback(hqspi); -#endif -} - -/** - * @brief DMA QSPI communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void QSPI_DMAError(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); - - /* if DMA error is FIFO error ignore it */ - if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) - { - hqspi->RxXferCount = 0U; - hqspi->TxXferCount = 0U; - hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; - - /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */ - CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); - - /* Abort the QSPI */ - (void)HAL_QSPI_Abort_IT(hqspi); - - } -} - -/** - * @brief DMA QSPI abort complete callback. - * @param hdma DMA handle - * @retval None - */ -static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) -{ - QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); - - hqspi->RxXferCount = 0U; - hqspi->TxXferCount = 0U; - - if(hqspi->State == HAL_QSPI_STATE_ABORT) - { - /* DMA Abort called by QSPI abort */ - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - } - else - { - /* DMA Abort called due to a transfer error interrupt */ - /* Change state of QSPI */ - hqspi->State = HAL_QSPI_STATE_READY; - - /* Error callback */ -#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) - hqspi->ErrorCallback(hqspi); -#else - HAL_QSPI_ErrorCallback(hqspi); -#endif - } -} - -/** - * @brief Wait for a flag state until timeout. - * @param hqspi QSPI handle - * @param Flag Flag checked - * @param State Value of the flag expected - * @param Tickstart Tick start value - * @param Timeout Duration of the timeout - * @retval HAL status - */ -static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, - FlagStatus State, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is in expected state */ - while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if(((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - hqspi->State = HAL_QSPI_STATE_ERROR; - hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; - - return HAL_ERROR; - } - } - } - return HAL_OK; -} - -/** - * @brief Wait for a flag state until timeout using CPU cycle. - * @param hqspi : QSPI handle - * @param Flag : Flag checked - * @param State : Value of the flag expected - * @param Timeout : Duration of the timeout - * @retval HAL status - */ -static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout) -{ - __IO uint32_t count = Timeout * (SystemCoreClock / 16U / 1000U); - do - { - if (count-- == 0U) - { - hqspi->State = HAL_QSPI_STATE_ERROR; - hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; - return HAL_TIMEOUT; - } - } - while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State); - - return HAL_OK; -} - -/** - * @brief Configure the communication registers. - * @param hqspi QSPI handle - * @param cmd structure that contains the command configuration information - * @param FunctionalMode functional mode to configured - * This parameter can be one of the following values: - * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode - * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode - * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode - * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode - * @retval None - */ -static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode) -{ - assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode)); - - if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) - { - /* Configure QSPI: DLR register with the number of data to read or write */ - WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); - } - - if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE) - { - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - /* Configure QSPI: ABR register with alternate bytes value */ - WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); - - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - /*---- Command with instruction, address and alternate bytes ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode | - cmd->Instruction | FunctionalMode)); - - if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) - { - /* Configure QSPI: AR register with address value */ - WRITE_REG(hqspi->Instance->AR, cmd->Address); - } - } - else - { - /*---- Command with instruction and alternate bytes ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | - cmd->Instruction | FunctionalMode)); - } - } - else - { - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - /*---- Command with instruction and address ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode | - cmd->InstructionMode | cmd->Instruction | FunctionalMode)); - - if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) - { - /* Configure QSPI: AR register with address value */ - WRITE_REG(hqspi->Instance->AR, cmd->Address); - } - } - else - { - /*---- Command with only instruction ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressMode | - cmd->InstructionMode | cmd->Instruction | FunctionalMode)); - } - } - } - else - { - if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE) - { - /* Configure QSPI: ABR register with alternate bytes value */ - WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); - - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - /*---- Command with address and alternate bytes ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressSize | cmd->AddressMode | - cmd->InstructionMode | FunctionalMode)); - - if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) - { - /* Configure QSPI: AR register with address value */ - WRITE_REG(hqspi->Instance->AR, cmd->Address); - } - } - else - { - /*---- Command with only alternate bytes ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateBytesSize | cmd->AlternateByteMode | - cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); - } - } - else - { - if (cmd->AddressMode != QSPI_ADDRESS_NONE) - { - /*---- Command with only address ----*/ - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressSize | - cmd->AddressMode | cmd->InstructionMode | FunctionalMode)); - - if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED) - { - /* Configure QSPI: AR register with address value */ - WRITE_REG(hqspi->Instance->AR, cmd->Address); - } - } - else - { - /*---- Command with only data phase ----*/ - if (cmd->DataMode != QSPI_DATA_NONE) - { - /* Configure QSPI: CCR register with all communications parameters */ - WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | - cmd->DataMode | (cmd->DummyCycles << QUADSPI_CCR_DCYC_Pos) | - cmd->AlternateByteMode | cmd->AddressMode | - cmd->InstructionMode | FunctionalMode)); - } - } - } - } -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_QSPI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(QUADSPI) */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c index 6c030ceb..49b94e9b 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c @@ -1,1239 +1,1239 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Internal High Speed oscillator - (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; - all peripherals mapped on these buses are running at HSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in input floating state, except the JTAG pins which - are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB buses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) - - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle - after the clock enable bit is set on the hardware register - (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle - after the clock enable bit is set on the hardware register - - [..] - Implemented Workaround: - (+) For AHB & APB peripherals, a dummy read to the peripheral register has been - inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. - - @endverbatim - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC - * @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define MCO1_GPIO_PORT GPIOA -#define MCO1_PIN GPIO_PIN_8 - -#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() -#define MCO2_GPIO_PORT GPIOC -#define MCO2_PIN GPIO_PIN_9 - -/** - * @} - */ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Variables RCC Private Variables - * @{ - */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== -##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal/external oscillators - (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also as RTC clock source. - - (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. - - (#) PLL (clocked by HSI or HSE), featuring two different output clocks: - (++) The first output is used to generate the high speed system clock (up to 216 MHz) - (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). - - (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS() - and if a HSE clock failure occurs(HSE used directly or through PLL as System - clock source), the System clock is automatically switched to HSI and an interrupt - is generated if enabled. The interrupt is linked to the Cortex-M7 NMI - (Non-Maskable Interrupt) exception vector. - - (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL - clock (through a configurable prescaler) on PA8 pin. - - (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S - clock (through a configurable prescaler) on PC9 pin. - - [..] System, AHB and APB buses clocks configuration - (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, - HSE and PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these buses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or - from an external clock mapped on the I2S_CKIN pin. - You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. - (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or - from an external clock mapped on the I2S_CKIN pin. - You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. - (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() - macros to configure this clock. - (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz - to work correctly, while the SDIO require a frequency equal or lower than - to 48. This clock is derived of the main PLL through PLLQ divider. - (+@) IWDG clock which is always the LSI clock. -@endverbatim - * @{ - */ - -/** - * @brief Resets the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL, PLLI2S and PLLSAI OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO1 and MCO2 OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_DeInit(void) -{ - uint32_t tickstart; - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Set HSION bit to the reset value */ - SET_BIT(RCC->CR, RCC_CR_HSION); - - /* Wait till HSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set HSITRIM[4:0] bits to the reset value */ - SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Wait till clock switch is ready */ - while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Clear HSEON, HSEBYP and CSSON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); - - /* Wait till HSE is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Clear PLLON bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); - - /* Wait till PLL is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Reset PLLI2SON bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); - - /* Wait till PLLI2S is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Get Start Tick */ - tickstart = HAL_GetTick(); - - /* Reset PLLSAI bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); - - /* Wait till PLLSAI is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ - RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U; - - /* Reset PLLI2SCFGR register to default value */ - RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; - - /* Reset PLLSAICFGR register to default value */ - RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U; - - /* Disable all interrupts */ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); - - /* Clear all interrupt flags */ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); - - /* Clear LSION bit */ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); - - /* Reset all CSR flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HSI_VALUE; - - /* Adapt Systick interrupt period */ - if (HAL_InitTick(uwTickPrio) != HAL_OK) - { - return HAL_ERROR; - } - else - { - return HAL_OK; - } -} - -/** - * @brief Initializes the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this function. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this function. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - uint32_t tickstart; - uint32_t pll_config; - FlagStatus pwrclkchanged = RESET; - - /* Check Null pointer */ - if (RCC_OscInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); - - /*------------------------------- HSE Configuration ------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); - /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ - if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - { - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is bypassed or disabled */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - { - /* When HSI is used as system clock it will not disabled */ - if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI). */ - __HAL_RCC_HSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); - - /* Check the LSI State */ - if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) - { - /* Enable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI). */ - __HAL_RCC_LSI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - /* Check the parameters */ - assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - /* Enable write access to Backup domain */ - PWR->CR1 |= PWR_CR1_DBP; - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) - { - if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - /* Check the LSE State */ - if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Restore clock configuration if changed */ - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); - if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - /* Check if the PLL is used as system clock or not */ - if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); -#if defined (RCC_PLLCFGR_PLLR) - assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); -#endif - - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure the main PLL clock source, multiplication and division factors. */ -#if defined (RCC_PLLCFGR_PLLR) - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLM, - RCC_OscInitStruct->PLL.PLLN, - RCC_OscInitStruct->PLL.PLLP, - RCC_OscInitStruct->PLL.PLLQ, - RCC_OscInitStruct->PLL.PLLR); -#else - __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, - RCC_OscInitStruct->PLL.PLLM, - RCC_OscInitStruct->PLL.PLLN, - RCC_OscInitStruct->PLL.PLLP, - RCC_OscInitStruct->PLL.PLLQ); -#endif - - /* Enable the main PLL. */ - __HAL_RCC_PLL_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the main PLL. */ - __HAL_RCC_PLL_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - /* Do not return HAL_ERROR if request repeats the current configuration */ - pll_config = RCC->PLLCFGR; -#if defined (RCC_PLLCFGR_PLLR) - if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) -#else - if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || - (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) -#endif - { - return HAL_ERROR; - } - } - } - return HAL_OK; -} - -/** - * @brief Initializes the CPU, AHB and APB buses clocks according to the specified - * parameters in the RCC_ClkInitStruct. - * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency, this parameter depend on device selected - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The HSI is used (enabled by hardware) as system clock source after - * startup from Reset, wake-up from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source will be ready. - * You can use HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * @note Depending on the device voltage range, the software has to set correctly - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval None - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) -{ - uint32_t tickstart = 0; - - /* Check Null pointer */ - if (RCC_ClkInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device. */ - - /* Increasing the CPU frequency */ - if (FLatency > __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - /* Set the highest APBx dividers in order to ensure that we do not go through - a non-spec phase whatever we decrease or increase HCLK. */ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - } - - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - } - - /* Set the new HCLK clock divider */ - assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); - - /* HSE is selected as System Clock Source */ - if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - { - return HAL_ERROR; - } - } - /* PLL is selected as System Clock Source */ - else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - /* Check the PLL ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - { - return HAL_ERROR; - } - } - - __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLatency < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings*/ - HAL_InitTick(uwTickPrio); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * - @verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - -@endverbatim - * @{ - */ - -/** - * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). - * @note PA8/PC9 should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * This parameter can be one of the following values: - * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). - * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source - * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source - * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source - * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source - * @param RCC_MCODiv specifies the MCOx prescaler. - * This parameter can be one of the following values: - * @arg RCC_MCODIV_1: no division applied to MCOx clock - * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock - * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock - * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock - * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock - * @retval None - */ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef GPIO_InitStruct; - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - /* RCC_MCO1 */ - if (RCC_MCOx == RCC_MCO1) - { - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* MCO1 Clock Enable */ - MCO1_CLK_ENABLE(); - - /* Configure the MCO1 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO1_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); - - /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); - } - else - { - assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); - - /* MCO2 Clock Enable */ - MCO2_CLK_ENABLE(); - - /* Configure the MCO2 pin in alternate function mode */ - GPIO_InitStruct.Pin = MCO2_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); - - /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); - } -} - -/** - * @brief Enables the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Disables the Clock Security System. - * @retval None - */ -void HAL_RCC_DisableCSS(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Returns the SYSCLK frequency - * - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t pllm = 0, pllvco = 0, pllp = 0; - uint32_t sysclockfreq = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - { - sysclockfreq = HSI_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ - { - sysclockfreq = HSE_VALUE; - break; - } - case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ - { - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP */ - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) - { - /* HSE used as PLL clock source */ - pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - } - pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); - - sysclockfreq = pllvco / pllp; - break; - } - default: - { - sysclockfreq = HSI_VALUE; - break; - } - } - return sysclockfreq; -} - -/** - * @brief Returns the HCLK frequency - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. - * @retval HCLK frequency - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - return SystemCoreClock; -} - -/** - * @brief Returns the PCLK1 frequency - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); -} - -/** - * @brief Returns the PCLK2 frequency - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); -} - -/** - * @brief Configures the RCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) -{ - /* Set all possible values for the Oscillator type parameter ---------------*/ - RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - - /* Get the HSE configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) - { - RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; - } - else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) - { - RCC_OscInitStruct->HSEState = RCC_HSE_ON; - } - else - { - RCC_OscInitStruct->HSEState = RCC_HSE_OFF; - } - - /* Get the HSI configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) - { - RCC_OscInitStruct->HSIState = RCC_HSI_ON; - } - else - { - RCC_OscInitStruct->HSIState = RCC_HSI_OFF; - } - - RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); - - /* Get the LSE configuration -----------------------------------------------*/ - if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) - { - RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; - } - else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) - { - RCC_OscInitStruct->LSEState = RCC_LSE_ON; - } - else - { - RCC_OscInitStruct->LSEState = RCC_LSE_OFF; - } - - /* Get the LSI configuration -----------------------------------------------*/ - if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) - { - RCC_OscInitStruct->LSIState = RCC_LSI_ON; - } - else - { - RCC_OscInitStruct->LSIState = RCC_LSI_OFF; - } - - /* Get the PLL configuration -----------------------------------------------*/ - if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); - RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); - RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos); - RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); -#if defined (RCC_PLLCFGR_PLLR) - RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); -#endif -} - -/** - * @brief Configures the RCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * will be configured. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Set all possible values for the Clock type parameter --------------------*/ - RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - - /* Get the SYSCLK configuration --------------------------------------------*/ - RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); -} - -/** - * @brief This function handles the RCC CSS interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF flag */ - if (__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - } -} - -/** - * @brief RCC Clock Security System interrupt callback - * @retval None - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc.c + * @author MCD Application Team + * @brief RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Reset and Clock Control (RCC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + @verbatim + ============================================================================== + ##### RCC specific features ##### + ============================================================================== + [..] + After reset the device is running from Internal High Speed oscillator + (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache + and I-Cache are disabled, and all peripherals are off except internal + SRAM, Flash and JTAG. + (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses; + all peripherals mapped on these buses are running at HSI speed. + (+) The clock for all peripherals is switched off, except the SRAM and FLASH. + (+) All GPIOs are in input floating state, except the JTAG pins which + are assigned to be used for debug purpose. + + [..] + Once the device started from reset, the user application has to: + (+) Configure the clock source to be used to drive the System clock + (if the application needs higher frequency/performance) + (+) Configure the System clock frequency and Flash settings + (+) Configure the AHB and APB buses prescalers + (+) Enable the clock for the peripheral(s) to be used + (+) Configure the clock source(s) for peripherals which clocks are not + derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Implemented Workaround: + (+) For AHB & APB peripherals, a dummy read to the peripheral register has been + inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. + + @endverbatim + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCC RCC + * @brief RCC HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCC_Private_Macros RCC Private Macros + * @{ + */ + +#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() +#define MCO1_GPIO_PORT GPIOA +#define MCO1_PIN GPIO_PIN_8 + +#define MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() +#define MCO2_GPIO_PORT GPIOC +#define MCO2_PIN GPIO_PIN_9 + +/** + * @} + */ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_Private_Variables RCC Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== +##### Initialization and de-initialization functions ##### + =============================================================================== + [..] + This section provides functions allowing to configure the internal/external oscillators + (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1 + and APB2). + + [..] Internal/external clock and PLL configuration + (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through + the PLL as System clock source. + + (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC + clock source. + + (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or + through the PLL as System clock source. Can be used also as RTC clock source. + + (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. + + (#) PLL (clocked by HSI or HSE), featuring two different output clocks: + (++) The first output is used to generate the high speed system clock (up to 216 MHz) + (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), + the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). + + (#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS() + and if a HSE clock failure occurs(HSE used directly or through PLL as System + clock source), the System clock is automatically switched to HSI and an interrupt + is generated if enabled. The interrupt is linked to the Cortex-M7 NMI + (Non-Maskable Interrupt) exception vector. + + (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL + clock (through a configurable prescaler) on PA8 pin. + + (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S + clock (through a configurable prescaler) on PC9 pin. + + [..] System, AHB and APB buses clocks configuration + (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, + HSE and PLL. + The AHB clock (HCLK) is derived from System clock through configurable + prescaler and used to clock the CPU, memory and peripherals mapped + on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived + from AHB clock through configurable prescalers and used to clock + the peripherals mapped on these buses. You can use + "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. + + -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: + (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or + from an external clock mapped on the I2S_CKIN pin. + You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + (+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or + from an external clock mapped on the I2S_CKIN pin. + You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. + (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock + divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() + macros to configure this clock. + (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz + to work correctly, while the SDIO require a frequency equal or lower than + to 48. This clock is derived of the main PLL through PLLQ divider. + (+@) IWDG clock which is always the LSI clock. +@endverbatim + * @{ + */ + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE, PLL, PLLI2S and PLLSAI OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS, MCO1 and MCO2 OFF + * - All interrupts disabled + * @note This function doesn't modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_DeInit(void) +{ + uint32_t tickstart; + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Set HSION bit to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSION); + + /* Wait till HSI is ready */ + while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Set HSITRIM[4:0] bits to the reset value */ + SET_BIT(RCC->CR, RCC_CR_HSITRIM_4); + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Wait till clock switch is ready */ + while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear HSEON, HSEBYP and CSSON bits */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON); + + /* Wait till HSE is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Clear PLLON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + + /* Wait till PLL is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLI2SON bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); + + /* Wait till PLLI2S is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + + /* Reset PLLSAI bit */ + CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); + + /* Wait till PLLSAI is disabled */ + while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */ + RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U; + + /* Reset PLLI2SCFGR register to default value */ + RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1; + + /* Reset PLLSAICFGR register to default value */ + RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U; + + /* Disable all interrupts */ + CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); + + /* Clear all interrupt flags */ + SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); + + /* Clear LSION bit */ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + + /* Reset all CSR flags */ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HSI_VALUE; + + /* Adapt Systick interrupt period */ + if (HAL_InitTick(uwTickPrio) != HAL_OK) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Initializes the RCC Oscillators according to the specified parameters in the + * RCC_OscInitTypeDef. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not + * supported by this function. User should request a transition to LSE Off + * first and then LSE On or LSE Bypass. + * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not + * supported by this function. User should request a transition to HSE Off + * first and then HSE On or HSE Bypass. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + uint32_t tickstart; + uint32_t pll_config; + FlagStatus pwrclkchanged = RESET; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + /* When the HSE is used as system clock or clock source for PLL, It can not be disabled */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) + { + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) + { + return HAL_ERROR; + } + } + else + { + /* Set the new HSE configuration ---------------------------------------*/ + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSE is bypassed or disabled */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + { + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) + || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) + { + /* When HSI is used as system clock it will not disabled */ + if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) + { + return HAL_ERROR; + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + } + else + { + /* Check the HSI State */ + if ((RCC_OscInitStruct->HSIState) != RCC_HSI_OFF) + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till HSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + } + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if ((RCC_OscInitStruct->LSIState) != RCC_LSI_OFF) + { + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSI is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + { + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + if (__HAL_RCC_PWR_IS_CLK_DISABLED()) + { + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + pwrclkchanged = SET; + } + + if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + + while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); + /* Check the LSE State */ + if ((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Restore clock configuration if changed */ + if (pwrclkchanged == SET) + { + __HAL_RCC_PWR_CLK_DISABLE(); + } + } + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) + { + /* Check if the PLL is used as system clock or not */ + if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + { + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) + { + /* Check the parameters */ + assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); + assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); + assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); +#if defined (RCC_PLLCFGR_PLLR) + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); +#endif + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ +#if defined (RCC_PLLCFGR_PLLR) + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); +#else + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + RCC_OscInitStruct->PLL.PLLM, + RCC_OscInitStruct->PLL.PLLN, + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ); +#endif + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLL is ready */ + while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; +#if defined (RCC_PLLCFGR_PLLR) + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) +#else + if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((((RCC_OscInitStruct->PLL.PLLP) >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)) || + (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) +#endif + { + return HAL_ERROR; + } + } + } + return HAL_OK; +} + +/** + * @brief Initializes the CPU, AHB and APB buses clocks according to the specified + * parameters in the RCC_ClkInitStruct. + * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that + * contains the configuration information for the RCC peripheral. + * @param FLatency FLASH Latency, this parameter depend on device selected + * + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency + * and updated by HAL_RCC_GetHCLKFreq() function called within this function + * + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use HAL_RCC_GetClockConfig() function to know which clock is + * currently used as system clock source. + * @note Depending on the device voltage range, the software has to set correctly + * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + uint32_t tickstart = 0; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); + assert_param(IS_FLASH_LATENCY(FLatency)); + + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the CPU clock + (HCLK) and the supply voltage of the device. */ + + /* Increasing the CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- HCLK Configuration --------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + { + /* Set the highest APBx dividers in order to ensure that we do not go through + a non-spec phase whatever we decrease or increase HCLK. */ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); + } + + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); + } + + /* Set the new HCLK clock divider */ + assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + { + /* Check the HSE ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) + { + return HAL_ERROR; + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + { + /* Check the PLL ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) + { + return HAL_ERROR; + } + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) + { + return HAL_ERROR; + } + } + + __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + if (__HAL_FLASH_GET_LATENCY() != FLatency) + { + return HAL_ERROR; + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + { + assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3)); + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]; + + /* Configure the source of time base considering new system clocks settings*/ + HAL_InitTick(uwTickPrio); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @brief RCC clocks control functions + * + @verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + +@endverbatim + * @{ + */ + +/** + * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). + * @note PA8/PC9 should be configured in alternate function mode. + * @param RCC_MCOx specifies the output direction for the clock source. + * This parameter can be one of the following values: + * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). + * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). + * @param RCC_MCOSource specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source + * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source + * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source + * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source + * @param RCC_MCODiv specifies the MCOx prescaler. + * This parameter can be one of the following values: + * @arg RCC_MCODIV_1: no division applied to MCOx clock + * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock + * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock + * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock + * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock + * @retval None + */ +void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) +{ + GPIO_InitTypeDef GPIO_InitStruct; + /* Check the parameters */ + assert_param(IS_RCC_MCO(RCC_MCOx)); + assert_param(IS_RCC_MCODIV(RCC_MCODiv)); + /* RCC_MCO1 */ + if (RCC_MCOx == RCC_MCO1) + { + assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); + + /* MCO1 Clock Enable */ + MCO1_CLK_ENABLE(); + + /* Configure the MCO1 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO1_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); + } + else + { + assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); + + /* MCO2 Clock Enable */ + MCO2_CLK_ENABLE(); + + /* Configure the MCO2 pin in alternate function mode */ + GPIO_InitStruct.Pin = MCO2_PIN; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Alternate = GPIO_AF0_MCO; + HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); + + /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3))); + } +} + +/** + * @brief Enables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector. + * @retval None + */ +void HAL_RCC_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Disables the Clock Security System. + * @retval None + */ +void HAL_RCC_DisableCSS(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Returns the SYSCLK frequency + * + * @note The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * + * @note Each time SYSCLK changes, this function must be called to update the + * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + uint32_t pllm = 0, pllvco = 0, pllp = 0; + uint32_t sysclockfreq = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ + { + sysclockfreq = HSI_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + { + sysclockfreq = HSE_VALUE; + break; + } + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */ + { + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN + SYSCLK = PLL_VCO / PLLP */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) + { + /* HSE used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSE_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (uint32_t)((((uint64_t) HSI_VALUE * ((uint64_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); + } + pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); + + sysclockfreq = pllvco / pllp; + break; + } + default: + { + sysclockfreq = HSI_VALUE; + break; + } + } + return sysclockfreq; +} + +/** + * @brief Returns the HCLK frequency + * @note Each time HCLK changes, this function must be called to update the + * right HCLK value. Otherwise, any configuration based on this function will be incorrect. + * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. + * @retval HCLK frequency + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + return SystemCoreClock; +} + +/** + * @brief Returns the PCLK1 frequency + * @note Each time PCLK1 changes, this function must be called to update the + * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK1 frequency + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]); +} + +/** + * @brief Returns the PCLK2 frequency + * @note Each time PCLK2 changes, this function must be called to update the + * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. + * @retval PCLK2 frequency + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ + return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos]); +} + +/** + * @brief Configures the RCC_OscInitStruct according to the internal + * RCC configuration registers. + * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that + * will be configured. + * @retval None + */ +void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + /* Set all possible values for the Oscillator type parameter ---------------*/ + RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; + + /* Get the HSE configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP) + { + RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; + } + else if ((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON) + { + RCC_OscInitStruct->HSEState = RCC_HSE_ON; + } + else + { + RCC_OscInitStruct->HSEState = RCC_HSE_OFF; + } + + /* Get the HSI configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION) + { + RCC_OscInitStruct->HSIState = RCC_HSI_ON; + } + else + { + RCC_OscInitStruct->HSIState = RCC_HSI_OFF; + } + + RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); + + /* Get the LSE configuration -----------------------------------------------*/ + if ((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) + { + RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; + } + else if ((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) + { + RCC_OscInitStruct->LSEState = RCC_LSE_ON; + } + else + { + RCC_OscInitStruct->LSEState = RCC_LSE_OFF; + } + + /* Get the LSI configuration -----------------------------------------------*/ + if ((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION) + { + RCC_OscInitStruct->LSIState = RCC_LSI_ON; + } + else + { + RCC_OscInitStruct->LSIState = RCC_LSI_OFF; + } + + /* Get the PLL configuration -----------------------------------------------*/ + if ((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON) + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; + } + else + { + RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; + } + RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); + RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos); + RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos); +#if defined (RCC_PLLCFGR_PLLR) + RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)); +#endif +} + +/** + * @brief Configures the RCC_ClkInitStruct according to the internal + * RCC configuration registers. + * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that + * will be configured. + * @param pFLatency Pointer on the Flash Latency. + * @retval None + */ +void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) +{ + /* Set all possible values for the Clock type parameter --------------------*/ + RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + + /* Get the SYSCLK configuration --------------------------------------------*/ + RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); + + /* Get the HCLK configuration ----------------------------------------------*/ + RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); + + /* Get the APB1 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); + + /* Get the APB2 configuration ----------------------------------------------*/ + RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3); + + /* Get the Flash Wait State (Latency) configuration ------------------------*/ + *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); +} + +/** + * @brief This function handles the RCC CSS interrupt request. + * @note This API should be called under the NMI_Handler(). + * @retval None + */ +void HAL_RCC_NMI_IRQHandler(void) +{ + /* Check RCC CSSF flag */ + if (__HAL_RCC_GET_IT(RCC_IT_CSS)) + { + /* RCC Clock Security System interrupt user callback */ + HAL_RCC_CSSCallback(); + + /* Clear RCC CSS pending bit */ + __HAL_RCC_CLEAR_IT(RCC_IT_CSS); + } +} + +/** + * @brief RCC Clock Security System interrupt callback + * @retval None + */ +__weak void HAL_RCC_CSSCallback(void) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RCC_CSSCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c index 60b0a076..b09fb437 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc_ex.c @@ -1,1773 +1,1773 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extension RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extension peripheral: - * + Extended Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup RCCEx RCCEx - * @brief RCCEx HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Defines RCCEx Private Defines - * @{ - */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ -/** - * @} - */ - -/** @defgroup RCCEx_Private_Macros RCCEx Private Macros - * @{ - */ - -/** - * @} - */ - - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) and RCC_BDCR register will be set to their reset values. - -@endverbatim - * @{ - */ -#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \ - defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \ - defined (STM32F750xx) -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals - * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0; - uint32_t tmpreg0 = 0; - uint32_t tmpreg1 = 0; - uint32_t plli2sused = 0; - uint32_t pllsaiused = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*----------------------------------- I2S configuration ----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); - - /* Configure I2S Clock source */ - __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - - /* Enable the PLLI2S when it's used as clock source for I2S */ - if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - } - - /*------------------------------------ SAI1 configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - - /* Configure SAI1 Clock source */ - __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) - { - pllsaiused = 1; - } - } - - /*------------------------------------ SAI2 configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - - /* Configure SAI2 Clock source */ - __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) - { - pllsaiused = 1; - } - } - - /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - { - plli2sused = 1; - } - - /*------------------------------------ RTC configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR1 |= PWR_CR1_DBP; - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait for Backup domain Write protection disable */ - while((PWR->CR1 & PWR_CR1_DBP) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset the Backup domain only if the RTC Clock source selection is modified */ - tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); - - if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg0; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - - /*------------------------------------ TIM configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - /* Check the parameters */ - assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); - - /* Configure Timer Prescaler */ - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } - - /*-------------------------------------- I2C1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - } - - /*-------------------------------------- I2C2 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - - /* Configure the I2C2 clock source */ - __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - } - - /*-------------------------------------- I2C3 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - - /* Configure the I2C3 clock source */ - __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - } - - /*-------------------------------------- I2C4 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); - - /* Configure the I2C4 clock source */ - __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); - } - - /*-------------------------------------- USART1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - } - - /*-------------------------------------- USART2 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - } - - /*-------------------------------------- USART3 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - { - /* Check the parameters */ - assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - - /* Configure the USART3 clock source */ - __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - } - - /*-------------------------------------- UART4 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - { - /* Check the parameters */ - assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - - /* Configure the UART4 clock source */ - __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - } - - /*-------------------------------------- UART5 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - { - /* Check the parameters */ - assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - - /* Configure the UART5 clock source */ - __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - } - - /*-------------------------------------- USART6 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) - { - /* Check the parameters */ - assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); - - /* Configure the USART6 clock source */ - __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); - } - - /*-------------------------------------- UART7 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) - { - /* Check the parameters */ - assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); - - /* Configure the UART7 clock source */ - __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); - } - - /*-------------------------------------- UART8 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) - { - /* Check the parameters */ - assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); - - /* Configure the UART8 clock source */ - __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); - } - - /*--------------------------------------- CEC Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) - { - /* Check the parameters */ - assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); - - /* Configure the CEC clock source */ - __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); - } - - /*-------------------------------------- CK48 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) - { - /* Check the parameters */ - assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); - - /* Configure the CLK48 source */ - __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - - /* Enable the PLLSAI when it's used as clock source for CK48 */ - if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) - { - pllsaiused = 1; - } - } - - /*-------------------------------------- LTDC Configuration -----------------------------------*/ -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) - { - pllsaiused = 1; - } -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - - /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) - { - /* Check the parameters */ - assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - - /* Configure the LTPIM1 clock source */ - __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - } - - /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) - { - /* Check the parameters */ - assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - - /* Configure the SDMMC1 clock source */ - __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - } - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) - { - /* Check the parameters */ - assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); - - /* Configure the SDMMC2 clock source */ - __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); - } - - /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); - - /* Configure the DFSDM1 interface clock source */ - __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); - } - - /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) - { - /* Check the parameters */ - assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); - - /* Configure the DFSDM interface clock source */ - __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); - } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ - /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ - if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) - { - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* check for common PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - - /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ - tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) - { - /* Check for PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - /* Check for PLLI2S/DIVQ parameters */ - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - - /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - - /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); - - /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ - tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ - /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - { - /* Check for Parameters */ - assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ - /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - - /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ - /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ - if(pllsaiused == 1) - { - /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI is disabled */ - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* Check the PLLSAI division factors */ - assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) - { - /* check for PLLSAIQ Parameter */ - assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); - /* check for PLLSAI/DIVQ Parameter */ - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - - /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - - /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ - /* In Case of PLLI2S is selected as source clock for CK48 */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); - /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ - tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - - /* Configure the PLLSAI division factors */ - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ - /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); - } - -#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) - /*---------------------------- LTDC configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) - { - assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); - assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); - - /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ - tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); - - /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); - } -#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - - /* Enable PLLSAI Clock */ - __HAL_RCC_PLLSAI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI is ready */ - while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg = 0; - - /* Set all possible values for the extended clock type parameter------------*/ -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ - RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ - RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ - RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ - RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ - RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; -#else - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ - RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ - RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ - RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ - RCC_PERIPHCLK_CLK48; -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - /* Get the PLLI2S Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); - PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - - /* Get the PLLSAI Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); - PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); - - /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); - PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos); - - /* Get the SAI1 clock configuration ----------------------------------------------*/ - PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - - /* Get the SAI2 clock configuration ----------------------------------------------*/ - PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - - /* Get the I2S clock configuration ------------------------------------------*/ - PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); - - /* Get the I2C1 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - - /* Get the I2C2 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); - - /* Get the I2C3 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - - /* Get the I2C4 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); - - /* Get the USART1 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - - /* Get the USART2 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - - /* Get the USART3 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); - - /* Get the UART4 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); - - /* Get the UART5 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); - - /* Get the USART6 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); - - /* Get the UART7 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); - - /* Get the UART8 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); - - /* Get the LPTIM1 clock configuration ------------------------------------------*/ - PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - - /* Get the CEC clock configuration -----------------------------------------------*/ - PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); - - /* Get the CK48 clock configuration -----------------------------------------------*/ - PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - - /* Get the SDMMC1 clock configuration -----------------------------------------------*/ - PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); - -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - /* Get the SDMMC2 clock configuration -----------------------------------------------*/ - PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); - - /* Get the DFSDM clock configuration -----------------------------------------------*/ - PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); - - /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ - PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - - /* Get the RTC Clock configuration -----------------------------------------------*/ - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - - /* Get the TIM Prescaler configuration --------------------------------------------*/ - if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } -} -#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ - -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) -/** - * @brief Initializes the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains the configuration information for the Extended Peripherals - * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source; in this case the Backup domain will be reset in - * order to modify the RTC Clock source, as consequence RTC registers (including - * the backup registers) are set to their reset values. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tickstart = 0; - uint32_t tmpreg0 = 0; - uint32_t plli2sused = 0; - uint32_t pllsaiused = 0; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); - - /*----------------------------------- I2S configuration ----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) - { - /* Check the parameters */ - assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); - - /* Configure I2S Clock source */ - __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); - - /* Enable the PLLI2S when it's used as clock source for I2S */ - if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - } - - /*------------------------------------ SAI1 configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); - - /* Configure SAI1 Clock source */ - __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) - { - pllsaiused = 1; - } - } - - /*------------------------------------ SAI2 configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); - - /* Configure SAI2 Clock source */ - __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); - - /* Enable the PLLI2S when it's used as clock source for SAI */ - if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) - { - plli2sused = 1; - } - /* Enable the PLLSAI when it's used as clock source for SAI */ - if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) - { - pllsaiused = 1; - } - } - - /*------------------------------------ RTC configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) - { - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); - - /* Enable Power Clock*/ - __HAL_RCC_PWR_CLK_ENABLE(); - - /* Enable write access to Backup domain */ - PWR->CR1 |= PWR_CR1_DBP; - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait for Backup domain Write protection disable */ - while((PWR->CR1 & PWR_CR1_DBP) == RESET) - { - if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset the Backup domain only if the RTC Clock source selection is modified */ - tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); - - if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); - - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpreg0; - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); - } - - /*------------------------------------ TIM configuration --------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) - { - /* Check the parameters */ - assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); - - /* Configure Timer Prescaler */ - __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); - } - - /*-------------------------------------- I2C1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); - - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); - } - - /*-------------------------------------- I2C2 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); - - /* Configure the I2C2 clock source */ - __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); - } - - /*-------------------------------------- I2C3 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - - /* Configure the I2C3 clock source */ - __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); - } - - /*-------------------------------------- USART1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); - - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); - } - - /*-------------------------------------- USART2 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); - } - - /*-------------------------------------- USART3 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - { - /* Check the parameters */ - assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); - - /* Configure the USART3 clock source */ - __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); - } - - /*-------------------------------------- UART4 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - { - /* Check the parameters */ - assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); - - /* Configure the UART4 clock source */ - __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); - } - - /*-------------------------------------- UART5 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - { - /* Check the parameters */ - assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); - - /* Configure the UART5 clock source */ - __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); - } - - /*-------------------------------------- USART6 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) - { - /* Check the parameters */ - assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); - - /* Configure the USART6 clock source */ - __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); - } - - /*-------------------------------------- UART7 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) - { - /* Check the parameters */ - assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); - - /* Configure the UART7 clock source */ - __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); - } - - /*-------------------------------------- UART8 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) - { - /* Check the parameters */ - assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); - - /* Configure the UART8 clock source */ - __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); - } - - /*-------------------------------------- CK48 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) - { - /* Check the parameters */ - assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); - - /* Configure the CLK48 source */ - __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); - - /* Enable the PLLSAI when it's used as clock source for CK48 */ - if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) - { - pllsaiused = 1; - } - } - - /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) - { - /* Check the parameters */ - assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); - - /* Configure the LTPIM1 clock source */ - __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); - } - - /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) - { - /* Check the parameters */ - assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); - - /* Configure the SDMMC1 clock source */ - __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); - } - - /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) - { - /* Check the parameters */ - assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); - - /* Configure the SDMMC2 clock source */ - __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); - } - - /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ - /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ - if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) - { - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is disabled */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* check for common PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); - - /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - - /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ - tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ - /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) - { - /* Check for PLLI2S Parameters */ - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - /* Check for PLLI2S/DIVQ parameters */ - assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); - - /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ - tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); - } - - /*----------------- In Case of PLLI2S is just selected -----------------*/ - if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) - { - /* Check for Parameters */ - assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); - - /* Configure the PLLI2S division factors */ - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ - __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); - } - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLI2S is ready */ - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - - /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ - /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ - if(pllsaiused == 1) - { - /* Disable PLLSAI Clock */ - __HAL_RCC_PLLSAI_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI is disabled */ - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* Check the PLLSAI division factors */ - assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); - - /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ - if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ - ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) - { - /* check for PLLSAIQ Parameter */ - assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); - /* check for PLLSAI/DIVQ Parameter */ - assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); - - /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ - tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); - } - - /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ - /* In Case of PLLI2S is selected as source clock for CK48 */ - if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) - { - /* check for Parameters */ - assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); - /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ - tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - - /* Configure the PLLSAI division factors */ - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ - /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ - __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0); - } - - /* Enable PLLSAI Clock */ - __HAL_RCC_PLLSAI_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLLSAI is ready */ - while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal - * RCC configuration registers. - * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) -{ - uint32_t tempreg = 0; - - /* Set all possible values for the extended clock type parameter------------*/ - PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ - RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ - RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ - RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ - RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ - RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2; - - /* Get the PLLI2S Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); - PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); - PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); - - /* Get the PLLSAI Clock configuration -----------------------------------------------*/ - PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); - PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); - PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); - - /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ - PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); - PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); - - /* Get the SAI1 clock configuration ----------------------------------------------*/ - PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - - /* Get the SAI2 clock configuration ----------------------------------------------*/ - PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); - - /* Get the I2S clock configuration ------------------------------------------*/ - PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); - - /* Get the I2C1 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - - /* Get the I2C2 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); - - /* Get the I2C3 clock configuration ------------------------------------------*/ - PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - - /* Get the USART1 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - - /* Get the USART2 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - - /* Get the USART3 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); - - /* Get the UART4 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); - - /* Get the UART5 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); - - /* Get the USART6 clock configuration ------------------------------------------*/ - PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); - - /* Get the UART7 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); - - /* Get the UART8 clock configuration ------------------------------------------*/ - PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); - - /* Get the LPTIM1 clock configuration ------------------------------------------*/ - PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - - /* Get the CK48 clock configuration -----------------------------------------------*/ - PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); - - /* Get the SDMMC1 clock configuration -----------------------------------------------*/ - PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); - - /* Get the SDMMC2 clock configuration -----------------------------------------------*/ - PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); - - /* Get the RTC Clock configuration -----------------------------------------------*/ - tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); - PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); - - /* Get the TIM Prescaler configuration --------------------------------------------*/ - if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; - } - else - { - PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; - } -} -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ - -/** - * @brief Return the peripheral clock frequency for a given peripheral(SAI..) - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock - * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock - * @retval Frequency in KHz - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) -{ - uint32_t tmpreg = 0; - /* This variable is used to store the SAI clock frequency (value in Hz) */ - uint32_t frequency = 0; - /* This variable is used to store the VCO Input (value in Hz) */ - uint32_t vcoinput = 0; - /* This variable is used to store the SAI clock source */ - uint32_t saiclocksource = 0; - - if (PeriphClk == RCC_PERIPHCLK_SAI1) - { - saiclocksource = RCC->DCKCFGR1; - saiclocksource &= RCC_DCKCFGR1_SAI1SEL; - switch (saiclocksource) - { - case 0: /* PLLSAI is the clock source for SAI1 */ - { - /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; - frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); - frequency = frequency/(tmpreg); - break; - } - case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; - frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); - frequency = frequency/(tmpreg); - break; - } - case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ - { - frequency = EXTERNAL_CLOCK_VALUE; - break; - } -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the main PLL Source is HSI */ - frequency = HSI_VALUE; - } - else - { - /* In Case the main PLL Source is HSE */ - frequency = HSE_VALUE; - } - break; - } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - default : - { - break; - } - } - } - - if (PeriphClk == RCC_PERIPHCLK_SAI2) - { - saiclocksource = RCC->DCKCFGR1; - saiclocksource &= RCC_DCKCFGR1_SAI2SEL; - switch (saiclocksource) - { - case 0: /* PLLSAI is the clock source for SAI*/ - { - /* Configure the PLLSAI division factor */ - /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ - /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ - tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; - frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ - tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); - frequency = frequency/(tmpreg); - break; - } - case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ - { - /* Configure the PLLI2S division factor */ - /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the PLL Source is HSI (Internal Clock) */ - vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); - } - else - { - /* In Case the PLL Source is HSE (External Clock) */ - vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); - } - - /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ - /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ - tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; - frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); - - /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ - tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); - frequency = frequency/(tmpreg); - break; - } - case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ - { - frequency = EXTERNAL_CLOCK_VALUE; - break; - } -#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) - case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ - { - if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) - { - /* In Case the main PLL Source is HSI */ - frequency = HSI_VALUE; - } - else - { - /* In Case the main PLL Source is HSE */ - frequency = HSE_VALUE; - } - break; - } -#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ - default : - { - break; - } - } - } - - return frequency; -} - -/** - * @} - */ - -/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions - * @brief Extended Clock management functions - * -@verbatim - =============================================================================== - ##### Extended clock management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the - activation or deactivation of PLLI2S, PLLSAI. -@endverbatim - * @{ - */ - -/** - * @brief Enable PLLI2S. - * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that - * contains the configuration information for the PLLI2S - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) -{ - uint32_t tickstart; - - /* Check for parameters */ - assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); - assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); - assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); -#if defined(RCC_PLLI2SCFGR_PLLI2SP) - assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); -#endif /* RCC_PLLI2SCFGR_PLLI2SP */ - - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Wait till PLLI2S is disabled */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* Configure the PLLI2S division factors */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ - /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ - /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); -#else - /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ - /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ - /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ - /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ - __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ - - /* Enable the PLLI2S */ - __HAL_RCC_PLLI2S_ENABLE(); - - /* Wait till PLLI2S is ready */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Disable PLLI2S. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) -{ - uint32_t tickstart; - - /* Disable the PLLI2S */ - __HAL_RCC_PLLI2S_DISABLE(); - - /* Wait till PLLI2S is disabled */ - tickstart = HAL_GetTick(); - while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) - { - if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Enable PLLSAI. - * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that - * contains the configuration information for the PLLSAI - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) -{ - uint32_t tickstart; - - /* Check for parameters */ - assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); - assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); - assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); -#if defined(RCC_PLLSAICFGR_PLLSAIR) - assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); -#endif /* RCC_PLLSAICFGR_PLLSAIR */ - - /* Disable the PLLSAI */ - __HAL_RCC_PLLSAI_DISABLE(); - - /* Wait till PLLSAI is disabled */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - /* Configure the PLLSAI division factors */ -#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ - /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ - /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ - __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ); -#else - /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ - /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ - /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ - /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ - __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ - PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); -#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ - - /* Enable the PLLSAI */ - __HAL_RCC_PLLSAI_ENABLE(); - - /* Wait till PLLSAI is ready */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) - { - if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Disable PLLSAI. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) -{ - uint32_t tickstart; - - /* Disable the PLLSAI */ - __HAL_RCC_PLLSAI_DISABLE(); - - /* Wait till PLLSAI is disabled */ - tickstart = HAL_GetTick(); - while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) - { - if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) - { - /* return in case of Timeout detected */ - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_rcc_ex.c + * @author MCD Application Team + * @brief Extension RCC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities RCC extension peripheral: + * + Extended Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup RCCEx RCCEx + * @brief RCCEx HAL module driver + * @{ + */ + +#ifdef HAL_RCC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Defines RCCEx Private Defines + * @{ + */ +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ +/** + * @} + */ + +/** @defgroup RCCEx_Private_Macros RCCEx Private Macros + * @{ + */ + +/** + * @} + */ + + +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the RCC Clocks + frequencies. + [..] + (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to + select the RTC clock source; in this case the Backup domain will be reset in + order to modify the RTC Clock source, as consequence RTC registers (including + the backup registers) and RCC_BDCR register will be set to their reset values. + +@endverbatim + * @{ + */ +#if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F765xx) || \ + defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || \ + defined (STM32F750xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg0 = 0; + uint32_t tmpreg1 = 0; + uint32_t plli2sused = 0; + uint32_t pllsaiused = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- SPDIF-RX Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + plli2sused = 1; + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------------------- I2C4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection)); + + /* Configure the I2C4 clock source */ + __HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection); + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + } + + /*--------------------------------------- CEC Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) + { + /* Check the parameters */ + assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection)); + + /* Configure the CEC clock source */ + __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection); + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) + { + pllsaiused = 1; + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + } + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*------------------------------------- DFSDM1 Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection)); + + /* Configure the DFSDM1 interface clock source */ + __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); + } + + /*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) + { + /* Check the parameters */ + assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection)); + + /* Configure the DFSDM interface clock source */ + __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection); + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ + if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, tmpreg1, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, tmpreg0, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SPDIF-RX -------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + + /* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); + } + +#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) || defined (STM32F750xx) + /*---------------------------- LTDC configuration -------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) + { + assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR)); + assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR)); + + /* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, tmpreg0, PeriphClkInit->PLLSAI.PLLSAIR); + + /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); + } +#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg = 0; + + /* Set all possible values for the extended clock type parameter------------*/ +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\ + RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO; +#else + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48; +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos); + + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); + PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S clock configuration ------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); + + /* Get the I2C1 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the I2C4 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); + + /* Get the USART1 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the USART3 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + + /* Get the UART4 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + + /* Get the UART5 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + + /* Get the USART6 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + + /* Get the UART7 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + + /* Get the UART8 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + + /* Get the LPTIM1 clock configuration ------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the CEC clock configuration -----------------------------------------------*/ + PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE(); + + /* Get the CK48 clock configuration -----------------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the DFSDM clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE(); + + /* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/ + PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE(); +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the TIM Prescaler configuration --------------------------------------------*/ + if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} +#endif /* STM32F745xx || STM32F746xx || STM32F756xx || STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx || STM32F750xx */ + +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) +/** + * @brief Initializes the RCC extended peripherals clocks according to the specified + * parameters in the RCC_PeriphCLKInitTypeDef. + * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that + * contains the configuration information for the Extended Peripherals + * clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...). + * + * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select + * the RTC clock source; in this case the Backup domain will be reset in + * order to modify the RTC Clock source, as consequence RTC registers (including + * the backup registers) are set to their reset values. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tickstart = 0; + uint32_t tmpreg0 = 0; + uint32_t plli2sused = 0; + uint32_t pllsaiused = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*----------------------------------- I2S configuration ----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S)) + { + /* Check the parameters */ + assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection)); + + /* Configure I2S Clock source */ + __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection); + + /* Enable the PLLI2S when it's used as clock source for I2S */ + if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + } + + /*------------------------------------ SAI1 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection)); + + /* Configure SAI1 Clock source */ + __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ SAI2 configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2)) + { + /* Check the parameters */ + assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection)); + + /* Configure SAI2 Clock source */ + __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection); + + /* Enable the PLLI2S when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S) + { + plli2sused = 1; + } + /* Enable the PLLSAI when it's used as clock source for SAI */ + if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI) + { + pllsaiused = 1; + } + } + + /*------------------------------------ RTC configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + { + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + /* Enable Power Clock*/ + __HAL_RCC_PWR_CLK_ENABLE(); + + /* Enable write access to Backup domain */ + PWR->CR1 |= PWR_CR1_DBP; + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait for Backup domain Write protection disable */ + while((PWR->CR1 & PWR_CR1_DBP) == RESET) + { + if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL); + + if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))) + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL)); + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + __HAL_RCC_BACKUPRESET_RELEASE(); + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpreg0; + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON)) + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till LSE is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) + { + return HAL_TIMEOUT; + } + } + } + } + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + } + + /*------------------------------------ TIM configuration --------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM)) + { + /* Check the parameters */ + assert_param(IS_RCC_TIMPRES(PeriphClkInit->TIMPresSelection)); + + /* Configure Timer Prescaler */ + __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection); + } + + /*-------------------------------------- I2C1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + } + + /*-------------------------------------- I2C2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + } + + /*-------------------------------------- I2C3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } + + /*-------------------------------------- USART1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + } + + /*-------------------------------------- USART2 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + } + + /*-------------------------------------- USART3 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) + { + /* Check the parameters */ + assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection)); + + /* Configure the USART3 clock source */ + __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection); + } + + /*-------------------------------------- UART4 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) + { + /* Check the parameters */ + assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection)); + + /* Configure the UART4 clock source */ + __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection); + } + + /*-------------------------------------- UART5 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) + { + /* Check the parameters */ + assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection)); + + /* Configure the UART5 clock source */ + __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection); + } + + /*-------------------------------------- USART6 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) + { + /* Check the parameters */ + assert_param(IS_RCC_USART6CLKSOURCE(PeriphClkInit->Usart6ClockSelection)); + + /* Configure the USART6 clock source */ + __HAL_RCC_USART6_CONFIG(PeriphClkInit->Usart6ClockSelection); + } + + /*-------------------------------------- UART7 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) + { + /* Check the parameters */ + assert_param(IS_RCC_UART7CLKSOURCE(PeriphClkInit->Uart7ClockSelection)); + + /* Configure the UART7 clock source */ + __HAL_RCC_UART7_CONFIG(PeriphClkInit->Uart7ClockSelection); + } + + /*-------------------------------------- UART8 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) + { + /* Check the parameters */ + assert_param(IS_RCC_UART8CLKSOURCE(PeriphClkInit->Uart8ClockSelection)); + + /* Configure the UART8 clock source */ + __HAL_RCC_UART8_CONFIG(PeriphClkInit->Uart8ClockSelection); + } + + /*-------------------------------------- CK48 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) + { + /* Check the parameters */ + assert_param(IS_RCC_CLK48SOURCE(PeriphClkInit->Clk48ClockSelection)); + + /* Configure the CLK48 source */ + __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection); + + /* Enable the PLLSAI when it's used as clock source for CK48 */ + if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP) + { + pllsaiused = 1; + } + } + + /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LTPIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + } + + /*------------------------------------- SDMMC1 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection)); + + /* Configure the SDMMC1 clock source */ + __HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection); + } + + /*------------------------------------- SDMMC2 Configuration ------------------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) + { + /* Check the parameters */ + assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection)); + + /* Configure the SDMMC2 clock source */ + __HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection); + } + + /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ + /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2 or I2S */ + if((plli2sused == 1) || ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)) + { + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is disabled */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* check for common PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + + /*----------------- In Case of PLLI2S is selected as source clock for I2S -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) && (PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLLI2S))) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + + /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */ + /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , tmpreg0, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /*----------------- In Case of PLLI2S is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) || + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S))) + { + /* Check for PLLI2S Parameters */ + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + /* Check for PLLI2S/DIVQ parameters */ + assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ)); + + /* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, tmpreg0); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ); + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLI2SM) */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLI2S is ready */ + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + + /*-------------------------------------- PLLSAI Configuration ---------------------------------*/ + /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, LTDC or CK48 */ + if(pllsaiused == 1) + { + /* Disable PLLSAI Clock */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is disabled */ + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Check the PLLSAI division factors */ + assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN)); + + /*----------------- In Case of PLLSAI is selected as source clock for SAI -------------------*/ + if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||\ + ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI))) + { + /* check for PLLSAIQ Parameter */ + assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ)); + /* check for PLLSAI/DIVQ Parameter */ + assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ)); + + /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg0, PeriphClkInit->PLLSAI.PLLSAIQ); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ); + } + + /*----------------- In Case of PLLSAI is selected as source clock for CLK48 -------------------*/ + /* In Case of PLLI2S is selected as source clock for CK48 */ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48SOURCE_PLLSAIP)) + { + /* check for Parameters */ + assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP)); + /* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */ + tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + + /* Configure the PLLSAI division factors */ + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */ + /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */ + __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0); + } + + /* Enable PLLSAI Clock */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + + /* Wait till PLLSAI is ready */ + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Get the RCC_PeriphCLKInitTypeDef according to the internal + * RCC configuration registers. + * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure + * @retval None + */ +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + uint32_t tempreg = 0; + + /* Set all possible values for the extended clock type parameter------------*/ + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\ + RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\ + RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\ + RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\ + RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\ + RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\ + RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\ + RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\ + RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2; + + /* Get the PLLI2S Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); + PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos); + PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos); + + /* Get the PLLSAI Clock configuration -----------------------------------------------*/ + PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); + PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos); + PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos); + + /* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/ + PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos); + PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos); + + /* Get the SAI1 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); + + /* Get the SAI2 clock configuration ----------------------------------------------*/ + PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); + + /* Get the I2S clock configuration ------------------------------------------*/ + PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2SCLKSOURCE(); + + /* Get the I2C1 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); + + /* Get the I2C2 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); + + /* Get the I2C3 clock configuration ------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); + + /* Get the USART1 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); + + /* Get the USART2 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); + + /* Get the USART3 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); + + /* Get the UART4 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); + + /* Get the UART5 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); + + /* Get the USART6 clock configuration ------------------------------------------*/ + PeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); + + /* Get the UART7 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart7ClockSelection = __HAL_RCC_GET_UART7_SOURCE(); + + /* Get the UART8 clock configuration ------------------------------------------*/ + PeriphClkInit->Uart8ClockSelection = __HAL_RCC_GET_UART8_SOURCE(); + + /* Get the LPTIM1 clock configuration ------------------------------------------*/ + PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); + + /* Get the CK48 clock configuration -----------------------------------------------*/ + PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE(); + + /* Get the SDMMC1 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE(); + + /* Get the SDMMC2 clock configuration -----------------------------------------------*/ + PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE(); + + /* Get the RTC Clock configuration -----------------------------------------------*/ + tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE); + PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL)); + + /* Get the TIM Prescaler configuration --------------------------------------------*/ + if ((RCC->DCKCFGR1 & RCC_DCKCFGR1_TIMPRE) == RESET) + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED; + } + else + { + PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED; + } +} +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + +/** + * @brief Return the peripheral clock frequency for a given peripheral(SAI..) + * @note Return 0 if peripheral clock identifier not managed by this API + * @param PeriphClk Peripheral clock identifier + * This parameter can be one of the following values: + * @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock + * @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock + * @retval Frequency in KHz + */ +uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) +{ + uint32_t tmpreg = 0; + /* This variable is used to store the SAI clock frequency (value in Hz) */ + uint32_t frequency = 0; + /* This variable is used to store the VCO Input (value in Hz) */ + uint32_t vcoinput = 0; + /* This variable is used to store the SAI clock source */ + uint32_t saiclocksource = 0; + + if (PeriphClk == RCC_PERIPHCLK_SAI1) + { + saiclocksource = RCC->DCKCFGR1; + saiclocksource &= RCC_DCKCFGR1_SAI1SEL; + switch (saiclocksource) + { + case 0: /* PLLSAI is the clock source for SAI1 */ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI1SEL_0: /* PLLI2S is the clock source for SAI1 */ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI1SEL_1: /* External clock is the clock source for SAI1 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + default : + { + break; + } + } + } + + if (PeriphClk == RCC_PERIPHCLK_SAI2) + { + saiclocksource = RCC->DCKCFGR1; + saiclocksource &= RCC_DCKCFGR1_SAI2SEL; + switch (saiclocksource) + { + case 0: /* PLLSAI is the clock source for SAI*/ + { + /* Configure the PLLSAI division factor */ + /* PLLSAI_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */ + /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */ + tmpreg = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24; + frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */ + tmpreg = (((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> 8) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI2SEL_0: /* PLLI2S is the clock source for SAI2 */ + { + /* Configure the PLLI2S division factor */ + /* PLLI2S_VCO Input = PLL_SOURCE/PLLM */ + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the PLL Source is HSI (Internal Clock) */ + vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)); + } + else + { + /* In Case the PLL Source is HSE (External Clock) */ + vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM))); + } + + /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */ + /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */ + tmpreg = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24; + frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg); + + /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */ + tmpreg = ((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) + 1); + frequency = frequency/(tmpreg); + break; + } + case RCC_DCKCFGR1_SAI2SEL_1: /* External clock is the clock source for SAI2 */ + { + frequency = EXTERNAL_CLOCK_VALUE; + break; + } +#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx) + case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */ + { + if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI) + { + /* In Case the main PLL Source is HSI */ + frequency = HSI_VALUE; + } + else + { + /* In Case the main PLL Source is HSE */ + frequency = HSE_VALUE; + } + break; + } +#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */ + default : + { + break; + } + } + } + + return frequency; +} + +/** + * @} + */ + +/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions + * @brief Extended Clock management functions + * +@verbatim + =============================================================================== + ##### Extended clock management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the + activation or deactivation of PLLI2S, PLLSAI. +@endverbatim + * @{ + */ + +/** + * @brief Enable PLLI2S. + * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that + * contains the configuration information for the PLLI2S + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN)); + assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ)); +#if defined(RCC_PLLI2SCFGR_PLLI2SP) + assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP)); +#endif /* RCC_PLLI2SCFGR_PLLI2SP */ + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLI2S division factors */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#else + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */ + /* I2SPCLK = PLLI2S_VCO / PLLI2SP */ + /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */ + /* I2SRCLK = PLLI2S_VCO / PLLI2SR */ + __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR); +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + + /* Enable the PLLI2S */ + __HAL_RCC_PLLI2S_ENABLE(); + + /* Wait till PLLI2S is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLI2S. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void) +{ + uint32_t tickstart; + + /* Disable the PLLI2S */ + __HAL_RCC_PLLI2S_DISABLE(); + + /* Wait till PLLI2S is disabled */ + tickstart = HAL_GetTick(); + while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET) + { + if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Enable PLLSAI. + * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that + * contains the configuration information for the PLLSAI + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit) +{ + uint32_t tickstart; + + /* Check for parameters */ + assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN)); + assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ)); + assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP)); +#if defined(RCC_PLLSAICFGR_PLLSAIR) + assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR)); +#endif /* RCC_PLLSAICFGR_PLLSAIR */ + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + /* Configure the PLLSAI division factors */ +#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F730xx) + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ); +#else + /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */ + /* SAIPCLK = PLLSAI_VCO / PLLSAIP */ + /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */ + /* SAIRCLK = PLLSAI_VCO / PLLSAIR */ + __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \ + PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR); +#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F730xx */ + + /* Enable the PLLSAI */ + __HAL_RCC_PLLSAI_ENABLE(); + + /* Wait till PLLSAI is ready */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET) + { + if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @brief Disable PLLSAI. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void) +{ + uint32_t tickstart; + + /* Disable the PLLSAI */ + __HAL_RCC_PLLSAI_DISABLE(); + + /* Wait till PLLSAI is disabled */ + tickstart = HAL_GetTick(); + while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET) + { + if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE) + { + /* return in case of Timeout detected */ + return HAL_TIMEOUT; + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_RCC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c deleted file mode 100644 index 7a44c372..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rng.c +++ /dev/null @@ -1,873 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rng.c - * @author MCD Application Team - * @brief RNG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Random Number Generator (RNG) peripheral: - * + Initialization and configuration functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The RNG HAL driver can be used as follows: - - (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro - in HAL_RNG_MspInit(). - (#) Activate the RNG peripheral using HAL_RNG_Init() function. - (#) Wait until the 32 bit Random Number Generator contains a valid - random data using (polling/interrupt) mode. - (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_RNG_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_RNG_RegisterCallback() to register a user callback. - Function HAL_RNG_RegisterCallback() allows to register following callbacks: - (+) ErrorCallback : RNG Error Callback. - (+) MspInitCallback : RNG MspInit. - (+) MspDeInitCallback : RNG MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. - HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) ErrorCallback : RNG Error Callback. - (+) MspInitCallback : RNG MspInit. - (+) MspDeInitCallback : RNG MspDeInit. - - [..] - For specific callback ReadyDataCallback, use dedicated register callbacks: - respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). - - [..] - By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET - all callbacks are set to the corresponding weak (overridden) functions: - example HAL_RNG_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (overridden) functions in the HAL_RNG_Init() - and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_RNG_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() - or HAL_RNG_Init() function. - - [..] - When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak (overridden) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#if defined (RNG) - -/** @addtogroup RNG - * @brief RNG HAL module driver. - * @{ - */ - -#ifdef HAL_RNG_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Private_Constants RNG Private Constants - * @{ - */ -#define RNG_TIMEOUT_VALUE 2U -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private functions prototypes ----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup RNG_Exported_Functions - * @{ - */ - -/** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize the RNG according to the specified parameters - in the RNG_InitTypeDef and create the associated handle - (+) DeInitialize the RNG peripheral - (+) Initialize the RNG MSP - (+) DeInitialize RNG MSP - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RNG peripheral and creates the associated handle. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) -{ - /* Check the RNG handle allocation */ - if (hrng == NULL) - { - return HAL_ERROR; - } - /* Check the parameters */ - assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); - -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) - if (hrng->State == HAL_RNG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrng->Lock = HAL_UNLOCKED; - - hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ - hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hrng->MspInitCallback == NULL) - { - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hrng->MspInitCallback(hrng); - } -#else - if (hrng->State == HAL_RNG_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrng->Lock = HAL_UNLOCKED; - - /* Init the low level hardware */ - HAL_RNG_MspInit(hrng); - } -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - - /* Enable the RNG Peripheral */ - __HAL_RNG_ENABLE(hrng); - - /* Initialize the RNG state */ - hrng->State = HAL_RNG_STATE_READY; - - /* Initialise the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_NONE; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief DeInitializes the RNG peripheral. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) -{ - /* Check the RNG handle allocation */ - if (hrng == NULL) - { - return HAL_ERROR; - } - - /* Disable the RNG Peripheral */ - CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); - - /* Clear RNG interrupt status flags */ - CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); - -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) - if (hrng->MspDeInitCallback == NULL) - { - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hrng->MspDeInitCallback(hrng); -#else - /* DeInit the low level hardware */ - HAL_RNG_MspDeInit(hrng); -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - - /* Update the RNG state */ - hrng->State = HAL_RNG_STATE_RESET; - - /* Initialise the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hrng); - - /* Return the function status */ - return HAL_OK; -} - -/** - * @brief Initializes the RNG MSP. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval None - */ -__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitializes the RNG MSP. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval None - */ -__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_MspDeInit must be implemented in the user file. - */ -} - -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User RNG Callback - * To be used instead of the weak predefined callback - * @param hrng RNG handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID - * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, - pRNG_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - - if (HAL_RNG_STATE_READY == hrng->State) - { - switch (CallbackID) - { - case HAL_RNG_ERROR_CB_ID : - hrng->ErrorCallback = pCallback; - break; - - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = pCallback; - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_RNG_STATE_RESET == hrng->State) - { - switch (CallbackID) - { - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = pCallback; - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an RNG Callback - * RNG callback is redirected to the weak predefined callback - * @param hrng RNG handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_RNG_ERROR_CB_ID Error callback ID - * @arg @ref HAL_RNG_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_RNG_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - - if (HAL_RNG_STATE_READY == hrng->State) - { - switch (CallbackID) - { - case HAL_RNG_ERROR_CB_ID : - hrng->ErrorCallback = HAL_RNG_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_RNG_STATE_RESET == hrng->State) - { - switch (CallbackID) - { - case HAL_RNG_MSPINIT_CB_ID : - hrng->MspInitCallback = HAL_RNG_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_RNG_MSPDEINIT_CB_ID : - hrng->MspDeInitCallback = HAL_RNG_MspDeInit; /* Legacy weak MspInit */ - break; - - default : - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Register Data Ready RNG Callback - * To be used instead of the weak HAL_RNG_ReadyDataCallback() predefined callback - * @param hrng RNG handle - * @param pCallback pointer to the Data Ready Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hrng); - - if (HAL_RNG_STATE_READY == hrng->State) - { - hrng->ReadyDataCallback = pCallback; - } - else - { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hrng); - return status; -} - -/** - * @brief UnRegister the Data Ready RNG Callback - * Data Ready RNG Callback is redirected to the weak HAL_RNG_ReadyDataCallback() predefined callback - * @param hrng RNG handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hrng); - - if (HAL_RNG_STATE_READY == hrng->State) - { - hrng->ReadyDataCallback = HAL_RNG_ReadyDataCallback; /* Legacy weak ReadyDataCallback */ - } - else - { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hrng); - return status; -} - -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup RNG_Exported_Functions_Group2 - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Get the 32 bit Random number - (+) Get the 32 bit Random number with interrupt enabled - (+) Handle RNG interrupt request - -@endverbatim - * @{ - */ - -/** - * @brief Generates a 32-bit random number. - * @note This function checks value of RNG_FLAG_DRDY flag to know if valid - * random number is available in the DR register (RNG_FLAG_DRDY flag set - * whenever a random number is available through the RNG_DR register). - * After transitioning from 0 to 1 (random number available), - * RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading - * four words from the RNG_DR register, i.e. further function calls - * will immediately return a new u32 random number (additional words are - * available and can be read by the application, till RNG_FLAG_DRDY flag remains high). - * @note When no more random number data is available in DR register, RNG_FLAG_DRDY - * flag is automatically cleared. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @param random32bit pointer to generated random number variable if successful. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) -{ - uint32_t tickstart; - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hrng); - - /* Check RNG peripheral state */ - if (hrng->State == HAL_RNG_STATE_READY) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check if data register contains valid random data */ - while (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) - { - if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) - { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; - } - } - } - - /* Get a 32bit Random number */ - hrng->RandomNumber = hrng->Instance->DR; - *random32bit = hrng->RandomNumber; - - hrng->State = HAL_RNG_STATE_READY; - } - else - { - hrng->ErrorCode = HAL_RNG_ERROR_BUSY; - status = HAL_ERROR; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - return status; -} - -/** - * @brief Generates a 32-bit random number in interrupt mode. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hrng); - - /* Check RNG peripheral state */ - if (hrng->State == HAL_RNG_STATE_READY) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); - } - else - { - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - - hrng->ErrorCode = HAL_RNG_ERROR_BUSY; - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Returns generated random number in polling mode (Obsolete) - * Use HAL_RNG_GenerateRandomNumber() API instead. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval Random value - */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) -{ - if (HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK) - { - return hrng->RandomNumber; - } - else - { - return 0U; - } -} - -/** - * @brief Returns a 32-bit random number with interrupt enabled (Obsolete), - * Use HAL_RNG_GenerateRandomNumber_IT() API instead. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval 32-bit random number - */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) -{ - uint32_t random32bit = 0U; - - /* Process locked */ - __HAL_LOCK(hrng); - - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get a 32bit Random number */ - random32bit = hrng->Instance->DR; - - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); - - /* Return the 32 bit random number */ - return random32bit; -} - -/** - * @brief Handles RNG interrupt request. - * @note In the case of a clock error, the RNG is no more able to generate - * random numbers because the PLL48CLK clock is not correct. User has - * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). - * The clock error has no impact on the previously generated - * random numbers, and the RNG_DR register contents can be used. - * @note In the case of a seed error, the generation of random numbers is - * interrupted as long as the SECS bit is '1'. If a number is - * available in the RNG_DR register, it must not be used because it may - * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable - * the RNG peripheral to reinitialize and restart the RNG. - * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS - * or CEIS are set. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval None - - */ -void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) -{ - uint32_t rngclockerror = 0U; - uint32_t itflag = hrng->Instance->SR; - - /* RNG clock error interrupt occurred */ - if ((itflag & RNG_IT_CEI) == RNG_IT_CEI) - { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_CLOCK; - rngclockerror = 1U; - } - else if ((itflag & RNG_IT_SEI) == RNG_IT_SEI) - { - /* Update the error code */ - hrng->ErrorCode = HAL_RNG_ERROR_SEED; - rngclockerror = 1U; - } - else - { - /* Nothing to do */ - } - - if (rngclockerror == 1U) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_ERROR; - -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) - /* Call registered Error callback */ - hrng->ErrorCallback(hrng); -#else - /* Call legacy weak Error callback */ - HAL_RNG_ErrorCallback(hrng); -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - - /* Clear the clock error flag */ - __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); - - return; - } - - /* Check RNG data ready interrupt occurred */ - if ((itflag & RNG_IT_DRDY) == RNG_IT_DRDY) - { - /* Generate random number once, so disable the IT */ - __HAL_RNG_DISABLE_IT(hrng); - - /* Get the 32bit Random number (DRDY flag automatically cleared) */ - hrng->RandomNumber = hrng->Instance->DR; - - if (hrng->State != HAL_RNG_STATE_ERROR) - { - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - -#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) - /* Call registered Data Ready callback */ - hrng->ReadyDataCallback(hrng, hrng->RandomNumber); -#else - /* Call legacy weak Data Ready callback */ - HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); -#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ - } - } -} - -/** - * @brief Read latest generated random number. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval random value - */ -uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng) -{ - return (hrng->RandomNumber); -} - -/** - * @brief Data Ready callback in non-blocking mode. - * @note When RNG_FLAG_DRDY flag value is set, first random number has been read - * from DR register in IRQ Handler and is provided as callback parameter. - * Depending on valid data available in the conditioning output buffer, - * additional words can be read by the application from DR register till - * DRDY bit remains high. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @param random32bit generated random number. - * @retval None - */ -__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - UNUSED(random32bit); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_ReadyDataCallback must be implemented in the user file. - */ -} - -/** - * @brief RNG error callbacks. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval None - */ -__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrng); - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_RNG_ErrorCallback must be implemented in the user file. - */ -} -/** - * @} - */ - - -/** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the RNG state. - * @param hrng pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval HAL state - */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng) -{ - return hrng->State; -} - -/** - * @brief Return the RNG handle error code. - * @param hrng: pointer to a RNG_HandleTypeDef structure. - * @retval RNG Error Code - */ -uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng) -{ - /* Return RNG Error Code */ - return hrng->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - - -#endif /* HAL_RNG_MODULE_ENABLED */ -/** - * @} - */ - -#endif /* RNG */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c deleted file mode 100644 index 413a4177..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc.c +++ /dev/null @@ -1,1920 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rtc.c - * @author MCD Application Team - * @brief RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) peripheral: - * + Initialization and de-initialization functions - * + RTC Calendar (Time and Date) configuration functions - * + RTC Alarms (Alarm A and Alarm B) configuration functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### RTC and Backup Domain Operating Condition ##### - ============================================================================== - [..] The real-time clock (RTC), the RTC backup registers, and the backup - SRAM (BKP SRAM) can be powered from the VBAT voltage when the main - VDD supply is powered off. - To retain the content of the RTC backup registers, BKP SRAM, and supply - the RTC when VDD is turned off, VBAT pin can be connected to an optional - standby voltage supplied by a battery or by another source. - - [..] To allow the RTC operating even when the main digital supply (VDD) is turned - off, the VBAT pin powers the following blocks: - (#) The RTC - (#) The LSE oscillator - (#) The BKP SRAM when the low power backup regulator is enabled - (#) PC13 to PC15 I/Os, plus PI8 and PC1 I/Os (when available) - - [..] When the backup domain is supplied by VDD (analog switch connected to VDD), - the following pins are available: - (#) PC14 and PC15 can be used as either GPIO or LSE pins - (#) PC13 can be used as a GPIO or as the RTC_AF1 pin - (#) PI8 can be used as a GPIO or as the RTC_AF2 pin - (#) PC1 can be used as a GPIO or as the RTC_AF3 pin - - [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT - because VDD is not present), the following pins are available: - (#) PC14 and PC15 can be used as LSE pins only - (#) PC13 can be used as the RTC_AF1 pin - (#) PI8 can be used as the RTC_AF2 pin - (#) PC1 can be used as the RTC_AF3 pin - - ##### Backup Domain Reset ##### - ================================================================== - [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. - The BKP SRAM is not affected by this reset. The only way to reset the BKP - SRAM is through the Flash interface by requesting a protection level - change from 1 to 0. - [..] A backup domain reset is generated when one of the following events occurs: - (#) Software reset, triggered by setting the BDRST bit in the - RCC Backup domain control register (RCC_BDCR). - (#) VDD or VBAT power on, if both supplies have previously been powered off. - (#) Tamper detection event resets all data backup registers. - - ##### Backup Domain Access ##### - ================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data registers - and BKP SRAM) is protected against possible unwanted write accesses. - [..] To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() macro. - (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. - - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable the RTC domain access (see description in the section above). - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** Time and Date configuration *** - =================================== - [..] - (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() - and HAL_RTC_SetDate() functions. - (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() - functions. - (+) To manage the RTC summer or winter time change, use the following - functions: - (++) HAL_RTC_DST_Add1Hour() or HAL_RTC_DST_Sub1Hour to add or subtract - 1 hour from the calendar time. - (++) HAL_RTC_DST_SetStoreOperation() or HAL_RTC_DST_ClearStoreOperation - to memorize whether the time change has been performed or not. - - *** Alarm configuration *** - =========================== - [..] - (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the - HAL_RTC_SetAlarm_IT() function. - (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. - - ##### RTC and low power modes ##### - ================================================================== - [..] The MCU can be woken up from a low power mode by an RTC alternate - function. - [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wakeup, RTC tamper event detection and RTC timestamp event detection. - These RTC alternate functions can wake up the system from the Stop and - Standby low power modes. - [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wakeup mode), by using the RTC alarm - or the RTC wakeup events. - [..] The RTC provides a programmable time base for waking up from the - Stop or Standby mode at regular intervals. - Wakeup from STOP and STANDBY modes is possible only when the RTC clock - source is LSE or LSI. - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. - [..] - Function HAL_RTC_RegisterCallback() allows to register following callbacks: - (+) AlarmAEventCallback : RTC Alarm A Event callback. - (+) AlarmBEventCallback : RTC Alarm B Event callback. - (+) TimeStampEventCallback : RTC Timestamp Event callback. - (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. - (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) Tamper2EventCallback : RTC Tamper 2 Event callback. - (+) Tamper3EventCallback : RTC Tamper 3 Event callback. - (+) MspInitCallback : RTC MspInit callback. - (+) MspDeInitCallback : RTC MspDeInit callback. - [..] - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - [..] - Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) AlarmAEventCallback : RTC Alarm A Event callback. - (+) AlarmBEventCallback : RTC Alarm B Event callback. - (+) TimeStampEventCallback : RTC Timestamp Event callback. - (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. - (+) Tamper1EventCallback : RTC Tamper 1 Event callback. - (+) Tamper2EventCallback : RTC Tamper 2 Event callback. - (+) Tamper3EventCallback : RTC Tamper 3 Event callback. - (+) MspInitCallback : RTC MspInit callback. - (+) MspDeInitCallback : RTC MspDeInit callback. - [..] - By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, - all callbacks are set to the corresponding weak functions: - examples AlarmAEventCallback(), WakeUpTimerEventCallback(). - Exception done for MspInit() and MspDeInit() callbacks that are reset to the - legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only - when these callbacks are null (not registered beforehand). - If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit() - keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand). - [..] - Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. - Exception done MspInit()/MspDeInit() that can be registered/unregistered - in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state. - Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the - Init/DeInit. - In that case first register the MspInit()/MspDeInit() user callbacks - using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() - or HAL_RTC_Init() functions. - [..] - When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all - callbacks are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup RTC RTC - * @brief RTC HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RTC_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to initialize and configure the - RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable - RTC registers Write protection, enter and exit the RTC initialization mode, - RTC registers synchronization check and reference clock detection enable. - (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. - It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. - (++) When both prescalers are used, it is recommended to configure the - asynchronous prescaler to a high value to minimize power consumption. - (#) All RTC registers are Write protected. Writing to the RTC registers - is enabled by writing a key into the Write Protection register, RTC_WPR. - (#) To configure the RTC Calendar, user application should enter - initialization mode. In this mode, the calendar counter is stopped - and its value can be updated. When the initialization sequence is - complete, the calendar restarts counting after 4 RTCCLK cycles. - (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wakeup from low power modes - the software must first clear the RSF flag. The software must then - wait until it is set again before reading the calendar, which means - that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function - implements the above software sequence (RSF clear and RSF check). - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the RTC peripheral - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check RTC handler validity */ - if (hrtc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); - assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); - assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); - assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if (hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ - hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ - hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ - hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ - hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ - - if (hrtc->MspInitCallback == NULL) - { - hrtc->MspInitCallback = HAL_RTC_MspInit; - } - /* Init the low level hardware */ - hrtc->MspInitCallback(hrtc); - - if (hrtc->MspDeInitCallback == NULL) - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } - } -#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ - if (hrtc->State == HAL_RTC_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hrtc->Lock = HAL_UNLOCKED; - - /* Initialize RTC MSP */ - HAL_RTC_MspInit(hrtc); - } -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Check whether the calendar needs to be initialized */ - if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) - { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - - if (status == HAL_OK) - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); - - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); - } - - if (status == HAL_OK) - { - hrtc->Instance->OR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL; - hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType); - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - } - else - { - /* The calendar is already initialized */ - status = HAL_OK; - } - - if (status == HAL_OK) - { - hrtc->State = HAL_RTC_STATE_READY; - } - - return status; -} - -/** - * @brief DeInitializes the RTC peripheral - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This function does not reset the RTC Backup Data registers. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - - if (status == HAL_OK) - { - /* Reset RTC registers */ - hrtc->Instance->TR = 0x00000000U; - hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0); - hrtc->Instance->CR &= 0x00000000U; - hrtc->Instance->WUTR = RTC_WUTR_WUT; - hrtc->Instance->PRER = (uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU); - hrtc->Instance->ALRMAR = 0x00000000U; - hrtc->Instance->ALRMBR = 0x00000000U; - hrtc->Instance->CALR = 0x00000000U; - hrtc->Instance->SHIFTR = 0x00000000U; - hrtc->Instance->ALRMASSR = 0x00000000U; - hrtc->Instance->ALRMBSSR = 0x00000000U; - - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - if (status == HAL_OK) - { - /* Reset Tamper and alternate functions configuration register */ - hrtc->Instance->TAMPCR = 0x00000000U; - - /* Reset Option register */ - hrtc->Instance->OR = 0x00000000U; - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if (hrtc->MspDeInitCallback == NULL) - { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } - - /* DeInit the low level hardware: CLOCK, NVIC.*/ - hrtc->MspDeInitCallback(hrtc); -#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - hrtc->State = HAL_RTC_STATE_RESET; - } - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return status; -} - -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -/** - * @brief Registers a User RTC Callback - * To be used instead of the weak predefined callback - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID - * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID - * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID - * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID - * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hrtc); - - if (HAL_RTC_STATE_READY == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = pCallback; - break; - - case HAL_RTC_ALARM_B_EVENT_CB_ID : - hrtc->AlarmBEventCallback = pCallback; - break; - - case HAL_RTC_TIMESTAMP_EVENT_CB_ID : - hrtc->TimeStampEventCallback = pCallback; - break; - - case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : - hrtc->WakeUpTimerEventCallback = pCallback; - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = pCallback; - break; - - case HAL_RTC_TAMPER2_EVENT_CB_ID : - hrtc->Tamper2EventCallback = pCallback; - break; - - case HAL_RTC_TAMPER3_EVENT_CB_ID : - hrtc->Tamper3EventCallback = pCallback; - break; - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_RTC_STATE_RESET == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return status; -} - -/** - * @brief Unregisters an RTC Callback - * RTC callback is redirected to the weak predefined callback - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID - * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID - * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID - * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID - * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID - * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID - * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID - * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID - * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hrtc); - - if (HAL_RTC_STATE_READY == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - break; - - case HAL_RTC_ALARM_B_EVENT_CB_ID : - hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ - break; - - case HAL_RTC_TIMESTAMP_EVENT_CB_ID : - hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ - break; - - case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : - hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ - break; - - case HAL_RTC_TAMPER2_EVENT_CB_ID : - hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ - break; - - case HAL_RTC_TAMPER3_EVENT_CB_ID : - hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ - break; - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_RTC_STATE_RESET == hrtc->State) - { - switch (CallbackID) - { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hrtc); - - return status; -} -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - -/** - * @brief Initializes the RTC MSP. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the RTC MSP. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions - * @brief RTC Time and Date functions - * -@verbatim - =============================================================================== - ##### RTC Time and Date functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Time and Date features - -@endverbatim - * @{ - */ - -/** - * @brief Sets RTC current time. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTime Pointer to Time structure - * @note DayLightSaving and StoreOperation interfaces are deprecated. - * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions. - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0U; - HAL_StatusTypeDef status; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); - assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if (Format == RTC_FORMAT_BIN) - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(sTime->Hours)); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(sTime->Hours)); - } - assert_param(IS_RTC_MINUTES(sTime->Minutes)); - assert_param(IS_RTC_SECONDS(sTime->Seconds)); - - tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ - ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ - ( (uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); - } - else - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); - assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); - } - else - { - sTime->TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours))); - } - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ - ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ - ((uint32_t) sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - - if (status == HAL_OK) - { - /* Set the RTC_TR register */ - hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - - /* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; - - /* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ - hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); - - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); - } - - if (status == HAL_OK) - { - hrtc->State = HAL_RTC_STATE_READY; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return status; -} - -/** - * @brief Gets RTC current time. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTime Pointer to Time structure - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You can use SubSeconds and SecondFraction (sTime structure fields - * returned) to convert SubSeconds value in second fraction ratio with - * time unit following generic formula: - * Second fraction ratio * time_unit = - * [(SecondFraction - SubSeconds) / (SecondFraction + 1)] * time_unit - * This conversion can be performed only if no shift operation is pending - * (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the - * values in the higher-order calendar shadow registers to ensure - * consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers - * until current date is read to ensure consistency between the time and - * date values. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get subseconds value from the corresponding register */ - sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); - - /* Get SecondFraction structure field from the corresponding register field*/ - sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S); - - /* Get the TR register */ - tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); - sTime->Seconds = (uint8_t)( tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); - - /* Check the input parameters format */ - if (Format == RTC_FORMAT_BIN) - { - /* Convert the time structure parameters to Binary format */ - sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); - sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes); - sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds); - } - - return HAL_OK; -} - -/** - * @brief Sets RTC current date. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sDate Pointer to date structure - * @param Format specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0U; - HAL_StatusTypeDef status; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) - { - sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); - } - - assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - - if (Format == RTC_FORMAT_BIN) - { - assert_param(IS_RTC_YEAR(sDate->Year)); - assert_param(IS_RTC_MONTH(sDate->Month)); - assert_param(IS_RTC_DATE(sDate->Date)); - - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); - } - else - { - assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year))); - assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); - assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); - - datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ - (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ - ((uint32_t) sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); - } - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - - if (status == HAL_OK) - { - /* Set the RTC_DR register */ - hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); - - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); - } - - if (status == HAL_OK) - { - hrtc->State = HAL_RTC_STATE_READY; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return status; -} - -/** - * @brief Gets RTC current date. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sDate Pointer to Date structure - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the - * values in the higher-order calendar shadow registers to ensure - * consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers - * until current date is read to ensure consistency between the time and - * date values. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) -{ - uint32_t datetmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the DR register */ - datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); - - /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); - sDate->Date = (uint8_t) (datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); - - /* Check the input parameters format */ - if (Format == RTC_FORMAT_BIN) - { - /* Convert the date structure parameters to Binary format */ - sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); - sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); - } - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions - * @brief RTC Alarm functions - * -@verbatim - =============================================================================== - ##### RTC Alarm functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Alarm feature - -@endverbatim - * @{ - */ -/** - * @brief Sets the specified RTC Alarm. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm Pointer to Alarm structure - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - uint32_t tickstart = 0U; - uint32_t tmpreg = 0U; - uint32_t subsecondtmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - /* Change RTC state to BUSY */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Check the data format (binary or BCD) and store the Alarm time and date - configuration accordingly */ - if (Format == RTC_FORMAT_BIN) - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ - ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t) sAlarm->AlarmMask)); - } - - /* Store the Alarm subseconds configuration */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \ - (uint32_t)(sAlarm->AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if (sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case interrupt mode is used, the interrupt source must be disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - /* Clear the Alarm flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Subseconds register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - } - else - { - /* Disable the Alarm B */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case interrupt mode is used, the interrupt source must be disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - /* Clear the Alarm flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Subseconds register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state back to READY */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets the specified RTC Alarm with Interrupt. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm Pointer to Alarm structure - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use the HAL_RTC_DeactivateAlarm()). - * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) -{ - __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); - uint32_t tmpreg = 0U; - uint32_t subsecondtmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(sAlarm->Alarm)); - assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); - assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); - assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - /* Change RTC state to BUSY */ - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Check the data format (binary or BCD) and store the Alarm time and date - configuration accordingly */ - if (Format == RTC_FORMAT_BIN) - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); - } - assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); - assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); - } - - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); - } - else - { - if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) - { - assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); - } - else - { - sAlarm->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); - } - - assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); - assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - - if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - else - { - assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); - } - - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ - ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t) sAlarm->AlarmMask)); - } - - /* Store the Alarm subseconds configuration */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \ - (uint32_t)(sAlarm->AlarmSubSecondMask)); - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the Alarm register */ - if (sAlarm->Alarm == RTC_ALARM_A) - { - /* Disable the Alarm A */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* Clear the Alarm flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ - do - { - count = count - 1U; - if (count == 0U) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U); - - hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Subseconds register */ - hrtc->Instance->ALRMASSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); - } - else - { - /* Disable the Alarm B */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* Clear the Alarm flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Reload the counter */ - count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); - - /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ - do - { - count = count - 1U; - if (count == 0U) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U); - - hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Subseconds register */ - hrtc->Instance->ALRMBSSR = subsecondtmpreg; - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMB_ENABLE(hrtc); - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB); - } - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state back to READY */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates the specified RTC Alarm. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Alarm Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: Alarm A - * @arg RTC_ALARM_B: Alarm B - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_ALARM(Alarm)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - if (Alarm == RTC_ALARM_A) - { - /* Disable Alarm A */ - __HAL_RTC_ALARMA_DISABLE(hrtc); - - /* In case interrupt mode is used, the interrupt source must be disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable Alarm B */ - __HAL_RTC_ALARMB_DISABLE(hrtc); - - /* In case interrupt mode is used, the interrupt source must be disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets the RTC Alarm value and masks. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sAlarm Pointer to Date structure - * @param Alarm Specifies the Alarm. - * This parameter can be one of the following values: - * @arg RTC_ALARM_A: Alarm A - * @arg RTC_ALARM_B: Alarm B - * @param Format Specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) -{ - uint32_t tmpreg = 0U; - uint32_t subsecondtmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_RTC_ALARM(Alarm)); - - if (Alarm == RTC_ALARM_A) - { - sAlarm->Alarm = RTC_ALARM_A; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS); - } - else - { - sAlarm->Alarm = RTC_ALARM_B; - - tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - - /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint8_t) ((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); - sAlarm->AlarmTime.Minutes = (uint8_t) ((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); - sAlarm->AlarmTime.Seconds = (uint8_t) ( tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint8_t) ((tmpreg & RTC_ALRMAR_PM) >> RTC_TR_PM_Pos); - sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint8_t) ((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); - sAlarm->AlarmDateWeekDaySel = (uint32_t) (tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t) (tmpreg & RTC_ALARMMASK_ALL); - - if (Format == RTC_FORMAT_BIN) - { - sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); - sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); - sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); - sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); - } - - return HAL_OK; -} - -/** - * @brief Handles Alarm interrupt request. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); - - /* Get the Alarm A interrupt source enable status */ - if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) - { - /* Get the pending status of the Alarm A Interrupt */ - if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U) - { - /* Clear the Alarm A interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Alarm A callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->AlarmAEventCallback(hrtc); -#else - HAL_RTC_AlarmAEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - } - } - - /* Get the Alarm B interrupt source enable status */ - if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U) - { - /* Get the pending status of the Alarm B Interrupt */ - if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U) - { - /* Clear the Alarm B interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Alarm B callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->AlarmBEventCallback(hrtc); -#else - HAL_RTCEx_AlarmBEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Alarm A callback. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handles Alarm A Polling request. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRAF flag is set and if timeout is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Wait for RTC Time and Date Synchronization - (+) Manage RTC Summer or Winter time change - -@endverbatim - * @{ - */ - -/** - * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0U; - - /* Clear RSF flag, keep reserved bits at reset values (setting other flags has no effect) */ - hrtc->Instance->ISR = ((uint32_t)(RTC_RSF_MASK & RTC_ISR_RESERVED_MASK)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait the registers to be synchronised */ - while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Daylight Saving Time, adds one hour to the calendar in one - * single operation without going through the initialization procedure. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) -{ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); -} - -/** - * @brief Daylight Saving Time, subtracts one hour from the calendar in one - * single operation without going through the initialization procedure. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) -{ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); -} - -/** - * @brief Daylight Saving Time, sets the store operation bit. - * @note It can be used by the software in order to memorize the DST status. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) -{ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(hrtc->Instance->CR, RTC_CR_BKP); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); -} - -/** - * @brief Daylight Saving Time, clears the store operation bit. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) -{ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP); - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); -} - -/** - * @brief Daylight Saving Time, reads the store operation bit. - * @param hrtc RTC handle - * @retval operation see RTC_StoreOperation_Definitions - */ -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) -{ - return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP); -} - -/** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Returns the RTC state. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) -{ - return hrtc->State; -} - -/** - * @} - */ - - -/** - * @} - */ - -/** @addtogroup RTC_Private_Functions - * @{ - */ - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0U; - HAL_StatusTypeDef status = HAL_OK; - - /* Check that Initialization mode is not already set */ - if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) - { - /* Set INIT bit to enter Initialization mode */ - SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC is in INIT state and if timeout is reached exit */ - while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - status = HAL_ERROR; - } - } - } - - return status; -} - -/** - * @brief Exits the RTC Initialization mode. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Clear INIT bit to exit Initialization mode */ - CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); - - /* If CR_BYPSHAD bit = 0, wait for synchro */ - if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U) - { - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Converts a 2-digit number from decimal to BCD format. - * @param number decimal-formatted number (from 0 to 99) to be converted - * @retval Converted byte - */ -uint8_t RTC_ByteToBcd2(uint8_t number) -{ - uint32_t bcdhigh = 0U; - - while (number >= 10U) - { - bcdhigh++; - number -= 10U; - } - - return ((uint8_t)(bcdhigh << 4U) | number); -} - -/** - * @brief Converts a 2-digit number from BCD to decimal format. - * @param number BCD-formatted number (from 00 to 99) to be converted - * @retval Converted word - */ -uint8_t RTC_Bcd2ToByte(uint8_t number) -{ - uint32_t tens = 0U; - tens = (((uint32_t)number & 0xF0U) >> 4U) * 10U; - return (uint8_t)(tens + ((uint32_t)number & 0x0FU)); -} - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c deleted file mode 100644 index 08bd986e..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rtc_ex.c +++ /dev/null @@ -1,2036 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_rtc_ex.c - * @author MCD Application Team - * @brief Extended RTC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Real-Time Clock (RTC) Extended peripheral: - * + RTC Timestamp functions - * + RTC Tamper functions - * + RTC Wakeup functions - * + Extended Control functions - * + Extended RTC features functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (+) Enable the RTC domain access. - (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour - format using the HAL_RTC_Init() function. - - *** RTC Wakeup configuration *** - ================================ - [..] - (+) To configure the RTC Wakeup Clock source and Counter use the - HAL_RTCEx_SetWakeUpTimer() function. - You can also configure the RTC Wakeup timer in interrupt mode using the - HAL_RTCEx_SetWakeUpTimer_IT() function. - (+) To read the RTC Wakeup Counter register, use the HAL_RTCEx_GetWakeUpTimer() - function. - - *** Timestamp configuration *** - =============================== - [..] - (+) To configure the RTC Timestamp use the HAL_RTCEx_SetTimeStamp() function. - You can also configure the RTC Timestamp with interrupt mode using the - HAL_RTCEx_SetTimeStamp_IT() function. - (+) To read the RTC Timestamp Time and Date register, use the - HAL_RTCEx_GetTimeStamp() function. - (+) The Timestamp alternate function can be mapped either to RTC_AF1 (PC13), - RTC_AF2 (PI8), or RTC_AF3 (PC1) depending on the value of TSINSEL field - in RTC_OR register. - The corresponding pin is also selected by HAL_RTCEx_SetTimeStamp() - or HAL_RTCEx_SetTimeStamp_IT() functions. - - *** Internal Timestamp configuration *** - =============================== - [..] - (+) To Enable the RTC internal Timestamp use the HAL_RTCEx_SetInternalTimeStamp() - function. - (+) To read the RTC Timestamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - - *** Tamper configuration *** - ============================ - [..] - (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger - Edge or Level according to the Tamper filter value (if equal to 0 Edge - else Level), sampling frequency, NoErase, MaskFlag, precharge or - discharge and Pull-UP use the HAL_RTCEx_SetTamper() function. - You can configure RTC Tamper in interrupt mode using HAL_RTCEx_SetTamper_IT() - function. - (+) The default configuration of the Tamper erases the backup registers. - To avoid this, enable the NoErase field on the RTC_TAMPCR register. - (+) The TAMPER1 alternate function is mapped to RTC_AF1 (PC13). - (+) The TAMPER2 alternate function is mapped to RTC_AF2 (PI8). - (+) The TAMPER3 alternate function is mapped to RTC_AF3 (PC1). - - *** Backup Data Registers configuration *** - =========================================== - [..] - (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite() - function. - (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() - function. - - *** Smooth Digital Calibration configuration *** - ================================================ - [..] - (+) RTC frequency can be digitally calibrated with a resolution of about - 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. - The correction of the frequency is performed using a series of small - adjustments (adding and/or subtracting individual RTCCLK pulses). - (+) The smooth digital calibration is performed during a cycle of about 2^20 - RTCCLK pulses (or 32 seconds) when the input frequency is 32,768 Hz. - This cycle is maintained by a 20-bit counter clocked by RTCCLK. - (+) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK - clock cycles to be masked during the 32-second cycle. - (+) The RTC Smooth Digital Calibration value and the corresponding calibration - cycle period (32s, 16s, or 8s) can be calibrated using the - HAL_RTCEx_SetSmoothCalib() function. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup RTCEx RTCEx - * @brief RTC Extended HAL module driver - * @{ - */ - -#ifdef HAL_RTC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions - * @{ - */ - -/** @defgroup RTCEx_Exported_Functions_Group1 RTC Timestamp and Tamper functions - * @brief RTC Timestamp and Tamper functions - * -@verbatim - =============================================================================== - ##### RTC Timestamp and Tamper functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Timestamp feature - -@endverbatim - * @{ - */ - -/** - * @brief Sets Timestamp. - * @note This API must be called before enabling the Timestamp feature. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on - * the rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on - * the falling edge of the related pin. - * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin. - * @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC Timestamp Pin. - * @arg RTC_TIMESTAMPPIN_POS2: PC1 is selected as RTC Timestamp Pin. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - /* Change RTC state to BUSY */ - hrtc->State = HAL_RTC_STATE_BUSY; - - hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL; - hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Configure the Timestamp TSEDGE bit */ - tmpreg |= RTC_TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Copy the desired configuration into the CR register */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - /* Clear RTC Timestamp flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - - /* Clear RTC Timestamp overrun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Enable the Timestamp saving */ - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state back to READY */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets Timestamp with Interrupt. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note This API must be called before enabling the Timestamp feature. - * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is - * activated. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on - * the rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on - * the falling edge of the related pin. - * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin. - * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin. - * @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC Timestamp Pin. - * @arg RTC_TIMESTAMPPIN_POS2: PC1 is selected as RTC Timestamp Pin. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge)); - assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - /* Change RTC state to BUSY */ - hrtc->State = HAL_RTC_STATE_BUSY; - - hrtc->Instance->OR &= (uint32_t)~RTC_OR_TSINSEL; - hrtc->Instance->OR |= (uint32_t)(RTC_TimeStampPin); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Configure the Timestamp TSEDGE bit */ - tmpreg |= RTC_TimeStampEdge; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Copy the desired configuration into the CR register */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - /* Clear RTC Timestamp flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - - /* Clear RTC Timestamp overrun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Enable the Timestamp saving */ - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable IT Timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* RTC Timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - /* Change RTC state back to READY */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates Timestamp. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) -{ - uint32_t tmpreg = 0U; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS); - - /* Get the RTC_CR register and clear the bits to be configured */ - tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - - /* Configure the Timestamp TSEDGE and Enable bits */ - hrtc->Instance->CR = (uint32_t)tmpreg; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets Internal Timestamp. - * @note This API must be called before enabling the internal Timestamp feature. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the internal Timestamp Enable bits */ - __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates internal Timestamp. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Configure the internal Timestamp Enable bits */ - __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets the RTC Timestamp value. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTimeStamp Pointer to Time structure - * @param sTimeStampDate Pointer to Date structure - * @param Format specifies the format of the entered parameters. - * This parameter can be one of the following values: - * @arg RTC_FORMAT_BIN: Binary data format - * @arg RTC_FORMAT_BCD: BCD data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format) -{ - uint32_t tmptime = 0U; - uint32_t tmpdate = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_FORMAT(Format)); - - /* Get the Timestamp time and date registers values */ - tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); - tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); - - /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); - sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); - sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; - - /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0U; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); - sTimeStampDate->Date = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); - - /* Check the input parameters format */ - if (Format == RTC_FORMAT_BIN) - { - /* Convert the Timestamp structure parameters to Binary format */ - sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); - sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); - sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); - - /* Convert the DateTimeStamp structure parameters to Binary format */ - sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); - sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); - sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); - } - - /* Clear the internal Timestamp Flag */ - __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_ITSF); - - /* Clear the Timestamp Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - - return HAL_OK; -} - -/** - * @brief Sets Tamper. - * @note By calling this API the tamper global interrupt will be disabled and - * the selected tamper's interrupt as well. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTamper Pointer to Tamper Structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Copy control register into temporary variable */ - tmpreg = hrtc->Instance->TAMPCR; - - /* Enable selected tamper */ - tmpreg |= (sTamper->Tamper); - - /* Configure the tamper trigger bit (this bit is just on the right of the - tamper enable bit, hence the one-time right shift before updating it) */ - if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE) - { - /* Set the tamper trigger bit (case of falling edge or high level) */ - tmpreg |= (uint32_t)(sTamper->Tamper << 1U); - } - else - { - /* Clear the tamper trigger bit (case of rising edge or low level) */ - tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); - } - - /* Configure the backup registers erasure enabling bits */ - if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1NOERASE); - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2NOERASE); - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3NOERASE); - } - } - else - { - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1NOERASE); - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2NOERASE); - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE); - } - } - - /* Configure the tamper flags masking bits */ - if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1MF); - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2MF); - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3MF); - } - } - else - { - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1MF); - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2MF); - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF); - } - } - - /* Clear remaining fields before setting them */ - tmpreg &= ~(RTC_TAMPERFILTER_MASK | \ - RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ - RTC_TAMPERPRECHARGEDURATION_MASK | \ - RTC_TAMPER_PULLUP_MASK | \ - RTC_TIMESTAMPONTAMPERDETECTION_MASK); - - /* Set remaining parameters of desired configuration into temporary variable */ - tmpreg |= ((uint32_t)sTamper->Filter | \ - (uint32_t)sTamper->SamplingFrequency | \ - (uint32_t)sTamper->PrechargeDuration | \ - (uint32_t)sTamper->TamperPullUp | \ - (uint32_t)sTamper->TimeStampOnTamperDetection); - - /* Disable interrupt on selected tamper in case it is enabled */ - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg &= (uint32_t)~RTC_IT_TAMP1; - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg &= (uint32_t)~RTC_IT_TAMP2; - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg &= (uint32_t)~RTC_IT_TAMP3; - } - - /* Disable tamper global interrupt in case it is enabled */ - tmpreg &= (uint32_t)~RTC_TAMPCR_TAMPIE; - - /* Copy desired configuration into configuration register */ - hrtc->Instance->TAMPCR = tmpreg; - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets Tamper with interrupt. - * @note By setting the tamper global interrupt bit, interrupts will be - * enabled for all tampers. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param sTamper Pointer to RTC Tamper. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) -{ - uint32_t tmpreg = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_TAMPER(sTamper->Tamper)); - assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); - assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)); - assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Copy control register into temporary variable */ - tmpreg = hrtc->Instance->TAMPCR; - - /* Enable selected tamper */ - tmpreg |= (sTamper->Tamper); - - /* Configure the tamper trigger bit (this bit is just on the right of the - tamper enable bit, hence the one-time right shift before updating it) */ - if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE) - { - /* Set the tamper trigger bit (case of falling edge or high level) */ - tmpreg |= (uint32_t)(sTamper->Tamper << 1U); - } - else - { - /* Clear the tamper trigger bit (case of rising edge or low level) */ - tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); - } - - /* Configure the backup registers erasure enabling bits */ - if (sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) - { - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1NOERASE); - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2NOERASE); - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3NOERASE); - } - } - else - { - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1NOERASE); - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2NOERASE); - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3NOERASE); - } - } - - /* Configure the tamper flags masking bits */ - if (sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) - { - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP1MF); - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP2MF); - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg |= (uint32_t)(RTC_TAMPCR_TAMP3MF); - } - } - else - { - if ((sTamper->Tamper & RTC_TAMPER_1) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP1MF); - } - if ((sTamper->Tamper & RTC_TAMPER_2) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP2MF); - } - if ((sTamper->Tamper & RTC_TAMPER_3) != 0U) - { - tmpreg &= (uint32_t)~(RTC_TAMPCR_TAMP3MF); - } - } - - /* Clear remaining fields before setting them */ - tmpreg &= ~(RTC_TAMPERFILTER_MASK | \ - RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ - RTC_TAMPERPRECHARGEDURATION_MASK | \ - RTC_TAMPER_PULLUP_MASK | \ - RTC_TIMESTAMPONTAMPERDETECTION_MASK); - - /* Set remaining parameters of desired configuration into temporary variable */ - tmpreg |= ((uint32_t)sTamper->Filter | \ - (uint32_t)sTamper->SamplingFrequency | \ - (uint32_t)sTamper->PrechargeDuration | \ - (uint32_t)sTamper->TamperPullUp | \ - (uint32_t)sTamper->TimeStampOnTamperDetection); - - /* Enable interrupt on selected tamper */ - tmpreg |= (uint32_t)sTamper->Interrupt; - - /* Copy desired configuration into configuration register */ - hrtc->Instance->TAMPCR = tmpreg; - - /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates Tamper. - * @note By calling this API the tamper global interrupt will be disabled. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Tamper Selected tamper pin. - * This parameter can be any combination of the following values: - * @arg RTC_TAMPER_1: Tamper 1 - * @arg RTC_TAMPER_2: Tamper 2 - * @arg RTC_TAMPER_3: Tamper 3 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) -{ - assert_param(IS_RTC_TAMPER(Tamper)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the selected Tamper pin */ - hrtc->Instance->TAMPCR &= (uint32_t)~Tamper; - - if ((Tamper & RTC_TAMPER_1) != 0U) - { - /* Disable the Tamper 1 interrupt */ - hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1); - } - if ((Tamper & RTC_TAMPER_2) != 0U) - { - /* Disable the Tamper 2 interrupt */ - hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2); - } - if ((Tamper & RTC_TAMPER_3) != 0U) - { - /* Disable the Tamper 3 interrupt */ - hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3); - } - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Handles Timestamp and Tamper interrupt request. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); - - /* Get the Timestamp interrupt source enable status */ - if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U) - { - /* Get the pending status of the Timestamp Interrupt */ - if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U) - { - /* Timestamp callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->TimeStampEventCallback(hrtc); -#else - HAL_RTCEx_TimeStampEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - - /* Clear the Timestamp interrupt pending bit after returning from callback - as RTC_TSTR and RTC_TSDR registers are cleared when TSF bit is reset */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - } - } - - /* Get the Tamper 1 interrupt source enable status */ - if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP1) != 0U) - { - /* Get the pending status of the Tamper 1 Interrupt */ - if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) - { - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Tamper callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper1EventCallback(hrtc); -#else - HAL_RTCEx_Tamper1EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - } - } - - /* Get the Tamper 2 interrupt source enable status */ - if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP2) != 0U) - { - /* Get the pending status of the Tamper 2 Interrupt */ - if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) - { - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Tamper callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper2EventCallback(hrtc); -#else - HAL_RTCEx_Tamper2EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - } - } - - /* Get the Tamper 3 interrupt source enable status */ - if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP | RTC_IT_TAMP3) != 0U) - { - /* Get the pending status of the Tamper 3 Interrupt */ - if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) != 0U) - { - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Tamper callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->Tamper3EventCallback(hrtc); -#else - HAL_RTCEx_Tamper3EventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Timestamp callback. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 1 callback. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 2 callback. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 3 callback. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file - */ -} - -/** - * @brief Handles Timestamp polling request. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - - if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U) - { - /* Clear the Timestamp Overrun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - - /* Change Timestamp state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Handles Tamper 1 Polling. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Handles Tamper 2 Polling. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Handles Tamper 3 Polling. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Get the status of the Interrupt */ - while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wakeup functions - * @brief RTC Wakeup functions - * -@verbatim - =============================================================================== - ##### RTC Wakeup functions ##### - =============================================================================== - - [..] This section provides functions allowing to configure Wakeup feature - -@endverbatim - * @{ - */ - -/** - * @brief Sets wakeup timer. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param WakeUpCounter Wakeup counter - * @param WakeUpClock Wakeup clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Check RTC WUTWF flag is reset only when wakeup timer enabled*/ - if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) - { - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Disable the Wakeup timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Clear the Wakeup flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Sets wakeup timer with interrupt. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param WakeUpCounter Wakeup counter - * @param WakeUpClock Wakeup clock - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); - - /* Check the parameters */ - assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Check RTC WUTWF flag is reset only when wakeup timer enabled */ - if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) - { - /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ - do - { - count = count - 1U; - if (count == 0U) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U); - } - - /* Disable the Wakeup timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* Clear the Wakeup flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Reload the counter */ - count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); - - /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ - do - { - count = count - 1U; - if (count == 0U) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U); - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* RTC wakeup timer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* Configure the interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT); - - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates wakeup timer counter. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - uint32_t tickstart = 0U; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Disable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Gets wakeup timer counter. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval Counter value - */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - /* Get the counter value */ - return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); -} - -/** - * @brief Handles Wakeup Timer interrupt request. - * @note Unlike alarm interrupt line (shared by Alarms A and B) or tamper - * interrupt line (shared by timestamp and tampers) wakeup timer - * interrupt line is exclusive to the wakeup timer. - * There is no need in this case to check on the interrupt enable - * status via __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(). - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); - - /* Get the pending status of the Wakeup timer Interrupt */ - if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) - { - /* Clear the Wakeup timer interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Wakeup timer callback */ -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - hrtc->WakeUpTimerEventCallback(hrtc); -#else - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); -#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - } - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Wakeup Timer callback. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handles Wakeup Timer Polling. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Wakeup timer Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Write a data in a specified RTC Backup data register - (+) Read a data in a specified RTC Backup data register - (+) Set the Smooth calibration parameters. - (+) Configure the Synchronization Shift Control Settings. - (+) Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Deactivate the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - (+) Enable the RTC reference clock detection. - (+) Disable the RTC reference clock detection. - (+) Enable the Bypass Shadow feature. - (+) Disable the Bypass Shadow feature. - -@endverbatim - * @{ - */ - -/** - * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 31) - * to specify the register. - * @param Data Data to be written in the specified RTC Backup data register. - * @retval None - */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t) & (hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4U); - - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; -} - -/** - * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 31) - * to specify the register. - * @retval Read value - */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); - - tmp = (uint32_t) & (hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4U); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} - -/** - * @brief Sets the Smooth calibration parameters. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param SmoothCalibPeriod Select the Smooth Calibration Period. - * This parameter can be can be one of the following values: - * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. - * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. - * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. - * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. - * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmoothCalibMinusPulsesValue must be equal to 0. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* check if a calibration is pending*/ - if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* check if a calibration is pending*/ - while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - } - - /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | \ - (uint32_t)SmoothCalibPlusPulses | \ - (uint32_t)SmoothCalibMinusPulsesValue); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param ShiftAdd1S Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values: - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the shift is completed */ - while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U) - { - if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_TIMEOUT; - } - } - - /* Check if the reference clock detection is disabled */ - if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) - { - if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param CalibOutput Select the Calibration output Selection. - * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. - * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) -{ - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Clear flags before config */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; - - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)CalibOutput; - - __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Enables the RTC reference clock detection. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) -{ - HAL_StatusTypeDef status; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - - if (status == HAL_OK) - { - /* Enable the reference clock detection */ - __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); - } - - if (status == HAL_OK) - { - hrtc->State = HAL_RTC_STATE_READY; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return status; -} - -/** - * @brief Disable the RTC reference clock detection. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) -{ - HAL_StatusTypeDef status; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Enter Initialization mode */ - status = RTC_EnterInitMode(hrtc); - - if (status == HAL_OK) - { - /* Disable the reference clock detection */ - __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); - - /* Exit Initialization mode */ - status = RTC_ExitInitMode(hrtc); - } - - if (status == HAL_OK) - { - hrtc->State = HAL_RTC_STATE_READY; - } - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return status; -} - -/** - * @brief Enables the Bypass Shadow feature. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @brief Disables the Bypass Shadow feature. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions - * @brief Extended features functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) RTC Alarm B callback - (+) RTC Poll for Alarm B request - -@endverbatim - * @{ - */ - -/** - * @brief Alarm B callback. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hrtc); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file - */ -} - -/** - * @brief Handles Alarm B Polling request. - * @param hrtc pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till RTC ALRBF flag is set and if timeout is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } - - /* Clear the Alarm flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_RTC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c deleted file mode 100644 index d62994c8..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai.c +++ /dev/null @@ -1,2558 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sai.c - * @author MCD Application Team - * @brief SAI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Serial Audio Interface (SAI) peripheral: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - The SAI HAL driver can be used as follows: - - (#) Declare a SAI_HandleTypeDef handle structure (eg. SAI_HandleTypeDef hsai). - (#) Initialize the SAI low level resources by implementing the HAL_SAI_MspInit() API: - (##) Enable the SAI interface clock. - (##) SAI pins configuration: - (+++) Enable the clock for the SAI GPIOs. - (+++) Configure these SAI pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_SAI_Transmit_IT() - and HAL_SAI_Receive_IT() APIs): - (+++) Configure the SAI interrupt priority. - (+++) Enable the NVIC SAI IRQ handle. - - (##) DMA Configuration if you need to use DMA process (HAL_SAI_Transmit_DMA() - and HAL_SAI_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx stream. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream. - (+++) Associate the initialized DMA handle to the SAI DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA Tx/Rx Stream. - - (#) The initialization can be done by two ways - (##) Expert mode : Initialize the structures Init, FrameInit and SlotInit and call HAL_SAI_Init(). - (##) Simplified mode : Initialize the high part of Init Structure and call HAL_SAI_InitProtocol(). - - [..] - (@) The specific SAI interrupts (FIFO request and Overrun underrun interrupt) - will be managed using the macros __HAL_SAI_ENABLE_IT() and __HAL_SAI_DISABLE_IT() - inside the transmit and receive process. - [..] - (@) Make sure that either: - (+@) I2S PLL is configured or - (+@) SAI PLL is configured or - (+@) External clock source is configured after setting correctly - the define constant EXTERNAL_CLOCK_VALUE in the stm32f7xx_hal_conf.h file. - [..] - (@) In master Tx mode: enabling the audio block immediately generates the bit clock - for the external slaves even if there is no data in the FIFO, However FS signal - generation is conditioned by the presence of data in the FIFO. - - [..] - (@) In master Rx mode: enabling the audio block immediately generates the bit clock - and FS signal for the external slaves. - - [..] - (@) It is mandatory to respect the following conditions in order to avoid bad SAI behavior: - (+@) First bit Offset <= (SLOT size - Data size) - (+@) Data size <= SLOT size - (+@) Number of SLOT x SLOT size = Frame length - (+@) The number of slots should be even when SAI_FS_CHANNEL_IDENTIFICATION is selected. - - [..] - Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_SAI_Transmit() - (+) Receive an amount of data in blocking mode using HAL_SAI_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non-blocking mode using HAL_SAI_Transmit_IT() - (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SAI_TxCpltCallback() - (+) Receive an amount of data in non-blocking mode using HAL_SAI_Receive_IT() - (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SAI_RxCpltCallback() - (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SAI_ErrorCallback() - - *** DMA mode IO operation *** - ============================= - [..] - (+) Send an amount of data in non-blocking mode (DMA) using HAL_SAI_Transmit_DMA() - (+) At transmission end of transfer HAL_SAI_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SAI_TxCpltCallback() - (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SAI_Receive_DMA() - (+) At reception end of transfer HAL_SAI_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SAI_RxCpltCallback() - (+) In case of flag error, HAL_SAI_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SAI_ErrorCallback() - (+) Pause the DMA Transfer using HAL_SAI_DMAPause() - (+) Resume the DMA Transfer using HAL_SAI_DMAResume() - (+) Stop the DMA Transfer using HAL_SAI_DMAStop() - - *** SAI HAL driver additional function list *** - =============================================== - [..] - Below the list the others API available SAI HAL driver : - - (+) HAL_SAI_EnableTxMuteMode(): Enable the mute in tx mode - (+) HAL_SAI_DisableTxMuteMode(): Disable the mute in tx mode - (+) HAL_SAI_EnableRxMuteMode(): Enable the mute in Rx mode - (+) HAL_SAI_DisableRxMuteMode(): Disable the mute in Rx mode - (+) HAL_SAI_FlushRxFifo(): Flush the rx fifo. - (+) HAL_SAI_Abort(): Abort the current transfer - - *** SAI HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in SAI HAL driver : - - (+) __HAL_SAI_ENABLE(): Enable the SAI peripheral - (+) __HAL_SAI_DISABLE(): Disable the SAI peripheral - (+) __HAL_SAI_ENABLE_IT(): Enable the specified SAI interrupts - (+) __HAL_SAI_DISABLE_IT(): Disable the specified SAI interrupts - (+) __HAL_SAI_GET_IT_SOURCE(): Check if the specified SAI interrupt source is - enabled or disabled - (+) __HAL_SAI_GET_FLAG(): Check whether the specified SAI flag is set or not - - *** Callback registration *** - ============================= - [..] - The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use functions HAL_SAI_RegisterCallback() to register a user callback. - - [..] - Function HAL_SAI_RegisterCallback() allows to register following callbacks: - (+) RxCpltCallback : SAI receive complete. - (+) RxHalfCpltCallback : SAI receive half complete. - (+) TxCpltCallback : SAI transmit complete. - (+) TxHalfCpltCallback : SAI transmit half complete. - (+) ErrorCallback : SAI error. - (+) MspInitCallback : SAI MspInit. - (+) MspDeInitCallback : SAI MspDeInit. - [..] - This function takes as parameters the HAL peripheral handle, the callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the callback ID. - [..] - This function allows to reset following callbacks: - (+) RxCpltCallback : SAI receive complete. - (+) RxHalfCpltCallback : SAI receive half complete. - (+) TxCpltCallback : SAI transmit complete. - (+) TxHalfCpltCallback : SAI transmit half complete. - (+) ErrorCallback : SAI error. - (+) MspInitCallback : SAI MspInit. - (+) MspDeInitCallback : SAI MspDeInit. - - [..] - By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET - all callbacks are reset to the corresponding legacy weak functions: - examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback(). - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak functions in the HAL_SAI_Init - and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit - or HAL_SAI_Init function. - - [..] - When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak callbacks are used. - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SAI SAI - * @brief SAI HAL module driver - * @{ - */ - -#ifdef HAL_SAI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/** @defgroup SAI_Private_Typedefs SAI Private Typedefs - * @{ - */ -typedef enum -{ - SAI_MODE_DMA, - SAI_MODE_IT -} SAI_ModeTypedef; -/** - * @} - */ - -/* Private define ------------------------------------------------------------*/ - -/** @defgroup SAI_Private_Constants SAI Private Constants - * @{ - */ -#define SAI_DEFAULT_TIMEOUT 4U /* 4ms */ -#define SAI_LONG_TIMEOUT 1000U -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup SAI_Private_Functions SAI Private Functions - * @{ - */ -static void SAI_FillFifo(SAI_HandleTypeDef *hsai); -static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode); -static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); -static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); - -static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai); -static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai); -static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai); -static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai); -static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai); -static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai); -static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai); - -static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma); -static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma); -static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void SAI_DMAError(DMA_HandleTypeDef *hdma); -static void SAI_DMAAbort(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup SAI_Exported_Functions SAI Exported Functions - * @{ - */ - -/** @defgroup SAI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the SAIx peripheral: - - (+) User must implement HAL_SAI_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_SAI_Init() to configure the selected device with - the selected configuration: - (++) Mode (Master/slave TX/RX) - (++) Protocol - (++) Data Size - (++) MCLK Output - (++) Audio frequency - (++) FIFO Threshold - (++) Frame Config - (++) Slot Config - - (+) Call the function HAL_SAI_DeInit() to restore the default configuration - of the selected SAI peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the structure FrameInit, SlotInit and the low part of - * Init according to the specified parameters and call the function - * HAL_SAI_Init to initialize the SAI block. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param protocol one of the supported protocol @ref SAI_Protocol - * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize - * the configuration information for SAI module. - * @param nbslot Number of slot. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_SAI_SUPPORTED_PROTOCOL(protocol)); - assert_param(IS_SAI_PROTOCOL_DATASIZE(datasize)); - - switch (protocol) - { - case SAI_I2S_STANDARD : - case SAI_I2S_MSBJUSTIFIED : - case SAI_I2S_LSBJUSTIFIED : - status = SAI_InitI2S(hsai, protocol, datasize, nbslot); - break; - case SAI_PCM_LONG : - case SAI_PCM_SHORT : - status = SAI_InitPCM(hsai, protocol, datasize, nbslot); - break; - default : - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - status = HAL_SAI_Init(hsai); - } - - return status; -} - -/** - * @brief Initialize the SAI according to the specified parameters. - * in the SAI_InitTypeDef structure and initialize the associated handle. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) -{ - uint32_t tmpregisterGCR = 0; - uint32_t ckstr_bits = 0; - uint32_t syncen_bits = 0; - - /* Check the SAI handle allocation */ - if (hsai == NULL) - { - return HAL_ERROR; - } - - /* check the instance */ - assert_param(IS_SAI_ALL_INSTANCE(hsai->Instance)); - - /* Check the SAI Block parameters */ - assert_param(IS_SAI_AUDIO_FREQUENCY(hsai->Init.AudioFrequency)); - assert_param(IS_SAI_BLOCK_PROTOCOL(hsai->Init.Protocol)); - assert_param(IS_SAI_BLOCK_MODE(hsai->Init.AudioMode)); - assert_param(IS_SAI_BLOCK_DATASIZE(hsai->Init.DataSize)); - assert_param(IS_SAI_BLOCK_FIRST_BIT(hsai->Init.FirstBit)); - assert_param(IS_SAI_BLOCK_CLOCK_STROBING(hsai->Init.ClockStrobing)); - assert_param(IS_SAI_BLOCK_SYNCHRO(hsai->Init.Synchro)); - assert_param(IS_SAI_BLOCK_OUTPUT_DRIVE(hsai->Init.OutputDrive)); - assert_param(IS_SAI_BLOCK_NODIVIDER(hsai->Init.NoDivider)); - assert_param(IS_SAI_BLOCK_FIFO_THRESHOLD(hsai->Init.FIFOThreshold)); - assert_param(IS_SAI_MONO_STEREO_MODE(hsai->Init.MonoStereoMode)); - assert_param(IS_SAI_BLOCK_COMPANDING_MODE(hsai->Init.CompandingMode)); - assert_param(IS_SAI_BLOCK_TRISTATE_MANAGEMENT(hsai->Init.TriState)); - assert_param(IS_SAI_BLOCK_SYNCEXT(hsai->Init.SynchroExt)); - - /* Check the SAI Block Frame parameters */ - assert_param(IS_SAI_BLOCK_FRAME_LENGTH(hsai->FrameInit.FrameLength)); - assert_param(IS_SAI_BLOCK_ACTIVE_FRAME(hsai->FrameInit.ActiveFrameLength)); - assert_param(IS_SAI_BLOCK_FS_DEFINITION(hsai->FrameInit.FSDefinition)); - assert_param(IS_SAI_BLOCK_FS_POLARITY(hsai->FrameInit.FSPolarity)); - assert_param(IS_SAI_BLOCK_FS_OFFSET(hsai->FrameInit.FSOffset)); - - /* Check the SAI Block Slot parameters */ - assert_param(IS_SAI_BLOCK_FIRSTBIT_OFFSET(hsai->SlotInit.FirstBitOffset)); - assert_param(IS_SAI_BLOCK_SLOT_SIZE(hsai->SlotInit.SlotSize)); - assert_param(IS_SAI_BLOCK_SLOT_NUMBER(hsai->SlotInit.SlotNumber)); - assert_param(IS_SAI_SLOT_ACTIVE(hsai->SlotInit.SlotActive)); - - if (hsai->State == HAL_SAI_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsai->Lock = HAL_UNLOCKED; - -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - /* Reset callback pointers to the weak predefined callbacks */ - hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; - hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; - hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; - hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; - hsai->ErrorCallback = HAL_SAI_ErrorCallback; - - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - if (hsai->MspInitCallback == NULL) - { - hsai->MspInitCallback = HAL_SAI_MspInit; - } - hsai->MspInitCallback(hsai); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_SAI_MspInit(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - - hsai->State = HAL_SAI_STATE_BUSY; - - /* Disable the selected SAI peripheral */ - SAI_Disable(hsai); - - /* SAI Block Synchro Configuration -----------------------------------------*/ - /* This setting must be done with both audio block (A & B) disabled */ - switch (hsai->Init.SynchroExt) - { - case SAI_SYNCEXT_DISABLE : - tmpregisterGCR = 0; - break; - case SAI_SYNCEXT_OUTBLOCKA_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_0; - break; - case SAI_SYNCEXT_OUTBLOCKB_ENABLE : - tmpregisterGCR = SAI_GCR_SYNCOUT_1; - break; - default: - break; - } - - switch (hsai->Init.Synchro) - { - case SAI_ASYNCHRONOUS : - { - syncen_bits = 0; - } - break; - case SAI_SYNCHRONOUS : - { - syncen_bits = SAI_xCR1_SYNCEN_0; - } - break; - case SAI_SYNCHRONOUS_EXT_SAI1 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - } - break; - case SAI_SYNCHRONOUS_EXT_SAI2 : - { - syncen_bits = SAI_xCR1_SYNCEN_1; - tmpregisterGCR |= SAI_GCR_SYNCIN_0; - } - break; - default: - break; - } - - if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) - { - SAI1->GCR = tmpregisterGCR; - } - else - { - SAI2->GCR = tmpregisterGCR; - } - - if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) - { - uint32_t freq = 0; - uint32_t tmpval; - - if ((hsai->Instance == SAI1_Block_A) || (hsai->Instance == SAI1_Block_B)) - { - freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI1); - } - if ((hsai->Instance == SAI2_Block_A) || (hsai->Instance == SAI2_Block_B)) - { - freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SAI2); - } - - /* Configure Master Clock using the following formula : - MCLK_x = SAI_CK_x / (MCKDIV[3:0] * 2) with MCLK_x = 256 * FS - FS = SAI_CK_x / (MCKDIV[3:0] * 2) * 256 - MCKDIV[3:0] = SAI_CK_x / FS * 512 */ - /* (freq x 10) to keep Significant digits */ - tmpval = (freq * 10) / (hsai->Init.AudioFrequency * 2 * 256); - hsai->Init.Mckdiv = tmpval / 10; - - /* Round result to the nearest integer */ - if ((tmpval % 10) > 8) - { - hsai->Init.Mckdiv += 1; - } - - /* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */ - if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL) - { - hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1; - } - } - /* Check the SAI Block master clock divider parameter */ - assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); - - /* Compute CKSTR bits of SAI CR1 according ClockStrobing and AudioMode */ - if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { - /* Transmit */ - ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? 0 : SAI_xCR1_CKSTR; - } - else - { - /* Receive */ - ckstr_bits = (hsai->Init.ClockStrobing == SAI_CLOCKSTROBING_RISINGEDGE) ? SAI_xCR1_CKSTR : 0; - } - - /* SAI Block Configuration -------------------------------------------------*/ - /* SAI CR1 Configuration */ - hsai->Instance->CR1 &= ~(SAI_xCR1_MODE | SAI_xCR1_PRTCFG | SAI_xCR1_DS | \ - SAI_xCR1_LSBFIRST | SAI_xCR1_CKSTR | SAI_xCR1_SYNCEN | \ - SAI_xCR1_MONO | SAI_xCR1_OUTDRIV | SAI_xCR1_DMAEN | \ - SAI_xCR1_NODIV | SAI_xCR1_MCKDIV); - - hsai->Instance->CR1 |= (hsai->Init.AudioMode | hsai->Init.Protocol | \ - hsai->Init.DataSize | hsai->Init.FirstBit | \ - ckstr_bits | syncen_bits | \ - hsai->Init.MonoStereoMode | hsai->Init.OutputDrive | \ - hsai->Init.NoDivider | (hsai->Init.Mckdiv << 20)); - - /* SAI CR2 Configuration */ - hsai->Instance->CR2 &= ~(SAI_xCR2_FTH | SAI_xCR2_FFLUSH | SAI_xCR2_COMP | SAI_xCR2_CPL); - hsai->Instance->CR2 |= (hsai->Init.FIFOThreshold | hsai->Init.CompandingMode | hsai->Init.TriState); - - /* SAI Frame Configuration -----------------------------------------*/ - hsai->Instance->FRCR &= (~(SAI_xFRCR_FRL | SAI_xFRCR_FSALL | SAI_xFRCR_FSDEF | \ - SAI_xFRCR_FSPOL | SAI_xFRCR_FSOFF)); - hsai->Instance->FRCR |= ((hsai->FrameInit.FrameLength - 1) | - hsai->FrameInit.FSOffset | - hsai->FrameInit.FSDefinition | - hsai->FrameInit.FSPolarity | - ((hsai->FrameInit.ActiveFrameLength - 1) << 8)); - - /* SAI Block_x SLOT Configuration ------------------------------------------*/ - /* This register has no meaning in AC 97 and SPDIF audio protocol */ - hsai->Instance->SLOTR &= (~(SAI_xSLOTR_FBOFF | SAI_xSLOTR_SLOTSZ | \ - SAI_xSLOTR_NBSLOT | SAI_xSLOTR_SLOTEN)); - - hsai->Instance->SLOTR |= hsai->SlotInit.FirstBitOffset | hsai->SlotInit.SlotSize - | (hsai->SlotInit.SlotActive << 16) | ((hsai->SlotInit.SlotNumber - 1) << 8); - - /* Initialize the error code */ - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Initialize the SAI state */ - hsai->State = HAL_SAI_STATE_READY; - - /* Release Lock */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief DeInitialize the SAI peripheral. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai) -{ - /* Check the SAI handle allocation */ - if (hsai == NULL) - { - return HAL_ERROR; - } - - hsai->State = HAL_SAI_STATE_BUSY; - - /* Disabled All interrupt and clear all the flag */ - hsai->Instance->IMR = 0; - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - /* Disable the SAI */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - if (hsai->MspDeInitCallback == NULL) - { - hsai->MspDeInitCallback = HAL_SAI_MspDeInit; - } - hsai->MspDeInitCallback(hsai); -#else - HAL_SAI_MspDeInit(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - - /* Initialize the error code */ - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Initialize the SAI state */ - hsai->State = HAL_SAI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief Initialize the SAI MSP. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the SAI MSP. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) -/** - * @brief Register a user SAI callback - * to be used instead of the weak predefined callback. - * @param hsai SAI handle. - * @param CallbackID ID of the callback to be registered. - * This parameter can be one of the following values: - * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. - * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. - * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. - * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. - * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. - * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. - * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. - * @param pCallback pointer to the callback function. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, - HAL_SAI_CallbackIDTypeDef CallbackID, - pSAI_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* update the error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - else - { - if (HAL_SAI_STATE_READY == hsai->State) - { - switch (CallbackID) - { - case HAL_SAI_RX_COMPLETE_CB_ID : - hsai->RxCpltCallback = pCallback; - break; - case HAL_SAI_RX_HALFCOMPLETE_CB_ID : - hsai->RxHalfCpltCallback = pCallback; - break; - case HAL_SAI_TX_COMPLETE_CB_ID : - hsai->TxCpltCallback = pCallback; - break; - case HAL_SAI_TX_HALFCOMPLETE_CB_ID : - hsai->TxHalfCpltCallback = pCallback; - break; - case HAL_SAI_ERROR_CB_ID : - hsai->ErrorCallback = pCallback; - break; - case HAL_SAI_MSPINIT_CB_ID : - hsai->MspInitCallback = pCallback; - break; - case HAL_SAI_MSPDEINIT_CB_ID : - hsai->MspDeInitCallback = pCallback; - break; - default : - /* update the error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SAI_STATE_RESET == hsai->State) - { - switch (CallbackID) - { - case HAL_SAI_MSPINIT_CB_ID : - hsai->MspInitCallback = pCallback; - break; - case HAL_SAI_MSPDEINIT_CB_ID : - hsai->MspDeInitCallback = pCallback; - break; - default : - /* update the error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update the error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - } - return status; -} - -/** - * @brief Unregister a user SAI callback. - * SAI callback is redirected to the weak predefined callback. - * @param hsai SAI handle. - * @param CallbackID ID of the callback to be unregistered. - * This parameter can be one of the following values: - * @arg @ref HAL_SAI_RX_COMPLETE_CB_ID receive complete callback ID. - * @arg @ref HAL_SAI_RX_HALFCOMPLETE_CB_ID receive half complete callback ID. - * @arg @ref HAL_SAI_TX_COMPLETE_CB_ID transmit complete callback ID. - * @arg @ref HAL_SAI_TX_HALFCOMPLETE_CB_ID transmit half complete callback ID. - * @arg @ref HAL_SAI_ERROR_CB_ID error callback ID. - * @arg @ref HAL_SAI_MSPINIT_CB_ID MSP init callback ID. - * @arg @ref HAL_SAI_MSPDEINIT_CB_ID MSP de-init callback ID. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, - HAL_SAI_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_SAI_STATE_READY == hsai->State) - { - switch (CallbackID) - { - case HAL_SAI_RX_COMPLETE_CB_ID : - hsai->RxCpltCallback = HAL_SAI_RxCpltCallback; - break; - case HAL_SAI_RX_HALFCOMPLETE_CB_ID : - hsai->RxHalfCpltCallback = HAL_SAI_RxHalfCpltCallback; - break; - case HAL_SAI_TX_COMPLETE_CB_ID : - hsai->TxCpltCallback = HAL_SAI_TxCpltCallback; - break; - case HAL_SAI_TX_HALFCOMPLETE_CB_ID : - hsai->TxHalfCpltCallback = HAL_SAI_TxHalfCpltCallback; - break; - case HAL_SAI_ERROR_CB_ID : - hsai->ErrorCallback = HAL_SAI_ErrorCallback; - break; - case HAL_SAI_MSPINIT_CB_ID : - hsai->MspInitCallback = HAL_SAI_MspInit; - break; - case HAL_SAI_MSPDEINIT_CB_ID : - hsai->MspDeInitCallback = HAL_SAI_MspDeInit; - break; - default : - /* update the error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SAI_STATE_RESET == hsai->State) - { - switch (CallbackID) - { - case HAL_SAI_MSPINIT_CB_ID : - hsai->MspInitCallback = HAL_SAI_MspInit; - break; - case HAL_SAI_MSPDEINIT_CB_ID : - hsai->MspDeInitCallback = HAL_SAI_MspDeInit; - break; - default : - /* update the error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update the error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - return status; -} -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup SAI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SAI data - transfers. - - (+) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated SAI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (+) Blocking mode functions are : - (++) HAL_SAI_Transmit() - (++) HAL_SAI_Receive() - - (+) Non Blocking mode functions with Interrupt are : - (++) HAL_SAI_Transmit_IT() - (++) HAL_SAI_Receive_IT() - - (+) Non Blocking mode functions with DMA are : - (++) HAL_SAI_Transmit_DMA() - (++) HAL_SAI_Receive_DMA() - - (+) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_SAI_TxCpltCallback() - (++) HAL_SAI_RxCpltCallback() - (++) HAL_SAI_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - if ((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if (hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->pBuffPtr = pData; - hsai->State = HAL_SAI_STATE_BUSY_TX; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Check if the SAI is already enabled */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* fill the fifo with data before to enabled the SAI */ - SAI_FillFifo(hsai); - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - while (hsai->XferCount > 0) - { - /* Write data if the FIFO is not full */ - if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) - { - if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - hsai->Instance->DR = (*hsai->pBuffPtr++); - } - else if (hsai->Init.DataSize <= SAI_DATASIZE_16) - { - hsai->Instance->DR = *((uint16_t *)hsai->pBuffPtr); - hsai->pBuffPtr += 2; - } - else - { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr += 4; - } - hsai->XferCount--; - } - else - { - /* Check for the Timeout */ - if ((Timeout != HAL_MAX_DELAY) && ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))) - { - /* Update error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - - /* Clear all the flags */ - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - /* Change the SAI state */ - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_ERROR; - } - } - } - - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData Pointer to data buffer - * @param Size Amount of data to be received - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - if ((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if (hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->State = HAL_SAI_STATE_BUSY_RX; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - - /* Check if the SAI is already enabled */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Receive data */ - while (hsai->XferCount > 0) - { - if ((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_EMPTY) - { - if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - (*hsai->pBuffPtr++) = hsai->Instance->DR; - } - else if (hsai->Init.DataSize <= SAI_DATASIZE_16) - { - *((uint16_t *)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr += 2; - } - else - { - *((uint32_t *)hsai->pBuffPtr) = hsai->Instance->DR; - hsai->pBuffPtr += 4; - } - hsai->XferCount--; - } - else - { - /* Check for the Timeout */ - if ((Timeout != HAL_MAX_DELAY) && ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))) - { - /* Update error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - - /* Clear all the flags */ - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - /* Change the SAI state */ - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_ERROR; - } - } - } - - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) -{ - if ((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if (hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - hsai->State = HAL_SAI_STATE_BUSY_TX; - - if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - hsai->InterruptServiceRoutine = SAI_Transmit_IT8Bit; - } - else if (hsai->Init.DataSize <= SAI_DATASIZE_16) - { - hsai->InterruptServiceRoutine = SAI_Transmit_IT16Bit; - } - else - { - hsai->InterruptServiceRoutine = SAI_Transmit_IT32Bit; - } - - /* Fill the fifo before starting the communication */ - SAI_FillFifo(hsai); - - /* Enable FRQ and OVRUDR interrupts */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Check if the SAI is already enabled */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData Pointer to data buffer - * @param Size Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) -{ - if ((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if (hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - hsai->State = HAL_SAI_STATE_BUSY_RX; - - if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - hsai->InterruptServiceRoutine = SAI_Receive_IT8Bit; - } - else if (hsai->Init.DataSize <= SAI_DATASIZE_16) - { - hsai->InterruptServiceRoutine = SAI_Receive_IT16Bit; - } - else - { - hsai->InterruptServiceRoutine = SAI_Receive_IT32Bit; - } - - /* Enable TXE and OVRUDR interrupts */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Check if the SAI is already enabled */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the audio stream playing from the Media. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai) -{ - /* Process Locked */ - __HAL_LOCK(hsai); - - /* Pause the audio file playing by disabling the SAI DMA requests */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief Resume the audio stream playing from the Media. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai) -{ - /* Process Locked */ - __HAL_LOCK(hsai); - - /* Enable the SAI DMA requests */ - hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - - /* If the SAI peripheral is still not enabled, enable it */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; -} - -/** - * @brief Stop the audio stream playing from the Media. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hsai); - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Disable the SAI DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI Tx DMA Stream */ - if ((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX)) - { - if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) - { - /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } - } - - /* Abort the SAI Rx DMA Stream */ - if ((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX)) - { - if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) - { - /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } - } - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - /* Set hsai state to ready */ - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return status; -} - -/** - * @brief Abort the current transfer and disable the SAI. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hsai); - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Check SAI DMA is enabled or not */ - if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) - { - /* Disable the SAI DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Abort the SAI Tx DMA Stream */ - if ((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX)) - { - if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) - { - /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } - } - - /* Abort the SAI Rx DMA Stream */ - if ((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX)) - { - if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) - { - /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ - if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER) - { - status = HAL_ERROR; - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - } - } - } - } - /* Disabled All interrupt and clear all the flag */ - hsai->Instance->IMR = 0; - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - - /* Set hsai state to ready */ - hsai->State = HAL_SAI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return status; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) -{ - uint32_t tickstart = HAL_GetTick(); - - if ((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if (hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - hsai->State = HAL_SAI_STATE_BUSY_TX; - - /* Set the SAI Tx DMA Half transfer complete callback */ - hsai->hdmatx->XferHalfCpltCallback = SAI_DMATxHalfCplt; - - /* Set the SAI TxDMA transfer complete callback */ - hsai->hdmatx->XferCpltCallback = SAI_DMATxCplt; - - /* Set the DMA error callback */ - hsai->hdmatx->XferErrorCallback = SAI_DMAError; - - /* Set the DMA Tx abort callback */ - hsai->hdmatx->XferAbortCallback = NULL; - - /* Enable the Tx DMA Stream */ - if (HAL_DMA_Start_IT(hsai->hdmatx, (uint32_t)hsai->pBuffPtr, (uint32_t)&hsai->Instance->DR, hsai->XferSize) != HAL_OK) - { - __HAL_UNLOCK(hsai); - return HAL_ERROR; - } - - /* Enable the interrupts for error handling */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - /* Enable SAI Tx DMA Request */ - hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - - /* Wait until FIFO is not empty */ - while ((hsai->Instance->SR & SAI_xSR_FLVL) == SAI_FIFOSTATUS_EMPTY) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > SAI_LONG_TIMEOUT) - { - /* Update error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_TIMEOUT; - } - } - - /* Check if the SAI is already enabled */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param pData Pointer to data buffer - * @param Size Amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size) -{ - - if ((pData == NULL) || (Size == 0)) - { - return HAL_ERROR; - } - - if (hsai->State == HAL_SAI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsai); - - hsai->pBuffPtr = pData; - hsai->XferSize = Size; - hsai->XferCount = Size; - hsai->ErrorCode = HAL_SAI_ERROR_NONE; - hsai->State = HAL_SAI_STATE_BUSY_RX; - - /* Set the SAI Rx DMA Half transfer complete callback */ - hsai->hdmarx->XferHalfCpltCallback = SAI_DMARxHalfCplt; - - /* Set the SAI Rx DMA transfer complete callback */ - hsai->hdmarx->XferCpltCallback = SAI_DMARxCplt; - - /* Set the DMA error callback */ - hsai->hdmarx->XferErrorCallback = SAI_DMAError; - - /* Set the DMA Rx abort callback */ - hsai->hdmarx->XferAbortCallback = NULL; - - /* Enable the Rx DMA Stream */ - if (HAL_DMA_Start_IT(hsai->hdmarx, (uint32_t)&hsai->Instance->DR, (uint32_t)hsai->pBuffPtr, hsai->XferSize) != HAL_OK) - { - __HAL_UNLOCK(hsai); - return HAL_ERROR; - } - - /* Enable the interrupts for error handling */ - __HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - /* Enable SAI Rx DMA Request */ - hsai->Instance->CR1 |= SAI_xCR1_DMAEN; - - /* Check if the SAI is already enabled */ - if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == RESET) - { - /* Enable SAI peripheral */ - __HAL_SAI_ENABLE(hsai); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsai); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable the Tx mute mode. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param val value sent during the mute @ref SAI_Block_Mute_Value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val) -{ - assert_param(IS_SAI_BLOCK_MUTE_VALUE(val)); - - if (hsai->State != HAL_SAI_STATE_RESET) - { - CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); - SET_BIT(hsai->Instance->CR2, SAI_xCR2_MUTE | val); - return HAL_OK; - } - return HAL_ERROR; -} - -/** - * @brief Disable the Tx mute mode. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai) -{ - if (hsai->State != HAL_SAI_STATE_RESET) - { - CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTEVAL | SAI_xCR2_MUTE); - return HAL_OK; - } - return HAL_ERROR; -} - -/** - * @brief Enable the Rx mute detection. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param callback function called when the mute is detected. - * @param counter number a data before mute detection max 63. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter) -{ - assert_param(IS_SAI_BLOCK_MUTE_COUNTER(counter)); - - if (hsai->State != HAL_SAI_STATE_RESET) - { - /* set the mute counter */ - CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT); - SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos)); - hsai->mutecallback = callback; - /* enable the IT interrupt */ - __HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET); - return HAL_OK; - } - return HAL_ERROR; -} - -/** - * @brief Disable the Rx mute detection. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai) -{ - if (hsai->State != HAL_SAI_STATE_RESET) - { - /* set the mutecallback to NULL */ - hsai->mutecallback = (SAIcallback)NULL; - /* enable the IT interrupt */ - __HAL_SAI_DISABLE_IT(hsai, SAI_IT_MUTEDET); - return HAL_OK; - } - return HAL_ERROR; -} - -/** - * @brief Handle SAI interrupt request. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai) -{ - if (hsai->State != HAL_SAI_STATE_RESET) - { - uint32_t itflags = hsai->Instance->SR; - uint32_t itsources = hsai->Instance->IMR; - uint32_t cr1config = hsai->Instance->CR1; - uint32_t tmperror; - - /* SAI Fifo request interrupt occurred ------------------------------------*/ - if (((itflags & SAI_xSR_FREQ) == SAI_xSR_FREQ) && ((itsources & SAI_IT_FREQ) == SAI_IT_FREQ)) - { - hsai->InterruptServiceRoutine(hsai); - } - /* SAI Overrun error interrupt occurred ----------------------------------*/ - else if (((itflags & SAI_FLAG_OVRUDR) == SAI_FLAG_OVRUDR) && ((itsources & SAI_IT_OVRUDR) == SAI_IT_OVRUDR)) - { - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - /* Get the SAI error code */ - tmperror = ((hsai->State == HAL_SAI_STATE_BUSY_RX) ? HAL_SAI_ERROR_OVR : HAL_SAI_ERROR_UDR); - /* Change the SAI error code */ - hsai->ErrorCode |= tmperror; - /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->ErrorCallback(hsai); -#else - HAL_SAI_ErrorCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - /* SAI mutedet interrupt occurred ----------------------------------*/ - else if (((itflags & SAI_FLAG_MUTEDET) == SAI_FLAG_MUTEDET) && ((itsources & SAI_IT_MUTEDET) == SAI_IT_MUTEDET)) - { - /* Clear the SAI mutedet flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_MUTEDET); - /* call the call back function */ - if (hsai->mutecallback != (SAIcallback)NULL) - { - /* inform the user that an RX mute event has been detected */ - hsai->mutecallback(); - } - } - /* SAI AFSDET interrupt occurred ----------------------------------*/ - else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) - { - /* Clear the SAI AFSDET flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET); - - /* Change the SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; - /* Check SAI DMA is enabled or not */ - if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) - { - /* Abort the SAI DMA Streams */ - if (hsai->hdmatx != NULL) - { - /* Set the DMA Tx abort callback */ - hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); - } - else if (hsai->hdmarx != NULL) - { - /* Set the DMA Rx abort callback */ - hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); - } - } - else - { - /* Abort SAI */ - HAL_SAI_Abort(hsai); - - /* Set error callback */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->ErrorCallback(hsai); -#else - HAL_SAI_ErrorCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - } - /* SAI LFSDET interrupt occurred ----------------------------------*/ - else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) - { - /* Clear the SAI LFSDET flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET); - - /* Change the SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; - - /* Check SAI DMA is enabled or not */ - if ((cr1config & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) - { - /* Abort the SAI DMA Streams */ - if (hsai->hdmatx != NULL) - { - /* Set the DMA Tx abort callback */ - hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); - } - else if (hsai->hdmarx != NULL) - { - /* Set the DMA Rx abort callback */ - hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); - } - } - else - { - /* Abort SAI */ - HAL_SAI_Abort(hsai); - - /* Set error callback */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->ErrorCallback(hsai); -#else - HAL_SAI_ErrorCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - } - /* SAI WCKCFG interrupt occurred ----------------------------------*/ - else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) - { - /* Clear the SAI WCKCFG flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG); - - /* Change the SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; - - /* Abort the SAI DMA Streams */ - if (hsai->hdmatx != NULL) - { - /* Set the DMA Tx abort callback */ - hsai->hdmatx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmatx); - } - else if (hsai->hdmarx != NULL) - { - /* Set the DMA Rx abort callback */ - hsai->hdmarx->XferAbortCallback = SAI_DMAAbort; - /* Abort DMA in IT mode */ - HAL_DMA_Abort_IT(hsai->hdmarx); - } - else - { - /* If WCKCFG occurs, SAI audio block is automatically disabled */ - /* Disable all interrupts and clear all flags */ - hsai->Instance->IMR = 0U; - hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Set the SAI state to ready to be able to start again the process */ - hsai->State = HAL_SAI_STATE_READY; - - /* Initialize XferCount */ - hsai->XferCount = 0U; - - /* SAI error Callback */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->ErrorCallback(hsai); -#else - HAL_SAI_ErrorCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - } - /* SAI CNRDY interrupt occurred ----------------------------------*/ - else if (((itflags & SAI_FLAG_CNRDY) == SAI_FLAG_CNRDY) && ((itsources & SAI_IT_CNRDY) == SAI_IT_CNRDY)) - { - /* Clear the SAI CNRDY flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_CNRDY); - /* Change the SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_CNREADY; - /* the transfer is not stopped, we will forward the information to the user and we let the user decide what needs to be done */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->ErrorCallback(hsai); -#else - HAL_SAI_ErrorCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } - } -} - -/** - * @brief Tx Transfer completed callback. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer Half completed callback. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer half completed callback. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SAI error callback. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -__weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsai); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SAI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SAI_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the SAI handle state. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval HAL state - */ -HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) -{ - return hsai->State; -} - -/** - * @brief Return the SAI error code. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for the specified SAI Block. -* @retval SAI Error Code -*/ -uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) -{ - return hsai->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup SAI_Private_Functions - * @brief Private functions - * @{ - */ - -/** - * @brief Initialize the SAI I2S protocol according to the specified parameters - * in the SAI_InitTypeDef and create the associated handle. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param protocol one of the supported protocol. - * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize - * the configuration information for SAI module. - * @param nbslot number of slot minimum value is 2 and max is 16. - * the value must be a multiple of 2. - * @retval HAL status - */ -static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) -{ - hsai->Init.Protocol = SAI_FREE_PROTOCOL; - hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; - /* Compute ClockStrobing according AudioMode */ - if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { - /* Transmit */ - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; - } - else - { - /* Receive */ - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; - } - hsai->FrameInit.FSDefinition = SAI_FS_CHANNEL_IDENTIFICATION; - hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - hsai->SlotInit.FirstBitOffset = 0; - hsai->SlotInit.SlotNumber = nbslot; - - /* in IS2 the number of slot must be even */ - if ((nbslot & 0x1) != 0) - { - return HAL_ERROR; - } - - if (protocol == SAI_I2S_STANDARD) - { - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; - hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - } - else - { - /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */ - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; - hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; - } - - /* Frame definition */ - switch (datasize) - { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32 * (nbslot / 2); - hsai->FrameInit.ActiveFrameLength = 16 * (nbslot / 2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 64 * (nbslot / 2); - hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT: - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 64 * (nbslot / 2); - hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 64 * (nbslot / 2); - hsai->FrameInit.ActiveFrameLength = 32 * (nbslot / 2); - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; - } - if (protocol == SAI_I2S_LSBJUSTIFIED) - { - if (datasize == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) - { - hsai->SlotInit.FirstBitOffset = 16; - } - if (datasize == SAI_PROTOCOL_DATASIZE_24BIT) - { - hsai->SlotInit.FirstBitOffset = 8; - } - } - return HAL_OK; -} - -/** - * @brief Initialize the SAI PCM protocol according to the specified parameters - * in the SAI_InitTypeDef and create the associated handle. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param protocol one of the supported protocol - * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize - * @param nbslot number of slot minimum value is 1 and the max is 16. - * @retval HAL status - */ -static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot) -{ - hsai->Init.Protocol = SAI_FREE_PROTOCOL; - hsai->Init.FirstBit = SAI_FIRSTBIT_MSB; - /* Compute ClockStrobing according AudioMode */ - if ((hsai->Init.AudioMode == SAI_MODEMASTER_TX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { - /* Transmit */ - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_RISINGEDGE; - } - else - { - /* Receive */ - hsai->Init.ClockStrobing = SAI_CLOCKSTROBING_FALLINGEDGE; - } - hsai->FrameInit.FSDefinition = SAI_FS_STARTFRAME; - hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; - hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; - hsai->SlotInit.FirstBitOffset = 0; - hsai->SlotInit.SlotNumber = nbslot; - hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; - - if (protocol == SAI_PCM_SHORT) - { - hsai->FrameInit.ActiveFrameLength = 1; - } - else - { - /* SAI_PCM_LONG */ - hsai->FrameInit.ActiveFrameLength = 13; - } - - switch (datasize) - { - case SAI_PROTOCOL_DATASIZE_16BIT: - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 16 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_16B; - break; - case SAI_PROTOCOL_DATASIZE_16BITEXTENDED : - hsai->Init.DataSize = SAI_DATASIZE_16; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_24BIT : - hsai->Init.DataSize = SAI_DATASIZE_24; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - case SAI_PROTOCOL_DATASIZE_32BIT: - hsai->Init.DataSize = SAI_DATASIZE_32; - hsai->FrameInit.FrameLength = 32 * nbslot; - hsai->SlotInit.SlotSize = SAI_SLOTSIZE_32B; - break; - default : - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Fill the fifo. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_FillFifo(SAI_HandleTypeDef *hsai) -{ - /* fill the fifo with data before to enabled the SAI */ - while (((hsai->Instance->SR & SAI_xSR_FLVL) != SAI_FIFOSTATUS_FULL) && (hsai->XferCount > 0)) - { - if ((hsai->Init.DataSize == SAI_DATASIZE_8) && (hsai->Init.CompandingMode == SAI_NOCOMPANDING)) - { - hsai->Instance->DR = (*hsai->pBuffPtr++); - } - else if (hsai->Init.DataSize <= SAI_DATASIZE_16) - { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr += 2; - } - else - { - hsai->Instance->DR = *((uint32_t *)hsai->pBuffPtr); - hsai->pBuffPtr += 4; - } - hsai->XferCount--; - } -} - -/** - * @brief Return the interrupt flag to set according the SAI setup. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @param mode SAI_MODE_DMA or SAI_MODE_IT - * @retval the list of the IT flag to enable - */ -static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode) -{ - uint32_t tmpIT = SAI_IT_OVRUDR; - - if (mode == SAI_MODE_IT) - { - tmpIT |= SAI_IT_FREQ; - } - - if ((hsai->Init.Protocol == SAI_AC97_PROTOCOL) && - ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODEMASTER_RX))) - { - tmpIT |= SAI_IT_CNRDY; - } - - if ((hsai->Init.AudioMode == SAI_MODESLAVE_RX) || (hsai->Init.AudioMode == SAI_MODESLAVE_TX)) - { - tmpIT |= SAI_IT_AFSDET | SAI_IT_LFSDET; - } - else - { - /* hsai has been configured in master mode */ - tmpIT |= SAI_IT_WCKCFG; - } - return tmpIT; -} - -/** - * @brief Disable the SAI and wait for the disabling. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static HAL_StatusTypeDef SAI_Disable(SAI_HandleTypeDef *hsai) -{ - uint32_t count = SAI_DEFAULT_TIMEOUT * (SystemCoreClock / 7 / 1000); - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the SAI instance */ - __HAL_SAI_DISABLE(hsai); - - do - { - /* Check for the Timeout */ - if (count-- == 0) - { - /* Update error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_TIMEOUT; - status = HAL_TIMEOUT; - break; - } - } - while ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) != RESET); - - return status; -} - -/** - * @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Transmit_IT8Bit(SAI_HandleTypeDef *hsai) -{ - if (hsai->XferCount == 0) - { - /* Handle the end of the transmission */ - /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - hsai->State = HAL_SAI_STATE_READY; -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->TxCpltCallback(hsai); -#else - HAL_SAI_TxCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - else - { - /* Write data on DR register */ - hsai->Instance->DR = (*hsai->pBuffPtr++); - hsai->XferCount--; - } -} - -/** - * @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Transmit_IT16Bit(SAI_HandleTypeDef *hsai) -{ - if (hsai->XferCount == 0) - { - /* Handle the end of the transmission */ - /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - hsai->State = HAL_SAI_STATE_READY; -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->TxCpltCallback(hsai); -#else - HAL_SAI_TxCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - else - { - /* Write data on DR register */ - hsai->Instance->DR = *(uint16_t *)hsai->pBuffPtr; - hsai->pBuffPtr += 2; - hsai->XferCount--; - } -} - -/** - * @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Transmit_IT32Bit(SAI_HandleTypeDef *hsai) -{ - if (hsai->XferCount == 0) - { - /* Handle the end of the transmission */ - /* Disable FREQ and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - hsai->State = HAL_SAI_STATE_READY; -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->TxCpltCallback(hsai); -#else - HAL_SAI_TxCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } - else - { - /* Write data on DR register */ - hsai->Instance->DR = *(uint32_t *)hsai->pBuffPtr; - hsai->pBuffPtr += 4; - hsai->XferCount--; - } -} - -/** - * @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Receive_IT8Bit(SAI_HandleTypeDef *hsai) -{ - /* Receive data */ - (*hsai->pBuffPtr++) = hsai->Instance->DR; - hsai->XferCount--; - - /* Check end of the transfer */ - if (hsai->XferCount == 0) - { - /* Disable TXE and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - - hsai->State = HAL_SAI_STATE_READY; -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->RxCpltCallback(hsai); -#else - HAL_SAI_RxCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Receive_IT16Bit(SAI_HandleTypeDef *hsai) -{ - /* Receive data */ - *(uint16_t *)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr += 2; - hsai->XferCount--; - - /* Check end of the transfer */ - if (hsai->XferCount == 0) - { - /* Disable TXE and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - - hsai->State = HAL_SAI_STATE_READY; -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->RxCpltCallback(hsai); -#else - HAL_SAI_RxCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer. - * @param hsai pointer to a SAI_HandleTypeDef structure that contains - * the configuration information for SAI module. - * @retval None - */ -static void SAI_Receive_IT32Bit(SAI_HandleTypeDef *hsai) -{ - /* Receive data */ - *(uint32_t *)hsai->pBuffPtr = hsai->Instance->DR; - hsai->pBuffPtr += 4; - hsai->XferCount--; - - /* Check end of the transfer */ - if (hsai->XferCount == 0) - { - /* Disable TXE and OVRUDR interrupts */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_IT)); - - /* Clear the SAI Overrun flag */ - __HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_OVRUDR); - - hsai->State = HAL_SAI_STATE_READY; -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->RxCpltCallback(hsai); -#else - HAL_SAI_RxCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA SAI transmit process complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMATxCplt(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma->Init.Mode != DMA_CIRCULAR) - { - hsai->XferCount = 0; - - /* Disable SAI Tx DMA Request */ - hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); - - /* Stop the interrupts error handling */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - hsai->State = HAL_SAI_STATE_READY; - } -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->TxCpltCallback(hsai); -#else - HAL_SAI_TxCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SAI transmit process half complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->TxHalfCpltCallback(hsai); -#else - HAL_SAI_TxHalfCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SAI receive process complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma->Init.Mode != DMA_CIRCULAR) - { - /* Disable Rx DMA Request */ - hsai->Instance->CR1 &= (uint32_t)(~SAI_xCR1_DMAEN); - hsai->XferCount = 0; - - /* Stop the interrupts error handling */ - __HAL_SAI_DISABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA)); - - hsai->State = HAL_SAI_STATE_READY; - } -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->RxCpltCallback(hsai); -#else - HAL_SAI_RxCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SAI receive process half complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->RxHalfCpltCallback(hsai); -#else - HAL_SAI_RxHalfCpltCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SAI communication error callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMAError(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Set SAI error code */ - hsai->ErrorCode |= HAL_SAI_ERROR_DMA; - - if ((hsai->hdmatx->ErrorCode == HAL_DMA_ERROR_TE) || (hsai->hdmarx->ErrorCode == HAL_DMA_ERROR_TE)) - { - /* Disable the SAI DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Set the SAI state ready to be able to start again the process */ - hsai->State = HAL_SAI_STATE_READY; - - /* Initialize XferCount */ - hsai->XferCount = 0U; - } - /* SAI error Callback */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->ErrorCallback(hsai); -#else - HAL_SAI_ErrorCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SAI Abort callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) -{ - SAI_HandleTypeDef *hsai = (SAI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable DMA request */ - hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; - - /* Disable all interrupts and clear all flags */ - hsai->Instance->IMR = 0U; - hsai->Instance->CLRFR = 0xFFFFFFFFU; - - if (hsai->ErrorCode != HAL_SAI_ERROR_WCKCFG) - { - /* Disable SAI peripheral */ - SAI_Disable(hsai); - - /* Flush the fifo */ - SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); - } - /* Set the SAI state to ready to be able to start again the process */ - hsai->State = HAL_SAI_STATE_READY; - - /* Initialize XferCount */ - hsai->XferCount = 0U; - - /* SAI error Callback */ -#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) - hsai->ErrorCallback(hsai); -#else - HAL_SAI_ErrorCallback(hsai); -#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */ -} - -/** - * @} - */ - -#endif /* HAL_SAI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai_ex.c deleted file mode 100644 index fc56356c..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sai_ex.c +++ /dev/null @@ -1,32 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sai_ex.c - * @author MCD Application Team - * @brief Empty file; This file is no longer used to set synchronization and - * to get SAI block frequency. Its content is now moved to common files - * (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7 - * family. It's just kept for compatibility reasons. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c index 4b9e95d5..29e4ceae 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sd.c @@ -1,3224 +1,3219 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sd.c - * @author MCD Application Team - * @brief SD card HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Secure Digital (SD) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver implements a high level communication layer for read and write from/to - this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by - the user in HAL_SD_MspInit() function (MSP layer). - Basically, the MSP layer configuration should be the same as we provide in the - examples. - You can easily tailor this configuration according to hardware resources. - - [..] - This driver is a generic layered driver for SDMMC memories which uses the HAL - SDMMC driver functions to interface with SD and uSD cards devices. - It is used as follows: - - (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API: - (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); - (##) SDMMC pins configuration for SD card - (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() - and according to your pin assignment; - (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() - and HAL_SD_WriteBlocks_DMA() APIs). - (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); - (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. - (##) NVIC configuration if you need to use interrupt process when using DMA transfer. - (+++) Configure the SDMMC and DMA interrupt priorities using functions - HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority - (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() - and __HAL_SD_DISABLE_IT() inside the communication process. - (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() - and __HAL_SD_CLEAR_IT() - (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() - and HAL_SD_WriteBlocks_IT() APIs). - (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); - (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() - (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() - and __HAL_SD_DISABLE_IT() inside the communication process. - (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() - and __HAL_SD_CLEAR_IT() - (#) At this stage, you can perform SD read/write/erase operations after SD card initialization - - - *** SD Card Initialization and configuration *** - ================================================ - [..] - To initialize the SD Card, use the HAL_SD_Init() function. It Initializes - SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). - This function provide the following operations: - - (#) Apply the SD Card initialization process at 400KHz and check the SD Card - type (Standard Capacity or High Capacity). You can change or adapt this - frequency by adjusting the "ClockDiv" field. - The SD Card frequency (SDMMC_CK) is computed as follows: - - SDMMC_CK = SDMMCCLK / (ClockDiv + 2) - - In initialization mode and according to the SD Card standard, - make sure that the SDMMC_CK frequency doesn't exceed 400KHz. - - This phase of initialization is done through SDMMC_Init() and - SDMMC_PowerState_ON() SDMMC low level APIs. - - (#) Initialize the SD card. The API used is HAL_SD_InitCard(). - This phase allows the card initialization and identification - and check the SD Card type (Standard Capacity or High Capacity) - The initialization flow is compatible with SD standard. - - This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case - of plug-off plug-in. - - (#) Configure the SD Card Data transfer frequency. You can change or adapt this - frequency by adjusting the "ClockDiv" field. - In transfer mode and according to the SD Card standard, make sure that the - SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. - To be able to use a frequency higher than 24MHz, you should use the SDMMC - peripheral in bypass mode. Refer to the corresponding reference manual - for more details. - - (#) Select the corresponding SD Card according to the address read with the step 2. - - (#) Configure the SD Card in wide bus mode: 4-bits data. - - *** SD Card Read operation *** - ============================== - [..] - (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_SD_GetCardState() function for SD card state. - - (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_SD_GetCardState() function for SD card state. - You could also check the DMA transfer process through the SD Rx interrupt event. - - (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_SD_GetCardState() function for SD card state. - You could also check the IT transfer process through the SD Rx interrupt event. - - *** SD Card Write operation *** - =============================== - [..] - (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_SD_GetCardState() function for SD card state. - - (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_SD_GetCardState() function for SD card state. - You could also check the DMA transfer process through the SD Tx interrupt event. - - (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). - This function support only 512-bytes block length (the block size should be - chosen as 512 bytes). - You can choose either one block read operation or multiple block read operation - by adjusting the "NumberOfBlocks" parameter. - After this, you have to ensure that the transfer is done correctly. The check is done - through HAL_SD_GetCardState() function for SD card state. - You could also check the IT transfer process through the SD Tx interrupt event. - - *** SD card status *** - ====================== - [..] - (+) The SD Status contains status bits that are related to the SD Memory - Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). - - *** SD card information *** - =========================== - [..] - (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). - It returns useful information about the SD card such as block size, card type, - block number ... - - *** SD card CSD register *** - ============================ - (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. - Some of the CSD parameters are useful for card initialization and identification. - - *** SD card CID register *** - ============================ - (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. - Some of the CSD parameters are useful for card initialization and identification. - - *** SD HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in SD HAL driver. - - (+) __HAL_SD_ENABLE : Enable the SD device - (+) __HAL_SD_DISABLE : Disable the SD device - (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer - (+) __HAL_SD_DMA_DISABLE: Disable the SDMMC DMA transfer - (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt - (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt - (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not - (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags - - (@) You can refer to the SD HAL driver header file for more useful macros - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - Use Functions HAL_SD_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) MspInitCallback : SD MspInit. - (+) MspDeInitCallback : SD MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_SD_UnRegisterCallback() to reset a callback to the default - weak (surcharged) function. It allows to reset following callbacks: - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) MspInitCallback : SD MspInit. - (+) MspDeInitCallback : SD MspDeInit. - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET - all callbacks are reset to the corresponding legacy weak (surcharged) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the HAL_SD_Init - and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_SD_RegisterCallback before calling HAL_SD_DeInit - or HAL_SD_Init function. - - When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -#if defined(SDMMC1) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup SD - * @{ - */ - -#ifdef HAL_SD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup SD_Private_Defines - * @{ - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup SD_Private_Functions SD Private Functions - * @{ - */ -static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); -static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); -static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); -static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); -static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); -static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); -static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); -static void SD_PowerOFF(SD_HandleTypeDef *hsd); -static void SD_Write_IT(SD_HandleTypeDef *hsd); -static void SD_Read_IT(SD_HandleTypeDef *hsd); -static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SD_DMAError(DMA_HandleTypeDef *hdma); -static void SD_DMATxAbort(DMA_HandleTypeDef *hdma); -static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SD_Exported_Functions - * @{ - */ - -/** @addtogroup SD_Exported_Functions_Group1 - * @brief Initialization and de-initialization functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize the SD - card device to be ready for use. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SD according to the specified parameters in the - SD_HandleTypeDef and create the associated handle. - * @param hsd: Pointer to the SD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) -{ - /* Check the SD handle allocation */ - if(hsd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); - assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge)); - assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass)); - assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); - assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); - assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); - assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); - - if(hsd->State == HAL_SD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsd->Lock = HAL_UNLOCKED; -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - /* Reset Callback pointers in HAL_SD_STATE_RESET only */ - hsd->TxCpltCallback = HAL_SD_TxCpltCallback; - hsd->RxCpltCallback = HAL_SD_RxCpltCallback; - hsd->ErrorCallback = HAL_SD_ErrorCallback; - hsd->AbortCpltCallback = HAL_SD_AbortCallback; - - if(hsd->MspInitCallback == NULL) - { - hsd->MspInitCallback = HAL_SD_MspInit; - } - - /* Init the low level hardware */ - hsd->MspInitCallback(hsd); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_SD_MspInit(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - - hsd->State = HAL_SD_STATE_BUSY; - - /* Initialize the Card parameters */ - if (HAL_SD_InitCard(hsd) != HAL_OK) - { - return HAL_ERROR; - } - - /* Initialize the error code */ - hsd->ErrorCode = HAL_SD_ERROR_NONE; - - /* Initialize the SD operation */ - hsd->Context = SD_CONTEXT_NONE; - - /* Initialize the SD state */ - hsd->State = HAL_SD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Initializes the SD Card. - * @param hsd: Pointer to SD handle - * @note This function initializes the SD card. It could be used when a card - re-initialization is needed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) -{ - uint32_t errorstate; - HAL_StatusTypeDef status; - SD_InitTypeDef Init; - - /* Default SDMMC peripheral configuration for SD card initialization */ - Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; - Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; - Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; - Init.BusWide = SDMMC_BUS_WIDE_1B; - Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; - Init.ClockDiv = SDMMC_INIT_CLK_DIV; - - /* Initialize SDMMC peripheral interface with default configuration */ - status = SDMMC_Init(hsd->Instance, Init); - if(status != HAL_OK) - { - return HAL_ERROR; - } - - /* Disable SDMMC Clock */ - __HAL_SD_DISABLE(hsd); - - /* Set Power State to ON */ - (void)SDMMC_PowerState_ON(hsd->Instance); - - /* Enable SDMMC Clock */ - __HAL_SD_ENABLE(hsd); - - /* Required power up waiting time before starting the SD initialization sequence */ - HAL_Delay(2); - - /* Identify card operating voltage */ - errorstate = SD_PowerON(hsd); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->State = HAL_SD_STATE_READY; - hsd->ErrorCode |= errorstate; - return HAL_ERROR; - } - - /* Card initialization */ - errorstate = SD_InitCard(hsd); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->State = HAL_SD_STATE_READY; - hsd->ErrorCode |= errorstate; - return HAL_ERROR; - } - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief De-Initializes the SD card. - * @param hsd: Pointer to SD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) -{ - /* Check the SD handle allocation */ - if(hsd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); - - hsd->State = HAL_SD_STATE_BUSY; - - /* Set SD power state to off */ - SD_PowerOFF(hsd); - -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - if(hsd->MspDeInitCallback == NULL) - { - hsd->MspDeInitCallback = HAL_SD_MspDeInit; - } - - /* DeInit the low level hardware */ - hsd->MspDeInitCallback(hsd); -#else - /* De-Initialize the MSP layer */ - HAL_SD_MspDeInit(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - - hsd->ErrorCode = HAL_SD_ERROR_NONE; - hsd->State = HAL_SD_STATE_RESET; - - return HAL_OK; -} - - -/** - * @brief Initializes the SD MSP. - * @param hsd: Pointer to SD handle - * @retval None - */ -__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_MspInit could be implemented in the user file - */ -} - -/** - * @brief De-Initialize SD MSP. - * @param hsd: Pointer to SD handle - * @retval None - */ -__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @addtogroup SD_Exported_Functions_Group2 - * @brief Data transfer functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the data - transfer from/to SD card. - -@endverbatim - * @{ - */ - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by polling mode. - * @note This API should be followed by a check on the card state through - * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param pData: pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of SD blocks to read - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; - uint32_t add = BlockAdd; - uint8_t *tempbuff = pData; - - if(NULL == pData) - { - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - return HAL_ERROR; - } - - if(hsd->State == HAL_SD_STATE_READY) - { - hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) - { - hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hsd->State = HAL_SD_STATE_BUSY; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0U; - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) - { - add *= 512U; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * BLOCKSIZE; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hsd->Instance, &config); - - /* Read block(s) in polling mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); - } - else - { - hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; - - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - - /* Poll on SDMMC flags */ - dataremaining = config.DataLength; - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) - { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) - { - /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) - { - data = SDMMC_ReadFIFO(hsd->Instance); - *tempbuff = (uint8_t)(data & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); - tempbuff++; - dataremaining--; - } - } - - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_TIMEOUT; - } - } - - /* Send stop transmission command in case of multiblock read */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) - { - if(hsd->SdCard.CardType != CARD_SECURED) - { - /* Send stop transmission command */ - errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - } - } - - /* Get error state */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - else - { - /* Nothing to do */ - } - - /* Empty FIFO if there is still any data */ - while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) - { - data = SDMMC_ReadFIFO(hsd->Instance); - *tempbuff = (uint8_t)(data & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); - tempbuff++; - dataremaining--; - *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); - tempbuff++; - dataremaining--; - - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; - hsd->State= HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - } - - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - hsd->State = HAL_SD_STATE_READY; - - return HAL_OK; - } - else - { - hsd->ErrorCode |= HAL_SD_ERROR_BUSY; - return HAL_ERROR; - } -} - -/** - * @brief Allows to write block(s) to a specified address in a card. The Data - * transfer is managed by polling mode. - * @note This API should be followed by a check on the card state through - * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param pData: pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of SD blocks to write - * @param Timeout: Specify timeout value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t tickstart = HAL_GetTick(); - uint32_t count, data, dataremaining; - uint32_t add = BlockAdd; - uint8_t *tempbuff = pData; - - if(NULL == pData) - { - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - return HAL_ERROR; - } - - if(hsd->State == HAL_SD_STATE_READY) - { - hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) - { - hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hsd->State = HAL_SD_STATE_BUSY; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0U; - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) - { - add *= 512U; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = NumberOfBlocks * BLOCKSIZE; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hsd->Instance, &config); - - /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); - } - else - { - hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; - - /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - - /* Write block(s) in polling mode */ - dataremaining = config.DataLength; - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) - { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) - { - /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) - { - data = (uint32_t)(*tempbuff); - tempbuff++; - dataremaining--; - data |= ((uint32_t)(*tempbuff) << 8U); - tempbuff++; - dataremaining--; - data |= ((uint32_t)(*tempbuff) << 16U); - tempbuff++; - dataremaining--; - data |= ((uint32_t)(*tempbuff) << 24U); - tempbuff++; - dataremaining--; - (void)SDMMC_WriteFIFO(hsd->Instance, &data); - } - } - - if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_TIMEOUT; - } - } - - /* Send stop transmission command in case of multiblock write */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) - { - if(hsd->SdCard.CardType != CARD_SECURED) - { - /* Send stop transmission command */ - errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - } - } - - /* Get error state */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - else - { - /* Nothing to do */ - } - - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - hsd->State = HAL_SD_STATE_READY; - - return HAL_OK; - } - else - { - hsd->ErrorCode |= HAL_SD_ERROR_BUSY; - return HAL_ERROR; - } -} - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed in interrupt mode. - * @note This API should be followed by a check on the card state through - * HAL_SD_GetCardState(). - * @note You could also check the IT transfer process through the SD Rx - * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t add = BlockAdd; - - if(NULL == pData) - { - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - return HAL_ERROR; - } - - if(hsd->State == HAL_SD_STATE_READY) - { - hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) - { - hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hsd->State = HAL_SD_STATE_BUSY; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0U; - - hsd->pRxBuffPtr = pData; - hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; - - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) - { - add *= 512U; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hsd->Instance, &config); - - /* Read Blocks in IT mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); - } - else - { - hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); - - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed in interrupt mode. - * @note This API should be followed by a check on the card state through - * HAL_SD_GetCardState(). - * @note You could also check the IT transfer process through the SD Tx - * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t add = BlockAdd; - - if(NULL == pData) - { - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - return HAL_ERROR; - } - - if(hsd->State == HAL_SD_STATE_READY) - { - hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) - { - hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hsd->State = HAL_SD_STATE_BUSY; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0U; - - hsd->pTxBuffPtr = pData; - hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; - - /* Enable transfer interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) - { - add *= 512U; - } - - /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); - } - else - { - hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); - - /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hsd->Instance, &config); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads block(s) from a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by a check on the card state through - * HAL_SD_GetCardState(). - * @note You could also check the DMA transfer process through the SD Rx - * interrupt event. - * @param hsd: Pointer SD handle - * @param pData: Pointer to the buffer that will contain the received data - * @param BlockAdd: Block Address from where data is to be read - * @param NumberOfBlocks: Number of blocks to read. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t add = BlockAdd; - - if(NULL == pData) - { - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - return HAL_ERROR; - } - - if(hsd->State == HAL_SD_STATE_READY) - { - hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) - { - hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hsd->State = HAL_SD_STATE_BUSY; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0U; - - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - - /* Set the DMA transfer complete callback */ - hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt; - - /* Set the DMA error callback */ - hsd->hdmarx->XferErrorCallback = SD_DMAError; - - /* Set the DMA Abort callback */ - hsd->hdmarx->XferAbortCallback = NULL; - - /* Force DMA Direction */ - hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; - MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction); - - /* Enable the DMA Channel */ - if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) - { - __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_DMA; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - else - { - /* Enable SD DMA transfer */ - __HAL_SD_DMA_ENABLE(hsd); - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) - { - add *= 512U; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hsd->Instance, &config); - - /* Read Blocks in DMA mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); - - /* Read Multi Block command */ - errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); - } - else - { - hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); - - /* Read Single Block command */ - errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Writes block(s) to a specified address in a card. The Data transfer - * is managed by DMA mode. - * @note This API should be followed by a check on the card state through - * HAL_SD_GetCardState(). - * @note You could also check the DMA transfer process through the SD Tx - * interrupt event. - * @param hsd: Pointer to SD handle - * @param pData: Pointer to the buffer that will contain the data to transmit - * @param BlockAdd: Block Address where data will be written - * @param NumberOfBlocks: Number of blocks to write - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t add = BlockAdd; - - if(NULL == pData) - { - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - return HAL_ERROR; - } - - if(hsd->State == HAL_SD_STATE_READY) - { - hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) - { - hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hsd->State = HAL_SD_STATE_BUSY; - - /* Initialize data control register */ - hsd->Instance->DCTRL = 0U; - - /* Enable SD Error interrupts */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); - - /* Set the DMA transfer complete callback */ - hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt; - - /* Set the DMA error callback */ - hsd->hdmatx->XferErrorCallback = SD_DMAError; - - /* Set the DMA Abort callback */ - hsd->hdmatx->XferAbortCallback = NULL; - - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) - { - add *= 512U; - } - - /* Write Blocks in Polling mode */ - if(NumberOfBlocks > 1U) - { - hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); - - /* Write Multi Block command */ - errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); - } - else - { - hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); - - /* Write Single Block command */ - errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); - } - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - - /* Enable SDMMC DMA transfer */ - __HAL_SD_DMA_ENABLE(hsd); - - /* Force DMA Direction */ - hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; - MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction); - - /* Enable the DMA Channel */ - if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) - { - __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_DMA; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - return HAL_ERROR; - } - else - { - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = BLOCKSIZE * NumberOfBlocks; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hsd->Instance, &config); - - return HAL_OK; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Erases the specified memory area of the given SD card. - * @note This API should be followed by a check on the card state through - * HAL_SD_GetCardState(). - * @param hsd: Pointer to SD handle - * @param BlockStartAdd: Start Block address - * @param BlockEndAdd: End Block address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) -{ - uint32_t errorstate; - uint32_t start_add = BlockStartAdd; - uint32_t end_add = BlockEndAdd; - - if(hsd->State == HAL_SD_STATE_READY) - { - hsd->ErrorCode = HAL_SD_ERROR_NONE; - - if(end_add < start_add) - { - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - return HAL_ERROR; - } - - if(end_add > (hsd->SdCard.LogBlockNbr)) - { - hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; - return HAL_ERROR; - } - - hsd->State = HAL_SD_STATE_BUSY; - - /* Check if the card command class supports erase command */ - if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - - /* Get start and end block for high capacity cards */ - if(hsd->SdCard.CardType != CARD_SDHC_SDXC) - { - start_add *= 512U; - end_add *= 512U; - } - - /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ - if(hsd->SdCard.CardType != CARD_SECURED) - { - /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ - errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - - /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ - errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - } - - /* Send CMD38 ERASE */ - errorstate = SDMMC_CmdErase(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - - hsd->State = HAL_SD_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief This function handles SD card interrupt request. - * @param hsd: Pointer to SD handle - * @retval None - */ -void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) -{ - uint32_t errorstate; - uint32_t context = hsd->Context; - - /* Check for SDMMC interrupt flags */ - if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) - { - SD_Read_IT(hsd); - } - - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) - { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); - - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ - SDMMC_IT_RXFIFOHF); - - hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); - - if((context & SD_CONTEXT_IT) != 0U) - { - if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) - { - errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->ErrorCode |= errorstate; -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->ErrorCallback(hsd); -#else - HAL_SD_ErrorCallback(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - } - - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) - { -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->RxCpltCallback(hsd); -#else - HAL_SD_RxCpltCallback(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - else - { -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->TxCpltCallback(hsd); -#else - HAL_SD_TxCpltCallback(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - } - else if((context & SD_CONTEXT_DMA) != 0U) - { - if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) - { - errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->ErrorCode |= errorstate; -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->ErrorCallback(hsd); -#else - HAL_SD_ErrorCallback(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - } - if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) - { - /* Disable the DMA transfer for transmit request by setting the DMAEN bit - in the SD DCTRL register */ - hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - - hsd->State = HAL_SD_STATE_READY; - -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->TxCpltCallback(hsd); -#else - HAL_SD_TxCpltCallback(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - } - else - { - /* Nothing to do */ - } - } - - else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) - { - SD_Write_IT(hsd); - } - - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) - { - /* Set Error code */ - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL) != RESET) - { - hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; - } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT) != RESET) - { - hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; - } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR) != RESET) - { - hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; - } - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR) != RESET) - { - hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; - } - - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - /* Disable all interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - - if((context & SD_CONTEXT_IT) != 0U) - { - /* Set the SD state to ready to be able to start again the process */ - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->ErrorCallback(hsd); -#else - HAL_SD_ErrorCallback(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - else if((context & SD_CONTEXT_DMA) != 0U) - { - /* Abort the SD DMA channel */ - if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) - { - /* Set the DMA Tx abort callback */ - hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; - /* Abort DMA in IT mode */ - if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) - { - SD_DMATxAbort(hsd->hdmatx); - } - } - else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) - { - /* Set the DMA Rx abort callback */ - hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; - /* Abort DMA in IT mode */ - if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) - { - SD_DMARxAbort(hsd->hdmarx); - } - } - else - { - hsd->ErrorCode = HAL_SD_ERROR_NONE; - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->AbortCpltCallback(hsd); -#else - HAL_SD_AbortCallback(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - } - else - { - /* Nothing to do */ - } - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief return the SD state - * @param hsd: Pointer to sd handle - * @retval HAL state - */ -HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) -{ - return hsd->State; -} - -/** -* @brief Return the SD error code -* @param hsd : Pointer to a SD_HandleTypeDef structure that contains - * the configuration information. -* @retval SD Error Code -*/ -uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) -{ - return hsd->ErrorCode; -} - -/** - * @brief Tx Transfer completed callbacks - * @param hsd: Pointer to SD handle - * @retval None - */ -__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_TxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callbacks - * @param hsd: Pointer SD handle - * @retval None - */ -__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_RxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief SD error callbacks - * @param hsd: Pointer SD handle - * @retval None - */ -__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_ErrorCallback can be implemented in the user file - */ -} - -/** - * @brief SD Abort callbacks - * @param hsd: Pointer SD handle - * @retval None - */ -__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SD_AbortCallback can be implemented in the user file - */ -} - -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User SD Callback - * To be used instead of the weak (surcharged) predefined callback - * @param hsd : SD handle - * @param CallbackID : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID - * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID - * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID - * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID - * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID - * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if(pCallback == NULL) - { - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hsd); - - if(hsd->State == HAL_SD_STATE_READY) - { - switch (CallbackID) - { - case HAL_SD_TX_CPLT_CB_ID : - hsd->TxCpltCallback = pCallback; - break; - case HAL_SD_RX_CPLT_CB_ID : - hsd->RxCpltCallback = pCallback; - break; - case HAL_SD_ERROR_CB_ID : - hsd->ErrorCallback = pCallback; - break; - case HAL_SD_ABORT_CB_ID : - hsd->AbortCpltCallback = pCallback; - break; - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = pCallback; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hsd->State == HAL_SD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = pCallback; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hsd); - return status; -} - -/** - * @brief Unregister a User SD Callback - * SD Callback is redirected to the weak (surcharged) predefined callback - * @param hsd : SD handle - * @param CallbackID : ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID - * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID - * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID - * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID - * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID - * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hsd); - - if(hsd->State == HAL_SD_STATE_READY) - { - switch (CallbackID) - { - case HAL_SD_TX_CPLT_CB_ID : - hsd->TxCpltCallback = HAL_SD_TxCpltCallback; - break; - case HAL_SD_RX_CPLT_CB_ID : - hsd->RxCpltCallback = HAL_SD_RxCpltCallback; - break; - case HAL_SD_ERROR_CB_ID : - hsd->ErrorCallback = HAL_SD_ErrorCallback; - break; - case HAL_SD_ABORT_CB_ID : - hsd->AbortCpltCallback = HAL_SD_AbortCallback; - break; - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = HAL_SD_MspInit; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = HAL_SD_MspDeInit; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hsd->State == HAL_SD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_SD_MSP_INIT_CB_ID : - hsd->MspInitCallback = HAL_SD_MspInit; - break; - case HAL_SD_MSP_DEINIT_CB_ID : - hsd->MspDeInitCallback = HAL_SD_MspDeInit; - break; - default : - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hsd); - return status; -} -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup SD_Exported_Functions_Group3 - * @brief management functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the SD card - operations and get the related information - -@endverbatim - * @{ - */ - -/** - * @brief Returns information the information of the card which are stored on - * the CID register. - * @param hsd: Pointer to SD handle - * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that - * contains all CID register parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) -{ - pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); - - pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U); - - pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U)); - - pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU); - - pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U); - - pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U)); - - pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U); - - pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U); - - pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U); - - pCID->Reserved2 = 1U; - - return HAL_OK; -} - -/** - * @brief Returns information the information of the card which are stored on - * the CSD register. - * @param hsd: Pointer to SD handle - * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that - * contains all CSD register parameters - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) -{ - pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); - - pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); - - pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); - - pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); - - pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); - - pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); - - pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); - - pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); - - pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); - - pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); - - pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); - - pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); - - pCSD->Reserved2 = 0U; /*!< Reserved */ - - if(hsd->SdCard.CardType == CARD_SDSC) - { - pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); - - pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); - - pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); - - pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); - - pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); - - pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); - - hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; - hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); - hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); - - hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); - hsd->SdCard.LogBlockSize = 512U; - } - else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) - { - /* Byte 7 */ - pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); - - hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); - hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; - hsd->SdCard.BlockSize = 512U; - hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; - } - else - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; - hsd->State = HAL_SD_STATE_READY; - return HAL_ERROR; - } - - pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); - - pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); - - pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); - - pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); - - pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); - - pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); - - pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); - - pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); - - pCSD->Reserved3 = 0; - - pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); - - pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); - - pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); - - pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); - - pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); - - pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); - - pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); - - pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); - - pCSD->Reserved4 = 1; - - return HAL_OK; -} - -/** - * @brief Gets the SD status info. - * @param hsd: Pointer to SD handle - * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that - * will contain the SD card status information - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) -{ - uint32_t sd_status[16]; - uint32_t errorstate; - HAL_StatusTypeDef status = HAL_OK; - - errorstate = SD_SendSDStatus(hsd, sd_status); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - hsd->State = HAL_SD_STATE_READY; - status = HAL_ERROR; - } - else - { - pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); - - pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); - - pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); - - pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | - ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); - - pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); - - pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); - - pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); - - pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); - - pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); - - pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); - } - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode = errorstate; - hsd->State = HAL_SD_STATE_READY; - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Gets the SD card info. - * @param hsd: Pointer to SD handle - * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that - * will contain the SD card status information - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) -{ - pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); - pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); - pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); - pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); - pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); - pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); - pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); - pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); - - return HAL_OK; -} - -/** - * @brief Enables wide bus operation for the requested card if supported by - * card. - * @param hsd: Pointer to SD handle - * @param WideMode: Specifies the SD card wide bus mode - * This parameter can be one of the following values: - * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer - * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer - * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) -{ - SDMMC_InitTypeDef Init; - uint32_t errorstate; - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_SDMMC_BUS_WIDE(WideMode)); - - /* Change State */ - hsd->State = HAL_SD_STATE_BUSY; - - if(hsd->SdCard.CardType != CARD_SECURED) - { - if(WideMode == SDMMC_BUS_WIDE_8B) - { - hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - else if(WideMode == SDMMC_BUS_WIDE_4B) - { - errorstate = SD_WideBus_Enable(hsd); - - hsd->ErrorCode |= errorstate; - } - else if(WideMode == SDMMC_BUS_WIDE_1B) - { - errorstate = SD_WideBus_Disable(hsd); - - hsd->ErrorCode |= errorstate; - } - else - { - /* WideMode is not a valid argument*/ - hsd->ErrorCode |= HAL_SD_ERROR_PARAM; - } - } - else - { - /* MMC Card does not support this feature */ - hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->State = HAL_SD_STATE_READY; - status = HAL_ERROR; - } - else - { - /* Configure the SDMMC peripheral */ - Init.ClockEdge = hsd->Init.ClockEdge; - Init.ClockBypass = hsd->Init.ClockBypass; - Init.ClockPowerSave = hsd->Init.ClockPowerSave; - Init.BusWide = WideMode; - Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; - Init.ClockDiv = hsd->Init.ClockDiv; - (void)SDMMC_Init(hsd->Instance, Init); - } - - /* Set Block Size for Card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); - if(errorstate != HAL_SD_ERROR_NONE) - { - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - hsd->ErrorCode |= errorstate; - status = HAL_ERROR; - } - - /* Change State */ - hsd->State = HAL_SD_STATE_READY; - - return status; -} - -/** - * @brief Gets the current sd card data state. - * @param hsd: pointer to SD handle - * @retval Card state - */ -HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) -{ - uint32_t cardstate; - uint32_t errorstate; - uint32_t resp1 = 0; - - errorstate = SD_SendStatus(hsd, &resp1); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->ErrorCode |= errorstate; - } - - cardstate = ((resp1 >> 9U) & 0x0FU); - - return (HAL_SD_CardStateTypeDef)cardstate; -} - -/** - * @brief Abort the current transfer and disable the SD. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains - * the configuration information for SD module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) -{ - HAL_SD_CardStateTypeDef CardState; - uint32_t context = hsd->Context; - - /* DIsable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); - - if ((context & SD_CONTEXT_DMA) != 0U) - { - /* Disable the SD DMA request */ - hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - - /* Abort the SD DMA Tx channel */ - if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) - { - if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK) - { - hsd->ErrorCode |= HAL_SD_ERROR_DMA; - } - } - /* Abort the SD DMA Rx channel */ - else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) - { - if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK) - { - hsd->ErrorCode |= HAL_SD_ERROR_DMA; - } - } - else - { - /* Nothing to do */ - } - } - - hsd->State = HAL_SD_STATE_READY; - - /* Initialize the SD operation */ - hsd->Context = SD_CONTEXT_NONE; - - CardState = HAL_SD_GetCardState(hsd); - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); - } - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) - { - return HAL_ERROR; - } - return HAL_OK; -} - -/** - * @brief Abort the current transfer and disable the SD (IT mode). - * @param hsd: pointer to a SD_HandleTypeDef structure that contains - * the configuration information for SD module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) -{ - HAL_SD_CardStateTypeDef CardState; - uint32_t context = hsd->Context; - - /* Disable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); - - if ((context & SD_CONTEXT_DMA) != 0U) - { - /* Disable the SD DMA request */ - hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - - /* Abort the SD DMA Tx channel */ - if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) - { - hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; - if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) - { - hsd->hdmatx = NULL; - } - } - /* Abort the SD DMA Rx channel */ - else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) - { - hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; - if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) - { - hsd->hdmarx = NULL; - } - } - else - { - /* Nothing to do */ - } - } - /* No transfer ongoing on both DMA channels*/ - else - { - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - CardState = HAL_SD_GetCardState(hsd); - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); - } - if(hsd->ErrorCode != HAL_SD_ERROR_NONE) - { - return HAL_ERROR; - } - else - { -#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) - hsd->AbortCpltCallback(hsd); -#else - HAL_SD_AbortCallback(hsd); -#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ - } - } - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private function ----------------------------------------------------------*/ -/** @addtogroup SD_Private_Functions - * @{ - */ - -/** - * @brief DMA SD transmit process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - - /* Enable DATAEND Interrupt */ - __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND)); -} - -/** - * @brief DMA SD receive process complete callback - * @param hdma: DMA handle - * @retval None - */ -static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - uint32_t errorstate; - - /* Send stop command in multiblock write */ - if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) - { - errorstate = SDMMC_CmdStopTransfer(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->ErrorCode |= errorstate; -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->ErrorCallback(hsd); -#else - HAL_SD_ErrorCallback(hsd); -#endif - } - } - - /* Disable the DMA transfer for transmit request by setting the DMAEN bit - in the SD DCTRL register */ - hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); - - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->RxCpltCallback(hsd); -#else - HAL_SD_RxCpltCallback(hsd); -#endif -} - -/** - * @brief DMA SD communication error callback - * @param hdma: DMA handle - * @retval None - */ -static void SD_DMAError(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - HAL_SD_CardStateTypeDef CardState; - uint32_t RxErrorCode, TxErrorCode; - - /* if DMA error is FIFO error ignore it */ - if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) - { - RxErrorCode = hsd->hdmarx->ErrorCode; - TxErrorCode = hsd->hdmatx->ErrorCode; - if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) - { - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); - - /* Disable All interrupts */ - __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ - SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); - - hsd->ErrorCode |= HAL_SD_ERROR_DMA; - CardState = HAL_SD_GetCardState(hsd); - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - } - - hsd->State= HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - } - -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->ErrorCallback(hsd); -#else - HAL_SD_ErrorCallback(hsd); -#endif - } -} - -/** - * @brief DMA SD Tx Abort callback - * @param hdma: DMA handle - * @retval None - */ -static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - HAL_SD_CardStateTypeDef CardState; - - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - CardState = HAL_SD_GetCardState(hsd); - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - } - - if(hsd->ErrorCode == HAL_SD_ERROR_NONE) - { -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->AbortCpltCallback(hsd); -#else - HAL_SD_AbortCallback(hsd); -#endif - } - else - { -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->ErrorCallback(hsd); -#else - HAL_SD_ErrorCallback(hsd); -#endif - } -} - -/** - * @brief DMA SD Rx Abort callback - * @param hdma: DMA handle - * @retval None - */ -static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) -{ - SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); - HAL_SD_CardStateTypeDef CardState; - - /* Clear All flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - CardState = HAL_SD_GetCardState(hsd); - hsd->State = HAL_SD_STATE_READY; - hsd->Context = SD_CONTEXT_NONE; - if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) - { - hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); - } - - if(hsd->ErrorCode == HAL_SD_ERROR_NONE) - { -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->AbortCpltCallback(hsd); -#else - HAL_SD_AbortCallback(hsd); -#endif - } - else - { -#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) - hsd->ErrorCallback(hsd); -#else - HAL_SD_ErrorCallback(hsd); -#endif - } -} - -/** - * @brief Initializes the sd card. - * @param hsd: Pointer to SD handle - * @retval SD Card error state - */ -static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) -{ - HAL_SD_CardCSDTypeDef CSD; - uint32_t errorstate; - uint16_t sd_rca = 1U; - - /* Check the power State */ - if(SDMMC_GetPowerState(hsd->Instance) == 0U) - { - /* Power off */ - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; - } - - if(hsd->SdCard.CardType != CARD_SECURED) - { - /* Send CMD2 ALL_SEND_CID */ - errorstate = SDMMC_CmdSendCID(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - else - { - /* Get Card identification number data */ - hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); - } - } - - if(hsd->SdCard.CardType != CARD_SECURED) - { - /* Send CMD3 SET_REL_ADDR with argument 0 */ - /* SD Card publishes its RCA. */ - errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - } - if(hsd->SdCard.CardType != CARD_SECURED) - { - /* Get the SD card RCA */ - hsd->SdCard.RelCardAdd = sd_rca; - - /* Send CMD9 SEND_CSD with argument as card's RCA */ - errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - else - { - /* Get Card Specific Data */ - hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); - hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); - hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); - } - } - - /* Get the Card Class */ - hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); - - /* Get CSD parameters */ - if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) - { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - - /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Configure SDMMC peripheral interface */ - (void)SDMMC_Init(hsd->Instance, hsd->Init); - - /* All cards are initialized */ - return HAL_SD_ERROR_NONE; -} - -/** - * @brief Enquires cards about their operating voltage and configures clock - * controls and stores SD information that will be needed in future - * in the SD handle. - * @param hsd: Pointer to SD handle - * @retval error state - */ -static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) -{ - __IO uint32_t count = 0U; - uint32_t response = 0U, validvoltage = 0U; - uint32_t errorstate; - - /* CMD0: GO_IDLE_STATE */ - errorstate = SDMMC_CmdGoIdleState(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ - errorstate = SDMMC_CmdOperCond(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->SdCard.CardVersion = CARD_V1_X; - /* CMD0: GO_IDLE_STATE */ - errorstate = SDMMC_CmdGoIdleState(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - } - else - { - hsd->SdCard.CardVersion = CARD_V2_X; - } - - if( hsd->SdCard.CardVersion == CARD_V2_X) - { - /* SEND CMD55 APP_CMD with RCA as 0 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) - { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - } - /* SD CARD */ - /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ - while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) - { - /* SEND CMD55 APP_CMD with RCA as 0 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Send CMD41 */ - errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); - if(errorstate != HAL_SD_ERROR_NONE) - { - return HAL_SD_ERROR_UNSUPPORTED_FEATURE; - } - - /* Get command response */ - response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - /* Get operating voltage*/ - validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); - - count++; - } - - if(count >= SDMMC_MAX_VOLT_TRIAL) - { - return HAL_SD_ERROR_INVALID_VOLTRANGE; - } - - if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ - { - hsd->SdCard.CardType = CARD_SDHC_SDXC; - } - else - { - hsd->SdCard.CardType = CARD_SDSC; - } - - - return HAL_SD_ERROR_NONE; -} - -/** - * @brief Turns the SDMMC output signals off. - * @param hsd: Pointer to SD handle - * @retval None - */ -static void SD_PowerOFF(SD_HandleTypeDef *hsd) -{ - /* Set Power State to OFF */ - (void)SDMMC_PowerState_OFF(hsd->Instance); -} - -/** - * @brief Send Status info command. - * @param hsd: pointer to SD handle - * @param pSDstatus: Pointer to the buffer that will contain the SD card status - * SD Status register) - * @retval error state - */ -static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t tickstart = HAL_GetTick(); - uint32_t count; - uint32_t *pData = pSDstatus; - - /* Check SD response */ - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) - { - return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; - } - - /* Set block size for card if it is not equal to current block size for card */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->ErrorCode |= HAL_SD_ERROR_NONE; - return errorstate; - } - - /* Send CMD55 */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->ErrorCode |= HAL_SD_ERROR_NONE; - return errorstate; - } - - /* Configure the SD DPSM (Data Path State Machine) */ - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 64U; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hsd->Instance, &config); - - /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ - errorstate = SDMMC_CmdStatusRegister(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - hsd->ErrorCode |= HAL_SD_ERROR_NONE; - return errorstate; - } - - /* Get status data */ - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) - { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) - { - for(count = 0U; count < 8U; count++) - { - *pData = SDMMC_ReadFIFO(hsd->Instance); - pData++; - } - } - - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - return HAL_SD_ERROR_TIMEOUT; - } - } - - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - return HAL_SD_ERROR_DATA_TIMEOUT; - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - return HAL_SD_ERROR_DATA_CRC_FAIL; - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - return HAL_SD_ERROR_RX_OVERRUN; - } - else - { - /* Nothing to do */ - } - - while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) - { - *pData = SDMMC_ReadFIFO(hsd->Instance); - pData++; - - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - return HAL_SD_ERROR_TIMEOUT; - } - } - - /* Clear all the static status flags*/ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - return HAL_SD_ERROR_NONE; -} - -/** - * @brief Returns the current card's status. - * @param hsd: Pointer to SD handle - * @param pCardStatus: pointer to the buffer that will contain the SD card - * status (Card Status register) - * @retval error state - */ -static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) -{ - uint32_t errorstate; - - if(pCardStatus == NULL) - { - return HAL_SD_ERROR_PARAM; - } - - /* Send Status command */ - errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Get SD card status */ - *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); - - return HAL_SD_ERROR_NONE; -} - -/** - * @brief Enables the SDMMC wide bus mode. - * @param hsd: pointer to SD handle - * @retval error state - */ -static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) -{ - uint32_t scr[2U] = {0U, 0U}; - uint32_t errorstate; - - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) - { - return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; - } - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* If requested card supports wide bus operation */ - if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) - { - /* Send CMD55 APP_CMD with argument as card's RCA.*/ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - return HAL_SD_ERROR_NONE; - } - else - { - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; - } -} - -/** - * @brief Disables the SDMMC wide bus mode. - * @param hsd: Pointer to SD handle - * @retval error state - */ -static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) -{ - uint32_t scr[2U] = {0U, 0U}; - uint32_t errorstate; - - if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) - { - return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; - } - - /* Get SCR Register */ - errorstate = SD_FindSCR(hsd, scr); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* If requested card supports 1 bit mode operation */ - if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) - { - /* Send CMD55 APP_CMD with argument as card's RCA */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ - errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - return HAL_SD_ERROR_NONE; - } - else - { - return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; - } -} - - -/** - * @brief Finds the SD card SCR register value. - * @param hsd: Pointer to SD handle - * @param pSCR: pointer to the buffer that will contain the SCR value - * @retval error state - */ -static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) -{ - SDMMC_DataInitTypeDef config; - uint32_t errorstate; - uint32_t tickstart = HAL_GetTick(); - uint32_t index = 0U; - uint32_t tempscr[2U] = {0U, 0U}; - uint32_t *scr = pSCR; - - /* Set Block Size To 8 Bytes */ - errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - /* Send CMD55 APP_CMD with argument as card's RCA */ - errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - config.DataTimeOut = SDMMC_DATATIMEOUT; - config.DataLength = 8U; - config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; - config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; - config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; - config.DPSM = SDMMC_DPSM_ENABLE; - (void)SDMMC_ConfigData(hsd->Instance, &config); - - /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - errorstate = SDMMC_CmdSendSCR(hsd->Instance); - if(errorstate != HAL_SD_ERROR_NONE) - { - return errorstate; - } - - while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT)) - { - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) - { - *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance); - index++; - } - else if(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) - { - break; - } - - if((HAL_GetTick() - tickstart) >= SDMMC_DATATIMEOUT) - { - return HAL_SD_ERROR_TIMEOUT; - } - } - - if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) - { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); - - return HAL_SD_ERROR_DATA_TIMEOUT; - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) - { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); - - return HAL_SD_ERROR_DATA_CRC_FAIL; - } - else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) - { - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); - - return HAL_SD_ERROR_RX_OVERRUN; - } - else - { - /* No error flag set */ - /* Clear all the static flags */ - __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); - - *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ - ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); - scr++; - *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ - ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); - - } - - return HAL_SD_ERROR_NONE; -} - -/** - * @brief Wrap up reading in non-blocking mode. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains - * the configuration information. - * @retval None - */ -static void SD_Read_IT(SD_HandleTypeDef *hsd) -{ - uint32_t count, data, dataremaining; - uint8_t* tmp; - - tmp = hsd->pRxBuffPtr; - dataremaining = hsd->RxXferSize; - - if (dataremaining > 0U) - { - /* Read data from SDMMC Rx FIFO */ - for(count = 0U; count < 8U; count++) - { - data = SDMMC_ReadFIFO(hsd->Instance); - *tmp = (uint8_t)(data & 0xFFU); - tmp++; - dataremaining--; - *tmp = (uint8_t)((data >> 8U) & 0xFFU); - tmp++; - dataremaining--; - *tmp = (uint8_t)((data >> 16U) & 0xFFU); - tmp++; - dataremaining--; - *tmp = (uint8_t)((data >> 24U) & 0xFFU); - tmp++; - dataremaining--; - } - - hsd->pRxBuffPtr = tmp; - hsd->RxXferSize = dataremaining; - } -} - -/** - * @brief Wrap up writing in non-blocking mode. - * @param hsd: pointer to a SD_HandleTypeDef structure that contains - * the configuration information. - * @retval None - */ -static void SD_Write_IT(SD_HandleTypeDef *hsd) -{ - uint32_t count, data, dataremaining; - uint8_t* tmp; - - tmp = hsd->pTxBuffPtr; - dataremaining = hsd->TxXferSize; - - if (dataremaining > 0U) - { - /* Write data to SDMMC Tx FIFO */ - for(count = 0U; count < 8U; count++) - { - data = (uint32_t)(*tmp); - tmp++; - dataremaining--; - data |= ((uint32_t)(*tmp) << 8U); - tmp++; - dataremaining--; - data |= ((uint32_t)(*tmp) << 16U); - tmp++; - dataremaining--; - data |= ((uint32_t)(*tmp) << 24U); - tmp++; - dataremaining--; - (void)SDMMC_WriteFIFO(hsd->Instance, &data); - } - - hsd->pTxBuffPtr = tmp; - hsd->TxXferSize = dataremaining; - } -} - -/** - * @} - */ - -#endif /* HAL_SD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* SDMMC1 */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_sd.c + * @author MCD Application Team + * @brief SD card HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Secure Digital (SD) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + This driver implements a high level communication layer for read and write from/to + this memory. The needed STM32 hardware resources (SDMMC and GPIO) are performed by + the user in HAL_SD_MspInit() function (MSP layer). + Basically, the MSP layer configuration should be the same as we provide in the + examples. + You can easily tailor this configuration according to hardware resources. + + [..] + This driver is a generic layered driver for SDMMC memories which uses the HAL + SDMMC driver functions to interface with SD and uSD cards devices. + It is used as follows: + + (#)Initialize the SDMMC low level resources by implementing the HAL_SD_MspInit() API: + (##) Enable the SDMMC interface clock using __HAL_RCC_SDMMC_CLK_ENABLE(); + (##) SDMMC pins configuration for SD card + (+++) Enable the clock for the SDMMC GPIOs using the functions __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these SDMMC pins as alternate function pull-up using HAL_GPIO_Init() + and according to your pin assignment; + (##) DMA configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA() + and HAL_SD_WriteBlocks_DMA() APIs). + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE(); + (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. + (##) NVIC configuration if you need to use interrupt process when using DMA transfer. + (+++) Configure the SDMMC and DMA interrupt priorities using functions + HAL_NVIC_SetPriority(); DMA priority is superior to SDMMC's priority + (+++) Enable the NVIC DMA and SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() + (##) NVIC configuration if you need to use interrupt process (HAL_SD_ReadBlocks_IT() + and HAL_SD_WriteBlocks_IT() APIs). + (+++) Configure the SDMMC interrupt priorities using function HAL_NVIC_SetPriority(); + (+++) Enable the NVIC SDMMC IRQs using function HAL_NVIC_EnableIRQ() + (+++) SDMMC interrupts are managed using the macros __HAL_SD_ENABLE_IT() + and __HAL_SD_DISABLE_IT() inside the communication process. + (+++) SDMMC interrupts pending bits are managed using the macros __HAL_SD_GET_IT() + and __HAL_SD_CLEAR_IT() + (#) At this stage, you can perform SD read/write/erase operations after SD card initialization + + + *** SD Card Initialization and configuration *** + ================================================ + [..] + To initialize the SD Card, use the HAL_SD_Init() function. It Initializes + SDMMC Peripheral(STM32 side) and the SD Card, and put it into StandBy State (Ready for data transfer). + This function provide the following operations: + + (#) Apply the SD Card initialization process at 400KHz and check the SD Card + type (Standard Capacity or High Capacity). You can change or adapt this + frequency by adjusting the "ClockDiv" field. + The SD Card frequency (SDMMC_CK) is computed as follows: + + SDMMC_CK = SDMMCCLK / (ClockDiv + 2) + + In initialization mode and according to the SD Card standard, + make sure that the SDMMC_CK frequency doesn't exceed 400KHz. + + This phase of initialization is done through SDMMC_Init() and + SDMMC_PowerState_ON() SDMMC low level APIs. + + (#) Initialize the SD card. The API used is HAL_SD_InitCard(). + This phase allows the card initialization and identification + and check the SD Card type (Standard Capacity or High Capacity) + The initialization flow is compatible with SD standard. + + This API (HAL_SD_InitCard()) could be used also to reinitialize the card in case + of plug-off plug-in. + + (#) Configure the SD Card Data transfer frequency. You can change or adapt this + frequency by adjusting the "ClockDiv" field. + In transfer mode and according to the SD Card standard, make sure that the + SDMMC_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch. + To be able to use a frequency higher than 24MHz, you should use the SDMMC + peripheral in bypass mode. Refer to the corresponding reference manual + for more details. + + (#) Select the corresponding SD Card according to the address read with the step 2. + + (#) Configure the SD Card in wide bus mode: 4-bits data. + + *** SD Card Read operation *** + ============================== + [..] + (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + + (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Rx interrupt event. + + (+) You can read from SD card in Interrupt mode by using function HAL_SD_ReadBlocks_IT(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Rx interrupt event. + + *** SD Card Write operation *** + =============================== + [..] + (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + + (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the DMA transfer process through the SD Tx interrupt event. + + (+) You can write to SD card in Interrupt mode by using function HAL_SD_WriteBlocks_IT(). + This function support only 512-bytes block length (the block size should be + chosen as 512 bytes). + You can choose either one block read operation or multiple block read operation + by adjusting the "NumberOfBlocks" parameter. + After this, you have to ensure that the transfer is done correctly. The check is done + through HAL_SD_GetCardState() function for SD card state. + You could also check the IT transfer process through the SD Tx interrupt event. + + *** SD card status *** + ====================== + [..] + (+) The SD Status contains status bits that are related to the SD Memory + Card proprietary features. To get SD card status use the HAL_SD_GetCardStatus(). + + *** SD card information *** + =========================== + [..] + (+) To get SD card information, you can use the function HAL_SD_GetCardInfo(). + It returns useful information about the SD card such as block size, card type, + block number ... + + *** SD card CSD register *** + ============================ + (+) The HAL_SD_GetCardCSD() API allows to get the parameters of the CSD register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD card CID register *** + ============================ + (+) The HAL_SD_GetCardCID() API allows to get the parameters of the CID register. + Some of the CSD parameters are useful for card initialization and identification. + + *** SD HAL driver macros list *** + ================================== + [..] + Below the list of most used macros in SD HAL driver. + + (+) __HAL_SD_ENABLE : Enable the SD device + (+) __HAL_SD_DISABLE : Disable the SD device + (+) __HAL_SD_DMA_ENABLE: Enable the SDMMC DMA transfer + (+) __HAL_SD_DMA_DISABLE: Disable the SDMMC DMA transfer + (+) __HAL_SD_ENABLE_IT: Enable the SD device interrupt + (+) __HAL_SD_DISABLE_IT: Disable the SD device interrupt + (+) __HAL_SD_GET_FLAG:Check whether the specified SD flag is set or not + (+) __HAL_SD_CLEAR_FLAG: Clear the SD's pending flags + + (@) You can refer to the SD HAL driver header file for more useful macros + + *** Callback registration *** + ============================================= + [..] + The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + Use Functions HAL_SD_RegisterCallback() to register a user callback, + it allows to register following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function HAL_SD_UnRegisterCallback() to reset a callback to the default + weak (surcharged) function. It allows to reset following callbacks: + (+) TxCpltCallback : callback when a transmission transfer is completed. + (+) RxCpltCallback : callback when a reception transfer is completed. + (+) ErrorCallback : callback when error occurs. + (+) AbortCpltCallback : callback when abort is completed. + (+) MspInitCallback : SD MspInit. + (+) MspDeInitCallback : SD MspDeInit. + This function) takes as parameters the HAL peripheral handle and the Callback ID. + + By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET + all callbacks are reset to the corresponding legacy weak (surcharged) functions. + Exception done for MspInit and MspDeInit callbacks that are respectively + reset to the legacy weak (surcharged) functions in the HAL_SD_Init + and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in READY state only. + Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered + in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used + during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_SD_RegisterCallback before calling HAL_SD_DeInit + or HAL_SD_Init function. + + When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +#if defined(SDMMC1) + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @addtogroup SD + * @{ + */ + +#ifdef HAL_SD_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup SD_Private_Defines + * @{ + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +/** @defgroup SD_Private_Functions SD Private Functions + * @{ + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd); +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd); +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus); +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus); +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd); +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd); +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR); +static void SD_PowerOFF(SD_HandleTypeDef *hsd); +static void SD_Write_IT(SD_HandleTypeDef *hsd); +static void SD_Read_IT(SD_HandleTypeDef *hsd); +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SD_DMAError(DMA_HandleTypeDef *hdma); +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma); +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SD_Exported_Functions + * @{ + */ + +/** @addtogroup SD_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to initialize/de-initialize the SD + card device to be ready for use. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SD according to the specified parameters in the + SD_HandleTypeDef and create the associated handle. + * @param hsd: Pointer to the SD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) +{ + /* Check the SD handle allocation */ + if(hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); + assert_param(IS_SDMMC_CLOCK_EDGE(hsd->Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_BYPASS(hsd->Init.ClockBypass)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(hsd->Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(hsd->Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(hsd->Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(hsd->Init.ClockDiv)); + + if(hsd->State == HAL_SD_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hsd->Lock = HAL_UNLOCKED; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + /* Reset Callback pointers in HAL_SD_STATE_RESET only */ + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + hsd->ErrorCallback = HAL_SD_ErrorCallback; + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + + if(hsd->MspInitCallback == NULL) + { + hsd->MspInitCallback = HAL_SD_MspInit; + } + + /* Init the low level hardware */ + hsd->MspInitCallback(hsd); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_SD_MspInit(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize the Card parameters */ + if (HAL_SD_InitCard(hsd) != HAL_OK) + { + return HAL_ERROR; + } + + /* Initialize the error code */ + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + + /* Initialize the SD state */ + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Initializes the SD Card. + * @param hsd: Pointer to SD handle + * @note This function initializes the SD card. It could be used when a card + re-initialization is needed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate; + SD_InitTypeDef Init; + + /* Default SDMMC peripheral configuration for SD card initialization */ + Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING; + Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE; + Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE; + Init.BusWide = SDMMC_BUS_WIDE_1B; + Init.HardwareFlowControl = SDMMC_HARDWARE_FLOW_CONTROL_DISABLE; + Init.ClockDiv = SDMMC_INIT_CLK_DIV; + + /* Initialize SDMMC peripheral interface with default configuration */ + SDMMC_Init(hsd->Instance, Init); + + /* Disable SDMMC Clock */ + __HAL_SD_DISABLE(hsd); + + /* Set Power State to ON */ + (void)SDMMC_PowerState_ON(hsd->Instance); + + /* Enable SDMMC Clock */ + __HAL_SD_ENABLE(hsd); + + /* Required power up waiting time before starting the SD initialization sequence */ + HAL_Delay(2); + + /* Identify card operating voltage */ + errorstate = SD_PowerON(hsd); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Card initialization */ + errorstate = SD_InitCard(hsd); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->State = HAL_SD_STATE_READY; + hsd->ErrorCode |= errorstate; + return HAL_ERROR; + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief De-Initializes the SD card. + * @param hsd: Pointer to SD handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd) +{ + /* Check the SD handle allocation */ + if(hsd == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(hsd->Instance)); + + hsd->State = HAL_SD_STATE_BUSY; + + /* Set SD power state to off */ + SD_PowerOFF(hsd); + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + if(hsd->MspDeInitCallback == NULL) + { + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + } + + /* DeInit the low level hardware */ + hsd->MspDeInitCallback(hsd); +#else + /* De-Initialize the MSP layer */ + HAL_SD_MspDeInit(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_RESET; + + return HAL_OK; +} + + +/** + * @brief Initializes the SD MSP. + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_MspInit could be implemented in the user file + */ +} + +/** + * @brief De-Initialize SD MSP. + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup SD_Exported_Functions_Group2 + * @brief Data transfer functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the data + transfer from/to SD card. + +@endverbatim + * @{ + */ + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of SD blocks to read + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Read block(s) in polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_READ_MULTIPLE_BLOCK; + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = SD_CONTEXT_READ_SINGLE_BLOCK; + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + dataremaining = config.DataLength; + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) && (dataremaining > 0U)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock read */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + } + } + + /* Get error state */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Empty FIFO if there is still any data */ + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) && (dataremaining > 0U)) + { + data = SDMMC_ReadFIFO(hsd->Instance); + *tempbuff = (uint8_t)(data & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 8U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 16U) & 0xFFU); + tempbuff++; + dataremaining--; + *tempbuff = (uint8_t)((data >> 24U) & 0xFFU); + tempbuff++; + dataremaining--; + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TIMEOUT; + hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Allows to write block(s) to a specified address in a card. The Data + * transfer is managed by polling mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param pData: pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of SD blocks to write + * @param Timeout: Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count, data, dataremaining; + uint32_t add = BlockAdd; + uint8_t *tempbuff = pData; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = NumberOfBlocks * BLOCKSIZE; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = SD_CONTEXT_WRITE_MULTIPLE_BLOCK; + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = SD_CONTEXT_WRITE_SINGLE_BLOCK; + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Write block(s) in polling mode */ + dataremaining = config.DataLength; + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DATAEND)) + { + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) && (dataremaining > 0U)) + { + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tempbuff); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 8U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 16U); + tempbuff++; + dataremaining--; + data |= ((uint32_t)(*tempbuff) << 24U); + tempbuff++; + dataremaining--; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_TIMEOUT; + } + } + + /* Send stop transmission command in case of multiblock write */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) && (NumberOfBlocks > 1U)) + { + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send stop transmission command */ + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + } + } + + /* Get error state */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR)) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + hsd->ErrorCode |= HAL_SD_ERROR_BUSY; + return HAL_ERROR; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pRxBuffPtr = pData; + hsd->RxXferSize = BLOCKSIZE * NumberOfBlocks; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND | SDMMC_FLAG_RXFIFOHF)); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Read Blocks in IT mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_IT); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed in interrupt mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the IT transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + hsd->pTxBuffPtr = pData; + hsd->TxXferSize = BLOCKSIZE * NumberOfBlocks; + + /* Enable transfer interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR | SDMMC_IT_DATAEND | SDMMC_FLAG_TXFIFOHE)); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK| SD_CONTEXT_IT); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_IT); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Reads block(s) from a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Rx + * interrupt event. + * @param hsd: Pointer SD handle + * @param pData: Pointer to the buffer that will contain the received data + * @param BlockAdd: Block Address from where data is to be read + * @param NumberOfBlocks: Number of blocks to read. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + + /* Set the DMA transfer complete callback */ + hsd->hdmarx->XferCpltCallback = SD_DMAReceiveCplt; + + /* Set the DMA error callback */ + hsd->hdmarx->XferErrorCallback = SD_DMAError; + + /* Set the DMA Abort callback */ + hsd->hdmarx->XferAbortCallback = NULL; + + /* Force DMA Direction */ + hsd->hdmarx->Init.Direction = DMA_PERIPH_TO_MEMORY; + MODIFY_REG(hsd->hdmarx->Instance->CR, DMA_SxCR_DIR, hsd->hdmarx->Init.Direction); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pData, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) + { + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_RXOVERR | SDMMC_IT_DATAEND)); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + else + { + /* Enable SD DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Read Blocks in DMA mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Multi Block command */ + errorstate = SDMMC_CmdReadMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_READ_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Read Single Block command */ + errorstate = SDMMC_CmdReadSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Writes block(s) to a specified address in a card. The Data transfer + * is managed by DMA mode. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @note You could also check the DMA transfer process through the SD Tx + * interrupt event. + * @param hsd: Pointer to SD handle + * @param pData: Pointer to the buffer that will contain the data to transmit + * @param BlockAdd: Block Address where data will be written + * @param NumberOfBlocks: Number of blocks to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t add = BlockAdd; + + if(NULL == pData) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if((add + NumberOfBlocks) > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Initialize data control register */ + hsd->Instance->DCTRL = 0U; + + /* Enable SD Error interrupts */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + + /* Set the DMA transfer complete callback */ + hsd->hdmatx->XferCpltCallback = SD_DMATransmitCplt; + + /* Set the DMA error callback */ + hsd->hdmatx->XferErrorCallback = SD_DMAError; + + /* Set the DMA Abort callback */ + hsd->hdmatx->XferAbortCallback = NULL; + + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + add *= 512U; + } + + /* Write Blocks in Polling mode */ + if(NumberOfBlocks > 1U) + { + hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Multi Block command */ + errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add); + } + else + { + hsd->Context = (SD_CONTEXT_WRITE_SINGLE_BLOCK | SD_CONTEXT_DMA); + + /* Write Single Block command */ + errorstate = SDMMC_CmdWriteSingleBlock(hsd->Instance, add); + } + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + + /* Enable SDMMC DMA transfer */ + __HAL_SD_DMA_ENABLE(hsd); + + /* Force DMA Direction */ + hsd->hdmatx->Init.Direction = DMA_MEMORY_TO_PERIPH; + MODIFY_REG(hsd->hdmatx->Instance->CR, DMA_SxCR_DIR, hsd->hdmatx->Init.Direction); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK) + { + __HAL_SD_DISABLE_IT(hsd, (SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT | SDMMC_IT_TXUNDERR)); + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + return HAL_ERROR; + } + else + { + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = BLOCKSIZE * NumberOfBlocks; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_512B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_CARD; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + return HAL_OK; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Erases the specified memory area of the given SD card. + * @note This API should be followed by a check on the card state through + * HAL_SD_GetCardState(). + * @param hsd: Pointer to SD handle + * @param BlockStartAdd: Start Block address + * @param BlockEndAdd: End Block address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd) +{ + uint32_t errorstate; + uint32_t start_add = BlockStartAdd; + uint32_t end_add = BlockEndAdd; + + if(hsd->State == HAL_SD_STATE_READY) + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + + if(end_add < start_add) + { + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + return HAL_ERROR; + } + + if(end_add > (hsd->SdCard.LogBlockNbr)) + { + hsd->ErrorCode |= HAL_SD_ERROR_ADDR_OUT_OF_RANGE; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_BUSY; + + /* Check if the card command class supports erase command */ + if(((hsd->SdCard.Class) & SDMMC_CCCC_ERASE) == 0U) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Get start and end block for high capacity cards */ + if(hsd->SdCard.CardType != CARD_SDHC_SDXC) + { + start_add *= 512U; + end_add *= 512U; + } + + /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */ + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD32 SD_ERASE_GRP_START with argument as addr */ + errorstate = SDMMC_CmdSDEraseStartAdd(hsd->Instance, start_add); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + /* Send CMD33 SD_ERASE_GRP_END with argument as addr */ + errorstate = SDMMC_CmdSDEraseEndAdd(hsd->Instance, end_add); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + } + + /* Send CMD38 ERASE */ + errorstate = SDMMC_CmdErase(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + hsd->State = HAL_SD_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief This function handles SD card interrupt request. + * @param hsd: Pointer to SD handle + * @retval None + */ +void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd) +{ + uint32_t errorstate; + uint32_t context = hsd->Context; + + /* Check for SDMMC interrupt flags */ + if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + { + SD_Read_IT(hsd); + } + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DATAEND) != RESET) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DATAEND); + + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR | SDMMC_IT_RXOVERR | SDMMC_IT_TXFIFOHE |\ + SDMMC_IT_RXFIFOHF); + + hsd->Instance->DCTRL &= ~(SDMMC_DCTRL_DTEN); + + if((context & SD_CONTEXT_IT) != 0U) + { + if(((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->RxCpltCallback(hsd); +#else + HAL_SD_RxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else + HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else if((context & SD_CONTEXT_DMA) != 0U) + { + if((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) == 0U) && ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) == 0U)) + { + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the SD DCTRL register */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + hsd->State = HAL_SD_STATE_READY; + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->TxCpltCallback(hsd); +#else + HAL_SD_TxCpltCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } + + else if((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXFIFOHE) != RESET) && ((context & SD_CONTEXT_IT) != 0U)) + { + SD_Write_IT(hsd); + } + + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_RXOVERR | SDMMC_FLAG_TXUNDERR) != RESET) + { + /* Set Error code */ + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_CRC_FAIL; + } + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_DATA_TIMEOUT; + } + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_RX_OVERRUN; + } + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_TXUNDERR) != RESET) + { + hsd->ErrorCode |= HAL_SD_ERROR_TX_UNDERRUN; + } + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + /* Disable all interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + + if((context & SD_CONTEXT_IT) != 0U) + { + /* Set the SD state to ready to be able to start again the process */ + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + else if((context & SD_CONTEXT_DMA) != 0U) + { + /* Abort the SD DMA channel */ + if(((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + /* Set the DMA Tx abort callback */ + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + { + SD_DMATxAbort(hsd->hdmatx); + } + } + else if(((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + /* Set the DMA Rx abort callback */ + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + /* Abort DMA in IT mode */ + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + { + SD_DMARxAbort(hsd->hdmarx); + } + } + else + { + hsd->ErrorCode = HAL_SD_ERROR_NONE; + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + else + { + /* Nothing to do */ + } + } + else + { + /* Nothing to do */ + } +} + +/** + * @brief return the SD state + * @param hsd: Pointer to sd handle + * @retval HAL state + */ +HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd) +{ + return hsd->State; +} + +/** +* @brief Return the SD error code +* @param hsd : Pointer to a SD_HandleTypeDef structure that contains + * the configuration information. +* @retval SD Error Code +*/ +uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd) +{ + return hsd->ErrorCode; +} + +/** + * @brief Tx Transfer completed callbacks + * @param hsd: Pointer to SD handle + * @retval None + */ +__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_TxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_RxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief SD error callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_ErrorCallback can be implemented in the user file + */ +} + +/** + * @brief SD Abort callbacks + * @param hsd: Pointer SD handle + * @retval None + */ +__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hsd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SD_AbortCallback can be implemented in the user file + */ +} + +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SD Callback + * To be used instead of the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @param pCallback : pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_SD_RegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = pCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = pCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = pCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = pCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = pCallback; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = pCallback; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} + +/** + * @brief Unregister a User SD Callback + * SD Callback is redirected to the weak (surcharged) predefined callback + * @param hsd : SD handle + * @param CallbackID : ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_SD_TX_CPLT_CB_ID SD Tx Complete Callback ID + * @arg @ref HAL_SD_RX_CPLT_CB_ID SD Rx Complete Callback ID + * @arg @ref HAL_SD_ERROR_CB_ID SD Error Callback ID + * @arg @ref HAL_SD_ABORT_CB_ID SD Abort Callback ID + * @arg @ref HAL_SD_MSP_INIT_CB_ID SD MspInit Callback ID + * @arg @ref HAL_SD_MSP_DEINIT_CB_ID SD MspDeInit Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hsd); + + if(hsd->State == HAL_SD_STATE_READY) + { + switch (CallbackID) + { + case HAL_SD_TX_CPLT_CB_ID : + hsd->TxCpltCallback = HAL_SD_TxCpltCallback; + break; + case HAL_SD_RX_CPLT_CB_ID : + hsd->RxCpltCallback = HAL_SD_RxCpltCallback; + break; + case HAL_SD_ERROR_CB_ID : + hsd->ErrorCallback = HAL_SD_ErrorCallback; + break; + case HAL_SD_ABORT_CB_ID : + hsd->AbortCpltCallback = HAL_SD_AbortCallback; + break; + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else if (hsd->State == HAL_SD_STATE_RESET) + { + switch (CallbackID) + { + case HAL_SD_MSP_INIT_CB_ID : + hsd->MspInitCallback = HAL_SD_MspInit; + break; + case HAL_SD_MSP_DEINIT_CB_ID : + hsd->MspDeInitCallback = HAL_SD_MspDeInit; + break; + default : + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hsd->ErrorCode |= HAL_SD_ERROR_INVALID_CALLBACK; + /* update return status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hsd); + return status; +} +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup SD_Exported_Functions_Group3 + * @brief management functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the SD card + operations and get the related information + +@endverbatim + * @{ + */ + +/** + * @brief Returns information the information of the card which are stored on + * the CID register. + * @param hsd: Pointer to SD handle + * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that + * contains all CID register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +{ + pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); + + pCID->OEM_AppliID = (uint16_t)((hsd->CID[0] & 0x00FFFF00U) >> 8U); + + pCID->ProdName1 = (((hsd->CID[0] & 0x000000FFU) << 24U) | ((hsd->CID[1] & 0xFFFFFF00U) >> 8U)); + + pCID->ProdName2 = (uint8_t)(hsd->CID[1] & 0x000000FFU); + + pCID->ProdRev = (uint8_t)((hsd->CID[2] & 0xFF000000U) >> 24U); + + pCID->ProdSN = (((hsd->CID[2] & 0x00FFFFFFU) << 8U) | ((hsd->CID[3] & 0xFF000000U) >> 24U)); + + pCID->Reserved1 = (uint8_t)((hsd->CID[3] & 0x00F00000U) >> 20U); + + pCID->ManufactDate = (uint16_t)((hsd->CID[3] & 0x000FFF00U) >> 8U); + + pCID->CID_CRC = (uint8_t)((hsd->CID[3] & 0x000000FEU) >> 1U); + + pCID->Reserved2 = 1U; + + return HAL_OK; +} + +/** + * @brief Returns information the information of the card which are stored on + * the CSD register. + * @param hsd: Pointer to SD handle + * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that + * contains all CSD register parameters + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD) +{ + pCSD->CSDStruct = (uint8_t)((hsd->CSD[0] & 0xC0000000U) >> 30U); + + pCSD->SysSpecVersion = (uint8_t)((hsd->CSD[0] & 0x3C000000U) >> 26U); + + pCSD->Reserved1 = (uint8_t)((hsd->CSD[0] & 0x03000000U) >> 24U); + + pCSD->TAAC = (uint8_t)((hsd->CSD[0] & 0x00FF0000U) >> 16U); + + pCSD->NSAC = (uint8_t)((hsd->CSD[0] & 0x0000FF00U) >> 8U); + + pCSD->MaxBusClkFrec = (uint8_t)(hsd->CSD[0] & 0x000000FFU); + + pCSD->CardComdClasses = (uint16_t)((hsd->CSD[1] & 0xFFF00000U) >> 20U); + + pCSD->RdBlockLen = (uint8_t)((hsd->CSD[1] & 0x000F0000U) >> 16U); + + pCSD->PartBlockRead = (uint8_t)((hsd->CSD[1] & 0x00008000U) >> 15U); + + pCSD->WrBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00004000U) >> 14U); + + pCSD->RdBlockMisalign = (uint8_t)((hsd->CSD[1] & 0x00002000U) >> 13U); + + pCSD->DSRImpl = (uint8_t)((hsd->CSD[1] & 0x00001000U) >> 12U); + + pCSD->Reserved2 = 0U; /*!< Reserved */ + + if(hsd->SdCard.CardType == CARD_SDSC) + { + pCSD->DeviceSize = (((hsd->CSD[1] & 0x000003FFU) << 2U) | ((hsd->CSD[2] & 0xC0000000U) >> 30U)); + + pCSD->MaxRdCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x38000000U) >> 27U); + + pCSD->MaxRdCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x07000000U) >> 24U); + + pCSD->MaxWrCurrentVDDMin = (uint8_t)((hsd->CSD[2] & 0x00E00000U) >> 21U); + + pCSD->MaxWrCurrentVDDMax = (uint8_t)((hsd->CSD[2] & 0x001C0000U) >> 18U); + + pCSD->DeviceSizeMul = (uint8_t)((hsd->CSD[2] & 0x00038000U) >> 15U); + + hsd->SdCard.BlockNbr = (pCSD->DeviceSize + 1U) ; + hsd->SdCard.BlockNbr *= (1UL << ((pCSD->DeviceSizeMul & 0x07U) + 2U)); + hsd->SdCard.BlockSize = (1UL << (pCSD->RdBlockLen & 0x0FU)); + + hsd->SdCard.LogBlockNbr = (hsd->SdCard.BlockNbr) * ((hsd->SdCard.BlockSize) / 512U); + hsd->SdCard.LogBlockSize = 512U; + } + else if(hsd->SdCard.CardType == CARD_SDHC_SDXC) + { + /* Byte 7 */ + pCSD->DeviceSize = (((hsd->CSD[1] & 0x0000003FU) << 16U) | ((hsd->CSD[2] & 0xFFFF0000U) >> 16U)); + + hsd->SdCard.BlockNbr = ((pCSD->DeviceSize + 1U) * 1024U); + hsd->SdCard.LogBlockNbr = hsd->SdCard.BlockNbr; + hsd->SdCard.BlockSize = 512U; + hsd->SdCard.LogBlockSize = hsd->SdCard.BlockSize; + } + else + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + hsd->State = HAL_SD_STATE_READY; + return HAL_ERROR; + } + + pCSD->EraseGrSize = (uint8_t)((hsd->CSD[2] & 0x00004000U) >> 14U); + + pCSD->EraseGrMul = (uint8_t)((hsd->CSD[2] & 0x00003F80U) >> 7U); + + pCSD->WrProtectGrSize = (uint8_t)(hsd->CSD[2] & 0x0000007FU); + + pCSD->WrProtectGrEnable = (uint8_t)((hsd->CSD[3] & 0x80000000U) >> 31U); + + pCSD->ManDeflECC = (uint8_t)((hsd->CSD[3] & 0x60000000U) >> 29U); + + pCSD->WrSpeedFact = (uint8_t)((hsd->CSD[3] & 0x1C000000U) >> 26U); + + pCSD->MaxWrBlockLen= (uint8_t)((hsd->CSD[3] & 0x03C00000U) >> 22U); + + pCSD->WriteBlockPaPartial = (uint8_t)((hsd->CSD[3] & 0x00200000U) >> 21U); + + pCSD->Reserved3 = 0; + + pCSD->ContentProtectAppli = (uint8_t)((hsd->CSD[3] & 0x00010000U) >> 16U); + + pCSD->FileFormatGroup = (uint8_t)((hsd->CSD[3] & 0x00008000U) >> 15U); + + pCSD->CopyFlag = (uint8_t)((hsd->CSD[3] & 0x00004000U) >> 14U); + + pCSD->PermWrProtect = (uint8_t)((hsd->CSD[3] & 0x00002000U) >> 13U); + + pCSD->TempWrProtect = (uint8_t)((hsd->CSD[3] & 0x00001000U) >> 12U); + + pCSD->FileFormat = (uint8_t)((hsd->CSD[3] & 0x00000C00U) >> 10U); + + pCSD->ECC= (uint8_t)((hsd->CSD[3] & 0x00000300U) >> 8U); + + pCSD->CSD_CRC = (uint8_t)((hsd->CSD[3] & 0x000000FEU) >> 1U); + + pCSD->Reserved4 = 1; + + return HAL_OK; +} + +/** + * @brief Gets the SD status info. + * @param hsd: Pointer to SD handle + * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that + * will contain the SD card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus) +{ + uint32_t sd_status[16]; + uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; + + errorstate = SD_SendSDStatus(hsd, sd_status); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + else + { + pStatus->DataBusWidth = (uint8_t)((sd_status[0] & 0xC0U) >> 6U); + + pStatus->SecuredMode = (uint8_t)((sd_status[0] & 0x20U) >> 5U); + + pStatus->CardType = (uint16_t)(((sd_status[0] & 0x00FF0000U) >> 8U) | ((sd_status[0] & 0xFF000000U) >> 24U)); + + pStatus->ProtectedAreaSize = (((sd_status[1] & 0xFFU) << 24U) | ((sd_status[1] & 0xFF00U) << 8U) | + ((sd_status[1] & 0xFF0000U) >> 8U) | ((sd_status[1] & 0xFF000000U) >> 24U)); + + pStatus->SpeedClass = (uint8_t)(sd_status[2] & 0xFFU); + + pStatus->PerformanceMove = (uint8_t)((sd_status[2] & 0xFF00U) >> 8U); + + pStatus->AllocationUnitSize = (uint8_t)((sd_status[2] & 0xF00000U) >> 20U); + + pStatus->EraseSize = (uint16_t)(((sd_status[2] & 0xFF000000U) >> 16U) | (sd_status[3] & 0xFFU)); + + pStatus->EraseTimeout = (uint8_t)((sd_status[3] & 0xFC00U) >> 10U); + + pStatus->EraseOffset = (uint8_t)((sd_status[3] & 0x0300U) >> 8U); + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode = errorstate; + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Gets the SD card info. + * @param hsd: Pointer to SD handle + * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that + * will contain the SD card status information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +{ + pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); + pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); + pCardInfo->Class = (uint32_t)(hsd->SdCard.Class); + pCardInfo->RelCardAdd = (uint32_t)(hsd->SdCard.RelCardAdd); + pCardInfo->BlockNbr = (uint32_t)(hsd->SdCard.BlockNbr); + pCardInfo->BlockSize = (uint32_t)(hsd->SdCard.BlockSize); + pCardInfo->LogBlockNbr = (uint32_t)(hsd->SdCard.LogBlockNbr); + pCardInfo->LogBlockSize = (uint32_t)(hsd->SdCard.LogBlockSize); + + return HAL_OK; +} + +/** + * @brief Enables wide bus operation for the requested card if supported by + * card. + * @param hsd: Pointer to SD handle + * @param WideMode: Specifies the SD card wide bus mode + * This parameter can be one of the following values: + * @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer + * @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer + * @arg SDMMC_BUS_WIDE_1B: 1-bit data transfer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode) +{ + SDMMC_InitTypeDef Init; + uint32_t errorstate; + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_SDMMC_BUS_WIDE(WideMode)); + + /* Change State */ + hsd->State = HAL_SD_STATE_BUSY; + + if(hsd->SdCard.CardType != CARD_SECURED) + { + if(WideMode == SDMMC_BUS_WIDE_8B) + { + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + else if(WideMode == SDMMC_BUS_WIDE_4B) + { + errorstate = SD_WideBus_Enable(hsd); + + hsd->ErrorCode |= errorstate; + } + else if(WideMode == SDMMC_BUS_WIDE_1B) + { + errorstate = SD_WideBus_Disable(hsd); + + hsd->ErrorCode |= errorstate; + } + else + { + /* WideMode is not a valid argument*/ + hsd->ErrorCode |= HAL_SD_ERROR_PARAM; + } + } + else + { + /* MMC Card does not support this feature */ + hsd->ErrorCode |= HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->State = HAL_SD_STATE_READY; + status = HAL_ERROR; + } + else + { + /* Configure the SDMMC peripheral */ + Init.ClockEdge = hsd->Init.ClockEdge; + Init.ClockBypass = hsd->Init.ClockBypass; + Init.ClockPowerSave = hsd->Init.ClockPowerSave; + Init.BusWide = WideMode; + Init.HardwareFlowControl = hsd->Init.HardwareFlowControl; + Init.ClockDiv = hsd->Init.ClockDiv; + (void)SDMMC_Init(hsd->Instance, Init); + } + + /* Set Block Size for Card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE); + if(errorstate != HAL_SD_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + hsd->ErrorCode |= errorstate; + status = HAL_ERROR; + } + + /* Change State */ + hsd->State = HAL_SD_STATE_READY; + + return status; +} + +/** + * @brief Gets the current sd card data state. + * @param hsd: pointer to SD handle + * @retval Card state + */ +HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd) +{ + uint32_t cardstate; + uint32_t errorstate; + uint32_t resp1 = 0; + + errorstate = SD_SendStatus(hsd, &resp1); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; + } + + cardstate = ((resp1 >> 9U) & 0x0FU); + + return (HAL_SD_CardStateTypeDef)cardstate; +} + +/** + * @brief Abort the current transfer and disable the SD. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardStateTypeDef CardState; + uint32_t context = hsd->Context; + + /* DIsable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0U) + { + /* Disable the SD DMA request */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Abort the SD DMA Tx channel */ + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + if(HAL_DMA_Abort(hsd->hdmatx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } + } + /* Abort the SD DMA Rx channel */ + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + if(HAL_DMA_Abort(hsd->hdmarx) != HAL_OK) + { + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + } + } + else + { + /* Nothing to do */ + } + } + + hsd->State = HAL_SD_STATE_READY; + + /* Initialize the SD operation */ + hsd->Context = SD_CONTEXT_NONE; + + CardState = HAL_SD_GetCardState(hsd); + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + return HAL_OK; +} + +/** + * @brief Abort the current transfer and disable the SD (IT mode). + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information for SD module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardStateTypeDef CardState; + uint32_t context = hsd->Context; + + /* Disable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + CLEAR_BIT(hsd->Instance->DCTRL, SDMMC_DCTRL_DTEN); + + if ((context & SD_CONTEXT_DMA) != 0U) + { + /* Disable the SD DMA request */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Abort the SD DMA Tx channel */ + if (((context & SD_CONTEXT_WRITE_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_WRITE_MULTIPLE_BLOCK) != 0U)) + { + hsd->hdmatx->XferAbortCallback = SD_DMATxAbort; + if(HAL_DMA_Abort_IT(hsd->hdmatx) != HAL_OK) + { + hsd->hdmatx = NULL; + } + } + /* Abort the SD DMA Rx channel */ + else if (((context & SD_CONTEXT_READ_SINGLE_BLOCK) != 0U) || ((context & SD_CONTEXT_READ_MULTIPLE_BLOCK) != 0U)) + { + hsd->hdmarx->XferAbortCallback = SD_DMARxAbort; + if(HAL_DMA_Abort_IT(hsd->hdmarx) != HAL_OK) + { + hsd->hdmarx = NULL; + } + } + else + { + /* Nothing to do */ + } + } + /* No transfer ongoing on both DMA channels*/ + else + { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode = SDMMC_CmdStopTransfer(hsd->Instance); + } + if(hsd->ErrorCode != HAL_SD_ERROR_NONE) + { + return HAL_ERROR; + } + else + { +#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif /* USE_HAL_SD_REGISTER_CALLBACKS */ + } + } + + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief DMA SD transmit process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + + /* Enable DATAEND Interrupt */ + __HAL_SD_ENABLE_IT(hsd, (SDMMC_IT_DATAEND)); +} + +/** + * @brief DMA SD receive process complete callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + uint32_t errorstate; + + /* Send stop command in multiblock write */ + if(hsd->Context == (SD_CONTEXT_READ_MULTIPLE_BLOCK | SD_CONTEXT_DMA)) + { + errorstate = SDMMC_CmdStopTransfer(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= errorstate; +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } + } + + /* Disable the DMA transfer for transmit request by setting the DMAEN bit + in the SD DCTRL register */ + hsd->Instance->DCTRL &= (uint32_t)~((uint32_t)SDMMC_DCTRL_DMAEN); + + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->RxCpltCallback(hsd); +#else + HAL_SD_RxCpltCallback(hsd); +#endif +} + +/** + * @brief DMA SD communication error callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMAError(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; + uint32_t RxErrorCode, TxErrorCode; + + /* if DMA error is FIFO error ignore it */ + if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) + { + RxErrorCode = hsd->hdmarx->ErrorCode; + TxErrorCode = hsd->hdmatx->ErrorCode; + if((RxErrorCode == HAL_DMA_ERROR_TE) || (TxErrorCode == HAL_DMA_ERROR_TE)) + { + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_FLAGS); + + /* Disable All interrupts */ + __HAL_SD_DISABLE_IT(hsd, SDMMC_IT_DATAEND | SDMMC_IT_DCRCFAIL | SDMMC_IT_DTIMEOUT|\ + SDMMC_IT_TXUNDERR| SDMMC_IT_RXOVERR); + + hsd->ErrorCode |= HAL_SD_ERROR_DMA; + CardState = HAL_SD_GetCardState(hsd); + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + hsd->State= HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + } + +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } +} + +/** + * @brief DMA SD Tx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMATxAbort(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif + } + else + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } +} + +/** + * @brief DMA SD Rx Abort callback + * @param hdma: DMA handle + * @retval None + */ +static void SD_DMARxAbort(DMA_HandleTypeDef *hdma) +{ + SD_HandleTypeDef* hsd = (SD_HandleTypeDef* )(hdma->Parent); + HAL_SD_CardStateTypeDef CardState; + + /* Clear All flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + CardState = HAL_SD_GetCardState(hsd); + hsd->State = HAL_SD_STATE_READY; + hsd->Context = SD_CONTEXT_NONE; + if((CardState == HAL_SD_CARD_RECEIVING) || (CardState == HAL_SD_CARD_SENDING)) + { + hsd->ErrorCode |= SDMMC_CmdStopTransfer(hsd->Instance); + } + + if(hsd->ErrorCode == HAL_SD_ERROR_NONE) + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->AbortCpltCallback(hsd); +#else + HAL_SD_AbortCallback(hsd); +#endif + } + else + { +#if (USE_HAL_SD_REGISTER_CALLBACKS == 1) + hsd->ErrorCallback(hsd); +#else + HAL_SD_ErrorCallback(hsd); +#endif + } +} + +/** + * @brief Initializes the sd card. + * @param hsd: Pointer to SD handle + * @retval SD Card error state + */ +static uint32_t SD_InitCard(SD_HandleTypeDef *hsd) +{ + HAL_SD_CardCSDTypeDef CSD; + uint32_t errorstate; + uint16_t sd_rca = 1U; + + /* Check the power State */ + if(SDMMC_GetPowerState(hsd->Instance) == 0U) + { + /* Power off */ + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } + + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD2 ALL_SEND_CID */ + errorstate = SDMMC_CmdSendCID(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card identification number data */ + hsd->CID[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CID[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CID[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CID[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + } + } + + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* SD Card publishes its RCA. */ + errorstate = SDMMC_CmdSetRelAdd(hsd->Instance, &sd_rca); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + } + if(hsd->SdCard.CardType != CARD_SECURED) + { + /* Get the SD card RCA */ + hsd->SdCard.RelCardAdd = sd_rca; + + /* Send CMD9 SEND_CSD with argument as card's RCA */ + errorstate = SDMMC_CmdSendCSD(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + else + { + /* Get Card Specific Data */ + hsd->CSD[0U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + hsd->CSD[1U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2); + hsd->CSD[2U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP3); + hsd->CSD[3U] = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP4); + } + } + + /* Get the Card Class */ + hsd->SdCard.Class = (SDMMC_GetResponse(hsd->Instance, SDMMC_RESP2) >> 20U); + + /* Get CSD parameters */ + if (HAL_SD_GetCardCSD(hsd, &CSD) != HAL_OK) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hsd->Instance, (uint32_t)(((uint32_t)hsd->SdCard.RelCardAdd) << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Configure SDMMC peripheral interface */ + (void)SDMMC_Init(hsd->Instance, hsd->Init); + + /* All cards are initialized */ + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Enquires cards about their operating voltage and configures clock + * controls and stores SD information that will be needed in future + * in the SD handle. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) +{ + __IO uint32_t count = 0U; + uint32_t response = 0U, validvoltage = 0U; + uint32_t errorstate; + + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ + errorstate = SDMMC_CmdOperCond(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->SdCard.CardVersion = CARD_V1_X; + /* CMD0: GO_IDLE_STATE */ + errorstate = SDMMC_CmdGoIdleState(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + } + else + { + hsd->SdCard.CardVersion = CARD_V2_X; + } + + if( hsd->SdCard.CardVersion == CARD_V2_X) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + } + /* SD CARD */ + /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */ + while((count < SDMMC_MAX_VOLT_TRIAL) && (validvoltage == 0U)) + { + /* SEND CMD55 APP_CMD with RCA as 0 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, 0); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD41 */ + errorstate = SDMMC_CmdAppOperCommand(hsd->Instance, SDMMC_VOLTAGE_WINDOW_SD | SDMMC_HIGH_CAPACITY | SD_SWITCH_1_8V_CAPACITY); + if(errorstate != HAL_SD_ERROR_NONE) + { + return HAL_SD_ERROR_UNSUPPORTED_FEATURE; + } + + /* Get command response */ + response = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + /* Get operating voltage*/ + validvoltage = (((response >> 31U) == 1U) ? 1U : 0U); + + count++; + } + + if(count >= SDMMC_MAX_VOLT_TRIAL) + { + return HAL_SD_ERROR_INVALID_VOLTRANGE; + } + + if((response & SDMMC_HIGH_CAPACITY) == SDMMC_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */ + { + hsd->SdCard.CardType = CARD_SDHC_SDXC; + } + else + { + hsd->SdCard.CardType = CARD_SDSC; + } + + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Turns the SDMMC output signals off. + * @param hsd: Pointer to SD handle + * @retval None + */ +static void SD_PowerOFF(SD_HandleTypeDef *hsd) +{ + /* Set Power State to OFF */ + (void)SDMMC_PowerState_OFF(hsd->Instance); +} + +/** + * @brief Send Status info command. + * @param hsd: pointer to SD handle + * @param pSDstatus: Pointer to the buffer that will contain the SD card status + * SD Status register) + * @retval error state + */ +static uint32_t SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *pData = pSDstatus; + + /* Check SD response */ + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Set block size for card if it is not equal to current block size for card */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 64U); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Send CMD55 */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Configure the SD DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 64U; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_64B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Send ACMD13 (SD_APP_STAUS) with argument as card's RCA */ + errorstate = SDMMC_CmdStatusRegister(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + hsd->ErrorCode |= HAL_SD_ERROR_NONE; + return errorstate; + } + + /* Get status data */ + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_DBCKEND)) + { + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXFIFOHF)) + { + for(count = 0U; count < 8U; count++) + { + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; + } + } + + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + return HAL_SD_ERROR_DATA_TIMEOUT; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + return HAL_SD_ERROR_DATA_CRC_FAIL; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + return HAL_SD_ERROR_RX_OVERRUN; + } + else + { + /* Nothing to do */ + } + + while ((__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL))) + { + *pData = SDMMC_ReadFIFO(hsd->Instance); + pData++; + + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + /* Clear all the static status flags*/ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Returns the current card's status. + * @param hsd: Pointer to SD handle + * @param pCardStatus: pointer to the buffer that will contain the SD card + * status (Card Status register) + * @retval error state + */ +static uint32_t SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus) +{ + uint32_t errorstate; + + if(pCardStatus == NULL) + { + return HAL_SD_ERROR_PARAM; + } + + /* Send Status command */ + errorstate = SDMMC_CmdSendStatus(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Get SD card status */ + *pCardStatus = SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1); + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Enables the SDMMC wide bus mode. + * @param hsd: pointer to SD handle + * @retval error state + */ +static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd) +{ + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate; + + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* If requested card supports wide bus operation */ + if((scr[1U] & SDMMC_WIDE_BUS_SUPPORT) != SDMMC_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA.*/ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 2U); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + return HAL_SD_ERROR_NONE; + } + else + { + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } +} + +/** + * @brief Disables the SDMMC wide bus mode. + * @param hsd: Pointer to SD handle + * @retval error state + */ +static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd) +{ + uint32_t scr[2U] = {0U, 0U}; + uint32_t errorstate; + + if((SDMMC_GetResponse(hsd->Instance, SDMMC_RESP1) & SDMMC_CARD_LOCKED) == SDMMC_CARD_LOCKED) + { + return HAL_SD_ERROR_LOCK_UNLOCK_FAILED; + } + + /* Get SCR Register */ + errorstate = SD_FindSCR(hsd, scr); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* If requested card supports 1 bit mode operation */ + if((scr[1U] & SDMMC_SINGLE_BUS_SUPPORT) != SDMMC_ALLZERO) + { + /* Send CMD55 APP_CMD with argument as card's RCA */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->SdCard.RelCardAdd << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */ + errorstate = SDMMC_CmdBusWidth(hsd->Instance, 0U); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + return HAL_SD_ERROR_NONE; + } + else + { + return HAL_SD_ERROR_REQUEST_NOT_APPLICABLE; + } +} + + +/** + * @brief Finds the SD card SCR register value. + * @param hsd: Pointer to SD handle + * @param pSCR: pointer to the buffer that will contain the SCR value + * @retval error state + */ +static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR) +{ + SDMMC_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t index = 0U; + uint32_t tempscr[2U] = {0U, 0U}; + uint32_t *scr = pSCR; + + /* Set Block Size To 8 Bytes */ + errorstate = SDMMC_CmdBlockLength(hsd->Instance, 8U); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + /* Send CMD55 APP_CMD with argument as card's RCA */ + errorstate = SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)((hsd->SdCard.RelCardAdd) << 16U)); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 8U; + config.DataBlockSize = SDMMC_DATABLOCK_SIZE_8B; + config.TransferDir = SDMMC_TRANSFER_DIR_TO_SDMMC; + config.TransferMode = SDMMC_TRANSFER_MODE_BLOCK; + config.DPSM = SDMMC_DPSM_ENABLE; + (void)SDMMC_ConfigData(hsd->Instance, &config); + + /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ + errorstate = SDMMC_CmdSendSCR(hsd->Instance); + if(errorstate != HAL_SD_ERROR_NONE) + { + return errorstate; + } + + while(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT)) + { + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXDAVL)) + { + *(tempscr + index) = SDMMC_ReadFIFO(hsd->Instance); + index++; + } + else if(!__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXACT)) + { + break; + } + + if((HAL_GetTick() - tickstart) >= SDMMC_SWDATATIMEOUT) + { + return HAL_SD_ERROR_TIMEOUT; + } + } + + if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DTIMEOUT)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DTIMEOUT); + + return HAL_SD_ERROR_DATA_TIMEOUT; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_DCRCFAIL)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_DCRCFAIL); + + return HAL_SD_ERROR_DATA_CRC_FAIL; + } + else if(__HAL_SD_GET_FLAG(hsd, SDMMC_FLAG_RXOVERR)) + { + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_FLAG_RXOVERR); + + return HAL_SD_ERROR_RX_OVERRUN; + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __HAL_SD_CLEAR_FLAG(hsd, SDMMC_STATIC_DATA_FLAGS); + + *scr = (((tempscr[1] & SDMMC_0TO7BITS) << 24) | ((tempscr[1] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[1] & SDMMC_16TO23BITS) >> 8) | ((tempscr[1] & SDMMC_24TO31BITS) >> 24)); + scr++; + *scr = (((tempscr[0] & SDMMC_0TO7BITS) << 24) | ((tempscr[0] & SDMMC_8TO15BITS) << 8) |\ + ((tempscr[0] & SDMMC_16TO23BITS) >> 8) | ((tempscr[0] & SDMMC_24TO31BITS) >> 24)); + + } + + return HAL_SD_ERROR_NONE; +} + +/** + * @brief Wrap up reading in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void SD_Read_IT(SD_HandleTypeDef *hsd) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hsd->pRxBuffPtr; + dataremaining = hsd->RxXferSize; + + if (dataremaining > 0U) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = SDMMC_ReadFIFO(hsd->Instance); + *tmp = (uint8_t)(data & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 8U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 16U) & 0xFFU); + tmp++; + dataremaining--; + *tmp = (uint8_t)((data >> 24U) & 0xFFU); + tmp++; + dataremaining--; + } + + hsd->pRxBuffPtr = tmp; + hsd->RxXferSize = dataremaining; + } +} + +/** + * @brief Wrap up writing in non-blocking mode. + * @param hsd: pointer to a SD_HandleTypeDef structure that contains + * the configuration information. + * @retval None + */ +static void SD_Write_IT(SD_HandleTypeDef *hsd) +{ + uint32_t count, data, dataremaining; + uint8_t* tmp; + + tmp = hsd->pTxBuffPtr; + dataremaining = hsd->TxXferSize; + + if (dataremaining > 0U) + { + /* Write data to SDMMC Tx FIFO */ + for(count = 0U; count < 8U; count++) + { + data = (uint32_t)(*tmp); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 8U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 16U); + tmp++; + dataremaining--; + data |= ((uint32_t)(*tmp) << 24U); + tmp++; + dataremaining--; + (void)SDMMC_WriteFIFO(hsd->Instance, &data); + } + + hsd->pTxBuffPtr = tmp; + hsd->TxXferSize = dataremaining; + } +} + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDMMC1 */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c deleted file mode 100644 index 9b6ee798..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sdram.c +++ /dev/null @@ -1,1308 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sdram.c - * @author MCD Application Team - * @brief SDRAM HAL module driver. - * This file provides a generic firmware to drive SDRAM memories mounted - * as external device. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control SDRAM memories. It uses the FMC layer functions to interface - with SDRAM devices. - The following sequence should be followed to configure the FMC to interface - with SDRAM memories: - - (#) Declare a SDRAM_HandleTypeDef handle structure, for example: - SDRAM_HandleTypeDef hsdram - - (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed - values of the structure member. - - (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined - base register instance for NOR or SDRAM device - - (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: - FMC_SDRAM_TimingTypeDef Timing; - and fill its fields with the allowed values of the structure member. - - (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function - performs the following sequence: - - (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() - (##) Control register configuration using the FMC SDRAM interface function - FMC_SDRAM_Init() - (##) Timing register configuration using the FMC SDRAM interface function - FMC_SDRAM_Timing_Init() - (##) Program the SDRAM external device by applying its initialization sequence - according to the device plugged in your hardware. This step is mandatory - for accessing the SDRAM device. - - (#) At this stage you can perform read/write accesses from/to the memory connected - to the SDRAM Bank. You can perform either polling or DMA transfer using the - following APIs: - (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access - (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer - - (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ - HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or - the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM - device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef - structure. - - (#) You can continuously monitor the SDRAM device HAL state by calling the function - HAL_SDRAM_GetState() - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) MspInitCallback : SDRAM MspInit. - (+) MspDeInitCallback : SDRAM MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. It allows to reset following callbacks: - (+) MspInitCallback : SDRAM MspInit. - (+) MspDeInitCallback : SDRAM MspDeInit. - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init - and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit - or HAL_SDRAM_Init function. - - When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_SDRAM_MODULE_ENABLED - -/** @defgroup SDRAM SDRAM - * @brief SDRAM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions - * @{ - */ -static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma); -static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma); -static void SDRAM_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions - * @{ - */ - -/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### SDRAM Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize/de-initialize - the SDRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Performs the SDRAM device initialization sequence. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param Timing Pointer to SDRAM control timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) -{ - /* Check the SDRAM handle parameter */ - if (hsdram == NULL) - { - return HAL_ERROR; - } - - if (hsdram->State == HAL_SDRAM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsdram->Lock = HAL_UNLOCKED; -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - if (hsdram->MspInitCallback == NULL) - { - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - } - hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; - hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - - /* Init the low level hardware */ - hsdram->MspInitCallback(hsdram); -#else - /* Initialize the low level hardware (MSP) */ - HAL_SDRAM_MspInit(hsdram); -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ - } - - /* Initialize the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Initialize SDRAM control Interface */ - (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); - - /* Initialize SDRAM timing Interface */ - (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Perform the SDRAM device initialization sequence. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) -{ -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - if (hsdram->MspDeInitCallback == NULL) - { - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - } - - /* DeInit the low level hardware */ - hsdram->MspDeInitCallback(hsdram); -#else - /* Initialize the low level hardware (MSP) */ - HAL_SDRAM_MspDeInit(hsdram); -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ - - /* Configure the SDRAM registers with their reset values */ - (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); - - /* Reset the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; -} - -/** - * @brief SDRAM MSP Init. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval None - */ -__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsdram); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_MspInit could be implemented in the user file - */ -} - -/** - * @brief SDRAM MSP DeInit. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval None - */ -__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsdram); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function handles SDRAM refresh error interrupt request. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL status - */ -void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) -{ - /* Check SDRAM interrupt Rising edge flag */ - if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) - { - /* SDRAM refresh error interrupt callback */ -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - hsdram->RefreshErrorCallback(hsdram); -#else - HAL_SDRAM_RefreshErrorCallback(hsdram); -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ - - /* Clear SDRAM refresh error interrupt pending bit */ - __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); - } -} - -/** - * @brief SDRAM Refresh error callback. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval None - */ -__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsdram); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete error callback. - * @param hdma DMA handle - * @retval None - */ -__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### SDRAM Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the SDRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Reads 8-bit data buffer from the SDRAM memory. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer - * @param BufferSize Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - uint8_t *pdestbuff = pDstBuffer; - HAL_SDRAM_StateTypeDef state = hsdram->State; - - /* Check the SDRAM controller state */ - if (state == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Read data from source */ - for (size = BufferSize; size != 0U; size--) - { - *pdestbuff = *(__IO uint8_t *)pSdramAddress; - pdestbuff++; - pSdramAddress++; - } - - /* Update the SDRAM controller state */ - hsdram->State = state; - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Writes 8-bit data buffer to SDRAM memory. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write - * @param BufferSize Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - uint8_t *psrcbuff = pSrcBuffer; - - /* Check the SDRAM controller state */ - if (hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hsdram->State == HAL_SDRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Write data to memory */ - for (size = BufferSize; size != 0U; size--) - { - *(__IO uint8_t *)pSdramAddress = *psrcbuff; - psrcbuff++; - pSdramAddress++; - } - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Reads 16-bit data buffer from the SDRAM memory. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer - * @param BufferSize Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint32_t *pSdramAddress = pAddress; - uint16_t *pdestbuff = pDstBuffer; - HAL_SDRAM_StateTypeDef state = hsdram->State; - - /* Check the SDRAM controller state */ - if (state == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Read data from memory */ - for (size = BufferSize; size >= 2U ; size -= 2U) - { - *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); - pdestbuff++; - *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U); - pdestbuff++; - pSdramAddress++; - } - - /* Read last 16-bits if size is not 32-bits multiple */ - if ((BufferSize % 2U) != 0U) - { - *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); - } - - /* Update the SDRAM controller state */ - hsdram->State = state; - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Writes 16-bit data buffer to SDRAM memory. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write - * @param BufferSize Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint32_t *psdramaddress = pAddress; - uint16_t *psrcbuff = pSrcBuffer; - - /* Check the SDRAM controller state */ - if (hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hsdram->State == HAL_SDRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Write data to memory */ - for (size = BufferSize; size >= 2U ; size -= 2U) - { - *psdramaddress = (uint32_t)(*psrcbuff); - psrcbuff++; - *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U); - psrcbuff++; - psdramaddress++; - } - - /* Write last 16-bits if size is not 32-bits multiple */ - if ((BufferSize % 2U) != 0U) - { - *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); - } - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Reads 32-bit data buffer from the SDRAM memory. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer - * @param BufferSize Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; - uint32_t *pdestbuff = pDstBuffer; - HAL_SDRAM_StateTypeDef state = hsdram->State; - - /* Check the SDRAM controller state */ - if (state == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Read data from source */ - for (size = BufferSize; size != 0U; size--) - { - *pdestbuff = *(__IO uint32_t *)pSdramAddress; - pdestbuff++; - pSdramAddress++; - } - - /* Update the SDRAM controller state */ - hsdram->State = state; - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Writes 32-bit data buffer to SDRAM memory. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write - * @param BufferSize Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint32_t *pSdramAddress = pAddress; - uint32_t *psrcbuff = pSrcBuffer; - - /* Check the SDRAM controller state */ - if (hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hsdram->State == HAL_SDRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Write data to memory */ - for (size = BufferSize; size != 0U; size--) - { - *pSdramAddress = *psrcbuff; - psrcbuff++; - pSdramAddress++; - } - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Reads a Words data from the SDRAM memory using DMA transfer. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer - * @param BufferSize Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, - uint32_t BufferSize) -{ - HAL_StatusTypeDef status; - HAL_SDRAM_StateTypeDef state = hsdram->State; - - /* Check the SDRAM controller state */ - if (state == HAL_SDRAM_STATE_BUSY) - { - status = HAL_BUSY; - } - else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - if (state == HAL_SDRAM_STATE_READY) - { - hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; - } - else - { - hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt; - } - hsdram->hdma->XferErrorCallback = SDRAM_DMAError; - - /* Enable the DMA Stream */ - status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - } - else - { - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write - * @param BufferSize Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, - uint32_t BufferSize) -{ - HAL_StatusTypeDef status; - - /* Check the SDRAM controller state */ - if (hsdram->State == HAL_SDRAM_STATE_BUSY) - { - status = HAL_BUSY; - } - else if (hsdram->State == HAL_SDRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; - hsdram->hdma->XferErrorCallback = SDRAM_DMAError; - - /* Enable the DMA Stream */ - status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - } - else - { - status = HAL_ERROR; - } - - return status; -} - -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User SDRAM Callback - * To be used to override the weak predefined callback - * @param hsdram : SDRAM handle - * @param CallbackId : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID - * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID - * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, - pSDRAM_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_SDRAM_StateTypeDef state; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - state = hsdram->State; - if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - switch (CallbackId) - { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = pCallback; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = pCallback; - break; - case HAL_SDRAM_REFRESH_ERR_CB_ID : - hsdram->RefreshErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hsdram->State == HAL_SDRAM_STATE_RESET) - { - switch (CallbackId) - { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = pCallback; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a User SDRAM Callback - * SDRAM Callback is redirected to the weak predefined callback - * @param hsdram : SDRAM handle - * @param CallbackId : ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID - * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID - * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID - * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID - * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_SDRAM_StateTypeDef state; - - state = hsdram->State; - if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - switch (CallbackId) - { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - break; - case HAL_SDRAM_REFRESH_ERR_CB_ID : - hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; - break; - case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : - hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - break; - case HAL_SDRAM_DMA_XFER_ERR_CB_ID : - hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hsdram->State == HAL_SDRAM_STATE_RESET) - { - switch (CallbackId) - { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Register a User SDRAM Callback for DMA transfers - * To be used to override the weak predefined callback - * @param hsdram : SDRAM handle - * @param CallbackId : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID - * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, - pSDRAM_DmaCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_SDRAM_StateTypeDef state; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hsdram); - - state = hsdram->State; - if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) - { - switch (CallbackId) - { - case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : - hsdram->DmaXferCpltCallback = pCallback; - break; - case HAL_SDRAM_DMA_XFER_ERR_CB_ID : - hsdram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hsdram); - return status; -} -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup SDRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### SDRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the SDRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically SDRAM write protection. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) -{ - /* Check the SDRAM controller state */ - if (hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hsdram->State == HAL_SDRAM_STATE_READY) - { - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Enable write protection */ - (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Disables dynamically SDRAM write protection. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) -{ - HAL_SDRAM_StateTypeDef state = hsdram->State; - - /* Check the SDRAM controller state */ - if (state == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED) - { - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Disable write protection */ - (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Sends Command to the SDRAM bank. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param Command SDRAM command structure - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, - uint32_t Timeout) -{ - HAL_SDRAM_StateTypeDef state = hsdram->State; - - /* Check the SDRAM controller state */ - if (state == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) - { - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Send SDRAM command */ - (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); - - /* Update the SDRAM controller state state */ - if (Command->CommandMode == FMC_SDRAM_CMD_PALL) - { - hsdram->State = HAL_SDRAM_STATE_PRECHARGED; - } - else - { - hsdram->State = HAL_SDRAM_STATE_READY; - } - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Programs the SDRAM Memory Refresh rate. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param RefreshRate The SDRAM refresh rate value - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) -{ - /* Check the SDRAM controller state */ - if (hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hsdram->State == HAL_SDRAM_STATE_READY) - { - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Program the refresh rate */ - (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param AutoRefreshNumber The SDRAM auto Refresh number - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) -{ - /* Check the SDRAM controller state */ - if (hsdram->State == HAL_SDRAM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (hsdram->State == HAL_SDRAM_STATE_READY) - { - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Set the Auto-Refresh number */ - (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Returns the SDRAM memory current mode. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval The SDRAM memory mode. - */ -uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) -{ - /* Return the SDRAM memory current mode */ - return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); -} - -/** - * @} - */ - -/** @defgroup SDRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### SDRAM State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the SDRAM controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the SDRAM state. - * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @retval HAL state - */ -HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) -{ - return hsdram->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup SDRAM_Private_Functions SDRAM Private Functions - * @{ - */ -/** - * @brief DMA SDRAM process complete callback. - * @param hdma : DMA handle - * @retval None - */ -static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma) -{ - SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_READY; - -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - hsdram->DmaXferCpltCallback(hdma); -#else - HAL_SDRAM_DMA_XferCpltCallback(hdma); -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SRAM process complete callback. - * @param hdma : DMA handle - * @retval None - */ -static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma) -{ - SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; - -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - hsdram->DmaXferCpltCallback(hdma); -#else - HAL_SDRAM_DMA_XferCpltCallback(hdma); -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SDRAM error callback. - * @param hdma : DMA handle - * @retval None - */ -static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) -{ - SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Update the SDRAM controller state */ - hsdram->State = HAL_SDRAM_STATE_ERROR; - -#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - hsdram->DmaXferErrorCallback(hdma); -#else - HAL_SDRAM_DMA_XferErrorCallback(hdma); -#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ -} - -/** - * @} - */ -/** - * @} - */ - -#endif /* HAL_SDRAM_MODULE_ENABLED */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c deleted file mode 100644 index 50782c45..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard.c +++ /dev/null @@ -1,2934 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_smartcard.c - * @author MCD Application Team - * @brief SMARTCARD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the SMARTCARD peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Error functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SMARTCARD HAL driver can be used as follows: - - (#) Declare a SMARTCARD_HandleTypeDef handle structure (eg. SMARTCARD_HandleTypeDef hsmartcard). - (#) Associate a USART to the SMARTCARD handle hsmartcard. - (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API: - (++) Enable the USARTx interface clock. - (++) USART pins configuration: - (+++) Enable the clock for the USART GPIOs. - (+++) Configure the USART pins (TX as alternate function pull-up, RX as alternate function Input). - (++) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT() - and HAL_SMARTCARD_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (++) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA() - and HAL_SMARTCARD_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the SMARTCARD DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Parity, Mode(Receiver/Transmitter), clock enabling/disabling and accordingly, - the clock parameters (parity, phase, last bit), prescaler value, guard time and NACK on transmission - error enabling or disabling in the hsmartcard handle Init structure. - - (#) If required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut, auto-retry counter,...) - in the hsmartcard handle AdvancedInit structure. - - (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_SMARTCARD_MspInit() API. - [..] - (@) The specific SMARTCARD interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process. - - [..] - [..] Three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() - (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive() - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Send an amount of data in non-blocking mode using HAL_SMARTCARD_Transmit_IT() - (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback() - (+) Receive an amount of data in non-blocking mode using HAL_SMARTCARD_Receive_IT() - (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback() - (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Send an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() - (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback() - (+) Receive an amount of data in non-blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() - (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback() is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback() - (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback() - - *** SMARTCARD HAL driver macros list *** - ======================================== - [..] - Below the list of most used macros in SMARTCARD HAL driver. - - (+) __HAL_SMARTCARD_GET_FLAG : Check whether or not the specified SMARTCARD flag is set - (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag - (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt - (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt - (+) __HAL_SMARTCARD_GET_IT_SOURCE: Check whether or not the specified SMARTCARD interrupt is enabled - - [..] - (@) You can refer to the SMARTCARD HAL driver header file for more useful macros - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : Tx Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) MspInitCallback : SMARTCARD MspInit. - (+) MspDeInitCallback : SMARTCARD MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxCpltCallback : Tx Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) MspInitCallback : SMARTCARD MspInit. - (+) MspDeInitCallback : SMARTCARD MspDeInit. - - [..] - By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak functions in the HAL_SMARTCARD_Init() - and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_SMARTCARD_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() - or HAL_SMARTCARD_Init() function. - - [..] - When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak callbacks are used. - - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SMARTCARD SMARTCARD - * @brief HAL SMARTCARD module driver - * @{ - */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Constants SMARTCARD Private Constants - * @{ - */ -#define SMARTCARD_TEACK_REACK_TIMEOUT 1000U /*!< SMARTCARD TX or RX enable acknowledge time-out value */ - -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | \ - USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by SMARTCARD_SetConfig API */ - -#define USART_CR2_CLK_FIELDS ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \ - USART_CR2_CPHA | USART_CR2_LBCL)) /*!< SMARTCARD clock-related USART CR2 fields of parameters */ - -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_RTOEN | USART_CR2_CLK_FIELDS | \ - USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by SMARTCARD_SetConfig API */ - -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_ONEBIT | USART_CR3_NACK | \ - USART_CR3_SCARCNT)) /*!< USART CR3 fields of parameters set by SMARTCARD_SetConfig API */ - -#define USART_BRR_MIN 0x10U /*!< USART BRR minimum authorized value */ - -#define USART_BRR_MAX 0x0000FFFFU /*!< USART BRR maximum authorized value */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SMARTCARD_Private_Functions - * @{ - */ -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ -static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard); -static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard); -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, - FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); -static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); -static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard); -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard); -static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard); -static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions - * @{ - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx - associated to the SmartCard. - (+) These parameters can be configured: - (++) Baud Rate - (++) Parity: parity should be enabled, frame Length is fixed to 8 bits plus parity - (++) Receiver/transmitter modes - (++) Synchronous mode (and if enabled, phase, polarity and last bit parameters) - (++) Prescaler value - (++) Guard bit time - (++) NACK enabling or disabling on transmission error - - (+) The following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) Time out enabling (and if activated, timeout value) - (++) Block length - (++) Auto-retry counter - [..] - The HAL_SMARTCARD_Init() API follows the USART synchronous configuration procedures - (details for the procedures are available in reference manual). - -@endverbatim - - The USART frame format is given in the following table: - - Table 1. USART frame format. - +---------------------------------------------------------------+ - | M1M0 bits | PCE bit | USART frame | - |-----------------------|---------------------------------------| - | 01 | 1 | | SB | 8 bit data | PB | STB | | - +---------------------------------------------------------------+ - - - * @{ - */ - -/** - * @brief Initialize the SMARTCARD mode according to the specified - * parameters in the SMARTCARD_HandleTypeDef and initialize the associated handle. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Check the SMARTCARD handle allocation */ - if (hsmartcard == NULL) - { - return HAL_ERROR; - } - - /* Check the USART associated to the SMARTCARD handle */ - assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - - if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsmartcard->Lock = HAL_UNLOCKED; - -#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 - SMARTCARD_InitCallbacksToDefault(hsmartcard); - - if (hsmartcard->MspInitCallback == NULL) - { - hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; - } - - /* Init the low level hardware */ - hsmartcard->MspInitCallback(hsmartcard); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_SMARTCARD_MspInit(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ - } - - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - - /* Disable the Peripheral to set smartcard mode */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* In SmartCard mode, the following bits must be kept cleared: - - LINEN in the USART_CR2 register, - - HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_LINEN); - CLEAR_BIT(hsmartcard->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN)); - - /* set the USART in SMARTCARD mode */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_SCEN); - - /* Set the SMARTCARD Communication parameters */ - if (SMARTCARD_SetConfig(hsmartcard) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* Set the SMARTCARD transmission completion indication */ - SMARTCARD_TRANSMISSION_COMPLETION_SETTING(hsmartcard); - - if (hsmartcard->AdvancedInit.AdvFeatureInit != SMARTCARD_ADVFEATURE_NO_INIT) - { - SMARTCARD_AdvFeatureConfig(hsmartcard); - } - - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* TEACK and/or REACK to check before moving hsmartcard->gState and hsmartcard->RxState to Ready */ - return (SMARTCARD_CheckIdleState(hsmartcard)); -} - -/** - * @brief DeInitialize the SMARTCARD peripheral. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Check the SMARTCARD handle allocation */ - if (hsmartcard == NULL) - { - return HAL_ERROR; - } - - /* Check the USART/UART associated to the SMARTCARD handle */ - assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - - /* Disable the Peripheral */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - WRITE_REG(hsmartcard->Instance->CR1, 0x0U); - WRITE_REG(hsmartcard->Instance->CR2, 0x0U); - WRITE_REG(hsmartcard->Instance->CR3, 0x0U); - WRITE_REG(hsmartcard->Instance->RTOR, 0x0U); - WRITE_REG(hsmartcard->Instance->GTPR, 0x0U); - - /* DeInit the low level hardware */ -#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1 - if (hsmartcard->MspDeInitCallback == NULL) - { - hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; - } - /* DeInit the low level hardware */ - hsmartcard->MspDeInitCallback(hsmartcard); -#else - HAL_SMARTCARD_MspDeInit(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->gState = HAL_SMARTCARD_STATE_RESET; - hsmartcard->RxState = HAL_SMARTCARD_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(hsmartcard); - - return HAL_OK; -} - -/** - * @brief Initialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the SMARTCARD MSP. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_MspDeInit can be implemented in the user file - */ -} - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User SMARTCARD Callback - * To be used to override the weak predefined callback - * @note The HAL_SMARTCARD_RegisterCallback() may be called before HAL_SMARTCARD_Init() - * in HAL_SMARTCARD_STATE_RESET to register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID - * and HAL_SMARTCARD_MSPDEINIT_CB_ID - * @param hsmartcard smartcard handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, - pSMARTCARD_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - switch (CallbackID) - { - - case HAL_SMARTCARD_TX_COMPLETE_CB_ID : - hsmartcard->TxCpltCallback = pCallback; - break; - - case HAL_SMARTCARD_RX_COMPLETE_CB_ID : - hsmartcard->RxCpltCallback = pCallback; - break; - - case HAL_SMARTCARD_ERROR_CB_ID : - hsmartcard->ErrorCallback = pCallback; - break; - - case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : - hsmartcard->AbortCpltCallback = pCallback; - break; - - case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : - hsmartcard->AbortTransmitCpltCallback = pCallback; - break; - - case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : - hsmartcard->AbortReceiveCpltCallback = pCallback; - break; - - - case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = pCallback; - break; - - case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hsmartcard->gState == HAL_SMARTCARD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = pCallback; - break; - - case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an SMARTCARD callback - * SMARTCARD callback is redirected to the weak predefined callback - * @note The HAL_SMARTCARD_UnRegisterCallback() may be called before HAL_SMARTCARD_Init() - * in HAL_SMARTCARD_STATE_RESET to un-register callbacks for HAL_SMARTCARD_MSPINIT_CB_ID - * and HAL_SMARTCARD_MSPDEINIT_CB_ID - * @param hsmartcard smartcard handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_SMARTCARD_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_SMARTCARD_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_SMARTCARD_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_SMARTCARD_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_SMARTCARD_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_SMARTCARD_MSPDEINIT_CB_ID MspDeInit Callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_SMARTCARD_STATE_READY == hsmartcard->gState) - { - switch (CallbackID) - { - case HAL_SMARTCARD_TX_COMPLETE_CB_ID : - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_SMARTCARD_RX_COMPLETE_CB_ID : - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_SMARTCARD_ERROR_CB_ID : - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_SMARTCARD_ABORT_COMPLETE_CB_ID : - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID : - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak - AbortTransmitCpltCallback*/ - break; - - case HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID : - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak - AbortReceiveCpltCallback */ - break; - - - case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; /* Legacy weak MspInitCallback */ - break; - - case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; /* Legacy weak MspDeInitCallback */ - break; - - default : - /* Update the error code */ - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SMARTCARD_STATE_RESET == hsmartcard->gState) - { - switch (CallbackID) - { - case HAL_SMARTCARD_MSPINIT_CB_ID : - hsmartcard->MspInitCallback = HAL_SMARTCARD_MspInit; - break; - - case HAL_SMARTCARD_MSPDEINIT_CB_ID : - hsmartcard->MspDeInitCallback = HAL_SMARTCARD_MspDeInit; - break; - - default : - /* Update the error code */ - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions - * @brief SMARTCARD Transmit and Receive functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SMARTCARD data transfers. - - [..] - Smartcard is a single wire half duplex communication protocol. - The Smartcard interface is designed to support asynchronous protocol Smartcards as - defined in the ISO 7816-3 standard. The USART should be configured as: - (+) 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register - (+) 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register. - - [..] - (#) There are two modes of transfer: - (##) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (##) Non-Blocking mode: The communication is performed using Interrupts - or DMA, the relevant API's return the HAL status. - The end of the data processing will be indicated through the - dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - (##) The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks - will be executed respectively at the end of the Transmit or Receive process - The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication - error is detected. - - (#) Blocking mode APIs are : - (##) HAL_SMARTCARD_Transmit() - (##) HAL_SMARTCARD_Receive() - - (#) Non Blocking mode APIs with Interrupt are : - (##) HAL_SMARTCARD_Transmit_IT() - (##) HAL_SMARTCARD_Receive_IT() - (##) HAL_SMARTCARD_IRQHandler() - - (#) Non Blocking mode functions with DMA are : - (##) HAL_SMARTCARD_Transmit_DMA() - (##) HAL_SMARTCARD_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (##) HAL_SMARTCARD_TxCpltCallback() - (##) HAL_SMARTCARD_RxCpltCallback() - (##) HAL_SMARTCARD_ErrorCallback() - - [..] - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (##) HAL_SMARTCARD_Abort() - (##) HAL_SMARTCARD_AbortTransmit() - (##) HAL_SMARTCARD_AbortReceive() - (##) HAL_SMARTCARD_Abort_IT() - (##) HAL_SMARTCARD_AbortTransmit_IT() - (##) HAL_SMARTCARD_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_SMARTCARD_Abortxxx_IT), - a set of Abort Complete Callbacks are provided: - (##) HAL_SMARTCARD_AbortCpltCallback() - (##) HAL_SMARTCARD_AbortTransmitCpltCallback() - (##) HAL_SMARTCARD_AbortReceiveCpltCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (##) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, - Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, - Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. Transfer is kept ongoing on SMARTCARD side. - If user wants to abort it, Abort services should be called by user. - (##) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Frame Error in Interrupt mode transmission, Overrun Error in Interrupt - mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, - and HAL_SMARTCARD_ErrorCallback() user callback is executed. - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData pointer to data buffer. - * @param Size amount of data to be sent. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size, - uint32_t Timeout) -{ - uint32_t tickstart; - const uint8_t *ptmpdata = pData; - - /* Check that a Tx process is not already ongoing */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - if ((ptmpdata == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsmartcard); - - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Disable the Peripheral first to update mode for TX master */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor - the bidirectional line to detect a NACK signal in case of parity error. - Therefore, the receiver block must be enabled as well (RE bit must be set). */ - if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) - { - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - } - /* Enable Tx */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* Perform a TX/RX FIFO Flush */ - __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->TxXferSize = Size; - hsmartcard->TxXferCount = Size; - - while (hsmartcard->TxXferCount > 0U) - { - hsmartcard->TxXferCount--; - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - hsmartcard->Instance->TDR = (uint8_t)(*ptmpdata & 0xFFU); - ptmpdata++; - } - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_TRANSMISSION_COMPLETION_FLAG(hsmartcard), RESET, - tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Disable the Peripheral first to update mode */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) - { - /* In case of TX only mode, if NACK is enabled, receiver block has been enabled - for Transmit phase. Disable this receiver block. */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - } - if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) - || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) - { - /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ - __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); - } - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* At end of Tx process, restore hsmartcard->gState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData pointer to data buffer. - * @param Size amount of data to be received. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, - uint32_t Timeout) -{ - uint32_t tickstart; - uint8_t *ptmpdata = pData; - - /* Check that a Rx process is not already ongoing */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) - { - if ((ptmpdata == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsmartcard); - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - hsmartcard->RxXferSize = Size; - hsmartcard->RxXferCount = Size; - - /* Check the remain data to be received */ - while (hsmartcard->RxXferCount > 0U) - { - hsmartcard->RxXferCount--; - - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, SMARTCARD_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); - ptmpdata++; - } - - /* At end of Rx process, restore hsmartcard->RxState to Ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData pointer to data buffer. - * @param Size amount of data to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsmartcard); - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - - hsmartcard->pTxBuffPtr = pData; - hsmartcard->TxXferSize = Size; - hsmartcard->TxXferCount = Size; - hsmartcard->TxISR = NULL; - - /* Disable the Peripheral first to update mode for TX master */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor - the bidirectional line to detect a NACK signal in case of parity error. - Therefore, the receiver block must be enabled as well (RE bit must be set). */ - if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) - { - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - } - /* Enable Tx */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* Perform a TX/RX FIFO Flush */ - __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); - - /* Configure Tx interrupt processing */ - /* Set the Tx ISR function pointer */ - hsmartcard->TxISR = SMARTCARD_TxISR; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Enable the SMARTCARD Error Interrupt: (Frame error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Enable the SMARTCARD Transmit Data Register Empty Interrupt */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData pointer to data buffer. - * @param Size amount of data to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsmartcard); - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - - hsmartcard->pRxBuffPtr = pData; - hsmartcard->RxXferSize = Size; - hsmartcard->RxXferCount = Size; - - /* Configure Rx interrupt processing */ - /* Set the Rx ISR function pointer */ - hsmartcard->RxISR = SMARTCARD_RxISR; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Enable the SMARTCARD Parity Error and Data Register not empty Interrupts */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData pointer to data buffer. - * @param Size amount of data to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsmartcard); - - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY_TX; - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->pTxBuffPtr = pData; - hsmartcard->TxXferSize = Size; - hsmartcard->TxXferCount = Size; - - /* Disable the Peripheral first to update mode for TX master */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* In case of TX only mode, if NACK is enabled, the USART must be able to monitor - the bidirectional line to detect a NACK signal in case of parity error. - Therefore, the receiver block must be enabled as well (RE bit must be set). */ - if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) - { - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - } - /* Enable Tx */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_TE); - - /* Enable the Peripheral */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* Perform a TX/RX FIFO Flush */ - __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); - - /* Set the SMARTCARD DMA transfer complete callback */ - hsmartcard->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt; - - /* Set the SMARTCARD error callback */ - hsmartcard->hdmatx->XferErrorCallback = SMARTCARD_DMAError; - - /* Set the DMA abort callback */ - hsmartcard->hdmatx->XferAbortCallback = NULL; - - /* Enable the SMARTCARD transmit DMA channel */ - if (HAL_DMA_Start_IT(hsmartcard->hdmatx, (uint32_t)hsmartcard->pTxBuffPtr, (uint32_t)&hsmartcard->Instance->TDR, - Size) == HAL_OK) - { - /* Clear the TC flag in the ICR register */ - CLEAR_BIT(hsmartcard->Instance->ICR, USART_ICR_TCCF); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Enable the UART Error Interrupt: (Frame error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the SMARTCARD associated USART CR3 register */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - /* Set error code to DMA */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Restore hsmartcard->State to ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - - return HAL_ERROR; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param pData pointer to data buffer. - * @param Size amount of data to be received. - * @note The SMARTCARD-associated USART parity is enabled (PCE = 1), - * the received data contain the parity bit (MSB position). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsmartcard); - - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - hsmartcard->RxState = HAL_SMARTCARD_STATE_BUSY_RX; - - hsmartcard->pRxBuffPtr = pData; - hsmartcard->RxXferSize = Size; - - /* Set the SMARTCARD DMA transfer complete callback */ - hsmartcard->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt; - - /* Set the SMARTCARD DMA error callback */ - hsmartcard->hdmarx->XferErrorCallback = SMARTCARD_DMAError; - - /* Set the DMA abort callback */ - hsmartcard->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(hsmartcard->hdmarx, (uint32_t)&hsmartcard->Instance->RDR, (uint32_t)hsmartcard->pRxBuffPtr, - Size) == HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Enable the SMARTCARD Parity Error Interrupt */ - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - - /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the SMARTCARD associated USART CR3 register */ - SET_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; - } - else - { - /* Set error code to DMA */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - /* Restore hsmartcard->State to ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - return HAL_ERROR; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable SMARTCARD Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, - (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | - USART_CR1_EOBIE)); - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Disable the SMARTCARD DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - - /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (hsmartcard->hdmatx != NULL) - { - /* Set the SMARTCARD DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - hsmartcard->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Disable the SMARTCARD DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - - /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (hsmartcard->hdmarx != NULL) - { - /* Set the SMARTCARD DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - hsmartcard->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx and Rx transfer counters */ - hsmartcard->TxXferCount = 0U; - hsmartcard->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | - SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - - /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - /* Reset Handle ErrorCode to No Error */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable SMARTCARD Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) - { - /* Disable the SMARTCARD Error Interrupt: (Frame error) */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - } - - /* Disable the SMARTCARD DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - - /* Abort the SMARTCARD DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (hsmartcard->hdmatx != NULL) - { - /* Set the SMARTCARD DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - hsmartcard->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(hsmartcard->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(hsmartcard->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); - - /* Restore hsmartcard->gState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable SMARTCARD Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - /* Disable the SMARTCARD Error Interrupt: (Frame error) */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - } - - /* Disable the SMARTCARD DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - - /* Abort the SMARTCARD DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (hsmartcard->hdmarx != NULL) - { - /* Set the SMARTCARD DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - hsmartcard->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(hsmartcard->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(hsmartcard->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | - SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - - /* Restore hsmartcard->RxState to Ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable SMARTCARD Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - uint32_t abortcplt = 1U; - - /* Disable RTOIE, EOBIE, TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, - (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RTOIE | - USART_CR1_EOBIE)); - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* If DMA Tx and/or DMA Rx Handles are associated to SMARTCARD Handle, - DMA Abort complete callbacks should be initialised before any call - to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (hsmartcard->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if SMARTCARD DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) - { - hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxAbortCallback; - } - else - { - hsmartcard->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (hsmartcard->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if SMARTCARD DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - { - hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxAbortCallback; - } - else - { - hsmartcard->hdmarx->XferAbortCallback = NULL; - } - } - - /* Disable the SMARTCARD DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at UART level */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - - /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (hsmartcard->hdmatx != NULL) - { - /* SMARTCARD Tx DMA Abort callback has already been initialised : - will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) - { - hsmartcard->hdmatx->XferAbortCallback = NULL; - } - else - { - abortcplt = 0U; - } - } - } - - /* Disable the SMARTCARD DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - - /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (hsmartcard->hdmarx != NULL) - { - /* SMARTCARD Rx DMA Abort callback has already been initialised : - will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) - { - hsmartcard->hdmarx->XferAbortCallback = NULL; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - hsmartcard->TxXferCount = 0U; - hsmartcard->RxXferCount = 0U; - - /* Clear ISR function pointers */ - hsmartcard->RxISR = NULL; - hsmartcard->TxISR = NULL; - - /* Reset errorCode */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | - SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - - /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - hsmartcard->AbortCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort complete callback */ - HAL_SMARTCARD_AbortCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable SMARTCARD Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) - { - /* Disable the SMARTCARD Error Interrupt: (Frame error) */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - } - - /* Disable the SMARTCARD DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - - /* Abort the SMARTCARD DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (hsmartcard->hdmatx != NULL) - { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ - hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) - { - /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ - hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - hsmartcard->TxISR = NULL; - - /* Restore hsmartcard->gState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - hsmartcard->AbortTransmitCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - } - else - { - /* Reset Tx transfer counter */ - hsmartcard->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - hsmartcard->TxISR = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); - - /* Restore hsmartcard->gState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - hsmartcard->AbortTransmitCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable SMARTCARD Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable RTOIE, EOBIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE | USART_CR1_EOBIE)); - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Check if a Transmit process is ongoing or not. If not disable ERR IT */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - /* Disable the SMARTCARD Error Interrupt: (Frame error) */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - } - - /* Disable the SMARTCARD DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - - /* Abort the SMARTCARD DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (hsmartcard->hdmarx != NULL) - { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_AbortCpltCallback() at end of DMA abort procedure */ - hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) - { - /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ - hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - hsmartcard->RxISR = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | - SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - - /* Restore hsmartcard->RxState to Ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - hsmartcard->AbortReceiveCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - } - else - { - /* Reset Rx transfer counter */ - hsmartcard->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - hsmartcard->RxISR = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | - SMARTCARD_CLEAR_FEF | SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - - /* Restore hsmartcard->RxState to Ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - hsmartcard->AbortReceiveCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - - return HAL_OK; -} - -/** - * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard) -{ - uint32_t isrflags = READ_REG(hsmartcard->Instance->ISR); - uint32_t cr1its = READ_REG(hsmartcard->Instance->CR1); - uint32_t cr3its = READ_REG(hsmartcard->Instance->CR3); - uint32_t errorflags; - uint32_t errorcode; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - if (errorflags == 0U) - { - /* SMARTCARD in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - if (hsmartcard->RxISR != NULL) - { - hsmartcard->RxISR(hsmartcard); - } - return; - } - } - - /* If some errors occur */ - if ((errorflags != 0U) - && (((cr3its & USART_CR3_EIE) != 0U) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) - { - /* SMARTCARD parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_PEF); - - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_PE; - } - - /* SMARTCARD frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_FEF); - - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_FE; - } - - /* SMARTCARD noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_NEF); - - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_NE; - } - - /* SMARTCARD Over-Run interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_ORE) != 0U) - && (((cr1its & USART_CR1_RXNEIE) != 0U) - || ((cr3its & USART_CR3_EIE) != 0U))) - { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_OREF); - - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; - } - - /* SMARTCARD receiver timeout interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) - { - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_RTOF); - - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_RTO; - } - - /* Call SMARTCARD Error Call back function if need be --------------------------*/ - if (hsmartcard->ErrorCode != HAL_SMARTCARD_ERROR_NONE) - { - /* SMARTCARD in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - if (hsmartcard->RxISR != NULL) - { - hsmartcard->RxISR(hsmartcard); - } - } - - /* If Error is to be considered as blocking : - - Receiver Timeout error in Reception - - Overrun error in Reception - - any error occurs in DMA mode reception - */ - errorcode = hsmartcard->ErrorCode; - if ((HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - || ((errorcode & (HAL_SMARTCARD_ERROR_RTO | HAL_SMARTCARD_ERROR_ORE)) != 0U)) - { - /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - SMARTCARD_EndRxTransfer(hsmartcard); - - /* Disable the SMARTCARD DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - - /* Abort the SMARTCARD DMA Rx channel */ - if (hsmartcard->hdmarx != NULL) - { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ - hsmartcard->hdmarx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hsmartcard->hdmarx) != HAL_OK) - { - /* Call Directly hsmartcard->hdmarx->XferAbortCallback function in case of error */ - hsmartcard->hdmarx->XferAbortCallback(hsmartcard->hdmarx); - } - } - else - { -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hsmartcard->ErrorCallback(hsmartcard); -#else - /* Call legacy weak user error callback */ - HAL_SMARTCARD_ErrorCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - } - else - { -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hsmartcard->ErrorCallback(hsmartcard); -#else - /* Call legacy weak user error callback */ - HAL_SMARTCARD_ErrorCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - } - /* other error type to be considered as blocking : - - Frame error in Transmission - */ - else if ((hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - && ((errorcode & HAL_SMARTCARD_ERROR_FE) != 0U)) - { - /* Blocking error : transfer is aborted - Set the SMARTCARD state ready to be able to start again the process, - Disable Tx Interrupts, and disable Tx DMA request, if ongoing */ - SMARTCARD_EndTxTransfer(hsmartcard); - - /* Disable the SMARTCARD DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - - /* Abort the SMARTCARD DMA Tx channel */ - if (hsmartcard->hdmatx != NULL) - { - /* Set the SMARTCARD DMA Abort callback : - will lead to call HAL_SMARTCARD_ErrorCallback() at end of DMA abort procedure */ - hsmartcard->hdmatx->XferAbortCallback = SMARTCARD_DMAAbortOnError; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hsmartcard->hdmatx) != HAL_OK) - { - /* Call Directly hsmartcard->hdmatx->XferAbortCallback function in case of error */ - hsmartcard->hdmatx->XferAbortCallback(hsmartcard->hdmatx); - } - } - else - { -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hsmartcard->ErrorCallback(hsmartcard); -#else - /* Call legacy weak user error callback */ - HAL_SMARTCARD_ErrorCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - } - else - { -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hsmartcard->ErrorCallback(hsmartcard); -#else - /* Call legacy weak user error callback */ - HAL_SMARTCARD_ErrorCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hsmartcard->ErrorCallback(hsmartcard); -#else - /* Call legacy weak user error callback */ - HAL_SMARTCARD_ErrorCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* SMARTCARD in mode Receiver, end of block interruption ------------------------*/ - if (((isrflags & USART_ISR_EOBF) != 0U) && ((cr1its & USART_CR1_EOBIE) != 0U)) - { - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - __HAL_UNLOCK(hsmartcard); -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Rx complete callback */ - hsmartcard->RxCpltCallback(hsmartcard); -#else - /* Call legacy weak Rx complete callback */ - HAL_SMARTCARD_RxCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - /* Clear EOBF interrupt after HAL_SMARTCARD_RxCpltCallback() call for the End of Block information - to be available during HAL_SMARTCARD_RxCpltCallback() processing */ - __HAL_SMARTCARD_CLEAR_IT(hsmartcard, SMARTCARD_CLEAR_EOBF); - return; - } - - /* SMARTCARD in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_ISR_TXE) != 0U) - && ((cr1its & USART_CR1_TXEIE) != 0U)) - { - if (hsmartcard->TxISR != NULL) - { - hsmartcard->TxISR(hsmartcard); - } - return; - } - - /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/ - if (__HAL_SMARTCARD_GET_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) - { - if (__HAL_SMARTCARD_GET_IT_SOURCE(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication) != RESET) - { - SMARTCARD_EndTransmit_IT(hsmartcard); - return; - } - } - -} - -/** - * @brief Tx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief SMARTCARD error callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_ErrorCallback can be implemented in the user file. - */ -} - -/** - * @brief SMARTCARD Abort Complete callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief SMARTCARD Abort Complete callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief SMARTCARD Abort Receive Complete callback. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -__weak void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmartcard); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMARTCARD_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup SMARTCARD_Exported_Functions_Group4 Peripheral State and Errors functions - * @brief SMARTCARD State and Errors functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Errors functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to return the State of SmartCard - handle and also return Peripheral Errors occurred during communication process - (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state - of the SMARTCARD peripheral. - (+) HAL_SMARTCARD_GetError() checks in run-time errors that could occur during - communication. - -@endverbatim - * @{ - */ - -/** - * @brief Return the SMARTCARD handle state. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD handle state - */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Return SMARTCARD handle state */ - uint32_t temp1; - uint32_t temp2; - temp1 = (uint32_t)hsmartcard->gState; - temp2 = (uint32_t)hsmartcard->RxState; - - return (HAL_SMARTCARD_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the SMARTCARD handle error code. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval SMARTCARD handle Error Code - */ -uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsmartcard) -{ - return hsmartcard->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SMARTCARD_Private_Functions SMARTCARD Private Functions - * @{ - */ - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -/** - * @brief Initialize the callbacks to their default values. - * @param hsmartcard SMARTCARD handle. - * @retval none - */ -void SMARTCARD_InitCallbacksToDefault(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Init the SMARTCARD Callback settings */ - hsmartcard->TxCpltCallback = HAL_SMARTCARD_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hsmartcard->RxCpltCallback = HAL_SMARTCARD_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hsmartcard->ErrorCallback = HAL_SMARTCARD_ErrorCallback; /* Legacy weak ErrorCallback */ - hsmartcard->AbortCpltCallback = HAL_SMARTCARD_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hsmartcard->AbortTransmitCpltCallback = HAL_SMARTCARD_AbortTransmitCpltCallback; /* Legacy weak - AbortTransmitCpltCallback */ - hsmartcard->AbortReceiveCpltCallback = HAL_SMARTCARD_AbortReceiveCpltCallback; /* Legacy weak - AbortReceiveCpltCallback */ - -} -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ - -/** - * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard) -{ - uint32_t tmpreg; - SMARTCARD_ClockSourceTypeDef clocksource; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t pclk; - - /* Check the parameters */ - assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); - assert_param(IS_SMARTCARD_BAUDRATE(hsmartcard->Init.BaudRate)); - assert_param(IS_SMARTCARD_WORD_LENGTH(hsmartcard->Init.WordLength)); - assert_param(IS_SMARTCARD_STOPBITS(hsmartcard->Init.StopBits)); - assert_param(IS_SMARTCARD_PARITY(hsmartcard->Init.Parity)); - assert_param(IS_SMARTCARD_MODE(hsmartcard->Init.Mode)); - assert_param(IS_SMARTCARD_POLARITY(hsmartcard->Init.CLKPolarity)); - assert_param(IS_SMARTCARD_PHASE(hsmartcard->Init.CLKPhase)); - assert_param(IS_SMARTCARD_LASTBIT(hsmartcard->Init.CLKLastBit)); - assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsmartcard->Init.OneBitSampling)); - assert_param(IS_SMARTCARD_NACK(hsmartcard->Init.NACKEnable)); - assert_param(IS_SMARTCARD_TIMEOUT(hsmartcard->Init.TimeOutEnable)); - assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsmartcard->Init.AutoRetryCount)); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* In SmartCard mode, M and PCE are forced to 1 (8 bits + parity). - * Oversampling is forced to 16 (OVER8 = 0). - * Configure the Parity and Mode: - * set PS bit according to hsmartcard->Init.Parity value - * set TE and RE bits according to hsmartcard->Init.Mode value */ - tmpreg = (((uint32_t)hsmartcard->Init.Parity) | ((uint32_t)hsmartcard->Init.Mode) | - ((uint32_t)hsmartcard->Init.WordLength)); - MODIFY_REG(hsmartcard->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - tmpreg = hsmartcard->Init.StopBits; - /* Synchronous mode is activated by default */ - tmpreg |= (uint32_t) USART_CR2_CLKEN | hsmartcard->Init.CLKPolarity; - tmpreg |= (uint32_t) hsmartcard->Init.CLKPhase | hsmartcard->Init.CLKLastBit; - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutEnable; - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_FIELDS, tmpreg); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - one-bit sampling method versus three samples' majority rule - * according to hsmartcard->Init.OneBitSampling - * - NACK transmission in case of parity error according - * to hsmartcard->Init.NACKEnable - * - autoretry counter according to hsmartcard->Init.AutoRetryCount */ - - tmpreg = (uint32_t) hsmartcard->Init.OneBitSampling | hsmartcard->Init.NACKEnable; - tmpreg |= ((uint32_t)hsmartcard->Init.AutoRetryCount << USART_CR3_SCARCNT_Pos); - MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_FIELDS, tmpreg); - - - /*-------------------------- USART GTPR Configuration ----------------------*/ - tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); - MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg); - - /*-------------------------- USART RTOR Configuration ----------------------*/ - tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); - if (hsmartcard->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) - { - assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); - tmpreg |= (uint32_t) hsmartcard->Init.TimeOutValue; - } - MODIFY_REG(hsmartcard->Instance->RTOR, (USART_RTOR_RTO | USART_RTOR_BLEN), tmpreg); - - /*-------------------------- USART BRR Configuration -----------------------*/ - SMARTCARD_GETCLOCKSOURCE(hsmartcard, clocksource); - tmpreg = 0U; - switch (clocksource) - { - case SMARTCARD_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - tmpreg = (uint32_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_PCLK2: - pclk = HAL_RCC_GetPCLK2Freq(); - tmpreg = (uint32_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_HSI: - tmpreg = (uint32_t)((HSI_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - tmpreg = (uint32_t)((pclk + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); - break; - case SMARTCARD_CLOCKSOURCE_LSE: - tmpreg = (uint32_t)((LSE_VALUE + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); - break; - default: - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 */ - if ((tmpreg >= USART_BRR_MIN) && (tmpreg <= USART_BRR_MAX)) - { - hsmartcard->Instance->BRR = (uint16_t)tmpreg; - } - else - { - ret = HAL_ERROR; - } - - - /* Clear ISR function pointers */ - hsmartcard->RxISR = NULL; - hsmartcard->TxISR = NULL; - - return ret; -} - - -/** - * @brief Configure the SMARTCARD associated USART peripheral advanced features. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_SMARTCARD_ADVFEATURE_INIT(hsmartcard->AdvancedInit.AdvFeatureInit)); - - /* if required, configure TX pin active level inversion */ - if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXINVERT_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_TXINV(hsmartcard->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_TXINV, hsmartcard->AdvancedInit.TxPinLevelInvert); - } - - /* if required, configure RX pin active level inversion */ - if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXINVERT_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_RXINV(hsmartcard->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_RXINV, hsmartcard->AdvancedInit.RxPinLevelInvert); - } - - /* if required, configure data inversion */ - if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DATAINVERT_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_DATAINV(hsmartcard->AdvancedInit.DataInvert)); - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_DATAINV, hsmartcard->AdvancedInit.DataInvert); - } - - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_SWAP(hsmartcard->AdvancedInit.Swap)); - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_SWAP, hsmartcard->AdvancedInit.Swap); - } - - /* if required, configure RX overrun detection disabling */ - if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_SMARTCARD_OVERRUN(hsmartcard->AdvancedInit.OverrunDisable)); - MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_OVRDIS, hsmartcard->AdvancedInit.OverrunDisable); - } - - /* if required, configure DMA disabling on reception error */ - if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(hsmartcard->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(hsmartcard->Instance->CR3, USART_CR3_DDRE, hsmartcard->AdvancedInit.DMADisableonRxError); - } - - /* if required, configure MSB first on communication line */ - if (HAL_IS_BIT_SET(hsmartcard->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_MSBFIRST_INIT)) - { - assert_param(IS_SMARTCARD_ADVFEATURE_MSBFIRST(hsmartcard->AdvancedInit.MSBFirst)); - MODIFY_REG(hsmartcard->Instance->CR2, USART_CR2_MSBFIRST, hsmartcard->AdvancedInit.MSBFirst); - } - -} - -/** - * @brief Check the SMARTCARD Idle State. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_CheckIdleState(SMARTCARD_HandleTypeDef *hsmartcard) -{ - uint32_t tickstart; - - /* Initialize the SMARTCARD ErrorCode */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if ((hsmartcard->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_TEACK, RESET, tickstart, - SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } -#if defined(USART_ISR_REACK) - /* Check if the Receiver is enabled */ - if ((hsmartcard->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if (SMARTCARD_WaitOnFlagUntilTimeout(hsmartcard, USART_ISR_REACK, RESET, tickstart, - SMARTCARD_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } -#endif /* USART_ISR_REACK */ - - /* Initialize the SMARTCARD states */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - return HAL_OK; -} - -/** - * @brief Handle SMARTCARD Communication Timeout. It waits - * until a flag is no longer in the specified status. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param Flag Specifies the SMARTCARD flag to check. - * @param Status The actual Flag status (SET or RESET). - * @param Tickstart Tick start value - * @param Timeout Timeout duration. - * @retval HAL status - */ -static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Flag, - FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while ((__HAL_SMARTCARD_GET_FLAG(hsmartcard, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - - -/** - * @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable TXEIE, TCIE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* At end of Tx process, restore hsmartcard->gState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; -} - - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* At end of Rx process, restore hsmartcard->RxState to Ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; -} - - -/** - * @brief DMA SMARTCARD transmit process complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - hsmartcard->TxXferCount = 0U; - - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the SMARTCARD associated USART CR3 register */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAT); - - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); -} - -/** - * @brief DMA SMARTCARD receive process complete callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - hsmartcard->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the SMARTCARD associated USART CR3 register */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore hsmartcard->RxState to Ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Rx complete callback */ - hsmartcard->RxCpltCallback(hsmartcard); -#else - /* Call legacy weak Rx complete callback */ - HAL_SMARTCARD_RxCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ -} - -/** - * @brief DMA SMARTCARD communication error callback. - * @param hdma Pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - - /* Stop SMARTCARD DMA Tx request if ongoing */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - { - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAT)) - { - hsmartcard->TxXferCount = 0U; - SMARTCARD_EndTxTransfer(hsmartcard); - } - } - - /* Stop SMARTCARD DMA Rx request if ongoing */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) - { - if (HAL_IS_BIT_SET(hsmartcard->Instance->CR3, USART_CR3_DMAR)) - { - hsmartcard->RxXferCount = 0U; - SMARTCARD_EndRxTransfer(hsmartcard); - } - } - - hsmartcard->ErrorCode |= HAL_SMARTCARD_ERROR_DMA; -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hsmartcard->ErrorCallback(hsmartcard); -#else - /* Call legacy weak user error callback */ - HAL_SMARTCARD_ErrorCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ -} - -/** - * @brief DMA SMARTCARD communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void SMARTCARD_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - hsmartcard->RxXferCount = 0U; - hsmartcard->TxXferCount = 0U; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered user error callback */ - hsmartcard->ErrorCallback(hsmartcard); -#else - /* Call legacy weak user error callback */ - HAL_SMARTCARD_ErrorCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ -} - -/** - * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void SMARTCARD_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - - hsmartcard->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (hsmartcard->hdmarx != NULL) - { - if (hsmartcard->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hsmartcard->TxXferCount = 0U; - hsmartcard->RxXferCount = 0U; - - /* Reset errorCode */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | - SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - - /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - hsmartcard->AbortCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort complete callback */ - HAL_SMARTCARD_AbortCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ -} - - -/** - * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void SMARTCARD_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - - hsmartcard->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (hsmartcard->hdmatx != NULL) - { - if (hsmartcard->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - hsmartcard->TxXferCount = 0U; - hsmartcard->RxXferCount = 0U; - - /* Reset errorCode */ - hsmartcard->ErrorCode = HAL_SMARTCARD_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | - SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - - /* Restore hsmartcard->gState and hsmartcard->RxState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - hsmartcard->AbortCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort complete callback */ - HAL_SMARTCARD_AbortCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ -} - - -/** - * @brief DMA SMARTCARD Tx communication abort callback, when initiated by user by a call to - * HAL_SMARTCARD_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void SMARTCARD_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - - hsmartcard->TxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, SMARTCARD_CLEAR_FEF); - - /* Restore hsmartcard->gState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - hsmartcard->AbortTransmitCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_SMARTCARD_AbortTransmitCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ -} - -/** - * @brief DMA SMARTCARD Rx communication abort callback, when initiated by user by a call to - * HAL_SMARTCARD_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void SMARTCARD_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - SMARTCARD_HandleTypeDef *hsmartcard = (SMARTCARD_HandleTypeDef *)(hdma->Parent); - - hsmartcard->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_SMARTCARD_CLEAR_FLAG(hsmartcard, - SMARTCARD_CLEAR_OREF | SMARTCARD_CLEAR_NEF | SMARTCARD_CLEAR_PEF | SMARTCARD_CLEAR_FEF | - SMARTCARD_CLEAR_RTOF | SMARTCARD_CLEAR_EOBF); - - /* Restore hsmartcard->RxState to Ready */ - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - hsmartcard->AbortReceiveCpltCallback(hsmartcard); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_SMARTCARD_AbortReceiveCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ -} - -/** - * @brief Send an amount of data in non-blocking mode. - * @note Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT(). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -static void SMARTCARD_TxISR(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Check that a Tx process is ongoing */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_BUSY_TX) - { - if (hsmartcard->TxXferCount == 0U) - { - /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_TXEIE); - - /* Enable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_ENABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); - } - else - { - hsmartcard->Instance->TDR = (uint8_t)(*hsmartcard->pTxBuffPtr & 0xFFU); - hsmartcard->pTxBuffPtr++; - hsmartcard->TxXferCount--; - } - } -} - -/** - * @brief Wrap up transmission in non-blocking mode. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -static void SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Disable the SMARTCARD Transmit Complete Interrupt */ - __HAL_SMARTCARD_DISABLE_IT(hsmartcard, hsmartcard->AdvancedInit.TxCompletionIndication); - - /* Check if a receive process is ongoing or not. If not disable ERR IT */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_READY) - { - /* Disable the SMARTCARD Error Interrupt: (Frame error) */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - } - - /* Disable the Peripheral first to update mode */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX) - && (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) - { - /* In case of TX only mode, if NACK is enabled, receiver block has been enabled - for Transmit phase. Disable this receiver block. */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RE); - } - if ((hsmartcard->Init.Mode == SMARTCARD_MODE_TX_RX) - || (hsmartcard->Init.NACKEnable == SMARTCARD_NACK_ENABLE)) - { - /* Perform a TX FIFO Flush at end of Tx phase, as all sent bytes are appearing in Rx Data register */ - __HAL_SMARTCARD_FLUSH_DRREGISTER(hsmartcard); - } - SET_BIT(hsmartcard->Instance->CR1, USART_CR1_UE); - - /* Tx process is ended, restore hsmartcard->gState to Ready */ - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - - /* Clear TxISR function pointer */ - hsmartcard->TxISR = NULL; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Tx complete callback */ - hsmartcard->TxCpltCallback(hsmartcard); -#else - /* Call legacy weak Tx complete callback */ - HAL_SMARTCARD_TxCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ -} - -/** - * @brief Receive an amount of data in non-blocking mode. - * @note Function called under interruption only, once - * interruptions have been enabled by HAL_SMARTCARD_Receive_IT(). - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval None - */ -static void SMARTCARD_RxISR(SMARTCARD_HandleTypeDef *hsmartcard) -{ - /* Check that a Rx process is ongoing */ - if (hsmartcard->RxState == HAL_SMARTCARD_STATE_BUSY_RX) - { - *hsmartcard->pRxBuffPtr = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0xFF); - hsmartcard->pRxBuffPtr++; - - hsmartcard->RxXferCount--; - if (hsmartcard->RxXferCount == 0U) - { - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_RXNEIE); - - /* Check if a transmit process is ongoing or not. If not disable ERR IT */ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(hsmartcard->Instance->CR3, USART_CR3_EIE); - } - - /* Disable the SMARTCARD Parity Error Interrupt */ - CLEAR_BIT(hsmartcard->Instance->CR1, USART_CR1_PEIE); - - hsmartcard->RxState = HAL_SMARTCARD_STATE_READY; - - /* Clear RxISR function pointer */ - hsmartcard->RxISR = NULL; - -#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) - /* Call registered Rx complete callback */ - hsmartcard->RxCpltCallback(hsmartcard); -#else - /* Call legacy weak Rx complete callback */ - HAL_SMARTCARD_RxCpltCallback(hsmartcard); -#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACK */ - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_SMARTCARD_SEND_REQ(hsmartcard, SMARTCARD_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @} - */ - -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c deleted file mode 100644 index 4bd42abd..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smartcard_ex.c +++ /dev/null @@ -1,197 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_smartcard_ex.c - * @author MCD Application Team - * @brief SMARTCARD HAL module driver. - * This file provides extended firmware functions to manage the following - * functionalities of the SmartCard. - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================= - ##### SMARTCARD peripheral extended features ##### - ============================================================================= - [..] - The Extended SMARTCARD HAL driver can be used as follows: - - (#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(), - then program SMARTCARD advanced features if required (TX/RX pins swap, TimeOut, - auto-retry counter,...) in the hsmartcard AdvancedInit structure. - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SMARTCARDEx SMARTCARDEx - * @brief SMARTCARD Extended HAL module driver - * @{ - */ -#ifdef HAL_SMARTCARD_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported Functions - * @{ - */ - -/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the SMARTCARD. - (+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly - (+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly - (+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature - (+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature - -@endverbatim - * @{ - */ - -/** @brief Update on the fly the SMARTCARD block length in RTOR register. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param BlockLength SMARTCARD block length (8-bit long at most) - * @retval None - */ -void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength) -{ - MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << USART_RTOR_BLEN_Pos)); -} - -/** @brief Update on the fly the receiver timeout value in RTOR register. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout - * value must be less or equal to 0x0FFFFFFFF. - * @retval None - */ -void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue) -{ - assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsmartcard->Init.TimeOutValue)); - MODIFY_REG(hsmartcard->Instance->RTOR, USART_RTOR_RTO, TimeOutValue); -} - -/** @brief Enable the SMARTCARD receiver timeout feature. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) -{ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsmartcard); - - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - - /* Set the USART RTOEN bit */ - SET_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN); - - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** @brief Disable the SMARTCARD receiver timeout feature. - * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains - * the configuration information for the specified SMARTCARD module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard) -{ - if (hsmartcard->gState == HAL_SMARTCARD_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsmartcard); - - hsmartcard->gState = HAL_SMARTCARD_STATE_BUSY; - - /* Clear the USART RTOEN bit */ - CLEAR_BIT(hsmartcard->Instance->CR2, USART_CR2_RTOEN); - - hsmartcard->gState = HAL_SMARTCARD_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmartcard); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @} - */ - -/** @defgroup SMARTCARDEx_Exported_Functions_Group2 Extended Peripheral IO operation functions - * @brief SMARTCARD Transmit and Receive functions - * - * @{ - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** @defgroup SMARTCARDEx_Private_Functions SMARTCARD Extended Private Functions - * @{ - */ - -/** - * @} - */ - -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c deleted file mode 100644 index 9caddfcc..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_smbus.c +++ /dev/null @@ -1,2810 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_smbus.c - * @author MCD Application Team - * @brief SMBUS HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the System Management Bus (SMBus) peripheral, - * based on I2C principles of operation : - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SMBUS HAL driver can be used as follows: - - (#) Declare a SMBUS_HandleTypeDef handle structure, for example: - SMBUS_HandleTypeDef hsmbus; - - (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: - (##) Enable the SMBUSx interface clock - (##) SMBUS pins configuration - (+++) Enable the clock for the SMBUS GPIOs - (+++) Configure SMBUS pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SMBUSx interrupt priority - (+++) Enable the NVIC SMBUS IRQ Channel - - (#) Configure the Communication Clock Timing, Bus Timeout, Own Address1, Master Addressing mode, - Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, - Peripheral mode and Packet Error Check mode in the hsmbus Init structure. - - (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init() API: - (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. - - (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() - - (#) For SMBUS IO operations, only one mode of operations is available within this driver - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master/host SMBUS mode an amount of data in non-blocking mode - using HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() - (+) Receive in master/host SMBUS mode an amount of data in non-blocking mode - using HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() - (+) Abort a master/host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() - (++) The associated previous transfer callback is called at the end of abort process - (++) mean HAL_SMBUS_MasterTxCpltCallback() in case of previous state was master transmit - (++) mean HAL_SMBUS_MasterRxCpltCallback() in case of previous state was master receive - (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and users can - add their own code to check the Address Match Code and the transmission direction - request by master/host (Write/Read). - (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() - (+) Transmit in slave/device SMBUS mode an amount of data in non-blocking mode - using HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device SMBUS mode an amount of data in non-blocking mode - using HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using - HAL_SMBUS_EnableAlert_IT() or HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and users can - add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() - to check the Alert Error Code using function HAL_SMBUS_GetError() - (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() - (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_SMBUS_ErrorCallback() - to check the Error Code using function HAL_SMBUS_GetError() - - *** SMBUS HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in SMBUS HAL driver. - - (+) __HAL_SMBUS_ENABLE: Enable the SMBUS peripheral - (+) __HAL_SMBUS_DISABLE: Disable the SMBUS peripheral - (+) __HAL_SMBUS_GET_FLAG: Check whether the specified SMBUS flag is set or not - (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag - (+) __HAL_SMBUS_ENABLE_IT: Enable the specified SMBUS interrupt - (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt - - *** Callback registration *** - ============================================= - [..] - The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterAddrCallback() - to register an interrupt callback. - [..] - Function HAL_SMBUS_RegisterCallback() allows to register following callbacks: - (+) MasterTxCpltCallback : callback for Master transmission end of transfer. - (+) MasterRxCpltCallback : callback for Master reception end of transfer. - (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. - (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. - (+) ListenCpltCallback : callback for end of listen mode. - (+) ErrorCallback : callback for error detection. - (+) MspInitCallback : callback for Msp Init. - (+) MspDeInitCallback : callback for Msp DeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - [..] - For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback. - [..] - Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default - weak function. - HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) MasterTxCpltCallback : callback for Master transmission end of transfer. - (+) MasterRxCpltCallback : callback for Master reception end of transfer. - (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. - (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. - (+) ListenCpltCallback : callback for end of listen mode. - (+) ErrorCallback : callback for error detection. - (+) MspInitCallback : callback for Msp Init. - (+) MspDeInitCallback : callback for Msp DeInit. - [..] - For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback. - [..] - By default, after the HAL_SMBUS_Init() and when the state is HAL_I2C_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when - these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - [..] - Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() - or HAL_SMBUS_Init() function. - [..] - When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - [..] - (@) You can refer to the SMBUS HAL driver header file for more useful macros - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SMBUS SMBUS - * @brief SMBUS HAL module driver - * @{ - */ - -#ifdef HAL_SMBUS_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SMBUS_Private_Define SMBUS Private Constants - * @{ - */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFUL) /*!< SMBUS TIMING clear register Mask */ -#define HAL_TIMEOUT_ADDR (10000U) /*!< 10 s */ -#define HAL_TIMEOUT_BUSY (25U) /*!< 25 ms */ -#define HAL_TIMEOUT_DIR (25U) /*!< 25 ms */ -#define HAL_TIMEOUT_RXNE (25U) /*!< 25 ms */ -#define HAL_TIMEOUT_STOPF (25U) /*!< 25 ms */ -#define HAL_TIMEOUT_TC (25U) /*!< 25 ms */ -#define HAL_TIMEOUT_TCR (25U) /*!< 25 ms */ -#define HAL_TIMEOUT_TXIS (25U) /*!< 25 ms */ -#define MAX_NBYTE_SIZE 255U -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @{ - */ -/* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, - FlagStatus Status, uint32_t Timeout); - -/* Private functions for SMBUS transfer IRQ handler */ -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags); -static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus); - -/* Private functions to centralize the enable/disable of Interrupts */ -static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); -static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest); - -/* Private function to flush TXDR register */ -static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus); - -/* Private function to handle start, restart or stop a transfer */ -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, - uint32_t Mode, uint32_t Request); - -/* Private function to Convert Specific options */ -static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SMBUS_Exported_Functions SMBUS Exported Functions - * @{ - */ - -/** @defgroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the SMBUSx peripheral: - - (+) User must Implement HAL_SMBUS_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, IT and NVIC ). - - (+) Call the function HAL_SMBUS_Init() to configure the selected device with - the selected configuration: - (++) Clock Timing - (++) Bus Timeout - (++) Analog Filer mode - (++) Own Address 1 - (++) Addressing mode (Master, Slave) - (++) Dual Addressing mode - (++) Own Address 2 - (++) Own Address 2 Mask - (++) General call mode - (++) Nostretch mode - (++) Packet Error Check mode - (++) Peripheral mode - - - (+) Call the function HAL_SMBUS_DeInit() to restore the default configuration - of the selected SMBUSx peripheral. - - (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and - HAL_SMBUS_ConfigDigitalFilter(). - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the SMBUS according to the specified parameters - * in the SMBUS_InitTypeDef and initialize the associated handle. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) -{ - /* Check the SMBUS handle allocation */ - if (hsmbus == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - assert_param(IS_SMBUS_ANALOG_FILTER(hsmbus->Init.AnalogFilter)); - assert_param(IS_SMBUS_OWN_ADDRESS1(hsmbus->Init.OwnAddress1)); - assert_param(IS_SMBUS_ADDRESSING_MODE(hsmbus->Init.AddressingMode)); - assert_param(IS_SMBUS_DUAL_ADDRESS(hsmbus->Init.DualAddressMode)); - assert_param(IS_SMBUS_OWN_ADDRESS2(hsmbus->Init.OwnAddress2)); - assert_param(IS_SMBUS_OWN_ADDRESS2_MASK(hsmbus->Init.OwnAddress2Masks)); - assert_param(IS_SMBUS_GENERAL_CALL(hsmbus->Init.GeneralCallMode)); - assert_param(IS_SMBUS_NO_STRETCH(hsmbus->Init.NoStretchMode)); - assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode)); - assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode)); - - if (hsmbus->State == HAL_SMBUS_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsmbus->Lock = HAL_UNLOCKED; - -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ - hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ - hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ - hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ - hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ - hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ - hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ - - if (hsmbus->MspInitCallback == NULL) - { - hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - hsmbus->MspInitCallback(hsmbus); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_SMBUS_MspInit(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - - hsmbus->State = HAL_SMBUS_STATE_BUSY; - - /* Disable the selected SMBUS peripheral */ - __HAL_SMBUS_DISABLE(hsmbus); - - /*---------------------------- SMBUSx TIMINGR Configuration ------------------------*/ - /* Configure SMBUSx: Frequency range */ - hsmbus->Instance->TIMINGR = hsmbus->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- SMBUSx TIMEOUTR Configuration ------------------------*/ - /* Configure SMBUSx: Bus Timeout */ - hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TIMOUTEN; - hsmbus->Instance->TIMEOUTR &= ~I2C_TIMEOUTR_TEXTEN; - hsmbus->Instance->TIMEOUTR = hsmbus->Init.SMBusTimeout; - - /*---------------------------- SMBUSx OAR1 Configuration -----------------------*/ - /* Configure SMBUSx: Own Address1 and ack own address1 mode */ - hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - if (hsmbus->Init.OwnAddress1 != 0UL) - { - if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT) - { - hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1); - } - else /* SMBUS_ADDRESSINGMODE_10BIT */ - { - hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hsmbus->Init.OwnAddress1); - } - } - - /*---------------------------- SMBUSx CR2 Configuration ------------------------*/ - /* Configure SMBUSx: Addressing Master mode */ - if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT) - { - hsmbus->Instance->CR2 = (I2C_CR2_ADD10); - } - /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process) */ - /* AUTOEND and NACK bit will be manage during Transfer process */ - hsmbus->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- SMBUSx OAR2 Configuration -----------------------*/ - /* Configure SMBUSx: Dual mode and Own Address2 */ - hsmbus->Instance->OAR2 = (hsmbus->Init.DualAddressMode | hsmbus->Init.OwnAddress2 | \ - (hsmbus->Init.OwnAddress2Masks << 8U)); - - /*---------------------------- SMBUSx CR1 Configuration ------------------------*/ - /* Configure SMBUSx: Generalcall and NoStretch mode */ - hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | \ - hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | \ - hsmbus->Init.AnalogFilter); - - /* Enable Slave Byte Control only in case of Packet Error Check is enabled - and SMBUS Peripheral is set in Slave mode */ - if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && \ - ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ - (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))) - { - hsmbus->Instance->CR1 |= I2C_CR1_SBC; - } - - /* Enable the selected SMBUS peripheral */ - __HAL_SMBUS_ENABLE(hsmbus); - - hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the SMBUS peripheral. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) -{ - /* Check the SMBUS handle allocation */ - if (hsmbus == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - - hsmbus->State = HAL_SMBUS_STATE_BUSY; - - /* Disable the SMBUS Peripheral Clock */ - __HAL_SMBUS_DISABLE(hsmbus); - -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - if (hsmbus->MspDeInitCallback == NULL) - { - hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - hsmbus->MspDeInitCallback(hsmbus); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_SMBUS_MspDeInit(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - - hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - hsmbus->PreviousState = HAL_SMBUS_STATE_RESET; - hsmbus->State = HAL_SMBUS_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} - -/** - * @brief Initialize the SMBUS MSP. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -__weak void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the SMBUS MSP. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -__weak void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Configure Analog noise filter. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param AnalogFilter This parameter can be one of the following values: - * @arg @ref SMBUS_ANALOGFILTER_ENABLE - * @arg @ref SMBUS_ANALOGFILTER_DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter)); - - if (hsmbus->State == HAL_SMBUS_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsmbus); - - hsmbus->State = HAL_SMBUS_STATE_BUSY; - - /* Disable the selected SMBUS peripheral */ - __HAL_SMBUS_DISABLE(hsmbus); - - /* Reset ANOFF bit */ - hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hsmbus->Instance->CR1 |= AnalogFilter; - - __HAL_SMBUS_ENABLE(hsmbus); - - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure Digital noise filter. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter)); - - if (hsmbus->State == HAL_SMBUS_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsmbus); - - hsmbus->State = HAL_SMBUS_STATE_BUSY; - - /* Disable the selected SMBUS peripheral */ - __HAL_SMBUS_DISABLE(hsmbus); - - /* Get the old register value */ - tmpreg = hsmbus->Instance->CR1; - - /* Reset I2C DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos; - - /* Store the new register value */ - hsmbus->Instance->CR1 = tmpreg; - - __HAL_SMBUS_ENABLE(hsmbus); - - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User SMBUS Callback - * To be used instead of the weak predefined callback - * @note The HAL_SMBUS_RegisterCallback() may be called before HAL_SMBUS_Init() in - * HAL_SMBUS_STATE_RESET to register callbacks for HAL_SMBUS_MSPINIT_CB_ID and - * HAL_SMBUS_MSPDEINIT_CB_ID. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID - * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID - * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID - * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID - * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID - * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID - * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, - HAL_SMBUS_CallbackIDTypeDef CallbackID, - pSMBUS_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (HAL_SMBUS_STATE_READY == hsmbus->State) - { - switch (CallbackID) - { - case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : - hsmbus->MasterTxCpltCallback = pCallback; - break; - - case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : - hsmbus->MasterRxCpltCallback = pCallback; - break; - - case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : - hsmbus->SlaveTxCpltCallback = pCallback; - break; - - case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : - hsmbus->SlaveRxCpltCallback = pCallback; - break; - - case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : - hsmbus->ListenCpltCallback = pCallback; - break; - - case HAL_SMBUS_ERROR_CB_ID : - hsmbus->ErrorCallback = pCallback; - break; - - case HAL_SMBUS_MSPINIT_CB_ID : - hsmbus->MspInitCallback = pCallback; - break; - - case HAL_SMBUS_MSPDEINIT_CB_ID : - hsmbus->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SMBUS_STATE_RESET == hsmbus->State) - { - switch (CallbackID) - { - case HAL_SMBUS_MSPINIT_CB_ID : - hsmbus->MspInitCallback = pCallback; - break; - - case HAL_SMBUS_MSPDEINIT_CB_ID : - hsmbus->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an SMBUS Callback - * SMBUS callback is redirected to the weak predefined callback - * @note The HAL_SMBUS_UnRegisterCallback() may be called before HAL_SMBUS_Init() in - * HAL_SMBUS_STATE_RESET to un-register callbacks for HAL_SMBUS_MSPINIT_CB_ID and - * HAL_SMBUS_MSPDEINIT_CB_ID - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * This parameter can be one of the following values: - * @arg @ref HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID - * @arg @ref HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID - * @arg @ref HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID - * @arg @ref HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID - * @arg @ref HAL_SMBUS_LISTEN_COMPLETE_CB_ID Listen Complete callback ID - * @arg @ref HAL_SMBUS_ERROR_CB_ID Error callback ID - * @arg @ref HAL_SMBUS_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_SMBUS_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, - HAL_SMBUS_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_SMBUS_STATE_READY == hsmbus->State) - { - switch (CallbackID) - { - case HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID : - hsmbus->MasterTxCpltCallback = HAL_SMBUS_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ - break; - - case HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID : - hsmbus->MasterRxCpltCallback = HAL_SMBUS_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ - break; - - case HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID : - hsmbus->SlaveTxCpltCallback = HAL_SMBUS_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ - break; - - case HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID : - hsmbus->SlaveRxCpltCallback = HAL_SMBUS_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ - break; - - case HAL_SMBUS_LISTEN_COMPLETE_CB_ID : - hsmbus->ListenCpltCallback = HAL_SMBUS_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ - break; - - case HAL_SMBUS_ERROR_CB_ID : - hsmbus->ErrorCallback = HAL_SMBUS_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_SMBUS_MSPINIT_CB_ID : - hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_SMBUS_MSPDEINIT_CB_ID : - hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SMBUS_STATE_RESET == hsmbus->State) - { - switch (CallbackID) - { - case HAL_SMBUS_MSPINIT_CB_ID : - hsmbus->MspInitCallback = HAL_SMBUS_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_SMBUS_MSPDEINIT_CB_ID : - hsmbus->MspDeInitCallback = HAL_SMBUS_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Register the Slave Address Match SMBUS Callback - * To be used instead of the weak HAL_SMBUS_AddrCallback() predefined callback - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param pCallback pointer to the Address Match Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, - pSMBUS_AddrCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (HAL_SMBUS_STATE_READY == hsmbus->State) - { - hsmbus->AddrCallback = pCallback; - } - else - { - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief UnRegister the Slave Address Match SMBUS Callback - * Info Ready SMBUS Callback is redirected to the weak HAL_SMBUS_AddrCallback() predefined callback - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_SMBUS_STATE_READY == hsmbus->State) - { - hsmbus->AddrCallback = HAL_SMBUS_AddrCallback; /* Legacy weak AddrCallback */ - } - else - { - /* Update the error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup SMBUS_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SMBUS data - transfers. - - (#) Blocking mode function to check if device is ready for usage is : - (++) HAL_SMBUS_IsDeviceReady() - - (#) There is only one mode of transfer: - (++) Non-Blocking mode : The communication is performed using Interrupts. - These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated SMBUS IRQ when using Interrupt mode. - - (#) Non-Blocking mode functions with Interrupt are : - (++) HAL_SMBUS_Master_Transmit_IT() - (++) HAL_SMBUS_Master_Receive_IT() - (++) HAL_SMBUS_Slave_Transmit_IT() - (++) HAL_SMBUS_Slave_Receive_IT() - (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT() - (++) HAL_SMBUS_DisableListen_IT() - (++) HAL_SMBUS_EnableAlert_IT() - (++) HAL_SMBUS_DisableAlert_IT() - - (#) A set of Transfer Complete Callbacks are provided in non-Blocking mode: - (++) HAL_SMBUS_MasterTxCpltCallback() - (++) HAL_SMBUS_MasterRxCpltCallback() - (++) HAL_SMBUS_SlaveTxCpltCallback() - (++) HAL_SMBUS_SlaveRxCpltCallback() - (++) HAL_SMBUS_AddrCallback() - (++) HAL_SMBUS_ListenCpltCallback() - (++) HAL_SMBUS_ErrorCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, - uint8_t *pData, uint16_t Size, uint32_t XferOptions) -{ - uint32_t tmp; - uint32_t sizetoxfer; - - /* Check the parameters */ - assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hsmbus->State == HAL_SMBUS_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsmbus); - - hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; - hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - /* Prepare transfer parameters */ - hsmbus->pBuffPtr = pData; - hsmbus->XferCount = Size; - hsmbus->XferOptions = XferOptions; - - /* In case of Quick command, remove autoend mode */ - /* Manage the stop generation by software */ - if (hsmbus->pBuffPtr == NULL) - { - hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; - } - - if (Size > MAX_NBYTE_SIZE) - { - hsmbus->XferSize = MAX_NBYTE_SIZE; - } - else - { - hsmbus->XferSize = Size; - } - - sizetoxfer = hsmbus->XferSize; - if ((sizetoxfer > 0U) && ((XferOptions == SMBUS_FIRST_FRAME) || - (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || - (XferOptions == SMBUS_FIRST_FRAME_WITH_PEC) || - (XferOptions == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) - { - if (hsmbus->pBuffPtr != NULL) - { - /* Preload TX register */ - /* Write data to TXDR */ - hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; - - /* Increment Buffer pointer */ - hsmbus->pBuffPtr++; - - hsmbus->XferCount--; - hsmbus->XferSize--; - } - else - { - return HAL_ERROR; - } - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((sizetoxfer < hsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE)) - { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), - SMBUS_GENERATE_START_WRITE); - } - else - { - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - - /* Store current volatile XferOptions, misra rule */ - tmp = hsmbus->XferOptions; - - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && \ - (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) - { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, hsmbus->XferOptions, - SMBUS_NO_STARTSTOP); - } - /* Else transfer direction change, so generate Restart with new transfer direction */ - else - { - /* Convert OTHER_xxx XferOptions if any */ - SMBUS_ConvertOtherXferOptions(hsmbus); - - /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)sizetoxfer, - hsmbus->XferOptions, - SMBUS_GENERATE_START_WRITE); - } - - /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ - /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) - { - if (hsmbus->XferSize > 0U) - { - hsmbus->XferSize--; - hsmbus->XferCount--; - } - else - { - return HAL_ERROR; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Note : The SMBUS interrupts must be enabled after unlocking current process - to avoid the risk of SMBUS interrupt handle execution before current - process unlock */ - SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hsmbus->State == HAL_SMBUS_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsmbus); - - hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; - hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - - /* Prepare transfer parameters */ - hsmbus->pBuffPtr = pData; - hsmbus->XferCount = Size; - hsmbus->XferOptions = XferOptions; - - /* In case of Quick command, remove autoend mode */ - /* Manage the stop generation by software */ - if (hsmbus->pBuffPtr == NULL) - { - hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; - } - - if (Size > MAX_NBYTE_SIZE) - { - hsmbus->XferSize = MAX_NBYTE_SIZE; - } - else - { - hsmbus->XferSize = Size; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) - { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), - SMBUS_GENERATE_START_READ); - } - else - { - /* If transfer direction not change, do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - - /* Store current volatile XferOptions, Misra rule */ - tmp = hsmbus->XferOptions; - - if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && \ - (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) - { - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, - SMBUS_NO_STARTSTOP); - } - /* Else transfer direction change, so generate Restart with new transfer direction */ - else - { - /* Convert OTHER_xxx XferOptions if any */ - SMBUS_ConvertOtherXferOptions(hsmbus); - - /* Handle Transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, - hsmbus->XferOptions, - SMBUS_GENERATE_START_READ); - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Note : The SMBUS interrupts must be enabled after unlocking current process - to avoid the risk of SMBUS interrupt handle execution before current - process unlock */ - SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master/host SMBUS process communication with Interrupt. - * @note This abort can be called only if state is ready - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress) -{ - if (hsmbus->State == HAL_SMBUS_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsmbus); - - /* Keep the same state as previous */ - /* to perform as well the call of the corresponding end of transfer callback */ - if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) - { - hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX; - } - else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) - { - hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } - hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - - /* Set NBYTES to 1 to generate a dummy read on SMBUS peripheral */ - /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - SMBUS_TransferConfig(hsmbus, DevAddress, 1, SMBUS_AUTOEND_MODE, SMBUS_NO_STARTSTOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Note : The SMBUS interrupts must be enabled after unlocking current process - to avoid the risk of SMBUS interrupt handle execution before current - process unlock */ - if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) - { - SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX); - } - else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) - { - SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX); - } - else - { - /* Nothing to do */ - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0UL)) - { - hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_TX); - - /* Process Locked */ - __HAL_LOCK(hsmbus); - - hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_TX | HAL_SMBUS_STATE_LISTEN); - hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - - /* Set SBC bit to manage Acknowledge at each bit */ - hsmbus->Instance->CR1 |= I2C_CR1_SBC; - - /* Enable Address Acknowledge */ - hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hsmbus->pBuffPtr = pData; - hsmbus->XferCount = Size; - hsmbus->XferOptions = XferOptions; - - /* Convert OTHER_xxx XferOptions if any */ - SMBUS_ConvertOtherXferOptions(hsmbus); - - if (Size > MAX_NBYTE_SIZE) - { - hsmbus->XferSize = MAX_NBYTE_SIZE; - } - else - { - hsmbus->XferSize = Size; - } - - /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hsmbus->XferSize < hsmbus->XferCount) && (hsmbus->XferSize == MAX_NBYTE_SIZE)) - { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), - SMBUS_NO_STARTSTOP); - } - else - { - /* Set NBYTE to transmit */ - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, - SMBUS_NO_STARTSTOP); - - /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ - /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) - { - hsmbus->XferSize--; - hsmbus->XferCount--; - } - } - - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Note : The SMBUS interrupts must be enabled after unlocking current process - to avoid the risk of SMBUS interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX | SMBUS_IT_ADDR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave/device SMBUS mode an amount of data in non-blocking mode with Interrupt. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Check the parameters */ - assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0UL)) - { - hsmbus->ErrorCode = HAL_SMBUS_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR | SMBUS_IT_RX); - - /* Process Locked */ - __HAL_LOCK(hsmbus); - - hsmbus->State = (HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_LISTEN); - hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - - /* Set SBC bit to manage Acknowledge at each bit */ - hsmbus->Instance->CR1 |= I2C_CR1_SBC; - - /* Enable Address Acknowledge */ - hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hsmbus->pBuffPtr = pData; - hsmbus->XferSize = Size; - hsmbus->XferCount = Size; - hsmbus->XferOptions = XferOptions; - - /* Convert OTHER_xxx XferOptions if any */ - SMBUS_ConvertOtherXferOptions(hsmbus); - - /* Set NBYTE to receive */ - /* If XferSize equal "1", or XferSize equal "2" with PEC requested (mean 1 data byte + 1 PEC byte */ - /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ - /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ - /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if (((SMBUS_GET_PEC_MODE(hsmbus) != 0UL) && (hsmbus->XferSize == 2U)) || (hsmbus->XferSize == 1U)) - { - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, - SMBUS_NO_STARTSTOP); - } - else - { - SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions | SMBUS_RELOAD_MODE, SMBUS_NO_STARTSTOP); - } - - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the HOST */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Note : The SMBUS interrupts must be enabled after unlocking current process - to avoid the risk of SMBUS interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_ADDR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus) -{ - hsmbus->State = HAL_SMBUS_STATE_LISTEN; - - /* Enable the Address Match interrupt */ - SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ADDR); - - return HAL_OK; -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus) -{ - /* Disable Address listen mode only if a transfer is not ongoing */ - if (hsmbus->State == HAL_SMBUS_STATE_LISTEN) - { - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Disable the Address Match interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable the SMBUS alert mode with Interrupt. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUSx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus) -{ - /* Enable SMBus alert */ - hsmbus->Instance->CR1 |= I2C_CR1_ALERTEN; - - /* Clear ALERT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); - - /* Enable Alert Interrupt */ - SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_ALERT); - - return HAL_OK; -} -/** - * @brief Disable the SMBUS alert mode with Interrupt. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUSx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus) -{ - /* Enable SMBus alert */ - hsmbus->Instance->CR1 &= ~I2C_CR1_ALERTEN; - - /* Disable Alert Interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ALERT); - - return HAL_OK; -} - -/** - * @brief Check if target device is ready for communication. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param Trials Number of trials - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout) -{ - uint32_t tickstart; - - __IO uint32_t SMBUS_Trials = 0UL; - - FlagStatus tmp1; - FlagStatus tmp2; - - if (hsmbus->State == HAL_SMBUS_STATE_READY) - { - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hsmbus); - - hsmbus->State = HAL_SMBUS_STATE_BUSY; - hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; - - do - { - /* Generate Start */ - hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - tickstart = HAL_GetTick(); - - tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); - tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); - - while ((tmp1 == RESET) && (tmp2 == RESET)) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - /* Device is ready */ - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Update SMBUS error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - return HAL_ERROR; - } - } - - tmp1 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF); - tmp2 = __HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF); - } - - /* Check if the NACKF flag has not been set */ - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) - { - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - - /* Device is ready */ - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; - } - else - { - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear NACK Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (SMBUS_Trials == Trials) - { - /* Generate Stop */ - hsmbus->Instance->CR2 |= I2C_CR2_STOP; - - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - - /* Increment Trials */ - SMBUS_Trials++; - } while (SMBUS_Trials < Trials); - - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Update SMBUS error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_ERROR; - } - else - { - return HAL_BUSY; - } -} -/** - * @} - */ - -/** @defgroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief Handle SMBUS event interrupt request. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus) -{ - /* Use a local variable to store the current ISR flags */ - /* This action will avoid a wrong treatment due to ISR flags change during interrupt handler */ - uint32_t tmpisrvalue = READ_REG(hsmbus->Instance->ISR); - uint32_t tmpcr1value = READ_REG(hsmbus->Instance->CR1); - - /* SMBUS in mode Transmitter ---------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | - SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET) && - ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) - { - /* Slave mode selected */ - if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - { - (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); - } - /* Master mode selected */ - else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX) - { - (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); - } - else - { - /* Nothing to do */ - } - } - - /* SMBUS in mode Receiver ----------------------------------------------------*/ - if ((SMBUS_CHECK_IT_SOURCE(tmpcr1value, (SMBUS_IT_TCI | SMBUS_IT_STOPI | - SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET) && - ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) - { - /* Slave mode selected */ - if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) - { - (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); - } - /* Master mode selected */ - else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX) - { - (void)SMBUS_Master_ISR(hsmbus, tmpisrvalue); - } - else - { - /* Nothing to do */ - } - } - - /* SMBUS in mode Listener Only --------------------------------------------------*/ - if (((SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_ADDRI) != RESET) || - (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_STOPI) != RESET) || - (SMBUS_CHECK_IT_SOURCE(tmpcr1value, SMBUS_IT_NACKI) != RESET)) && - ((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || - (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))) - { - if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) - { - (void)SMBUS_Slave_ISR(hsmbus, tmpisrvalue); - } - } -} - -/** - * @brief Handle SMBUS error interrupt request. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) -{ - SMBUS_ITErrorHandler(hsmbus); -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -__weak void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_MasterTxCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -__weak void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_MasterRxCpltCallback() could be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -__weak void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_SlaveTxCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -__weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_SlaveRxCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param TransferDirection Master request Transfer Direction (Write/Read) - * @param AddrMatchCode Address Match Code - * @retval None - */ -__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, - uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_AddrCallback() could be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -__weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_ListenCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief SMBUS error callback. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval None - */ -__weak void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsmbus); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SMBUS_ErrorCallback() could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State and Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the SMBUS handle state. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval HAL state - */ -uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus) -{ - /* Return SMBUS handle state */ - return hsmbus->State; -} - -/** - * @brief Return the SMBUS error code. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @retval SMBUS Error Code - */ -uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus) -{ - return hsmbus->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup SMBUS_Private_Functions SMBUS Private Functions - * @brief Data transfers Private functions - * @{ - */ - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param StatusFlags Value of Interrupt Flags. - * @retval HAL status - */ -static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) -{ - uint16_t DevAddress; - - /* Process Locked */ - __HAL_LOCK(hsmbus); - - if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; - - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to inform upper layer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->ErrorCallback(hsmbus); -#else - HAL_SMBUS_ErrorCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) - { - /* Check and treat errors if errors occurs during STOP process */ - SMBUS_ITErrorHandler(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) - { - /* Disable Interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - SMBUS_RESET_CR2(hsmbus); - - /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ - /* Disable the selected SMBUS peripheral */ - __HAL_SMBUS_DISABLE(hsmbus); - - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Re-enable the selected SMBUS peripheral */ - __HAL_SMBUS_ENABLE(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->MasterTxCpltCallback(hsmbus); -#else - HAL_SMBUS_MasterTxCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) - { - /* Store Last receive data if any */ - if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) - { - /* Read data from RXDR */ - *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); - - /* Increment Buffer pointer */ - hsmbus->pBuffPtr++; - - if ((hsmbus->XferSize > 0U)) - { - hsmbus->XferSize--; - hsmbus->XferCount--; - } - } - - /* Disable Interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - SMBUS_RESET_CR2(hsmbus); - - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->MasterRxCpltCallback(hsmbus); -#else - HAL_SMBUS_MasterRxCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } - } - else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) - { - /* Read data from RXDR */ - *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); - - /* Increment Buffer pointer */ - hsmbus->pBuffPtr++; - - /* Increment Size counter */ - hsmbus->XferSize--; - hsmbus->XferCount--; - } - else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) - { - /* Write data to TXDR */ - hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; - - /* Increment Buffer pointer */ - hsmbus->pBuffPtr++; - - /* Increment Size counter */ - hsmbus->XferSize--; - hsmbus->XferCount--; - } - else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET) - { - if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) - { - DevAddress = (uint16_t)(hsmbus->Instance->CR2 & I2C_CR2_SADD); - - if (hsmbus->XferCount > MAX_NBYTE_SIZE) - { - SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, - (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), - SMBUS_NO_STARTSTOP); - hsmbus->XferSize = MAX_NBYTE_SIZE; - } - else - { - hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, DevAddress, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, - SMBUS_NO_STARTSTOP); - /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ - /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) - { - hsmbus->XferSize--; - hsmbus->XferCount--; - } - } - } - else if ((hsmbus->XferCount == 0U) && (hsmbus->XferSize == 0U)) - { - /* Call TxCpltCallback() if no stop mode is set */ - if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) - { - /* Disable Interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->MasterTxCpltCallback(hsmbus); -#else - HAL_SMBUS_MasterTxCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) - { - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->MasterRxCpltCallback(hsmbus); -#else - HAL_SMBUS_MasterRxCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } - } - } - else - { - /* Nothing to do */ - } - } - else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TC) != RESET) - { - if (hsmbus->XferCount == 0U) - { - /* Specific use case for Quick command */ - if (hsmbus->pBuffPtr == NULL) - { - /* Generate a Stop command */ - hsmbus->Instance->CR2 |= I2C_CR2_STOP; - } - /* Call TxCpltCallback() if no stop mode is set */ - else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) - { - /* No Generate Stop, to permit restart mode */ - /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) - { - /* Disable Interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->MasterTxCpltCallback(hsmbus); -#else - HAL_SMBUS_MasterTxCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX) - { - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->MasterRxCpltCallback(hsmbus); -#else - HAL_SMBUS_MasterRxCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } - } - else - { - /* Nothing to do */ - } - } - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param StatusFlags Value of Interrupt Flags. - * @retval HAL status - */ -static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t StatusFlags) -{ - uint8_t TransferDirection; - uint16_t SlaveAddrCode; - - /* Process Locked */ - __HAL_LOCK(hsmbus); - - if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_AF) != RESET) - { - /* Check that SMBUS transfer finished */ - /* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hsmbus->XferCount == 0U) - { - /* Clear NACK Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - } - else - { - /* if no, error usecase, a Non-Acknowledge of last Data is generated by the HOST*/ - /* Clear NACK Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - - /* Set HAL State to "Idle" State, mean to LISTEN state */ - /* So reset Slave Busy state */ - hsmbus->PreviousState = hsmbus->State; - hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); - hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); - - /* Disable RX/TX Interrupts, keep only ADDR Interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ACKF; - - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the Error callback to inform upper layer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->ErrorCallback(hsmbus); -#else - HAL_SMBUS_ErrorCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - } - else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_ADDR) != RESET) - { - TransferDirection = (uint8_t)(SMBUS_GET_DIR(hsmbus)); - SlaveAddrCode = (uint16_t)(SMBUS_GET_ADDR_MATCH(hsmbus)); - - /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ - /* Other ADDRInterrupt will be treat in next Listen usecase */ - __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_ADDRI); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call Slave Addr callback */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); -#else - HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else if ((SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_RXNE) != RESET) || - (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TCR) != RESET)) - { - if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX) - { - /* Read data from RXDR */ - *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); - - /* Increment Buffer pointer */ - hsmbus->pBuffPtr++; - - hsmbus->XferSize--; - hsmbus->XferCount--; - - if (hsmbus->XferCount == 1U) - { - /* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */ - /* or only the last Byte of Transfer */ - /* So reset the RELOAD bit mode */ - hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE; - SMBUS_TransferConfig(hsmbus, 0, 1, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); - } - else if (hsmbus->XferCount == 0U) - { - /* Last Byte is received, disable Interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - - /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ - hsmbus->PreviousState = hsmbus->State; - hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->SlaveRxCpltCallback(hsmbus); -#else - HAL_SMBUS_SlaveRxCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - else - { - /* Set Reload for next Bytes */ - SMBUS_TransferConfig(hsmbus, 0, 1, - SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), - SMBUS_NO_STARTSTOP); - - /* Ack last Byte Read */ - hsmbus->Instance->CR2 &= ~I2C_CR2_NACK; - } - } - else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - { - if ((hsmbus->XferCount != 0U) && (hsmbus->XferSize == 0U)) - { - if (hsmbus->XferCount > MAX_NBYTE_SIZE) - { - SMBUS_TransferConfig(hsmbus, 0, MAX_NBYTE_SIZE, - (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), - SMBUS_NO_STARTSTOP); - hsmbus->XferSize = MAX_NBYTE_SIZE; - } - else - { - hsmbus->XferSize = hsmbus->XferCount; - SMBUS_TransferConfig(hsmbus, 0, (uint8_t)hsmbus->XferSize, hsmbus->XferOptions, - SMBUS_NO_STARTSTOP); - /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ - /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if (SMBUS_GET_PEC_MODE(hsmbus) != 0UL) - { - hsmbus->XferSize--; - hsmbus->XferCount--; - } - } - } - } - else - { - /* Nothing to do */ - } - } - else if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_TXIS) != RESET) - { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Data have already been sent */ - /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if (hsmbus->XferCount > 0U) - { - /* Write data to TXDR */ - hsmbus->Instance->TXDR = *hsmbus->pBuffPtr; - - /* Increment Buffer pointer */ - hsmbus->pBuffPtr++; - - hsmbus->XferCount--; - hsmbus->XferSize--; - } - - if (hsmbus->XferCount == 0U) - { - /* Last Byte is Transmitted */ - /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); - hsmbus->PreviousState = hsmbus->State; - hsmbus->State &= ~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->SlaveTxCpltCallback(hsmbus); -#else - HAL_SMBUS_SlaveTxCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - } - else - { - /* Nothing to do */ - } - - /* Check if STOPF is set */ - if (SMBUS_CHECK_FLAG(StatusFlags, SMBUS_FLAG_STOPF) != RESET) - { - if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN) - { - /* Store Last receive data if any */ - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) - { - /* Read data from RXDR */ - *hsmbus->pBuffPtr = (uint8_t)(hsmbus->Instance->RXDR); - - /* Increment Buffer pointer */ - hsmbus->pBuffPtr++; - - if ((hsmbus->XferSize > 0U)) - { - hsmbus->XferSize--; - hsmbus->XferCount--; - } - } - - /* Disable RX and TX Interrupts */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX | SMBUS_IT_TX); - - /* Disable ADDR Interrupt */ - SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_ADDR); - - /* Disable Address Acknowledge */ - hsmbus->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear Configuration Register 2 */ - SMBUS_RESET_CR2(hsmbus); - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - - /* Clear ADDR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR); - - hsmbus->XferOptions = 0; - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->ListenCpltCallback(hsmbus); -#else - HAL_SMBUS_ListenCpltCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_OK; -} -/** - * @brief Manage the enabling of Interrupts. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. - * @retval HAL status - */ -static void SMBUS_Enable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) -{ - uint32_t tmpisr = 0UL; - - if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) - { - /* Enable ERR interrupt */ - tmpisr |= SMBUS_IT_ERRI; - } - - if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) - { - /* Enable ADDR, STOP interrupt */ - tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI; - } - - if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) - { - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI; - } - - if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) - { - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI; - } - - /* Enable interrupts only at the end */ - /* to avoid the risk of SMBUS interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_SMBUS_ENABLE_IT(hsmbus, tmpisr); -} -/** - * @brief Manage the disabling of Interrupts. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param InterruptRequest Value of @ref SMBUS_Interrupt_configuration_definition. - * @retval HAL status - */ -static void SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint32_t InterruptRequest) -{ - uint32_t tmpisr = 0UL; - uint32_t tmpstate = hsmbus->State; - - if ((tmpstate == HAL_SMBUS_STATE_READY) && ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)) - { - /* Disable ERR interrupt */ - tmpisr |= SMBUS_IT_ERRI; - } - - if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX) - { - /* Disable TC, STOP, NACK and TXI interrupt */ - tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - - if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) - && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) - { - /* Disable ERR interrupt */ - tmpisr |= SMBUS_IT_ERRI; - } - - if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) - { - /* Disable STOP and NACK interrupt */ - tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; - } - } - - if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX) - { - /* Disable TC, STOP, NACK and RXI interrupt */ - tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - - if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) - && ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) - { - /* Disable ERR interrupt */ - tmpisr |= SMBUS_IT_ERRI; - } - - if ((tmpstate & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN) - { - /* Disable STOP and NACK interrupt */ - tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI; - } - } - - if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR) - { - /* Disable ADDR, STOP and NACK interrupt */ - tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - - if (SMBUS_GET_ALERT_ENABLED(hsmbus) == 0UL) - { - /* Disable ERR interrupt */ - tmpisr |= SMBUS_IT_ERRI; - } - } - - /* Disable interrupts only at the end */ - /* to avoid a breaking situation like at "t" time */ - /* all disable interrupts request are not done */ - __HAL_SMBUS_DISABLE_IT(hsmbus, tmpisr); -} - -/** - * @brief SMBUS interrupts error handler. - * @param hsmbus SMBUS handle. - * @retval None - */ -static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus) -{ - uint32_t itflags = READ_REG(hsmbus->Instance->ISR); - uint32_t itsources = READ_REG(hsmbus->Instance->CR1); - uint32_t tmpstate; - uint32_t tmperror; - - /* SMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_BERR) == SMBUS_FLAG_BERR) && \ - ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR); - } - - /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & SMBUS_FLAG_OVR) == SMBUS_FLAG_OVR) && \ - ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR); - } - - /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & SMBUS_FLAG_ARLO) == SMBUS_FLAG_ARLO) && \ - ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO); - } - - /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & SMBUS_FLAG_TIMEOUT) == SMBUS_FLAG_TIMEOUT) && \ - ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT; - - /* Clear TIMEOUT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT); - } - - /* SMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & SMBUS_FLAG_ALERT) == SMBUS_FLAG_ALERT) && \ - ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT; - - /* Clear ALERT flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT); - } - - /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & SMBUS_FLAG_PECERR) == SMBUS_FLAG_PECERR) && \ - ((itsources & SMBUS_IT_ERRI) == SMBUS_IT_ERRI)) - { - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; - - /* Clear PEC error flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); - } - - if (hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) - { - /* Flush TX register */ - SMBUS_Flush_TXDR(hsmbus); - } - - /* Store current volatile hsmbus->ErrorCode, misra rule */ - tmperror = hsmbus->ErrorCode; - - /* Call the Error Callback in case of Error detected */ - if ((tmperror != HAL_SMBUS_ERROR_NONE) && (tmperror != HAL_SMBUS_ERROR_ACKF)) - { - /* Do not Reset the HAL state in case of ALERT error */ - if ((tmperror & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) - { - /* Store current volatile hsmbus->State, misra rule */ - tmpstate = hsmbus->State; - - if (((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX) - || ((tmpstate & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)) - { - /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */ - /* keep HAL_SMBUS_STATE_LISTEN if set */ - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; - hsmbus->State = HAL_SMBUS_STATE_LISTEN; - } - } - - /* Call the Error callback to inform upper layer */ -#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) - hsmbus->ErrorCallback(hsmbus); -#else - HAL_SMBUS_ErrorCallback(hsmbus); -#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Handle SMBUS Communication Timeout. - * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains - * the configuration information for the specified SMBUS. - * @param Flag Specifies the SMBUS flag to check. - * @param Status The new Flag status (SET or RESET). - * @param Timeout Timeout duration - * @retval HAL status - */ -static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, - FlagStatus Status, uint32_t Timeout) -{ - uint32_t tickstart = HAL_GetTick(); - - /* Wait until flag is set */ - while ((FlagStatus)(__HAL_SMBUS_GET_FLAG(hsmbus, Flag)) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - hsmbus->PreviousState = hsmbus->State; - hsmbus->State = HAL_SMBUS_STATE_READY; - - /* Update SMBUS error code */ - hsmbus->ErrorCode |= HAL_SMBUS_ERROR_HALTIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); - - return HAL_ERROR; - } - } - } - - return HAL_OK; -} - -/** - * @brief SMBUS Tx data register flush process. - * @param hsmbus SMBUS handle. - * @retval None - */ -static void SMBUS_Flush_TXDR(SMBUS_HandleTypeDef *hsmbus) -{ - /* If a pending TXIS flag is set */ - /* Write a dummy data in TXDR to clear it */ - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET) - { - hsmbus->Instance->TXDR = 0x00U; - } - - /* Flush TX register if not empty */ - if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXE) == RESET) - { - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TXE); - } -} - -/** - * @brief Handle SMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hsmbus SMBUS handle. - * @param DevAddress specifies the slave address to be programmed. - * @param Size specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param Mode New state of the SMBUS START condition generation. - * This parameter can be one or a combination of the following values: - * @arg @ref SMBUS_RELOAD_MODE Enable Reload mode. - * @arg @ref SMBUS_AUTOEND_MODE Enable Automatic end mode. - * @arg @ref SMBUS_SOFTEND_MODE Enable Software end mode and Reload mode. - * @arg @ref SMBUS_SENDPEC_MODE Enable Packet Error Calculation mode. - * @param Request New state of the SMBUS START condition generation. - * This parameter can be one of the following values: - * @arg @ref SMBUS_NO_STARTSTOP Don't Generate stop and start condition. - * @arg @ref SMBUS_GENERATE_STOP Generate stop condition (Size should be set to 0). - * @arg @ref SMBUS_GENERATE_START_READ Generate Restart for read request. - * @arg @ref SMBUS_GENERATE_START_WRITE Generate Restart for write request. - * @retval None - */ -static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, - uint32_t Mode, uint32_t Request) -{ - /* Check the parameters */ - assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance)); - assert_param(IS_SMBUS_TRANSFER_MODE(Mode)); - assert_param(IS_SMBUS_TRANSFER_REQUEST(Request)); - - /* update CR2 register */ - MODIFY_REG(hsmbus->Instance->CR2, - ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \ - (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request)); -} - -/** - * @brief Convert SMBUSx OTHER_xxx XferOptions to functional XferOptions. - * @param hsmbus SMBUS handle. - * @retval None - */ -static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus) -{ - /* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */ - /* it request implicitly to generate a restart condition */ - /* set XferOptions to SMBUS_FIRST_FRAME */ - if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC) - { - hsmbus->XferOptions = SMBUS_FIRST_FRAME; - } - /* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */ - /* it request implicitly to generate a restart condition */ - /* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */ - else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC) - { - hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE; - } - /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_NO_PEC */ - /* it request implicitly to generate a restart condition */ - /* then generate a stop condition at the end of transfer */ - /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */ - else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) - { - hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC; - } - /* else if user set XferOptions to SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC */ - /* it request implicitly to generate a restart condition */ - /* then generate a stop condition at the end of transfer */ - /* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */ - else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC) - { - hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC; - } - else - { - /* Nothing to do */ - } -} -/** - * @} - */ - -#endif /* HAL_SMBUS_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c deleted file mode 100644 index 42b789ba..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spdifrx.c +++ /dev/null @@ -1,1647 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_spdifrx.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the SPDIFRX audio interface: - * + Initialization and Configuration - * + Data transfers functions - * + DMA transfers management - * + Interrupts and flags management - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The SPDIFRX HAL driver can be used as follow: - - (#) Declare SPDIFRX_HandleTypeDef handle structure. - (#) Initialize the SPDIFRX low level resources by implement the HAL_SPDIFRX_MspInit() API: - (##) Enable the SPDIFRX interface clock. - (##) SPDIFRX pins configuration: - (+++) Enable the clock for the SPDIFRX GPIOs. - (+++) Configure these SPDIFRX pins as alternate function pull-up. - (##) NVIC configuration if you need to use interrupt process (HAL_SPDIFRX_ReceiveControlFlow_IT() and - HAL_SPDIFRX_ReceiveDataFlow_IT() API's). - (+++) Configure the SPDIFRX interrupt priority. - (+++) Enable the NVIC SPDIFRX IRQ handle. - (##) DMA Configuration if you need to use DMA process (HAL_SPDIFRX_ReceiveDataFlow_DMA() and - HAL_SPDIFRX_ReceiveControlFlow_DMA() API's). - (+++) Declare a DMA handle structure for the reception of the Data Flow channel. - (+++) Declare a DMA handle structure for the reception of the Control Flow channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure CtrlRx/DataRx with the required parameters. - (+++) Configure the DMA Channel. - (+++) Associate the initialized DMA handle to the SPDIFRX DMA CtrlRx/DataRx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA CtrlRx/DataRx channel. - - (#) Program the input selection, re-tries number, wait for activity, channel status selection, data format, - stereo mode and masking of user bits using HAL_SPDIFRX_Init() function. - - -@- The specific SPDIFRX interrupts (RXNE/CSRNE and Error Interrupts) will be managed using the macros - __SPDIFRX_ENABLE_IT() and __SPDIFRX_DISABLE_IT() inside the receive process. - -@- Make sure that ck_spdif clock is configured. - - (#) Three operation modes are available within this driver : - - *** Polling mode for reception operation (for debug purpose) *** - ================================================================ - [..] - (+) Receive data flow in blocking mode using HAL_SPDIFRX_ReceiveDataFlow() - (+) Receive control flow of data in blocking mode using HAL_SPDIFRX_ReceiveControlFlow() - - *** Interrupt mode for reception operation *** - ========================================= - [..] - (+) Receive an amount of data (Data Flow) in non blocking mode using HAL_SPDIFRX_ReceiveDataFlow_IT() - (+) Receive an amount of data (Control Flow) in non blocking mode using HAL_SPDIFRX_ReceiveControlFlow_IT() - (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback - (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback - (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback - - *** DMA mode for reception operation *** - ======================================== - [..] - (+) Receive an amount of data (Data Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveDataFlow_DMA() - (+) Receive an amount of data (Control Flow) in non blocking mode (DMA) using HAL_SPDIFRX_ReceiveControlFlow_DMA() - (+) At reception end of half transfer HAL_SPDIFRX_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_RxHalfCpltCallback - (+) At reception end of transfer HAL_SPDIFRX_RxCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_RxCpltCallback - (+) In case of transfer Error, HAL_SPDIFRX_ErrorCallback() function is executed and user can - add his own code by customization of function pointer HAL_SPDIFRX_ErrorCallback - (+) Stop the DMA Transfer using HAL_SPDIFRX_DMAStop() - - *** SPDIFRX HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in SPDIFRX HAL driver. - (+) __HAL_SPDIFRX_IDLE: Disable the specified SPDIFRX peripheral (IDLE State) - (+) __HAL_SPDIFRX_SYNC: Enable the synchronization state of the specified SPDIFRX peripheral (SYNC State) - (+) __HAL_SPDIFRX_RCV: Enable the receive state of the specified SPDIFRX peripheral (RCV State) - (+) __HAL_SPDIFRX_ENABLE_IT : Enable the specified SPDIFRX interrupts - (+) __HAL_SPDIFRX_DISABLE_IT : Disable the specified SPDIFRX interrupts - (+) __HAL_SPDIFRX_GET_FLAG: Check whether the specified SPDIFRX flag is set or not. - - [..] - (@) You can refer to the SPDIFRX HAL driver header file for more useful macros - - *** Callback registration *** - ============================================= - - The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use HAL_SPDIFRX_RegisterCallback() function to register an interrupt callback. - - The HAL_SPDIFRX_RegisterCallback() function allows to register the following callbacks: - (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback. - (+) RxCpltCallback : SPDIFRX Data flow completed callback. - (+) CxHalfCpltCallback : SPDIFRX Control flow half completed callback. - (+) CxCpltCallback : SPDIFRX Control flow completed callback. - (+) ErrorCallback : SPDIFRX error callback. - (+) MspInitCallback : SPDIFRX MspInit. - (+) MspDeInitCallback : SPDIFRX MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use HAL_SPDIFRX_UnRegisterCallback() function to reset a callback to the default - weak function. - The HAL_SPDIFRX_UnRegisterCallback() function takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset the following callbacks: - (+) RxHalfCpltCallback : SPDIFRX Data flow half completed callback. - (+) RxCpltCallback : SPDIFRX Data flow completed callback. - (+) CxHalfCpltCallback : SPDIFRX Control flow half completed callback. - (+) CxCpltCallback : SPDIFRX Control flow completed callback. - (+) ErrorCallback : SPDIFRX error callback. - (+) MspInitCallback : SPDIFRX MspInit. - (+) MspDeInitCallback : SPDIFRX MspDeInit. - - By default, after the HAL_SPDIFRX_Init() and when the state is HAL_SPDIFRX_STATE_RESET - all callbacks are set to the corresponding weak functions : - HAL_SPDIFRX_RxHalfCpltCallback() , HAL_SPDIFRX_RxCpltCallback(), HAL_SPDIFRX_CxHalfCpltCallback(), - HAL_SPDIFRX_CxCpltCallback() and HAL_SPDIFRX_ErrorCallback() - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_SPDIFRX_Init()/ HAL_SPDIFRX_DeInit() only when - these callbacks pointers are NULL (not registered beforehand). - If not, MspInit or MspDeInit callbacks pointers are not null, the HAL_SPDIFRX_Init() / HAL_SPDIFRX_DeInit() - keep and use the user MspInit/MspDeInit functions (registered beforehand) - - Callbacks can be registered/unregistered in HAL_SPDIFRX_STATE_READY state only. - Exception done MspInit/MspDeInit callbacks that can be registered/unregistered - in HAL_SPDIFRX_STATE_READY or HAL_SPDIFRX_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_SPDIFRX_RegisterCallback() before calling HAL_SPDIFRX_DeInit() - or HAL_SPDIFRX_Init() function. - - When The compilation define USE_HAL_SPDIFRX_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SPDIFRX SPDIFRX - * @brief SPDIFRX HAL module driver - * @{ - */ - -#ifdef HAL_SPDIFRX_MODULE_ENABLED -#if defined (SPDIFRX) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup SPDIFRX_Private_Defines SPDIFRX Private Defines - * @{ - */ -#define SPDIFRX_TIMEOUT_VALUE 10U -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SPDIFRX_Private_Functions - * @{ - */ -static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma); -static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma); -static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma); -static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma); -static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif); -static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif); -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, - FlagStatus Status, uint32_t Timeout, uint32_t tickstart); -/** - * @} - */ -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup SPDIFRX_Exported_Functions SPDIFRX Exported Functions - * @{ - */ - -/** @defgroup SPDIFRX_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the SPDIFRX peripheral: - - (+) User must Implement HAL_SPDIFRX_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_SPDIFRX_Init() to configure the SPDIFRX peripheral with - the selected configuration: - (++) Input Selection (IN0, IN1,...) - (++) Maximum allowed re-tries during synchronization phase - (++) Wait for activity on SPDIF selected input - (++) Channel status selection (from channel A or B) - (++) Data format (LSB, MSB, ...) - (++) Stereo mode - (++) User bits masking (PT,C,U,V,...) - - (+) Call the function HAL_SPDIFRX_DeInit() to restore the default configuration - of the selected SPDIFRXx peripheral. - @endverbatim - * @{ - */ - -/** - * @brief Initializes the SPDIFRX according to the specified parameters - * in the SPDIFRX_InitTypeDef and create the associated handle. - * @param hspdif SPDIFRX handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) -{ - uint32_t tmpreg; - - /* Check the SPDIFRX handle allocation */ - if (hspdif == NULL) - { - return HAL_ERROR; - } - - /* Check the SPDIFRX parameters */ - assert_param(IS_STEREO_MODE(hspdif->Init.StereoMode)); - assert_param(IS_SPDIFRX_INPUT_SELECT(hspdif->Init.InputSelection)); - assert_param(IS_SPDIFRX_MAX_RETRIES(hspdif->Init.Retries)); - assert_param(IS_SPDIFRX_WAIT_FOR_ACTIVITY(hspdif->Init.WaitForActivity)); - assert_param(IS_SPDIFRX_CHANNEL(hspdif->Init.ChannelSelection)); - assert_param(IS_SPDIFRX_DATA_FORMAT(hspdif->Init.DataFormat)); - assert_param(IS_PREAMBLE_TYPE_MASK(hspdif->Init.PreambleTypeMask)); - assert_param(IS_CHANNEL_STATUS_MASK(hspdif->Init.ChannelStatusMask)); - assert_param(IS_VALIDITY_MASK(hspdif->Init.ValidityBitMask)); - assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask)); - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - if (hspdif->State == HAL_SPDIFRX_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hspdif->Lock = HAL_UNLOCKED; - - hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback; /* Legacy weak CxHalfCpltCallback */ - hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; /* Legacy weak CxCpltCallback */ - hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; /* Legacy weak ErrorCallback */ - - if (hspdif->MspInitCallback == NULL) - { - hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hspdif->MspInitCallback(hspdif); - } -#else - if (hspdif->State == HAL_SPDIFRX_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hspdif->Lock = HAL_UNLOCKED; - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_SPDIFRX_MspInit(hspdif); - } -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - - /* SPDIFRX peripheral state is BUSY */ - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Disable SPDIFRX interface (IDLE State) */ - __HAL_SPDIFRX_IDLE(hspdif); - - /* Reset the old SPDIFRX CR configuration */ - tmpreg = hspdif->Instance->CR; - - tmpreg &= ~(SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | - SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | - SPDIFRX_CR_CHSEL | SPDIFRX_CR_NBTR | SPDIFRX_CR_WFA | - SPDIFRX_CR_INSEL); - - /* Sets the new configuration of the SPDIFRX peripheral */ - tmpreg |= (hspdif->Init.StereoMode | - hspdif->Init.InputSelection | - hspdif->Init.Retries | - hspdif->Init.WaitForActivity | - hspdif->Init.ChannelSelection | - hspdif->Init.DataFormat | - hspdif->Init.PreambleTypeMask | - hspdif->Init.ChannelStatusMask | - hspdif->Init.ValidityBitMask | - hspdif->Init.ParityErrorMask - ); - - - hspdif->Instance->CR = tmpreg; - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* SPDIFRX peripheral state is READY*/ - hspdif->State = HAL_SPDIFRX_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the SPDIFRX peripheral - * @param hspdif SPDIFRX handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Check the SPDIFRX handle allocation */ - if (hspdif == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPDIFRX_ALL_INSTANCE(hspdif->Instance)); - - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Disable SPDIFRX interface (IDLE state) */ - __HAL_SPDIFRX_IDLE(hspdif); - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - if (hspdif->MspDeInitCallback == NULL) - { - hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hspdif->MspDeInitCallback(hspdif); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_SPDIFRX_MspDeInit(hspdif); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* SPDIFRX peripheral state is RESET*/ - hspdif->State = HAL_SPDIFRX_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; -} - -/** - * @brief SPDIFRX MSP Init - * @param hspdif SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_MspInit could be implemented in the user file - */ -} - -/** - * @brief SPDIFRX MSP DeInit - * @param hspdif SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User SPDIFRX Callback - * To be used instead of the weak predefined callback - * @param hspdif SPDIFRX handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID - * @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID - * @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID - * @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID - * @arg @ref HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID - * @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, - pSPDIFRX_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hspdif); - - if (HAL_SPDIFRX_STATE_READY == hspdif->State) - { - switch (CallbackID) - { - case HAL_SPDIFRX_RX_HALF_CB_ID : - hspdif->RxHalfCpltCallback = pCallback; - break; - - case HAL_SPDIFRX_RX_CPLT_CB_ID : - hspdif->RxCpltCallback = pCallback; - break; - - case HAL_SPDIFRX_CX_HALF_CB_ID : - hspdif->CxHalfCpltCallback = pCallback; - break; - - case HAL_SPDIFRX_CX_CPLT_CB_ID : - hspdif->CxCpltCallback = pCallback; - break; - - case HAL_SPDIFRX_ERROR_CB_ID : - hspdif->ErrorCallback = pCallback; - break; - - case HAL_SPDIFRX_MSPINIT_CB_ID : - hspdif->MspInitCallback = pCallback; - break; - - case HAL_SPDIFRX_MSPDEINIT_CB_ID : - hspdif->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) - { - switch (CallbackID) - { - case HAL_SPDIFRX_MSPINIT_CB_ID : - hspdif->MspInitCallback = pCallback; - break; - - case HAL_SPDIFRX_MSPDEINIT_CB_ID : - hspdif->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hspdif); - return status; -} - -/** - * @brief Unregister a SPDIFRX Callback - * SPDIFRX callback is redirected to the weak predefined callback - * @param hspdif SPDIFRX handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_SPDIFRX_RX_HALF_CB_ID SPDIFRX Data flow half completed callback ID - * @arg @ref HAL_SPDIFRX_RX_CPLT_CB_ID SPDIFRX Data flow completed callback ID - * @arg @ref HAL_SPDIFRX_CX_HALF_CB_ID SPDIFRX Control flow half completed callback ID - * @arg @ref HAL_SPDIFRX_CX_CPLT_CB_ID SPDIFRX Control flow completed callback ID - * @arg @ref HAL_SPDIFRX_ERROR_CB_ID SPDIFRX error callback ID - * @arg @ref HAL_SPDIFRX_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, - HAL_SPDIFRX_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hspdif); - - if (HAL_SPDIFRX_STATE_READY == hspdif->State) - { - switch (CallbackID) - { - case HAL_SPDIFRX_RX_HALF_CB_ID : - hspdif->RxHalfCpltCallback = HAL_SPDIFRX_RxHalfCpltCallback; - break; - - case HAL_SPDIFRX_RX_CPLT_CB_ID : - hspdif->RxCpltCallback = HAL_SPDIFRX_RxCpltCallback; - break; - - case HAL_SPDIFRX_CX_HALF_CB_ID : - hspdif->CxHalfCpltCallback = HAL_SPDIFRX_CxHalfCpltCallback; - break; - - case HAL_SPDIFRX_CX_CPLT_CB_ID : - hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; - break; - - case HAL_SPDIFRX_ERROR_CB_ID : - hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; - break; - - default : - /* Update the error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) - { - switch (CallbackID) - { - case HAL_SPDIFRX_MSPINIT_CB_ID : - hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_SPDIFRX_MSPDEINIT_CB_ID : - hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspInit */ - break; - - default : - /* Update the error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hspdif); - return status; -} - -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - -/** - * @brief Set the SPDIFRX data format according to the specified parameters in the SPDIFRX_InitTypeDef. - * @param hspdif SPDIFRX handle - * @param sDataFormat SPDIFRX data format - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat) -{ - uint32_t tmpreg; - - /* Check the SPDIFRX handle allocation */ - if (hspdif == NULL) - { - return HAL_ERROR; - } - - /* Check the SPDIFRX parameters */ - assert_param(IS_STEREO_MODE(sDataFormat.StereoMode)); - assert_param(IS_SPDIFRX_DATA_FORMAT(sDataFormat.DataFormat)); - assert_param(IS_PREAMBLE_TYPE_MASK(sDataFormat.PreambleTypeMask)); - assert_param(IS_CHANNEL_STATUS_MASK(sDataFormat.ChannelStatusMask)); - assert_param(IS_VALIDITY_MASK(sDataFormat.ValidityBitMask)); - assert_param(IS_PARITY_ERROR_MASK(sDataFormat.ParityErrorMask)); - - /* Reset the old SPDIFRX CR configuration */ - tmpreg = hspdif->Instance->CR; - - if (((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && - (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || - ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) - { - return HAL_ERROR; - } - - tmpreg &= ~(SPDIFRX_CR_RXSTEO | SPDIFRX_CR_DRFMT | SPDIFRX_CR_PMSK | - SPDIFRX_CR_VMSK | SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK); - - /* Configure the new data format */ - tmpreg |= (sDataFormat.StereoMode | - sDataFormat.DataFormat | - sDataFormat.PreambleTypeMask | - sDataFormat.ChannelStatusMask | - sDataFormat.ValidityBitMask | - sDataFormat.ParityErrorMask); - - hspdif->Instance->CR = tmpreg; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SPDIFRX_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim -=============================================================================== - ##### IO operation functions ##### -=============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SPDIFRX data - transfers. - - (#) There is two mode of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer start-up. - The end of the data processing will be indicated through the - dedicated SPDIFRX IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_SPDIFRX_ReceiveDataFlow() - (++) HAL_SPDIFRX_ReceiveControlFlow() - (+@) Do not use blocking mode to receive both control and data flow at the same time. - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_SPDIFRX_ReceiveControlFlow_IT() - (++) HAL_SPDIFRX_ReceiveDataFlow_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_SPDIFRX_ReceiveControlFlow_DMA() - (++) HAL_SPDIFRX_ReceiveDataFlow_DMA() - - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: - (++) HAL_SPDIFRX_RxCpltCallback() - (++) HAL_SPDIFRX_CxCpltCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Receives an amount of data (Data Flow) in blocking mode. - * @param hspdif pointer to SPDIFRX_HandleTypeDef structure that contains - * the configuration information for SPDIFRX module. - * @param pData Pointer to data buffer - * @param Size Amount of data to be received - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, - uint32_t Timeout) -{ - uint32_t tickstart; - uint16_t sizeCounter = Size; - uint32_t *pTmpBuf = pData; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (hspdif->State == HAL_SPDIFRX_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Start synchronisation */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until SYNCD flag is set */ - if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - - /* Receive data flow */ - while (sizeCounter > 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until RXNE flag is set */ - if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*pTmpBuf) = hspdif->Instance->DR; - pTmpBuf++; - sizeCounter--; - } - - /* SPDIFRX ready */ - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives an amount of data (Control Flow) in blocking mode. - * @param hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains - * the configuration information for SPDIFRX module. - * @param pData Pointer to data buffer - * @param Size Amount of data to be received - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, - uint32_t Timeout) -{ - uint32_t tickstart; - uint16_t sizeCounter = Size; - uint32_t *pTmpBuf = pData; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if (hspdif->State == HAL_SPDIFRX_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->State = HAL_SPDIFRX_STATE_BUSY; - - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until SYNCD flag is set */ - if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - - /* Receive control flow */ - while (sizeCounter > 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until CSRNE flag is set */ - if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*pTmpBuf) = hspdif->Instance->CSR; - pTmpBuf++; - sizeCounter--; - } - - /* SPDIFRX ready */ - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt - * @param hspdif SPDIFRX handle - * @param pData a 32-bit pointer to the Receive data buffer. - * @param Size number of data sample to be received . - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) -{ - uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); - - const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - - if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->pRxBuffPtr = pData; - hspdif->RxXferSize = Size; - hspdif->RxXferCount = Size; - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* Check if a receive process is ongoing or not */ - hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; - - /* Enable the SPDIFRX PE Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - - /* Enable the SPDIFRX OVR Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - - /* Enable the SPDIFRX RXNE interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE); - - if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - do - { - if (count == 0U) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt - process */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_TIMEOUT; - } - count--; - } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif SPDIFRX handle - * @param pData a 32-bit pointer to the Receive data buffer. - * @param Size number of data sample (Control Flow) to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) -{ - uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); - - const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - - if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->pCsBuffPtr = pData; - hspdif->CsXferSize = Size; - hspdif->CsXferCount = Size; - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - - /* Check if a receive process is ongoing or not */ - hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; - - /* Enable the SPDIFRX PE Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - - /* Enable the SPDIFRX OVR Error Interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - - /* Enable the SPDIFRX CSRNE interrupt */ - __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - - if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - do - { - if (count == 0U) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt - process */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_TIMEOUT; - } - count--; - } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data (Data Flow) mode with DMA - * @param hspdif SPDIFRX handle - * @param pData a 32-bit pointer to the Receive data buffer. - * @param Size number of data sample to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) -{ - uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); - - const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) - { - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->pRxBuffPtr = pData; - hspdif->RxXferSize = Size; - hspdif->RxXferCount = Size; - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - hspdif->State = HAL_SPDIFRX_STATE_BUSY_RX; - - /* Set the SPDIFRX Rx DMA Half transfer complete callback */ - hspdif->hdmaDrRx->XferHalfCpltCallback = SPDIFRX_DMARxHalfCplt; - - /* Set the SPDIFRX Rx DMA transfer complete callback */ - hspdif->hdmaDrRx->XferCpltCallback = SPDIFRX_DMARxCplt; - - /* Set the DMA error callback */ - hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; - - /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != - HAL_OK) - { - /* Set SPDIFRX error */ - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; - - /* Set SPDIFRX state */ - hspdif->State = HAL_SPDIFRX_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_ERROR; - } - - /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/ - hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; - - if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - do - { - if (count == 0U) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt - process */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_TIMEOUT; - } - count--; - } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data (Control Flow) with DMA - * @param hspdif SPDIFRX handle - * @param pData a 32-bit pointer to the Receive data buffer. - * @param Size number of data (Control Flow) sample to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) -{ - uint32_t count = SPDIFRX_TIMEOUT_VALUE * (SystemCoreClock / 24U / 1000U); - - const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) - { - hspdif->pCsBuffPtr = pData; - hspdif->CsXferSize = Size; - hspdif->CsXferCount = Size; - - /* Process Locked */ - __HAL_LOCK(hspdif); - - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; - hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; - - /* Set the SPDIFRX Rx DMA Half transfer complete callback */ - hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt; - - /* Set the SPDIFRX Rx DMA transfer complete callback */ - hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt; - - /* Set the DMA error callback */ - hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; - - /* Enable the DMA request */ - if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != - HAL_OK) - { - /* Set SPDIFRX error */ - hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; - - /* Set SPDIFRX state */ - hspdif->State = HAL_SPDIFRX_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_ERROR; - } - - /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ - hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; - - if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) - { - /* Start synchronization */ - __HAL_SPDIFRX_SYNC(hspdif); - - /* Wait until SYNCD flag is set */ - do - { - if (count == 0U) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt - process */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_TIMEOUT; - } - count--; - } while (__HAL_SPDIFRX_GET_FLAG(hspdif, SPDIFRX_FLAG_SYNCD) == RESET); - - /* Start reception */ - __HAL_SPDIFRX_RCV(hspdif); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief stop the audio stream receive from the Media. - * @param hspdif SPDIFRX handle - * @retval None - */ -HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Process Locked */ - __HAL_LOCK(hspdif); - - /* Disable the SPDIFRX DMA requests */ - hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); - hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); - - /* Disable the SPDIFRX DMA channel */ - if (hspdif->hdmaDrRx != NULL) - { - __HAL_DMA_DISABLE(hspdif->hdmaDrRx); - } - if (hspdif->hdmaCsRx != NULL) - { - __HAL_DMA_DISABLE(hspdif->hdmaCsRx); - } - - /* Disable SPDIFRX peripheral */ - __HAL_SPDIFRX_IDLE(hspdif); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_OK; -} - -/** - * @brief This function handles SPDIFRX interrupt request. - * @param hspdif SPDIFRX handle - * @retval HAL status - */ -void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) -{ - uint32_t itFlag = hspdif->Instance->SR; - uint32_t itSource = hspdif->Instance->IMR; - - /* SPDIFRX in mode Data Flow Reception */ - if (((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE)) - { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); - SPDIFRX_ReceiveDataFlow_IT(hspdif); - } - - /* SPDIFRX in mode Control Flow Reception */ - if (((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE)) - { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); - SPDIFRX_ReceiveControlFlow_IT(hspdif); - } - - /* SPDIFRX Overrun error interrupt occurred */ - if (((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE)) - { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE); - - /* Change the SPDIFRX error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_OVR; - - /* the transfer is not stopped */ - HAL_SPDIFRX_ErrorCallback(hspdif); - } - - /* SPDIFRX Parity error interrupt occurred */ - if (((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE)) - { - __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE); - - /* Change the SPDIFRX error code */ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_PE; - - /* the transfer is not stopped */ - HAL_SPDIFRX_ErrorCallback(hspdif); - } -} - -/** - * @brief Rx Transfer (Data flow) half completed callbacks - * @param hspdif SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer (Data flow) completed callbacks - * @param hspdif SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx (Control flow) Transfer half completed callbacks - * @param hspdif SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer (Control flow) completed callbacks - * @param hspdif SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief SPDIFRX error callbacks - * @param hspdif SPDIFRX handle - * @retval None - */ -__weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspdif); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPDIFRX_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SPDIFRX_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral State functions - * -@verbatim -=============================================================================== -##### Peripheral State and Errors functions ##### -=============================================================================== -[..] -This subsection permit to get in run-time the status of the peripheral -and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the SPDIFRX state - * @param hspdif SPDIFRX handle - * @retval HAL state - */ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif) -{ - return hspdif->State; -} - -/** - * @brief Return the SPDIFRX error code - * @param hspdif SPDIFRX handle - * @retval SPDIFRX Error Code - */ -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif) -{ - return hspdif->ErrorCode; -} - -/** - * @} - */ - -/** - * @brief DMA SPDIFRX receive process (Data flow) complete callback - * @param hdma DMA handle - * @retval None - */ -static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Rx DMA Request */ - if (hdma->Init.Mode != DMA_CIRCULAR) - { - hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); - hspdif->RxXferCount = 0; - hspdif->State = HAL_SPDIFRX_STATE_READY; - } -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->RxCpltCallback(hspdif); -#else - HAL_SPDIFRX_RxCpltCallback(hspdif); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPDIFRX receive process (Data flow) half complete callback - * @param hdma DMA handle - * @retval None - */ -static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->RxHalfCpltCallback(hspdif); -#else - HAL_SPDIFRX_RxHalfCpltCallback(hspdif); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -} - - -/** - * @brief DMA SPDIFRX receive process (Control flow) complete callback - * @param hdma DMA handle - * @retval None - */ -static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Cb DMA Request */ - hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); - hspdif->CsXferCount = 0; - - hspdif->State = HAL_SPDIFRX_STATE_READY; -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->CxCpltCallback(hspdif); -#else - HAL_SPDIFRX_CxCpltCallback(hspdif); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPDIFRX receive process (Control flow) half complete callback - * @param hdma DMA handle - * @retval None - */ -static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->CxHalfCpltCallback(hspdif); -#else - HAL_SPDIFRX_CxHalfCpltCallback(hspdif); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPDIFRX communication error callback - * @param hdma DMA handle - * @retval None - */ -static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) -{ - SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Disable Rx and Cb DMA Request */ - hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN)); - hspdif->RxXferCount = 0; - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Set the error code and execute error callback*/ - hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA; - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - /* The transfer is not stopped */ - hspdif->ErrorCallback(hspdif); -#else - /* The transfer is not stopped */ - HAL_SPDIFRX_ErrorCallback(hspdif); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ -} - -/** - * @brief Receive an amount of data (Data Flow) with Interrupt - * @param hspdif SPDIFRX handle - * @retval None - */ -static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Receive data */ - (*hspdif->pRxBuffPtr) = hspdif->Instance->DR; - hspdif->pRxBuffPtr++; - hspdif->RxXferCount--; - - if (hspdif->RxXferCount == 0U) - { - /* Disable RXNE/PE and OVR interrupts */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->RxCpltCallback(hspdif); -#else - HAL_SPDIFRX_RxCpltCallback(hspdif); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif SPDIFRX handle - * @retval None - */ -static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) -{ - /* Receive data */ - (*hspdif->pCsBuffPtr) = hspdif->Instance->CSR; - hspdif->pCsBuffPtr++; - hspdif->CsXferCount--; - - if (hspdif->CsXferCount == 0U) - { - /* Disable CSRNE interrupt */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - -#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->CxCpltCallback(hspdif); -#else - HAL_SPDIFRX_CxCpltCallback(hspdif); -#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ - } -} - -/** - * @brief This function handles SPDIFRX Communication Timeout. - * @param hspdif SPDIFRX handle - * @param Flag Flag checked - * @param Status Value of the flag expected - * @param Timeout Duration of the timeout - * @param tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, - FlagStatus Status, uint32_t Timeout, uint32_t tickstart) -{ - /* Wait until flag is set */ - while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt - process */ - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); - __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - - hspdif->State = HAL_SPDIFRX_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspdif); - - return HAL_TIMEOUT; - } - } - } - - return HAL_OK; -} - -/** - * @} - */ - - -#endif /* SPDIFRX */ -#endif /* HAL_SPDIFRX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c index e9c04a39..bd12c67c 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi.c @@ -1,4530 +1,4532 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_spi.c - * @author MCD Application Team - * @brief SPI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Serial Peripheral Interface (SPI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SPI HAL driver can be used as follows: - - (#) Declare a SPI_HandleTypeDef handle structure, for example: - SPI_HandleTypeDef hspi; - - (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: - (##) Enable the SPIx interface clock - (##) SPI pins configuration - (+++) Enable the clock for the SPI GPIOs - (+++) Configure these SPI pins as alternate function push-pull - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the SPIx interrupt priority - (+++) Enable the NVIC SPI IRQ handle - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel - (+++) Enable the DMAx clock - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Stream/Channel - (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel - - (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS - management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. - - (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_SPI_MspInit() API. - [..] - Circular mode restriction: - (#) The DMA circular mode cannot be used when the SPI is configured in these modes: - (##) Master 2Lines RxOnly - (##) Master 1Line Rx - (#) The CRC feature is not managed when the DMA circular mode is enabled - (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs - the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks - [..] - Master Receive mode restriction: - (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or - bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI - does not initiate a new transfer the following procedure has to be respected: - (##) HAL_SPI_DeInit() - (##) HAL_SPI_Init() - [..] - Callback registration: - - (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. - - Function HAL_SPI_RegisterCallback() allows to register following callbacks: - (++) TxCpltCallback : SPI Tx Completed callback - (++) RxCpltCallback : SPI Rx Completed callback - (++) TxRxCpltCallback : SPI TxRx Completed callback - (++) TxHalfCpltCallback : SPI Tx Half Completed callback - (++) RxHalfCpltCallback : SPI Rx Half Completed callback - (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (++) ErrorCallback : SPI Error callback - (++) AbortCpltCallback : SPI Abort callback - (++) MspInitCallback : SPI Msp Init callback - (++) MspDeInitCallback : SPI Msp DeInit callback - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - - (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default - weak function. - HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (++) TxCpltCallback : SPI Tx Completed callback - (++) RxCpltCallback : SPI Rx Completed callback - (++) TxRxCpltCallback : SPI TxRx Completed callback - (++) TxHalfCpltCallback : SPI Tx Half Completed callback - (++) RxHalfCpltCallback : SPI Rx Half Completed callback - (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (++) ErrorCallback : SPI Error callback - (++) AbortCpltCallback : SPI Abort callback - (++) MspInitCallback : SPI Msp Init callback - (++) MspDeInitCallback : SPI Msp DeInit callback - - [..] - By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when - these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - - [..] - Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() - or HAL_SPI_Init() function. - - [..] - When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. - - [..] - Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, - the following table resume the max SPI frequency reached with data size 8bits/16bits, - according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. - - @endverbatim - - Additional table : - - DataSize = SPI_DATASIZE_8BIT: - +----------------------------------------------------------------------------------------------+ - | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Transfer mode |---------------------|----------------------|----------------------| - | | | Master | Slave | Master | Slave | Master | Slave | - |==============================================================================================| - | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | - | X |----------------|----------|----------|-----------|----------|-----------|----------| - | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | - | R |----------------|----------|----------|-----------|----------|-----------|----------| - | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | - |=========|================|==========|==========|===========|==========|===========|==========| - | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | - | |----------------|----------|----------|-----------|----------|-----------|----------| - | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | - | X |----------------|----------|----------|-----------|----------|-----------|----------| - | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | - |=========|================|==========|==========|===========|==========|===========|==========| - | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | - | |----------------|----------|----------|-----------|----------|-----------|----------| - | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | - | X |----------------|----------|----------|-----------|----------|-----------|----------| - | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | - +----------------------------------------------------------------------------------------------+ - - DataSize = SPI_DATASIZE_16BIT: - +----------------------------------------------------------------------------------------------+ - | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Transfer mode |---------------------|----------------------|----------------------| - | | | Master | Slave | Master | Slave | Master | Slave | - |==============================================================================================| - | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | - | X |----------------|----------|----------|-----------|----------|-----------|----------| - | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | - | R |----------------|----------|----------|-----------|----------|-----------|----------| - | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | - |=========|================|==========|==========|===========|==========|===========|==========| - | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | - | |----------------|----------|----------|-----------|----------|-----------|----------| - | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | - | X |----------------|----------|----------|-----------|----------|-----------|----------| - | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | - |=========|================|==========|==========|===========|==========|===========|==========| - | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | - | |----------------|----------|----------|-----------|----------|-----------|----------| - | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | - | X |----------------|----------|----------|-----------|----------|-----------|----------| - | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | - +----------------------------------------------------------------------------------------------+ - @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), - SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). - @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() - (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() - (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SPI SPI - * @brief SPI HAL module driver - * @{ - */ -#ifdef HAL_SPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup SPI_Private_Constants SPI Private Constants - * @{ - */ -#define SPI_DEFAULT_TIMEOUT 100U -#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup SPI_Private_Functions SPI Private Functions - * @{ - */ -static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAError(DMA_HandleTypeDef *hdma); -static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, - uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, - uint32_t Timeout, uint32_t Tickstart); -static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); -#if (USE_SPI_CRC != 0U) -static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); -static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); -static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); -#endif /* USE_SPI_CRC */ -static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); -static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); -static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); -static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); -static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); -static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SPI_Exported_Functions SPI Exported Functions - * @{ - */ - -/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the SPIx peripheral: - - (+) User must implement HAL_SPI_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_SPI_Init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Direction - (++) Data Size - (++) Clock Polarity and Phase - (++) NSS Management - (++) BaudRate Prescaler - (++) FirstBit - (++) TIMode - (++) CRC Calculation - (++) CRC Polynomial if CRC enabled - (++) CRC Length, used only with Data8 and Data16 - (++) FIFO reception threshold - - (+) Call the function HAL_SPI_DeInit() to restore the default configuration - of the selected SPIx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the SPI according to the specified parameters - * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) -{ - uint32_t frxth; - - /* Check the SPI handle allocation */ - if (hspi == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); - assert_param(IS_SPI_MODE(hspi->Init.Mode)); - assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); - assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); - assert_param(IS_SPI_NSS(hspi->Init.NSS)); - assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); - assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); - if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) - { - assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); - assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); - - if (hspi->Init.Mode == SPI_MODE_MASTER) - { - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - } - else - { - /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ - hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; - } - } - else - { - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - - /* Force polarity and phase to TI protocaol requirements */ - hspi->Init.CLKPolarity = SPI_POLARITY_LOW; - hspi->Init.CLKPhase = SPI_PHASE_1EDGE; - } -#if (USE_SPI_CRC != 0U) - assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); - assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); - } -#else - hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; -#endif /* USE_SPI_CRC */ - - if (hspi->State == HAL_SPI_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hspi->Lock = HAL_UNLOCKED; - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - /* Init the SPI Callback settings */ - hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ - hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ - hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ - hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - - if (hspi->MspInitCallback == NULL) - { - hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - hspi->MspInitCallback(hspi); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_SPI_MspInit(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Disable the selected SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Align by default the rs fifo threshold on the data size */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - frxth = SPI_RXFIFO_THRESHOLD_HF; - } - else - { - frxth = SPI_RXFIFO_THRESHOLD_QF; - } - - /* CRC calculation is valid only for 16Bit and 8 Bit */ - if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) - { - /* CRC must be disabled */ - hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - } - - /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ - /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, - Communication speed, First bit and CRC calculation state */ - WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | - (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | - (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | - (hspi->Init.CLKPhase & SPI_CR1_CPHA) | - (hspi->Init.NSS & SPI_CR1_SSM) | - (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | - (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | - (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); -#if (USE_SPI_CRC != 0U) - /*---------------------------- SPIx CRCL Configuration -------------------*/ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Align the CRC Length on the data size */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) - { - /* CRC Length aligned on the data size : value set by default */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; - } - else - { - hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; - } - } - - /* Configure : CRC Length */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); - } - } -#endif /* USE_SPI_CRC */ - - /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ - WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | - (hspi->Init.TIMode & SPI_CR2_FRF) | - (hspi->Init.NSSPMode & SPI_CR2_NSSP) | - (hspi->Init.DataSize & SPI_CR2_DS_Msk) | - (frxth & SPI_CR2_FRXTH))); - -#if (USE_SPI_CRC != 0U) - /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ - /* Configure : CRC Polynomial */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); - } -#endif /* USE_SPI_CRC */ - -#if defined(SPI_I2SCFGR_I2SMOD) - /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ - CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); -#endif /* SPI_I2SCFGR_I2SMOD */ - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State = HAL_SPI_STATE_READY; - - return HAL_OK; -} - -/** - * @brief De-Initialize the SPI peripheral. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) -{ - /* Check the SPI handle allocation */ - if (hspi == NULL) - { - return HAL_ERROR; - } - - /* Check SPI Instance parameter */ - assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Disable the SPI Peripheral Clock */ - __HAL_SPI_DISABLE(hspi); - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - if (hspi->MspDeInitCallback == NULL) - { - hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - hspi->MspDeInitCallback(hspi); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_SPI_MspDeInit(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State = HAL_SPI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Initialize the SPI MSP. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_MspInit should be implemented in the user file - */ -} - -/** - * @brief De-Initialize the SPI MSP. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_MspDeInit should be implemented in the user file - */ -} - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User SPI Callback - * To be used instead of the weak predefined callback - * @param hspi Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI. - * @param CallbackID ID of the callback to be registered - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, - pSPI_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hspi); - - if (HAL_SPI_STATE_READY == hspi->State) - { - switch (CallbackID) - { - case HAL_SPI_TX_COMPLETE_CB_ID : - hspi->TxCpltCallback = pCallback; - break; - - case HAL_SPI_RX_COMPLETE_CB_ID : - hspi->RxCpltCallback = pCallback; - break; - - case HAL_SPI_TX_RX_COMPLETE_CB_ID : - hspi->TxRxCpltCallback = pCallback; - break; - - case HAL_SPI_TX_HALF_COMPLETE_CB_ID : - hspi->TxHalfCpltCallback = pCallback; - break; - - case HAL_SPI_RX_HALF_COMPLETE_CB_ID : - hspi->RxHalfCpltCallback = pCallback; - break; - - case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : - hspi->TxRxHalfCpltCallback = pCallback; - break; - - case HAL_SPI_ERROR_CB_ID : - hspi->ErrorCallback = pCallback; - break; - - case HAL_SPI_ABORT_CB_ID : - hspi->AbortCpltCallback = pCallback; - break; - - case HAL_SPI_MSPINIT_CB_ID : - hspi->MspInitCallback = pCallback; - break; - - case HAL_SPI_MSPDEINIT_CB_ID : - hspi->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SPI_STATE_RESET == hspi->State) - { - switch (CallbackID) - { - case HAL_SPI_MSPINIT_CB_ID : - hspi->MspInitCallback = pCallback; - break; - - case HAL_SPI_MSPDEINIT_CB_ID : - hspi->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hspi); - return status; -} - -/** - * @brief Unregister an SPI Callback - * SPI callback is redirected to the weak predefined callback - * @param hspi Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI. - * @param CallbackID ID of the callback to be unregistered - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hspi); - - if (HAL_SPI_STATE_READY == hspi->State) - { - switch (CallbackID) - { - case HAL_SPI_TX_COMPLETE_CB_ID : - hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_SPI_RX_COMPLETE_CB_ID : - hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_SPI_TX_RX_COMPLETE_CB_ID : - hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ - break; - - case HAL_SPI_TX_HALF_COMPLETE_CB_ID : - hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_SPI_RX_HALF_COMPLETE_CB_ID : - hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : - hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ - break; - - case HAL_SPI_ERROR_CB_ID : - hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_SPI_ABORT_CB_ID : - hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_SPI_MSPINIT_CB_ID : - hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_SPI_MSPDEINIT_CB_ID : - hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SPI_STATE_RESET == hspi->State) - { - switch (CallbackID) - { - case HAL_SPI_MSPINIT_CB_ID : - hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_SPI_MSPDEINIT_CB_ID : - hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hspi); - return status; -} -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SPI - data transfers. - - [..] The SPI supports master and slave mode : - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected - - (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) - exist for 1Line (simplex) and 2Lines (full duplex) modes. - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; - uint16_t initial_TxXferCount; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - initial_TxXferCount = Size; - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0U; - hspi->RxXferCount = 0U; - hspi->TxISR = NULL; - hspi->RxISR = NULL; - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ - __HAL_SPI_DISABLE(hspi); - SPI_1LINE_TX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif /* USE_SPI_CRC */ - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Transmit data in 16 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - } - /* Transmit data in 16 Bit mode */ - while (hspi->TxXferCount > 0U) - { - /* Wait until TXE flag is set to send data */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - errorcode = HAL_TIMEOUT; - hspi->State = HAL_SPI_STATE_READY; - goto error; - } - } - } - } - /* Transmit data in 8 Bit mode */ - else - { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - { - if (hspi->TxXferCount > 1U) - { - /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr ++; - hspi->TxXferCount--; - } - } - while (hspi->TxXferCount > 0U) - { - /* Wait until TXE flag is set to send data */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) - { - if (hspi->TxXferCount > 1U) - { - /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - errorcode = HAL_TIMEOUT; - hspi->State = HAL_SPI_STATE_READY; - goto error; - } - } - } - } -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - - /* Check the end of the transaction */ - if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - errorcode = HAL_ERROR; - } - else - { - hspi->State = HAL_SPI_STATE_READY; - } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ -#if (USE_SPI_CRC != 0U) - __IO uint32_t tmpreg = 0U; - __IO uint8_t *ptmpreg8; - __IO uint8_t tmpreg8 = 0; -#endif /* USE_SPI_CRC */ - uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = (uint8_t *)pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0U; - hspi->TxXferCount = 0U; - hspi->RxISR = NULL; - hspi->TxISR = NULL; - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - /* this is done to handle the CRCNEXT before the latest data */ - hspi->RxXferCount--; - } -#endif /* USE_SPI_CRC */ - - /* Set the Rx Fifo threshold */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Set RX Fifo threshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* Set RX Fifo threshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - /* Configure communication direction: 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ - __HAL_SPI_DISABLE(hspi); - SPI_1LINE_RX(hspi); - } - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Receive data in 8 Bit mode */ - if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - /* Transfer loop */ - while (hspi->RxXferCount > 0U) - { - /* Check the RXNE flag */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) - { - /* read the received data */ - (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - errorcode = HAL_TIMEOUT; - hspi->State = HAL_SPI_STATE_READY; - goto error; - } - } - } - } - else - { - /* Transfer loop */ - while (hspi->RxXferCount > 0U) - { - /* Check the RXNE flag */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) - { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - errorcode = HAL_TIMEOUT; - hspi->State = HAL_SPI_STATE_READY; - goto error; - } - } - } - } - -#if (USE_SPI_CRC != 0U) - /* Handle the CRC Transmission */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* freeze the CRC before the latest data */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - - /* Read the latest data */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) - { - /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; - } - - /* Receive last data in 16 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; - } - /* Receive last data in 8 Bit mode */ - else - { - (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; - } - - /* Wait the CRC data */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; - } - - /* Read CRC to Flush DR and RXNE flag */ - if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) - { - /* Read 16bit CRC */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); - } - else - { - /* Initialize the 8bit temporary pointer */ - ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; - /* Read 8bit CRC */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - - if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) - { - /* Error on the CRC reception */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; - } - /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - } - } - } -#endif /* USE_SPI_CRC */ - - /* Check the end of the transaction */ - if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } -#endif /* USE_SPI_CRC */ - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - errorcode = HAL_ERROR; - } - else - { - hspi->State = HAL_SPI_STATE_READY; - } - -error : - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) -{ - uint16_t initial_TxXferCount; - uint16_t initial_RxXferCount; - uint32_t tmp_mode; - HAL_SPI_StateTypeDef tmp_state; - uint32_t tickstart; -#if (USE_SPI_CRC != 0U) - __IO uint32_t tmpreg = 0U; - uint32_t spi_cr1; - uint32_t spi_cr2; - __IO uint8_t *ptmpreg8; - __IO uint8_t tmpreg8 = 0; -#endif /* USE_SPI_CRC */ - - /* Variable used to alternate Rx and Tx during transfer */ - uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - initial_TxXferCount = Size; - initial_RxXferCount = Size; -#if (USE_SPI_CRC != 0U) - spi_cr1 = READ_REG(hspi->Instance->CR1); - spi_cr2 = READ_REG(hspi->Instance->CR2); -#endif /* USE_SPI_CRC */ - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) - { - errorcode = HAL_BUSY; - goto error; - } - - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - /* Set the transaction information */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferCount = Size; - hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; - hspi->TxXferCount = Size; - hspi->TxXferSize = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = NULL; - hspi->TxISR = NULL; - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif /* USE_SPI_CRC */ - - /* Set the Rx Fifo threshold */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) - { - /* Set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* Set fiforxthreshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Transmit and Receive data in 16 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); - } - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - - } - while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) - { - /* Check TXE flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - /* Next Data is a reception (Rx). Tx not allowed */ - txallowed = 0U; - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); - } - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - } - - /* Check RXNE flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) - { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - /* Next Data is a Transmission (Tx). Tx is allowed */ - txallowed = 1U; - } - if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) - { - errorcode = HAL_TIMEOUT; - hspi->State = HAL_SPI_STATE_READY; - goto error; - } - } - } - /* Transmit and Receive data in 8 Bit mode */ - else - { - if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) - { - if (hspi->TxXferCount > 1U) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); - } - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - } - } - while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) - { - /* Check TXE flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) - { - if (hspi->TxXferCount > 1U) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - else - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } - /* Next Data is a reception (Rx). Tx not allowed */ - txallowed = 0U; - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ - if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); - } - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - } - - /* Wait until RXNE flag is reset */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) - { - if (hspi->RxXferCount > 1U) - { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2U; - if (hspi->RxXferCount <= 1U) - { - /* Set RX Fifo threshold before to switch on 8 bit data size */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - } - else - { - (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; - hspi->pRxBuffPtr++; - hspi->RxXferCount--; - } - /* Next Data is a Transmission (Tx). Tx is allowed */ - txallowed = 1U; - } - if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) - { - errorcode = HAL_TIMEOUT; - hspi->State = HAL_SPI_STATE_READY; - goto error; - } - } - } - -#if (USE_SPI_CRC != 0U) - /* Read CRC from DR to close CRC calculation process */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until TXE flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) - { - /* Error on the CRC reception */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; - } - /* Read CRC */ - if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) - { - /* Read 16bit CRC */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); - } - else - { - /* Initialize the 8bit temporary pointer */ - ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; - /* Read 8bit CRC */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) - { - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) - { - /* Error on the CRC reception */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; - } - /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - } - } - } - - /* Check if CRC error occurred */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - /* Clear CRC Flag */ - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; - } -#endif /* USE_SPI_CRC */ - - /* Check the end of the transaction */ - if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) - { - errorcode = HAL_ERROR; - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - errorcode = HAL_ERROR; - } - else - { - hspi->State = HAL_SPI_STATE_READY; - } - -error : - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /* Init field not used in handle to zero */ - hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->RxXferSize = 0U; - hspi->RxXferCount = 0U; - hspi->RxISR = NULL; - - /* Set the function for IT treatment */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->TxISR = SPI_TxISR_16BIT; - } - else - { - hspi->TxISR = SPI_TxISR_8BIT; - } - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ - __HAL_SPI_DISABLE(hspi); - SPI_1LINE_TX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif /* USE_SPI_CRC */ - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - -error : - return errorcode; -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); - } - - - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = (uint8_t *)pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Init field not used in handle to zero */ - hspi->pTxBuffPtr = (uint8_t *)NULL; - hspi->TxXferSize = 0U; - hspi->TxXferCount = 0U; - hspi->TxISR = NULL; - - /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Set RX Fifo threshold according the reception data length: 16 bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_RxISR_16BIT; - } - else - { - /* Set RX Fifo threshold according the reception data length: 8 bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_RxISR_8BIT; - } - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ - __HAL_SPI_DISABLE(hspi); - SPI_1LINE_RX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1U; - if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2U; - } - SPI_RESET_CRC(hspi); - } - else - { - hspi->CRCSize = 0U; - } -#endif /* USE_SPI_CRC */ - - /* Note : The SPI must be enabled after unlocking current process - to avoid the risk of SPI interrupt handle execution before current - process unlock */ - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* Enable RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - -error : - return errorcode; -} - -/** - * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) -{ - uint32_t tmp_mode; - HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - - if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) - { - errorcode = HAL_BUSY; - goto error; - } - - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Process locked */ - __HAL_LOCK(hspi); - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - /* Set the transaction information */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Set the function for IT treatment */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->RxISR = SPI_2linesRxISR_16BIT; - hspi->TxISR = SPI_2linesTxISR_16BIT; - } - else - { - hspi->RxISR = SPI_2linesRxISR_8BIT; - hspi->TxISR = SPI_2linesTxISR_8BIT; - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->CRCSize = 1U; - if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) - { - hspi->CRCSize = 2U; - } - SPI_RESET_CRC(hspi); - } - else - { - hspi->CRCSize = 0U; - } -#endif /* USE_SPI_CRC */ - - /* Check if packing mode is enabled and if there is more than 2 data to receive */ - if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) - { - /* Set RX Fifo threshold according the reception data length: 16 bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* Set RX Fifo threshold according the reception data length: 8 bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - -error : - return errorcode; -} - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Check tx dma handle */ - assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - - /* Process Locked */ - __HAL_LOCK(hspi); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /* Init field not used in handle to zero */ - hspi->pRxBuffPtr = (uint8_t *)NULL; - hspi->TxISR = NULL; - hspi->RxISR = NULL; - hspi->RxXferSize = 0U; - hspi->RxXferCount = 0U; - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ - __HAL_SPI_DISABLE(hspi); - SPI_1LINE_TX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif /* USE_SPI_CRC */ - - /* Set the SPI TxDMA Half transfer complete callback */ - hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; - - /* Set the SPI TxDMA transfer complete callback */ - hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; - - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA AbortCpltCallback */ - hspi->hdmatx->XferAbortCallback = NULL; - - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - /* Packing mode is enabled only if the DMA setting is HALWORD */ - if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) - { - /* Check the even/odd of the data size + crc if enabled */ - if ((hspi->TxXferCount & 0x1U) == 0U) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1U); - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; - } - } - - /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, - hspi->TxXferCount)) - { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; - } - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Enable the SPI Error Interrupt Bit */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); - - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA. - * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData pointer to data buffer - * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Check rx dma handle */ - assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - hspi->State = HAL_SPI_STATE_BUSY_RX; - - /* Check tx dma handle */ - assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); - - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); - } - - /* Process Locked */ - __HAL_LOCK(hspi); - - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = (uint8_t *)pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = NULL; - hspi->TxISR = NULL; - hspi->TxXferSize = 0U; - hspi->TxXferCount = 0U; - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ - __HAL_SPI_DISABLE(hspi); - SPI_1LINE_RX(hspi); - } - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif /* USE_SPI_CRC */ - - - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Set RX Fifo threshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* Set RX Fifo threshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - /* Set RX Fifo threshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - if ((hspi->RxXferCount & 0x1U) == 0x0U) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = hspi->RxXferCount >> 1U; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; - } - } - } - - /* Set the SPI RxDMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - - /* Set the SPI Rx DMA transfer complete callback */ - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA AbortCpltCallback */ - hspi->hdmarx->XferAbortCallback = NULL; - - /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount)) - { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; - } - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - /* Enable the SPI Error Interrupt Bit */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); - - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size) -{ - uint32_t tmp_mode; - HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Check rx & tx dma handles */ - assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); - assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Process locked */ - __HAL_LOCK(hspi); - - /* Init temporary variables */ - tmp_state = hspi->State; - tmp_mode = hspi->Init.Mode; - - if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) - { - errorcode = HAL_BUSY; - goto error; - } - - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - - /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - } - - /* Set the transaction information */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Init field not used in handle to zero */ - hspi->RxISR = NULL; - hspi->TxISR = NULL; - -#if (USE_SPI_CRC != 0U) - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } -#endif /* USE_SPI_CRC */ - - /* Reset the threshold bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); - - /* The packing mode management is enabled by the DMA settings according the spi data size */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Set fiforxthreshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - else - { - /* Set RX Fifo threshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - if ((hspi->TxXferSize & 0x1U) == 0x0U) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = hspi->TxXferCount >> 1U; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); - hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; - } - } - - if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) - { - /* Set RX Fifo threshold according the reception data length: 16bit */ - CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - - if ((hspi->RxXferCount & 0x1U) == 0x0U) - { - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = hspi->RxXferCount >> 1U; - } - else - { - SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); - hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; - } - } - } - - /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ - if (hspi->State == HAL_SPI_STATE_BUSY_RX) - { - /* Set the SPI Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - } - else - { - /* Set the SPI Tx/Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; - } - - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA AbortCpltCallback */ - hspi->hdmarx->XferAbortCallback = NULL; - - /* Enable the Rx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount)) - { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; - } - - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing - is performed in DMA reception complete callback */ - hspi->hdmatx->XferHalfCpltCallback = NULL; - hspi->hdmatx->XferCpltCallback = NULL; - hspi->hdmatx->XferErrorCallback = NULL; - hspi->hdmatx->XferAbortCallback = NULL; - - /* Enable the Tx DMA Stream/Channel */ - if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, - hspi->TxXferCount)) - { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; - } - - /* Check if the SPI is already enabled */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - /* Enable the SPI Error Interrupt Bit */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); - - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Abort ongoing transfer (blocking mode). - * @param hspi SPI handle. - * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), - * started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable SPI Interrupts (depending of transfer direction) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) -{ - HAL_StatusTypeDef errorcode; - __IO uint32_t count; - __IO uint32_t resetcount; - - /* Initialized local variable */ - errorcode = HAL_OK; - resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - count = resetcount; - - /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - - /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) - { - hspi->TxISR = SPI_AbortTx_ISR; - /* Wait HAL_SPI_STATE_ABORT state */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while (hspi->State != HAL_SPI_STATE_ABORT); - /* Reset Timeout Counter */ - count = resetcount; - } - - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) - { - hspi->RxISR = SPI_AbortRx_ISR; - /* Wait HAL_SPI_STATE_ABORT state */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while (hspi->State != HAL_SPI_STATE_ABORT); - /* Reset Timeout Counter */ - count = resetcount; - } - - /* Disable the SPI DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) - { - /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ - if (hspi->hdmatx != NULL) - { - /* Set the SPI DMA Abort callback : - will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ - hspi->hdmatx->XferAbortCallback = NULL; - - /* Abort DMA Tx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); - - if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Disable SPI Peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - } - } - - /* Disable the SPI DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) - { - /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ - if (hspi->hdmarx != NULL) - { - /* Set the SPI DMA Abort callback : - will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ - hspi->hdmarx->XferAbortCallback = NULL; - - /* Abort DMA Rx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Disable peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Disable Rx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); - } - } - /* Reset Tx and Rx transfer counters */ - hspi->RxXferCount = 0U; - hspi->TxXferCount = 0U; - - /* Check error during Abort procedure */ - if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) - { - /* return HAL_Error in case of error during Abort procedure */ - errorcode = HAL_ERROR; - } - else - { - /* Reset errorCode */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - } - - /* Clear the Error flags in the SR register */ - __HAL_SPI_CLEAR_OVRFLAG(hspi); - __HAL_SPI_CLEAR_FREFLAG(hspi); - - /* Restore hspi->state to ready */ - hspi->State = HAL_SPI_STATE_READY; - - return errorcode; -} - -/** - * @brief Abort ongoing transfer (Interrupt mode). - * @param hspi SPI handle. - * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), - * started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable SPI Interrupts (depending of transfer direction) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) -{ - HAL_StatusTypeDef errorcode; - uint32_t abortcplt ; - __IO uint32_t count; - __IO uint32_t resetcount; - - /* Initialized local variable */ - errorcode = HAL_OK; - abortcplt = 1U; - resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - count = resetcount; - - /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); - - /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) - { - hspi->TxISR = SPI_AbortTx_ISR; - /* Wait HAL_SPI_STATE_ABORT state */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while (hspi->State != HAL_SPI_STATE_ABORT); - /* Reset Timeout Counter */ - count = resetcount; - } - - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) - { - hspi->RxISR = SPI_AbortRx_ISR; - /* Wait HAL_SPI_STATE_ABORT state */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while (hspi->State != HAL_SPI_STATE_ABORT); - /* Reset Timeout Counter */ - count = resetcount; - } - - /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (hspi->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) - { - hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; - } - else - { - hspi->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (hspi->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) - { - hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; - } - else - { - hspi->hdmarx->XferAbortCallback = NULL; - } - } - - /* Disable the SPI DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) - { - /* Abort the SPI DMA Tx Stream/Channel */ - if (hspi->hdmatx != NULL) - { - /* Abort DMA Tx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) - { - hspi->hdmatx->XferAbortCallback = NULL; - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - else - { - abortcplt = 0U; - } - } - } - /* Disable the SPI DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) - { - /* Abort the SPI DMA Rx Stream/Channel */ - if (hspi->hdmarx != NULL) - { - /* Abort DMA Rx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) - { - hspi->hdmarx->XferAbortCallback = NULL; - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - else - { - abortcplt = 0U; - } - } - } - - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - hspi->RxXferCount = 0U; - hspi->TxXferCount = 0U; - - /* Check error during Abort procedure */ - if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) - { - /* return HAL_Error in case of error during Abort procedure */ - errorcode = HAL_ERROR; - } - else - { - /* Reset errorCode */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - } - - /* Clear the Error flags in the SR register */ - __HAL_SPI_CLEAR_OVRFLAG(hspi); - __HAL_SPI_CLEAR_FREFLAG(hspi); - - /* Restore hspi->State to Ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->AbortCpltCallback(hspi); -#else - HAL_SPI_AbortCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - - return errorcode; -} - -/** - * @brief Pause the DMA Transfer. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) -{ - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) -{ - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Enable the SPI DMA Tx & Rx requests */ - SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): - when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() - */ - - /* Abort the SPI DMA tx Stream/Channel */ - if (hspi->hdmatx != NULL) - { - if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - } - } - /* Abort the SPI DMA rx Stream/Channel */ - if (hspi->hdmarx != NULL) - { - if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - } - } - - /* Disable the SPI DMA Tx & Rx requests */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - hspi->State = HAL_SPI_STATE_READY; - return errorcode; -} - -/** - * @brief Handle SPI interrupt request. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval None - */ -void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) -{ - uint32_t itsource = hspi->Instance->CR2; - uint32_t itflag = hspi->Instance->SR; - - /* SPI in mode Receiver ----------------------------------------------------*/ - if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && - (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) - { - hspi->RxISR(hspi); - return; - } - - /* SPI in mode Transmitter -------------------------------------------------*/ - if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) - { - hspi->TxISR(hspi); - return; - } - - /* SPI in Error Treatment --------------------------------------------------*/ - if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) - || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) - { - /* SPI Overrun error interrupt occurred ----------------------------------*/ - if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) - { - if (hspi->State != HAL_SPI_STATE_BUSY_TX) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - else - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - return; - } - } - - /* SPI Mode Fault error interrupt occurred -------------------------------*/ - if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); - __HAL_SPI_CLEAR_MODFFLAG(hspi); - } - - /* SPI Frame error interrupt occurred ------------------------------------*/ - if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); - __HAL_SPI_CLEAR_FREFLAG(hspi); - } - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - /* Disable all interrupts */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); - - hspi->State = HAL_SPI_STATE_READY; - /* Disable the SPI DMA requests if enabled */ - if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) - { - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); - - /* Abort the SPI DMA Rx channel */ - if (hspi->hdmarx != NULL) - { - /* Set the SPI DMA Abort callback : - will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ - hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; - if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - } - } - /* Abort the SPI DMA Tx channel */ - if (hspi->hdmatx != NULL) - { - /* Set the SPI DMA Abort callback : - will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ - hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; - if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - } - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - } - return; - } -} - -/** - * @brief Tx Transfer completed callback. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_RxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Tx and Rx Transfer completed callback. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxRxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxHalfCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file - */ -} - -/** - * @brief Tx and Rx Half Transfer callback. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file - */ -} - -/** - * @brief SPI error callback. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_ErrorCallback should be implemented in the user file - */ - /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes - and user can use HAL_SPI_GetError() API to check the latest error occurred - */ -} - -/** - * @brief SPI Abort Complete callback. - * @param hspi SPI handle. - * @retval None - */ -__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SPI control functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SPI. - (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral - (+) HAL_SPI_GetError() check in run-time Errors occurring during communication -@endverbatim - * @{ - */ - -/** - * @brief Return the SPI handle state. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI state - */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) -{ - /* Return SPI handle state */ - return hspi->State; -} - -/** - * @brief Return the SPI error code. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI error code in bitmap format - */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) -{ - /* Return SPI ErrorCode */ - return hspi->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup SPI_Private_Functions - * @brief Private functions - * @{ - */ - -/** - * @brief DMA SPI transmit process complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - uint32_t tickstart; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* DMA Normal Mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) - { - /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - /* Check the end of the transaction */ - if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Clear overrun flag in 2 Lines communication mode because received data is not read */ - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - hspi->TxXferCount = 0U; - hspi->State = HAL_SPI_STATE_READY; - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - return; - } - } - /* Call user Tx complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->TxCpltCallback(hspi); -#else - HAL_SPI_TxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI receive process complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - uint32_t tickstart; -#if (USE_SPI_CRC != 0U) - __IO uint32_t tmpreg = 0U; - __IO uint8_t *ptmpreg8; - __IO uint8_t tmpreg8 = 0; -#endif /* USE_SPI_CRC */ - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* DMA Normal Mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) - { - /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); - -#if (USE_SPI_CRC != 0U) - /* CRC handling */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until RXNE flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) - { - /* Error on the CRC reception */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - } - /* Read CRC */ - if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Read 16bit CRC */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); - } - else - { - /* Initialize the 8bit temporary pointer */ - ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; - /* Read 8bit CRC */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) - { - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) - { - /* Error on the CRC reception */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - } - /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - } - } - } -#endif /* USE_SPI_CRC */ - - /* Check if we are in Master RX 2 line mode */ - if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - } - else - { - /* Normal case */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - } - - /* Check the end of the transaction */ - if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_FLAG; - } - - hspi->RxXferCount = 0U; - hspi->State = HAL_SPI_STATE_READY; - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } -#endif /* USE_SPI_CRC */ - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - return; - } - } - /* Call user Rx complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->RxCpltCallback(hspi); -#else - HAL_SPI_RxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI transmit receive process complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - uint32_t tickstart; -#if (USE_SPI_CRC != 0U) - __IO uint32_t tmpreg = 0U; - __IO uint8_t *ptmpreg8; - __IO uint8_t tmpreg8 = 0; -#endif /* USE_SPI_CRC */ - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* DMA Normal Mode */ - if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) - { - /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); - -#if (USE_SPI_CRC != 0U) - /* CRC handling */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) - { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT, - tickstart) != HAL_OK) - { - /* Error on the CRC reception */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - } - /* Initialize the 8bit temporary pointer */ - ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; - /* Read 8bit CRC */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - } - else - { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) - { - /* Error on the CRC reception */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - } - /* Read CRC to Flush DR and RXNE flag */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); - } - } -#endif /* USE_SPI_CRC */ - - /* Check the end of the transaction */ - if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Disable Rx/Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - hspi->TxXferCount = 0U; - hspi->RxXferCount = 0U; - hspi->State = HAL_SPI_STATE_READY; - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } -#endif /* USE_SPI_CRC */ - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - return; - } - } - /* Call user TxRx complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->TxRxCpltCallback(hspi); -#else - HAL_SPI_TxRxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI half transmit process complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - - /* Call user Tx half complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->TxHalfCpltCallback(hspi); -#else - HAL_SPI_TxHalfCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI half receive process complete callback - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - - /* Call user Rx half complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->RxHalfCpltCallback(hspi); -#else - HAL_SPI_RxHalfCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI half transmit receive process complete callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - - /* Call user TxRx half complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->TxRxHalfCpltCallback(hspi); -#else - HAL_SPI_TxRxHalfCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI communication error callback. - * @param hdma pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAError(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - - /* Stop the disable DMA transfer on SPI side */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - hspi->State = HAL_SPI_STATE_READY; - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - hspi->RxXferCount = 0U; - hspi->TxXferCount = 0U; - - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - - hspi->hdmatx->XferAbortCallback = NULL; - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - - if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Disable SPI Peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Check if an Abort process is still ongoing */ - if (hspi->hdmarx != NULL) - { - if (hspi->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ - hspi->RxXferCount = 0U; - hspi->TxXferCount = 0U; - - /* Check no error during Abort procedure */ - if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) - { - /* Reset errorCode */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - } - - /* Clear the Error flags in the SR register */ - __HAL_SPI_CLEAR_OVRFLAG(hspi); - __HAL_SPI_CLEAR_FREFLAG(hspi); - - /* Restore hspi->State to Ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->AbortCpltCallback(hspi); -#else - HAL_SPI_AbortCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ - - /* Disable SPI Peripheral */ - __HAL_SPI_DISABLE(hspi); - - hspi->hdmarx->XferAbortCallback = NULL; - - /* Disable Rx DMA Request */ - CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Check if an Abort process is still ongoing */ - if (hspi->hdmatx != NULL) - { - if (hspi->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ - hspi->RxXferCount = 0U; - hspi->TxXferCount = 0U; - - /* Check no error during Abort procedure */ - if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) - { - /* Reset errorCode */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - } - - /* Clear the Error flags in the SR register */ - __HAL_SPI_CLEAR_OVRFLAG(hspi); - __HAL_SPI_CLEAR_FREFLAG(hspi); - - /* Restore hspi->State to Ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->AbortCpltCallback(hspi); -#else - HAL_SPI_AbortCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Receive data in packing mode */ - if (hspi->RxXferCount > 1U) - { - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount -= 2U; - if (hspi->RxXferCount == 1U) - { - /* Set RX Fifo threshold according the reception data length: 8bit */ - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - } - } - /* Receive data in 8 Bit mode */ - else - { - *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); - hspi->pRxBuffPtr++; - hspi->RxXferCount--; - } - - /* Check end of the reception */ - if (hspi->RxXferCount == 0U) - { -#if (USE_SPI_CRC != 0U) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); - hspi->RxISR = SPI_2linesRxISR_8BITCRC; - return; - } -#endif /* USE_SPI_CRC */ - - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - if (hspi->TxXferCount == 0U) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} - -#if (USE_SPI_CRC != 0U) -/** - * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) -{ - __IO uint8_t *ptmpreg8; - __IO uint8_t tmpreg8 = 0; - - /* Initialize the 8bit temporary pointer */ - ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; - /* Read 8bit CRC to flush Data Register */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - - hspi->CRCSize--; - - /* Check end of the reception */ - if (hspi->CRCSize == 0U) - { - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - if (hspi->TxXferCount == 0U) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} -#endif /* USE_SPI_CRC */ - -/** - * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Transmit data in packing Bit mode */ - if (hspi->TxXferCount >= 2U) - { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= 2U; - } - /* Transmit data in 8 Bit mode */ - else - { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - } - - /* Check the end of the transmission */ - if (hspi->TxXferCount == 0U) - { -#if (USE_SPI_CRC != 0U) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Set CRC Next Bit to send CRC */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - return; - } -#endif /* USE_SPI_CRC */ - - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - - if (hspi->RxXferCount == 0U) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} - -/** - * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Receive data in 16 Bit mode */ - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - - if (hspi->RxXferCount == 0U) - { -#if (USE_SPI_CRC != 0U) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->RxISR = SPI_2linesRxISR_16BITCRC; - return; - } -#endif /* USE_SPI_CRC */ - - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - - if (hspi->TxXferCount == 0U) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} - -#if (USE_SPI_CRC != 0U) -/** - * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) -{ - __IO uint32_t tmpreg = 0U; - - /* Read 16bit CRC to flush Data Register */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); - - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); - - SPI_CloseRxTx_ISR(hspi); -} -#endif /* USE_SPI_CRC */ - -/** - * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - - /* Enable CRC Transmission */ - if (hspi->TxXferCount == 0U) - { -#if (USE_SPI_CRC != 0U) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Set CRC Next Bit to send CRC */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - return; - } -#endif /* USE_SPI_CRC */ - - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); - - if (hspi->RxXferCount == 0U) - { - SPI_CloseRxTx_ISR(hspi); - } - } -} - -#if (USE_SPI_CRC != 0U) -/** - * @brief Manage the CRC 8-bit receive in Interrupt context. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) -{ - __IO uint8_t *ptmpreg8; - __IO uint8_t tmpreg8 = 0; - - /* Initialize the 8bit temporary pointer */ - ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; - /* Read 8bit CRC to flush Data Register */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - - hspi->CRCSize--; - - if (hspi->CRCSize == 0U) - { - SPI_CloseRx_ISR(hspi); - } -} -#endif /* USE_SPI_CRC */ - -/** - * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) -{ - *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); - hspi->pRxBuffPtr++; - hspi->RxXferCount--; - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - - if (hspi->RxXferCount == 0U) - { -#if (USE_SPI_CRC != 0U) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->RxISR = SPI_RxISR_8BITCRC; - return; - } -#endif /* USE_SPI_CRC */ - SPI_CloseRx_ISR(hspi); - } -} - -#if (USE_SPI_CRC != 0U) -/** - * @brief Manage the CRC 16-bit receive in Interrupt context. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) -{ - __IO uint32_t tmpreg = 0U; - - /* Read 16bit CRC to flush Data Register */ - tmpreg = READ_REG(hspi->Instance->DR); - /* To avoid GCC warning */ - UNUSED(tmpreg); - - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - SPI_CloseRx_ISR(hspi); -} -#endif /* USE_SPI_CRC */ - -/** - * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ - *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - -#if (USE_SPI_CRC != 0U) - /* Enable CRC Transmission */ - if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - - if (hspi->RxXferCount == 0U) - { -#if (USE_SPI_CRC != 0U) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - hspi->RxISR = SPI_RxISR_16BITCRC; - return; - } -#endif /* USE_SPI_CRC */ - SPI_CloseRx_ISR(hspi); - } -} - -/** - * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) -{ - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); - hspi->pTxBuffPtr++; - hspi->TxXferCount--; - - if (hspi->TxXferCount == 0U) - { -#if (USE_SPI_CRC != 0U) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Enable CRC Transmission */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - SPI_CloseTx_ISR(hspi); - } -} - -/** - * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - - if (hspi->TxXferCount == 0U) - { -#if (USE_SPI_CRC != 0U) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Enable CRC Transmission */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } -#endif /* USE_SPI_CRC */ - SPI_CloseTx_ISR(hspi); - } -} - -/** - * @brief Handle SPI Communication Timeout. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Flag SPI flag to check - * @param State flag state to check - * @param Timeout Timeout duration - * @param Tickstart tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, - uint32_t Timeout, uint32_t Tickstart) -{ - __IO uint32_t count; - uint32_t tmp_timeout; - uint32_t tmp_tickstart; - - /* Adjust Timeout value in case of end of transfer */ - tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); - tmp_tickstart = HAL_GetTick(); - - /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ - count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); - - while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) - || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ - if (count == 0U) - { - tmp_timeout = 0U; - } - count--; - } - } - - return HAL_OK; -} - -/** - * @brief Handle SPI FIFO Communication Timeout. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Fifo Fifo to check - * @param State Fifo state to check - * @param Timeout Timeout duration - * @param Tickstart tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, - uint32_t Timeout, uint32_t Tickstart) -{ - __IO uint32_t count; - uint32_t tmp_timeout; - uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; - __IO uint8_t tmpreg8 = 0; - - /* Adjust Timeout value in case of end of transfer */ - tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); - tmp_tickstart = HAL_GetTick(); - - /* Initialize the 8bit temporary pointer */ - ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; - - /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ - count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); - - while ((hspi->Instance->SR & Fifo) != State) - { - if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) - { - /* Flush Data Register by a blank read */ - tmpreg8 = *ptmpreg8; - /* To avoid GCC warning */ - UNUSED(tmpreg8); - } - - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) - { - /* Disable the SPI and reset the CRC: the CRC value should be cleared - on both master and slave sides in order to resynchronize the master - and slave for their respective CRC calculation */ - - /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); - - if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) - || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Reset CRC Calculation */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - SPI_RESET_CRC(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ - if (count == 0U) - { - tmp_timeout = 0U; - } - count--; - } - } - - return HAL_OK; -} - -/** - * @brief Handle the check of the RX transaction complete. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Timeout Timeout duration - * @param Tickstart tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) -{ - if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) - || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ - if (hspi->Init.Mode == SPI_MODE_MASTER) - { - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - } - else /* SPI_MODE_SLAVE */ - { - /* Timeout in µs */ - __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); - - /* Wait BSY flag during 1 Byte time transfer in case of Rx transfer - * If Timeout is reached, the transfer is considered as finish. - * User have to calculate the timeout value to fit with the time of 1 byte transfer. - * This time is directly link with the SPI clock from Master device. - */ - do - { - if (count == 0U) - { - break; - } - count--; - } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); - } - - if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) - || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Handle the check of the RXTX or TX transaction complete. - * @param hspi SPI handle - * @param Timeout Timeout duration - * @param Tickstart tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) -{ - /* Control if the TX fifo is empty */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - - /* Timeout in µs */ - __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); - /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ - if (hspi->Init.Mode == SPI_MODE_MASTER) - { - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - } - else - { - /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer - * If Timeout is reached, the transfer is considered as finish. - * User have to calculate the timeout value to fit with the time of 1 byte transfer. - * This time is directly link with the SPI clock from Master device. - */ - do - { - if (count == 0U) - { - break; - } - count--; - } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); - } - - - /* Control if the RX fifo is empty */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief Handle the end of the RXTX transaction. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) -{ - uint32_t tickstart; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); - - /* Check the end of the transaction */ - if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->State = HAL_SPI_STATE_READY; - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - else - { -#endif /* USE_SPI_CRC */ - if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - if (hspi->State == HAL_SPI_STATE_BUSY_RX) - { - hspi->State = HAL_SPI_STATE_READY; - /* Call user Rx complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->RxCpltCallback(hspi); -#else - HAL_SPI_RxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - else - { - hspi->State = HAL_SPI_STATE_READY; - /* Call user TxRx complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->TxRxCpltCallback(hspi); -#else - HAL_SPI_TxRxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - } - else - { - hspi->State = HAL_SPI_STATE_READY; - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } -#if (USE_SPI_CRC != 0U) - } -#endif /* USE_SPI_CRC */ -} - -/** - * @brief Handle the end of the RX transaction. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) -{ - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - - /* Check the end of the transaction */ - if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - hspi->State = HAL_SPI_STATE_READY; - -#if (USE_SPI_CRC != 0U) - /* Check if CRC error occurred */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - else - { -#endif /* USE_SPI_CRC */ - if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - /* Call user Rx complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->RxCpltCallback(hspi); -#else - HAL_SPI_RxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - else - { - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } -#if (USE_SPI_CRC != 0U) - } -#endif /* USE_SPI_CRC */ -} - -/** - * @brief Handle the end of the TX transaction. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) -{ - uint32_t tickstart; - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - /* Disable TXE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check the end of the transaction */ - if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Clear overrun flag in 2 Lines communication mode because received is not read */ - if (hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - else - { - /* Call user Rx complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) - hspi->TxCpltCallback(hspi); -#else - HAL_SPI_TxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Handle abort a Rx transaction. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) -{ - __IO uint32_t count; - - /* Disable SPI Peripheral */ - __HAL_SPI_DISABLE(hspi); - - count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - - /* Disable RXNEIE interrupt */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); - - /* Check RXNEIE is disabled */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); - - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - hspi->State = HAL_SPI_STATE_ABORT; -} - -/** - * @brief Handle abort a Tx or Rx/Tx transaction. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) -{ - __IO uint32_t count; - - count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); - - /* Disable TXEIE interrupt */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); - - /* Check TXEIE is disabled */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); - - if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Disable SPI Peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ - if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) - { - /* Disable RXNEIE interrupt */ - CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); - - /* Check RXNEIE is disabled */ - do - { - if (count == 0U) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - count--; - } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); - - /* Control the BSY flag */ - if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - - /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - } - hspi->State = HAL_SPI_STATE_ABORT; -} - -/** - * @} - */ - -#endif /* HAL_SPI_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_spi.c + * @author MCD Application Team + * @brief SPI HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Serial Peripheral Interface (SPI) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + The SPI HAL driver can be used as follows: + + (#) Declare a SPI_HandleTypeDef handle structure, for example: + SPI_HandleTypeDef hspi; + + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: + (##) Enable the SPIx interface clock + (##) SPI pins configuration + (+++) Enable the clock for the SPI GPIOs + (+++) Configure these SPI pins as alternate function push-pull + (##) NVIC configuration if you need to use interrupt process + (+++) Configure the SPIx interrupt priority + (+++) Enable the NVIC SPI IRQ handle + (##) DMA Configuration if you need to use DMA process + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel + (+++) Enable the DMAx clock + (+++) Configure the DMA handle parameters + (+++) Configure the DMA Tx or Rx Stream/Channel + (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel + + (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS + management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. + + (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_SPI_MspInit() API. + [..] + Circular mode restriction: + (#) The DMA circular mode cannot be used when the SPI is configured in these modes: + (##) Master 2Lines RxOnly + (##) Master 1Line Rx + (#) The CRC feature is not managed when the DMA circular mode is enabled + (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs + the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks + [..] + Master Receive mode restriction: + (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or + bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI + does not initiate a new transfer the following procedure has to be respected: + (##) HAL_SPI_DeInit() + (##) HAL_SPI_Init() + [..] + Callback registration: + + (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. + + Function HAL_SPI_RegisterCallback() allows to register following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + + (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default + weak function. + HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (++) TxCpltCallback : SPI Tx Completed callback + (++) RxCpltCallback : SPI Rx Completed callback + (++) TxRxCpltCallback : SPI TxRx Completed callback + (++) TxHalfCpltCallback : SPI Tx Half Completed callback + (++) RxHalfCpltCallback : SPI Rx Half Completed callback + (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback + (++) ErrorCallback : SPI Error callback + (++) AbortCpltCallback : SPI Abort callback + (++) MspInitCallback : SPI Msp Init callback + (++) MspDeInitCallback : SPI Msp DeInit callback + + [..] + By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when + these callbacks are null (not registered beforehand). + If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + + [..] + Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() + or HAL_SPI_Init() function. + + [..] + When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registering feature is not available + and weak (surcharged) callbacks are used. + + [..] + Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes, + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance. + + @endverbatim + + Additional table : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Transfer mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Transfer mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/2 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/8 | Fpclk/16 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/4 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/4 | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | NA | NA | Fpclk/8 | Fpclk/16 | + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), + SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). + @note + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() + (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() + (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() + + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup SPI SPI + * @brief SPI HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_DEFAULT_TIMEOUT 100U +#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 us */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); +static void SPI_DMAError(DMA_HandleTypeDef *hdma); +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPIx peripheral: + + (+) User must implement HAL_SPI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function HAL_SPI_Init() to configure the selected device with + the selected configuration: + (++) Mode + (++) Direction + (++) Data Size + (++) Clock Polarity and Phase + (++) NSS Management + (++) BaudRate Prescaler + (++) FirstBit + (++) TIMode + (++) CRC Calculation + (++) CRC Polynomial if CRC enabled + (++) CRC Length, used only with Data8 and Data16 + (++) FIFO reception threshold + + (+) Call the function HAL_SPI_DeInit() to restore the default configuration + of the selected SPIx peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the SPI according to the specified parameters + * in the SPI_InitTypeDef and initialize the associated handle. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) +{ + uint32_t frxth; + + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + assert_param(IS_SPI_MODE(hspi->Init.Mode)); + assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); + assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); + assert_param(IS_SPI_NSS(hspi->Init.NSS)); + assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); + assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); + if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) + { + assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); + assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); + + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + } + else + { + /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */ + hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; + } + } + else + { + assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); + + /* Force polarity and phase to TI protocaol requirements */ + hspi->Init.CLKPolarity = SPI_POLARITY_LOW; + hspi->Init.CLKPhase = SPI_PHASE_1EDGE; + } +#if (USE_SPI_CRC != 0U) + assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); + assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); + } +#else + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; +#endif /* USE_SPI_CRC */ + + if (hspi->State == HAL_SPI_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hspi->Lock = HAL_UNLOCKED; + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + /* Init the SPI Callback settings */ + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + + if (hspi->MspInitCallback == NULL) + { + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hspi->MspInitCallback(hspi); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SPI_MspInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the selected SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Align by default the rs fifo threshold on the data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + frxth = SPI_RXFIFO_THRESHOLD_HF; + } + else + { + frxth = SPI_RXFIFO_THRESHOLD_QF; + } + + /* CRC calculation is valid only for 16Bit and 8 Bit */ + if ((hspi->Init.DataSize != SPI_DATASIZE_16BIT) && (hspi->Init.DataSize != SPI_DATASIZE_8BIT)) + { + /* CRC must be disabled */ + hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; + } + + /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ + /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, + Communication speed, First bit and CRC calculation state */ + WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) | + (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) | + (hspi->Init.CLKPolarity & SPI_CR1_CPOL) | + (hspi->Init.CLKPhase & SPI_CR1_CPHA) | + (hspi->Init.NSS & SPI_CR1_SSM) | + (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) | + (hspi->Init.FirstBit & SPI_CR1_LSBFIRST) | + (hspi->Init.CRCCalculation & SPI_CR1_CRCEN))); +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCL Configuration -------------------*/ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Align the CRC Length on the data size */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) + { + /* CRC Length aligned on the data size : value set by default */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT; + } + else + { + hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT; + } + } + + /* Configure : CRC Length */ + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCL); + } + } +#endif /* USE_SPI_CRC */ + + /* Configure : NSS management, TI Mode, NSS Pulse, Data size and Rx Fifo threshold */ + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | + (hspi->Init.TIMode & SPI_CR2_FRF) | + (hspi->Init.NSSPMode & SPI_CR2_NSSP) | + (hspi->Init.DataSize & SPI_CR2_DS_Msk) | + (frxth & SPI_CR2_FRXTH))); + +#if (USE_SPI_CRC != 0U) + /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ + /* Configure : CRC Polynomial */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk)); + } +#endif /* USE_SPI_CRC */ + +#if defined(SPI_I2SCFGR_I2SMOD) + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); +#endif /* SPI_I2SCFGR_I2SMOD */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_READY; + + return HAL_OK; +} + +/** + * @brief De-Initialize the SPI peripheral. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) +{ + /* Check the SPI handle allocation */ + if (hspi == NULL) + { + return HAL_ERROR; + } + + /* Check SPI Instance parameter */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); + + hspi->State = HAL_SPI_STATE_BUSY; + + /* Disable the SPI Peripheral Clock */ + __HAL_SPI_DISABLE(hspi); + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + if (hspi->MspDeInitCallback == NULL) + { + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + hspi->MspDeInitCallback(hspi); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ + HAL_SPI_MspDeInit(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->State = HAL_SPI_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspInit should be implemented in the user file + */ +} + +/** + * @brief De-Initialize the SPI MSP. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_MspDeInit should be implemented in the user file + */ +} + +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) +/** + * @brief Register a User SPI Callback + * To be used instead of the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be registered + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = pCallback; + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = pCallback; + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = pCallback; + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = pCallback; + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = pCallback; + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = pCallback; + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} + +/** + * @brief Unregister an SPI Callback + * SPI callback is redirected to the weak predefined callback + * @param hspi Pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI. + * @param CallbackID ID of the callback to be unregistered + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(hspi); + + if (HAL_SPI_STATE_READY == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_TX_COMPLETE_CB_ID : + hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_SPI_RX_COMPLETE_CB_ID : + hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_SPI_TX_RX_COMPLETE_CB_ID : + hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_SPI_TX_HALF_COMPLETE_CB_ID : + hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_SPI_RX_HALF_COMPLETE_CB_ID : + hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : + hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ + break; + + case HAL_SPI_ERROR_CB_ID : + hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_SPI_ABORT_CB_ID : + hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_SPI_STATE_RESET == hspi->State) + { + switch (CallbackID) + { + case HAL_SPI_MSPINIT_CB_ID : + hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_SPI_MSPDEINIT_CB_ID : + hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); + + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hspi); + return status; +} +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SPI + data transfers. + + [..] The SPI supports master and slave mode : + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These APIs return the HAL status. + The end of the data processing will be indicated through the + dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected + + (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) + exist for 1Line (simplex) and 2Lines (full duplex) modes. + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t initial_TxXferCount; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + initial_TxXferCount = Size; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + /* Transmit data in 16 Bit mode */ + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + /* Transmit data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr ++; + hspi->TxXferCount--; + } + } + while (hspi->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) + { + if (hspi->TxXferCount > 1U) + { + /* write on the data register in packing mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms + * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data + */ +HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + uint32_t tickstart; + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); + } + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + /* this is done to handle the CRCNEXT before the latest data */ + hspi->RxXferCount--; + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Configure communication direction: 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Receive data in 8 Bit mode */ + if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + /* read the received data */ + (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint8_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + else + { + /* Transfer loop */ + while (hspi->RxXferCount > 0U) + { + /* Check the RXNE flag */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + } + else + { + /* Timeout management */ + if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Handle the CRC Transmission */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* freeze the CRC before the latest data */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + + /* Read the latest data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* the latest data has not been received */ + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + + /* Receive last data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + } + /* Receive last data in 8 Bit mode */ + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + } + + /* Wait the CRC data */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + + /* Read CRC to Flush DR and RXNE flag */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit and Receive an amount of data in blocking mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint16_t initial_TxXferCount; + uint16_t initial_RxXferCount; + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + uint32_t spi_cr1; + uint32_t spi_cr2; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + + /* Variable used to alternate Rx and Tx during transfer */ + uint32_t txallowed = 1U; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + initial_TxXferCount = Size; + initial_RxXferCount = Size; +#if (USE_SPI_CRC != 0U) + spi_cr1 = READ_REG(hspi->Instance->CR1); + spi_cr2 = READ_REG(hspi->Instance->CR2); +#endif /* USE_SPI_CRC */ + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferCount = Size; + hspi->RxXferSize = Size; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferCount = Size; + hspi->TxXferSize = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the Rx Fifo threshold */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (initial_RxXferCount > 1U)) + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set fiforxthreshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Transmit and Receive data in 16 Bit mode */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Check RXNE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + /* Transmit and Receive data in 8 Bit mode */ + else + { + if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) + { + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + } + while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U)) + { + /* Check TXE flag */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) + { + if (hspi->TxXferCount > 1U) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + else + { + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + /* Next Data is a reception (Rx). Tx not allowed */ + txallowed = 0U; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + /* Set NSS Soft to received correctly the CRC on slave mode with NSS pulse activated */ + if ((READ_BIT(spi_cr1, SPI_CR1_MSTR) == 0U) && (READ_BIT(spi_cr2, SPI_CR2_NSSP) == SPI_CR2_NSSP)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_SSM); + } + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + } + + /* Wait until RXNE flag is reset */ + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U)) + { + if (hspi->RxXferCount > 1U) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount <= 1U) + { + /* Set RX Fifo threshold before to switch on 8 bit data size */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + else + { + (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR; + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + } + /* Next Data is a Transmission (Tx). Tx is allowed */ + txallowed = 1U; + } + if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) + { + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + } + } + +#if (USE_SPI_CRC != 0U) + /* Read CRC from DR to close CRC calculation process */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until TXE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + /* Read CRC */ + if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } + } + + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + /* Clear CRC Flag */ + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + return HAL_ERROR; + } + else + { + return HAL_OK; + } +} + +/** + * @brief Transmit an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + hspi->RxISR = NULL; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + } + + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pTxBuffPtr = (uint8_t *)NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + hspi->TxISR = NULL; + + /* Check the data size to adapt Rx threshold and the set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + /* Set RX Fifo threshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_RxISR_8BIT; + } + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } + SPI_RESET_CRC(hspi); + } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ + + /* Note : The SPI must be enabled after unlocking current process + to avoid the risk of SPI interrupt handle execution before current + process unlock */ + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || \ + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Set the function for IT treatment */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->CRCSize = 1U; + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)) + { + hspi->CRCSize = 2U; + } + SPI_RESET_CRC(hspi); + } + else + { + hspi->CRCSize = 0U; + } +#endif /* USE_SPI_CRC */ + + /* Check if packing mode is enabled and if there is more than 2 data to receive */ + if ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (Size >= 2U)) + { + /* Set RX Fifo threshold according the reception data length: 16 bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8 bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + return HAL_OK; +} + +/** + * @brief Transmit an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) +{ + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_TX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->pRxBuffPtr = (uint8_t *)NULL; + hspi->TxISR = NULL; + hspi->RxISR = NULL; + hspi->RxXferSize = 0U; + hspi->RxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_TX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Set the SPI TxDMA Half transfer complete callback */ + hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; + + /* Set the SPI TxDMA transfer complete callback */ + hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; + + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmatx->XferAbortCallback = NULL; + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + /* Packing mode is enabled only if the DMA setting is HALWORD */ + if ((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)) + { + /* Check the even/odd of the data size + crc if enabled */ + if ((hspi->TxXferCount & 0x1U) == 0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U); + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in non-blocking mode with DMA. + * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pData pointer to data buffer (u8 or u16 data elements) + * @note When the CRC feature is enabled the pData Length must be Size + 1. + * @param Size amount of data elements (u8 or u16) to be received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +{ + /* Check rx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + + if (hspi->State != HAL_SPI_STATE_READY) + { + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + hspi->State = HAL_SPI_STATE_BUSY_RX; + + /* Check tx dma handle */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + } + + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Set the transaction information */ + hspi->State = HAL_SPI_STATE_BUSY_RX; + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pRxBuffPtr = (uint8_t *)pData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /*Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + hspi->TxXferSize = 0U; + hspi->TxXferCount = 0U; + + /* Configure communication direction : 1Line */ + if (hspi->Init.Direction == SPI_DIRECTION_1LINE) + { + /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */ + __HAL_SPI_DISABLE(hspi); + SPI_1LINE_RX(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } + } + + /* Set the SPI RxDMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + + /* Set the SPI Rx DMA transfer complete callback */ + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + return HAL_OK; +} + +/** + * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @note When the CRC feature is enabled the pRxData Length must be Size + 1 + * @param Size amount of data elements (u8 or u16) to be sent and received + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + uint32_t tmp_mode; + HAL_SPI_StateTypeDef tmp_state; + + /* Check rx & tx dma handles */ + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); + + /* Check Direction parameter */ + assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); + + /* Init temporary variables */ + tmp_state = hspi->State; + tmp_mode = hspi->Init.Mode; + + if (!((tmp_state == HAL_SPI_STATE_READY) || + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + { + return HAL_BUSY; + } + + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process locked */ + __HAL_LOCK(hspi); + + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ + if (hspi->State != HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_BUSY_TX_RX; + } + + /* Set the transaction information */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; + hspi->TxXferSize = Size; + hspi->TxXferCount = Size; + hspi->pRxBuffPtr = (uint8_t *)pRxData; + hspi->RxXferSize = Size; + hspi->RxXferCount = Size; + + /* Init field not used in handle to zero */ + hspi->RxISR = NULL; + hspi->TxISR = NULL; + +#if (USE_SPI_CRC != 0U) + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } +#endif /* USE_SPI_CRC */ + + /* Reset the threshold bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX | SPI_CR2_LDMARX); + + /* The packing mode management is enabled by the DMA settings according the spi data size */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Set fiforxthreshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + else + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + if ((hspi->TxXferSize & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = hspi->TxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX); + hspi->TxXferCount = (hspi->TxXferCount >> 1U) + 1U; + } + } + + if (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) + { + /* Set RX Fifo threshold according the reception data length: 16bit */ + CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + + if ((hspi->RxXferCount & 0x1U) == 0x0U) + { + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = hspi->RxXferCount >> 1U; + } + else + { + SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); + hspi->RxXferCount = (hspi->RxXferCount >> 1U) + 1U; + } + } + } + + /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + /* Set the SPI Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; + } + else + { + /* Set the SPI Tx/Rx DMA Half transfer complete callback */ + hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; + } + + /* Set the DMA error callback */ + hspi->hdmarx->XferErrorCallback = SPI_DMAError; + + /* Set the DMA AbortCpltCallback */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Enable the Rx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, + hspi->RxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Enable Rx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing + is performed in DMA reception complete callback */ + hspi->hdmatx->XferHalfCpltCallback = NULL; + hspi->hdmatx->XferCpltCallback = NULL; + hspi->hdmatx->XferErrorCallback = NULL; + hspi->hdmatx->XferAbortCallback = NULL; + + /* Enable the Tx DMA Stream/Channel */ + if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, + hspi->TxXferCount)) + { + /* Update SPI error code */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; + } + + /* Check if the SPI is already enabled */ + if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) + { + /* Enable SPI peripheral */ + __HAL_SPI_ENABLE(hspi); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + /* Enable the SPI Error Interrupt Bit */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); + + /* Enable Tx DMA Request */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfer (blocking mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + } + + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = NULL; + + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN)); + } + } + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->state to ready */ + hspi->State = HAL_SPI_STATE_READY; + + return errorcode; +} + +/** + * @brief Abort ongoing transfer (Interrupt mode). + * @param hspi SPI handle. + * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), + * started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable SPI Interrupts (depending of transfer direction) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode; + uint32_t abortcplt ; + __IO uint32_t count; + __IO uint32_t resetcount; + + /* Initialized local variable */ + errorcode = HAL_OK; + abortcplt = 1U; + resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + count = resetcount; + + /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE); + + /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)) + { + hspi->TxISR = SPI_AbortTx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + hspi->RxISR = SPI_AbortRx_ISR; + /* Wait HAL_SPI_STATE_ABORT state */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (hspi->State != HAL_SPI_STATE_ABORT); + /* Reset Timeout Counter */ + count = resetcount; + } + + /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (hspi->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; + } + else + { + hspi->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (hspi->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; + } + else + { + hspi->hdmarx->XferAbortCallback = NULL; + } + } + + /* Disable the SPI DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN)) + { + /* Abort the SPI DMA Tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + /* Abort DMA Tx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) + { + hspi->hdmatx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + /* Disable the SPI DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN)) + { + /* Abort the SPI DMA Rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + /* Abort DMA Rx Handle linked to SPI Peripheral */ + if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) + { + hspi->hdmarx->XferAbortCallback = NULL; + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + else + { + abortcplt = 0U; + } + } + } + + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check error during Abort procedure */ + if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT) + { + /* return HAL_Error in case of error during Abort procedure */ + errorcode = HAL_ERROR; + } + else + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + + return errorcode; +} + +/** + * @brief Pause the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) +{ + /* Process Locked */ + __HAL_LOCK(hspi); + + /* Enable the SPI DMA Tx & Rx requests */ + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) +{ + HAL_StatusTypeDef errorcode = HAL_OK; + /* The Lock is not implemented on this API to allow the user application + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): + when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() + */ + + /* Abort the SPI DMA tx Stream/Channel */ + if (hspi->hdmatx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + /* Abort the SPI DMA rx Stream/Channel */ + if (hspi->hdmarx != NULL) + { + if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + errorcode = HAL_ERROR; + } + } + + /* Disable the SPI DMA Tx & Rx requests */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + hspi->State = HAL_SPI_STATE_READY; + return errorcode; +} + +/** + * @brief Handle SPI interrupt request. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval None + */ +void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) +{ + uint32_t itsource = hspi->Instance->CR2; + uint32_t itflag = hspi->Instance->SR; + + /* SPI in mode Receiver ----------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) && + (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET)) + { + hspi->RxISR(hspi); + return; + } + + /* SPI in mode Transmitter -------------------------------------------------*/ + if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET)) + { + hspi->TxISR(hspi); + return; + } + + /* SPI in Error Treatment --------------------------------------------------*/ + if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) + { + /* SPI Overrun error interrupt occurred ----------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) + { + if (hspi->State != HAL_SPI_STATE_BUSY_TX) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + else + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + return; + } + } + + /* SPI Mode Fault error interrupt occurred -------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); + __HAL_SPI_CLEAR_MODFFLAG(hspi); + } + + /* SPI Frame error interrupt occurred ------------------------------------*/ + if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); + __HAL_SPI_CLEAR_FREFLAG(hspi); + } + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Disable all interrupts */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); + + hspi->State = HAL_SPI_STATE_READY; + /* Disable the SPI DMA requests if enabled */ + if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN))) + { + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN)); + + /* Abort the SPI DMA Rx channel */ + if (hspi->hdmarx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + /* Abort the SPI DMA Tx channel */ + if (hspi->hdmatx != NULL) + { + /* Set the SPI DMA Abort callback : + will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ + hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; + if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + } + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxHalfCpltCallback should be implemented in the user file + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief Tx and Rx Half Transfer callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file + */ +} + +/** + * @brief SPI error callback. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_ErrorCallback should be implemented in the user file + */ + /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes + and user can use HAL_SPI_GetError() API to check the latest error occurred + */ +} + +/** + * @brief SPI Abort Complete callback. + * @param hspi SPI handle. + * @retval None + */ +__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hspi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SPI_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions + * @brief SPI control functions + * +@verbatim + =============================================================================== + ##### Peripheral State and Errors functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SPI. + (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral + (+) HAL_SPI_GetError() check in run-time Errors occurring during communication +@endverbatim + * @{ + */ + +/** + * @brief Return the SPI handle state. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI state + */ +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI handle state */ + return hspi->State; +} + +/** + * @brief Return the SPI error code. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval SPI error code in bitmap format + */ +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) +{ + /* Return SPI ErrorCode */ + return hspi->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup SPI_Private_Functions + * @brief Private functions + * @{ + */ + +/** + * @brief DMA SPI transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received data is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->TxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Tx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Wait until RXNE flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC */ + if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + /* Read 16bit CRC */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + else + { + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + if (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + } + } +#endif /* USE_SPI_CRC */ + + /* Check if we are in Master RX 2 line mode */ + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) + { + /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + } + else + { + /* Normal case */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + } + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + } + + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; +#endif /* USE_SPI_CRC */ + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* DMA Normal Mode */ + if ((hdma->Instance->CR & DMA_SxCR_CIRC) != DMA_SxCR_CIRC) + { + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + +#if (USE_SPI_CRC != 0U) + /* CRC handling */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + if ((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT)) + { + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + else + { + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) + { + /* Error on the CRC reception */ + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + } + /* Read CRC to Flush DR and RXNE flag */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + } + } +#endif /* USE_SPI_CRC */ + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Disable Rx/Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + hspi->TxXferCount = 0U; + hspi->RxXferCount = 0U; + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR)) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + } +#endif /* USE_SPI_CRC */ + + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + return; + } + } + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user Tx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxHalfCpltCallback(hspi); +#else + HAL_SPI_TxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half receive process complete callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user Rx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxHalfCpltCallback(hspi); +#else + HAL_SPI_RxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI half transmit receive process complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Call user TxRx half complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxHalfCpltCallback(hspi); +#else + HAL_SPI_TxRxHalfCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication error callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void SPI_DMAError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Stop the disable DMA transfer on SPI side */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); + + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + hspi->hdmatx->XferAbortCallback = NULL; + + /* Disable Tx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmarx != NULL) + { + if (hspi->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SPI Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + hspi->hdmarx->XferAbortCallback = NULL; + + /* Disable Rx DMA Request */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check if an Abort process is still ongoing */ + if (hspi->hdmatx != NULL) + { + if (hspi->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */ + hspi->RxXferCount = 0U; + hspi->TxXferCount = 0U; + + /* Check no error during Abort procedure */ + if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT) + { + /* Reset errorCode */ + hspi->ErrorCode = HAL_SPI_ERROR_NONE; + } + + /* Clear the Error flags in the SR register */ + __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_FREFLAG(hspi); + + /* Restore hspi->State to Ready */ + hspi->State = HAL_SPI_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->AbortCpltCallback(hspi); +#else + HAL_SPI_AbortCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ +} + +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in packing mode */ + if (hspi->RxXferCount > 1U) + { + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount -= 2U; + if (hspi->RxXferCount == 1U) + { + /* Set RX Fifo threshold according the reception data length: 8bit */ + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + } + } + /* Receive data in 8 Bit mode */ + else + { + *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + } + + /* Check end of the reception */ + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + hspi->CRCSize--; + + /* Check end of the reception */ + if (hspi->CRCSize == 0U) + { + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in packing Bit mode */ + if (hspi->TxXferCount >= 2U) + { + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount -= 2U; + } + /* Transmit data in 8 Bit mode */ + else + { + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + } + + /* Check the end of the transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if (hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Set CRC Next Bit to send CRC */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if (hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + /* Read 8bit CRC to flush Data Register */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + + hspi->CRCSize--; + + if (hspi->CRCSize == 0U) + { + SPI_CloseRx_ISR(hspi); + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->pRxBuffPtr++; + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg = 0U; + + /* Read 16bit CRC to flush Data Register */ + tmpreg = READ_REG(hspi->Instance->DR); + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR); + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if (hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr++; + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if (hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag SPI flag to check + * @param State flag state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U); + + while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State) + { + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + { + tmp_timeout = 0U; + } + else + { + count--; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle SPI FIFO Communication Timeout. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Fifo Fifo to check + * @param State Fifo state to check + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, + uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + uint32_t tmp_timeout; + uint32_t tmp_tickstart; + __IO const uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + + /* Adjust Timeout value in case of end of transfer */ + tmp_timeout = Timeout - (HAL_GetTick() - Tickstart); + tmp_tickstart = HAL_GetTick(); + + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; + + /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */ + count = tmp_timeout * ((SystemCoreClock * 35U) >> 20U); + + while ((hspi->Instance->SR & Fifo) != State) + { + if ((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY)) + { + /* Flush Data Register by a blank read */ + tmpreg8 = *ptmpreg8; + /* To avoid GCC warning */ + UNUSED(tmpreg8); + } + + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ + if (count == 0U) + { + tmp_timeout = 0U; + } + else + { + count--; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle the check of the RX transaction complete. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else /* SPI_MODE_SLAVE */ + { + /* Timeout in us */ + count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + + /* Wait BSY flag during 1 Byte time transfer in case of Rx transfer + * If Timeout is reached, the transfer is considered as finish. + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + { + break; + } + count--; + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + } + + if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE) + || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @brief Handle the check of the RXTX or TX transaction complete. + * @param hspi SPI handle + * @param Timeout Timeout duration + * @param Tickstart tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + __IO uint32_t count; + + /* Control if the TX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + /* Timeout in us */ + count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U); + /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */ + if (hspi->Init.Mode == SPI_MODE_MASTER) + { + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + } + else + { + /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer + * If Timeout is reached, the transfer is considered as finish. + * User have to calculate the timeout value to fit with the time of 1 byte transfer. + * This time is directly link with the SPI clock from Master device. + */ + do + { + if (count == 0U) + { + break; + } + count--; + } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET); + } + + + /* Control if the RX fifo is empty */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if (hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user TxRx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxRxCpltCallback(hspi); +#else + HAL_SPI_TxRxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the RX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { +#endif /* USE_SPI_CRC */ + if (hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->RxCpltCallback(hspi); +#else + HAL_SPI_RxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart; + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if (hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + /* Call user error callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->ErrorCallback(hspi); +#else + HAL_SPI_ErrorCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } + else + { + /* Call user Rx complete callback */ +#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) + hspi->TxCpltCallback(hspi); +#else + HAL_SPI_TxCpltCallback(hspi); +#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Handle abort a Rx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count; + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @brief Handle abort a Tx or Rx/Tx transaction. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) +{ + __IO uint32_t count; + + count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U); + + /* Disable TXEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE)); + + /* Check TXEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE)); + + if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Disable SPI Peripheral */ + __HAL_SPI_DISABLE(hspi); + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Check case of Full-Duplex Mode and disable directly RXNEIE interrupt */ + if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)) + { + /* Disable RXNEIE interrupt */ + CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXNEIE)); + + /* Check RXNEIE is disabled */ + do + { + if (count == 0U) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); + break; + } + count--; + } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE)); + + /* Control the BSY flag */ + if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + + /* Empty the FRLVL fifo */ + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) + { + hspi->ErrorCode = HAL_SPI_ERROR_ABORT; + } + } + hspi->State = HAL_SPI_STATE_ABORT; +} + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c index 6351d32c..9aa992c5 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_spi_ex.c @@ -1,112 +1,112 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_spi_ex.c - * @author MCD Application Team - * @brief Extended SPI HAL module driver. - * This file provides firmware functions to manage the following - * SPI peripheral extended functionalities : - * + IO operation functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SPIEx SPIEx - * @brief SPI Extended HAL module driver - * @{ - */ -#ifdef HAL_SPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup SPIEx_Private_Constants SPIEx Private Constants - * @{ - */ -#define SPI_FIFO_SIZE 4UL -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions - * @{ - */ - -/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions - * @brief Data transfers functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of extended functions to manage the SPI - data transfers. - - (#) Rx data flush function: - (++) HAL_SPIEx_FlushRxFifo() - -@endverbatim - * @{ - */ - -/** - * @brief Flush the RX fifo. - * @param hspi pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) -{ - __IO uint32_t tmpreg; - uint8_t count = 0U; - while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) - { - count++; - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - if (count == SPI_FIFO_SIZE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_SPI_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_spi_ex.c + * @author MCD Application Team + * @brief Extended SPI HAL module driver. + * This file provides firmware functions to manage the following + * SPI peripheral extended functionalities : + * + IO operation functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup SPIEx SPIEx + * @brief SPI Extended HAL module driver + * @{ + */ +#ifdef HAL_SPI_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup SPIEx_Private_Constants SPIEx Private Constants + * @{ + */ +#define SPI_FIFO_SIZE 4UL +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions + * @{ + */ + +/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of extended functions to manage the SPI + data transfers. + + (#) Rx data flush function: + (++) HAL_SPIEx_FlushRxFifo() + +@endverbatim + * @{ + */ + +/** + * @brief Flush the RX fifo. + * @param hspi pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) +{ + __IO uint32_t tmpreg; + uint8_t count = 0U; + while ((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_FRLVL_EMPTY) + { + count++; + tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* To avoid GCC warning */ + if (count == SPI_FIFO_SIZE) + { + return HAL_TIMEOUT; + } + } + return HAL_OK; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_SPI_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c deleted file mode 100644 index a95df692..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c +++ /dev/null @@ -1,1112 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_sram.c - * @author MCD Application Team - * @brief SRAM HAL module driver. - * This file provides a generic firmware to drive SRAM memories - * mounted as external device. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a generic layered driver which contains a set of APIs used to - control SRAM memories. It uses the FMC layer functions to interface - with SRAM devices. - The following sequence should be followed to configure the FMC to interface - with SRAM/PSRAM memories: - - (#) Declare a SRAM_HandleTypeDef handle structure, for example: - SRAM_HandleTypeDef hsram; and: - - (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed - values of the structure member. - - (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined - base register instance for NOR or SRAM device - - (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined - base register instance for NOR or SRAM extended mode - - (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended - mode timings; for example: - FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; - and fill its fields with the allowed values of the structure member. - - (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function - performs the following sequence: - - (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() - (##) Control register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Init() - (##) Timing register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Timing_Init() - (##) Extended mode Timing register configuration using the FMC NORSRAM interface function - FMC_NORSRAM_Extended_Timing_Init() - (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() - - (#) At this stage you can perform read/write accesses from/to the memory connected - to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the - following APIs: - (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access - (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer - - (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ - HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation - - (#) You can continuously monitor the SRAM device HAL state by calling the function - HAL_SRAM_GetState() - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - Use Functions HAL_SRAM_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) MspInitCallback : SRAM MspInit. - (+) MspDeInitCallback : SRAM MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. It allows to reset following callbacks: - (+) MspInitCallback : SRAM MspInit. - (+) MspDeInitCallback : SRAM MspDeInit. - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the HAL_SRAM_Init - and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit - or HAL_SRAM_Init function. - - When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_SRAM_MODULE_ENABLED - -/** @defgroup SRAM SRAM - * @brief SRAM driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup SRAM_Private_Functions SRAM Private Functions - * @{ - */ -static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); -static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); -static void SRAM_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SRAM_Exported_Functions SRAM Exported Functions - * @{ - */ - -/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * - @verbatim - ============================================================================== - ##### SRAM Initialization and de_initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to initialize/de-initialize - the SRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Performs the SRAM device initialization sequence - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param Timing Pointer to SRAM control timing structure - * @param ExtTiming Pointer to SRAM extended mode timing structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, - FMC_NORSRAM_TimingTypeDef *ExtTiming) -{ - /* Check the SRAM handle parameter */ - if (hsram == NULL) - { - return HAL_ERROR; - } - - if (hsram->State == HAL_SRAM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hsram->Lock = HAL_UNLOCKED; - -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if (hsram->MspInitCallback == NULL) - { - hsram->MspInitCallback = HAL_SRAM_MspInit; - } - hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Init the low level hardware */ - hsram->MspInitCallback(hsram); -#else - /* Initialize the low level hardware (MSP) */ - HAL_SRAM_MspInit(hsram); -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ - } - - /* Initialize SRAM control Interface */ - (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); - - /* Initialize SRAM timing Interface */ - (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); - - /* Initialize SRAM extended mode timing Interface */ - (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, - hsram->Init.ExtendedMode); - - /* Enable the NORSRAM device */ - __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); - - /* Initialize the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Performs the SRAM device De-initialization sequence. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) -{ -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if (hsram->MspDeInitCallback == NULL) - { - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - } - - /* DeInit the low level hardware */ - hsram->MspDeInitCallback(hsram); -#else - /* De-Initialize the low level hardware (MSP) */ - HAL_SRAM_MspDeInit(hsram); -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ - - /* Configure the SRAM registers with their reset values */ - (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); - - /* Reset the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hsram); - - return HAL_OK; -} - -/** - * @brief SRAM MSP Init. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsram); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_MspInit could be implemented in the user file - */ -} - -/** - * @brief SRAM MSP DeInit. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hsram); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete callback. - * @param hdma pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file - */ -} - -/** - * @brief DMA transfer complete error callback. - * @param hdma pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval None - */ -__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hdma); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions - * @brief Input Output and memory control functions - * - @verbatim - ============================================================================== - ##### SRAM Input and Output functions ##### - ============================================================================== - [..] - This section provides functions allowing to use and control the SRAM memory - -@endverbatim - * @{ - */ - -/** - * @brief Reads 8-bit buffer from SRAM memory. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer - * @param BufferSize Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint8_t *psramaddress = (uint8_t *)pAddress; - uint8_t *pdestbuff = pDstBuffer; - HAL_SRAM_StateTypeDef state = hsram->State; - - /* Check the SRAM controller state */ - if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for (size = BufferSize; size != 0U; size--) - { - *pdestbuff = *psramaddress; - pdestbuff++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = state; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Writes 8-bit buffer to SRAM memory. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write - * @param BufferSize Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint8_t *psramaddress = (uint8_t *)pAddress; - uint8_t *psrcbuff = pSrcBuffer; - - /* Check the SRAM controller state */ - if (hsram->State == HAL_SRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for (size = BufferSize; size != 0U; size--) - { - *psramaddress = *psrcbuff; - psrcbuff++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Reads 16-bit buffer from SRAM memory. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer - * @param BufferSize Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint32_t *psramaddress = pAddress; - uint16_t *pdestbuff = pDstBuffer; - uint8_t limit; - HAL_SRAM_StateTypeDef state = hsram->State; - - /* Check the SRAM controller state */ - if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Check if the size is a 32-bits multiple */ - limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); - - /* Read data from memory */ - for (size = BufferSize; size != limit; size -= 2U) - { - *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); - pdestbuff++; - *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U); - pdestbuff++; - psramaddress++; - } - - /* Read last 16-bits if size is not 32-bits multiple */ - if (limit != 0U) - { - *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); - } - - /* Update the SRAM controller state */ - hsram->State = state; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Writes 16-bit buffer to SRAM memory. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write - * @param BufferSize Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint32_t *psramaddress = pAddress; - uint16_t *psrcbuff = pSrcBuffer; - uint8_t limit; - - /* Check the SRAM controller state */ - if (hsram->State == HAL_SRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Check if the size is a 32-bits multiple */ - limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); - - /* Write data to memory */ - for (size = BufferSize; size != limit; size -= 2U) - { - *psramaddress = (uint32_t)(*psrcbuff); - psrcbuff++; - *psramaddress |= ((uint32_t)(*psrcbuff) << 16U); - psrcbuff++; - psramaddress++; - } - - /* Write last 16-bits if size is not 32-bits multiple */ - if (limit != 0U) - { - *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U); - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Reads 32-bit buffer from SRAM memory. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer - * @param BufferSize Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint32_t *psramaddress = pAddress; - uint32_t *pdestbuff = pDstBuffer; - HAL_SRAM_StateTypeDef state = hsram->State; - - /* Check the SRAM controller state */ - if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for (size = BufferSize; size != 0U; size--) - { - *pdestbuff = *psramaddress; - pdestbuff++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = state; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Writes 32-bit buffer to SRAM memory. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write - * @param BufferSize Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, - uint32_t BufferSize) -{ - uint32_t size; - __IO uint32_t *psramaddress = pAddress; - uint32_t *psrcbuff = pSrcBuffer; - - /* Check the SRAM controller state */ - if (hsram->State == HAL_SRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Write data to memory */ - for (size = BufferSize; size != 0U; size--) - { - *psramaddress = *psrcbuff; - psrcbuff++; - psramaddress++; - } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Reads a Words data from the SRAM memory using DMA transfer. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer - * @param BufferSize Size of the buffer to read from memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, - uint32_t BufferSize) -{ - HAL_StatusTypeDef status; - HAL_SRAM_StateTypeDef state = hsram->State; - - /* Check the SRAM controller state */ - if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - if (state == HAL_SRAM_STATE_READY) - { - hsram->hdma->XferCpltCallback = SRAM_DMACplt; - } - else - { - hsram->hdma->XferCpltCallback = SRAM_DMACpltProt; - } - hsram->hdma->XferErrorCallback = SRAM_DMAError; - - /* Enable the DMA Stream */ - status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Writes a Words data buffer to SRAM memory using DMA transfer. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write - * @param BufferSize Size of the buffer to write to memory - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, - uint32_t BufferSize) -{ - HAL_StatusTypeDef status; - - /* Check the SRAM controller state */ - if (hsram->State == HAL_SRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = SRAM_DMACplt; - hsram->hdma->XferErrorCallback = SRAM_DMAError; - - /* Enable the DMA Stream */ - status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - status = HAL_ERROR; - } - - return status; -} - -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User SRAM Callback - * To be used to override the weak predefined callback - * @param hsram : SRAM handle - * @param CallbackId : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID - * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, - pSRAM_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_SRAM_StateTypeDef state; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - state = hsram->State; - if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) - { - switch (CallbackId) - { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = pCallback; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a User SRAM Callback - * SRAM Callback is redirected to the weak predefined callback - * @param hsram : SRAM handle - * @param CallbackId : ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_SRAM_MSP_INIT_CB_ID SRAM MspInit callback ID - * @arg @ref HAL_SRAM_MSP_DEINIT_CB_ID SRAM MspDeInit callback ID - * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID - * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_SRAM_StateTypeDef state; - - state = hsram->State; - if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) - { - switch (CallbackId) - { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (state == HAL_SRAM_STATE_RESET) - { - switch (CallbackId) - { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Register a User SRAM Callback for DMA transfers - * To be used to override the weak predefined callback - * @param hsram : SRAM handle - * @param CallbackId : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_SRAM_DMA_XFER_CPLT_CB_ID SRAM DMA Xfer Complete callback ID - * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, - pSRAM_DmaCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - HAL_SRAM_StateTypeDef state; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hsram); - - state = hsram->State; - if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) - { - switch (CallbackId) - { - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = pCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* update return status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hsram); - return status; -} -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief Control functions - * -@verbatim - ============================================================================== - ##### SRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the SRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically SRAM write operation. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) -{ - /* Check the SRAM controller state */ - if (hsram->State == HAL_SRAM_STATE_PROTECTED) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Enable write operation */ - (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Disables dynamically SRAM write operation. - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) -{ - /* Check the SRAM controller state */ - if (hsram->State == HAL_SRAM_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Disable write operation */ - (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### SRAM State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the SRAM controller - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the SRAM controller state - * @param hsram pointer to a SRAM_HandleTypeDef structure that contains - * the configuration information for SRAM module. - * @retval HAL state - */ -HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) -{ - return hsram->State; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup SRAM_Private_Functions SRAM Private Functions - * @{ - */ - -/** - * @brief DMA SRAM process complete callback. - * @param hdma : DMA handle - * @retval None - */ -static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) -{ - SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - hsram->DmaXferCpltCallback(hdma); -#else - HAL_SRAM_DMA_XferCpltCallback(hdma); -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SRAM process complete callback. - * @param hdma : DMA handle - * @retval None - */ -static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) -{ - SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_PROTECTED; - -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - hsram->DmaXferCpltCallback(hdma); -#else - HAL_SRAM_DMA_XferCpltCallback(hdma); -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SRAM error callback. - * @param hdma : DMA handle - * @retval None - */ -static void SRAM_DMAError(DMA_HandleTypeDef *hdma) -{ - SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_ERROR; - -#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - hsram->DmaXferErrorCallback(hdma); -#else - HAL_SRAM_DMA_XferErrorCallback(hdma); -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_SRAM_MODULE_ENABLED */ - -/** - * @} - */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c index 380ce78a..43cac113 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c @@ -1,7897 +1,7894 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + TIM Time Base Initialization - * + TIM Time Base Start - * + TIM Time Base Start Interruption - * + TIM Time Base Start DMA - * + TIM Output Compare/PWM Initialization - * + TIM Output Compare/PWM Channel Configuration - * + TIM Output Compare/PWM Start - * + TIM Output Compare/PWM Start Interruption - * + TIM Output Compare/PWM Start DMA - * + TIM Input Capture Initialization - * + TIM Input Capture Channel Configuration - * + TIM Input Capture Start - * + TIM Input Capture Start Interruption - * + TIM Input Capture Start DMA - * + TIM One Pulse Initialization - * + TIM One Pulse Channel Configuration - * + TIM One Pulse Start - * + TIM Encoder Interface Initialization - * + TIM Encoder Interface Start - * + TIM Encoder Interface Start Interruption - * + TIM Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + TIM OCRef clear configuration - * + TIM External Clock configuration - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to interconnect - several timers together. - (#) Supports incremental encoder for positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an - Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - *** Callback registration *** - ============================================= - - [..] - The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_TIM_RegisterCallback() to register a callback. - HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, - the Callback ID and a pointer to the user callback function. - - [..] - Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - - [..] - These functions allow to register/unregister following callbacks: - (+) Base_MspInitCallback : TIM Base Msp Init Callback. - (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. - (+) IC_MspInitCallback : TIM IC Msp Init Callback. - (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. - (+) OC_MspInitCallback : TIM OC Msp Init Callback. - (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. - (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. - (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. - (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. - (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. - (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. - (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. - (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. - (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. - (+) PeriodElapsedCallback : TIM Period Elapsed Callback. - (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. - (+) TriggerCallback : TIM Trigger Callback. - (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. - (+) IC_CaptureCallback : TIM Input Capture Callback. - (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. - (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. - (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. - (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. - (+) ErrorCallback : TIM Error Callback. - (+) CommutationCallback : TIM Commutation Callback. - (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. - (+) BreakCallback : TIM Break Callback. - (+) Break2Callback : TIM Break2 Callback. - - [..] -By default, after the Init and when the state is HAL_TIM_STATE_RESET -all interrupt callbacks are set to the corresponding weak functions: - examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). - - [..] - Exception done for MspInit and MspDeInit functions that are reset to the legacy weak - functionalities in the Init / DeInit only when these callbacks are null - (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit - keep and use the user MspInit / MspDeInit callbacks(registered beforehand) - - [..] - Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. - Exception done MspInit / MspDeInit that can be registered / unregistered - in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, - thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_TIM_RegisterCallback() before calling DeInit or Init function. - - [..] - When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - const TIM_SlaveConfigTypeDef *sSlaveConfig); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Base_MspInitCallback == NULL) - { - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Base_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Base_MspDeInitCallback == NULL) - { - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Base_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - if (htim->State == HAL_TIM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->State == HAL_TIM_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * -@verbatim - ============================================================================== - ##### TIM Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the TIM Output Compare. - (+) Stop the TIM Output Compare. - (+) Start the TIM Output Compare and enable interrupt. - (+) Stop the TIM Output Compare and disable interrupt. - (+) Start the TIM Output Compare and enable DMA transfer. - (+) Stop the TIM Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OC_MspInitCallback == NULL) - { - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OC_MspDeInitCallback == NULL) - { - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * -@verbatim - ============================================================================== - ##### TIM PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM PWM. - (+) De-initialize the TIM PWM. - (+) Start the TIM PWM. - (+) Stop the TIM PWM. - (+) Start the TIM PWM and enable interrupt. - (+) Stop the TIM PWM and disable interrupt. - (+) Start the TIM PWM and enable DMA transfer. - (+) Stop the TIM PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->PWM_MspInitCallback == NULL) - { - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->PWM_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->PWM_MspDeInitCallback == NULL) - { - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - } - /* DeInit the low level hardware */ - htim->PWM_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * -@verbatim - ============================================================================== - ##### TIM Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the TIM Input Capture. - (+) Stop the TIM Input Capture. - (+) Start the TIM Input Capture and enable interrupt. - (+) Stop the TIM Input Capture and disable interrupt. - (+) Start the TIM Input Capture and enable DMA transfer. - (+) Stop the TIM Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->IC_MspInitCallback == NULL) - { - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->IC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->IC_MspDeInitCallback == NULL) - { - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->IC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture MSP. - * @param htim TIM Input Capture handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * -@verbatim - ============================================================================== - ##### TIM One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the TIM One Pulse. - (+) Stop the TIM One Pulse. - (+) Start the TIM One Pulse and enable interrupt. - (+) Stop the TIM One Pulse and disable interrupt. - (+) Start the TIM One Pulse and enable DMA transfer. - (+) Stop the TIM One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @note When the timer instance is initialized in One Pulse mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM One Pulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OnePulse_MspInitCallback == NULL) - { - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OnePulse_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OnePulse_MspDeInitCallback == NULL) - { - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OnePulse_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * -@verbatim - ============================================================================== - ##### TIM Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the TIM Encoder. - (+) Stop the TIM Encoder. - (+) Start the TIM Encoder and enable interrupt. - (+) Stop the TIM Encoder and disable interrupt. - (+) Start the TIM Encoder and enable DMA transfer. - (+) Stop the TIM Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() - * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together - * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource - * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa - * @note When the timer instance is initialized in Encoder mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) -{ - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Encoder_MspInitCallback == NULL) - { - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Encoder_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the SMS and ECE bits */ - htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - - /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim TIM Encoder Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Encoder_MspDeInitCallback == NULL) - { - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Encoder_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData1 == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData2 == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - - default: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief TIM IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - uint32_t itsource = htim->Instance->DIER; - uint32_t itflag = htim->Instance->SR; - - /* Capture compare 1 event */ - if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) - { - if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) - { - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) - { - if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) - { - if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) - { - if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) - { - if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Break input event */ - if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ - ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) - { - if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->BreakCallback(htim); -#else - HAL_TIMEx_BreakCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Break2 input event */ - if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) - { - if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->Break2Callback(htim); -#else - HAL_TIMEx_Break2Callback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Trigger detection event */ - if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) - { - if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM commutation event */ - if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) - { - if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief TIM Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - const TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 5 in Output Compare */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 6 in Output Compare */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - break; - } - - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_4) - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); - } - else - { - status = HAL_ERROR; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM PWM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be configured - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - const TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - break; - } - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel5*/ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the Channel 6 in PWM mode */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel6 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; - break; - } - - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM output channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM input Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @note To output a waveform with a minimum delay user can enable the fast - * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx - * output is forced in response to the edge detection on TIx input, - * without taking in account the comparison. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel) -{ - HAL_StatusTypeDef status = HAL_OK; - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if (OutputChannel != InputChannel) - { - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Output compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - break; - } - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - default: - status = HAL_ERROR; - break; - } - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_OR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_AF1 (*) - * @arg TIM_DMABASE_AF2 (*) - * (*) value not defined in all devices - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength) -{ - HAL_StatusTypeDef status; - - status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); - - - - return status; -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_OR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_AF1 (*) - * @arg TIM_DMABASE_AF2 (*) - * (*) value not defined in all devices - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_COM: - { - /* Set the DMA commutation callbacks */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA stream) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_COM: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_OR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_AF1 (*) - * @arg TIM_DMABASE_AF2 (*) - * (*) value not defined in all devices - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) -{ - HAL_StatusTypeDef status; - - status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); - - - return status; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_OR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_AF1 (*) - * @arg TIM_DMABASE_AF2 (*) - * (*) value not defined in all devices - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_COM: - { - /* Set the DMA commutation callbacks */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA stream) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_COM: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source - * @note Basic timers can only generate an update event. - * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. - * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant - * only for timer instances supporting break input(s). - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 - * @arg TIM_CHANNEL_6: TIM Channel 6 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - const TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Clear the OCREF clear selection bit and the the ETR Bits */ - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); - break; - } - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ - if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - switch (Channel) - { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - break; - } - case TIM_CHANNEL_5: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 5 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); - } - else - { - /* Disable the OCREF clear feature for Channel 5 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); - } - break; - } - case TIM_CHANNEL_6: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 6 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); - } - else - { - /* Disable the OCREF clear feature for Channel 6 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); - } - break; - } - default: - break; - } - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - break; - } - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - break; - } - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - break; - } - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - break; - } - - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - break; - } - - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - break; - } - - case TIM_CLOCKSOURCE_ITR0: - case TIM_CLOCKSOURCE_ITR1: - case TIM_CLOCKSOURCE_ITR2: - case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } - - default: - status = HAL_ERROR; - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - const TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0U; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - return tmpreg; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) TIM Period elapsed callback - (+) TIM Output Compare callback - (+) TIM Input capture callback - (+) TIM Trigger callback - (+) TIM Error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Period elapsed half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Output Compare callback in non-blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture half complete callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User TIM callback to be used instead of the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID - * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID - * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID - * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID - * @param pCallback pointer to the callback function - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = pCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = pCallback; - break; - - case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = pCallback; - break; - - case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = pCallback; - break; - - case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = pCallback; - break; - - case HAL_TIM_BREAK2_CB_ID : - htim->Break2Callback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a TIM callback - * TIM callback is redirected to the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID - * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID - * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID - * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - /* Legacy weak Base MspInit Callback */ - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - /* Legacy weak Base Msp DeInit Callback */ - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - /* Legacy weak IC Msp Init Callback */ - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - /* Legacy weak IC Msp DeInit Callback */ - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - /* Legacy weak OC Msp Init Callback */ - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - /* Legacy weak OC Msp DeInit Callback */ - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - /* Legacy weak PWM Msp Init Callback */ - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - /* Legacy weak PWM Msp DeInit Callback */ - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - /* Legacy weak One Pulse Msp Init Callback */ - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - /* Legacy weak One Pulse Msp DeInit Callback */ - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - /* Legacy weak Encoder Msp Init Callback */ - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - /* Legacy weak Encoder Msp DeInit Callback */ - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - /* Legacy weak Hall Sensor Msp Init Callback */ - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - /* Legacy weak Hall Sensor Msp DeInit Callback */ - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - /* Legacy weak Period Elapsed Callback */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - /* Legacy weak Period Elapsed half complete Callback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - /* Legacy weak Trigger Callback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - /* Legacy weak Trigger half complete Callback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - /* Legacy weak IC Capture Callback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - /* Legacy weak IC Capture half complete Callback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - /* Legacy weak OC Delay Elapsed Callback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - /* Legacy weak PWM Pulse Finished Callback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - /* Legacy weak PWM Pulse Finished half complete Callback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - /* Legacy weak Error Callback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; - break; - - case HAL_TIM_COMMUTATION_CB_ID : - /* Legacy weak Commutation Callback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; - break; - - case HAL_TIM_COMMUTATION_HALF_CB_ID : - /* Legacy weak Commutation half complete Callback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; - break; - - case HAL_TIM_BREAK_CB_ID : - /* Legacy weak Break Callback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; - break; - - case HAL_TIM_BREAK2_CB_ID : - /* Legacy weak Break2 Callback */ - htim->Break2Callback = HAL_TIMEx_Break2Callback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - /* Legacy weak Base MspInit Callback */ - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - /* Legacy weak Base Msp DeInit Callback */ - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - /* Legacy weak IC Msp Init Callback */ - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - /* Legacy weak IC Msp DeInit Callback */ - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - /* Legacy weak OC Msp Init Callback */ - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - /* Legacy weak OC Msp DeInit Callback */ - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - /* Legacy weak PWM Msp Init Callback */ - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - /* Legacy weak PWM Msp DeInit Callback */ - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - /* Legacy weak One Pulse Msp Init Callback */ - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - /* Legacy weak One Pulse Msp DeInit Callback */ - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - /* Legacy weak Encoder Msp Init Callback */ - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - /* Legacy weak Encoder Msp DeInit Callback */ - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - /* Legacy weak Hall Sensor Msp Init Callback */ - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - /* Legacy weak Hall Sensor Msp DeInit Callback */ - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief TIM Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base handle state. - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC handle state. - * @param htim TIM Output Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM handle state. - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture handle state. - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode handle state. - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder Interface handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM handle - * @retval Active channel - */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) -{ - return htim->Channel; -} - -/** - * @brief Return actual state of the TIM channel. - * @param htim TIM handle - * @param Channel TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 - * @arg TIM_CHANNEL_6: TIM Channel 6 - * @retval TIM Channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - - return channel_state; -} - -/** - * @brief Return actual state of a DMA burst operation. - * @param htim TIM handle - * @retval DMA burst state - */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - - return htim->DMABurstState; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedHalfCpltCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureHalfCpltCallback(htim); -#else - HAL_TIM_IC_CaptureHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Period Elapse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedHalfCpltCallback(htim); -#else - HAL_TIM_PeriodElapsedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerHalfCpltCallback(htim); -#else - HAL_TIM_TriggerHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief Time Base configuration - * @param TIMx TIM peripheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter (only for advanced timer) value immediately */ - TIMx->EGR = TIM_EGR_UG; - - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } -} - -/** - * @brief Timer Output Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - { - /* Check parameters */ - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 5 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, - const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC5E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC5M); - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC5P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 16U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS5; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 8U); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR5 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 6 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, - const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC6E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC6M); - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC6P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 20U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS6; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 10U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR6 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Slave Timer configuration function - * @param htim TIM handle - * @param sSlaveConfig Slave timer configuration - * @retval None - */ -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - const TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) - { - return HAL_ERROR; - } - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - break; - } - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_ITR0: - case TIM_TS_ITR1: - case TIM_TS_ITR2: - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } - - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Select the Input */ - if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4U); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12U); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 3: Reset the CC3E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 4: Reset the CC4E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) -{ - uint32_t tmpsmcr; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param ChannelState specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Reset interrupt callbacks to the legacy weak callbacks. - * @param htim pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -void TIM_ResetCallback(TIM_HandleTypeDef *htim) -{ - /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; - htim->TriggerCallback = HAL_TIM_TriggerCallback; - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; - htim->ErrorCallback = HAL_TIM_ErrorCallback; - htim->CommutationCallback = HAL_TIMEx_CommutCallback; - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; - htim->BreakCallback = HAL_TIMEx_BreakCallback; - htim->Break2Callback = HAL_TIMEx_Break2Callback; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer (TIM) peripheral: + * + TIM Time Base Initialization + * + TIM Time Base Start + * + TIM Time Base Start Interruption + * + TIM Time Base Start DMA + * + TIM Output Compare/PWM Initialization + * + TIM Output Compare/PWM Channel Configuration + * + TIM Output Compare/PWM Start + * + TIM Output Compare/PWM Start Interruption + * + TIM Output Compare/PWM Start DMA + * + TIM Input Capture Initialization + * + TIM Input Capture Channel Configuration + * + TIM Input Capture Start + * + TIM Input Capture Start Interruption + * + TIM Input Capture Start DMA + * + TIM One Pulse Initialization + * + TIM One Pulse Channel Configuration + * + TIM One Pulse Start + * + TIM Encoder Interface Initialization + * + TIM Encoder Interface Start + * + TIM Encoder Interface Start Interruption + * + TIM Encoder Interface Start DMA + * + Commutation Event configuration with Interruption and DMA + * + TIM OCRef clear configuration + * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Generic features ##### + ============================================================================== + [..] The Timer features include: + (#) 16-bit up, down, up/down auto-reload counter. + (#) 16-bit programmable prescaler allowing dividing (also on the fly) the + counter clock frequency either by any factor between 1 and 65536. + (#) Up to 4 independent channels for: + (++) Input Capture + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to interconnect + several timers together. + (#) Supports incremental encoder for positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + Initialization function of this driver: + (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base + (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an + Output Compare signal. + (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a + PWM signal. + (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an + external signal. + (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer + in One Pulse Mode. + (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. + + (#) Activate the TIM peripheral using one of the start functions depending from the feature used: + (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() + (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() + (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() + (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() + (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() + (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). + + (#) The DMA Burst is managed with the two following functions: + HAL_TIM_DMABurst_WriteStart() + HAL_TIM_DMABurst_ReadStart() + + *** Callback registration *** + ============================================= + + [..] + The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + the Callback ID and a pointer to the user callback function. + + [..] + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + + [..] + These functions allow to register/unregister following callbacks: + (+) Base_MspInitCallback : TIM Base Msp Init Callback. + (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. + (+) IC_MspInitCallback : TIM IC Msp Init Callback. + (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. + (+) OC_MspInitCallback : TIM OC Msp Init Callback. + (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. + (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. + (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. + (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. + (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. + (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. + (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. + (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. + (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. + (+) PeriodElapsedCallback : TIM Period Elapsed Callback. + (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. + (+) TriggerCallback : TIM Trigger Callback. + (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. + (+) IC_CaptureCallback : TIM Input Capture Callback. + (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. + (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. + (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. + (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. + (+) ErrorCallback : TIM Error Callback. + (+) CommutationCallback : TIM Commutation Callback. + (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. + (+) BreakCallback : TIM Break Callback. + (+) Break2Callback : TIM Break2 Callback. + + [..] +By default, after the Init and when the state is HAL_TIM_STATE_RESET +all interrupt callbacks are set to the corresponding weak functions: + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). + + [..] + Exception done for MspInit and MspDeInit functions that are reset to the legacy weak + functionalities in the Init / DeInit only when these callbacks are null + (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit + keep and use the user MspInit / MspDeInit callbacks(registered beforehand) + + [..] + Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. + Exception done MspInit / MspDeInit that can be registered / unregistered + in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, + thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. + + [..] + When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIM TIM + * @brief TIM HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup TIM_Private_Functions + * @{ + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions + * @brief Time Base functions + * +@verbatim + ============================================================================== + ##### Time Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Time Base. + (+) Stop the Time Base. + (+) Start the Time Base and enable interrupt. + (+) Stop the Time Base and disable interrupt. + (+) Start the Time Base and enable DMA transfer. + (+) Stop the Time Base and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Time base Unit according to the specified + * parameters in the TIM_HandleTypeDef and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Base_MspInitCallback == NULL) + { + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Base_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the Time Base configuration */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Base peripheral + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Base_MspDeInitCallback == NULL) + { + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Base_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Base MSP. + * @param htim TIM Base handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ +} + + +/** + * @brief Starts the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Check the TIM state */ + if (htim->State != HAL_TIM_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Set the TIM state */ + if (htim->State == HAL_TIM_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->State == HAL_TIM_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + else + { + return HAL_ERROR; + } + + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Base generation in DMA mode. + * @param htim TIM Base handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions + * @brief TIM Output Compare functions + * +@verbatim + ============================================================================== + ##### TIM Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the TIM Output Compare. + (+) Stop the TIM Output Compare. + (+) Start the TIM Output Compare and enable interrupt. + (+) Stop the TIM Output Compare and disable interrupt. + (+) Start the TIM Output Compare and enable DMA transfer. + (+) Stop the TIM Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OC_MspInitCallback == NULL) + { + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Output Compare handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OC_MspDeInitCallback == NULL) + { + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Output Compare MSP. + * @param htim TIM Output Compare handle + * @retval None + */ +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions + * @brief TIM PWM functions + * +@verbatim + ============================================================================== + ##### TIM PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM PWM. + (+) De-initialize the TIM PWM. + (+) Start the TIM PWM. + (+) Stop the TIM PWM. + (+) Start the TIM PWM and enable interrupt. + (+) Stop the TIM PWM and disable interrupt. + (+) Start the TIM PWM and enable DMA transfer. + (+) Stop the TIM PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->PWM_MspInitCallback == NULL) + { + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->PWM_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM PWM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->PWM_MspDeInitCallback == NULL) + { + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + } + /* DeInit the low level hardware */ + htim->PWM_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim TIM PWM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the PWM signal generation. + * @param htim TIM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Set the TIM channel state */ + if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Capture/Compare 3 request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode. + * @param htim TIM PWM handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions + * @brief TIM Input Capture functions + * +@verbatim + ============================================================================== + ##### TIM Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the TIM Input Capture. + (+) Stop the TIM Input Capture. + (+) Start the TIM Input Capture and enable interrupt. + (+) Stop the TIM Input Capture and disable interrupt. + (+) Start the TIM Input Capture and enable DMA transfer. + (+) Stop the TIM Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->IC_MspInitCallback == NULL) + { + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->IC_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->IC_MspDeInitCallback == NULL) + { + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + } + /* DeInit the low level hardware */ + htim->IC_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Input Capture MSP. + * @param htim TIM Input Capture handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + /* Check the TIM channel state */ + if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Enable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in interrupt mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + case TIM_CHANNEL_4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); + break; + } + + default: + status = HAL_ERROR; + break; + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Input Capture measurement in DMA mode. + * @param htim TIM Input Capture handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions + * @brief TIM One Pulse functions + * +@verbatim + ============================================================================== + ##### TIM One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the TIM One Pulse. + (+) Stop the TIM One Pulse. + (+) Start the TIM One Pulse and enable interrupt. + (+) Stop the TIM One Pulse and disable interrupt. + (+) Start the TIM One Pulse and enable DMA transfer. + (+) Stop the TIM One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and initializes the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() + * @note When the timer instance is initialized in One Pulse mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM One Pulse handle + * @param OnePulseMode Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->OnePulse_MspInitCallback == NULL) + { + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->OnePulse_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->OnePulse_MspDeInitCallback == NULL) + { + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + } + /* DeInit the low level hardware */ + htim->OnePulse_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim TIM One Pulse handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware + (the counter starts in response to a stimulus and generate a pulse */ + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode. + * @note Though OutputChannel parameter is deprecated and ignored by the function + * it has been kept to avoid HAL_TIM API compatibility break. + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel See note above + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(OutputChannel); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions + * @brief TIM Encoder functions + * +@verbatim + ============================================================================== + ##### TIM Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the TIM Encoder. + (+) Stop the TIM Encoder. + (+) Start the TIM Encoder and enable interrupt. + (+) Stop the TIM Encoder and disable interrupt. + (+) Start the TIM Encoder and enable DMA transfer. + (+) Stop the TIM Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and initialize the associated handle. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() + * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together + * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource + * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa + * @note When the timer instance is initialized in Encoder mode, timer + * channels 1 and channel 2 are reserved and cannot be used for other + * purpose. + * @param htim TIM Encoder Interface handle + * @param sConfig TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) +{ + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy weak callbacks */ + TIM_ResetCallback(htim); + + if (htim->Encoder_MspInitCallback == NULL) + { + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->Encoder_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Reset the SMS and ECE bits */ + htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); + + /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); + tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim TIM Encoder Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->Encoder_MspDeInitCallback == NULL) + { + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + } + /* DeInit the low level hardware */ + htim->Encoder_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim TIM Encoder Interface handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + break; + } + } + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + break; + } + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + + /* Enable the encoder interface channels */ + /* Enable the capture compare Interrupts 1 and/or 2 */ + switch (Channel) + { + case TIM_CHANNEL_1: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + default : + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + } + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in interrupt mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts 1 and 2 */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, + uint32_t *pData2, uint16_t Length) +{ + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel(s) state */ + if (Channel == TIM_CHANNEL_1) + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData1 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else if (Channel == TIM_CHANNEL_2) + { + if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData2 == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + else + { + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + + default: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the TIM Input Capture DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + break; + } + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Encoder Interface in DMA mode. + * @param htim TIM Encoder Interface handle + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1 and 2 + (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ + if (Channel == TIM_CHANNEL_1) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + } + else if (Channel == TIM_CHANNEL_2) + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + else + { + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the capture compare DMA Request 1 and 2 */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + } + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel(s) state */ + if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) + { + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ +/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management + * @brief TIM IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + uint32_t itsource = htim->Instance->DIER; + uint32_t itflag = htim->Instance->SR; + + /* Capture compare 1 event */ + if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) + { + if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) + { + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) + { + if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) + { + if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) + { + if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + /* Output compare event */ + else + { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->OC_DelayElapsedCallback(htim); + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) + { + if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break input event */ + if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ + ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->BreakCallback(htim); +#else + HAL_TIMEx_BreakCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Break2 input event */ + if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) + { + if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->Break2Callback(htim); +#else + HAL_TIMEx_Break2Callback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM Trigger detection event */ + if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) + { + if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } + /* TIM commutation event */ + if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) + { + if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) + { + __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + } +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions + * @brief TIM Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure External Clock source. + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master and the Slave synchronization. + (+) Configure the DMA Burst Mode. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the TIM Output Compare Channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM Output Compare handle + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 1 in Output Compare */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 2 in Output Compare */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 3 in Output Compare */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 4 in Output Compare */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 5 in Output Compare */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the TIM Channel 6 in Output Compare */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM Input Capture Channels according to the specified + * parameters in the TIM_IC_InitTypeDef. + * @param htim TIM IC handle + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); + assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); + + /* Process Locked */ + __HAL_LOCK(htim); + + if (Channel == TIM_CHANNEL_1) + { + /* TI1 Configuration */ + TIM_TI1_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_2) + { + /* TI2 Configuration */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Set the IC2PSC value */ + htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); + } + else if (Channel == TIM_CHANNEL_3) + { + /* TI3 Configuration */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + TIM_TI3_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC3PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; + + /* Set the IC3PSC value */ + htim->Instance->CCMR2 |= sConfig->ICPrescaler; + } + else if (Channel == TIM_CHANNEL_4) + { + /* TI4 Configuration */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + TIM_TI4_SetConfig(htim->Instance, + sConfig->ICPolarity, + sConfig->ICSelection, + sConfig->ICFilter); + + /* Reset the IC4PSC Bits */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; + + /* Set the IC4PSC value */ + htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); + } + else + { + status = HAL_ERROR; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM PWM channels according to the specified + * parameters in the TIM_OC_InitTypeDef. + * @param htim TIM PWM handle + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be configured + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, + const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); + assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); + + /* Process Locked */ + __HAL_LOCK(htim); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Configure the Channel 1 in PWM mode */ + TIM_OC1_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel1 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Configure the Channel 2 in PWM mode */ + TIM_OC2_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel2 */ + htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; + htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Configure the Channel 3 in PWM mode */ + TIM_OC3_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel3 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Configure the Channel 4 in PWM mode */ + TIM_OC4_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel4 */ + htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; + break; + } + + case TIM_CHANNEL_5: + { + /* Check the parameters */ + assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); + + /* Configure the Channel 5 in PWM mode */ + TIM_OC5_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel5*/ + htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode; + break; + } + + case TIM_CHANNEL_6: + { + /* Check the parameters */ + assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); + + /* Configure the Channel 6 in PWM mode */ + TIM_OC6_SetConfig(htim->Instance, sConfig); + + /* Set the Preload enable bit for channel6 */ + htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; + + /* Configure the Output Fast mode */ + htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; + htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; + break; + } + + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Initializes the TIM One Pulse Channels according to the specified + * parameters in the TIM_OnePulse_InitTypeDef. + * @param htim TIM One Pulse handle + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM output channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @param InputChannel TIM input Channel to configure + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @note To output a waveform with a minimum delay user can enable the fast + * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx + * output is forced in response to the edge detection on TIx input, + * without taking in account the comparison. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, + uint32_t OutputChannel, uint32_t InputChannel) +{ + HAL_StatusTypeDef status = HAL_OK; + TIM_OC_InitTypeDef temp1; + + /* Check the parameters */ + assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); + assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); + + if (OutputChannel != InputChannel) + { + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Extract the Output compare configuration from sConfig structure */ + temp1.OCMode = sConfig->OCMode; + temp1.Pulse = sConfig->Pulse; + temp1.OCPolarity = sConfig->OCPolarity; + temp1.OCNPolarity = sConfig->OCNPolarity; + temp1.OCIdleState = sConfig->OCIdleState; + temp1.OCNIdleState = sConfig->OCNIdleState; + + switch (OutputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_OC1_SetConfig(htim->Instance, &temp1); + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_OC2_SetConfig(htim->Instance, &temp1); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (InputChannel) + { + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); + + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; + + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM DMA Burst mode + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @note This function should be used only when BurstLength is equal to DMA data transfer length. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) +{ + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; +} + +/** + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim TIM handle + * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read + * This parameter can be one of the following values: + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_RCR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_BDTR + * @arg TIM_DMABASE_OR + * @arg TIM_DMABASE_CCMR3 + * @arg TIM_DMABASE_CCR5 + * @arg TIM_DMABASE_CCR6 + * @arg TIM_DMABASE_AF1 (*) + * @arg TIM_DMABASE_AF2 (*) + * (*) value not defined in all devices + * @param BurstRequestSrc TIM DMA Request sources + * This parameter can be one of the following values: + * @arg TIM_DMA_UPDATE: TIM update Interrupt source + * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM: TIM Commutation DMA source + * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value + * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. + * @param DataLength Data length. This parameter can be one value + * between 1 and 0xFFFF. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + assert_param(IS_TIM_DMA_LENGTH(BurstLength)); + assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); + + if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) + { + return HAL_BUSY; + } + else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) + { + if ((BurstBuffer == NULL) && (BurstLength > 0U)) + { + return HAL_ERROR; + } + else + { + htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; + } + } + else + { + /* nothing to do */ + } + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + /* Set the DMA Period elapsed callbacks */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC1: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC2: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC3: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_CC4: + { + /* Set the DMA capture callbacks */ + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_COM: + { + /* Set the DMA commutation callbacks */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + case TIM_DMA_TRIGGER: + { + /* Set the DMA trigger callbacks */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, + DataLength) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } + + /* Return function status */ + return status; +} + +/** + * @brief Stop the DMA burst reading + * @param htim TIM handle + * @param BurstRequestSrc TIM DMA Request sources to disable. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + + /* Abort the DMA transfer (at least disable the DMA stream) */ + switch (BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); + break; + } + case TIM_DMA_CC1: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + case TIM_DMA_CC2: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + case TIM_DMA_CC3: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + case TIM_DMA_CC4: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); + break; + } + case TIM_DMA_COM: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); + break; + } + case TIM_DMA_TRIGGER: + { + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); + break; + } + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Generate a software event + * @param htim TIM handle + * @param EventSource specifies the event source. + * This parameter can be one of the following values: + * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source + * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source + * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_COM: Timer COM event source + * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source + * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source + * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source + * @note Basic timers can only generate an update event. + * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. + * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant + * only for timer instances supporting break input(s). + * @retval HAL status + */ + +HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_EVENT_SOURCE(EventSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Set the event sources */ + htim->Instance->EGR = EventSource; + + /* Change the TIM state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the OCRef clear feature + * @param htim TIM handle + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that + * contains the OCREF clear feature and parameters for the TIM peripheral. + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, + uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + switch (sClearInputConfig->ClearInputSource) + { + case TIM_CLEARINPUTSOURCE_NONE: + { + /* Clear the OCREF clear selection bit and the the ETR Bits */ + CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); + break; + } + + case TIM_CLEARINPUTSOURCE_ETR: + { + /* Check the parameters */ + assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); + assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); + assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); + + /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + TIM_ETR_SetConfig(htim->Instance, + sClearInputConfig->ClearInputPrescaler, + sClearInputConfig->ClearInputPolarity, + sClearInputConfig->ClearInputFilter); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + switch (Channel) + { + case TIM_CHANNEL_1: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; + } + case TIM_CHANNEL_2: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; + } + case TIM_CHANNEL_3: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; + } + case TIM_CHANNEL_4: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; + } + case TIM_CHANNEL_5: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 5 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + else + { + /* Disable the OCREF clear feature for Channel 5 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); + } + break; + } + case TIM_CHANNEL_6: + { + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 6 */ + SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + else + { + /* Disable the OCREF clear feature for Channel 6 */ + CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); + } + break; + } + default: + break; + } + } + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Configures the clock source to be used + * @param htim TIM handle + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that + * contains the clock source information for the TIM peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); + + /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + htim->Instance->SMCR = tmpsmcr; + + switch (sClockSourceConfig->ClockSource) + { + case TIM_CLOCKSOURCE_INTERNAL: + { + assert_param(IS_TIM_INSTANCE(htim->Instance)); + break; + } + + case TIM_CLOCKSOURCE_ETRMODE1: + { + /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + + /* Select the External clock mode1 and the ETRF trigger */ + tmpsmcr = htim->Instance->SMCR; + tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + break; + } + + case TIM_CLOCKSOURCE_ETRMODE2: + { + /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); + + /* Check ETR input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + /* Configure the ETR Clock source */ + TIM_ETR_SetConfig(htim->Instance, + sClockSourceConfig->ClockPrescaler, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + /* Enable the External clock mode2 */ + htim->Instance->SMCR |= TIM_SMCR_ECE; + break; + } + + case TIM_CLOCKSOURCE_TI1: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); + break; + } + + case TIM_CLOCKSOURCE_TI2: + { + /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI2 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI2_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); + break; + } + + case TIM_CLOCKSOURCE_TI1ED: + { + /* Check whether or not the timer instance supports external clock mode 1 */ + assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); + + /* Check TI1 input conditioning related parameters */ + assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); + assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); + + TIM_TI1_ConfigInputStage(htim->Instance, + sClockSourceConfig->ClockPolarity, + sClockSourceConfig->ClockFilter); + TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); + break; + } + + case TIM_CLOCKSOURCE_ITR0: + case TIM_CLOCKSOURCE_ITR1: + case TIM_CLOCKSOURCE_ITR2: + case TIM_CLOCKSOURCE_ITR3: + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } + + default: + status = HAL_ERROR; + break; + } + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return status; +} + +/** + * @brief Selects the signal connected to the TI1 input: direct from CH1_input + * or a XOR combination between CH1_input, CH2_input & CH3_input + * @param htim TIM handle. + * @param TI1_Selection Indicate whether or not channel 1 is connected to the + * output of a XOR gate. + * This parameter can be one of the following values: + * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input + * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 + * pins are connected to the TI1 input (XOR combination) + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) +{ + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Reset the TI1 selection */ + tmpcr2 &= ~TIM_CR2_TI1S; + + /* Set the TI1 selection */ + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the Slave mode + * (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) + { + htim->State = HAL_TIM_STATE_READY; + __HAL_UNLOCK(htim); + return HAL_ERROR; + } + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Read the captured value from Capture Compare unit + * @param htim TIM handle. + * @param Channel TIM Channels to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval Captured value + */ +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpreg = 0U; + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + + /* Return the capture 1 value */ + tmpreg = htim->Instance->CCR1; + + break; + } + case TIM_CHANNEL_2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + /* Return the capture 2 value */ + tmpreg = htim->Instance->CCR2; + + break; + } + + case TIM_CHANNEL_3: + { + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); + + /* Return the capture 3 value */ + tmpreg = htim->Instance->CCR3; + + break; + } + + case TIM_CHANNEL_4: + { + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); + + /* Return the capture 4 value */ + tmpreg = htim->Instance->CCR4; + + break; + } + + default: + break; + } + + return tmpreg; +} + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions + * @brief TIM Callbacks functions + * +@verbatim + ============================================================================== + ##### TIM Callbacks functions ##### + ============================================================================== + [..] + This section provides TIM callback functions: + (+) TIM Period elapsed callback + (+) TIM Output Compare callback + (+) TIM Input capture callback + (+) TIM Trigger callback + (+) TIM Error callback + +@endverbatim + * @{ + */ + +/** + * @brief Period elapsed callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Period elapsed half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Output Compare callback in non-blocking mode + * @param htim TIM OC handle + * @retval None + */ +__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureCallback could be implemented in the user file + */ +} + +/** + * @brief Input Capture half complete callback in non-blocking mode + * @param htim TIM IC handle + * @retval None + */ +__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file + */ +} + +/** + * @brief PWM Pulse finished half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerCallback could be implemented in the user file + */ +} + +/** + * @brief Hall Trigger detection half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Timer error callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User TIM callback to be used instead of the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @param pCallback pointer to the callback function + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, + pTIM_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + return HAL_ERROR; + } + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + htim->PeriodElapsedCallback = pCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + htim->PeriodElapsedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + htim->TriggerCallback = pCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + htim->TriggerHalfCpltCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + htim->IC_CaptureCallback = pCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + htim->IC_CaptureHalfCpltCallback = pCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + htim->OC_DelayElapsedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + htim->PWM_PulseFinishedCallback = pCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + htim->PWM_PulseFinishedHalfCpltCallback = pCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + htim->ErrorCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + htim->CommutationCallback = pCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + htim->CommutationHalfCpltCallback = pCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + htim->BreakCallback = pCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + htim->Break2Callback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + htim->Base_MspInitCallback = pCallback; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + htim->Base_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + htim->IC_MspInitCallback = pCallback; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + htim->IC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + htim->OC_MspInitCallback = pCallback; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + htim->OC_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + htim->PWM_MspInitCallback = pCallback; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + htim->PWM_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + htim->OnePulse_MspInitCallback = pCallback; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + htim->OnePulse_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + htim->Encoder_MspInitCallback = pCallback; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + htim->Encoder_MspDeInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + htim->HallSensor_MspInitCallback = pCallback; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + htim->HallSensor_MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a TIM callback + * TIM callback is redirected to the weak predefined callback + * @param htim tim handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID + * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID + * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID + * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID + * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID + * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID + * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID + * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID + * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID + * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID + * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID + * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID + * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID + * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID + * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID + * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID + * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID + * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID + * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID + * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (htim->State == HAL_TIM_STATE_READY) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + case HAL_TIM_PERIOD_ELAPSED_CB_ID : + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + break; + + case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + break; + + case HAL_TIM_TRIGGER_CB_ID : + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; + break; + + case HAL_TIM_TRIGGER_HALF_CB_ID : + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + break; + + case HAL_TIM_IC_CAPTURE_CB_ID : + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + break; + + case HAL_TIM_IC_CAPTURE_HALF_CB_ID : + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + break; + + case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + break; + + case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + break; + + case HAL_TIM_ERROR_CB_ID : + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; + break; + + case HAL_TIM_COMMUTATION_CB_ID : + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + break; + + case HAL_TIM_COMMUTATION_HALF_CB_ID : + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + break; + + case HAL_TIM_BREAK_CB_ID : + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; + break; + + case HAL_TIM_BREAK2_CB_ID : + /* Legacy weak Break2 Callback */ + htim->Break2Callback = HAL_TIMEx_Break2Callback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (htim->State == HAL_TIM_STATE_RESET) + { + switch (CallbackID) + { + case HAL_TIM_BASE_MSPINIT_CB_ID : + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; + break; + + case HAL_TIM_BASE_MSPDEINIT_CB_ID : + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; + break; + + case HAL_TIM_IC_MSPINIT_CB_ID : + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; + break; + + case HAL_TIM_IC_MSPDEINIT_CB_ID : + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; + break; + + case HAL_TIM_OC_MSPINIT_CB_ID : + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; + break; + + case HAL_TIM_OC_MSPDEINIT_CB_ID : + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; + break; + + case HAL_TIM_PWM_MSPINIT_CB_ID : + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; + break; + + case HAL_TIM_PWM_MSPDEINIT_CB_ID : + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; + break; + + case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; + break; + + case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; + break; + + case HAL_TIM_ENCODER_MSPINIT_CB_ID : + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; + break; + + case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + break; + + case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions + * @brief TIM Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base handle state. + * @param htim TIM Base handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC handle state. + * @param htim TIM Output Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM handle state. + * @param htim TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture handle state. + * @param htim TIM IC handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode handle state. + * @param htim TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM Encoder Interface handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode handle state. + * @param htim TIM handle + * @retval Active channel + */ +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) +{ + return htim->Channel; +} + +/** + * @brief Return actual state of the TIM channel. + * @param htim TIM handle + * @param Channel TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 + * @arg TIM_CHANNEL_6: TIM Channel 6 + * @retval TIM Channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); + + return channel_state; +} + +/** + * @brief Return actual state of a DMA burst operation. + * @param htim TIM handle + * @retval DMA burst state + */ +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); + + return htim->DMABurstState; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ + +/** + * @brief TIM DMA error callback + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMAError(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Delay Pulse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedHalfCpltCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureCallback(htim); +#else + HAL_TIM_IC_CaptureCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Capture half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->IC_CaptureHalfCpltCallback(htim); +#else + HAL_TIM_IC_CaptureHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA Period Elapse complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedCallback(htim); +#else + HAL_TIM_PeriodElapsedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Period Elapse half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PeriodElapsedHalfCpltCallback(htim); +#else + HAL_TIM_PeriodElapsedHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) + { + htim->State = HAL_TIM_STATE_READY; + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerCallback(htim); +#else + HAL_TIM_TriggerCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Trigger half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->TriggerHalfCpltCallback(htim); +#else + HAL_TIM_TriggerHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief Time Base configuration + * @param TIMx TIM peripheral + * @param Structure TIM Base configuration structure + * @retval None + */ +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) +{ + uint32_t tmpcr1; + tmpcr1 = TIMx->CR1; + + /* Set TIM Time Base Unit parameters ---------------------------------------*/ + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); + tmpcr1 |= Structure->CounterMode; + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + tmpcr1 &= ~TIM_CR1_CKD; + tmpcr1 |= (uint32_t)Structure->ClockDivision; + } + + /* Set the auto-reload preload */ + MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); + + /* Set the Autoreload value */ + TIMx->ARR = (uint32_t)Structure->Period ; + + /* Set the Prescaler value */ + TIMx->PSC = Structure->Prescaler; + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = Structure->RepetitionCounter; + } + + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + + /* Generate an update event to reload the Prescaler + and the repetition counter (only for advanced timer) value immediately */ + TIMx->EGR = TIM_EGR_UG; + + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Timer Output Compare 1 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= ~TIM_CCER_CC1E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~TIM_CCMR1_OC1M; + tmpccmrx &= ~TIM_CCMR1_CC1S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC1P; + /* Set the Output Compare Polarity */ + tmpccer |= OC_Config->OCPolarity; + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + /* Check parameters */ + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC1NP; + /* Set the Output N Polarity */ + tmpccer |= OC_Config->OCNPolarity; + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC1NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS1; + tmpcr2 &= ~TIM_CR2_OIS1N; + /* Set the Output Idle state */ + tmpcr2 |= OC_Config->OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= OC_Config->OCNIdleState; + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR1 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 2 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC2E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR1_OC2M; + tmpccmrx &= ~TIM_CCMR1_CC2S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC2P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 4U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC2NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 4U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC2NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS2; + tmpcr2 &= ~TIM_CR2_OIS2N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 2U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 2U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR2 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 3 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC2E Bit */ + TIMx->CCER &= ~TIM_CCER_CC3E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC3M; + tmpccmrx &= ~TIM_CCMR2_CC3S; + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC3P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 8U); + + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + + /* Reset the Output N Polarity level */ + tmpccer &= ~TIM_CCER_CC3NP; + /* Set the Output N Polarity */ + tmpccer |= (OC_Config->OCNPolarity << 8U); + /* Reset the Output N State */ + tmpccer &= ~TIM_CCER_CC3NE; + } + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare and Output Compare N IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS3; + tmpcr2 &= ~TIM_CR2_OIS3N; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 4U); + /* Set the Output N Idle state */ + tmpcr2 |= (OC_Config->OCNIdleState << 4U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR3 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 4 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= ~TIM_CCMR2_OC4M; + tmpccmrx &= ~TIM_CCMR2_CC4S; + + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC4P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Check parameters */ + assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); + + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS4; + + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR4 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 5 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC5E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC5M); + /* Select the Output Compare Mode */ + tmpccmrx |= OC_Config->OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= ~TIM_CCER_CC5P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 16U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS5; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 8U); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR5 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Timer Output Compare 6 configuration + * @param TIMx to select the TIM peripheral + * @param OC_Config The output configuration structure + * @retval None + */ +static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, + const TIM_OC_InitTypeDef *OC_Config) +{ + uint32_t tmpccmrx; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Disable the output: Reset the CCxE Bit */ + TIMx->CCER &= ~TIM_CCER_CC6E; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= ~(TIM_CCMR3_OC6M); + /* Select the Output Compare Mode */ + tmpccmrx |= (OC_Config->OCMode << 8U); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)~TIM_CCER_CC6P; + /* Set the Output Compare Polarity */ + tmpccer |= (OC_Config->OCPolarity << 20U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + /* Reset the Output Compare IDLE State */ + tmpcr2 &= ~TIM_CR2_OIS6; + /* Set the Output Idle state */ + tmpcr2 |= (OC_Config->OCIdleState << 10U); + } + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Set the Capture Compare Register value */ + TIMx->CCR6 = OC_Config->Pulse; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Slave Timer configuration function + * @param htim TIM handle + * @param sSlaveConfig Slave timer configuration + * @retval None + */ +static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + const TIM_SlaveConfigTypeDef *sSlaveConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + if (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) + { + return HAL_ERROR; + } + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + break; + } + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + break; + } + + case TIM_TS_ITR0: + case TIM_TS_ITR1: + case TIM_TS_ITR2: + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } + + default: + status = HAL_ERROR; + break; + } + + return status; +} + +/** + * @brief Configure the TI1 as Input. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 + * (on channel2 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) + { + tmpccmr1 &= ~TIM_CCMR1_CC1S; + tmpccmr1 |= TIM_ICSelection; + } + else + { + tmpccmr1 |= TIM_CCMR1_CC1S_0; + } + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI1. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= (TIM_ICFilter << 4U); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); + tmpccer |= TIM_ICPolarity; + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 + * (on channel1 path) is used as the input signal. Therefore CCMR1 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Select the Input */ + tmpccmr1 &= ~TIM_CCMR1_CC2S; + tmpccmr1 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the Polarity and Filter for TI2. + * @param TIMx to select the TIM peripheral. + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Disable the Channel 2: Reset the CC2E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC2E; + tmpccmr1 = TIMx->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC2F; + tmpccmr1 |= (TIM_ICFilter << 12U); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (TIM_ICPolarity << 4U); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + */ +static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 3: Reset the CC3E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC3E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC3S; + tmpccmr2 |= TIM_ICSelection; + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC3F; + tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); + tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx to select the TIM peripheral + * @param TIM_ICPolarity The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPOLARITY_RISING + * @arg TIM_ICPOLARITY_FALLING + * @arg TIM_ICPOLARITY_BOTHEDGE + * @param TIM_ICSelection specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 + * (on channel1 path) is used as the input signal. Therefore CCMR2 must be + * protected against un-initialized filter and polarity values. + * @retval None + */ +static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + + /* Disable the Channel 4: Reset the CC4E Bit */ + tmpccer = TIMx->CCER; + TIMx->CCER &= ~TIM_CCER_CC4E; + tmpccmr2 = TIMx->CCMR2; + + /* Select the Input */ + tmpccmr2 &= ~TIM_CCMR2_CC4S; + tmpccmr2 |= (TIM_ICSelection << 8U); + + /* Set the filter */ + tmpccmr2 &= ~TIM_CCMR2_IC4F; + tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); + tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer ; +} + +/** + * @brief Selects the Input Trigger source + * @param TIMx to select the TIM peripheral + * @param InputTriggerSource The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 + * @arg TIM_TS_ETRF: External Trigger input + * @retval None + */ +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) +{ + uint32_t tmpsmcr; + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + /* Reset the TS Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source and the slave mode*/ + tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx to select the TIM peripheral + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. + * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. + * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. + * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. + * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. + * @param ExtTRGFilter External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr; + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_5: TIM Channel 5 selected + * @arg TIM_CHANNEL_6: TIM Channel 6 selected + * @param ChannelState specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. + * @retval None + */ +void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_TIM_CHANNELS(Channel)); + + tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ + + /* Reset the CCxE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ +} + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) +/** + * @brief Reset interrupt callbacks to the legacy weak callbacks. + * @param htim pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @retval None + */ +void TIM_ResetCallback(TIM_HandleTypeDef *htim) +{ + /* Reset the TIM callback to the legacy weak callbacks */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; + htim->Break2Callback = HAL_TIMEx_Break2Callback; +} +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c index 03876442..6dfd403e 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c @@ -1,2588 +1,2588 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal break and dead time configuration - * + Time Master and Slave synchronization configuration - * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) - * + Timer remapping capabilities configuration - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Complementary outputs with programmable dead-time for : - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), - HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), - HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), - HAL_TIMEx_HallSensor_Start_IT(). - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); -static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @note When the timer instance is initialized in Hall Sensor Interface mode, - * timer channels 1 and channel 2 are reserved and cannot be used for - * other purpose. - * @param htim TIM Hall Sensor Interface handle - * @param sConfig TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy week callbacks */ - TIM_ResetCallback(htim); - - if (htim->HallSensor_MspInitCallback == NULL) - { - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->HallSensor_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Hall Sensor interface - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->HallSensor_MspDeInitCallback == NULL) - { - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - } - /* DeInit the low level hardware */ - htim->HallSensor_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM Hall Sensor Interface handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim TIM Hall Sensor Interface handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor Interface handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA stream for Capture 1*/ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complementary - * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to enable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to enable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Output channels for OC and PWM mode. - - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - (+) Enable or disable channel grouping. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the TIM commutation event sequence. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Disable Commutation Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); - - /* Disable Commutation DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Disable Commutation DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); - - /* Enable the Commutation Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; - - /* Disable Commutation Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - const TIM_MasterConfigTypeDef *sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Change the handler state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ - if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); - - /* Clear the MMS2 bits */ - tmpcr2 &= ~TIM_CR2_MMS2; - /* Select the TRGO2 source*/ - tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - } - - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim TIM handle - * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @note Interrupts can be generated when an active level is detected on the - * break input, the break 2 input or the system break input. Break - * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) -{ - /* Keep this variable initialized to 0 as it is used to configure BDTR register */ - uint32_t tmpbdtr = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); - assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - - /* Set the BREAK2 input related BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - } - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} -#if defined(TIM_BREAK_INPUT_SUPPORT) - -/** - * @brief Configures the break input source. - * @param htim TIM handle. - * @param BreakInput Break input to configure - * This parameter can be one of the following values: - * @arg TIM_BREAKINPUT_BRK: Timer break input - * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig Break input source configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, - uint32_t BreakInput, - const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmporx; - uint32_t bkin_enable_mask; - uint32_t bkin_polarity_mask; - uint32_t bkin_enable_bitpos; - uint32_t bkin_polarity_bitpos; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_BREAKINPUT(BreakInput)); - assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); - assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); -#if defined(DFSDM1_Channel0) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) - { - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); - } -#else - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); -#endif /* DFSDM1_Channel0 */ - - /* Check input state */ - __HAL_LOCK(htim); - - switch (sBreakInputConfig->Source) - { - case TIM_BREAKINPUTSOURCE_BKIN: - { - bkin_enable_mask = TIM1_AF1_BKINE; - bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; - bkin_polarity_mask = TIM1_AF1_BKINP; - bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; - break; - } -#if defined(DFSDM1_Channel0) - case TIM_BREAKINPUTSOURCE_DFSDM1: - { - bkin_enable_mask = TIM1_AF1_BKDF1BKE; - bkin_enable_bitpos = TIM1_AF1_BKDF1BKE_Pos; - bkin_polarity_mask = 0U; - bkin_polarity_bitpos = 0U; - break; - } -#endif /* DFSDM1_Channel0 */ - - default: - { - bkin_enable_mask = 0U; - bkin_polarity_mask = 0U; - bkin_enable_bitpos = 0U; - bkin_polarity_bitpos = 0U; - break; - } - } - - switch (BreakInput) - { - case TIM_BREAKINPUT_BRK: - { - /* Get the TIMx_AF1 register value */ - tmporx = htim->Instance->AF1; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined(DFSDM1_Channel0) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* DFSDM1_Channel0 */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_AF1 */ - htim->Instance->AF1 = tmporx; - break; - } - case TIM_BREAKINPUT_BRK2: - { - /* Get the TIMx_AF2 register value */ - tmporx = htim->Instance->AF2; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ -#if defined(DFSDM1_Channel0) - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) -#endif /* DFSDM1_Channel0 */ - { - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - } - - /* Set TIMx_AF2 */ - htim->Instance->AF2 = tmporx; - break; - } - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} -#endif /*TIM_BREAK_INPUT_SUPPORT */ - -/** - * @brief Configures the TIMx Remapping input capabilities. - * @param htim TIM handle. - * @param Remap specifies the TIM remapping source. - * This parameter can be one of the following values: - * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) - * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. - * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. - * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. - * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock. - * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock. - * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. - * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) - * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous - * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock - * (HSE divided by a programmable prescaler) - * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - __HAL_LOCK(htim); - - /* Set the Timer remapping configuration */ - htim->Instance->OR = Remap; - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim TIM handle. - * @param Channels specifies the reference signal(s) the OC5REF is combined with. - * This parameter can be any combination of the following values: - * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC - * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF - * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF - * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) -{ - /* Check parameters */ - assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_GROUPCH5(Channels)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); - - /* Set GC5Cx bit fields */ - htim->Instance->CCR5 |= Channels; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * -@verbatim - ============================================================================== - ##### Extended Callbacks functions ##### - ============================================================================== - [..] - This section provides Extended TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Commutation callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutCallback could be implemented in the user file - */ -} -/** - * @brief Commutation half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Break detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - -/** - * @brief Break2 detection callback in non blocking mode - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_Break2Callback could be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extended Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface handle state. - * @param htim TIM Hall Sensor handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return actual state of the TIM complementary channel. - * @param htim TIM handle - * @param ChannelN TIM Complementary channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @retval TIM Complementary channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); - - channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); - - return channel_state; -} -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions - * @{ - */ - -/** - * @brief TIM DMA Commutation callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Commutation half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationHalfCpltCallback(htim); -#else - HAL_TIMEx_CommutHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - - -/** - * @brief TIM DMA Delay Pulse complete callback (complementary channel). - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - - if (hdma->Init.Mode == DMA_NORMAL) - { - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA error callback (complementary channel) - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @param ChannelNState specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp; - - tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ -} -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_hal_tim_ex.c + * @author MCD Application Team + * @brief TIM HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Timer Extended peripheral: + * + Time Hall Sensor Interface Initialization + * + Time Hall Sensor Interface Start + * + Time Complementary signal break and dead time configuration + * + Time Master and Slave synchronization configuration + * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) + * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### TIMER Extended features ##### + ============================================================================== + [..] + The Timer Extended features include: + (#) Complementary outputs with programmable dead-time for : + (++) Output Compare + (++) PWM generation (Edge and Center-aligned Mode) + (++) One-pulse mode output + (#) Synchronization circuit to control the timer with external signals and to + interconnect several timers together. + (#) Break input to put the timer output signals in reset state or in a known state. + (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for + positioning purposes + + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the TIM low level resources by implementing the following functions + depending on the selected feature: + (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + + (#) The external Clock can be configured, if needed (the default clock is the + internal clock from the APBx), using the following function: + HAL_TIM_ConfigClockSource, the clock configuration should be done before + any start function. + + (#) Configure the TIM in the desired functioning mode using one of the + initialization function of this driver: + (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the + Timer Hall Sensor Interface and the commutation event with the corresponding + Interrupt and DMA request if needed (Note that One Timer is used to interface + with the Hall sensor Interface and another Timer should be used to use + the commutation event). + + (#) Activate the TIM peripheral using one of the start functions: + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() + (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup TIMEx TIMEx + * @brief TIM Extended HAL module driver + * @{ + */ + +#ifdef HAL_TIM_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions + * @brief Timer Hall Sensor functions + * +@verbatim + ============================================================================== + ##### Timer Hall Sensor functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure TIM HAL Sensor. + (+) De-initialize TIM HAL Sensor. + (+) Start the Hall Sensor Interface. + (+) Stop the Hall Sensor Interface. + (+) Start the Hall Sensor Interface and enable interrupts. + (+) Stop the Hall Sensor Interface and disable interrupts. + (+) Start the Hall Sensor Interface and enable DMA transfers. + (+) Stop the Hall Sensor Interface and disable DMA transfers. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. + * @note When the timer instance is initialized in Hall Sensor Interface mode, + * timer channels 1 and channel 2 are reserved and cannot be used for + * other purpose. + * @param htim TIM Hall Sensor Interface handle + * @param sConfig TIM Hall Sensor configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) +{ + TIM_OC_InitTypeDef OC_Config; + + /* Check the TIM handle allocation */ + if (htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + + if (htim->State == HAL_TIM_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + /* Reset interrupt callbacks to legacy week callbacks */ + TIM_ResetCallback(htim); + + if (htim->HallSensor_MspInitCallback == NULL) + { + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; + } + /* Init the low level hardware : GPIO, CLOCK, NVIC */ + htim->HallSensor_MspInitCallback(htim); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIMEx_HallSensor_MspInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + } + + /* Set the TIM state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ + TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); + + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Set the IC1PSC value */ + htim->Instance->CCMR1 |= sConfig->IC1Prescaler; + + /* Enable the Hall sensor interface (XOR function of the three inputs) */ + htim->Instance->CR2 |= TIM_CR2_TI1S; + + /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1F_ED; + + /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; + + /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ + OC_Config.OCFastMode = TIM_OCFAST_DISABLE; + OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; + OC_Config.OCMode = TIM_OCMODE_PWM2; + OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; + OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; + OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; + OC_Config.Pulse = sConfig->Commutation_Delay; + + TIM_OC2_SetConfig(htim->Instance, &OC_Config); + + /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 + register to 101 */ + htim->Instance->CR2 &= ~TIM_CR2_MMS; + htim->Instance->CR2 |= TIM_TRGO_OC2REF; + + /* Initialize the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + + /* Initialize the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Initialize the TIM state*/ + htim->State = HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Hall Sensor interface + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + if (htim->HallSensor_MspDeInitCallback == NULL) + { + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; + } + /* DeInit the low level hardware */ + htim->HallSensor_MspDeInitCallback(htim); +#else + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIMEx_HallSensor_MspDeInit(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; + + /* Change the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Hall Sensor MSP. + * @param htim TIM Hall Sensor Interface handle + * @retval None + */ +__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file + */ +} + +/** + * @brief Starts the TIM Hall Sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall sensor Interface. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channels 1, 2 and 3 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the capture compare Interrupts 1 event */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in interrupt mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + /* Disable the capture compare Interrupts event */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +{ + uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Set the TIM channel state */ + if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) + || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) + { + return HAL_BUSY; + } + else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) + && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + /* Enable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + /* Set the DMA Input Capture 1 Callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + + /* Enable the DMA stream for Capture 1*/ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the capture compare 1 Interrupt */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Hall Sensor Interface in DMA mode. + * @param htim TIM Hall Sensor Interface handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); + + /* Disable the Input Capture channel 1 + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + + /* Disable the capture compare Interrupts 1 event */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions + * @brief Timer Complementary Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Complementary Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary Output Compare/PWM. + (+) Stop the Complementary Output Compare/PWM. + (+) Start the Complementary Output Compare/PWM and enable interrupts. + (+) Stop the Complementary Output Compare/PWM and disable interrupts. + (+) Start the Complementary Output Compare/PWM and enable DMA transfers. + (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Output Compare signal generation on the complementary + * output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM OC handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Output Compare interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in interrupt mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Output Compare DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM Output Compare signal generation in DMA mode + * on the complementary output. + * @param htim TIM Output Compare handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Output Compare DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions + * @brief Timer Complementary PWM functions + * +@verbatim + ============================================================================== + ##### Timer Complementary PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary PWM. + (+) Stop the Complementary PWM. + (+) Start the Complementary PWM and enable interrupts. + (+) Stop the Complementary PWM and disable interrupts. + (+) Start the Complementary PWM and enable DMA transfers. + (+) Stop the Complementary PWM and disable DMA transfers. +@endverbatim + * @{ + */ + +/** + * @brief Starts the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the PWM signal generation on the complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Check the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) + { + return HAL_ERROR; + } + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Enable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the PWM signal generation in interrupt mode on the + * complementary output. + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @brief Starts the TIM PWM signal generation in DMA mode on the + * complementary output + * @param htim TIM handle + * @param Channel TIM Channel to be enabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + /* Set the TIM complementary channel state */ + if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) + { + return HAL_BUSY; + } + else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) + { + if ((pData == NULL) || (Length == 0U)) + { + return HAL_ERROR; + } + else + { + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); + } + } + else + { + return HAL_ERROR; + } + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + break; + } + + case TIM_CHANNEL_2: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + break; + } + + case TIM_CHANNEL_3: + { + /* Set the DMA compare callbacks */ + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; + + /* Enable the DMA stream */ + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) + { + /* Return error status */ + return HAL_ERROR; + } + /* Enable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else + { + __HAL_TIM_ENABLE(htim); + } + } + + /* Return function status */ + return status; +} + +/** + * @brief Stops the TIM PWM signal generation in DMA mode on the complementary + * output + * @param htim TIM handle + * @param Channel TIM Channel to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); + break; + } + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); + break; + } + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); + break; + } + + default: + status = HAL_ERROR; + break; + } + + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } + + /* Return function status */ + return status; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions + * @brief Timer Complementary One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer Complementary One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Start the Complementary One Pulse generation. + (+) Stop the Complementary One Pulse. + (+) Start the Complementary One Pulse and enable interrupts. + (+) Stop the Complementary One Pulse and disable interrupts. + +@endverbatim + * @{ + */ + +/** + * @brief Starts the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation on the complementary + * output. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Starts the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to enable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); + HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); + HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Check the TIM channels state */ + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) + { + return HAL_ERROR; + } + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); + + /* Enable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); + + /* Enable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); + + /* Enable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); + + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM One Pulse signal generation in interrupt mode on the + * complementary channel. + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @param htim TIM One Pulse handle + * @param OutputChannel pulse output channel to disable + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) +{ + uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); + + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the complementary One Pulse output channel and the Input Capture channel */ + TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); + TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); + + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channels state */ + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Configure the commutation event in case of use of the Hall sensor interface. + (+) Configure Output channels for OC and PWM mode. + + (+) Configure Complementary channels, break features and dead time. + (+) Configure Master synchronization. + (+) Configure timer remapping capabilities. + (+) Enable or disable channel grouping. + +@endverbatim + * @{ + */ + +/** + * @brief Configure the TIM commutation event sequence. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with interrupt. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Disable Commutation DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); + + /* Enable the Commutation Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configure the TIM commutation event sequence with DMA. + * @note This function is mandatory to use the commutation event in order to + * update the configuration at each commutation detection on the TRGI input of the Timer, + * the typical use of this feature is with the use of another Timer(interface Timer) + * configured in Hall sensor interface, this interface Timer will generate the + * commutation at its TRGO output (connected to Timer used in this function) each time + * the TI1 of the Interface Timer detect a commutation at its input TI1. + * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set + * @param htim TIM handle + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal trigger 0 selected + * @arg TIM_TS_ITR1: Internal trigger 1 selected + * @arg TIM_TS_ITR2: Internal trigger 2 selected + * @arg TIM_TS_ITR3: Internal trigger 3 selected + * @arg TIM_TS_NONE: No trigger is needed + * @param CommutationSource the Commutation Event source + * This parameter can be one of the following values: + * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer + * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, + uint32_t CommutationSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); + assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger)); + + __HAL_LOCK(htim); + + if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || + (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3)) + { + /* Select the Input trigger */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= InputTrigger; + } + + /* Select the Capture Compare preload feature */ + htim->Instance->CR2 |= TIM_CR2_CCPC; + /* Select the Commutation event source */ + htim->Instance->CR2 &= ~TIM_CR2_CCUS; + htim->Instance->CR2 |= CommutationSource; + + /* Enable the Commutation DMA Request */ + /* Set the DMA Commutation Callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; + + /* Disable Commutation Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); + + /* Enable the Commutation DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the TIM in master mode. + * @param htim TIM handle. + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that + * contains the selected trigger output (TRGO) and the Master/Slave + * mode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, + const TIM_MasterConfigTypeDef *sMasterConfig) +{ + uint32_t tmpcr2; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); + assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Change the handler state */ + htim->State = HAL_TIM_STATE_BUSY; + + /* Get the TIMx CR2 register value */ + tmpcr2 = htim->Instance->CR2; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ + if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); + + /* Clear the MMS2 bits */ + tmpcr2 &= ~TIM_CR2_MMS2; + /* Select the TRGO2 source*/ + tmpcr2 |= sMasterConfig->MasterOutputTrigger2; + } + + /* Reset the MMS Bits */ + tmpcr2 &= ~TIM_CR2_MMS; + /* Select the TRGO source */ + tmpcr2 |= sMasterConfig->MasterOutputTrigger; + + /* Update TIMx CR2 */ + htim->Instance->CR2 = tmpcr2; + + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + /* Reset the MSM Bit */ + tmpsmcr &= ~TIM_SMCR_MSM; + /* Set master mode */ + tmpsmcr |= sMasterConfig->MasterSlaveMode; + + /* Update TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + } + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param htim TIM handle + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @note Interrupts can be generated when an active level is detected on the + * break input, the break 2 input or the system break input. Break + * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) +{ + /* Keep this variable initialized to 0 as it is used to configure BDTR register */ + uint32_t tmpbdtr = 0U; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); + assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); + assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); + assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); + assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); + assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); + + /* Check input state */ + __HAL_LOCK(htim); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); + + if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) + { + /* Check the parameters */ + assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); + assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); + assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); + + /* Set the BREAK2 input related BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); + MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); + } + + /* Set TIMx_BDTR */ + htim->Instance->BDTR = tmpbdtr; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} +#if defined(TIM_BREAK_INPUT_SUPPORT) + +/** + * @brief Configures the break input source. + * @param htim TIM handle. + * @param BreakInput Break input to configure + * This parameter can be one of the following values: + * @arg TIM_BREAKINPUT_BRK: Timer break input + * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input + * @param sBreakInputConfig Break input source configuration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, + uint32_t BreakInput, + const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); + assert_param(IS_TIM_BREAKINPUT(BreakInput)); + assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) + { + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); + } +#else + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); +#endif /* DFSDM1_Channel0 */ + + /* Check input state */ + __HAL_LOCK(htim); + + switch (sBreakInputConfig->Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM1_AF1_BKINE; + bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; + bkin_polarity_mask = TIM1_AF1_BKINP; + bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; + break; + } +#if defined(DFSDM1_Channel0) + case TIM_BREAKINPUTSOURCE_DFSDM1: + { + bkin_enable_mask = TIM1_AF1_BKDF1BKE; + bkin_enable_bitpos = TIM1_AF1_BKDF1BKE_Pos; + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + break; + } +#endif /* DFSDM1_Channel0 */ + + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + switch (BreakInput) + { + case TIM_BREAKINPUT_BRK: + { + /* Get the TIMx_AF1 register value */ + tmporx = htim->Instance->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF1 */ + htim->Instance->AF1 = tmporx; + break; + } + case TIM_BREAKINPUT_BRK2: + { + /* Get the TIMx_AF2 register value */ + tmporx = htim->Instance->AF2; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ +#if defined(DFSDM1_Channel0) + if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1) +#endif /* DFSDM1_Channel0 */ + { + tmporx &= ~bkin_polarity_mask; + tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + } + + /* Set TIMx_AF2 */ + htim->Instance->AF2 = tmporx; + break; + } + default: + status = HAL_ERROR; + break; + } + + __HAL_UNLOCK(htim); + + return status; +} +#endif /*TIM_BREAK_INPUT_SUPPORT */ + +/** + * @brief Configures the TIMx Remapping input capabilities. + * @param htim TIM handle. + * @param Remap specifies the TIM remapping source. + * This parameter can be one of the following values: + * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) + * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. + * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. + * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. + * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock. + * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock. + * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event. + * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default) + * @arg TIM_TIM11_SPDIF: SPDIF Frame synchronous + * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock + * (HSE divided by a programmable prescaler) + * @arg TIM_TIM11_MCO1: TIM11 CH1 input is connected to MCO1 + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) +{ + /* Check parameters */ + assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); + assert_param(IS_TIM_REMAP(Remap)); + + __HAL_LOCK(htim); + + /* Set the Timer remapping configuration */ + htim->Instance->OR = Remap; + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param htim TIM handle. + * @param Channels specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) +{ + /* Check parameters */ + assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_GROUPCH5(Channels)); + + /* Process Locked */ + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Clear GC5Cx bit fields */ + htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + htim->Instance->CCR5 |= Channels; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions + * @brief Extended Callbacks functions + * +@verbatim + ============================================================================== + ##### Extended Callbacks functions ##### + ============================================================================== + [..] + This section provides Extended TIM callback functions: + (+) Timer Commutation callback + (+) Timer Break callback + +@endverbatim + * @{ + */ + +/** + * @brief Commutation callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutCallback could be implemented in the user file + */ +} +/** + * @brief Commutation half complete callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Break detection callback in non-blocking mode + * @param htim TIM handle + * @retval None + */ +__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_TIMEx_BreakCallback could be implemented in the user file + */ +} + +/** + * @brief Break2 detection callback in non blocking mode + * @param htim: TIM handle + * @retval None + */ +__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(htim); + + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIMEx_Break2Callback could be implemented in the user file + */ +} +/** + * @} + */ + +/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions + * @brief Extended Peripheral State functions + * +@verbatim + ============================================================================== + ##### Extended Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Hall Sensor interface handle state. + * @param htim TIM Hall Sensor handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return actual state of the TIM complementary channel. + * @param htim TIM handle + * @param ChannelN TIM Complementary channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @retval TIM Complementary channel state + */ +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) +{ + HAL_TIM_ChannelStateTypeDef channel_state; + + /* Check the parameters */ + assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); + + channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); + + return channel_state; +} +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions + * @{ + */ + +/** + * @brief TIM DMA Commutation callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationCallback(htim); +#else + HAL_TIMEx_CommutCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + +/** + * @brief TIM DMA Commutation half complete callback. + * @param hdma pointer to DMA handle. + * @retval None + */ +void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->CommutationHalfCpltCallback(htim); +#else + HAL_TIMEx_CommutHalfCpltCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ +} + + +/** + * @brief TIM DMA Delay Pulse complete callback (complementary channel). + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + + if (hdma->Init.Mode == DMA_NORMAL) + { + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->PWM_PulseFinishedCallback(htim); +#else + HAL_TIM_PWM_PulseFinishedCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief TIM DMA error callback (complementary channel) + * @param hdma pointer to DMA handle. + * @retval None + */ +static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) +{ + TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); + } + else + { + /* nothing to do */ + } + +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) + htim->ErrorCallback(htim); +#else + HAL_TIM_ErrorCallback(htim); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx to select the TIM peripheral + * @param Channel specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 + * @arg TIM_CHANNEL_2: TIM Channel 2 + * @arg TIM_CHANNEL_3: TIM Channel 3 + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. + * @retval None + */ +static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) +{ + uint32_t tmp; + + tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ + + /* Reset the CCxNE Bit */ + TIMx->CCER &= ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ +} +/** + * @} + */ + +#endif /* HAL_TIM_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_alarm_template.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_alarm_template.c deleted file mode 100644 index 04bad07a..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_alarm_template.c +++ /dev/null @@ -1,317 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_timebase_rtc_alarm_template.c - * @author MCD Application Team - * @brief HAL time base based on the hardware RTC_ALARM Template. - * - * This file override the native HAL time base functions (defined as weak) - * to use the RTC ALARM for time base generation: - * + Initializes the RTC peripheral to increment the seconds registers each 1ms - * + The alarm is configured to assert an interrupt when the RTC reaches 1ms - * + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00 - * + HSE (default), LSE or LSI can be selected as RTC clock source - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This file must be copied to the application folder and modified as follows: - (#) Rename it to 'stm32f7xx_hal_timebase_rtc_alarm.c' - (#) Add this file and the RTC HAL drivers to your project and uncomment - HAL_RTC_MODULE_ENABLED define in stm32f7xx_hal_conf.h - - [..] - (@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes: - The wake up capability of the RTC may be intrusive in case of prior low power mode - configuration requiring different wake up sources. - Application/Example behavior is no more guaranteed - (@) The stm32f7xx_hal_timebase_tim use is recommended for the Applications/Examples - requiring low power modes - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Uncomment the line below to select the appropriate RTC Clock source for your application: - + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision. - + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing - precision. - + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing - precision. - */ -#define RTC_CLOCK_SOURCE_HSE -/* #define RTC_CLOCK_SOURCE_LSE */ -/* #define RTC_CLOCK_SOURCE_LSI */ - -#ifdef RTC_CLOCK_SOURCE_HSE - #define RTC_ASYNCH_PREDIV 99U - #define RTC_SYNCH_PREDIV 9U - #define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U))) -#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */ - #define RTC_ASYNCH_PREDIV 0U - #define RTC_SYNCH_PREDIV 31U -#endif /* RTC_CLOCK_SOURCE_HSE */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -RTC_HandleTypeDef hRTC_Handle; -/* Private function prototypes -----------------------------------------------*/ -void RTC_Alarm_IRQHandler(void); -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief This function configures the RTC_ALARMA as a time base source. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - __IO uint32_t counter = 0U; - - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - HAL_StatusTypeDef status; - -#ifdef RTC_CLOCK_SOURCE_LSE - /* Configure LSE as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; -#elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configure LSI as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; -#elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configure HSE as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - /* Ensure that RTC is clocked by 1MHz */ - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_1MHZ; -#else -#error Please select the RTC Clock source -#endif /* RTC_CLOCK_SOURCE_LSE */ - - status = HAL_RCC_OscConfig(&RCC_OscInitStruct); - if (status == HAL_OK) - { - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - } - if (status == HAL_OK) - { - /* Enable RTC Clock */ - __HAL_RCC_RTC_ENABLE(); - /* The time base should be 1ms - Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK - HSE as RTC clock - Time base = ((99 + 1) * (9 + 1)) / 1MHz - = 1ms - LSE as RTC clock - Time base = ((31 + 1) * (0 + 1)) / 32.768KHz - = ~1ms - LSI as RTC clock - ime base = ((31 + 1) * (0 + 1)) / 32KHz - = 1ms - */ - hRTC_Handle.Instance = RTC; - hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24; - hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; - hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV; - hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; - hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - status = HAL_RTC_Init(&hRTC_Handle); - } - if (status == HAL_OK) - { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - - /* Disable the Alarm A interrupt */ - __HAL_RTC_ALARMA_DISABLE(&hRTC_Handle); - - /* Clear flag alarm A */ - __HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF); - - counter = 0U; - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while (__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == RESET) - { - if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */ - { - status = HAL_ERROR; - } - } - } - if (status == HAL_OK) - { - hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U; - - /* Configure the Alarm state: Enable Alarm */ - __HAL_RTC_ALARMA_ENABLE(&hRTC_Handle); - - /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA); - - /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); - - /* Check if the Initialization mode is set */ - if ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - /* Set the Initialization mode */ - hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK; - counter = 0U; - while ((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - if (counter++ == (SystemCoreClock / 48U)) /* Timeout = ~ 1s */ - { - status = HAL_ERROR; - } - } - } - } - if (status == HAL_OK) - { - hRTC_Handle.Instance->DR = 0U; - hRTC_Handle.Instance->TR = 0U; - - hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); - - /* Enable the RTC Alarm Interrupt */ - HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn); - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - } - else - { - status = HAL_ERROR; - } - } - return status; -} - -/** - * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling RTC ALARM interrupt. - * @retval None - */ -void HAL_SuspendTick(void) -{ - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - /* Disable RTC ALARM update Interrupt */ - __HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); -} - -/** - * @brief Resume Tick increment. - * @note Enable the tick increment by Enabling RTC ALARM interrupt. - * @retval None - */ -void HAL_ResumeTick(void) -{ - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - /* Enable RTC ALARM Update interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); -} - -/** - * @brief ALARM A Event Callback in non blocking mode - * @note This function is called when RTC_ALARM interrupt took place, inside - * RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) -{ - __IO uint32_t counter = 0U; - - HAL_IncTick(); - - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; - - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) - { - if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */ - { - break; - } - } - - hrtc->Instance->DR = 0U; - hrtc->Instance->TR = 0U; - - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); -} - -/** - * @brief This function handles RTC ALARM interrupt request. - * @retval None - */ -void RTC_Alarm_IRQHandler(void) -{ - HAL_RTC_AlarmIRQHandler(&hRTC_Handle); -} - -/** - * @} - */ - -/** - * @} - */ - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_wakeup_template.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_wakeup_template.c deleted file mode 100644 index 87f71954..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_wakeup_template.c +++ /dev/null @@ -1,293 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_timebase_rtc_wakeup_template.c - * @author MCD Application Team - * @brief HAL time base based on the hardware RTC_WAKEUP Template. - * - * This file overrides the native HAL time base functions (defined as weak) - * to use the RTC WAKEUP for the time base generation: - * + Initializes the RTC peripheral and configures the wakeup timer to be - * incremented each 1ms - * + The wakeup feature is configured to assert an interrupt each 1ms - * + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback - * + HSE (default), LSE or LSI can be selected as RTC clock source - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - This file must be copied to the application folder and modified as follows: - (#) Rename it to 'stm32f7xx_hal_timebase_rtc_wakeup.c' - (#) Add this file and the RTC HAL drivers to your project and uncomment - HAL_RTC_MODULE_ENABLED define in stm32f7xx_hal_conf.h - - [..] - (@) HAL RTC alarm and HAL RTC wakeup drivers can't be used with low power modes: - The wake up capability of the RTC may be intrusive in case of prior low power mode - configuration requiring different wake up sources. - Application/Example behavior is no more guaranteed - (@) The stm32f7xx_hal_timebase_tim use is recommended for the Applications/Examples - requiring low power modes - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL_TimeBase_RTC_WakeUp_Template HAL TimeBase RTC WakeUp Template - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Uncomment the line below to select the appropriate RTC Clock source for your application: - + RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision. - + RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing - precision. - + RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing - precision. - */ -#define RTC_CLOCK_SOURCE_HSE -/* #define RTC_CLOCK_SOURCE_LSE */ -/* #define RTC_CLOCK_SOURCE_LSI */ - -#ifdef RTC_CLOCK_SOURCE_HSE - #define RTC_ASYNCH_PREDIV 99U - #define RTC_SYNCH_PREDIV 9U - #define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U))) -#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */ - #define RTC_ASYNCH_PREDIV 0U - #define RTC_SYNCH_PREDIV 31U -#endif /* RTC_CLOCK_SOURCE_HSE */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -RTC_HandleTypeDef hRTC_Handle; - -/* Private function prototypes -----------------------------------------------*/ -void RTC_WKUP_IRQHandler(void); - -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief This function configures the RTC_WKUP as a time base source. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK - = 1ms - * Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1) - = 1 ms - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority) -{ - __IO uint32_t counter = 0U; - - RCC_OscInitTypeDef RCC_OscInitStruct; - RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; - HAL_StatusTypeDef status; - -#ifdef RTC_CLOCK_SOURCE_LSE - /* Configure LSE as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSEState = RCC_LSE_ON; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; -#elif defined (RTC_CLOCK_SOURCE_LSI) - /* Configure LSI as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.LSIState = RCC_LSI_ON; - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; -#elif defined (RTC_CLOCK_SOURCE_HSE) - /* Configure HSE as RTC clock source */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; - /* Ensure that RTC is clocked by 1MHz */ - PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_1MHZ; -#else -#error Please select the RTC Clock source -#endif /* RTC_CLOCK_SOURCE_LSE */ - - status = HAL_RCC_OscConfig(&RCC_OscInitStruct); - if (status == HAL_OK) - { - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; - status = HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); - } - if (status == HAL_OK) - { - /* Enable RTC Clock */ - __HAL_RCC_RTC_ENABLE(); - /* The time base should be 1ms - Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK - HSE as RTC clock - Time base = ((99 + 1) * (9 + 1)) / 1Mhz - = 1ms - LSE as RTC clock - Time base = ((31 + 1) * (0 + 1)) / 32.768Khz - = ~1ms - LSI as RTC clock - Time base = ((31 + 1) * (0 + 1)) / 32Khz - = 1ms - */ - hRTC_Handle.Instance = RTC; - hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24; - hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV; - hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV; - hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE; - hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; - hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; - status = HAL_RTC_Init(&hRTC_Handle); - } - if (status == HAL_OK) - { - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - - /* Disable the Wake-up Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT); - - /* Wait till RTC WUTWF flag is set */ - while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == RESET) - { - if(counter++ == (SystemCoreClock / 48U)) - { - status = HAL_ERROR; - } - } - } - if (status == HAL_OK) - { - /* Clear PWR wake up Flag */ - __HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU); - - /* Clear RTC Wake Up timer Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF); - - /* Configure the Wake-up Timer counter */ - hRTC_Handle.Instance->WUTR = (uint32_t)0U; - - /* Clear the Wake-up Timer clock source bits in CR register */ - hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS; - - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT); - - /* Enable the Wake-up Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); - - /* Enable the RTC global Interrupt */ - HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); - - /* Configure the SysTick IRQ priority */ - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - } - else - { - status = HAL_ERROR; - } - } - - return status; -} - -/** - * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling RTC_WKUP interrupt. - * @retval None - */ -void HAL_SuspendTick(void) -{ - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - /* Disable WAKE UP TIMER Interrupt */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); -} - -/** - * @brief Resume Tick increment. - * @note Enable the tick increment by Enabling RTC_WKUP interrupt. - * @retval None - */ -void HAL_ResumeTick(void) -{ - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle); - /* Enable WAKE UP TIMER interrupt */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle); -} - -/** - * @brief Wake Up Timer Event Callback in non blocking mode - * @note This function is called when RTC_WKUP interrupt took place, inside - * RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param hrtc RTC handle - * @retval None - */ -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) -{ - HAL_IncTick(); -} - -/** - * @brief This function handles WAKE UP TIMER interrupt request. - * @retval None - */ -void RTC_WKUP_IRQHandler(void) -{ - HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle); -} - -/** - * @} - */ - -/** - * @} - */ - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c deleted file mode 100644 index 5407a69d..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c +++ /dev/null @@ -1,176 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_timebase_tim_template.c - * @author MCD Application Team - * @brief HAL time base based on the hardware TIM Template. - * - * This file overrides the native HAL time base functions (defined as weak) - * the TIM time base: - * + Initializes the TIM peripheral generate a Period elapsed Event each 1ms - * + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL_TimeBase - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -TIM_HandleTypeDef TimHandle; -/* Private function prototypes -----------------------------------------------*/ -void TIM6_DAC_IRQHandler(void); -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief This function configures the TIM6 as a time base source. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority Tick interrupt priority. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - RCC_ClkInitTypeDef clkconfig; - uint32_t uwTimclock, uwAPB1Prescaler = 0U; - uint32_t uwPrescalerValue = 0U; - uint32_t pFLatency; - HAL_StatusTypeDef status; - - /* Enable TIM6 clock */ - __HAL_RCC_TIM6_CLK_ENABLE(); - - /* Get clock configuration */ - HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); - - /* Get APB1 prescaler */ - uwAPB1Prescaler = clkconfig.APB1CLKDivider; - - /* Compute TIM6 clock */ - if (uwAPB1Prescaler == RCC_HCLK_DIV1) - { - uwTimclock = HAL_RCC_GetPCLK1Freq(); - } - else - { - uwTimclock = 2 * HAL_RCC_GetPCLK1Freq(); - } - - /* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */ - uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); - - /* Initialize TIM6 */ - TimHandle.Instance = TIM6; - - /* Initialize TIMx peripheral as follow: - + Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base. - + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. - + ClockDivision = 0 - + Counter direction = Up - */ - TimHandle.Init.Period = (1000000U / 1000U) - 1U; - TimHandle.Init.Prescaler = uwPrescalerValue; - TimHandle.Init.ClockDivision = 0; - TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; - TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - status = HAL_TIM_Base_Init(&TimHandle); - if (status == HAL_OK) - { - /* Start the TIM time Base generation in interrupt mode */ - status = HAL_TIM_Base_Start_IT(&TimHandle); - if (status == HAL_OK) - { - /* Enable the TIM6 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn); - - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - /* Enable the TIM6 global Interrupt */ - HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority, 0); - uwTickPrio = TickPriority; - } - else - { - status = HAL_ERROR; - } - } - } - /* Return function status */ - return status; -} - -/** - * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling TIM6 update interrupt. - * @retval None - */ -void HAL_SuspendTick(void) -{ - /* Disable TIM6 update Interrupt */ - __HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE); -} - -/** - * @brief Resume Tick increment. - * @note Enable the tick increment by Enabling TIM6 update interrupt. - * @retval None - */ -void HAL_ResumeTick(void) -{ - /* Enable TIM6 Update interrupt */ - __HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE); -} - -/** - * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM6 interrupt took place, inside - * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - HAL_IncTick(); -} - -/** - * @brief This function handles TIM interrupt request. - * @retval None - */ -void TIM6_DAC_IRQHandler(void) -{ - HAL_TIM_IRQHandler(&TimHandle); -} - -/** - * @} - */ - -/** - * @} - */ - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c index 9e661496..49599d9f 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c @@ -1,4052 +1,4106 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_uart.c - * @author MCD Application Team - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (++) Enable the USARTx interface clock. - (++) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins as alternate function pull-up. - (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (++) UART interrupts handling: - -@@- The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) - are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() - inside the transmit and receive processes. - (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware - flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. - - (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) - in the huart handle AdvancedInit structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers - by calling the HAL_LIN_Init() API. - - (#) For the UART Multiprocessor mode, initialize the UART registers - by calling the HAL_MultiProcessor_Init() API. - - (#) For the UART RS485 Driver Enabled mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - [..] - (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), - also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by - calling the customized HAL_UART_MspInit() API. - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_UART_RegisterCallback() to register a user callback. - Function HAL_UART_RegisterCallback() allows to register following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) WakeupCallback : Wakeup Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_UART_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) WakeupCallback : Wakeup Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - - [..] - For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). - - [..] - By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak functions in the HAL_UART_Init() - and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() - or HAL_UART_Init() function. - - [..] - When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak callbacks are used. - - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief HAL UART module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ - USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ - -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE |\ - USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ - - -#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ -#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions - * @{ - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart); -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Exported Constants --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API - follow respectively the UART asynchronous, UART Half duplex, UART LIN mode - and UART multiprocessor mode configuration procedures (details for the procedures - are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* Check the parameters */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - else - { - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - } - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check UART instance */ - assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @param BreakDetectLength Specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection - * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the LIN UART instance */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Check the Break detection length parameter */ - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - - /* LIN mode limited to 16-bit oversampling only */ - if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - return HAL_ERROR; - } - /* LIN mode limited to 8-bit data length */ - if (huart->Init.WordLength != UART_WORDLENGTH_8B) - { - return HAL_ERROR; - } - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In LIN mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - - /* Set the USART LIN Break detection length. */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @param Address UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod Specifies the UART wakeup method. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection - * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark - * @note If the user resorts to idle line detection wake up, the Address parameter - * is useless and ignored by the initialization function. - * @note If the user resorts to address mark wake up, the address length detection - * is configured by default to 4 bits only. For the UART to be able to - * manage 6-, 7- or 8-bit long addresses detection, the API - * HAL_MultiProcessorEx_AddressLength_Set() must be called after - * HAL_MultiProcessor_Init(). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the wake up method parameter */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In multiprocessor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) - { - /* If address mark wake up method is chosen, set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); - } - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief DeInitialize the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(huart->Instance)); - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0U; - huart->Instance->CR2 = 0x0U; - huart->Instance->CR3 = 0x0U; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - if (huart->MspDeInitCallback == NULL) - { - huart->MspDeInitCallback = HAL_UART_MspDeInit; - } - /* DeInit the low level hardware */ - huart->MspDeInitCallback(huart); -#else - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Initialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit can be implemented in the user file - */ -} - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User UART Callback - * To be used to override the weak predefined callback - * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), - * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register - * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID - * @param huart uart handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, - pUART_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (huart->gState == HAL_UART_STATE_READY) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = pCallback; - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = pCallback; - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = pCallback; - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = pCallback; - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = pCallback; - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = pCallback; - break; - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - case HAL_UART_WAKEUP_CB_ID : - huart->WakeupCallback = pCallback; - break; - -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else if (huart->gState == HAL_UART_STATE_RESET) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), - * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register - * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID - * @param huart uart handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_UART_STATE_READY == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak - AbortTransmitCpltCallback */ - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak - AbortReceiveCpltCallback */ - break; - -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - case HAL_UART_WAKEUP_CB_ID : - huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ - break; - -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else if (HAL_UART_STATE_RESET == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Register a User UART Rx Event Callback - * To be used instead of the weak predefined callback - * @param huart Uart handle - * @param pCallback Pointer to the Rx Event Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (huart->RxState == HAL_UART_STATE_READY) - { - huart->RxEventCallback = pCallback; - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief UnRegister the UART Rx Event Callback - * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback - * @param huart Uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (huart->RxState == HAL_UART_STATE_READY) - { - huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - - (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() - - (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced - reception services: - (+) HAL_UARTEx_RxEventCallback() -#if defined(USART_CR1_UESM) - - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() -#endif - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. - - -@- In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - const uint8_t *pdata8bits; - const uint16_t *pdata16bits; - uint32_t tickstart; - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (const uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - while (huart->TxXferCount > 0U) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - - huart->gState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); - pdata16bits++; - } - else - { - huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); - pdata8bits++; - } - huart->TxXferCount--; - } - - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - huart->gState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint16_t uhMask; - uint32_t tickstart; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - /* as long as data have to be received */ - while (huart->RxXferCount > 0U) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - huart->RxState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); - pdata16bits++; - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - pdata8bits++; - } - huart->RxXferCount--; - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - huart->TxISR = NULL; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->TxISR = UART_TxISR_16BIT; - } - else - { - huart->TxISR = UART_TxISR_8BIT; - } - - /* Enable the Transmit Data Register Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Set Reception type to Standard reception */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - - return (UART_Start_Receive_IT(huart, pData, Size)); - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - if (huart->hdmatx != NULL) - { - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* Enable the UART transmit DMA channel */ - if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_ERROR; - } - } - /* Clear the TC flag in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Set Reception type to Standard reception */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - - return (UART_Start_Receive_DMA(huart, pData, Size)); - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - /* Disable the UART DMA Tx request */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the UART DMA Rx request */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - /* Enable the UART DMA Tx request */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - if (huart->Init.Parity != UART_PARITY_NONE) - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - } - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the UART DMA Rx request */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - /* Stop UART DMA Tx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel */ - if (huart->hdmatx != NULL) - { - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - UART_EndRxTransfer(huart); - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Abort the UART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable the UART DMA Tx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Abort the UART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable the UART DMA Tx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) -{ - uint32_t abortcplt = 1U; - - /* Disable interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (huart->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; - } - else - { - huart->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (huart->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; - } - else - { - huart->hdmarx->XferAbortCallback = NULL; - } - } - - /* Abort the UART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at UART level */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmatx != NULL) - { - /* UART Tx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - huart->hdmatx->XferAbortCallback = NULL; - } - else - { - abortcplt = 0U; - } - } - } - - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmarx != NULL) - { - /* UART Rx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - huart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* Abort the UART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable the UART DMA Tx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ - huart->hdmatx->XferAbortCallback(huart->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Handle UART interrupt request. - * @param huart UART handle. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t isrflags = READ_REG(huart->Instance->ISR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - - uint32_t errorflags; - uint32_t errorcode; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - if (errorflags == 0U) - { - /* UART in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - if (huart->RxISR != NULL) - { - huart->RxISR(huart); - } - return; - } - } - - /* If some errors occur */ - if ((errorflags != 0U) - && (((cr3its & USART_CR3_EIE) != 0U) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) - { - /* UART parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* UART Over-Run interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_ORE) != 0U) - && (((cr1its & USART_CR1_RXNEIE) != 0U) || - ((cr3its & USART_CR3_EIE) != 0U))) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - /* UART Receiver Timeout interrupt occurred ---------------------------------*/ - if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - - huart->ErrorCode |= HAL_UART_ERROR_RTO; - } - - /* Call UART Error Call back function if need be ----------------------------*/ - if (huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* UART in mode Receiver --------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - if (huart->RxISR != NULL) - { - huart->RxISR(huart); - } - } - - /* If Error is to be considered as blocking : - - Receiver Timeout error in Reception - - Overrun error in Reception - - any error occurs in DMA mode reception - */ - errorcode = huart->ErrorCode; - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - && ((isrflags & USART_ISR_IDLE) != 0U) - && ((cr1its & USART_ISR_IDLE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - - /* Check if DMA mode is enabled in UART */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* DMA mode enabled */ - /* Check received length : If all expected data are received, do nothing, - (DMA cplt callback will be called). - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - if ((nb_remaining_rx_data > 0U) - && (nb_remaining_rx_data < huart->RxXferSize)) - { - /* Reception is not complete */ - huart->RxXferCount = nb_remaining_rx_data; - - /* In Normal mode, end DMA xfer and HAL UART Rx process*/ - if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - /* Last bytes received, so no need as the abort is immediate */ - (void)HAL_DMA_Abort(huart->hdmarx); - } - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Idle Event */ - huart->RxEventType = HAL_UART_RXEVENT_IDLE; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - return; - } - else - { - /* DMA mode not enabled */ - /* Check received length : If all expected data are received, do nothing. - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - if ((huart->RxXferCount > 0U) - && (nb_rx_data > 0U)) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Idle Event */ - huart->RxEventType = HAL_UART_RXEVENT_IDLE; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxEventCallback(huart, nb_rx_data); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, nb_rx_data); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - return; - } - } -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - - /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ - if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); - - /* UART Rx state is not reset as a reception process might be ongoing. - If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Wakeup Callback */ - huart->WakeupCallback(huart); -#else - /* Call legacy weak Wakeup Callback */ - HAL_UARTEx_WakeupCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - return; - } -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ - - /* UART in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_ISR_TXE) != 0U) - && ((cr1its & USART_CR1_TXEIE) != 0U)) - { - if (huart->TxISR != NULL) - { - huart->TxISR(huart); - } - return; - } - - /* UART in mode Transmitter (transmission end) -----------------------------*/ - if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) - { - UART_EndTransmit_IT(huart); - return; - } - -} - -/** - * @brief Tx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART error callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Receive Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). - * @param huart UART handle - * @param Size Number of data available in application reception buffer (indicates a position in - * reception buffer until which, data are available) - * @retval None - */ -__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - UNUSED(Size); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_RxEventCallback can be implemented in the user file. - */ -} - -#if defined(USART_CR1_UESM) -/** - * @brief UART wakeup from Stop mode callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_WakeupCallback can be implemented in the user file. - */ -} - -#endif /* USART_CR1_UESM */ -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART. - (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly - (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature - (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode - (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) UART_SetConfig() API configures the UART peripheral - (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features - (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter - (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver - (+) HAL_LIN_SendBreak() API transmits the break characters -@endverbatim - * @{ - */ - -/** - * @brief Update on the fly the receiver timeout value in RTOR register. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout - * value must be less or equal to 0x0FFFFFFFF. - * @retval None - */ -void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) -{ - assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); - MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); -} - -/** - * @brief Enable the UART receiver timeout feature. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) -{ - if (huart->gState == HAL_UART_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Set the USART RTOEN bit */ - SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the UART receiver timeout feature. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) -{ - if (huart->gState == HAL_UART_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear the USART RTOEN bit */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Enable UART in mute mode (does not mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Enable USART mute mode by setting the MME bit in the CR1 register */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Enter UART mute mode (means UART actually enters mute mode). - * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart UART handle. - * @retval None - */ -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); -} - -/** - * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart UART handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - - -/** - * @brief Transmit break characters. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Send break characters */ - __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) Return the UART handle state. - (+) Return the UART handle error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the UART handle state. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) -{ - uint32_t temp1; - uint32_t temp2; - temp1 = huart->gState; - temp2 = huart->RxState; - - return (HAL_UART_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the UART handle error code. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval UART Error Code - */ -uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -/** - * @brief Initialize the callbacks to their default values. - * @param huart UART handle. - * @retval none - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) -{ - /* Init the UART Callback settings */ - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ -#if defined(USART_CR1_UESM) -#if defined(USART_CR3_WUFIE) - huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ -#endif /* USART_CR3_WUFIE */ -#endif /* USART_CR1_UESM */ - huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ - -} -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @brief Configure the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg; - uint16_t brrtemp; - UART_ClockSourceTypeDef clocksource; - uint32_t usartdiv; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t pclk; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); - - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) */ - tmpreg = (uint32_t)huart->Init.HwFlowCtl; - - tmpreg |= huart->Init.OneBitSampling; - MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - - - /*-------------------------- USART BRR Configuration -----------------------*/ - UART_GETCLOCKSOURCE(huart, clocksource); - - if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - break; - case UART_CLOCKSOURCE_PCLK2: - pclk = HAL_RCC_GetPCLK2Freq(); - break; - case UART_CLOCKSOURCE_HSI: - pclk = (uint32_t) HSI_VALUE; - break; - case UART_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - break; - case UART_CLOCKSOURCE_LSE: - pclk = (uint32_t) LSE_VALUE; - break; - default: - pclk = 0U; - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 */ - if (pclk != 0U) - { - usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; - } - } - } - else - { - switch (clocksource) - { - case UART_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - break; - case UART_CLOCKSOURCE_PCLK2: - pclk = HAL_RCC_GetPCLK2Freq(); - break; - case UART_CLOCKSOURCE_HSI: - pclk = (uint32_t) HSI_VALUE; - break; - case UART_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - break; - case UART_CLOCKSOURCE_LSE: - pclk = (uint32_t) LSE_VALUE; - break; - default: - pclk = 0U; - ret = HAL_ERROR; - break; - } - - if (pclk != 0U) - { - /* USARTDIV must be greater than or equal to 0d16 */ - usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - huart->Instance->BRR = (uint16_t)usartdiv; - } - else - { - ret = HAL_ERROR; - } - } - } - - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - return ret; -} - -/** - * @brief Configure the UART peripheral advanced features. - * @param huart UART handle. - * @retval None - */ -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - - /* if required, configure TX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - } - - /* if required, configure RX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - } - - /* if required, configure data inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - } - - /* if required, configure RX overrun detection disabling */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - } - - /* if required, configure DMA disabling on reception error */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - } - - /* if required, configure auto Baud rate detection scheme */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - { - assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - /* set auto Baudrate detection parameters if detection is enabled */ - if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - { - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - } - } - - /* if required, configure MSB first on communication line */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - { - assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - } -} - -/** - * @brief Check the UART Idle State. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) -{ - uint32_t tickstart; - - /* Initialize the UART ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Disable TXE interrupt for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE)); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } -#if defined(USART_ISR_REACK) - - /* Check if the Receiver is enabled */ - if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } -#endif /* USART_ISR_REACK */ - - /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief This function handles UART Communication Timeout. It waits - * until a flag is no longer in the specified status. - * @param huart UART handle. - * @param Flag Specifies the UART flag to check - * @param Status The actual Flag status (SET or RESET) - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - - return HAL_TIMEOUT; - } - - if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) - { - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) - { - /* Clear Overrun Error flag*/ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts if ongoing */ - UART_EndRxTransfer(huart); - - huart->ErrorCode = HAL_UART_ERROR_ORE; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_ERROR; - } - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - { - /* Clear Receiver Timeout flag*/ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts if ongoing */ - UART_EndRxTransfer(huart); - - huart->ErrorCode = HAL_UART_ERROR_RTO; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Start Receive operation in interrupt mode. - * @note This function could be called by all HAL UART API providing reception in Interrupt mode. - * @note When calling this function, parameters validity is considered as already checked, - * i.e. Rx State, buffer address, ... - * UART Handle is assumed as Locked. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; - } - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - if (huart->Init.Parity != UART_PARITY_NONE) - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - } - else - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE); - } - return HAL_OK; -} - -/** - * @brief Start Receive operation in DMA mode. - * @note This function could be called by all HAL UART API providing reception in DMA mode. - * @note When calling this function, parameters validity is considered as already checked, - * i.e. Rx State, buffer address, ... - * UART Handle is assumed as Locked. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - if (huart->hdmarx != NULL) - { - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - /* Restore huart->RxState to ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_ERROR; - } - } - - /* Enable the UART Parity Error Interrupt */ - if (huart->Init.Parity != UART_PARITY_NONE) - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - } - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; -} - - -/** - * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE and TCIE interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; -} - - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Reset RxIsr function pointer */ - huart->RxISR = NULL; -} - - -/** - * @brief DMA UART transmit process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* DMA Normal mode */ - if (hdma->Init.Mode != DMA_CIRCULAR) - { - huart->TxXferCount = 0U; - - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - /* DMA Circular mode */ - else - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART transmit process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx Half complete callback*/ - huart->TxHalfCpltCallback(huart); -#else - /*Call legacy weak Tx Half complete callback*/ - HAL_UART_TxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART receive process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* DMA Normal mode */ - if (hdma->Init.Mode != DMA_CIRCULAR) - { - huart->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - } - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Transfer Complete */ - huart->RxEventType = HAL_UART_RXEVENT_TC; - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - else - { - /* In other cases : use Rx Complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART receive process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Half Transfer */ - huart->RxEventType = HAL_UART_RXEVENT_HT; - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - else - { - /* In other cases : use Rx Half Complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); -#else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART communication error callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - /* Stop UART DMA Tx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - huart->TxXferCount = 0U; - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - huart->RxXferCount = 0U; - UART_EndRxTransfer(huart); - } - - huart->ErrorCode |= HAL_UART_ERROR_DMA; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmarx != NULL) - { - if (huart->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmatx != NULL) - { - if (huart->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->TxXferCount = 0U; - - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief TX interrupt handler for 7 or 8 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) -{ - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if (huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); - huart->pTxBuffPtr++; - huart->TxXferCount--; - } - } -} - -/** - * @brief TX interrupt handler for 9 bits data word length. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) -{ - const uint16_t *tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if (huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - tmp = (const uint16_t *) huart->pTxBuffPtr; - huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); - huart->pTxBuffPtr += 2U; - huart->TxXferCount--; - } - } -} - - -/** - * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Cleat TxISR function pointer */ - huart->TxISR = NULL; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief RX interrupt handler for 7 or 8 bits data word length . - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) -{ - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); - huart->pRxBuffPtr++; - huart->RxXferCount--; - - if (huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - /* Initialize type of RxEvent to Transfer Complete */ - huart->RxEventType = HAL_UART_RXEVENT_TC; - - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Set reception type to Standard */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Disable IDLE interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - { - /* Clear IDLE Flag */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - } - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrupt handler for 9 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) -{ - uint16_t *tmp; - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t *) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr += 2U; - huart->RxXferCount--; - - if (huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - /* Initialize type of RxEvent to Transfer Complete */ - huart->RxEventType = HAL_UART_RXEVENT_TC; - - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Set reception type to Standard */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Disable IDLE interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - { - /* Clear IDLE Flag */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - } - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE |\ + USART_CR3_ONEBIT)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/* Exported Constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(huart->Instance)); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID +#endif +#endif + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID +#endif +#endif + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (++) HAL_UARTEx_RxEventCallback() +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() +#endif +#endif + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Enable the Transmit Data Register Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Disable the UART DMA Tx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the UART DMA Rx request */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Enable the UART DMA Tx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the UART DMA Rx request */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Init.Mode == DMA_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + } + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + } + } +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +#if defined(USART_CR1_UESM) +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ +#if defined(USART_CR1_UESM) +#if defined(USART_CR3_WUFIE) + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ +#endif /* USART_CR3_WUFIE */ +#endif /* USART_CR1_UESM */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + tmpreg |= huart->Init.OneBitSampling; + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + switch (clocksource) + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + break; + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + break; + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + break; + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + break; + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + break; + default: + pclk = 0U; + ret = HAL_ERROR; + break; + } + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } +#if defined(USART_ISR_REACK) + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } +#endif /* USART_ISR_REACK */ + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE); + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* Enable the DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE and TCIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + huart->TxXferCount = 0U; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c index bfd711a6..e47b49b2 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart_ex.c @@ -1,794 +1,792 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_uart_ex.c - * @author MCD Application Team - * @brief Extended UART HAL module driver. - * This file provides firmware functions to manage the following extended - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### UART peripheral extended features ##### - ============================================================================== - - (#) Declare a UART_HandleTypeDef handle structure. - - (#) For the UART RS485 Driver Enable mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup UARTEx UARTEx - * @brief UART Extended HAL module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UARTEx_Private_Functions UARTEx Private Functions - * @{ - */ -#if defined(USART_CR1_UESM) -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -#endif /* USART_CR1_UESM */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions - * @{ - */ - -/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Extended Initialization and Configuration Functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration - procedures (details for the procedures are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the RS485 Driver enable feature according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @param Polarity Select the driver enable polarity. - * This parameter can be one of the following values: - * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high - * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime Driver Enable assertion time: - * 5-bit value defining the time between the activation of the DE (Driver Enable) - * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime Driver Enable deassertion time: - * 5-bit value defining the time between the end of the last stop bit, in a - * transmitted message, and the de-activation of the DE (Driver Enable) signal. - * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, - uint32_t DeassertionTime) -{ - uint32_t temp; - - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - /* Check the Driver Enable UART instance */ - assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - - /* Check the Driver Enable polarity */ - assert_param(IS_UART_DE_POLARITY(Polarity)); - - /* Check the Driver Enable assertion time */ - assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - - /* Check the Driver Enable deassertion time */ - assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - - /* Set the Driver Enable polarity */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - - /* Set the Driver Enable assertion and deassertion times */ - temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @} - */ - - -/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides the following functions: - (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode - (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality - (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address - detection length to more than 4 bits for multiprocessor address mark wake up. -#if defined(USART_CR1_UESM) - (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode - trigger: address match, Start Bit detection or RXNE bit status. - (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode - (+) HAL_UARTEx_DisableStopMode() API disables the above functionality -#endif - - [..] This subsection also provides a set of additional functions providing enhanced reception - services to user. (For example, these functions allow application to handle use cases - where number of data to be received is unknown). - - (#) Compared to standard reception services which only consider number of received - data elements as reception completion criteria, these functions also consider additional events - as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) - for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state - for a programmable time, after last received byte. - (+) Detection that a specific character has been received. - - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, - or till IDLE event occurs. Reception is handled only during function execution. - When function exits, no data reception could occur. HAL status and number of actually received data elements, - are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. - These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. - - (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() - - (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() - - (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() - -@endverbatim - * @{ - */ - -#if defined(USART_CR3_UCESM) -/** - * @brief Keep UART Clock enabled when in Stop Mode. - * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled - * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. - * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, - * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Set UCESM bit */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable UART Clock when in Stop Mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Clear UCESM bit */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -#endif /* USART_CR3_UCESM */ -/** - * @brief By default in multiprocessor mode, when the wake up method is set - * to address mark, the UART handles only 4-bit long addresses detection; - * this API allows to enable longer addresses detection (6-, 7- or 8-bit - * long). - * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, - * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart UART handle. - * @param AddressLength This parameter can be one of the following values: - * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address - * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the address length parameter */ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState to Ready */ - return (UART_CheckIdleState(huart)); -} - -#if defined(USART_CR1_UESM) -/** - * @brief Set Wakeup from Stop mode interrupt flag selection. - * @note It is the application responsibility to enable the interrupt used as - * usart_wkup interrupt source before entering low-power mode. - * @param huart UART handle. - * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUP_ON_ADDRESS - * @arg @ref UART_WAKEUP_ON_STARTBIT - * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* check the wake-up from stop mode UART instance */ - assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); - /* check the wake-up selection parameter */ - assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - -#if defined(USART_CR3_WUS) - /* Set the wake-up selection scheme */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); -#endif /* USART_CR3_WUS */ - - if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) - { - UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); - } - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Wait until REACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else - { - /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief Enable UART Stop Mode. - * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Set UESM bit */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable UART Stop Mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Clear UESM bit */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -#endif /* USART_CR1_UESM */ -/** - * @brief Receive an amount of data in blocking mode till either the expected number of data - * is received or an IDLE event occurs. - * @note HAL_OK is returned if reception is completed (expected number of data has been received) - * or if reception is stopped after IDLE event (less than the expected number of data has been received) - * In this case, RxLen output parameter indicates number of data available in reception buffer. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @param RxLen Number of data elements finally received - * (could be lower than Size, in case reception ends on IDLE event) - * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, - uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint16_t uhMask; - uint32_t tickstart; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - /* Initialize output number of received elements */ - *RxLen = 0U; - - /* as long as data have to be received */ - while (huart->RxXferCount > 0U) - { - /* Check if IDLE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) - { - /* Clear IDLE flag in ISR */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - - /* If Set, but no data ever received, clear flag without exiting loop */ - /* If Set, and data has already been received, this means Idle Event is valid : End reception */ - if (*RxLen > 0U) - { - huart->RxEventType = HAL_UART_RXEVENT_IDLE; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - } - - /* Check if RXNE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) - { - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); - pdata16bits++; - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - pdata8bits++; - } - /* Increment number of received elements */ - *RxLen += 1U; - huart->RxXferCount--; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - huart->RxState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - } - } - - /* Set number of received elements in output parameter : RxLen */ - *RxLen = huart->RxXferSize - huart->RxXferCount; - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode till either the expected number of data - * is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating - * number of received data elements. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - (void)UART_Start_Receive_IT(huart, pData, Size); - - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } - - return status; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode till either the expected number - * of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to DMA services, transferring automatically received data elements in user reception buffer and - * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider - * reception phase as ended. In all cases, callback execution will indicate number of received data elements. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - status = UART_Start_Receive_DMA(huart, pData, Size); - - /* Check Rx process has been successfully started */ - if (status == HAL_OK) - { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } - } - - return status; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Provide Rx Event type that has lead to RxEvent callback execution. - * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress - * of reception process is provided to application through calls of Rx Event callback (either default one - * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, - * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead - * to Rx Event callback execution. - * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; - * When DMA is configured in Normal Mode, HT event does not stop Reception process; - * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; - * @param huart UART handle. - * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) - */ -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) -{ - /* Return Rx Event type value, as stored in UART handle */ - return (huart->RxEventType); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UARTEx_Private_Functions - * @{ - */ -#if defined(USART_CR1_UESM) - -/** - * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart UART handle. - * @param WakeUpSelection UART wake up from stop mode parameters. - * @retval None - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - - /* Set the USART address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - - /* Set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); -} -#endif /* USART_CR1_UESM */ - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + [..] + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +#if defined(USART_CR1_UESM) +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +#endif /* USART_CR1_UESM */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode + (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. +#if defined(USART_CR1_UESM) + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality +#endif + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (+++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (++) Detection that a specific character has been received. + + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (++) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (++) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (++) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +#if defined(USART_CR3_UCESM) +/** + * @brief Keep UART Clock enabled when in Stop Mode. + * @note When the USART clock source is configured to be LSE or HSI, it is possible to keep enabled + * this clock during STOP mode by setting the UCESM bit in USART_CR3 control register. + * @note When LPUART is used to wakeup from stop with LSE is selected as LPUART clock source, + * and desired baud rate is 9600 baud, the bit UCESM bit in LPUART_CR3 control register must be set. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UCESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Clock when in Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UCESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_UCESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#endif /* USART_CR3_UCESM */ +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +#if defined(USART_CR1_UESM) +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + +#if defined(USART_CR3_WUS) + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); +#endif /* USART_CR3_WUS */ + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +#endif /* USART_CR1_UESM */ +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + (void)UART_Start_Receive_IT(huart, pData, Size); + + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ +#if defined(USART_CR1_UESM) + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} +#endif /* USART_CR1_UESM */ + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c index 2324036e..5df28a68 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c @@ -1,3126 +1,3126 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_usart.c - * @author MCD Application Team - * @brief USART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter - * Peripheral (USART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State and Error functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The USART HAL driver can be used as follows: - - (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart). - (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: - (++) Enable the USARTx interface clock. - (++) USART pins configuration: - (+++) Enable the clock for the USART GPIOs. - (+++) Configure these USART pins as alternate function pull-up. - (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), - HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (++) USART interrupts handling: - -@@- The specific USART interrupts (Transmission complete interrupt, - RXNE interrupt and Error Interrupts) will be managed using the macros - __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. - (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() - HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer - complete interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode - (Receiver/Transmitter) in the husart handle Init structure. - - (#) Initialize the USART registers by calling the HAL_USART_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_USART_MspInit(&husart) API. - - [..] - (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's - HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and - HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_USART_RegisterCallback() to register a user callback. - Function HAL_USART_RegisterCallback() allows to register following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) TxRxCpltCallback : Tx Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) MspInitCallback : USART MspInit. - (+) MspDeInitCallback : USART MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_USART_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) TxRxCpltCallback : Tx Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) MspInitCallback : USART MspInit. - (+) MspDeInitCallback : USART MspDeInit. - - [..] - By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak functions in the HAL_USART_Init() - and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() - or HAL_USART_Init() function. - - [..] - When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak callbacks are used. - - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup USART USART - * @brief HAL USART Synchronous module driver - * @{ - */ - -#ifdef HAL_USART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup USART_Private_Constants USART Private Constants - * @{ - */ -#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ -#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ -#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ - USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ - -#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ -#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup USART_Private_Functions - * @{ - */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -static void USART_EndTransfer(USART_HandleTypeDef *husart); -static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void USART_DMAError(DMA_HandleTypeDef *hdma); -static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout); -static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); -static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); -static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); -static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); -static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); -static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); -static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USART_Exported_Functions USART Exported Functions - * @{ - */ - -/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USART - in asynchronous and in synchronous modes. - (+) For the asynchronous mode only these parameters can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) USART polarity - (++) USART phase - (++) USART LastBit - (++) Receiver/transmitter modes - - [..] - The HAL_USART_Init() function follows the USART synchronous configuration - procedure (details for the procedure are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible USART formats are listed in the - following table. - - Table 1. USART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | USART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the USART mode according to the specified - * parameters in the USART_InitTypeDef and initialize the associated handle. - * @param husart USART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) -{ - /* Check the USART handle allocation */ - if (husart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_USART_INSTANCE(husart->Instance)); - - if (husart->State == HAL_USART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - husart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - USART_InitCallbacksToDefault(husart); - - if (husart->MspInitCallback == NULL) - { - husart->MspInitCallback = HAL_USART_MspInit; - } - - /* Init the low level hardware */ - husart->MspInitCallback(husart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_USART_MspInit(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - - husart->State = HAL_USART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_USART_DISABLE(husart); - - /* Set the Usart Communication parameters */ - if (USART_SetConfig(husart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In Synchronous mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register - - HDSEL, SCEN and IREN bits in the USART_CR3 register. - */ - husart->Instance->CR2 &= ~USART_CR2_LINEN; - husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); - - /* Enable the Peripheral */ - __HAL_USART_ENABLE(husart); - - /* TEACK and/or REACK to check before moving husart->State to Ready */ - return (USART_CheckIdleState(husart)); -} - -/** - * @brief DeInitialize the USART peripheral. - * @param husart USART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) -{ - /* Check the USART handle allocation */ - if (husart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_USART_INSTANCE(husart->Instance)); - - husart->State = HAL_USART_STATE_BUSY; - - husart->Instance->CR1 = 0x0U; - husart->Instance->CR2 = 0x0U; - husart->Instance->CR3 = 0x0U; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - if (husart->MspDeInitCallback == NULL) - { - husart->MspDeInitCallback = HAL_USART_MspDeInit; - } - /* DeInit the low level hardware */ - husart->MspDeInitCallback(husart); -#else - /* DeInit the low level hardware */ - HAL_USART_MspDeInit(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_RESET; - - /* Process Unlock */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief Initialize the USART MSP. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the USART MSP. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_MspDeInit can be implemented in the user file - */ -} - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User USART Callback - * To be used to override the weak predefined callback - * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET - * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID - * @param husart usart handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status -+ */ -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, - pUSART_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (husart->State == HAL_USART_STATE_READY) - { - switch (CallbackID) - { - case HAL_USART_TX_HALFCOMPLETE_CB_ID : - husart->TxHalfCpltCallback = pCallback; - break; - - case HAL_USART_TX_COMPLETE_CB_ID : - husart->TxCpltCallback = pCallback; - break; - - case HAL_USART_RX_HALFCOMPLETE_CB_ID : - husart->RxHalfCpltCallback = pCallback; - break; - - case HAL_USART_RX_COMPLETE_CB_ID : - husart->RxCpltCallback = pCallback; - break; - - case HAL_USART_TX_RX_COMPLETE_CB_ID : - husart->TxRxCpltCallback = pCallback; - break; - - case HAL_USART_ERROR_CB_ID : - husart->ErrorCallback = pCallback; - break; - - case HAL_USART_ABORT_COMPLETE_CB_ID : - husart->AbortCpltCallback = pCallback; - break; - - - case HAL_USART_MSPINIT_CB_ID : - husart->MspInitCallback = pCallback; - break; - - case HAL_USART_MSPDEINIT_CB_ID : - husart->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (husart->State == HAL_USART_STATE_RESET) - { - switch (CallbackID) - { - case HAL_USART_MSPINIT_CB_ID : - husart->MspInitCallback = pCallback; - break; - - case HAL_USART_MSPDEINIT_CB_ID : - husart->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an USART Callback - * USART callaback is redirected to the weak predefined callback - * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET - * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID - * @param husart usart handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_USART_STATE_READY == husart->State) - { - switch (CallbackID) - { - case HAL_USART_TX_HALFCOMPLETE_CB_ID : - husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_USART_TX_COMPLETE_CB_ID : - husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_USART_RX_HALFCOMPLETE_CB_ID : - husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_USART_RX_COMPLETE_CB_ID : - husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_USART_TX_RX_COMPLETE_CB_ID : - husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ - break; - - case HAL_USART_ERROR_CB_ID : - husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_USART_ABORT_COMPLETE_CB_ID : - husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - - case HAL_USART_MSPINIT_CB_ID : - husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ - break; - - case HAL_USART_MSPDEINIT_CB_ID : - husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ - break; - - default : - /* Update the error code */ - husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_USART_STATE_RESET == husart->State) - { - switch (CallbackID) - { - case HAL_USART_MSPINIT_CB_ID : - husart->MspInitCallback = HAL_USART_MspInit; - break; - - case HAL_USART_MSPDEINIT_CB_ID : - husart->MspDeInitCallback = HAL_USART_MspDeInit; - break; - - default : - /* Update the error code */ - husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions_Group2 IO operation functions - * @brief USART Transmit and Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to manage the USART synchronous - data transfers. - - [..] The USART supports master mode only: it cannot receive or send data related to an input - clock (SCLK is always an output). - - [..] - - (#) There are two modes of transfer: - (++) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated USART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (++) HAL_USART_Transmit() in simplex mode - (++) HAL_USART_Receive() in full duplex receive only - (++) HAL_USART_TransmitReceive() in full duplex mode - - (#) Non-Blocking mode API's with Interrupt are : - (++) HAL_USART_Transmit_IT() in simplex mode - (++) HAL_USART_Receive_IT() in full duplex receive only - (++) HAL_USART_TransmitReceive_IT() in full duplex mode - (++) HAL_USART_IRQHandler() - - (#) No-Blocking mode API's with DMA are : - (++) HAL_USART_Transmit_DMA() in simplex mode - (++) HAL_USART_Receive_DMA() in full duplex receive only - (++) HAL_USART_TransmitReceive_DMA() in full duplex mode - (++) HAL_USART_DMAPause() - (++) HAL_USART_DMAResume() - (++) HAL_USART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (++) HAL_USART_TxCpltCallback() - (++) HAL_USART_RxCpltCallback() - (++) HAL_USART_TxHalfCpltCallback() - (++) HAL_USART_RxHalfCpltCallback() - (++) HAL_USART_ErrorCallback() - (++) HAL_USART_TxRxCpltCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (++) HAL_USART_Abort() - (++) HAL_USART_Abort_IT() - - (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: - (++) HAL_USART_AbortCpltCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, - Parity Error or Noise Error in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify - error type, and HAL_USART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on USART side. - If user wants to abort it, Abort services should be called by user. - (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, - and HAL_USART_ErrorCallback() user callback is executed. - -@endverbatim - * @{ - */ - -/** - * @brief Simplex send an amount of data in blocking mode. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pTxData. - * @param husart USART handle. - * @param pTxData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, - uint32_t Timeout) -{ - const uint8_t *ptxdata8bits; - const uint16_t *ptxdata16bits; - uint32_t tickstart; - - if (husart->State == HAL_USART_STATE_READY) - { - if ((pTxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */ - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - ptxdata8bits = NULL; - ptxdata16bits = (const uint16_t *) pTxData; - } - else - { - ptxdata8bits = pTxData; - ptxdata16bits = NULL; - } - - /* Check the remaining data to be sent */ - while (husart->TxXferCount > 0U) - { - if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (ptxdata8bits == NULL) - { - husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU); - ptxdata16bits++; - } - else - { - husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU); - ptxdata8bits++; - } - - husart->TxXferCount--; - } - - if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - /* Clear Transmission Complete Flag */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - - /* Clear overrun flag and discard the received data */ - __HAL_USART_CLEAR_OREFLAG(husart); - __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); - __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); - - /* At end of Tx process, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pRxData. - * @param husart USART handle. - * @param pRxData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) -{ - uint8_t *prxdata8bits; - uint16_t *prxdata16bits; - uint16_t uhMask; - uint32_t tickstart; - - if (husart->State == HAL_USART_STATE_READY) - { - if ((pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - husart->RxXferSize = Size; - husart->RxXferCount = Size; - - /* Computation of USART mask to apply to RDR register */ - USART_MASK_COMPUTATION(husart); - uhMask = husart->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - prxdata8bits = NULL; - prxdata16bits = (uint16_t *) pRxData; - } - else - { - prxdata8bits = pRxData; - prxdata16bits = NULL; - } - - /* as long as data have to be received */ - while (husart->RxXferCount > 0U) - { - { - /* Wait until TXE flag is set to send dummy byte in order to generate the - * clock for the slave to send data. - * Whatever the frame length (7, 8 or 9-bit long), the same dummy value - * can be written for all the cases. */ - if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); - } - - /* Wait for RXNE Flag */ - if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (prxdata8bits == NULL) - { - *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); - prxdata16bits++; - } - else - { - *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); - prxdata8bits++; - } - - husart->RxXferCount--; - - } - - - /* At end of Rx process, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Send and Receive an amount of data in blocking mode. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number - * of u16 available through pTxData and through pRxData. - * @param husart USART handle. - * @param pTxData pointer to TX data buffer (u8 or u16 data elements). - * @param pRxData pointer to RX data buffer (u8 or u16 data elements). - * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size, uint32_t Timeout) -{ - uint8_t *prxdata8bits; - uint16_t *prxdata16bits; - const uint8_t *ptxdata8bits; - const uint16_t *ptxdata16bits; - uint16_t uhMask; - uint16_t rxdatacount; - uint32_t tickstart; - - if (husart->State == HAL_USART_STATE_READY) - { - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - husart->RxXferSize = Size; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - husart->RxXferCount = Size; - - /* Computation of USART mask to apply to RDR register */ - USART_MASK_COMPUTATION(husart); - uhMask = husart->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - prxdata8bits = NULL; - ptxdata8bits = NULL; - ptxdata16bits = (const uint16_t *) pTxData; - prxdata16bits = (uint16_t *) pRxData; - } - else - { - prxdata8bits = pRxData; - ptxdata8bits = pTxData; - ptxdata16bits = NULL; - prxdata16bits = NULL; - } - - if (husart->TxXferCount == 0x01U) - { - /* Wait until TXE flag is set to send data */ - if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (ptxdata8bits == NULL) - { - husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); - ptxdata16bits++; - } - else - { - husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); - ptxdata8bits++; - } - - husart->TxXferCount--; - } - - /* Check the remain data to be sent */ - /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ - rxdatacount = husart->RxXferCount; - while ((husart->TxXferCount > 0U) || (rxdatacount > 0U)) - { - if (husart->TxXferCount > 0U) - { - /* Wait until TXE flag is set to send data */ - if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - if (ptxdata8bits == NULL) - { - husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); - ptxdata16bits++; - } - else - { - husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); - ptxdata8bits++; - } - - husart->TxXferCount--; - } - - if (husart->RxXferCount > 0U) - { - /* Wait for RXNE Flag */ - if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - if (prxdata8bits == NULL) - { - *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); - prxdata16bits++; - } - else - { - *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); - prxdata8bits++; - } - - husart->RxXferCount--; - } - rxdatacount = husart->RxXferCount; - } - - /* At end of TxRx process, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pTxData. - * @param husart USART handle. - * @param pTxData pointer to data buffer (u8 or u16 data elements). - * @param Size amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) -{ - if (husart->State == HAL_USART_STATE_READY) - { - if ((pTxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - husart->TxISR = NULL; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - /* The USART Error Interrupts: (Frame error, noise error, overrun error) - are not managed by the USART Transmit Process to avoid the overrun interrupt - when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" - to benefit for the frame error and noise interrupts the usart mode should be - configured only for transmit "USART_MODE_TX" */ - - { - /* Set the Tx ISR function pointer according to the data word length */ - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - husart->TxISR = USART_TxISR_16BIT; - } - else - { - husart->TxISR = USART_TxISR_8BIT; - } - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Transmit Data Register Empty Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @note To receive synchronous data, dummy data are simultaneously transmitted. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pRxData. - * @param husart USART handle. - * @param pRxData pointer to data buffer (u8 or u16 data elements). - * @param Size amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) -{ - - if (husart->State == HAL_USART_STATE_READY) - { - if ((pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->RxXferCount = Size; - husart->RxISR = NULL; - - USART_MASK_COMPUTATION(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - husart->RxISR = USART_RxISR_16BIT; - } - else - { - husart->RxISR = USART_RxISR_8BIT; - } - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Parity Error and Data Register not empty Interrupts */ - if (husart->Init.Parity != USART_PARITY_NONE) - { - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - } - else - { - SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - } - } - - { - /* Send dummy data in order to generate the clock for the Slave to send the next data. - */ - { - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); - } - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number - * of u16 available through pTxData and through pRxData. - * @param husart USART handle. - * @param pTxData pointer to TX data buffer (u8 or u16 data elements). - * @param pRxData pointer to RX data buffer (u8 or u16 data elements). - * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size) -{ - - if (husart->State == HAL_USART_STATE_READY) - { - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->RxXferCount = Size; - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - /* Computation of USART mask to apply to RDR register */ - USART_MASK_COMPUTATION(husart); - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX_RX; - - { - if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) - { - husart->TxISR = USART_TxISR_16BIT; - husart->RxISR = USART_RxISR_16BIT; - } - else - { - husart->TxISR = USART_TxISR_8BIT; - husart->RxISR = USART_RxISR_8BIT; - } - - /* Process Locked */ - __HAL_UNLOCK(husart); - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ - if (husart->Init.Parity != USART_PARITY_NONE) - { - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); - } - else - { - SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - } - - /* Enable the USART Transmit Data Register Empty Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in DMA mode. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pTxData. - * @param husart USART handle. - * @param pTxData pointer to data buffer (u8 or u16 data elements). - * @param Size amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) -{ - HAL_StatusTypeDef status = HAL_OK; - const uint32_t *tmp; - - if (husart->State == HAL_USART_STATE_READY) - { - if ((pTxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - husart->TxXferCount = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX; - - if (husart->hdmatx != NULL) - { - /* Set the USART DMA transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - - /* Set the DMA error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; - - /* Enable the USART transmit DMA channel */ - tmp = (const uint32_t *)&pTxData; - status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); - } - - if (status == HAL_OK) - { - /* Clear the TC flag in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - /* Set error code to DMA */ - husart->ErrorCode = HAL_USART_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Restore husart->State to ready */ - husart->State = HAL_USART_STATE_READY; - - return HAL_ERROR; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @note When the USART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pRxData. - * @param husart USART handle. - * @param pRxData pointer to data buffer (u8 or u16 data elements). - * @param Size amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t *tmp = (uint32_t *)&pRxData; - - /* Check that a Rx process is not already ongoing */ - if (husart->State == HAL_USART_STATE_READY) - { - if ((pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->pTxBuffPtr = pRxData; - husart->TxXferSize = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_RX; - - if (husart->hdmarx != NULL) - { - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; - - /* Enable the USART receive DMA channel */ - status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); - } - - { - /* Enable the USART transmit DMA channel: the transmit channel is used in order - to generate in the non-blocking mode the clock to the slave device, - this mode isn't a simplex receive mode but a full-duplex receive mode */ - - /* Set the USART DMA Tx Complete and Error callback to Null */ - if (husart->hdmatx != NULL) - { - husart->hdmatx->XferErrorCallback = NULL; - husart->hdmatx->XferHalfCpltCallback = NULL; - husart->hdmatx->XferCpltCallback = NULL; - status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); - } - } - - if (status == HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - if (husart->Init.Parity != USART_PARITY_NONE) - { - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - } - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - if (husart->hdmarx != NULL) - { - status = HAL_DMA_Abort(husart->hdmarx); - } - - /* No need to check on error code */ - UNUSED(status); - - /* Set error code to DMA */ - husart->ErrorCode = HAL_USART_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Restore husart->State to ready */ - husart->State = HAL_USART_STATE_READY; - - return HAL_ERROR; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. - * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. - * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number - * of u16 available through pTxData and through pRxData. - * @param husart USART handle. - * @param pTxData pointer to TX data buffer (u8 or u16 data elements). - * @param pRxData pointer to RX data buffer (u8 or u16 data elements). - * @param Size amount of data elements (u8 or u16) to be received/sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size) -{ - HAL_StatusTypeDef status; - const uint32_t *tmp; - - if (husart->State == HAL_USART_STATE_READY) - { - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(husart); - - husart->pRxBuffPtr = pRxData; - husart->RxXferSize = Size; - husart->pTxBuffPtr = pTxData; - husart->TxXferSize = Size; - - husart->ErrorCode = HAL_USART_ERROR_NONE; - husart->State = HAL_USART_STATE_BUSY_TX_RX; - - if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL)) - { - /* Set the USART DMA Rx transfer complete callback */ - husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; - - /* Set the USART DMA Tx transfer complete callback */ - husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; - - /* Set the USART DMA Half transfer complete callback */ - husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; - - /* Set the USART DMA Tx transfer error callback */ - husart->hdmatx->XferErrorCallback = USART_DMAError; - - /* Set the USART DMA Rx transfer error callback */ - husart->hdmarx->XferErrorCallback = USART_DMAError; - - /* Enable the USART receive DMA channel */ - tmp = (uint32_t *)&pRxData; - status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size); - - /* Enable the USART transmit DMA channel */ - if (status == HAL_OK) - { - tmp = (const uint32_t *)&pTxData; - status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); - } - } - else - { - status = HAL_ERROR; - } - - if (status == HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - if (husart->Init.Parity != USART_PARITY_NONE) - { - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - } - - /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Clear the TC flag in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - if (husart->hdmarx != NULL) - { - status = HAL_DMA_Abort(husart->hdmarx); - } - - /* No need to check on error code */ - UNUSED(status); - - /* Set error code to DMA */ - husart->ErrorCode = HAL_USART_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - /* Restore husart->State to ready */ - husart->State = HAL_USART_STATE_READY; - - return HAL_ERROR; - } - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the DMA Transfer. - * @param husart USART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) -{ - const HAL_USART_StateTypeDef state = husart->State; - - /* Process Locked */ - __HAL_LOCK(husart); - - if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && - (state == HAL_USART_STATE_BUSY_TX)) - { - /* Disable the USART DMA Tx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - else if ((state == HAL_USART_STATE_BUSY_RX) || - (state == HAL_USART_STATE_BUSY_TX_RX)) - { - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable the USART DMA Tx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Disable the USART DMA Rx request */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - } - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param husart USART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) -{ - const HAL_USART_StateTypeDef state = husart->State; - - /* Process Locked */ - __HAL_LOCK(husart); - - if (state == HAL_USART_STATE_BUSY_TX) - { - /* Enable the USART DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - else if ((state == HAL_USART_STATE_BUSY_RX) || - (state == HAL_USART_STATE_BUSY_TX_RX)) - { - /* Clear the Overrun flag before resuming the Rx transfer*/ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); - - /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - if (husart->Init.Parity != USART_PARITY_NONE) - { - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); - } - SET_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Enable the USART DMA Rx request before the DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Enable the USART DMA Tx request */ - SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param husart USART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / - HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - /* Disable the USART Tx/Rx DMA requests */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the USART DMA tx channel */ - if (husart->hdmatx != NULL) - { - if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - husart->ErrorCode = HAL_USART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - /* Abort the USART DMA rx channel */ - if (husart->hdmarx != NULL) - { - if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - husart->ErrorCode = HAL_USART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - USART_EndTransfer(husart); - husart->State = HAL_USART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param husart USART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable USART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) -{ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Abort the USART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable the USART DMA Tx request if enabled */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (husart->hdmatx != NULL) - { - /* Set the USART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - husart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - husart->ErrorCode = HAL_USART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Abort the USART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable the USART DMA Rx request if enabled */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (husart->hdmarx != NULL) - { - /* Set the USART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - husart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - husart->ErrorCode = HAL_USART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Reset Tx and Rx transfer counters */ - husart->TxXferCount = 0U; - husart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); - - - /* Discard the received data */ - __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); - - /* Restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* Reset Handle ErrorCode to No Error */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param husart USART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable USART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) -{ - uint32_t abortcplt = 1U; - - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (husart->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) - { - husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; - } - else - { - husart->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (husart->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { - husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; - } - else - { - husart->hdmarx->XferAbortCallback = NULL; - } - } - - /* Abort the USART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) - { - /* Disable DMA Tx at USART level */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (husart->hdmatx != NULL) - { - /* USART Tx DMA Abort callback has already been initialised : - will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) - { - husart->hdmatx->XferAbortCallback = NULL; - } - else - { - abortcplt = 0U; - } - } - } - - /* Abort the USART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable the USART DMA Rx request if enabled */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (husart->hdmarx != NULL) - { - /* USART Rx DMA Abort callback has already been initialised : - will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) - { - husart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - husart->TxXferCount = 0U; - husart->RxXferCount = 0U; - - /* Reset errorCode */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); - - - /* Discard the received data */ - __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); - - /* Restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Complete Callback */ - husart->AbortCpltCallback(husart); -#else - /* Call legacy weak Abort Complete Callback */ - HAL_USART_AbortCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Handle USART interrupt request. - * @param husart USART handle. - * @retval None - */ -void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) -{ - uint32_t isrflags = READ_REG(husart->Instance->ISR); - uint32_t cr1its = READ_REG(husart->Instance->CR1); - uint32_t cr3its = READ_REG(husart->Instance->CR3); - - uint32_t errorflags; - uint32_t errorcode; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - if (errorflags == 0U) - { - /* USART in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - if (husart->RxISR != NULL) - { - husart->RxISR(husart); - } - return; - } - } - - /* If some errors occur */ - if ((errorflags != 0U) - && (((cr3its & USART_CR3_EIE) != 0U) - || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) - { - /* USART parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); - - husart->ErrorCode |= HAL_USART_ERROR_PE; - } - - /* USART frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); - - husart->ErrorCode |= HAL_USART_ERROR_FE; - } - - /* USART noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); - - husart->ErrorCode |= HAL_USART_ERROR_NE; - } - - /* USART Over-Run interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_ORE) != 0U) - && (((cr1its & USART_CR1_RXNEIE) != 0U) || - ((cr3its & USART_CR3_EIE) != 0U))) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); - - husart->ErrorCode |= HAL_USART_ERROR_ORE; - } - - /* USART Receiver Timeout interrupt occurred ---------------------------------*/ - if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) - { - __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); - - husart->ErrorCode |= HAL_USART_ERROR_RTO; - } - - - /* Call USART Error Call back function if need be --------------------------*/ - if (husart->ErrorCode != HAL_USART_ERROR_NONE) - { - /* USART in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE) != 0U) - && ((cr1its & USART_CR1_RXNEIE) != 0U)) - { - if (husart->RxISR != NULL) - { - husart->RxISR(husart); - } - } - - /* If Overrun error occurs, or if any error occurs in DMA mode reception, - consider error as blocking */ - errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE; - if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) || - (errorcode != 0U)) - { - /* Blocking error : transfer is aborted - Set the USART state ready to be able to start again the process, - Disable Interrupts, and disable DMA requests, if ongoing */ - USART_EndTransfer(husart); - - /* Abort the USART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) - { - /* Disable the USART DMA Rx request if enabled */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); - - /* Abort the USART DMA Tx channel */ - if (husart->hdmatx != NULL) - { - /* Set the USART Tx DMA Abort callback to NULL : no callback - executed at end of DMA abort procedure */ - husart->hdmatx->XferAbortCallback = NULL; - - /* Abort DMA TX */ - (void)HAL_DMA_Abort_IT(husart->hdmatx); - } - - /* Abort the USART DMA Rx channel */ - if (husart->hdmarx != NULL) - { - /* Set the USART Rx DMA Abort callback : - will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ - husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) - { - /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ - husart->hdmarx->XferAbortCallback(husart->hdmarx); - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Error Callback */ - husart->ErrorCallback(husart); -#else - /* Call legacy weak Error Callback */ - HAL_USART_ErrorCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Error Callback */ - husart->ErrorCallback(husart); -#else - /* Call legacy weak Error Callback */ - HAL_USART_ErrorCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Error Callback */ - husart->ErrorCallback(husart); -#else - /* Call legacy weak Error Callback */ - HAL_USART_ErrorCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - - /* USART in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_ISR_TXE) != 0U) - && ((cr1its & USART_CR1_TXEIE) != 0U)) - { - if (husart->TxISR != NULL) - { - husart->TxISR(husart); - } - return; - } - - /* USART in mode Transmitter (transmission end) -----------------------------*/ - if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) - { - USART_EndTransmit_IT(husart); - return; - } - -} - -/** - * @brief Tx Transfer completed callback. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_TxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_TxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_USART_RxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_RxHalfCpltCallback can be implemented in the user file - */ -} - -/** - * @brief Tx/Rx Transfers completed callback for the non-blocking process. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_TxRxCpltCallback can be implemented in the user file - */ -} - -/** - * @brief USART error callback. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_ErrorCallback can be implemented in the user file. - */ -} - -/** - * @brief USART Abort Complete callback. - * @param husart USART handle. - * @retval None - */ -__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(husart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_USART_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief USART Peripheral State and Error functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) Return the USART handle state - (+) Return the USART handle error code - -@endverbatim - * @{ - */ - - -/** - * @brief Return the USART handle state. - * @param husart pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART. - * @retval USART handle state - */ -HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) -{ - return husart->State; -} - -/** - * @brief Return the USART error code. - * @param husart pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART. - * @retval USART handle Error Code - */ -uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) -{ - return husart->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup USART_Private_Functions USART Private Functions - * @{ - */ - -/** - * @brief Initialize the callbacks to their default values. - * @param husart USART handle. - * @retval none - */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) -{ - /* Init the USART Callback settings */ - husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ - husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ - husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ -} -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - -/** - * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). - * @param husart USART handle. - * @retval None - */ -static void USART_EndTransfer(USART_HandleTypeDef *husart) -{ - /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* At end of process, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; -} - -/** - * @brief DMA USART transmit process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - - /* DMA Normal mode */ - if (hdma->Init.Mode != DMA_CIRCULAR) - { - husart->TxXferCount = 0U; - - if (husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - /* Enable the USART Transmit Complete Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - } - } - /* DMA Circular mode */ - else - { - if (husart->State == HAL_USART_STATE_BUSY_TX) - { -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Complete Callback */ - husart->TxCpltCallback(husart); -#else - /* Call legacy weak Tx Complete Callback */ - HAL_USART_TxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - } -} - -/** - * @brief DMA USART transmit process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Half Complete Callback */ - husart->TxHalfCpltCallback(husart); -#else - /* Call legacy weak Tx Half Complete Callback */ - HAL_USART_TxHalfCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA USART receive process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - - /* DMA Normal mode */ - if (hdma->Init.Mode != DMA_CIRCULAR) - { - husart->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit - in USART CR3 register */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); - /* similarly, disable the DMA TX transfer that was started to provide the - clock to the slave device */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); - - if (husart->State == HAL_USART_STATE_BUSY_RX) - { -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Rx Complete Callback */ - husart->RxCpltCallback(husart); -#else - /* Call legacy weak Rx Complete Callback */ - HAL_USART_RxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ - else - { -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Rx Complete Callback */ - husart->TxRxCpltCallback(husart); -#else - /* Call legacy weak Tx Rx Complete Callback */ - HAL_USART_TxRxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - husart->State = HAL_USART_STATE_READY; - } - /* DMA circular mode */ - else - { - if (husart->State == HAL_USART_STATE_BUSY_RX) - { -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Rx Complete Callback */ - husart->RxCpltCallback(husart); -#else - /* Call legacy weak Rx Complete Callback */ - HAL_USART_RxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ - else - { -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Rx Complete Callback */ - husart->TxRxCpltCallback(husart); -#else - /* Call legacy weak Tx Rx Complete Callback */ - HAL_USART_TxRxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - } -} - -/** - * @brief DMA USART receive process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Rx Half Complete Callback */ - husart->RxHalfCpltCallback(husart); -#else - /* Call legacy weak Rx Half Complete Callback */ - HAL_USART_RxHalfCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA USART communication error callback. - * @param hdma DMA handle. - * @retval None - */ -static void USART_DMAError(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - - husart->RxXferCount = 0U; - husart->TxXferCount = 0U; - USART_EndTransfer(husart); - - husart->ErrorCode |= HAL_USART_ERROR_DMA; - husart->State = HAL_USART_STATE_READY; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Error Callback */ - husart->ErrorCallback(husart); -#else - /* Call legacy weak Error Callback */ - HAL_USART_ErrorCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA USART communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - husart->RxXferCount = 0U; - husart->TxXferCount = 0U; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Error Callback */ - husart->ErrorCallback(husart); -#else - /* Call legacy weak Error Callback */ - HAL_USART_ErrorCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA USART Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - - husart->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (husart->hdmarx != NULL) - { - if (husart->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - husart->TxXferCount = 0U; - husart->RxXferCount = 0U; - - /* Reset errorCode */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); - - /* Restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Complete Callback */ - husart->AbortCpltCallback(husart); -#else - /* Call legacy weak Abort Complete Callback */ - HAL_USART_AbortCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - -} - - -/** - * @brief DMA USART Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); - - husart->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (husart->hdmatx != NULL) - { - if (husart->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - husart->TxXferCount = 0U; - husart->RxXferCount = 0U; - - /* Reset errorCode */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); - - /* Restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Complete Callback */ - husart->AbortCpltCallback(husart); -#else - /* Call legacy weak Abort Complete Callback */ - HAL_USART_AbortCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ -} - - -/** - * @brief Handle USART Communication Timeout. It waits - * until a flag is no longer in the specified status. - * @param husart USART handle. - * @param Flag Specifies the USART flag to check. - * @param Status the actual Flag status (SET or RESET). - * @param Tickstart Tick start value - * @param Timeout timeout duration. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - -/** - * @brief Configure the USART peripheral. - * @param husart USART handle. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) -{ - uint32_t tmpreg; - USART_ClockSourceTypeDef clocksource; - HAL_StatusTypeDef ret = HAL_OK; - uint16_t brrtemp; - uint32_t usartdiv = 0x00000000; - uint32_t pclk; - - /* Check the parameters */ - assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); - assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); - assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); - assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); - assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); - assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); - assert_param(IS_USART_PARITY(husart->Init.Parity)); - assert_param(IS_USART_MODE(husart->Init.Mode)); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE and RE bits and configure - * the USART Word Length, Parity and Mode: - * set the M bits according to husart->Init.WordLength value - * set PCE and PS bits according to husart->Init.Parity value - * set TE and RE bits according to husart->Init.Mode value - * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ - tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; - MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*---------------------------- USART CR2 Configuration ---------------------*/ - /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: - * set CPOL bit according to husart->Init.CLKPolarity value - * set CPHA bit according to husart->Init.CLKPhase value - * set LBCL bit according to husart->Init.CLKLastBit value (used in SPI master mode only) - * set STOP[13:12] bits according to husart->Init.StopBits value */ - tmpreg = (uint32_t)(USART_CLOCK_ENABLE); - tmpreg |= (uint32_t)husart->Init.CLKLastBit; - tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); - tmpreg |= (uint32_t)husart->Init.StopBits; - MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); - - - /*-------------------------- USART BRR Configuration -----------------------*/ - /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ - USART_GETCLOCKSOURCE(husart, clocksource); - - switch (clocksource) - { - case USART_CLOCKSOURCE_PCLK1: - pclk = HAL_RCC_GetPCLK1Freq(); - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); - break; - case USART_CLOCKSOURCE_PCLK2: - pclk = HAL_RCC_GetPCLK2Freq(); - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); - break; - case USART_CLOCKSOURCE_HSI: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); - break; - case USART_CLOCKSOURCE_SYSCLK: - pclk = HAL_RCC_GetSysClockFreq(); - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); - break; - case USART_CLOCKSOURCE_LSE: - usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); - break; - default: - ret = HAL_ERROR; - break; - } - - /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ - if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) - { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - husart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; - } - - - /* Clear ISR function pointers */ - husart->RxISR = NULL; - husart->TxISR = NULL; - - return ret; -} - -/** - * @brief Check the USART Idle State. - * @param husart USART handle. - * @retval HAL status - */ -static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) -{ - uint32_t tickstart; - - /* Initialize the USART ErrorCode */ - husart->ErrorCode = HAL_USART_ERROR_NONE; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } -#if defined(USART_ISR_REACK) - /* Check if the Receiver is enabled */ - if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) - { - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } -#endif /* USART_ISR_REACK */ - - /* Initialize the USART state*/ - husart->State = HAL_USART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(husart); - - return HAL_OK; -} - -/** - * @brief Simplex send an amount of data in non-blocking mode. - * @note Function called under interruption only, once - * interruptions have been enabled by HAL_USART_Transmit_IT(). - * @note The USART errors are not managed to avoid the overrun error. - * @note ISR function executed when data word length is less than 9 bits long. - * @param husart USART handle. - * @retval None - */ -static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) -{ - const HAL_USART_StateTypeDef state = husart->State; - - /* Check that a Tx process is ongoing */ - if ((state == HAL_USART_STATE_BUSY_TX) || - (state == HAL_USART_STATE_BUSY_TX_RX)) - { - if (husart->TxXferCount == 0U) - { - /* Disable the USART Transmit data register empty interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - - /* Enable the USART Transmit Complete Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - } - else - { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); - husart->pTxBuffPtr++; - husart->TxXferCount--; - } - } -} - -/** - * @brief Simplex send an amount of data in non-blocking mode. - * @note Function called under interruption only, once - * interruptions have been enabled by HAL_USART_Transmit_IT(). - * @note The USART errors are not managed to avoid the overrun error. - * @note ISR function executed when data word length is 9 bits long. - * @param husart USART handle. - * @retval None - */ -static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) -{ - const HAL_USART_StateTypeDef state = husart->State; - const uint16_t *tmp; - - if ((state == HAL_USART_STATE_BUSY_TX) || - (state == HAL_USART_STATE_BUSY_TX_RX)) - { - if (husart->TxXferCount == 0U) - { - /* Disable the USART Transmit data register empty interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - - /* Enable the USART Transmit Complete Interrupt */ - __HAL_USART_ENABLE_IT(husart, USART_IT_TC); - } - else - { - tmp = (const uint16_t *) husart->pTxBuffPtr; - husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); - husart->pTxBuffPtr += 2U; - husart->TxXferCount--; - } - } -} - - -/** - * @brief Wraps up transmission in non-blocking mode. - * @param husart Pointer to a USART_HandleTypeDef structure that contains - * the configuration information for the specified USART module. - * @retval None - */ -static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) -{ - /* Disable the USART Transmit Complete Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TC); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - /* Clear TxISR function pointer */ - husart->TxISR = NULL; - - if (husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Clear overrun flag and discard the received data */ - __HAL_USART_CLEAR_OREFLAG(husart); - __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); - - /* Tx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Complete Callback */ - husart->TxCpltCallback(husart); -#else - /* Call legacy weak Tx Complete Callback */ - HAL_USART_TxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - else if (husart->RxXferCount == 0U) - { - /* TxRx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Rx Complete Callback */ - husart->TxRxCpltCallback(husart); -#else - /* Call legacy weak Tx Rx Complete Callback */ - HAL_USART_TxRxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } -} - - -/** - * @brief Simplex receive an amount of data in non-blocking mode. - * @note Function called under interruption only, once - * interruptions have been enabled by HAL_USART_Receive_IT(). - * @note ISR function executed when data word length is less than 9 bits long. - * @param husart USART handle - * @retval None - */ -static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) -{ - const HAL_USART_StateTypeDef state = husart->State; - uint16_t txdatacount; - uint16_t uhMask = husart->Mask; - - if ((state == HAL_USART_STATE_BUSY_RX) || - (state == HAL_USART_STATE_BUSY_TX_RX)) - { - *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); - husart->pRxBuffPtr++; - husart->RxXferCount--; - - if (husart->RxXferCount == 0U) - { - /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Clear RxISR function pointer */ - husart->RxISR = NULL; - - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ - txdatacount = husart->TxXferCount; - - if (state == HAL_USART_STATE_BUSY_RX) - { - - /* Rx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Rx Complete Callback */ - husart->RxCpltCallback(husart); -#else - /* Call legacy weak Rx Complete Callback */ - HAL_USART_RxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && - (txdatacount == 0U)) - { - /* TxRx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Rx Complete Callback */ - husart->TxRxCpltCallback(husart); -#else - /* Call legacy weak Tx Rx Complete Callback */ - HAL_USART_TxRxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } - } - else if (state == HAL_USART_STATE_BUSY_RX) - { - /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); - } - else - { - /* Nothing to do */ - } - } -} - -/** - * @brief Simplex receive an amount of data in non-blocking mode. - * @note Function called under interruption only, once - * interruptions have been enabled by HAL_USART_Receive_IT(). - * @note ISR function executed when data word length is 9 bits long. - * @param husart USART handle - * @retval None - */ -static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) -{ - const HAL_USART_StateTypeDef state = husart->State; - uint16_t txdatacount; - uint16_t *tmp; - uint16_t uhMask = husart->Mask; - - if ((state == HAL_USART_STATE_BUSY_RX) || - (state == HAL_USART_STATE_BUSY_TX_RX)) - { - tmp = (uint16_t *) husart->pRxBuffPtr; - *tmp = (uint16_t)(husart->Instance->RDR & uhMask); - husart->pRxBuffPtr += 2U; - husart->RxXferCount--; - - if (husart->RxXferCount == 0U) - { - /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ - CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); - - /* Clear RxISR function pointer */ - husart->RxISR = NULL; - - /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ - txdatacount = husart->TxXferCount; - - if (state == HAL_USART_STATE_BUSY_RX) - { - - /* Rx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Rx Complete Callback */ - husart->RxCpltCallback(husart); -#else - /* Call legacy weak Rx Complete Callback */ - HAL_USART_RxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && - (txdatacount == 0U)) - { - /* TxRx process is completed, restore husart->State to Ready */ - husart->State = HAL_USART_STATE_READY; - -#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Rx Complete Callback */ - husart->TxRxCpltCallback(husart); -#else - /* Call legacy weak Tx Rx Complete Callback */ - HAL_USART_TxRxCpltCallback(husart); -#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } - } - else if (state == HAL_USART_STATE_BUSY_RX) - { - /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ - husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); - } - else - { - /* Nothing to do */ - } - } -} - - -/** - * @} - */ - -#endif /* HAL_USART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - +/** + ****************************************************************************** + * @file stm32f7xx_hal_usart.c + * @author MCD Application Team + * @brief USART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter + * Peripheral (USART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Error functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The USART HAL driver can be used as follows: + + (#) Declare a USART_HandleTypeDef handle structure (eg. USART_HandleTypeDef husart). + (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) USART pins configuration: + (+++) Enable the clock for the USART GPIOs. + (+++) Configure these USART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(), + HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) USART interrupts handling: + -@@- The specific USART interrupts (Transmission complete interrupt, + RXNE interrupt and Error Interrupts) will be managed using the macros + __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process. + (++) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA() + HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the USART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer + complete interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, and Mode + (Receiver/Transmitter) in the husart handle Init structure. + + (#) Initialize the USART registers by calling the HAL_USART_Init() API: + (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) + by calling the customized HAL_USART_MspInit(&husart) API. + + [..] + (@) To configure and enable/disable the USART to wake up the MCU from stop mode, resort to UART API's + HAL_UARTEx_StopModeWakeUpSourceConfig(), HAL_UARTEx_EnableStopMode() and + HAL_UARTEx_DisableStopMode() in casting the USART handle to UART type UART_HandleTypeDef. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_USART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_USART_RegisterCallback() to register a user callback. + Function HAL_USART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_USART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_USART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) TxRxCpltCallback : Tx Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) MspInitCallback : USART MspInit. + (+) MspDeInitCallback : USART MspDeInit. + + [..] + By default, after the HAL_USART_Init() and when the state is HAL_USART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_USART_TxCpltCallback(), HAL_USART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_USART_Init() + and HAL_USART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_USART_Init() and HAL_USART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_USART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_USART_STATE_READY or HAL_USART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_USART_RegisterCallback() before calling HAL_USART_DeInit() + or HAL_USART_Init() function. + + [..] + When The compilation define USE_HAL_USART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup USART USART + * @brief HAL USART Synchronous SPI module driver + * @{ + */ + +#ifdef HAL_USART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +#define USART_DUMMY_DATA ((uint16_t) 0xFFFF) /*!< USART transmitted dummy data */ +#define USART_TEACK_REACK_TIMEOUT 1000U /*!< USART TX or RX enable acknowledge time-out value */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | \ + USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) /*!< USART CR1 fields of parameters set by USART_SetConfig API */ +#define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ + USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /*!< USART CR2 fields of parameters set by USART_SetConfig API */ + +#define USART_BRR_MIN 0x10U /* USART BRR minimum authorized value */ +#define USART_BRR_MAX 0xFFFFU /* USART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup USART_Private_Functions + * @{ + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +static void USART_EndTransfer(USART_HandleTypeDef *husart); +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void USART_DMAError(DMA_HandleTypeDef *hdma); +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart); +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart); +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart); +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart); + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USART + in synchronous SPI master mode. + (+) For the synchronous SPI mode only these parameters can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) USART polarity + (++) USART phase + (++) USART LastBit + (++) Receiver/transmitter modes + + [..] + The HAL_USART_Init() function follows the USART synchronous SPI configuration + procedure (details for the procedure are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible USART formats are listed in the + following table. + + Table 1. USART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | USART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the USART mode according to the specified + * parameters in the USART_InitTypeDef and initialize the associated handle. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + if (husart->State == HAL_USART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + husart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + USART_InitCallbacksToDefault(husart); + + if (husart->MspInitCallback == NULL) + { + husart->MspInitCallback = HAL_USART_MspInit; + } + + /* Init the low level hardware */ + husart->MspInitCallback(husart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_USART_MspInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + husart->State = HAL_USART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_USART_DISABLE(husart); + + /* Set the Usart Communication parameters */ + if (USART_SetConfig(husart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In Synchronous SPI mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register + - HDSEL, SCEN and IREN bits in the USART_CR3 register. + */ + husart->Instance->CR2 &= ~USART_CR2_LINEN; + husart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN); + + /* Enable the Peripheral */ + __HAL_USART_ENABLE(husart); + + /* TEACK and/or REACK to check before moving husart->State to Ready */ + return (USART_CheckIdleState(husart)); +} + +/** + * @brief DeInitialize the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) +{ + /* Check the USART handle allocation */ + if (husart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_USART_INSTANCE(husart->Instance)); + + husart->State = HAL_USART_STATE_BUSY; + + husart->Instance->CR1 = 0x0U; + husart->Instance->CR2 = 0x0U; + husart->Instance->CR3 = 0x0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + if (husart->MspDeInitCallback == NULL) + { + husart->MspDeInitCallback = HAL_USART_MspDeInit; + } + /* DeInit the low level hardware */ + husart->MspDeInitCallback(husart); +#else + /* DeInit the low level hardware */ + HAL_USART_MspDeInit(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_RESET; + + /* Process Unlock */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Initialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the USART MSP. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User USART Callback + * To be used to override the weak predefined callback + * @note The HAL_USART_RegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status ++ */ +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (husart->State == HAL_USART_STATE_READY) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = pCallback; + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = pCallback; + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = pCallback; + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = pCallback; + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = pCallback; + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = pCallback; + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = pCallback; + break; + + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (husart->State == HAL_USART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = pCallback; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an USART Callback + * USART callaback is redirected to the weak predefined callback + * @note The HAL_USART_UnRegisterCallback() may be called before HAL_USART_Init() in HAL_USART_STATE_RESET + * to un-register callbacks for HAL_USART_MSPINIT_CB_ID and HAL_USART_MSPDEINIT_CB_ID + * @param husart usart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_USART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_USART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_USART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_USART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_TX_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_USART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_USART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_USART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_USART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_USART_STATE_READY == husart->State) + { + switch (CallbackID) + { + case HAL_USART_TX_HALFCOMPLETE_CB_ID : + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_USART_TX_COMPLETE_CB_ID : + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_USART_RX_HALFCOMPLETE_CB_ID : + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_USART_RX_COMPLETE_CB_ID : + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_USART_TX_RX_COMPLETE_CB_ID : + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + break; + + case HAL_USART_ERROR_CB_ID : + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_USART_ABORT_COMPLETE_CB_ID : + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_USART_STATE_RESET == husart->State) + { + switch (CallbackID) + { + case HAL_USART_MSPINIT_CB_ID : + husart->MspInitCallback = HAL_USART_MspInit; + break; + + case HAL_USART_MSPDEINIT_CB_ID : + husart->MspDeInitCallback = HAL_USART_MspDeInit; + break; + + default : + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + husart->ErrorCode |= HAL_USART_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @brief USART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART synchronous SPI + data transfers. + + [..] The USART Synchronous SPI supports master mode only: it cannot receive or send data related to an input + clock (SCLK is always an output). + + [..] + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated USART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_USART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_USART_Transmit() in simplex mode + (++) HAL_USART_Receive() in full duplex receive only + (++) HAL_USART_TransmitReceive() in full duplex mode + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_USART_Transmit_IT() in simplex mode + (++) HAL_USART_Receive_IT() in full duplex receive only + (++) HAL_USART_TransmitReceive_IT() in full duplex mode + (++) HAL_USART_IRQHandler() + + (#) No-Blocking mode API's with DMA are : + (++) HAL_USART_Transmit_DMA() in simplex mode + (++) HAL_USART_Receive_DMA() in full duplex receive only + (++) HAL_USART_TransmitReceive_DMA() in full duplex mode + (++) HAL_USART_DMAPause() + (++) HAL_USART_DMAResume() + (++) HAL_USART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_USART_TxCpltCallback() + (++) HAL_USART_RxCpltCallback() + (++) HAL_USART_TxHalfCpltCallback() + (++) HAL_USART_RxHalfCpltCallback() + (++) HAL_USART_ErrorCallback() + (++) HAL_USART_TxRxCpltCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_USART_Abort() + (++) HAL_USART_Abort_IT() + + (#) For Abort services based on interrupts (HAL_USART_Abort_IT), a Abort Complete Callbacks is provided: + (++) HAL_USART_AbortCpltCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, + Parity Error or Noise Error in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify + error type, and HAL_USART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on USART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, + and HAL_USART_ErrorCallback() user callback is executed. + +@endverbatim + * @{ + */ + +/** + * @brief Simplex send an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout) +{ + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pTxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + } + else + { + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + } + + /* Check the remaining data to be sent */ + while (husart->TxXferCount > 0U) + { + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & 0x01FFU); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & 0xFFU); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + /* Clear Transmission Complete Flag */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + __HAL_USART_SEND_REQ(husart, USART_TXDATA_FLUSH_REQUEST); + + /* At end of Tx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + prxdata16bits = NULL; + } + + /* as long as data have to be received */ + while (husart->RxXferCount > 0U) + { + { + /* Wait until TXE flag is set to send dummy byte in order to generate the + * clock for the slave to send data. + * Whatever the frame length (7, 8 or 9-bit long), the same dummy value + * can be written for all the cases. */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x0FF); + } + + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + + } + + + /* At end of Rx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in blocking mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) +{ + uint8_t *prxdata8bits; + uint16_t *prxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; + uint16_t uhMask; + uint16_t rxdatacount; + uint32_t tickstart; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + husart->RxXferSize = Size; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->RxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + uhMask = husart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + prxdata8bits = NULL; + ptxdata8bits = NULL; + ptxdata16bits = (const uint16_t *) pTxData; + prxdata16bits = (uint16_t *) pRxData; + } + else + { + prxdata8bits = pRxData; + ptxdata8bits = pTxData; + ptxdata16bits = NULL; + prxdata16bits = NULL; + } + + if (husart->TxXferCount == 0x01U) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + /* Check the remain data to be sent */ + /* rxdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + rxdatacount = husart->RxXferCount; + while ((husart->TxXferCount > 0U) || (rxdatacount > 0U)) + { + if (husart->TxXferCount > 0U) + { + /* Wait until TXE flag is set to send data */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + if (ptxdata8bits == NULL) + { + husart->Instance->TDR = (uint16_t)(*ptxdata16bits & uhMask); + ptxdata16bits++; + } + else + { + husart->Instance->TDR = (uint8_t)(*ptxdata8bits & (uint8_t)(uhMask & 0xFFU)); + ptxdata8bits++; + } + + husart->TxXferCount--; + } + + if (husart->RxXferCount > 0U) + { + /* Wait for RXNE Flag */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + if (prxdata8bits == NULL) + { + *prxdata16bits = (uint16_t)(husart->Instance->RDR & uhMask); + prxdata16bits++; + } + else + { + *prxdata8bits = (uint8_t)(husart->Instance->RDR & (uint8_t)(uhMask & 0xFFU)); + prxdata8bits++; + } + + husart->RxXferCount--; + } + rxdatacount = husart->RxXferCount; + } + + /* At end of TxRx process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + husart->TxISR = NULL; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + /* The USART Error Interrupts: (Frame error, noise error, overrun error) + are not managed by the USART Transmit Process to avoid the overrun interrupt + when the usart mode is configured for transmit and receive "USART_MODE_TX_RX" + to benefit for the frame error and noise interrupts the usart mode should be + configured only for transmit "USART_MODE_TX" */ + + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Transmit Data Register Empty Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TXE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note To receive synchronous data, dummy data are simultaneously transmitted. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->RxISR = NULL; + + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Parity Error and Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); + } + } + + { + /* Send dummy data in order to generate the clock for the Slave to send the next data. + */ + { + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Send and Receive an amount of data in interrupt mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent (same amount to be received). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->RxXferCount = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + /* Computation of USART mask to apply to RDR register */ + USART_MASK_COMPUTATION(husart); + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + { + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) + { + husart->TxISR = USART_TxISR_16BIT; + husart->RxISR = USART_RxISR_16BIT; + } + else + { + husart->TxISR = USART_TxISR_8BIT; + husart->RxISR = USART_RxISR_8BIT; + } + + /* Process Locked */ + __HAL_UNLOCK(husart); + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART Parity Error and USART Data Register not empty Interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + } + else + { + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); + } + + /* Enable the USART Transmit Data Register Empty Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_TXEIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in DMA mode. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pTxData. + * @param husart USART handle. + * @param pTxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + const uint32_t *tmp; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + husart->TxXferCount = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX; + + if (husart->hdmatx != NULL) + { + /* Set the USART DMA transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the DMA error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Enable the USART transmit DMA channel */ + tmp = (const uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } + + if (status == HAL_OK) + { + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the USART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note The USART DMA transmit channel must be configured in order to generate the clock for the slave. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pRxData. + * @param husart USART handle. + * @param pRxData pointer to data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t *tmp = (uint32_t *)&pRxData; + + /* Check that a Rx process is not already ongoing */ + if (husart->State == HAL_USART_STATE_READY) + { + if ((pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pRxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_RX; + + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* Enable the USART receive DMA channel */ + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(uint32_t *)tmp, Size); + } + + { + /* Enable the USART transmit DMA channel: the transmit channel is used in order + to generate in the non-blocking mode the clock to the slave device, + this mode isn't a simplex receive mode but a full-duplex receive mode */ + + /* Set the USART DMA Tx Complete and Error callback to Null */ + if (husart->hdmatx != NULL) + { + husart->hdmatx->XferErrorCallback = NULL; + husart->hdmatx->XferHalfCpltCallback = NULL; + husart->hdmatx->XferCpltCallback = NULL; + status = HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if (husart->hdmarx != NULL) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode. + * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. + * @note When USART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data and the received data are handled as sets of u16. In this case, Size must indicate the number + * of u16 available through pTxData and through pRxData. + * @param husart USART handle. + * @param pTxData pointer to TX data buffer (u8 or u16 data elements). + * @param pRxData pointer to RX data buffer (u8 or u16 data elements). + * @param Size amount of data elements (u8 or u16) to be received/sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) +{ + HAL_StatusTypeDef status; + const uint32_t *tmp; + + if (husart->State == HAL_USART_STATE_READY) + { + if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(husart); + + husart->pRxBuffPtr = pRxData; + husart->RxXferSize = Size; + husart->pTxBuffPtr = pTxData; + husart->TxXferSize = Size; + + husart->ErrorCode = HAL_USART_ERROR_NONE; + husart->State = HAL_USART_STATE_BUSY_TX_RX; + + if ((husart->hdmarx != NULL) && (husart->hdmatx != NULL)) + { + /* Set the USART DMA Rx transfer complete callback */ + husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt; + + /* Set the USART DMA Tx transfer complete callback */ + husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt; + + /* Set the USART DMA Half transfer complete callback */ + husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt; + + /* Set the USART DMA Tx transfer error callback */ + husart->hdmatx->XferErrorCallback = USART_DMAError; + + /* Set the USART DMA Rx transfer error callback */ + husart->hdmarx->XferErrorCallback = USART_DMAError; + + /* Enable the USART receive DMA channel */ + tmp = (uint32_t *)&pRxData; + status = HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->RDR, *(const uint32_t *)tmp, Size); + + /* Enable the USART transmit DMA channel */ + if (status == HAL_OK) + { + tmp = (const uint32_t *)&pTxData; + status = HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->TDR, Size); + } + } + else + { + status = HAL_ERROR; + } + + if (status == HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear the TC flag in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_TCF); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the USART CR3 register */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + if (husart->hdmarx != NULL) + { + status = HAL_DMA_Abort(husart->hdmarx); + } + + /* No need to check on error code */ + UNUSED(status); + + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + /* Restore husart->State to ready */ + husart->State = HAL_USART_STATE_READY; + + return HAL_ERROR; + } + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) && + (state == HAL_USART_STATE_BUSY_TX)) + { + /* Disable the USART DMA Tx request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the USART DMA Tx request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Disable the USART DMA Rx request */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + } + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Process Locked */ + __HAL_LOCK(husart); + + if (state == HAL_USART_STATE_BUSY_TX) + { + /* Enable the USART DMA Tx request */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + else if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + /* Clear the Overrun flag before resuming the Rx transfer*/ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (husart->Init.Parity != USART_PARITY_NONE) + { + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } + SET_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Enable the USART DMA Rx request before the DMA Tx request */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Enable the USART DMA Tx request */ + SET_BIT(husart->Instance->CR3, USART_CR3_DMAT); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param husart USART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback() / + HAL_USART_TxHalfCpltCallback / HAL_USART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + /* Disable the USART Tx/Rx DMA requests */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA tx channel */ + if (husart->hdmatx != NULL) + { + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + /* Abort the USART DMA rx channel */ + if (husart->hdmarx != NULL) + { + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + USART_EndTransfer(husart); + husart->State = HAL_USART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) +{ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable the USART DMA Tx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmatx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (husart->hdmarx != NULL) + { + /* Set the USART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(husart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(husart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + husart->ErrorCode = HAL_USART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Reset Handle ErrorCode to No Error */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param husart USART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable USART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) +{ + uint32_t abortcplt = 1U; + + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* If DMA Tx and/or DMA Rx Handles are associated to USART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (husart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + husart->hdmatx->XferAbortCallback = USART_DMATxAbortCallback; + } + else + { + husart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (husart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if USART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + husart->hdmarx->XferAbortCallback = USART_DMARxAbortCallback; + } + else + { + husart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the USART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAT)) + { + /* Disable DMA Tx at USART level */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the USART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmatx != NULL) + { + /* USART Tx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(husart->hdmatx) != HAL_OK) + { + husart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the USART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (husart->hdmarx != NULL) + { + /* USART Rx DMA Abort callback has already been initialised : + will lead to call HAL_USART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + husart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + + /* Discard the received data */ + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle USART interrupt request. + * @param husart USART handle. + * @retval None + */ +void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) +{ + uint32_t isrflags = READ_REG(husart->Instance->ISR); + uint32_t cr1its = READ_REG(husart->Instance->CR1); + uint32_t cr3its = READ_REG(husart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && (((cr3its & USART_CR3_EIE) != 0U) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != 0U))) + { + /* USART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_PEF); + + husart->ErrorCode |= HAL_USART_ERROR_PE; + } + + /* USART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_FEF); + + husart->ErrorCode |= HAL_USART_ERROR_FE; + } + + /* USART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_NEF); + + husart->ErrorCode |= HAL_USART_ERROR_NE; + } + + /* USART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE) != 0U) || + ((cr3its & USART_CR3_EIE) != 0U))) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + + husart->ErrorCode |= HAL_USART_ERROR_ORE; + } + + /* USART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_USART_CLEAR_IT(husart, USART_CLEAR_RTOF); + + husart->ErrorCode |= HAL_USART_ERROR_RTO; + } + + + /* Call USART Error Call back function if need be --------------------------*/ + if (husart->ErrorCode != HAL_USART_ERROR_NONE) + { + /* USART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE) != 0U) + && ((cr1its & USART_CR1_RXNEIE) != 0U)) + { + if (husart->RxISR != NULL) + { + husart->RxISR(husart); + } + } + + /* If Overrun error occurs, or if any error occurs in DMA mode reception, + consider error as blocking */ + errorcode = husart->ErrorCode & HAL_USART_ERROR_ORE; + if ((HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) || + (errorcode != 0U)) + { + /* Blocking error : transfer is aborted + Set the USART state ready to be able to start again the process, + Disable Interrupts, and disable DMA requests, if ongoing */ + USART_EndTransfer(husart); + + /* Abort the USART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(husart->Instance->CR3, USART_CR3_DMAR)) + { + /* Disable the USART DMA Rx request if enabled */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR | USART_CR3_DMAR); + + /* Abort the USART DMA Tx channel */ + if (husart->hdmatx != NULL) + { + /* Set the USART Tx DMA Abort callback to NULL : no callback + executed at end of DMA abort procedure */ + husart->hdmatx->XferAbortCallback = NULL; + + /* Abort DMA TX */ + (void)HAL_DMA_Abort_IT(husart->hdmatx); + } + + /* Abort the USART DMA Rx channel */ + if (husart->hdmarx != NULL) + { + /* Set the USART Rx DMA Abort callback : + will lead to call HAL_USART_ErrorCallback() at end of DMA abort procedure */ + husart->hdmarx->XferAbortCallback = USART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(husart->hdmarx) != HAL_OK) + { + /* Call Directly husart->hdmarx->XferAbortCallback function in case of error */ + husart->hdmarx->XferAbortCallback(husart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + + /* USART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE) != 0U) + && ((cr1its & USART_CR1_TXEIE) != 0U)) + { + if (husart->TxISR != NULL) + { + husart->TxISR(husart); + } + return; + } + + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + USART_EndTransmit_IT(husart); + return; + } + +} + +/** + * @brief Tx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_USART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_RxHalfCpltCallback can be implemented in the user file + */ +} + +/** + * @brief Tx/Rx Transfers completed callback for the non-blocking process. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_TxRxCpltCallback can be implemented in the user file + */ +} + +/** + * @brief USART error callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief USART Abort Complete callback. + * @param husart USART handle. + * @retval None + */ +__weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(husart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_USART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup USART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief USART Peripheral State and Error functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the USART handle state + (+) Return the USART handle error code + +@endverbatim + * @{ + */ + + +/** + * @brief Return the USART handle state. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle state + */ +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) +{ + return husart->State; +} + +/** + * @brief Return the USART error code. + * @param husart pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART. + * @retval USART handle Error Code + */ +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) +{ + return husart->ErrorCode; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup USART_Private_Functions USART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param husart USART handle. + * @retval none + */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) +void USART_InitCallbacksToDefault(USART_HandleTypeDef *husart) +{ + /* Init the USART Callback settings */ + husart->TxHalfCpltCallback = HAL_USART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + husart->TxCpltCallback = HAL_USART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + husart->RxHalfCpltCallback = HAL_USART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + husart->RxCpltCallback = HAL_USART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + husart->TxRxCpltCallback = HAL_USART_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ + husart->ErrorCallback = HAL_USART_ErrorCallback; /* Legacy weak ErrorCallback */ + husart->AbortCpltCallback = HAL_USART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ +} +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +/** + * @brief End ongoing transfer on USART peripheral (following error detection or Transfer completion). + * @param husart USART handle. + * @retval None + */ +static void USART_EndTransfer(USART_HandleTypeDef *husart) +{ + /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* At end of process, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; +} + +/** + * @brief DMA USART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + husart->TxXferCount = 0U; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + } + /* DMA Circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_TX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Half Complete Callback */ + husart->TxHalfCpltCallback(husart); +#else + /* Call legacy weak Tx Half Complete Callback */ + HAL_USART_TxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + /* DMA Normal mode */ + if (hdma->Init.Mode != DMA_CIRCULAR) + { + husart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE); + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT); + + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + husart->State = HAL_USART_STATE_READY; + } + /* DMA circular mode */ + else + { + if (husart->State == HAL_USART_STATE_BUSY_RX) + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + } +} + +/** + * @brief DMA USART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Half Complete Callback */ + husart->RxHalfCpltCallback(husart); +#else + /* Call legacy weak Rx Half Complete Callback */ + HAL_USART_RxHalfCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + USART_EndTransfer(husart); + + husart->ErrorCode |= HAL_USART_ERROR_DMA; + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + husart->RxXferCount = 0U; + husart->TxXferCount = 0U; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Error Callback */ + husart->ErrorCallback(husart); +#else + /* Call legacy weak Error Callback */ + HAL_USART_ErrorCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA USART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmarx != NULL) + { + if (husart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + +} + + +/** + * @brief DMA USART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + USART_HandleTypeDef *husart = (USART_HandleTypeDef *)(hdma->Parent); + + husart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (husart->hdmatx != NULL) + { + if (husart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + husart->TxXferCount = 0U; + husart->RxXferCount = 0U; + + /* Reset errorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_USART_CLEAR_FLAG(husart, USART_CLEAR_OREF | USART_CLEAR_NEF | USART_CLEAR_PEF | USART_CLEAR_FEF); + + /* Restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Complete Callback */ + husart->AbortCpltCallback(husart); +#else + /* Call legacy weak Abort Complete Callback */ + HAL_USART_AbortCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +} + + +/** + * @brief Handle USART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param husart USART handle. + * @param Flag Specifies the USART flag to check. + * @param Status the actual Flag status (SET or RESET). + * @param Tickstart Tick start value + * @param Timeout timeout duration. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_TIMEOUT; + } + } + } + return HAL_OK; +} + +/** + * @brief Configure the USART peripheral. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) +{ + uint32_t tmpreg; + USART_ClockSourceTypeDef clocksource; + HAL_StatusTypeDef ret = HAL_OK; + uint16_t brrtemp; + uint32_t usartdiv = 0x00000000; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); + assert_param(IS_USART_PHASE(husart->Init.CLKPhase)); + assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit)); + assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate)); + assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength)); + assert_param(IS_USART_STOPBITS(husart->Init.StopBits)); + assert_param(IS_USART_PARITY(husart->Init.Parity)); + assert_param(IS_USART_MODE(husart->Init.Mode)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE and RE bits and configure + * the USART Word Length, Parity and Mode: + * set the M bits according to husart->Init.WordLength value + * set PCE and PS bits according to husart->Init.Parity value + * set TE and RE bits according to husart->Init.Mode value + * force OVER8 to 1 to allow to reach the maximum speed (Fclock/8) */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; + MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*---------------------------- USART CR2 Configuration ---------------------*/ + /* Clear and configure the USART Clock, CPOL, CPHA, LBCL and STOP bits: + * set CPOL bit according to husart->Init.CLKPolarity value + * set CPHA bit according to husart->Init.CLKPhase value + * set LBCL bit according to husart->Init.CLKLastBit value (used in USART Synchronous SPI master mode only) + * set STOP[13:12] bits according to husart->Init.StopBits value */ + tmpreg = (uint32_t)(USART_CLOCK_ENABLE); + tmpreg |= (uint32_t)husart->Init.CLKLastBit; + tmpreg |= ((uint32_t)husart->Init.CLKPolarity | (uint32_t)husart->Init.CLKPhase); + tmpreg |= (uint32_t)husart->Init.StopBits; + MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); + + + /*-------------------------- USART BRR Configuration -----------------------*/ + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + USART_GETCLOCKSOURCE(husart, clocksource); + + switch (clocksource) + { + case USART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); + break; + case USART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); + break; + case USART_CLOCKSOURCE_HSI: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(HSI_VALUE, husart->Init.BaudRate)); + break; + case USART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(pclk, husart->Init.BaudRate)); + break; + case USART_CLOCKSOURCE_LSE: + usartdiv = (uint32_t)(USART_DIV_SAMPLING8(LSE_VALUE, husart->Init.BaudRate)); + break; + default: + ret = HAL_ERROR; + break; + } + + /* USARTDIV must be greater than or equal to 0d16 and smaller than or equal to ffff */ + if ((usartdiv >= USART_BRR_MIN) && (usartdiv <= USART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + husart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + + + /* Clear ISR function pointers */ + husart->RxISR = NULL; + husart->TxISR = NULL; + + return ret; +} + +/** + * @brief Check the USART Idle State. + * @param husart USART handle. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) +{ + uint32_t tickstart; + + /* Initialize the USART ErrorCode */ + husart->ErrorCode = HAL_USART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((husart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_TEACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } +#if defined(USART_ISR_REACK) + /* Check if the Receiver is enabled */ + if ((husart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (USART_WaitOnFlagUntilTimeout(husart, USART_ISR_REACK, RESET, tickstart, USART_TEACK_REACK_TIMEOUT) != HAL_OK) + { + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } +#endif /* USART_ISR_REACK */ + + /* Initialize the USART state*/ + husart->State = HAL_USART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(husart); + + return HAL_OK; +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when data word length is less than 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + + /* Check that a Tx process is ongoing */ + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr & (uint8_t)0xFF); + husart->pTxBuffPtr++; + husart->TxXferCount--; + } + } +} + +/** + * @brief Simplex send an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Transmit_IT(). + * @note The USART errors are not managed to avoid the overrun error. + * @note ISR function executed when data word length is 9 bits long. + * @param husart USART handle. + * @retval None + */ +static void USART_TxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + const uint16_t *tmp; + + if ((state == HAL_USART_STATE_BUSY_TX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + if (husart->TxXferCount == 0U) + { + /* Disable the USART Transmit data register empty interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + } + else + { + tmp = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->TDR = (uint16_t)(*tmp & 0x01FFU); + husart->pTxBuffPtr += 2U; + husart->TxXferCount--; + } + } +} + + +/** + * @brief Wraps up transmission in non-blocking mode. + * @param husart Pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval None + */ +static void USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + /* Clear TxISR function pointer */ + husart->TxISR = NULL; + + if (husart->State == HAL_USART_STATE_BUSY_TX) + { + /* Clear overrun flag and discard the received data */ + __HAL_USART_CLEAR_OREFLAG(husart); + __HAL_USART_SEND_REQ(husart, USART_RXDATA_FLUSH_REQUEST); + + /* Tx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Complete Callback */ + husart->TxCpltCallback(husart); +#else + /* Call legacy weak Tx Complete Callback */ + HAL_USART_TxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if (husart->RxXferCount == 0U) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } +} + + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when data word length is less than 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_8BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t uhMask = husart->Mask; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->RDR & (uint8_t)uhMask); + husart->pRxBuffPtr++; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if (state == HAL_USART_STATE_BUSY_RX) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + +/** + * @brief Simplex receive an amount of data in non-blocking mode. + * @note Function called under interruption only, once + * interruptions have been enabled by HAL_USART_Receive_IT(). + * @note ISR function executed when data word length is 9 bits long. + * @param husart USART handle + * @retval None + */ +static void USART_RxISR_16BIT(USART_HandleTypeDef *husart) +{ + const HAL_USART_StateTypeDef state = husart->State; + uint16_t txdatacount; + uint16_t *tmp; + uint16_t uhMask = husart->Mask; + + if ((state == HAL_USART_STATE_BUSY_RX) || + (state == HAL_USART_STATE_BUSY_TX_RX)) + { + tmp = (uint16_t *) husart->pRxBuffPtr; + *tmp = (uint16_t)(husart->Instance->RDR & uhMask); + husart->pRxBuffPtr += 2U; + husart->RxXferCount--; + + if (husart->RxXferCount == 0U) + { + /* Disable the USART Parity Error Interrupt and RXNE interrupt*/ + CLEAR_BIT(husart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE); + + /* Clear RxISR function pointer */ + husart->RxISR = NULL; + + /* txdatacount is a temporary variable for MISRAC2012-Rule-13.5 */ + txdatacount = husart->TxXferCount; + + if (state == HAL_USART_STATE_BUSY_RX) + { + + /* Rx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Complete Callback */ + husart->RxCpltCallback(husart); +#else + /* Call legacy weak Rx Complete Callback */ + HAL_USART_RxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else if ((READ_BIT(husart->Instance->CR1, USART_CR1_TCIE) != USART_CR1_TCIE) && + (txdatacount == 0U)) + { + /* TxRx process is completed, restore husart->State to Ready */ + husart->State = HAL_USART_STATE_READY; + +#if (USE_HAL_USART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Rx Complete Callback */ + husart->TxRxCpltCallback(husart); +#else + /* Call legacy weak Tx Rx Complete Callback */ + HAL_USART_TxRxCpltCallback(husart); +#endif /* USE_HAL_USART_REGISTER_CALLBACKS */ + } + else + { + /* Nothing to do */ + } + } + else if (state == HAL_USART_STATE_BUSY_RX) + { + /* Send dummy byte in order to generate the clock for the Slave to Send the next data */ + husart->Instance->TDR = (USART_DUMMY_DATA & (uint16_t)0x00FF); + } + else + { + /* Nothing to do */ + } + } +} + + +/** + * @} + */ + +#endif /* HAL_USART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c deleted file mode 100644 index dcdcbd5d..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c +++ /dev/null @@ -1,420 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_hal_wwdg.c - * @author MCD Application Team - * @brief WWDG HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Window Watchdog (WWDG) peripheral: - * + Initialization and Configuration functions - * + IO operation functions - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### WWDG Specific features ##### - ============================================================================== - [..] - Once enabled the WWDG generates a system reset on expiry of a programmed - time period, unless the program refreshes the counter (T[6;0] downcounter) - before reaching 0x3F value (i.e. a reset is generated when the counter - value rolls down from 0x40 to 0x3F). - - (+) An MCU reset is also generated if the counter value is refreshed - before the counter has reached the refresh window value. This - implies that the counter must be refreshed in a limited window. - (+) Once enabled the WWDG cannot be disabled except by a system reset. - (+) If required by application, an Early Wakeup Interrupt can be triggered - in order to be warned before WWDG expiration. The Early Wakeup Interrupt - (EWI) can be used if specific safety operations or data logging must - be performed before the actual reset is generated. When the downcounter - reaches 0x40, interrupt occurs. This mechanism requires WWDG interrupt - line to be enabled in NVIC. Once enabled, EWI interrupt cannot be - disabled except by a system reset. - (+) WWDGRST flag in RCC CSR register can be used to inform when a WWDG - reset occurs. - (+) The WWDG counter input clock is derived from the APB clock divided - by a programmable prescaler. - (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler) - (+) WWDG timeout (mS) = 1000 * (T[5;0] + 1) / WWDG clock (Hz) - where T[5;0] are the lowest 6 bits of Counter. - (+) WWDG Counter refresh is allowed between the following limits : - (++) min time (mS) = 1000 * (Counter - Window) / WWDG clock - (++) max time (mS) = 1000 * (Counter - 0x40) / WWDG clock - (+) Typical values: - (++) Counter min (T[5;0] = 0x00) at 54MHz (PCLK1) with zero prescaler: - max timeout before reset: approximately 75.85us - (++) Counter max (T[5;0] = 0x3F) at 54MHz (PCLK1) with prescaler - dividing by 8: - max timeout before reset: approximately 38.83ms - - ##### How to use this driver ##### - ============================================================================== - - *** Common driver usage *** - =========================== - - [..] - (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). - (+) Configure the WWDG prescaler, refresh window value, counter value and early - interrupt status using HAL_WWDG_Init() function. This will automatically - enable WWDG and start its downcounter. Time reference can be taken from - function exit. Care must be taken to provide a counter value - greater than 0x40 to prevent generation of immediate reset. - (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is - generated when the counter reaches 0x40. When HAL_WWDG_IRQHandler is - triggered by the interrupt service routine, flag will be automatically - cleared and HAL_WWDG_WakeupCallback user callback will be executed. User - can add his own code by customization of callback HAL_WWDG_WakeupCallback. - (+) Then the application program must refresh the WWDG counter at regular - intervals during normal operation to prevent an MCU reset, using - HAL_WWDG_Refresh() function. This operation must occur only when - the counter is lower than the refresh window value already programmed. - - *** Callback registration *** - ============================= - - [..] - The compilation define USE_HAL_WWDG_REGISTER_CALLBACKS when set to 1 allows - the user to configure dynamically the driver callbacks. Use Functions - HAL_WWDG_RegisterCallback() to register a user callback. - - (+) Function HAL_WWDG_RegisterCallback() allows to register following - callbacks: - (++) EwiCallback : callback for Early WakeUp Interrupt. - (++) MspInitCallback : WWDG MspInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() - takes as parameters the HAL peripheral handle and the Callback ID. - This function allows to reset following callbacks: - (++) EwiCallback : callback for Early WakeUp Interrupt. - (++) MspInitCallback : WWDG MspInit. - - [..] - When calling HAL_WWDG_Init function, callbacks are reset to the - corresponding legacy weak (surcharged) functions: - HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have - not been registered before. - - [..] - When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. - - *** WWDG HAL driver macros list *** - =================================== - [..] - Below the list of available macros in WWDG HAL driver. - (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral - (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status - (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags - (+) __HAL_WWDG_ENABLE_IT: Enable the WWDG early wakeup interrupt - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -#ifdef HAL_WWDG_MODULE_ENABLED -/** @defgroup WWDG WWDG - * @brief WWDG HAL module driver. - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup WWDG_Exported_Functions WWDG Exported Functions - * @{ - */ - -/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions. - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and start the WWDG according to the specified parameters - in the WWDG_InitTypeDef of associated handle. - (+) Initialize the WWDG MSP. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the WWDG according to the specified. - * parameters in the WWDG_InitTypeDef of associated handle. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) -{ - /* Check the WWDG handle allocation */ - if (hwwdg == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); - assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler)); - assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); - assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); - assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode)); - -#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - /* Reset Callback pointers */ - if (hwwdg->EwiCallback == NULL) - { - hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; - } - - if (hwwdg->MspInitCallback == NULL) - { - hwwdg->MspInitCallback = HAL_WWDG_MspInit; - } - - /* Init the low level hardware */ - hwwdg->MspInitCallback(hwwdg); -#else - /* Init the low level hardware */ - HAL_WWDG_MspInit(hwwdg); -#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ - - /* Set WWDG Counter */ - WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter)); - - /* Set WWDG Prescaler and Window */ - WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window)); - - /* Return function status */ - return HAL_OK; -} - - -/** - * @brief Initialize the WWDG MSP. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @note When rewriting this function in user file, mechanism may be added - * to avoid multiple initialize when HAL_WWDG_Init function is called - * again to change parameters. - * @retval None - */ -__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hwwdg); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_WWDG_MspInit could be implemented in the user file - */ -} - - -#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User WWDG Callback - * To be used instead of the weak (surcharged) predefined callback - * @param hwwdg WWDG handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID - * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID - * @param pCallback pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, - pWWDG_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - status = HAL_ERROR; - } - else - { - switch (CallbackID) - { - case HAL_WWDG_EWI_CB_ID: - hwwdg->EwiCallback = pCallback; - break; - - case HAL_WWDG_MSPINIT_CB_ID: - hwwdg->MspInitCallback = pCallback; - break; - - default: - status = HAL_ERROR; - break; - } - } - - return status; -} - - -/** - * @brief Unregister a WWDG Callback - * WWDG Callback is redirected to the weak (surcharged) predefined callback - * @param hwwdg WWDG handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_WWDG_EWI_CB_ID Early WakeUp Interrupt Callback ID - * @arg @ref HAL_WWDG_MSPINIT_CB_ID MspInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - switch (CallbackID) - { - case HAL_WWDG_EWI_CB_ID: - hwwdg->EwiCallback = HAL_WWDG_EarlyWakeupCallback; - break; - - case HAL_WWDG_MSPINIT_CB_ID: - hwwdg->MspInitCallback = HAL_WWDG_MspInit; - break; - - default: - status = HAL_ERROR; - break; - } - - return status; -} -#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Refresh the WWDG. - (+) Handle WWDG interrupt request and associated function callback. - -@endverbatim - * @{ - */ - -/** - * @brief Refresh the WWDG. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg) -{ - /* Write to WWDG CR the WWDG Counter value to refresh with */ - WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter)); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Handle WWDG interrupt request. - * @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations - * or data logging must be performed before the actual reset is generated. - * The EWI interrupt is enabled by calling HAL_WWDG_Init function with - * EWIMode set to WWDG_EWI_ENABLE. - * When the downcounter reaches the value 0x40, and EWI interrupt is - * generated and the corresponding Interrupt Service Routine (ISR) can - * be used to trigger specific actions (such as communications or data - * logging), before resetting the device. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) -{ - /* Check if Early Wakeup Interrupt is enable */ - if (__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) - { - /* Check if WWDG Early Wakeup Interrupt occurred */ - if (__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) - { - /* Clear the WWDG Early Wakeup flag */ - __HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF); - -#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) - /* Early Wakeup registered callback */ - hwwdg->EwiCallback(hwwdg); -#else - /* Early Wakeup callback */ - HAL_WWDG_EarlyWakeupCallback(hwwdg); -#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */ - } - } -} - - -/** - * @brief WWDG Early Wakeup callback. - * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains - * the configuration information for the specified WWDG module. - * @retval None - */ -__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hwwdg); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_WWDG_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_adc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_adc.c deleted file mode 100644 index 3f9d58b3..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_adc.c +++ /dev/null @@ -1,910 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_adc.c - * @author MCD Application Team - * @brief ADC LL module driver - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_adc.h" -#include "stm32f7xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT - #include "stm32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (ADC1) || defined (ADC2) || defined (ADC3) - -/** @addtogroup ADC_LL ADC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/** @addtogroup ADC_LL_Private_Macros - * @{ - */ - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* common to several ADC instances. */ -#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ - ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ - ) - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* ADC instance. */ -#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ - ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ - ) - -#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ - ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ - || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ - ) - -#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ - ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ - || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ - ) - -#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ - ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ - || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ - ) - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* ADC group regular */ -#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ - ) - -#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ - ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ - || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ - ) - -#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ - ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ - || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ - || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ - ) - -#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ - ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ - || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ - ) - -#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ - ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ - || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ - ) - -#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ - ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ - ) - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* ADC group injected */ -#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ - ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \ - || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \ - ) -#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ - ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ - || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ - || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ - ) - -#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ - ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ - || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ - ) - -#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ - ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ - || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ - || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ - || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ - ) - -#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ - ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ - || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ - ) - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* multimode. */ -#if defined(ADC3) -#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ - ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ - ) -#else -#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ - ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ - || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ - ) -#endif - -#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ - ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ - || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ - ) - -#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ - ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ - || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ - ) - -#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ - ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ - || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ - || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ - ) - -/** - * @} - */ - - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize registers of all ADC instances belonging to - * the same ADC common instance to their default reset values. - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC common registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Check the parameters */ - assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - - - /* Force reset of ADC clock (core clock) */ - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); - - /* Release reset of ADC clock (core clock) */ - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); - - return SUCCESS; -} - -/** - * @brief Initialize some features of ADC common parameters - * (all ADC instances belonging to the same ADC common instance) - * and multimode (for devices with several ADC instances available). - * @note The setting of ADC common parameters is conditioned to - * ADC instances state: - * All ADC instances belonging to the same ADC common instance - * must be disabled. - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC common registers are initialized - * - ERROR: ADC common registers are not initialized - */ -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); - - assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) - { - assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); - assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); - } - - /* Note: Hardware constraint (refer to description of functions */ - /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ - /* On this STM32 series, setting of these features is conditioned to */ - /* ADC state: */ - /* All ADC instances of the ADC common group must be disabled. */ - if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) - { - /* Configuration of ADC hierarchical scope: */ - /* - common to several ADC */ - /* (all ADC instances belonging to the same ADC common instance) */ - /* - Set ADC clock (conversion clock) */ - /* - multimode (if several ADC instances available on the */ - /* selected device) */ - /* - Set ADC multimode configuration */ - /* - Set ADC multimode DMA transfer */ - /* - Set ADC multimode: delay between 2 sampling phases */ - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) - { - MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_ADCPRE - | ADC_CCR_MULTI - | ADC_CCR_DMA - | ADC_CCR_DDS - | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock - | ADC_CommonInitStruct->Multimode - | ADC_CommonInitStruct->MultiDMATransfer - | ADC_CommonInitStruct->MultiTwoSamplingDelay - ); - } - else - { - MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_ADCPRE - | ADC_CCR_MULTI - | ADC_CCR_DMA - | ADC_CCR_DDS - | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock - | LL_ADC_MULTI_INDEPENDENT - ); - } - } - else - { - /* Initialization error: One or several ADC instances belonging to */ - /* the same ADC common instance are not disabled. */ - status = ERROR; - } - - return status; -} - -/** - * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. - * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) -{ - /* Set ADC_CommonInitStruct fields to default values */ - /* Set fields of ADC common */ - /* (all ADC instances belonging to the same ADC common instance) */ - ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - - /* Set fields of ADC multimode */ - ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; - ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; - ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; -} - -/** - * @brief De-initialize registers of the selected ADC instance - * to their default reset values. - * @note To reset all ADC instances quickly (perform a hard reset), - * use function @ref LL_ADC_CommonDeInit(). - * @param ADCx ADC instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are de-initialized - * - ERROR: ADC registers are not de-initialized - */ -ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - - /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1U) - { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - - /* Set ADC group injected trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - - /* Disable the ADC instance */ - LL_ADC_Disable(ADCx); - } - - /* Check whether ADC state is compliant with expected state */ - /* (hardware requirements of bits state to reset registers below) */ - if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) - { - /* ========== Reset ADC registers ========== */ - /* Reset register SR */ - CLEAR_BIT(ADCx->SR, - ( LL_ADC_FLAG_STRT - | LL_ADC_FLAG_JSTRT - | LL_ADC_FLAG_EOCS - | LL_ADC_FLAG_OVR - | LL_ADC_FLAG_JEOS - | LL_ADC_FLAG_AWD1 ) - ); - - /* Reset register CR1 */ - CLEAR_BIT(ADCx->CR1, - ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN - | ADC_CR1_JAWDEN - | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN - | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN - | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE - | ADC_CR1_AWDCH ) - ); - - /* Reset register CR2 */ - CLEAR_BIT(ADCx->CR2, - ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL - | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL - | ADC_CR2_ALIGN | ADC_CR2_EOCS - | ADC_CR2_DDS | ADC_CR2_DMA - | ADC_CR2_CONT | ADC_CR2_ADON ) - ); - - /* Reset register SMPR1 */ - CLEAR_BIT(ADCx->SMPR1, - ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 - | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 - | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) - ); - - /* Reset register SMPR2 */ - CLEAR_BIT(ADCx->SMPR2, - ( ADC_SMPR2_SMP9 - | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 - | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 - | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) - ); - - /* Reset register JOFR1 */ - CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); - /* Reset register JOFR2 */ - CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); - /* Reset register JOFR3 */ - CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); - /* Reset register JOFR4 */ - CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); - - /* Reset register HTR */ - SET_BIT(ADCx->HTR, ADC_HTR_HT); - /* Reset register LTR */ - CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); - - /* Reset register SQR1 */ - CLEAR_BIT(ADCx->SQR1, - ( ADC_SQR1_L - | ADC_SQR1_SQ16 - | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) - ); - - /* Reset register SQR2 */ - CLEAR_BIT(ADCx->SQR2, - ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 - | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) - ); - - /* Reset register SQR3 */ - CLEAR_BIT(ADCx->SQR3, - ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 - | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) - ); - - /* Reset register JSQR */ - CLEAR_BIT(ADCx->JSQR, - ( ADC_JSQR_JL - | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 - | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) - ); - - /* Reset register DR */ - /* bits in access mode read only, no direct reset applicable */ - - /* Reset registers JDR1, JDR2, JDR3, JDR4 */ - /* bits in access mode read only, no direct reset applicable */ - - /* Reset register CCR */ - CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); - } - - return status; -} - -/** - * @brief Initialize some features of ADC instance. - * @note These parameters have an impact on ADC scope: ADC instance. - * Affects both group regular and group injected (availability - * of ADC group injected depends on STM32 families). - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Instance . - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note After using this function, some other features must be configured - * using LL unitary functions. - * The minimum configuration remaining to be done is: - * - Set ADC group regular or group injected sequencer: - * map channel on the selected sequencer rank. - * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). - * - Set ADC channel sampling time - * Refer to function LL_ADC_SetChannelSamplingTime(); - * @param ADCx ADC instance - * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are initialized - * - ERROR: ADC registers are not initialized - */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - - assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); - assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); - assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); - - /* Note: Hardware constraint (refer to description of this function): */ - /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) - { - /* Configuration of ADC hierarchical scope: */ - /* - ADC instance */ - /* - Set ADC data resolution */ - /* - Set ADC conversion data alignment */ - MODIFY_REG(ADCx->CR1, - ADC_CR1_RES - | ADC_CR1_SCAN - , - ADC_InitStruct->Resolution - | ADC_InitStruct->SequencersScanMode - ); - - MODIFY_REG(ADCx->CR2, - ADC_CR2_ALIGN - , - ADC_InitStruct->DataAlignment - ); - - } - else - { - /* Initialization error: ADC instance is not disabled. */ - status = ERROR; - } - return status; -} - -/** - * @brief Set each @ref LL_ADC_InitTypeDef field to default value. - * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) -{ - /* Set ADC_InitStruct fields to default values */ - /* Set fields of ADC instance */ - ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; - ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; - - /* Enable scan mode to have a generic behavior with ADC of other */ - /* STM32 families, without this setting available: */ - /* ADC group regular sequencer and ADC group injected sequencer depend */ - /* only of their own configuration. */ - ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; - -} - -/** - * @brief Initialize some features of ADC group regular. - * @note These parameters have an impact on ADC scope: ADC group regular. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "REG"). - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note After using this function, other features must be configured - * using LL unitary functions. - * The minimum configuration remaining to be done is: - * - Set ADC group regular or group injected sequencer: - * map channel on the selected sequencer rank. - * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). - * - Set ADC channel sampling time - * Refer to function LL_ADC_SetChannelSamplingTime(); - * @param ADCx ADC instance - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are initialized - * - ERROR: ADC registers are not initialized - */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) - { - assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); - } - assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); - assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); - - /* ADC group regular continuous mode and discontinuous mode */ - /* can not be enabled simultenaeously */ - assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) - || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); - - /* Note: Hardware constraint (refer to description of this function): */ - /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) - { - /* Configuration of ADC hierarchical scope: */ - /* - ADC group regular */ - /* - Set ADC group regular trigger source */ - /* - Set ADC group regular sequencer length */ - /* - Set ADC group regular sequencer discontinuous mode */ - /* - Set ADC group regular continuous mode */ - /* - Set ADC group regular conversion data transfer: no transfer or */ - /* transfer by DMA, and DMA requests mode */ - /* Note: On this STM32 series, ADC trigger edge is set when starting */ - /* ADC conversion. */ - /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) - { - MODIFY_REG(ADCx->CR1, - ADC_CR1_DISCEN - | ADC_CR1_DISCNUM - , - ADC_REG_InitStruct->SequencerLength - | ADC_REG_InitStruct->SequencerDiscont - ); - } - else - { - MODIFY_REG(ADCx->CR1, - ADC_CR1_DISCEN - | ADC_CR1_DISCNUM - , - ADC_REG_InitStruct->SequencerLength - | LL_ADC_REG_SEQ_DISCONT_DISABLE - ); - } - - MODIFY_REG(ADCx->CR2, - ADC_CR2_EXTSEL - | ADC_CR2_EXTEN - | ADC_CR2_CONT - | ADC_CR2_DMA - | ADC_CR2_DDS - , - (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - ); - - /* Set ADC group regular sequencer length and scan direction */ - /* Note: Hardware constraint (refer to description of this function): */ - /* Note: If ADC instance feature scan mode is disabled */ - /* (refer to ADC instance initialization structure */ - /* parameter @ref SequencersScanMode */ - /* or function @ref LL_ADC_SetSequencersScanMode() ), */ - /* this parameter is discarded. */ - LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); - } - else - { - /* Initialization error: ADC instance is not disabled. */ - status = ERROR; - } - return status; -} - -/** - * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) -{ - /* Set ADC_REG_InitStruct fields to default values */ - /* Set fields of ADC group regular */ - /* Note: On this STM32 series, ADC trigger edge is set when starting */ - /* ADC conversion. */ - /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ - ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; - ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; - ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; - ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; - ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; -} - -/** - * @brief Initialize some features of ADC group injected. - * @note These parameters have an impact on ADC scope: ADC group injected. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "INJ"). - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note After using this function, other features must be configured - * using LL unitary functions. - * The minimum configuration remaining to be done is: - * - Set ADC group injected sequencer: - * map channel on the selected sequencer rank. - * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). - * - Set ADC channel sampling time - * Refer to function LL_ADC_SetChannelSamplingTime(); - * @param ADCx ADC instance - * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are initialized - * - ERROR: ADC registers are not initialized - */ -ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) - { - assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); - } - assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); - - /* Note: Hardware constraint (refer to description of this function): */ - /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) - { - /* Configuration of ADC hierarchical scope: */ - /* - ADC group injected */ - /* - Set ADC group injected trigger source */ - /* - Set ADC group injected sequencer length */ - /* - Set ADC group injected sequencer discontinuous mode */ - /* - Set ADC group injected conversion trigger: independent or */ - /* from ADC group regular */ - /* Note: On this STM32 series, ADC trigger edge is set when starting */ - /* ADC conversion. */ - /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) - { - MODIFY_REG(ADCx->CR1, - ADC_CR1_JDISCEN - | ADC_CR1_JAUTO - , - ADC_INJ_InitStruct->SequencerDiscont - | ADC_INJ_InitStruct->TrigAuto - ); - } - else - { - MODIFY_REG(ADCx->CR1, - ADC_CR1_JDISCEN - | ADC_CR1_JAUTO - , - LL_ADC_REG_SEQ_DISCONT_DISABLE - | ADC_INJ_InitStruct->TrigAuto - ); - } - - MODIFY_REG(ADCx->CR2, - ADC_CR2_JEXTSEL - | ADC_CR2_JEXTEN - , - (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) - ); - - /* Note: Hardware constraint (refer to description of this function): */ - /* Note: If ADC instance feature scan mode is disabled */ - /* (refer to ADC instance initialization structure */ - /* parameter @ref SequencersScanMode */ - /* or function @ref LL_ADC_SetSequencersScanMode() ), */ - /* this parameter is discarded. */ - LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); - } - else - { - /* Initialization error: ADC instance is not disabled. */ - status = ERROR; - } - return status; -} - -/** - * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. - * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) -{ - /* Set ADC_INJ_InitStruct fields to default values */ - /* Set fields of ADC group injected */ - ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; - ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; - ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; - ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ADC1 || ADC2 || ADC3 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_crc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_crc.c deleted file mode 100644 index ba8f0e57..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_crc.c +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_crc.c - * @author MCD Application Team - * @brief CRC LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_crc.h" -#include "stm32f7xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (CRC) - -/** @addtogroup CRC_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CRC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup CRC_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize CRC registers (Registers restored to their default values). - * @param CRCx CRC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: CRC registers are de-initialized - * - ERROR: CRC registers are not de-initialized - */ -ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_CRC_ALL_INSTANCE(CRCx)); - - if (CRCx == CRC) - { - /* Force CRC reset */ - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC); - - /* Release CRC reset */ - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC); - } - else - { - status = ERROR; - } - - return (status); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (CRC) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dac.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dac.c deleted file mode 100644 index 171db28c..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dac.c +++ /dev/null @@ -1,268 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_dac.c - * @author MCD Application Team - * @brief DAC LL module driver - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_dac.h" -#include "stm32f7xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(DAC) - -/** @addtogroup DAC_LL DAC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/** @addtogroup DAC_LL_Private_Macros - * @{ - */ -#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \ - (((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \ - || ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \ - ) - -#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \ - (((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \ - || ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \ - ) - -#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \ - (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - || ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - ) - -#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_MODE__, __WAVE_AUTO_GENERATION_CONFIG__) \ - ( (((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \ - && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0)) \ - ) \ - ||(((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \ - && (((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \ - || ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095)) \ - ) \ - ) - -#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \ - (((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \ - || ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \ - ) - -/** - * @} - */ - - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DAC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup DAC_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize registers of the selected DAC instance - * to their default reset values. - * @param DACx DAC instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DAC registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx) -{ - /* Check the parameters */ - assert_param(IS_DAC_ALL_INSTANCE(DACx)); - - /* Force reset of DAC clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1); - - /* Release reset of DAC clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1); - - return SUCCESS; -} - -/** - * @brief Initialize some features of DAC channel. - * @note @ref LL_DAC_Init() aims to ease basic configuration of a DAC channel. - * Leaving it ready to be enabled and output: - * a level by calling one of - * @ref LL_DAC_ConvertData12RightAligned - * @ref LL_DAC_ConvertData12LeftAligned - * @ref LL_DAC_ConvertData8RightAligned - * or one of the supported autogenerated wave. - * @note This function allows configuration of: - * - Output mode - * - Trigger - * - Wave generation - * @note The setting of these parameters by function @ref LL_DAC_Init() - * is conditioned to DAC state: - * DAC channel must be disabled. - * @param DACx DAC instance - * @param DAC_Channel This parameter can be one of the following values: - * @arg @ref LL_DAC_CHANNEL_1 - * @arg @ref LL_DAC_CHANNEL_2 - * @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DAC registers are initialized - * - ERROR: DAC registers are not initialized - */ -ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_DAC_ALL_INSTANCE(DACx)); - assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel)); - assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource)); - assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer)); - assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration)); - if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) - { - assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGeneration, - DAC_InitStruct->WaveAutoGenerationConfig)); - } - - /* Note: Hardware constraint (refer to description of this function) */ - /* DAC instance must be disabled. */ - if (LL_DAC_IsEnabled(DACx, DAC_Channel) == 0UL) - { - /* Configuration of DAC channel: */ - /* - TriggerSource */ - /* - WaveAutoGeneration */ - /* - OutputBuffer */ - /* - OutputMode */ - if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE) - { - MODIFY_REG(DACx->CR, - (DAC_CR_TSEL1 - | DAC_CR_WAVE1 - | DAC_CR_MAMP1 - | DAC_CR_BOFF1 - ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - , - (DAC_InitStruct->TriggerSource - | DAC_InitStruct->WaveAutoGeneration - | DAC_InitStruct->WaveAutoGenerationConfig - | DAC_InitStruct->OutputBuffer - ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - ); - } - else - { - MODIFY_REG(DACx->CR, - (DAC_CR_TSEL1 - | DAC_CR_WAVE1 - | DAC_CR_BOFF1 - ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - , - (DAC_InitStruct->TriggerSource - | LL_DAC_WAVE_AUTO_GENERATION_NONE - | DAC_InitStruct->OutputBuffer - ) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) - ); - } - } - else - { - /* Initialization error: DAC instance is not disabled. */ - status = ERROR; - } - return status; -} - -/** - * @brief Set each @ref LL_DAC_InitTypeDef field to default value. - * @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) -{ - /* Set DAC_InitStruct fields to default values */ - DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE; - DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE; - /* Note: Parameter discarded if wave auto generation is disabled, */ - /* set anyway to its default value. */ - DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0; - DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DAC */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c deleted file mode 100644 index 2f25caae..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c +++ /dev/null @@ -1,444 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_dma.c - * @author MCD Application Team - * @brief DMA LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_dma.h" -#include "stm32f7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (DMA1) || defined (DMA2) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup DMA_LL_Private_Macros - * @{ - */ -#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ - ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ - ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) - -#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ - ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \ - ((__VALUE__) == LL_DMA_MODE_PFCTRL)) - -#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ - ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) - -#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ - ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) - -#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ - ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ - ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) - -#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ - ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ - ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) - -#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - -#if defined(DMA_CHANNEL_SELECTION_8_15) -#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ - ((__VALUE__) == LL_DMA_CHANNEL_1) || \ - ((__VALUE__) == LL_DMA_CHANNEL_2) || \ - ((__VALUE__) == LL_DMA_CHANNEL_3) || \ - ((__VALUE__) == LL_DMA_CHANNEL_4) || \ - ((__VALUE__) == LL_DMA_CHANNEL_5) || \ - ((__VALUE__) == LL_DMA_CHANNEL_6) || \ - ((__VALUE__) == LL_DMA_CHANNEL_7) || \ - ((__VALUE__) == LL_DMA_CHANNEL_8) || \ - ((__VALUE__) == LL_DMA_CHANNEL_9) || \ - ((__VALUE__) == LL_DMA_CHANNEL_10) || \ - ((__VALUE__) == LL_DMA_CHANNEL_11) || \ - ((__VALUE__) == LL_DMA_CHANNEL_12) || \ - ((__VALUE__) == LL_DMA_CHANNEL_13) || \ - ((__VALUE__) == LL_DMA_CHANNEL_14) || \ - ((__VALUE__) == LL_DMA_CHANNEL_15)) - -#else -#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \ - ((__VALUE__) == LL_DMA_CHANNEL_1) || \ - ((__VALUE__) == LL_DMA_CHANNEL_2) || \ - ((__VALUE__) == LL_DMA_CHANNEL_3) || \ - ((__VALUE__) == LL_DMA_CHANNEL_4) || \ - ((__VALUE__) == LL_DMA_CHANNEL_5) || \ - ((__VALUE__) == LL_DMA_CHANNEL_6) || \ - ((__VALUE__) == LL_DMA_CHANNEL_7)) - -#endif /* DMA_CHANNEL_SELECTION_8_15 */ - -#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ - ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ - ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ - ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) - -#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \ - (((STREAM) == LL_DMA_STREAM_0) || \ - ((STREAM) == LL_DMA_STREAM_1) || \ - ((STREAM) == LL_DMA_STREAM_2) || \ - ((STREAM) == LL_DMA_STREAM_3) || \ - ((STREAM) == LL_DMA_STREAM_4) || \ - ((STREAM) == LL_DMA_STREAM_5) || \ - ((STREAM) == LL_DMA_STREAM_6) || \ - ((STREAM) == LL_DMA_STREAM_7) || \ - ((STREAM) == LL_DMA_STREAM_ALL))) ||\ - (((INSTANCE) == DMA2) && \ - (((STREAM) == LL_DMA_STREAM_0) || \ - ((STREAM) == LL_DMA_STREAM_1) || \ - ((STREAM) == LL_DMA_STREAM_2) || \ - ((STREAM) == LL_DMA_STREAM_3) || \ - ((STREAM) == LL_DMA_STREAM_4) || \ - ((STREAM) == LL_DMA_STREAM_5) || \ - ((STREAM) == LL_DMA_STREAM_6) || \ - ((STREAM) == LL_DMA_STREAM_7) || \ - ((STREAM) == LL_DMA_STREAM_ALL)))) - -#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \ - ((STATE) == LL_DMA_FIFOMODE_ENABLE)) - -#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \ - ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \ - ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \ - ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL)) - -#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \ - ((BURST) == LL_DMA_MBURST_INC4) || \ - ((BURST) == LL_DMA_MBURST_INC8) || \ - ((BURST) == LL_DMA_MBURST_INC16)) - -#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \ - ((BURST) == LL_DMA_PBURST_INC4) || \ - ((BURST) == LL_DMA_PBURST_INC8) || \ - ((BURST) == LL_DMA_PBURST_INC16)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_LL_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the DMA registers to their default reset values. - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @arg @ref LL_DMA_STREAM_ALL - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DMA registers are de-initialized - * - ERROR: DMA registers are not de-initialized - */ -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream) -{ - DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0; - ErrorStatus status = SUCCESS; - - /* Check the DMA Instance DMAx and Stream parameters*/ - assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); - - if (Stream == LL_DMA_STREAM_ALL) - { - if (DMAx == DMA1) - { - /* Force reset of DMA clock */ - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1); - - /* Release reset of DMA clock */ - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1); - } - else if (DMAx == DMA2) - { - /* Force reset of DMA clock */ - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2); - - /* Release reset of DMA clock */ - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2); - } - else - { - status = ERROR; - } - } - else - { - /* Disable the selected Stream */ - LL_DMA_DisableStream(DMAx,Stream); - - /* Get the DMA Stream Instance */ - tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream)); - - /* Reset DMAx_Streamy configuration register */ - LL_DMA_WriteReg(tmp, CR, 0U); - - /* Reset DMAx_Streamy remaining bytes register */ - LL_DMA_WriteReg(tmp, NDTR, 0U); - - /* Reset DMAx_Streamy peripheral address register */ - LL_DMA_WriteReg(tmp, PAR, 0U); - - /* Reset DMAx_Streamy memory address register */ - LL_DMA_WriteReg(tmp, M0AR, 0U); - - /* Reset DMAx_Streamy memory address register */ - LL_DMA_WriteReg(tmp, M1AR, 0U); - - /* Reset DMAx_Streamy FIFO control register */ - LL_DMA_WriteReg(tmp, FCR, 0x00000021U); - - /* Reset Channel register field for DMAx Stream*/ - LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0); - - if(Stream == LL_DMA_STREAM_0) - { - /* Reset the Stream0 pending flags */ - DMAx->LIFCR = 0x0000003FU; - } - else if(Stream == LL_DMA_STREAM_1) - { - /* Reset the Stream1 pending flags */ - DMAx->LIFCR = 0x00000F40U; - } - else if(Stream == LL_DMA_STREAM_2) - { - /* Reset the Stream2 pending flags */ - DMAx->LIFCR = 0x003F0000U; - } - else if(Stream == LL_DMA_STREAM_3) - { - /* Reset the Stream3 pending flags */ - DMAx->LIFCR = 0x0F400000U; - } - else if(Stream == LL_DMA_STREAM_4) - { - /* Reset the Stream4 pending flags */ - DMAx->HIFCR = 0x0000003FU; - } - else if(Stream == LL_DMA_STREAM_5) - { - /* Reset the Stream5 pending flags */ - DMAx->HIFCR = 0x00000F40U; - } - else if(Stream == LL_DMA_STREAM_6) - { - /* Reset the Stream6 pending flags */ - DMAx->HIFCR = 0x003F0000U; - } - else if(Stream == LL_DMA_STREAM_7) - { - /* Reset the Stream7 pending flags */ - DMAx->HIFCR = 0x0F400000U; - } - else - { - status = ERROR; - } - } - - return status; -} - -/** - * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. - * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros : - * @arg @ref __LL_DMA_GET_INSTANCE - * @arg @ref __LL_DMA_GET_STREAM - * @param DMAx DMAx Instance - * @param Stream This parameter can be one of the following values: - * @arg @ref LL_DMA_STREAM_0 - * @arg @ref LL_DMA_STREAM_1 - * @arg @ref LL_DMA_STREAM_2 - * @arg @ref LL_DMA_STREAM_3 - * @arg @ref LL_DMA_STREAM_4 - * @arg @ref LL_DMA_STREAM_5 - * @arg @ref LL_DMA_STREAM_6 - * @arg @ref LL_DMA_STREAM_7 - * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DMA registers are initialized - * - ERROR: Not applicable - */ -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct) -{ - /* Check the DMA Instance DMAx and Stream parameters*/ - assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream)); - - /* Check the DMA parameters from DMA_InitStruct */ - assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); - assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); - assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); - assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); - assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); - assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); - assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); - assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel)); - assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); - assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode)); - /* Check the memory burst, peripheral burst and FIFO threshold parameters only - when FIFO mode is enabled */ - if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) - { - assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold)); - assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst)); - assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst)); - } - - /*---------------------------- DMAx SxCR Configuration ------------------------ - * Configure DMAx_Streamy: data transfer direction, data transfer mode, - * peripheral and memory increment mode, - * data size alignment and priority level with parameters : - * - Direction: DMA_SxCR_DIR[1:0] bits - * - Mode: DMA_SxCR_CIRC bit - * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit - * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit - * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits - * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits - * - Priority: DMA_SxCR_PL[1:0] bits - */ - LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \ - DMA_InitStruct->Mode | \ - DMA_InitStruct->PeriphOrM2MSrcIncMode | \ - DMA_InitStruct->MemoryOrM2MDstIncMode | \ - DMA_InitStruct->PeriphOrM2MSrcDataSize | \ - DMA_InitStruct->MemoryOrM2MDstDataSize | \ - DMA_InitStruct->Priority - ); - - if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE) - { - /*---------------------------- DMAx SxFCR Configuration ------------------------ - * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters : - * - FIFOMode: DMA_SxFCR_DMDIS bit - * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits - */ - LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold); - - /*---------------------------- DMAx SxCR Configuration -------------------------- - * Configure DMAx_Streamy: memory burst transfer with parameters : - * - MemBurst: DMA_SxCR_MBURST[1:0] bits - */ - LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst); - - /*---------------------------- DMAx SxCR Configuration -------------------------- - * Configure DMAx_Streamy: peripheral burst transfer with parameters : - * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits - */ - LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst); - } - - /*-------------------------- DMAx SxM0AR Configuration -------------------------- - * Configure the memory or destination base address with parameter : - * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits - */ - LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress); - - /*-------------------------- DMAx SxPAR Configuration --------------------------- - * Configure the peripheral or source base address with parameter : - * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits - */ - LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress); - - /*--------------------------- DMAx SxNDTR Configuration ------------------------- - * Configure the peripheral base address with parameter : - * - NbData: DMA_SxNDT[15:0] bits - */ - LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData); - - /*--------------------------- DMA SxCR_CHSEL Configuration ---------------------- - * Configure the peripheral base address with parameter : - * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits - */ - LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel); - - return SUCCESS; -} - -/** - * @brief Set each @ref LL_DMA_InitTypeDef field to default value. - * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval None - */ -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) -{ - /* Set DMA_InitStruct fields to default values */ - DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; - DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; - DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; - DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; - DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; - DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; - DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; - DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct->NbData = 0x00000000U; - DMA_InitStruct->Channel = LL_DMA_CHANNEL_0; - DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; - DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE; - DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4; - DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE; - DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 || DMA2 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma2d.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma2d.c deleted file mode 100644 index 3858cf19..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma2d.c +++ /dev/null @@ -1,645 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_dma2d.c - * @author MCD Application Team - * @brief DMA2D LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_dma2d.h" -#include "stm32f7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (DMA2D) - -/** @addtogroup DMA2D_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants - * @{ - */ -#define LL_DMA2D_COLOR 0xFFU /*!< Maximum output color setting */ -#define LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL /*!< Maximum number of lines */ -#define LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos) /*!< Maximum number of pixels per lines */ -#define LL_DMA2D_OFFSET_MAX 0x3FFFU /*!< Maximum output line offset expressed in pixels */ -#define LL_DMA2D_CLUTSIZE_MAX 0xFFU /*!< Maximum CLUT size */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup DMA2D_LL_Private_Macros - * @{ - */ -#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \ - ((MODE) == LL_DMA2D_MODE_M2M_PFC) || \ - ((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \ - ((MODE) == LL_DMA2D_MODE_R2M)) - -#define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \ - ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \ - ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565) || \ - ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \ - ((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444)) - -#define IS_LL_DMA2D_GREEN(GREEN) ((GREEN) <= LL_DMA2D_COLOR) -#define IS_LL_DMA2D_RED(RED) ((RED) <= LL_DMA2D_COLOR) -#define IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR) -#define IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR) - - -#define IS_LL_DMA2D_OFFSET(OFFSET) ((OFFSET) <= LL_DMA2D_OFFSET_MAX) - -#define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES) -#define IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS) - - -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) -#define IS_LL_DMA2D_ALPHAINV(ALPHA) (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \ - ((ALPHA) == LL_DMA2D_ALPHA_INVERTED)) - -#define IS_LL_DMA2D_RBSWAP(RBSWAP) (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \ - ((RBSWAP) == LL_DMA2D_RB_MODE_SWAP)) -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - -#define IS_LL_DMA2D_LCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8) || \ - ((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4)) - -#define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \ - ((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888)) - -#define IS_LL_DMA2D_CLUTSIZE(SIZE) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX) - -#define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \ - ((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \ - ((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE)) - - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA2D_LL_Exported_Functions - * @{ - */ - -/** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions - * @{ - */ - -/** - * @brief De-initialize DMA2D registers (registers restored to their default values). - * @param DMA2Dx DMA2D Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DMA2D registers are de-initialized - * - ERROR: DMA2D registers are not de-initialized - */ -ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); - - if (DMA2Dx == DMA2D) - { - /* Force reset of DMA2D clock */ - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2D); - - /* Release reset of DMA2D clock */ - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2D); - } - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct. - * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, - * otherwise ERROR result is returned. - * @param DMA2Dx DMA2D Instance - * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure - * that contains the configuration information for the specified DMA2D peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content - * - ERROR: Issue occurred during DMA2D registers initialization - */ -ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct) -{ - ErrorStatus status = ERROR; - LL_DMA2D_ColorTypeDef dma2d_colorstruct; - uint32_t tmp; - uint32_t tmp1; - uint32_t tmp2; - uint32_t regMask; - uint32_t regValue; - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); - assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode)); - assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode)); - assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines)); - assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines)); - assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen)); - assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed)); - assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue)); - assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha)); - assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset)); -#if defined (DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode)); - assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode)); -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - /* DMA2D transfers must be disabled to configure bits in initialization registers */ - tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx); - tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx); - tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx); - if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U)) - { - /* DMA2D CR register configuration -------------------------------------------*/ - LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode); - - /* DMA2D OPFCCR register configuration ---------------------------------------*/ - regMask = DMA2D_OPFCCR_CM; - regValue = DMA2D_InitStruct->ColorMode; - - -#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - regMask |= (DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI); - regValue |= (DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode); -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - - MODIFY_REG(DMA2Dx->OPFCCR, regMask, regValue); - - /* DMA2D OOR register configuration ------------------------------------------*/ - LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset); - - /* DMA2D NLR register configuration ------------------------------------------*/ - LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines); - - /* DMA2D OMAR register configuration ------------------------------------------*/ - LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress); - - /* DMA2D OCOLR register configuration ------------------------------------------*/ - dma2d_colorstruct.ColorMode = DMA2D_InitStruct->ColorMode; - dma2d_colorstruct.OutputBlue = DMA2D_InitStruct->OutputBlue; - dma2d_colorstruct.OutputGreen = DMA2D_InitStruct->OutputGreen; - dma2d_colorstruct.OutputRed = DMA2D_InitStruct->OutputRed; - dma2d_colorstruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha; - LL_DMA2D_ConfigOutputColor(DMA2Dx, &dma2d_colorstruct); - - status = SUCCESS; - } - /* If DMA2D transfers are not disabled, return ERROR */ - - return (status); -} - -/** - * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. - * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct) -{ - /* Set DMA2D_InitStruct fields to default values */ - DMA2D_InitStruct->Mode = LL_DMA2D_MODE_M2M; - DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888; - DMA2D_InitStruct->NbrOfLines = 0x0U; - DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U; - DMA2D_InitStruct->LineOffset = 0x0U; - DMA2D_InitStruct->OutputBlue = 0x0U; - DMA2D_InitStruct->OutputGreen = 0x0U; - DMA2D_InitStruct->OutputRed = 0x0U; - DMA2D_InitStruct->OutputAlpha = 0x0U; - DMA2D_InitStruct->OutputMemoryAddress = 0x0U; -#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - DMA2D_InitStruct->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; - DMA2D_InitStruct->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ -} - -/** - * @brief Configure the foreground or background according to the specified parameters - * in the LL_DMA2D_LayerCfgTypeDef structure. - * @param DMA2Dx DMA2D Instance - * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains - * the configuration information for the specified layer. - * @param LayerIdx DMA2D Layer index. - * This parameter can be one of the following values: - * 0(background) / 1(foreground) - * @retval None - */ -void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx) -{ - /* Check the parameters */ - assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset)); - assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode)); - assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode)); - assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize)); - assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode)); - assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green)); - assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red)); - assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue)); - assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha)); -#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode)); - assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode)); -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - - if (LayerIdx == 0U) - { - /* Configure the background memory address */ - LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress); - - /* Configure the background line offset */ - LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset); - -#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - /* Configure the background Alpha value, Alpha mode, RB swap, Alpha inversion - CLUT size, CLUT Color mode and Color mode */ - MODIFY_REG(DMA2Dx->BGPFCCR, \ - (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_RBS | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_AM | \ - DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \ - ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \ - DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \ - (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ - DMA2D_LayerCfg->ColorMode)); -#else - /* Configure the background Alpha value, Alpha mode, CLUT size, CLUT Color mode and Color mode */ - MODIFY_REG(DMA2Dx->BGPFCCR, \ - (DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \ - ((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->AlphaMode | \ - (DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ - DMA2D_LayerCfg->ColorMode)); -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - /* Configure the background color */ - LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue); - - /* Configure the background CLUT memory address */ - LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress); - } - else - { - /* Configure the foreground memory address */ - LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress); - - /* Configure the foreground line offset */ - LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset); - -#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - /* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion - CLUT size, CLUT Color mode and Color mode */ - MODIFY_REG(DMA2Dx->FGPFCCR, \ - (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_AM | \ - DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \ - ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \ - DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \ - (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ - DMA2D_LayerCfg->ColorMode)); -#else - /* Configure the foreground Alpha value, Alpha mode, CLUT size, CLUT Color mode and Color mode */ - MODIFY_REG(DMA2Dx->FGPFCCR, \ - (DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \ - ((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->AlphaMode | \ - (DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \ - DMA2D_LayerCfg->ColorMode)); -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ - - /* Configure the foreground color */ - LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue); - - /* Configure the foreground CLUT memory address */ - LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress); - } -} - -/** - * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. - * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg) -{ - /* Set DMA2D_LayerCfg fields to default values */ - DMA2D_LayerCfg->MemoryAddress = 0x0U; - DMA2D_LayerCfg->ColorMode = LL_DMA2D_INPUT_MODE_ARGB8888; - DMA2D_LayerCfg->LineOffset = 0x0U; - DMA2D_LayerCfg->CLUTColorMode = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888; - DMA2D_LayerCfg->CLUTSize = 0x0U; - DMA2D_LayerCfg->AlphaMode = LL_DMA2D_ALPHA_MODE_NO_MODIF; - DMA2D_LayerCfg->Alpha = 0x0U; - DMA2D_LayerCfg->Blue = 0x0U; - DMA2D_LayerCfg->Green = 0x0U; - DMA2D_LayerCfg->Red = 0x0U; - DMA2D_LayerCfg->CLUTMemoryAddress = 0x0U; -#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT) - DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR; - DMA2D_LayerCfg->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR; -#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */ -} - -/** - * @brief Initialize DMA2D output color register according to the specified parameters - * in DMA2D_ColorStruct. - * @param DMA2Dx DMA2D Instance - * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains - * the color configuration information for the specified DMA2D peripheral. - * @retval None - */ -void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct) -{ - uint32_t outgreen; - uint32_t outred; - uint32_t outalpha; - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); - assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode)); - assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen)); - assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed)); - assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue)); - assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha)); - - /* DMA2D OCOLR register configuration ------------------------------------------*/ - if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) - { - outgreen = DMA2D_ColorStruct->OutputGreen << 8U; - outred = DMA2D_ColorStruct->OutputRed << 16U; - outalpha = DMA2D_ColorStruct->OutputAlpha << 24U; - } - else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) - { - outgreen = DMA2D_ColorStruct->OutputGreen << 8U; - outred = DMA2D_ColorStruct->OutputRed << 16U; - outalpha = 0x00000000U; - } - else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) - { - outgreen = DMA2D_ColorStruct->OutputGreen << 5U; - outred = DMA2D_ColorStruct->OutputRed << 11U; - outalpha = 0x00000000U; - } - else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) - { - outgreen = DMA2D_ColorStruct->OutputGreen << 5U; - outred = DMA2D_ColorStruct->OutputRed << 10U; - outalpha = DMA2D_ColorStruct->OutputAlpha << 15U; - } - else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ - { - outgreen = DMA2D_ColorStruct->OutputGreen << 4U; - outred = DMA2D_ColorStruct->OutputRed << 8U; - outalpha = DMA2D_ColorStruct->OutputAlpha << 12U; - } - LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha)); -} - -/** - * @brief Return DMA2D output Blue color. - * @param DMA2Dx DMA2D Instance. - * @param ColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 - * @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF - */ -uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) -{ - uint32_t color; - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); - assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); - - /* DMA2D OCOLR register reading ------------------------------------------*/ - if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU)); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU)); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU)); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU)); - } - else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU)); - } - - return color; -} - -/** - * @brief Return DMA2D output Green color. - * @param DMA2Dx DMA2D Instance. - * @param ColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 - * @retval Output Green color value between Min_Data=0 and Max_Data=0xFF - */ -uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) -{ - uint32_t color; - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); - assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); - - /* DMA2D OCOLR register reading ------------------------------------------*/ - if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U); - } - else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U); - } - - return color; -} - -/** - * @brief Return DMA2D output Red color. - * @param DMA2Dx DMA2D Instance. - * @param ColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 - * @retval Output Red color value between Min_Data=0 and Max_Data=0xFF - */ -uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) -{ - uint32_t color; - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); - assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); - - /* DMA2D OCOLR register reading ------------------------------------------*/ - if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U); - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U); - } - else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U); - } - - return color; -} - -/** - * @brief Return DMA2D output Alpha color. - * @param DMA2Dx DMA2D Instance. - * @param ColorMode This parameter can be one of the following values: - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 - * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 - * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 - * @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF - */ -uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) -{ - uint32_t color; - - /* Check the parameters */ - assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx)); - assert_param(IS_LL_DMA2D_OCMODE(ColorMode)); - - /* DMA2D OCOLR register reading ------------------------------------------*/ - if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U); - } - else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)) - { - color = 0x0U; - } - else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555) - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U); - } - else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */ - { - color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U); - } - - return color; -} - -/** - * @brief Configure DMA2D transfer size. - * @param DMA2Dx DMA2D Instance - * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF - * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF - * @retval None - */ -void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines) -{ - MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \ - ((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (DMA2D) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c deleted file mode 100644 index f615e266..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c +++ /dev/null @@ -1,212 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_exti.c - * @author MCD Application Team - * @brief EXTI LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_exti.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Private_Macros - * @{ - */ - -#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) - -#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ - || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ - || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) - - -#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the EXTI registers to their default reset values. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are de-initialized - * - ERROR: not applicable - */ -uint32_t LL_EXTI_DeInit(void) -{ - /* Interrupt mask register set to default reset values */ - LL_EXTI_WriteReg(IMR, 0x00000000U); - /* Event mask register set to default reset values */ - LL_EXTI_WriteReg(EMR, 0x00000000U); - /* Rising Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(RTSR, 0x00000000U); - /* Falling Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(FTSR, 0x00000000U); - /* Software interrupt event register set to default reset values */ - LL_EXTI_WriteReg(SWIER, 0x00000000U); - /* Pending register set to default reset values */ - LL_EXTI_WriteReg(PR, 0x01FFFFFFU); - - return SUCCESS; -} - -/** - * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. - * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are initialized - * - ERROR: not applicable - */ -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - ErrorStatus status = SUCCESS; - /* Check the parameters */ - assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); - assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); - - /* ENABLE LineCommand */ - if (EXTI_InitStruct->LineCommand != DISABLE) - { - assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); - - /* Configure EXTI Lines in range from 0 to 31 */ - if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) - { - switch (EXTI_InitStruct->Mode) - { - case LL_EXTI_MODE_IT: - /* First Disable Event on provided Lines */ - LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable IT on provided Lines */ - LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_MODE_EVENT: - /* First Disable IT on provided Lines */ - LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Event on provided Lines */ - LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_MODE_IT_EVENT: - /* Directly Enable IT & Event on provided Lines */ - LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); - break; - default: - status = ERROR; - break; - } - if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) - { - switch (EXTI_InitStruct->Trigger) - { - case LL_EXTI_TRIGGER_RISING: - /* First Disable Falling Trigger on provided Lines */ - LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Rising Trigger on provided Lines */ - LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_TRIGGER_FALLING: - /* First Disable Rising Trigger on provided Lines */ - LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Falling Trigger on provided Lines */ - LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_TRIGGER_RISING_FALLING: - LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - default: - status = ERROR; - break; - } - } - } - } - /* DISABLE LineCommand */ - else - { - /* De-configure EXTI Lines in range from 0 to 31 */ - LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); - } - return status; -} - -/** - * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. - * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval None - */ -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; - EXTI_InitStruct->LineCommand = DISABLE; - EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; - EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (EXTI) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c deleted file mode 100644 index 7d647836..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c +++ /dev/null @@ -1,1092 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_fmc.c - * @author MCD Application Team - * @brief FMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Flexible Memory Controller (FMC) peripheral memories: - * + Initialization/de-initialization functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### FMC peripheral features ##### - ============================================================================== - [..] The Flexible memory controller (FMC) includes following memory controllers: - (+) The NOR/PSRAM memory controller - (+) The NAND memory controller - (+) The Synchronous DRAM (SDRAM) controller - - [..] The FMC functional block makes the interface with synchronous and asynchronous static - memories and SDRAM memories. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol - (+) to meet the access time requirements of the external memory devices - - [..] All external memories share the addresses, data and control signals with the controller. - Each external device is accessed by means of a unique Chip Select. The FMC performs - only one access at a time to an external device. - The main features of the FMC controller are the following: - (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM) - (++) Read-only memory (ROM) - (++) NOR Flash memory/OneNAND Flash memory - (++) PSRAM (4 memory banks) - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of - data - (+) Interface with synchronous DRAM (SDRAM) memories - (+) Independent Chip Select control for each memory bank - (+) Independent configuration for each memory bank - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ -#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\ - || defined(HAL_SRAM_MODULE_ENABLED) - -/** @defgroup FMC_LL FMC Low Layer - * @brief FMC driver modules - * @{ - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants - * @{ - */ - -/* ----------------------- FMC registers bit mask --------------------------- */ - -/* --- BCR Register ---*/ -/* BCR register clear mask */ - -/* --- BTR Register ---*/ -/* BTR register clear mask */ -#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\ - FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\ - FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\ - FMC_BTR1_ACCMOD)) - -/* --- BWTR Register ---*/ -/* BWTR register clear mask */ -#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\ - FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\ - FMC_BWTR1_ACCMOD)) - -/* --- PCR Register ---*/ -/* PCR register clear mask */ -#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ - FMC_PCR_PTYP | FMC_PCR_PWID | \ - FMC_PCR_ECCEN | FMC_PCR_TCLR | \ - FMC_PCR_TAR | FMC_PCR_ECCPS)) -/* --- PMEM Register ---*/ -/* PMEM register clear mask */ -#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET3 | FMC_PMEM_MEMWAIT3 |\ - FMC_PMEM_MEMHOLD3 | FMC_PMEM_MEMHIZ3)) - -/* --- PATT Register ---*/ -/* PATT register clear mask */ -#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET3 | FMC_PATT_ATTWAIT3 |\ - FMC_PATT_ATTHOLD3 | FMC_PATT_ATTHIZ3)) - - -/* --- SDCR Register ---*/ -/* SDCR register clear mask */ -#define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \ - FMC_SDCR1_MWID | FMC_SDCR1_NB | \ - FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \ - FMC_SDCR1_RPIPE)) - -/* --- SDTR Register ---*/ -/* SDTR register clear mask */ -#define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \ - FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \ - FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions - * @{ - */ - - -/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions - * @brief NORSRAM Controller functions - * - @verbatim - ============================================================================== - ##### How to use NORSRAM device driver ##### - ============================================================================== - - [..] - This driver contains a set of APIs to interface with the FMC NORSRAM banks in order - to run the NORSRAM external devices. - - (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() - (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() - (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() - (+) FMC NORSRAM bank extended timing configuration using the function - FMC_NORSRAM_Extended_Timing_Init() - (+) FMC NORSRAM bank enable/disable write operation using the functions - FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() - -@endverbatim - * @{ - */ - -/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NORSRAM interface - (+) De-initialize the FMC NORSRAM interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the FMC_NORSRAM device according to the specified - * control parameters in the FMC_NORSRAM_InitTypeDef - * @param Device Pointer to NORSRAM device instance - * @param Init Pointer to NORSRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) -{ - uint32_t flashaccess; - uint32_t btcr_reg; - uint32_t mask; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); - assert_param(IS_FMC_MUX(Init->DataAddressMux)); - assert_param(IS_FMC_MEMORY(Init->MemoryType)); - assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); - assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); - assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); - assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); - assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); - assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); - assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); - assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); - assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); - assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); - assert_param(IS_FMC_PAGESIZE(Init->PageSize)); - - /* Disable NORSRAM Device */ - __FMC_NORSRAM_DISABLE(Device, Init->NSBank); - - /* Set NORSRAM device control parameters */ - if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) - { - flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; - } - else - { - flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; - } - - btcr_reg = (flashaccess | \ - Init->DataAddressMux | \ - Init->MemoryType | \ - Init->MemoryDataWidth | \ - Init->BurstAccessMode | \ - Init->WaitSignalPolarity | \ - Init->WaitSignalActive | \ - Init->WriteOperation | \ - Init->WaitSignal | \ - Init->ExtendedMode | \ - Init->AsynchronousWait | \ - Init->WriteBurst); - - btcr_reg |= Init->ContinuousClock; - btcr_reg |= Init->WriteFifo; - btcr_reg |= Init->PageSize; - - mask = (FMC_BCR1_MBKEN | - FMC_BCR1_MUXEN | - FMC_BCR1_MTYP | - FMC_BCR1_MWID | - FMC_BCR1_FACCEN | - FMC_BCR1_BURSTEN | - FMC_BCR1_WAITPOL | - FMC_BCR1_WAITCFG | - FMC_BCR1_WREN | - FMC_BCR1_WAITEN | - FMC_BCR1_EXTMOD | - FMC_BCR1_ASYNCWAIT | - FMC_BCR1_CBURSTRW); - - mask |= FMC_BCR1_CCLKEN; - mask |= FMC_BCR1_WFDIS; - mask |= FMC_BCR1_CPSIZE; - - MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); - - /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) - { - MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); - } - - if (Init->NSBank != FMC_NORSRAM_BANK1) - { - /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ - SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); - } - - return HAL_OK; -} - -/** - * @brief DeInitialize the FMC_NORSRAM peripheral - * @param Device Pointer to NORSRAM device instance - * @param ExDevice Pointer to NORSRAM extended mode device instance - * @param Bank NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Disable the FMC_NORSRAM device */ - __FMC_NORSRAM_DISABLE(Device, Bank); - - /* De-initialize the FMC_NORSRAM device */ - /* FMC_NORSRAM_BANK1 */ - if (Bank == FMC_NORSRAM_BANK1) - { - Device->BTCR[Bank] = 0x000030DBU; - } - /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ - else - { - Device->BTCR[Bank] = 0x000030D2U; - } - - Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; - ExDevice->BWTR[Bank] = 0x0FFFFFFFU; - - return HAL_OK; -} - -/** - * @brief Initialize the FMC_NORSRAM Timing according to the specified - * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device Pointer to NORSRAM device instance - * @param Timing Pointer to NORSRAM Timing structure - * @param Bank NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr; - - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); - assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); - assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Set FMC_NORSRAM device timing parameters */ - MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) | - ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) | - (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) | - (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) | - (Timing->AccessMode))); - - /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) - { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); - tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); - MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); - } - - return HAL_OK; -} - -/** - * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified - * parameters in the FMC_NORSRAM_TimingTypeDef - * @param Device Pointer to NORSRAM device instance - * @param Timing Pointer to NORSRAM Timing structure - * @param Bank NORSRAM bank number - * @param ExtendedMode FMC Extended Mode - * This parameter can be one of the following values: - * @arg FMC_EXTENDED_MODE_DISABLE - * @arg FMC_EXTENDED_MODE_ENABLE - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, - uint32_t ExtendedMode) -{ - /* Check the parameters */ - assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); - - /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) - { - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); - assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); - assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); - assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); - assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); - assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | - ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) | - ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) | - Timing->AccessMode | - ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos))); - } - else - { - Device->BWTR[Bank] = 0x0FFFFFFFU; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NORSRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NORSRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FMC_NORSRAM write operation. - * @param Device Pointer to NORSRAM device instance - * @param Bank NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Enable write operation */ - SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NORSRAM write operation. - * @param Device Pointer to NORSRAM device instance - * @param Bank NORSRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_DEVICE(Device)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Disable write operation */ - CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); - - return HAL_OK; -} - -/** - * @} - */ - -/** - * @} - */ - - -/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions - * @brief NAND Controller functions - * - @verbatim - ============================================================================== - ##### How to use NAND device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FMC NAND banks in order - to run the NAND external devices. - - (+) FMC NAND bank reset using the function FMC_NAND_DeInit() - (+) FMC NAND bank control configuration using the function FMC_NAND_Init() - (+) FMC NAND bank common space timing configuration using the function - FMC_NAND_CommonSpace_Timing_Init() - (+) FMC NAND bank attribute space timing configuration using the function - FMC_NAND_AttributeSpace_Timing_Init() - (+) FMC NAND bank enable/disable ECC correction feature using the functions - FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() - (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() - -@endverbatim - * @{ - */ - -/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NAND interface - (+) De-initialize the FMC NAND interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FMC_NAND device according to the specified - * control parameters in the FMC_NAND_HandleTypeDef - * @param Device Pointer to NAND device instance - * @param Init Pointer to NAND Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Init->NandBank)); - assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); - assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); - assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); - assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | - FMC_PCR_MEMORY_TYPE_NAND | - Init->MemoryDataWidth | - Init->EccComputation | - Init->ECCPageSize | - ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | - ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Common space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device Pointer to NAND device instance - * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT3_Pos) | - ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD3_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ3_Pos))); - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Attribute space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device Pointer to NAND device instance - * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - /* NAND bank 3 registers configuration */ - MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT3_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD3_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ3_Pos))); - - return HAL_OK; -} - -/** - * @brief DeInitializes the FMC_NAND device - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable the NAND Bank */ - __FMC_NAND_DISABLE(Device, Bank); - - /* De-initialize the NAND Bank */ - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - /* Set the FMC_NAND_BANK3 registers to their reset values */ - WRITE_REG(Device->PCR, 0x00000018U); - WRITE_REG(Device->SR, 0x00000040U); - WRITE_REG(Device->PMEM, 0xFCFCFCFCU); - WRITE_REG(Device->PATT, 0xFCFCFCFCU); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NAND interface. - -@endverbatim - * @{ - */ - - -/** - * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Enable ECC feature */ - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - SET_BIT(Device->PCR, FMC_PCR_ECCEN); - - return HAL_OK; -} - - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable ECC feature */ - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param ECCval Pointer to ECC value - * @param Bank NAND bank number - * @param Timeout Timeout wait value - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, - uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until FIFO is empty */ - while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - return HAL_TIMEOUT; - } - } - } - - /* Prevent unused argument(s) compilation warning if no assert_param check */ - UNUSED(Bank); - - /* Get the ECCR register value */ - *ECCval = (uint32_t)Device->ECCR; - - return HAL_OK; -} - -/** - * @} - */ - - - -/** @defgroup FMC_LL_SDRAM - * @brief SDRAM Controller functions - * - @verbatim - ============================================================================== - ##### How to use SDRAM device driver ##### - ============================================================================== - [..] - This driver contains a set of APIs to interface with the FMC SDRAM banks in order - to run the SDRAM external devices. - - (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() - (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() - (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() - (+) FMC SDRAM bank enable/disable write operation using the functions - FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() - (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() - -@endverbatim - * @{ - */ - -/** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC SDRAM interface - (+) De-initialize the FMC SDRAM interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FMC_SDRAM device according to the specified - * control parameters in the FMC_SDRAM_InitTypeDef - * @param Device Pointer to SDRAM device instance - * @param Init Pointer to SDRAM Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); - assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); - assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); - assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); - assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); - assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); - assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); - assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); - assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); - - /* Set SDRAM bank configuration parameters */ - if (Init->SDBank == FMC_SDRAM_BANK1) - { - MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], - SDCR_CLEAR_MASK, - (Init->ColumnBitsNumber | - Init->RowBitsNumber | - Init->MemoryDataWidth | - Init->InternalBankNumber | - Init->CASLatency | - Init->WriteProtection | - Init->SDClockPeriod | - Init->ReadBurst | - Init->ReadPipeDelay)); - } - else /* FMC_Bank2_SDRAM */ - { - MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], - FMC_SDCR1_SDCLK | - FMC_SDCR1_RBURST | - FMC_SDCR1_RPIPE, - (Init->SDClockPeriod | - Init->ReadBurst | - Init->ReadPipeDelay)); - - MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], - SDCR_CLEAR_MASK, - (Init->ColumnBitsNumber | - Init->RowBitsNumber | - Init->MemoryDataWidth | - Init->InternalBankNumber | - Init->CASLatency | - Init->WriteProtection)); - } - - return HAL_OK; -} - - -/** - * @brief Initializes the FMC_SDRAM device timing according to the specified - * parameters in the FMC_SDRAM_TimingTypeDef - * @param Device Pointer to SDRAM device instance - * @param Timing Pointer to SDRAM Timing structure - * @param Bank SDRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); - assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); - assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); - assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); - assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); - assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); - assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Set SDRAM device timing parameters */ - if (Bank == FMC_SDRAM_BANK1) - { - MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], - SDTR_CLEAR_MASK, - (((Timing->LoadToActiveDelay) - 1U) | - (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | - (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | - (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | - (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | - (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | - (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); - } - else /* FMC_Bank2_SDRAM */ - { - MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], - FMC_SDTR1_TRC | - FMC_SDTR1_TRP, - (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | - (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); - - MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], - SDTR_CLEAR_MASK, - (((Timing->LoadToActiveDelay) - 1U) | - (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | - (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | - (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | - (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); - } - - return HAL_OK; -} - -/** - * @brief DeInitializes the FMC_SDRAM peripheral - * @param Device Pointer to SDRAM device instance - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* De-initialize the SDRAM device */ - Device->SDCR[Bank] = 0x000002D0U; - Device->SDTR[Bank] = 0x0FFFFFFFU; - Device->SDCMR = 0x00000000U; - Device->SDRTR = 0x00000000U; - Device->SDSR = 0x00000000U; - - return HAL_OK; -} - -/** - * @} - */ - -/** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_SDRAM Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC SDRAM interface. - -@endverbatim - * @{ - */ - -/** - * @brief Enables dynamically FMC_SDRAM write protection. - * @param Device Pointer to SDRAM device instance - * @param Bank SDRAM bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Enable write protection */ - SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_SDRAM write protection. - * @param hsdram FMC_SDRAM handle - * @retval HAL status - */ -HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Disable write protection */ - CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); - - return HAL_OK; -} - -/** - * @brief Send Command to the FMC SDRAM bank - * @param Device Pointer to SDRAM device instance - * @param Command Pointer to SDRAM command structure - * @param Timing Pointer to SDRAM Timing structure - * @param Timeout Timeout wait value - * @retval HAL state - */ -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, - FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); - assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); - assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); - assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); - - /* Set command register */ - MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD), - ((Command->CommandMode) | (Command->CommandTarget) | - (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | - ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); - /* Prevent unused argument(s) compilation warning */ - UNUSED(Timeout); - return HAL_OK; -} - -/** - * @brief Program the SDRAM Memory Refresh rate. - * @param Device Pointer to SDRAM device instance - * @param RefreshRate The SDRAM refresh rate value. - * @retval HAL state - */ -HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); - - /* Set the refresh rate in command register */ - MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); - - return HAL_OK; -} - -/** - * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. - * @param Device Pointer to SDRAM device instance - * @param AutoRefreshNumber Specifies the auto Refresh number. - * @retval None - */ -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, - uint32_t AutoRefreshNumber) -{ - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); - - /* Set the Auto-refresh number in command register */ - MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); - - return HAL_OK; -} - -/** - * @brief Returns the indicated FMC SDRAM bank mode status. - * @param Device Pointer to SDRAM device instance - * @param Bank Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. - * @retval The FMC SDRAM bank mode status, could be on of the following values: - * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or - * FMC_SDRAM_POWER_DOWN_MODE. - */ -uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_FMC_SDRAM_DEVICE(Device)); - assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Get the corresponding bank mode */ - if (Bank == FMC_SDRAM_BANK1) - { - tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); - } - else - { - tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); - } - - /* Return the mode status */ - return tmpreg; -} - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_NOR_MODULE_ENABLED */ -/** - * @} - */ -/** - * @} - */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c deleted file mode 100644 index 2730301c..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c +++ /dev/null @@ -1,300 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_gpio.c - * @author MCD Application Team - * @brief GPIO LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_gpio.h" -#include "stm32f7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) - -/** @addtogroup GPIO_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Private_Macros - * @{ - */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) - -#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ - ((__VALUE__) == LL_GPIO_MODE_ANALOG)) - -#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ - ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) - -#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) - -#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ - ((__VALUE__) == LL_GPIO_PULL_UP) ||\ - ((__VALUE__) == LL_GPIO_PULL_DOWN)) - -#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ - ((__VALUE__) == LL_GPIO_AF_1 ) ||\ - ((__VALUE__) == LL_GPIO_AF_2 ) ||\ - ((__VALUE__) == LL_GPIO_AF_3 ) ||\ - ((__VALUE__) == LL_GPIO_AF_4 ) ||\ - ((__VALUE__) == LL_GPIO_AF_5 ) ||\ - ((__VALUE__) == LL_GPIO_AF_6 ) ||\ - ((__VALUE__) == LL_GPIO_AF_7 ) ||\ - ((__VALUE__) == LL_GPIO_AF_8 ) ||\ - ((__VALUE__) == LL_GPIO_AF_9 ) ||\ - ((__VALUE__) == LL_GPIO_AF_10 ) ||\ - ((__VALUE__) == LL_GPIO_AF_11 ) ||\ - ((__VALUE__) == LL_GPIO_AF_12 ) ||\ - ((__VALUE__) == LL_GPIO_AF_13 ) ||\ - ((__VALUE__) == LL_GPIO_AF_14 ) ||\ - ((__VALUE__) == LL_GPIO_AF_15 )) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize GPIO registers (Registers restored to their default values). - * @param GPIOx GPIO Port - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are de-initialized - * - ERROR: Wrong GPIO Port - */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Force and Release reset on clock of GPIOx Port */ - if (GPIOx == GPIOA) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA); - } - else if (GPIOx == GPIOB) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB); - } - else if (GPIOx == GPIOC) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC); - } -#if defined(GPIOD) - else if (GPIOx == GPIOD) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD); - } -#endif /* GPIOD */ -#if defined(GPIOE) - else if (GPIOx == GPIOE) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE); - } -#endif /* GPIOE */ -#if defined(GPIOF) - else if (GPIOx == GPIOF) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF); - } -#endif /* GPIOF */ -#if defined(GPIOG) - else if (GPIOx == GPIOG) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG); - } -#endif /* GPIOG */ -#if defined(GPIOH) - else if (GPIOx == GPIOH) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH); - } -#endif /* GPIOH */ -#if defined(GPIOI) - else if (GPIOx == GPIOI) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI); - } -#endif /* GPIOI */ -#if defined(GPIOJ) - else if (GPIOx == GPIOJ) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ); - } -#endif /* GPIOJ */ -#if defined(GPIOK) - else if (GPIOx == GPIOK) - { - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK); - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK); - } -#endif /* GPIOK */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. - * @param GPIOx GPIO Port - * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure - * that contains the configuration information for the specified GPIO peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content - * - ERROR: Not applicable - */ -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t pinpos = 0x00000000U; - uint32_t currentpin = 0x00000000U; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); - assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); - assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); - - /* ------------------------- Configure the port pins ---------------- */ - /* Initialize pinpos on first pin set */ - pinpos = POSITION_VAL(GPIO_InitStruct->Pin); - - /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U) - { - /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos); - - if (currentpin) - { - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Speed mode parameters */ - assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); - - /* Speed mode configuration */ - LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); - - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - } - - /* Pull-up Pull down resistor configuration*/ - LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); - - if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) - { - /* Check Alternate parameter */ - assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); - - /* Speed mode configuration */ - if (POSITION_VAL(currentpin) < 0x00000008U) - { - LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - else - { - LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - } - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - } - pinpos++; - } - return (SUCCESS); -} - -/** - * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; - GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; - GPIO_InitStruct->Alternate = LL_GPIO_AF_0; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_i2c.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_i2c.c deleted file mode 100644 index 1c2363c6..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_i2c.c +++ /dev/null @@ -1,242 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_i2c.c - * @author MCD Application Team - * @brief I2C LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_i2c.h" -#include "stm32f7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) - -/** @defgroup I2C_LL I2C - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup I2C_LL_Private_Macros - * @{ - */ - -#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \ - ((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \ - ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \ - ((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP)) - -#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \ - ((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE)) - -#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU) - -#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) - -#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ - ((__VALUE__) == LL_I2C_NACK)) - -#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \ - ((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT)) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_LL_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the I2C registers to their default reset values. - * @param I2Cx I2C Instance. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: I2C registers are de-initialized - * - ERROR: I2C registers are not de-initialized - */ -ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx) -{ - ErrorStatus status = SUCCESS; - - /* Check the I2C Instance I2Cx */ - assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); - - if (I2Cx == I2C1) - { - /* Force reset of I2C clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); - - /* Release reset of I2C clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); - } - else if (I2Cx == I2C2) - { - /* Force reset of I2C clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2); - - /* Release reset of I2C clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2); - - } - else if (I2Cx == I2C3) - { - /* Force reset of I2C clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3); - - /* Release reset of I2C clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3); - } -#if defined(I2C4) - else if (I2Cx == I2C4) - { - /* Force reset of I2C clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C4); - - /* Release reset of I2C clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C4); - } -#endif /* I2C4 */ - else - { - status = ERROR; - } - - return status; -} - -/** - * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. - * @param I2Cx I2C Instance. - * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: I2C registers are initialized - * - ERROR: Not applicable - */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct) -{ - /* Check the I2C Instance I2Cx */ - assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); - - /* Check the I2C parameters from I2C_InitStruct */ - assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode)); - assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter)); - assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter)); - assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); - assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); - assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize)); - - /* Disable the selected I2Cx Peripheral */ - LL_I2C_Disable(I2Cx); - - /*---------------------------- I2Cx CR1 Configuration ------------------------ - * Configure the analog and digital noise filters with parameters : - * - AnalogFilter: I2C_CR1_ANFOFF bit - * - DigitalFilter: I2C_CR1_DNF[3:0] bits - */ - LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter); - - /*---------------------------- I2Cx TIMINGR Configuration -------------------- - * Configure the SDA setup, hold time and the SCL high, low period with parameter : - * - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0], - * I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits - */ - LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing); - - /* Enable the selected I2Cx Peripheral */ - LL_I2C_Enable(I2Cx); - - /*---------------------------- I2Cx OAR1 Configuration ----------------------- - * Disable, Configure and Enable I2Cx device own address 1 with parameters : - * - OwnAddress1: I2C_OAR1_OA1[9:0] bits - * - OwnAddrSize: I2C_OAR1_OA1MODE bit - */ - LL_I2C_DisableOwnAddress1(I2Cx); - LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize); - - /* OwnAdress1 == 0 is reserved for General Call address */ - if (I2C_InitStruct->OwnAddress1 != 0U) - { - LL_I2C_EnableOwnAddress1(I2Cx); - } - - /*---------------------------- I2Cx MODE Configuration ----------------------- - * Configure I2Cx peripheral mode with parameter : - * - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits - */ - LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode); - - /*---------------------------- I2Cx CR2 Configuration ------------------------ - * Configure the ACKnowledge or Non ACKnowledge condition - * after the address receive match code or next received byte with parameter : - * - TypeAcknowledge: I2C_CR2_NACK bit - */ - LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); - - return SUCCESS; -} - -/** - * @brief Set each @ref LL_I2C_InitTypeDef field to default value. - * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. - * @retval None - */ -void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) -{ - /* Set I2C_InitStruct fields to default values */ - I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C; - I2C_InitStruct->Timing = 0U; - I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE; - I2C_InitStruct->DigitalFilter = 0U; - I2C_InitStruct->OwnAddress1 = 0U; - I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; - I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* I2C1 || I2C2 || I2C3 || I2C4 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_lptim.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_lptim.c deleted file mode 100644 index 812bba98..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_lptim.c +++ /dev/null @@ -1,297 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_lptim.c - * @author MCD Application Team - * @brief LPTIM LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_lptim.h" -#include "stm32f7xx_ll_bus.h" -#include "stm32f7xx_ll_rcc.h" - - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (LPTIM1) - -/** @addtogroup LPTIM_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup LPTIM_LL_Private_Macros - * @{ - */ -#define IS_LL_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \ - || ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL)) - -#define IS_LL_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \ - || ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128)) - -#define IS_LL_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE)) - -#define IS_LL_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \ - || ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE)) -/** - * @} - */ - - -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup LPTIM_Private_Functions LPTIM Private Functions - * @{ - */ -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup LPTIM_LL_Exported_Functions - * @{ - */ - -/** @addtogroup LPTIM_LL_EF_Init - * @{ - */ - -/** - * @brief Set LPTIMx registers to their reset values. - * @param LPTIMx LP Timer instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: LPTIMx registers are de-initialized - * - ERROR: invalid LPTIMx instance - */ -ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx) -{ - ErrorStatus result = SUCCESS; - - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - - if (LPTIMx == LPTIM1) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1); - } - else - { - result = ERROR; - } - - return result; -} - -/** - * @brief Set each fields of the LPTIM_InitStruct structure to its default - * value. - * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure - * @retval None - */ -void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) -{ - /* Set the default configuration */ - LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL; - LPTIM_InitStruct->Prescaler = LL_LPTIM_PRESCALER_DIV1; - LPTIM_InitStruct->Waveform = LL_LPTIM_OUTPUT_WAVEFORM_PWM; - LPTIM_InitStruct->Polarity = LL_LPTIM_OUTPUT_POLARITY_REGULAR; -} - -/** - * @brief Configure the LPTIMx peripheral according to the specified parameters. - * @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled. - * @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable(). - * @param LPTIMx LP Timer Instance - * @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: LPTIMx instance has been initialized - * - ERROR: LPTIMx instance hasn't been initialized - */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) -{ - ErrorStatus result = SUCCESS; - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - assert_param(IS_LL_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource)); - assert_param(IS_LL_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); - assert_param(IS_LL_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform)); - assert_param(IS_LL_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity)); - - /* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled - (ENABLE bit is reset to 0). - */ - if (LL_LPTIM_IsEnabled(LPTIMx) == 1UL) - { - result = ERROR; - } - else - { - /* Set CKSEL bitfield according to ClockSource value */ - /* Set PRESC bitfield according to Prescaler value */ - /* Set WAVE bitfield according to Waveform value */ - /* Set WAVEPOL bitfield according to Polarity value */ - MODIFY_REG(LPTIMx->CFGR, - (LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL), - LPTIM_InitStruct->ClockSource | \ - LPTIM_InitStruct->Prescaler | \ - LPTIM_InitStruct->Waveform | \ - LPTIM_InitStruct->Polarity); - } - - return result; -} - -/** - * @brief Disable the LPTIM instance - * @rmtoll CR ENABLE LL_LPTIM_Disable - * @param LPTIMx Low-Power Timer instance - * @note The following sequence is required to solve LPTIM disable HW limitation. - * Please check Errata Sheet ES0335 for more details under "MCU may remain - * stuck in LPTIM interrupt when entering Stop mode" section. - * @retval None - */ -void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) -{ - LL_RCC_ClocksTypeDef rcc_clock; - uint32_t tmpclksource = 0; - uint32_t tmpIER; - uint32_t tmpCFGR; - uint32_t tmpCMP; - uint32_t tmpARR; - uint32_t primask_bit; - - /* Check the parameters */ - assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - - /* Enter critical section */ - primask_bit = __get_PRIMASK(); - __set_PRIMASK(1) ; - - /********** Save LPTIM Config *********/ - /* Save LPTIM source clock */ - switch ((uint32_t)LPTIMx) - { - case LPTIM1_BASE: - tmpclksource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); - break; - default: - break; - } - - /* Save LPTIM configuration registers */ - tmpIER = LPTIMx->IER; - tmpCFGR = LPTIMx->CFGR; - tmpCMP = LPTIMx->CMP; - tmpARR = LPTIMx->ARR; - - /************* Reset LPTIM ************/ - (void)LL_LPTIM_DeInit(LPTIMx); - - /********* Restore LPTIM Config *******/ - LL_RCC_GetSystemClocksFreq(&rcc_clock); - - if ((tmpCMP != 0UL) || (tmpARR != 0UL)) - { - /* Force LPTIM source kernel clock from APB */ - switch ((uint32_t)LPTIMx) - { - case LPTIM1_BASE: - LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_PCLK1); - break; - default: - break; - } - - if (tmpCMP != 0UL) - { - /* Restore CMP and ARR registers (LPTIM should be enabled first) */ - LPTIMx->CR |= LPTIM_CR_ENABLE; - LPTIMx->CMP = tmpCMP; - - /* Polling on CMP write ok status after above restore operation */ - do - { - rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_CMPOK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); - - LL_LPTIM_ClearFlag_CMPOK(LPTIMx); - } - - if (tmpARR != 0UL) - { - LPTIMx->CR |= LPTIM_CR_ENABLE; - LPTIMx->ARR = tmpARR; - - LL_RCC_GetSystemClocksFreq(&rcc_clock); - /* Polling on ARR write ok status after above restore operation */ - do - { - rcc_clock.SYSCLK_Frequency--; /* Used for timeout */ - } while (((LL_LPTIM_IsActiveFlag_ARROK(LPTIMx) != 1UL)) && ((rcc_clock.SYSCLK_Frequency) > 0UL)); - - LL_LPTIM_ClearFlag_ARROK(LPTIMx); - } - - - /* Restore LPTIM source kernel clock */ - LL_RCC_SetLPTIMClockSource(tmpclksource); - } - - /* Restore configuration registers (LPTIM should be disabled first) */ - LPTIMx->CR &= ~(LPTIM_CR_ENABLE); - LPTIMx->IER = tmpIER; - LPTIMx->CFGR = tmpCFGR; - - /* Exit critical section: restore previous priority mask */ - __set_PRIMASK(primask_bit); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* LPTIM1 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_pwr.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_pwr.c deleted file mode 100644 index c36a096c..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_pwr.c +++ /dev/null @@ -1,85 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_pwr.c - * @author MCD Application Team - * @brief PWR LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_pwr.h" -#include "stm32f7xx_ll_bus.h" - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(PWR) - -/** @defgroup PWR_LL PWR - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PWR_LL_Exported_Functions - * @{ - */ - -/** @addtogroup PWR_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the PWR registers to their default reset values. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: PWR registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_PWR_DeInit(void) -{ - /* Force reset of PWR clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR); - - /* Release reset of PWR clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR); - - WRITE_REG(PWR->CR2, (PWR_CR2_CWUPF1 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF6)); - - return SUCCESS; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined(PWR) */ -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c deleted file mode 100644 index d96774d1..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c +++ /dev/null @@ -1,1585 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_rcc.c - * @author MCD Application Team - * @brief RCC LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file in - * the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_rcc.h" -#ifdef USE_FULL_ASSERT - #include "stm32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @addtogroup RCC_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_LL_Private_Macros - * @{ - */ -#define IS_LL_RCC_USART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USART1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART3_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_USART6_CLKSOURCE)) - -#define IS_LL_RCC_UART_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_UART4_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_UART5_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_UART7_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_UART8_CLKSOURCE)) - -#if defined(I2C4) -#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C4_CLKSOURCE)) -#else -#define IS_LL_RCC_I2C_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2C1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C2_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_I2C3_CLKSOURCE)) -#endif /* I2C4 */ - -#define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)) - -#define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE)) - -#if defined(SDMMC2) -#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_SDMMC2_CLKSOURCE)) -#else -#define IS_LL_RCC_SDMMC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDMMC1_CLKSOURCE)) -#endif /* SDMMC2 */ - -#define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE)) - -#define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE)) - -#if defined(DFSDM1_Channel0) -#define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE)) - -#define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)) -#endif /* DFSDM1_Channel0 */ - -#define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE)) - -#if defined(CEC) -#define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE)) -#endif /* CEC */ - -#if defined(DSI) -#define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE)) -#endif /* DSI */ - -#if defined(LTDC) -#define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE)) -#endif /* LTDC */ - -#if defined(SPDIFRX) -#define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE)) -#endif /* SPDIFRX */ - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCC_LL_Private_Functions RCC Private functions - * @{ - */ -uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency); -uint32_t RCC_PLL_GetFreqDomain_SYS(void); -uint32_t RCC_PLL_GetFreqDomain_SAI(void); -uint32_t RCC_PLL_GetFreqDomain_48M(void); -#if defined(DSI) -uint32_t RCC_PLL_GetFreqDomain_DSI(void); -#endif /* DSI */ -uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void); -uint32_t RCC_PLLSAI_GetFreqDomain_48M(void); -#if defined(LTDC) -uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void); -#endif /* LTDC */ -uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void); -uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void); -#if defined(SPDIFRX) -uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void); -#endif /* SPDIFRX */ -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_LL_EF_Init - * @{ - */ - -/** - * @brief Reset the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE, PLL, PLLI2S, PLLSAI OFF - * - AHB, APB1 and APB2 prescaler set to 1. - * - CSS, MCO OFF - * - All interrupts disabled - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RCC registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_RCC_DeInit(void) -{ - __IO uint32_t vl_mask; - - /* Set HSION bit */ - LL_RCC_HSI_Enable(); - - /* Wait for HSI READY bit */ - while(LL_RCC_HSI_IsReady() != 1U) - {} - - /* Reset CFGR register */ - LL_RCC_WriteReg(CFGR, 0x00000000U); - - /* Read CR register */ - vl_mask = LL_RCC_ReadReg(CR); - - /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */ - CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON)); - - /* Write new value in CR register */ - LL_RCC_WriteReg(CR, vl_mask); - - /* Set HSITRIM bits to the reset value*/ - LL_RCC_HSI_SetCalibTrimming(0x10U); - - /* Wait for PLL READY bit to be reset */ - while(LL_RCC_PLL_IsReady() != 0U) - {} - - /* Wait for PLLI2S READY bit to be reset */ - while(LL_RCC_PLLI2S_IsReady() != 0U) - {} - - /* Wait for PLLSAI READY bit to be reset */ - while(LL_RCC_PLLSAI_IsReady() != 0U) - {} - - /* Reset PLLCFGR register */ - LL_RCC_WriteReg(PLLCFGR, 0x24003010U); - - /* Reset PLLI2SCFGR register */ - LL_RCC_WriteReg(PLLI2SCFGR, 0x24003000U); - - /* Reset PLLSAICFGR register */ - LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U); - - /* Disable all interrupts */ - CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE); - - /* Clear all interrupt flags */ - SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC); - - /* Clear LSION bit */ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); - - /* Reset all CSR flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - - return SUCCESS; -} - -/** - * @} - */ - -/** @addtogroup RCC_LL_EF_Get_Freq - * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks - * and different peripheral clocks available on the device. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) - * or HSI_VALUE(**) multiplied/divided by the PLL factors. - * @note (**) HSI_VALUE is a constant defined in this file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (***) HSE_VALUE is a constant defined in this file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * @note The result of this function could be incorrect when using fractional - * value for HSE crystal. - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * @{ - */ - -/** - * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks - * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function - * must be called to update structure fields. Otherwise, any - * configuration based on this function will be incorrect. - * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies - * @retval None - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) -{ - /* Get SYSCLK frequency */ - RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); - - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); - - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); - - /* PCLK2 clock frequency */ - RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency); -} - -/** - * @brief Return USARTx clock frequency - * @param USARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE - * @arg @ref LL_RCC_USART2_CLKSOURCE - * @arg @ref LL_RCC_USART3_CLKSOURCE - * @arg @ref LL_RCC_USART6_CLKSOURCE - * @retval USART clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready - */ -uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource) -{ - uint32_t usart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_USART_CLKSOURCE(USARTxSource)); - - if (USARTxSource == LL_RCC_USART1_CLKSOURCE) - { - /* USART1CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART1_CLKSOURCE_SYSCLK: /* USART1 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART1_CLKSOURCE_HSI: /* USART1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART1_CLKSOURCE_LSE: /* USART1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART1_CLKSOURCE_PCLK2: /* USART1 Clock is PCLK2 */ - default: - usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - else if (USARTxSource == LL_RCC_USART2_CLKSOURCE) - { - /* USART2CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART2_CLKSOURCE_SYSCLK: /* USART2 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART2_CLKSOURCE_HSI: /* USART2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART2_CLKSOURCE_LSE: /* USART2 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART2_CLKSOURCE_PCLK1: /* USART2 Clock is PCLK1 */ - default: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - else if (USARTxSource == LL_RCC_USART6_CLKSOURCE) - { - /* USART6CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART6_CLKSOURCE_SYSCLK: /* USART6 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART6_CLKSOURCE_HSI: /* USART6 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART6_CLKSOURCE_LSE: /* USART6 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART6_CLKSOURCE_PCLK2: /* USART6 Clock is PCLK2 */ - default: - usart_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - else - { - if (USARTxSource == LL_RCC_USART3_CLKSOURCE) - { - /* USART3CLK clock frequency */ - switch (LL_RCC_GetUSARTClockSource(USARTxSource)) - { - case LL_RCC_USART3_CLKSOURCE_SYSCLK: /* USART3 Clock is System Clock */ - usart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_USART3_CLKSOURCE_HSI: /* USART3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - usart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_USART3_CLKSOURCE_LSE: /* USART3 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - usart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_USART3_CLKSOURCE_PCLK1: /* USART3 Clock is PCLK1 */ - default: - usart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - } - return usart_frequency; -} - -/** - * @brief Return UARTx clock frequency - * @param UARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_UART4_CLKSOURCE - * @arg @ref LL_RCC_UART5_CLKSOURCE - * @arg @ref LL_RCC_UART7_CLKSOURCE - * @arg @ref LL_RCC_UART8_CLKSOURCE - * @retval UART clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready - */ -uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource) -{ - uint32_t uart_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_UART_CLKSOURCE(UARTxSource)); - - if (UARTxSource == LL_RCC_UART4_CLKSOURCE) - { - /* UART4CLK clock frequency */ - switch (LL_RCC_GetUARTClockSource(UARTxSource)) - { - case LL_RCC_UART4_CLKSOURCE_SYSCLK: /* UART4 Clock is System Clock */ - uart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_UART4_CLKSOURCE_HSI: /* UART4 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - uart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_UART4_CLKSOURCE_LSE: /* UART4 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - uart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_UART4_CLKSOURCE_PCLK1: /* UART4 Clock is PCLK1 */ - default: - uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - else if (UARTxSource == LL_RCC_UART5_CLKSOURCE) - { - /* UART5CLK clock frequency */ - switch (LL_RCC_GetUARTClockSource(UARTxSource)) - { - case LL_RCC_UART5_CLKSOURCE_SYSCLK: /* UART5 Clock is System Clock */ - uart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_UART5_CLKSOURCE_HSI: /* UART5 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - uart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_UART5_CLKSOURCE_LSE: /* UART5 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - uart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_UART5_CLKSOURCE_PCLK1: /* UART5 Clock is PCLK1 */ - default: - uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - else if (UARTxSource == LL_RCC_UART7_CLKSOURCE) - { - /* UART7CLK clock frequency */ - switch (LL_RCC_GetUARTClockSource(UARTxSource)) - { - case LL_RCC_UART7_CLKSOURCE_SYSCLK: /* UART7 Clock is System Clock */ - uart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_UART7_CLKSOURCE_HSI: /* UART7 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - uart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_UART7_CLKSOURCE_LSE: /* UART7 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - uart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_UART7_CLKSOURCE_PCLK1: /* UART7 Clock is PCLK1 */ - default: - uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - else - { - if (UARTxSource == LL_RCC_UART8_CLKSOURCE) - { - /* UART8CLK clock frequency */ - switch (LL_RCC_GetUARTClockSource(UARTxSource)) - { - case LL_RCC_UART8_CLKSOURCE_SYSCLK: /* UART8 Clock is System Clock */ - uart_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_UART8_CLKSOURCE_HSI: /* UART8 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - uart_frequency = HSI_VALUE; - } - break; - - case LL_RCC_UART8_CLKSOURCE_LSE: /* UART8 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - uart_frequency = LSE_VALUE; - } - break; - - case LL_RCC_UART8_CLKSOURCE_PCLK1: /* UART8 Clock is PCLK1 */ - default: - uart_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - } - return uart_frequency; -} - -/** - * @brief Return I2Cx clock frequency - * @param I2CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE - * @arg @ref LL_RCC_I2C2_CLKSOURCE - * @arg @ref LL_RCC_I2C3_CLKSOURCE - * @arg @ref LL_RCC_I2C4_CLKSOURCE (*) - * - * (*) value not defined in all devices. - * @retval I2C clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready - */ -uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource) -{ - uint32_t i2c_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_I2C_CLKSOURCE(I2CxSource)); - - if (I2CxSource == LL_RCC_I2C1_CLKSOURCE) - { - /* I2C1 CLK clock frequency */ - switch (LL_RCC_GetI2CClockSource(I2CxSource)) - { - case LL_RCC_I2C1_CLKSOURCE_SYSCLK: /* I2C1 Clock is System Clock */ - i2c_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_I2C1_CLKSOURCE_HSI: /* I2C1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - i2c_frequency = HSI_VALUE; - } - break; - - case LL_RCC_I2C1_CLKSOURCE_PCLK1: /* I2C1 Clock is PCLK1 */ - default: - i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - else if (I2CxSource == LL_RCC_I2C2_CLKSOURCE) - { - /* I2C2 CLK clock frequency */ - switch (LL_RCC_GetI2CClockSource(I2CxSource)) - { - case LL_RCC_I2C2_CLKSOURCE_SYSCLK: /* I2C2 Clock is System Clock */ - i2c_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_I2C2_CLKSOURCE_HSI: /* I2C2 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - i2c_frequency = HSI_VALUE; - } - break; - - case LL_RCC_I2C2_CLKSOURCE_PCLK1: /* I2C2 Clock is PCLK1 */ - default: - i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - else if (I2CxSource == LL_RCC_I2C3_CLKSOURCE) - { - /* I2C3 CLK clock frequency */ - switch (LL_RCC_GetI2CClockSource(I2CxSource)) - { - case LL_RCC_I2C3_CLKSOURCE_SYSCLK: /* I2C3 Clock is System Clock */ - i2c_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_I2C3_CLKSOURCE_HSI: /* I2C3 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - i2c_frequency = HSI_VALUE; - } - break; - - case LL_RCC_I2C3_CLKSOURCE_PCLK1: /* I2C3 Clock is PCLK1 */ - default: - i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } -#if defined(I2C4) - else - { - if (I2CxSource == LL_RCC_I2C4_CLKSOURCE) - { - /* I2C4 CLK clock frequency */ - switch (LL_RCC_GetI2CClockSource(I2CxSource)) - { - case LL_RCC_I2C4_CLKSOURCE_SYSCLK: /* I2C4 Clock is System Clock */ - i2c_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_I2C4_CLKSOURCE_HSI: /* I2C4 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - i2c_frequency = HSI_VALUE; - } - break; - - case LL_RCC_I2C4_CLKSOURCE_PCLK1: /* I2C4 Clock is PCLK1 */ - default: - i2c_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - } -#else - else - { - /* Nothing to do */ - } -#endif /* I2C4 */ - - return i2c_frequency; -} - -/** - * @brief Return I2Sx clock frequency - * @param I2SxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2S1_CLKSOURCE - * @retval I2S clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLLI2S oscillator is not ready - */ -uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource) -{ - uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource)); - - if (I2SxSource == LL_RCC_I2S1_CLKSOURCE) - { - /* I2S1 CLK clock frequency */ - switch (LL_RCC_GetI2SClockSource(I2SxSource)) - { - case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */ - if (LL_RCC_PLLI2S_IsReady()) - { - i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S(); - } - break; - - case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */ - default: - i2s_frequency = EXTERNAL_CLOCK_VALUE; - break; - } - } - - return i2s_frequency; -} - -/** - * @brief Return LPTIMx clock frequency - * @param LPTIMxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE - * @retval LPTIM clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready - */ -uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource) -{ - uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource)); - - if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE) - { - /* LPTIM1CLK clock frequency */ - switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource)) - { - case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ - if (LL_RCC_LSI_IsReady()) - { - lptim_frequency = LSI_VALUE; - } - break; - - case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */ - if (LL_RCC_HSI_IsReady()) - { - lptim_frequency = HSI_VALUE; - } - break; - - case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - lptim_frequency = LSE_VALUE; - } - break; - - case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ - default: - lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - - return lptim_frequency; -} - -/** - * @brief Return SAIx clock frequency - * @param SAIxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE - * @arg @ref LL_RCC_SAI2_CLKSOURCE - * @retval SAI clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that PLL is not ready - */ -uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource) -{ - uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource)); - - if (SAIxSource == LL_RCC_SAI1_CLKSOURCE) - { - /* SAI1CLK clock frequency */ - switch (LL_RCC_GetSAIClockSource(SAIxSource)) - { - case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */ - if (LL_RCC_PLLSAI_IsReady()) - { - sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); - } - break; - - case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */ - if (LL_RCC_PLLI2S_IsReady()) - { - sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); - } - break; - -#if defined(RCC_SAI1SEL_PLLSRC_SUPPORT) - case LL_RCC_SAI1_CLKSOURCE_PLLSRC: - switch (LL_RCC_PLL_GetMainSource()) - { - case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 clock source */ - if (LL_RCC_HSE_IsReady()) - { - sai_frequency = HSE_VALUE; - } - break; - - case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 clock source */ - default: - if (LL_RCC_HSI_IsReady()) - { - sai_frequency = HSI_VALUE; - } - break; - } - break; -#endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */ - case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */ - sai_frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; - - default: - break; - } - } - else - { - if (SAIxSource == LL_RCC_SAI2_CLKSOURCE) - { - /* SAI2CLK clock frequency */ - switch (LL_RCC_GetSAIClockSource(SAIxSource)) - { - case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */ - if (LL_RCC_PLLSAI_IsReady()) - { - sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI(); - } - break; - - case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */ - if (LL_RCC_PLLI2S_IsReady()) - { - sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI(); - } - break; - -#if defined(RCC_SAI2SEL_PLLSRC_SUPPORT) - case LL_RCC_SAI2_CLKSOURCE_PLLSRC: - switch (LL_RCC_PLL_GetMainSource()) - { - case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */ - if (LL_RCC_HSE_IsReady()) - { - sai_frequency = HSE_VALUE; - } - break; - - case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */ - default: - if (LL_RCC_HSI_IsReady()) - { - sai_frequency = HSI_VALUE; - } - break; - } - break; -#endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */ - case LL_RCC_SAI2_CLKSOURCE_PIN: /* External input clock used as SAI2 clock source */ - sai_frequency = EXTERNAL_SAI2_CLOCK_VALUE; - break; - - default: - break; - } - } - } - - return sai_frequency; -} - -/** - * @brief Return SDMMCx clock frequency - * @param SDMMCxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SDMMC1_CLKSOURCE - * @arg @ref LL_RCC_SDMMC2_CLKSOURCE (*) - * - * (*) value not defined in all devices. - * @retval SDMMC clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLL is not ready - */ -uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource) -{ - uint32_t sdmmc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_SDMMC_CLKSOURCE(SDMMCxSource)); - - if (SDMMCxSource == LL_RCC_SDMMC1_CLKSOURCE) - { - /* SDMMC1CLK clock frequency */ - switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) - { - case LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC1 clock source */ - switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE)) - { - case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */ - if (LL_RCC_PLL_IsReady()) - { - sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); - } - break; - - case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */ - default: - if (LL_RCC_PLLSAI_IsReady()) - { - sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M(); - } - break; - } - break; - - case LL_RCC_SDMMC1_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC1 clock source */ - default: - sdmmc_frequency = RCC_GetSystemClockFreq(); - break; - } - } -#if defined(SDMMC2) - else - { - /* SDMMC2CLK clock frequency */ - switch (LL_RCC_GetSDMMCClockSource(SDMMCxSource)) - { - case LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK: /* PLL48 clock used as SDMMC2 clock source */ - switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE)) - { - case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */ - if (LL_RCC_PLL_IsReady()) - { - sdmmc_frequency = RCC_PLL_GetFreqDomain_48M(); - } - break; - - case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */ - default: - if (LL_RCC_PLLSAI_IsReady()) - { - sdmmc_frequency = RCC_PLLSAI_GetFreqDomain_48M(); - } - break; - } - break; - - case LL_RCC_SDMMC2_CLKSOURCE_SYSCLK: /* PLL clock used as SDMMC2 clock source */ - default: - sdmmc_frequency = RCC_GetSystemClockFreq(); - break; - } - } -#endif /* SDMMC2 */ - - return sdmmc_frequency; -} - -/** - * @brief Return RNGx clock frequency - * @param RNGxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE - * @retval RNG clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready - */ -uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource) -{ - uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource)); - - /* RNGCLK clock frequency */ - switch (LL_RCC_GetRNGClockSource(RNGxSource)) - { - case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */ - if (LL_RCC_PLL_IsReady()) - { - rng_frequency = RCC_PLL_GetFreqDomain_48M(); - } - break; - - case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */ - default: - if (LL_RCC_PLLSAI_IsReady()) - { - rng_frequency = RCC_PLLSAI_GetFreqDomain_48M(); - } - break; - } - - return rng_frequency; -} - -#if defined(CEC) -/** - * @brief Return CEC clock frequency - * @param CECxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_CEC_CLKSOURCE - * @retval CEC clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready - */ -uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource) -{ - uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource)); - - /* CECCLK clock frequency */ - switch (LL_RCC_GetCECClockSource(CECxSource)) - { - case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady()) - { - cec_frequency = LSE_VALUE; - } - break; - - case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */ - default: - if (LL_RCC_HSI_IsReady()) - { - cec_frequency = HSI_VALUE/488U; - } - break; - } - - return cec_frequency; -} -#endif /* CEC */ - -/** - * @brief Return USBx clock frequency - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval USB clock frequency (in Hz) - */ -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource) -{ - uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource)); - - /* USBCLK clock frequency */ - switch (LL_RCC_GetUSBClockSource(USBxSource)) - { - case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ - if (LL_RCC_PLL_IsReady()) - { - usb_frequency = RCC_PLL_GetFreqDomain_48M(); - } - break; - - case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */ - default: - if (LL_RCC_PLLSAI_IsReady()) - { - usb_frequency = RCC_PLLSAI_GetFreqDomain_48M(); - } - break; - } - - return usb_frequency; -} - -#if defined(DFSDM1_Channel0) -/** - * @brief Return DFSDMx clock frequency - * @param DFSDMxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_CLKSOURCE - * @retval DFSDM clock frequency (in Hz) - */ -uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource) -{ - uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource)); - - /* DFSDM1CLK clock frequency */ - switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource)) - { - case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */ - dfsdm_frequency = RCC_GetSystemClockFreq(); - break; - - case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */ - default: - dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - - return dfsdm_frequency; -} - -/** - * @brief Return DFSDMx Audio clock frequency - * @param DFSDMxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE - * @retval DFSDM clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready - */ -uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource) -{ - uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource)); - - /* DFSDM1CLK clock frequency */ - switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource)) - { - case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1: /* SAI1 clock used as DFSDM1 audio clock */ - dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI1_CLKSOURCE); - break; - - case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2: /* SAI2 clock used as DFSDM1 audio clock */ - default: - dfsdm_frequency = LL_RCC_GetSAIClockFreq(LL_RCC_SAI2_CLKSOURCE); - break; - } - - return dfsdm_frequency; -} -#endif /* DFSDM1_Channel0 */ - -#if defined(DSI) -/** - * @brief Return DSI clock frequency - * @param DSIxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE - * @retval DSI clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready - * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used - */ -uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource) -{ - uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource)); - - /* DSICLK clock frequency */ - switch (LL_RCC_GetDSIClockSource(DSIxSource)) - { - case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */ - if (LL_RCC_PLL_IsReady()) - { - dsi_frequency = RCC_PLL_GetFreqDomain_DSI(); - } - break; - - case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */ - default: - dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA; - break; - } - - return dsi_frequency; -} -#endif /* DSI */ - -#if defined(LTDC) -/** - * @brief Return LTDC clock frequency - * @param LTDCxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_LTDC_CLKSOURCE - * @retval LTDC clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready - */ -uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource) -{ - uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource)); - - if (LL_RCC_PLLSAI_IsReady()) - { - ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC(); - } - - return ltdc_frequency; -} -#endif /* LTDC */ - -#if defined(SPDIFRX) -/** - * @brief Return SPDIFRX clock frequency - * @param SPDIFRXxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE - * @retval SPDIFRX clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready - */ -uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource) -{ - uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource)); - - if (LL_RCC_PLLI2S_IsReady()) - { - spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX(); - } - - return spdifrx_frequency; -} -#endif /* SPDIFRX */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup RCC_LL_Private_Functions - * @{ - */ - -/** - * @brief Return SYSTEM clock frequency - * @retval SYSTEM clock frequency (in Hz) - */ -uint32_t RCC_GetSystemClockFreq(void) -{ - uint32_t frequency = 0U; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (LL_RCC_GetSysClkSource()) - { - case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */ - frequency = HSI_VALUE; - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ - frequency = HSE_VALUE; - break; - - case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ - frequency = RCC_PLL_GetFreqDomain_SYS(); - break; - - default: - frequency = HSI_VALUE; - break; - } - - return frequency; -} - -/** - * @brief Return HCLK clock frequency - * @param SYSCLK_Frequency SYSCLK clock frequency - * @retval HCLK clock frequency (in Hz) - */ -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) -{ - /* HCLK clock frequency */ - return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); -} - -/** - * @brief Return PCLK1 clock frequency - * @param HCLK_Frequency HCLK clock frequency - * @retval PCLK1 clock frequency (in Hz) - */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) -{ - /* PCLK1 clock frequency */ - return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); -} - -/** - * @brief Return PCLK2 clock frequency - * @param HCLK_Frequency HCLK clock frequency - * @retval PCLK2 clock frequency (in Hz) - */ -uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency) -{ - /* PCLK2 clock frequency */ - return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler()); -} - -/** - * @brief Return PLL clock frequency used for system domain - * @retval PLL clock frequency (in Hz) - */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - SYSCLK = PLL_VCO / PLLP - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); -} - -/** - * @brief Return PLL clock frequency used for 48 MHz domain - * @retval PLL clock frequency (in Hz) - */ -uint32_t RCC_PLL_GetFreqDomain_48M(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN - 48M Domain clock = PLL_VCO / PLLQ - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllinputfreq = HSI_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); -} - -#if defined(DSI) -/** - * @brief Return PLL clock frequency used for DSI clock - * @retval PLL clock frequency (in Hz) - */ -uint32_t RCC_PLL_GetFreqDomain_DSI(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN - DSICLK = PLL_VCO / PLLR - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllinputfreq = HSE_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); -} -#endif /* DSI */ - -/** - * @brief Return PLLSAI clock frequency used for SAI1 and SAI2 domains - * @retval PLLSAI clock frequency (in Hz) - */ -uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN - SAI1 and SAI2 domains clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ - pllinputfreq = HSI_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ()); -} - -/** - * @brief Return PLLSAI clock frequency used for 48Mhz domain - * @retval PLLSAI clock frequency (in Hz) - */ -uint32_t RCC_PLLSAI_GetFreqDomain_48M(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN - 48M Domain clock = PLLSAI_VCO / PLLSAIP - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ - pllinputfreq = HSI_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP()); -} - -#if defined(LTDC) -/** - * @brief Return PLLSAI clock frequency used for LTDC domain - * @retval PLLSAI clock frequency (in Hz) - */ -uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLSAIN - LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */ - pllinputfreq = HSI_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR()); -} -#endif /* LTDC */ - -/** - * @brief Return PLLI2S clock frequency used for SAI1 and SAI2 domains - * @retval PLLI2S clock frequency (in Hz) - */ -uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN - SAI1 and SAI2 domains clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ - pllinputfreq = HSI_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLI2S_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ()); -} - -#if defined(SPDIFRX) -/** - * @brief Return PLLI2S clock frequency used for SPDIFRX domain - * @retval PLLI2S clock frequency (in Hz) - */ -uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN - SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ - pllinputfreq = HSI_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ - pllinputfreq = HSE_VALUE; - break; - - default: - pllinputfreq = HSI_VALUE; - break; - } - - return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP()); -} -#endif /* SPDIFRX */ - -/** - * @brief Return PLLI2S clock frequency used for I2S domain - * @retval PLLI2S clock frequency (in Hz) - */ -uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void) -{ - uint32_t pllinputfreq = 0U, pllsource = 0U; - - /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLI2SN - I2S Domain clock = PLLI2S_VCO / PLLI2SR - */ - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */ - pllinputfreq = HSE_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */ - default: - pllinputfreq = HSI_VALUE; - break; - } - return __LL_RCC_CALC_PLLI2S_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), - LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR()); -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rng.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rng.c deleted file mode 100644 index 56257f81..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rng.c +++ /dev/null @@ -1,103 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_rng.c - * @author MCD Application Team - * @brief RNG LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_rng.h" -#include "stm32f7xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (RNG) - -/** @addtogroup RNG_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_LL_Exported_Functions - * @{ - */ - -/** @addtogroup RNG_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize RNG registers (Registers restored to their default values). - * @param RNGx RNG Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RNG registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_RNG_ALL_INSTANCE(RNGx)); - if (RNGx == RNG) - { - /* Enable RNG reset state */ - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); - - /* Release RNG from reset state */ - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); - } - else - { - status = ERROR; - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* RNG */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c deleted file mode 100644 index d53d5933..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c +++ /dev/null @@ -1,841 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_rtc.c - * @author MCD Application Team - * @brief RTC LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_rtc.h" -#include "stm32f7xx_ll_cortex.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(RTC) - -/** @addtogroup RTC_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup RTC_LL_Private_Constants - * @{ - */ -/* Default values used for prescaler */ -#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU -#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU - -/* Values used for timeout */ -#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */ -#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RTC_LL_Private_Macros - * @{ - */ - -#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \ - || ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM)) - -#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU) - -#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU) - -#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ - || ((__VALUE__) == LL_RTC_FORMAT_BCD)) - -#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \ - || ((__VALUE__) == LL_RTC_TIME_FORMAT_PM)) - -#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U)) -#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) -#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) -#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) - -#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \ - || ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \ - || ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \ - || ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \ - || ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \ - || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ - || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) - -#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) - -#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) - -#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) - -#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ - || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ - || ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \ - || ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \ - || ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \ - || ((__VALUE__) == LL_RTC_ALMA_MASK_ALL)) - -#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \ - || ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \ - || ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \ - || ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \ - || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ - || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) - -#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \ - ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY)) - -#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \ - ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY)) - -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup RTC_LL_EF_Init - * @{ - */ - -/** - * @brief De-Initializes the RTC registers to their default reset values. - * @note This function does not reset the RTC Clock source and RTC Backup Data - * registers. - * @param RTCx RTC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are de-initialized - * - ERROR: RTC registers are not de-initialized - */ -ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) -{ - ErrorStatus status = ERROR; - - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Disable the write protection for RTC registers */ - LL_RTC_DisableWriteProtection(RTCx); - - /* Set Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - /* Reset TR, DR and CR registers */ - LL_RTC_WriteReg(RTCx, TR, 0x00000000U); - LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); - LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); - - /* Reset All CR bits except CR[2:0] */ - LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); - - LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); - LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); - LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); - LL_RTC_WriteReg(RTCx, CALR, 0x00000000U); - LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); - LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); - LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); - - /* Reset ISR register and exit initialization mode */ - LL_RTC_WriteReg(RTCx, ISR, 0x00000000U); - - /* Reset Tamper and alternate functions configuration register */ - LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U); - - /* Reset Option register */ - LL_RTC_WriteReg(RTCx, OR, 0x00000000U); - - /* Wait till the RTC RSF flag is set */ - status = LL_RTC_WaitForSynchro(RTCx); - } - - /* Enable the write protection for RTC registers */ - LL_RTC_EnableWriteProtection(RTCx); - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTCx RTC Instance - * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat)); - assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); - assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler)); - - /* Disable the write protection for RTC registers */ - LL_RTC_DisableWriteProtection(RTCx); - - /* Set Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - /* Set Hour Format */ - LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat); - - /* Configure Synchronous and Asynchronous prescaler factor */ - LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler); - LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); - - /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTCx); - - status = SUCCESS; - } - /* Enable the write protection for RTC registers */ - LL_RTC_EnableWriteProtection(RTCx); - - return status; -} - -/** - * @brief Set each @ref LL_RTC_InitTypeDef field to default value. - * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. - * @retval None - */ -void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) -{ - /* Set RTC_InitStruct fields to default values */ - RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR; - RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; - RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT; -} - -/** - * @brief Set the RTC current time. - * @param RTCx RTC Instance - * @param RTC_Format This parameter can be one of the following values: - * @arg @ref LL_RTC_FORMAT_BIN - * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - assert_param(IS_LL_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == LL_RTC_FORMAT_BIN) - { - if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) - { - assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours)); - assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); - } - else - { - RTC_TimeStruct->TimeFormat = 0x00U; - assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); - } - assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); - assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); - } - else - { - if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) - { - assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); - assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat)); - } - else - { - RTC_TimeStruct->TimeFormat = 0x00U; - assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); - } - assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); - assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); - } - - /* Disable the write protection for RTC registers */ - LL_RTC_DisableWriteProtection(RTCx); - - /* Set Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - /* Check the input parameters format */ - if (RTC_Format != LL_RTC_FORMAT_BIN) - { - LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours, - RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds); - } - else - { - LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours), - __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes), - __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds)); - } - - /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTCx); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) - { - status = LL_RTC_WaitForSynchro(RTCx); - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - LL_RTC_EnableWriteProtection(RTCx); - - return status; -} - -/** - * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). - * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. - * @retval None - */ -void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24; - RTC_TimeStruct->Hours = 0U; - RTC_TimeStruct->Minutes = 0U; - RTC_TimeStruct->Seconds = 0U; -} - -/** - * @brief Set the RTC current date. - * @param RTCx RTC Instance - * @param RTC_Format This parameter can be one of the following values: - * @arg @ref LL_RTC_FORMAT_BIN - * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains - * the date configuration information for the RTC. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Day register is configured - * - ERROR: RTC Day register is not configured - */ -ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - assert_param(IS_LL_RTC_FORMAT(RTC_Format)); - - if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) - { - RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU; - } - if (RTC_Format == LL_RTC_FORMAT_BIN) - { - assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year)); - assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month)); - assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day)); - } - else - { - assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year))); - assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month))); - assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day))); - } - assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay)); - - /* Disable the write protection for RTC registers */ - LL_RTC_DisableWriteProtection(RTCx); - - /* Set Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - /* Check the input parameters format */ - if (RTC_Format != LL_RTC_FORMAT_BIN) - { - LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year); - } - else - { - LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day), - __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year)); - } - - /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTCx); - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) - { - status = LL_RTC_WaitForSynchro(RTCx); - } - else - { - status = SUCCESS; - } - } - /* Enable the write protection for RTC registers */ - LL_RTC_EnableWriteProtection(RTCx); - - return status; -} - -/** - * @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00) - * @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized. - * @retval None - */ -void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct) -{ - /* Monday, January 01 xx00 */ - RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY; - RTC_DateStruct->Day = 1U; - RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY; - RTC_DateStruct->Year = 0U; -} - -/** - * @brief Set the RTC Alarm A. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (Use @ref LL_RTC_ALMA_Disable function). - * @param RTCx RTC Instance - * @param RTC_Format This parameter can be one of the following values: - * @arg @ref LL_RTC_FORMAT_BIN - * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ALARMA registers are configured - * - ERROR: ALARMA registers are not configured - */ -ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) -{ - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - assert_param(IS_LL_RTC_FORMAT(RTC_Format)); - assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask)); - assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); - - if (RTC_Format == LL_RTC_FORMAT_BIN) - { - if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) - { - assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); - assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); - } - else - { - RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); - } - assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); - assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); - - if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) - { - assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); - } - else - { - assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); - } - } - else - { - if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) - { - assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); - assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); - } - else - { - RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); - } - - assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); - assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); - - if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) - { - assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); - } - else - { - assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); - } - } - - /* Disable the write protection for RTC registers */ - LL_RTC_DisableWriteProtection(RTCx); - - /* Select weekday selection */ - if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) - { - /* Set the date for ALARM */ - LL_RTC_ALMA_DisableWeekday(RTCx); - if (RTC_Format != LL_RTC_FORMAT_BIN) - { - LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); - } - else - { - LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); - } - } - else - { - /* Set the week day for ALARM */ - LL_RTC_ALMA_EnableWeekday(RTCx); - LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); - } - - /* Configure the Alarm register */ - if (RTC_Format != LL_RTC_FORMAT_BIN) - { - LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, - RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); - } - else - { - LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, - __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), - __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), - __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); - } - /* Set ALARM mask */ - LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); - - /* Enable the write protection for RTC registers */ - LL_RTC_EnableWriteProtection(RTCx); - - return SUCCESS; -} - -/** - * @brief Set the RTC Alarm B. - * @note The Alarm register can only be written when the corresponding Alarm - * is disabled (@ref LL_RTC_ALMB_Disable function). - * @param RTCx RTC Instance - * @param RTC_Format This parameter can be one of the following values: - * @arg @ref LL_RTC_FORMAT_BIN - * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ALARMB registers are configured - * - ERROR: ALARMB registers are not configured - */ -ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) -{ - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - assert_param(IS_LL_RTC_FORMAT(RTC_Format)); - assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask)); - assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel)); - - if (RTC_Format == LL_RTC_FORMAT_BIN) - { - if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) - { - assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours)); - assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); - } - else - { - RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); - } - assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); - assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); - - if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) - { - assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay)); - } - else - { - assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay)); - } - } - else - { - if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR) - { - assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); - assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat)); - } - else - { - RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U; - assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); - } - - assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); - assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); - - if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) - { - assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); - } - else - { - assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay))); - } - } - - /* Disable the write protection for RTC registers */ - LL_RTC_DisableWriteProtection(RTCx); - - /* Select weekday selection */ - if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) - { - /* Set the date for ALARM */ - LL_RTC_ALMB_DisableWeekday(RTCx); - if (RTC_Format != LL_RTC_FORMAT_BIN) - { - LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); - } - else - { - LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay)); - } - } - else - { - /* Set the week day for ALARM */ - LL_RTC_ALMB_EnableWeekday(RTCx); - LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay); - } - - /* Configure the Alarm register */ - if (RTC_Format != LL_RTC_FORMAT_BIN) - { - LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours, - RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds); - } - else - { - LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, - __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours), - __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes), - __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds)); - } - /* Set ALARM mask */ - LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask); - - /* Enable the write protection for RTC registers */ - LL_RTC_EnableWriteProtection(RTCx); - - return SUCCESS; -} - -/** - * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / - * Day = 1st day of the month/Mask = all fields are masked). - * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. - * @retval None - */ -void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM; - RTC_AlarmStruct->AlarmTime.Hours = 0U; - RTC_AlarmStruct->AlarmTime.Minutes = 0U; - RTC_AlarmStruct->AlarmTime.Seconds = 0U; - - /* Alarm Day Settings : Day = 1st day of the month */ - RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE; - RTC_AlarmStruct->AlarmDateWeekDay = 1U; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE; -} - -/** - * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec / - * Day = 1st day of the month/Mask = all fields are masked). - * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. - * @retval None - */ -void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM; - RTC_AlarmStruct->AlarmTime.Hours = 0U; - RTC_AlarmStruct->AlarmTime.Minutes = 0U; - RTC_AlarmStruct->AlarmTime.Seconds = 0U; - - /* Alarm Day Settings : Day = 1st day of the month */ - RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE; - RTC_AlarmStruct->AlarmDateWeekDay = 1U; - - /* Alarm Masks Settings : Mask = all fields are not masked */ - RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE; -} - -/** - * @brief Enters the RTC Initialization mode. - * @note The RTC Initialization mode is write protected, use the - * @ref LL_RTC_DisableWriteProtection before calling this function. - * @param RTCx RTC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) -{ - __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; - ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; - - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Check if the Initialization mode is set */ - if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U) - { - /* Set the Initialization mode */ - LL_RTC_EnableInitMode(RTCx); - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - tmp = LL_RTC_IsActiveFlag_INIT(RTCx); - while ((timeout != 0U) && (tmp != 1U)) - { - if (LL_SYSTICK_IsActiveCounterFlag() == 1U) - { - timeout --; - } - tmp = LL_RTC_IsActiveFlag_INIT(RTCx); - if (timeout == 0U) - { - status = ERROR; - } - } - } - return status; -} - -/** - * @brief Exit the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @note The RTC Initialization mode is write protected, use the - * @ref LL_RTC_DisableWriteProtection before calling this function. - * @param RTCx RTC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC exited from in Init mode - * - ERROR: Not applicable - */ -ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) -{ - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Disable initialization mode */ - LL_RTC_DisableInitMode(RTCx); - - return SUCCESS; -} - -/** - * @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are - * synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * @ref LL_RTC_DisableWriteProtection before calling this function. - * @note To read the calendar through the shadow registers after calendar - * initialization, calendar update or after wakeup from low power modes - * the software must first clear the RSF flag. - * The software must then wait until it is set again before reading - * the calendar, which means that the calendar registers have been - * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param RTCx RTC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) -{ - __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; - ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; - - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Clear RSF flag */ - LL_RTC_ClearFlag_RS(RTCx); - - /* Wait the registers to be synchronised */ - tmp = LL_RTC_IsActiveFlag_RS(RTCx); - while ((timeout != 0U) && (tmp != 1U)) - { - if (LL_SYSTICK_IsActiveCounterFlag() == 1U) - { - timeout--; - } - tmp = LL_RTC_IsActiveFlag_RS(RTCx); - if (timeout == 0U) - { - status = ERROR; - } - } - - return (status); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RTC) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c index 82893db0..28efb6a6 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c @@ -1,1578 +1,1578 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_sdmmc.c - * @author MCD Application Team - * @brief SDMMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the SDMMC peripheral: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### SDMMC peripheral features ##### - ============================================================================== - [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB - peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA - devices. - - [..] The SDMMC features include the following: - (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support - for three different databus modes: 1-bit (default), 4-bit and 8-bit - (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) - (+) Full compliance with SD Memory Card Specifications Version 2.0 - (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two - different data bus modes: 1-bit (default) and 4-bit - (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol - Rev1.1) - (+) Data transfer up to 48 MHz for the 8 bit mode - (+) Data and command output enable signals to control external bidirectional drivers - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a considered as a driver of service for external devices drivers - that interfaces with the SDMMC peripheral. - According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs - is used in the device's driver to perform SDMMC operations and functionalities. - - This driver is almost transparent for the final user, it is only used to implement other - functionalities of the external device. - - [..] - (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK, - PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the - PLL is well configured. - The SDMMC peripheral uses two clock signals: - (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) - (++) APB2 bus clock (PCLK2) - - -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: - Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) - - (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC - peripheral. - - (+) Enable the Power ON State using the SDMMC_PowerState_ON() - function and disable it using the function SDMMC_PowerState_OFF(). - - (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros. - - (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT() - and __SDMMC_DISABLE_IT() if you need to use interrupt mode. - - (+) When using the DMA mode - (++) Configure the DMA in the MSP layer of the external device - (++) Active the needed channel Request - (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro - __SDMMC_DMA_DISABLE(). - - (+) To control the CPSM (Command Path State Machine) and send - commands to the card use the SDMMC_SendCommand(), - SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has - to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according - to the selected command to be sent. - The parameters that should be filled are: - (++) Command Argument - (++) Command Index - (++) Command Response type - (++) Command Wait - (++) CPSM Status (Enable or Disable). - - -@@- To check if the command is well received, read the SDMMC_CMDRESP - register using the SDMMC_GetCommandResponse(). - The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the - SDMMC_GetResponse() function. - - (+) To control the DPSM (Data Path State Machine) and send/receive - data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), - SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions. - - *** Read Operations *** - ======================= - [..] - (#) First, user has to fill the data structure (pointer to - SDMMC_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be from card (To SDMMC) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDMMC resources to receive the data from the card - according to selected transfer mode (Refer to Step 8, 9 and 10). - - (#) Send the selected Read command (refer to step 11). - - (#) Use the SDMMC flags/interrupts to check the transfer status. - - *** Write Operations *** - ======================== - [..] - (#) First, user has to fill the data structure (pointer to - SDMMC_DataInitTypeDef) according to the selected data type to be received. - The parameters that should be filled are: - (++) Data TimeOut - (++) Data Length - (++) Data Block size - (++) Data Transfer direction: should be to card (To CARD) - (++) Data Transfer mode - (++) DPSM Status (Enable or Disable) - - (#) Configure the SDMMC resources to send the data to the card according to - selected transfer mode. - - (#) Send the selected Write command. - - (#) Use the SDMMC flags/interrupts to check the transfer status. - - *** Command management operations *** - ===================================== - [..] - (#) The commands used for Read/Write/Erase operations are managed in - separate functions. - Each function allows to send the needed command with the related argument, - then check the response. - By the same approach, you could implement a command and check the response. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -#if defined(SDMMC1) - -/** @addtogroup STM32F7xx_HAL_Driver - * @{ - */ - -/** @defgroup SDMMC_LL SDMMC Low Layer - * @brief Low layer module for SD - * @{ - */ - -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx); - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions - * @{ - */ - -/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the SDMMC according to the specified - * parameters in the SDMMC_InitTypeDef and create the associated handle. - * @param SDMMCx: Pointer to SDMMC register base - * @param Init: SDMMC initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); - assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); - assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass)); - assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave)); - assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); - assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); - assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); - - /* Set SDMMC configuration parameters */ - tmpreg |= (Init.ClockEdge |\ - Init.ClockBypass |\ - Init.ClockPowerSave |\ - Init.BusWide |\ - Init.HardwareFlowControl |\ - Init.ClockDiv - ); - - /* Write to SDMMC CLKCR */ - MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); - - return HAL_OK; -} - - -/** - * @} - */ - -/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### I/O operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SDMMC data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Read data (word) from Rx FIFO in blocking mode (polling) - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) -{ - /* Read data from Rx FIFO */ - return (SDMMCx->FIFO); -} - -/** - * @brief Write data (word) to Tx FIFO in blocking mode (polling) - * @param SDMMCx: Pointer to SDMMC register base - * @param pWriteData: pointer to data to write - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) -{ - /* Write data to FIFO */ - SDMMCx->FIFO = *pWriteData; - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SDMMC data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Set SDMMC Power state to ON. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) -{ - /* Set power state to ON */ - SDMMCx->POWER = SDMMC_POWER_PWRCTRL; - - return HAL_OK; -} - -/** - * @brief Set SDMMC Power state to OFF. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) -{ - /* Set power state to OFF */ - SDMMCx->POWER = (uint32_t)0x00000000; - - return HAL_OK; -} - -/** - * @brief Get SDMMC Power state. - * @param SDMMCx: Pointer to SDMMC register base - * @retval Power status of the controller. The returned value can be one of the - * following values: - * - 0x00: Power OFF - * - 0x02: Power UP - * - 0x03: Power ON - */ -uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) -{ - return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); -} - -/** - * @brief Configure the SDMMC command path according to the specified parameters in - * SDMMC_CmdInitTypeDef structure and send the command - * @param SDMMCx: Pointer to SDMMC register base - * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains - * the configuration information for the SDMMC command - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex)); - assert_param(IS_SDMMC_RESPONSE(Command->Response)); - assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt)); - assert_param(IS_SDMMC_CPSM(Command->CPSM)); - - /* Set the SDMMC Argument value */ - SDMMCx->ARG = Command->Argument; - - /* Set SDMMC command parameters */ - tmpreg |= (uint32_t)(Command->CmdIndex |\ - Command->Response |\ - Command->WaitForInterrupt |\ - Command->CPSM); - - /* Write to SDMMC CMD register */ - MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); - - return HAL_OK; -} - -/** - * @brief Return the command index of last command for which response received - * @param SDMMCx: Pointer to SDMMC register base - * @retval Command index of the last command response received - */ -uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) -{ - return (uint8_t)(SDMMCx->RESPCMD); -} - - -/** - * @brief Return the response received from the card for the last command - * @param SDMMCx: Pointer to SDMMC register base - * @param Response: Specifies the SDMMC response register. - * This parameter can be one of the following values: - * @arg SDMMC_RESP1: Response Register 1 - * @arg SDMMC_RESP2: Response Register 2 - * @arg SDMMC_RESP3: Response Register 3 - * @arg SDMMC_RESP4: Response Register 4 - * @retval The Corresponding response register value - */ -uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_SDMMC_RESP(Response)); - - /* Get the response */ - tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; - - return (*(__IO uint32_t *) tmp); -} - -/** - * @brief Configure the SDMMC data path according to the specified - * parameters in the SDMMC_DataInitTypeDef. - * @param SDMMCx: Pointer to SDMMC register base - * @param Data : pointer to a SDMMC_DataInitTypeDef structure - * that contains the configuration information for the SDMMC data. - * @retval HAL status - */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) -{ - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength)); - assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize)); - assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir)); - assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode)); - assert_param(IS_SDMMC_DPSM(Data->DPSM)); - - /* Set the SDMMC Data TimeOut value */ - SDMMCx->DTIMER = Data->DataTimeOut; - - /* Set the SDMMC DataLength value */ - SDMMCx->DLEN = Data->DataLength; - - /* Set the SDMMC data configuration parameters */ - tmpreg |= (uint32_t)(Data->DataBlockSize |\ - Data->TransferDir |\ - Data->TransferMode |\ - Data->DPSM); - - /* Write to SDMMC DCTRL */ - MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); - - return HAL_OK; - -} - -/** - * @brief Returns number of remaining data bytes to be transferred. - * @param SDMMCx: Pointer to SDMMC register base - * @retval Number of remaining data bytes to be transferred - */ -uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) -{ - return (SDMMCx->DCOUNT); -} - -/** - * @brief Get the FIFO data - * @param SDMMCx: Pointer to SDMMC register base - * @retval Data received - */ -uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) -{ - return (SDMMCx->FIFO); -} - -/** - * @brief Sets one of the two options of inserting read wait interval. - * @param SDMMCx: Pointer to SDMMC register base - * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode. - * This parameter can be: - * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK - * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 - * @retval None - */ -HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode) -{ - /* Check the parameters */ - assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode)); - - /* Set SDMMC read wait mode */ - MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup HAL_SDMMC_LL_Group4 Command management functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### Commands management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the needed commands. - -@endverbatim - * @{ - */ - -/** - * @brief Send the Data Block Length command and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)BlockSize; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Read Single Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Read Multi Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Write Single Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Write Multi Block command and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Start Address Erase command for SD and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)StartAdd; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the End Address Erase command for SD and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)EndAdd; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Start Address Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)StartAdd; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the End Address Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = (uint32_t)EndAdd; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Erase command and check the response - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Set Block Size for Card */ - sdmmc_cmdinit.Argument = 0U; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Stop Transfer command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD12 STOP_TRANSMISSION */ - sdmmc_cmdinit.Argument = 0U; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Select Deselect command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param addr: Address of the card to be selected - * @retval HAL status - */ -uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD7 SDMMC_SEL_DESEL_CARD */ - sdmmc_cmdinit.Argument = (uint32_t)Addr; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Go Idle State command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - sdmmc_cmdinit.Argument = 0U; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdError(SDMMCx); - - return errorstate; -} - -/** - * @brief Send the Operating Condition command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD8 to verify SD card interface operating condition */ - /* Argument: - [31:12]: Reserved (shall be set to '0') - - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) - - [7:0]: Check Pattern (recommended 0xAA) */ - /* CMD Response: R7 */ - sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp7(SDMMCx); - - return errorstate; -} - -/** - * @brief Send the Application command to verify that that the next command - * is an application specific com-mand rather than a standard command - * and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param Argument: Command Argument - * @retval HAL status - */ -uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - sdmmc_cmdinit.Argument = (uint32_t)Argument; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - /* If there is a HAL_ERROR, it is a MMC card, else - it is a SD card: SD card 2.0 (voltage range mismatch) - or SD card 1.x */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the command asking the accessed card to send its operating - * condition register (OCR) - * @param SDMMCx: Pointer to SDMMC register base - * @param Argument: Command Argument - * @retval HAL status - */ -uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp3(SDMMCx); - - return errorstate; -} - -/** - * @brief Send the Bus Width command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param BusWidth: BusWidth - * @retval HAL status - */ -uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - sdmmc_cmdinit.Argument = (uint32_t)BusWidth; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Send SCR command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD51 SD_APP_SEND_SCR */ - sdmmc_cmdinit.Argument = 0U; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Send CID command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD2 ALL_SEND_CID */ - sdmmc_cmdinit.Argument = 0U; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp2(SDMMCx); - - return errorstate; -} - -/** - * @brief Send the Send CSD command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param Argument: Command Argument - * @retval HAL status - */ -uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD9 SEND_CSD */ - sdmmc_cmdinit.Argument = Argument; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp2(SDMMCx); - - return errorstate; -} - -/** - * @brief Send the Send CSD command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param pRCA: Card RCA - * @retval HAL status - */ -uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD3 SD_CMD_SET_REL_ADDR */ - sdmmc_cmdinit.Argument = 0U; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); - - return errorstate; -} - -/** - * @brief Send the Set Relative Address command to MMC card (not SD card). - * @param SDMMCx Pointer to SDMMC register base - * @param RCA Card RCA - * @retval HAL status - */ -uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD3 SD_CMD_SET_REL_ADDR */ - sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Status command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @param Argument: Command Argument - * @retval HAL status - */ -uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - sdmmc_cmdinit.Argument = Argument; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Status register command and check the response. - * @param SDMMCx: Pointer to SDMMC register base - * @retval HAL status - */ -uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - sdmmc_cmdinit.Argument = 0U; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Sends host capacity support information and activates the card's - * initialization process. Send SDMMC_CMD_SEND_OP_COND command - * @param SDMMCx: Pointer to SDMMC register base - * @parame Argument: Argument used for the command - * @retval HAL status - */ -uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - sdmmc_cmdinit.Argument = Argument; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp3(SDMMCx); - - return errorstate; -} - -/** - * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command - * @param SDMMCx: Pointer to SDMMC register base - * @parame Argument: Argument used for the command - * @retval HAL status - */ -uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ - /* CMD Response: R1 */ - sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */ - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @brief Send the Send EXT_CSD command and check the response. - * @param SDMMCx Pointer to SDMMC register base - * @param Argument Command Argument - * @retval HAL status - */ -uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) -{ - SDMMC_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - - /* Send CMD9 SEND_CSD */ - sdmmc_cmdinit.Argument = Argument; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; - sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; - sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; - (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT); - - return errorstate; -} - -/** - * @} - */ - -/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions - * @brief Responses functions - * -@verbatim - =============================================================================== - ##### Responses management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the needed responses. - -@endverbatim - * @{ - */ -/** - * @brief Checks for error conditions for R1 response. - * @param SDMMCx Pointer to SDMMC register base - * @param SD_CMD: The sent command index - * @retval SD Card error state - */ -uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) -{ - uint32_t response_r1; - uint32_t sta_reg; - - /* 8 is the number of required instructions cycles for the below loop statement. - The Timeout is expressed in ms */ - uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } - sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); - - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) - { - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - - return SDMMC_ERROR_CMD_RSP_TIMEOUT; - } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) - { - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); - - return SDMMC_ERROR_CMD_CRC_FAIL; - } - else - { - /* Nothing to do */ - } - - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - - /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) - { - return SDMMC_ERROR_CMD_CRC_FAIL; - } - - /* We have received response, retrieve it for analysis */ - response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); - - if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) - { - return SDMMC_ERROR_NONE; - } - else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) - { - return SDMMC_ERROR_ADDR_OUT_OF_RANGE; - } - else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) - { - return SDMMC_ERROR_ADDR_MISALIGNED; - } - else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) - { - return SDMMC_ERROR_BLOCK_LEN_ERR; - } - else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) - { - return SDMMC_ERROR_ERASE_SEQ_ERR; - } - else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) - { - return SDMMC_ERROR_BAD_ERASE_PARAM; - } - else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) - { - return SDMMC_ERROR_WRITE_PROT_VIOLATION; - } - else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) - { - return SDMMC_ERROR_LOCK_UNLOCK_FAILED; - } - else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) - { - return SDMMC_ERROR_COM_CRC_FAILED; - } - else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) - { - return SDMMC_ERROR_ILLEGAL_CMD; - } - else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) - { - return SDMMC_ERROR_CARD_ECC_FAILED; - } - else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) - { - return SDMMC_ERROR_CC_ERR; - } - else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) - { - return SDMMC_ERROR_STREAM_READ_UNDERRUN; - } - else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) - { - return SDMMC_ERROR_STREAM_WRITE_OVERRUN; - } - else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) - { - return SDMMC_ERROR_CID_CSD_OVERWRITE; - } - else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) - { - return SDMMC_ERROR_WP_ERASE_SKIP; - } - else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) - { - return SDMMC_ERROR_CARD_ECC_DISABLED; - } - else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) - { - return SDMMC_ERROR_ERASE_RESET; - } - else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) - { - return SDMMC_ERROR_AKE_SEQ_ERR; - } - else - { - return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; - } -} - -/** - * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param SDMMCx Pointer to SDMMC register base - * @retval SD Card error state - */ -uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) -{ - uint32_t sta_reg; - /* 8 is the number of required instructions cycles for the below loop statement. - The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } - sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); - - if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) - { - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - - return SDMMC_ERROR_CMD_RSP_TIMEOUT; - } - else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) - { - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); - - return SDMMC_ERROR_CMD_CRC_FAIL; - } - else - { - /* No error flag set */ - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - } - - return SDMMC_ERROR_NONE; -} - -/** - * @brief Checks for error conditions for R3 (OCR) response. - * @param SDMMCx Pointer to SDMMC register base - * @retval SD Card error state - */ -uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) -{ - uint32_t sta_reg; - /* 8 is the number of required instructions cycles for the below loop statement. - The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } - sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); - - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) - { - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - - return SDMMC_ERROR_CMD_RSP_TIMEOUT; - } - else - { - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - } - - return SDMMC_ERROR_NONE; -} - -/** - * @brief Checks for error conditions for R6 (RCA) response. - * @param SDMMCx Pointer to SDMMC register base - * @param SD_CMD: The sent command index - * @param pRCA: Pointer to the variable that will contain the SD card relative - * address RCA - * @retval SD Card error state - */ -uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) -{ - uint32_t response_r1; - uint32_t sta_reg; - - /* 8 is the number of required instructions cycles for the below loop statement. - The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } - sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); - - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) - { - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - - return SDMMC_ERROR_CMD_RSP_TIMEOUT; - } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) - { - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); - - return SDMMC_ERROR_CMD_CRC_FAIL; - } - else - { - /* Nothing to do */ - } - - /* Check response received is of desired command */ - if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) - { - return SDMMC_ERROR_CMD_CRC_FAIL; - } - - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - - /* We have received response, retrieve it. */ - response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); - - if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) - { - *pRCA = (uint16_t) (response_r1 >> 16); - - return SDMMC_ERROR_NONE; - } - else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) - { - return SDMMC_ERROR_ILLEGAL_CMD; - } - else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) - { - return SDMMC_ERROR_COM_CRC_FAILED; - } - else - { - return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; - } -} - -/** - * @brief Checks for error conditions for R7 response. - * @param SDMMCx Pointer to SDMMC register base - * @retval SD Card error state - */ -uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) -{ - uint32_t sta_reg; - /* 8 is the number of required instructions cycles for the below loop statement. - The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } - sta_reg = SDMMCx->STA; - }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || - ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); - - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) - { - /* Card is SD V2.0 compliant */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); - - return SDMMC_ERROR_CMD_RSP_TIMEOUT; - } - else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) - { - /* Card is SD V2.0 compliant */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); - - return SDMMC_ERROR_CMD_CRC_FAIL; - } - else - { - /* Nothing to do */ - } - - if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) - { - /* Card is SD V2.0 compliant */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); - } - - return SDMMC_ERROR_NONE; - -} - -/** - * @} - */ - -/* Private function ----------------------------------------------------------*/ -/** @addtogroup SD_Private_Functions - * @{ - */ - -/** - * @brief Checks for error conditions for CMD0. - * @param SDMMCx Pointer to SDMMC register base - * @retval SD Card error state - */ -static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) -{ - /* 8 is the number of required instructions cycles for the below loop statement. - The SDMMC_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } - - }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); - - /* Clear all the static flags */ - __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); - - return SDMMC_ERROR_NONE; -} - - -/** - * @} - */ - -#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* SDMMC1 */ +/** + ****************************************************************************** + * @file stm32f7xx_ll_sdmmc.c + * @author MCD Application Team + * @brief SDMMC Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the SDMMC peripheral: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### SDMMC peripheral features ##### + ============================================================================== + [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the AHB + peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA + devices. + + [..] The SDMMC features include the following: + (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support + for three different databus modes: 1-bit (default), 4-bit and 8-bit + (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility) + (+) Full compliance with SD Memory Card Specifications Version 2.0 + (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two + different data bus modes: 1-bit (default) and 4-bit + (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol + Rev1.1) + (+) Data transfer up to 48 MHz for the 8 bit mode + (+) Data and command output enable signals to control external bidirectional drivers + + ##### How to use this driver ##### + ============================================================================== + [..] + This driver is a considered as a driver of service for external devices drivers + that interfaces with the SDMMC peripheral. + According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs + is used in the device's driver to perform SDMMC operations and functionalities. + + This driver is almost transparent for the final user, it is only used to implement other + functionalities of the external device. + + [..] + (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK, + PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the + PLL is well configured. + The SDMMC peripheral uses two clock signals: + (++) SDMMC adapter clock (SDMMCCLK = 48 MHz) + (++) APB2 bus clock (PCLK2) + + -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition: + Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK)) + + (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC + peripheral. + + (+) Enable the Power ON State using the SDMMC_PowerState_ON() + function and disable it using the function SDMMC_PowerState_OFF(). + + (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros. + + (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT() + and __SDMMC_DISABLE_IT() if you need to use interrupt mode. + + (+) When using the DMA mode + (++) Configure the DMA in the MSP layer of the external device + (++) Active the needed channel Request + (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro + __SDMMC_DMA_DISABLE(). + + (+) To control the CPSM (Command Path State Machine) and send + commands to the card use the SDMMC_SendCommand(), + SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has + to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according + to the selected command to be sent. + The parameters that should be filled are: + (++) Command Argument + (++) Command Index + (++) Command Response type + (++) Command Wait + (++) CPSM Status (Enable or Disable). + + -@@- To check if the command is well received, read the SDMMC_CMDRESP + register using the SDMMC_GetCommandResponse(). + The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the + SDMMC_GetResponse() function. + + (+) To control the DPSM (Data Path State Machine) and send/receive + data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), + SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions. + + *** Read Operations *** + ======================= + [..] + (#) First, user has to fill the data structure (pointer to + SDMMC_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be from card (To SDMMC) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDMMC resources to receive the data from the card + according to selected transfer mode (Refer to Step 8, 9 and 10). + + (#) Send the selected Read command (refer to step 11). + + (#) Use the SDMMC flags/interrupts to check the transfer status. + + *** Write Operations *** + ======================== + [..] + (#) First, user has to fill the data structure (pointer to + SDMMC_DataInitTypeDef) according to the selected data type to be received. + The parameters that should be filled are: + (++) Data TimeOut + (++) Data Length + (++) Data Block size + (++) Data Transfer direction: should be to card (To CARD) + (++) Data Transfer mode + (++) DPSM Status (Enable or Disable) + + (#) Configure the SDMMC resources to send the data to the card according to + selected transfer mode. + + (#) Send the selected Write command. + + (#) Use the SDMMC flags/interrupts to check the transfer status. + + *** Command management operations *** + ===================================== + [..] + (#) The commands used for Read/Write/Erase operations are managed in + separate functions. + Each function allows to send the needed command with the related argument, + then check the response. + By the same approach, you could implement a command and check the response. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +#if defined(SDMMC1) + +/** @addtogroup STM32F7xx_HAL_Driver + * @{ + */ + +/** @defgroup SDMMC_LL SDMMC Low Layer + * @brief Low layer module for SD + * @{ + */ + +#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx); + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions + * @{ + */ + +/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the SDMMC according to the specified + * parameters in the SDMMC_InitTypeDef and create the associated handle. + * @param SDMMCx: Pointer to SDMMC register base + * @param Init: SDMMC initialization structure + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx)); + assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); + assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass)); + assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave)); + assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide)); + assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl)); + assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv)); + + /* Set SDMMC configuration parameters */ + tmpreg |= (Init.ClockEdge |\ + Init.ClockBypass |\ + Init.ClockPowerSave |\ + Init.BusWide |\ + Init.HardwareFlowControl |\ + Init.ClockDiv + ); + + /* Write to SDMMC CLKCR */ + MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, tmpreg); + + return HAL_OK; +} + + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### I/O operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SDMMC data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Read data (word) from Rx FIFO in blocking mode (polling) + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx) +{ + /* Read data from Rx FIFO */ + return (SDMMCx->FIFO); +} + +/** + * @brief Write data (word) to Tx FIFO in blocking mode (polling) + * @param SDMMCx: Pointer to SDMMC register base + * @param pWriteData: pointer to data to write + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData) +{ + /* Write data to FIFO */ + SDMMCx->FIFO = *pWriteData; + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the SDMMC data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Set SDMMC Power state to ON. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx) +{ + /* Set power state to ON */ + SDMMCx->POWER = SDMMC_POWER_PWRCTRL; + + return HAL_OK; +} + +/** + * @brief Set SDMMC Power state to OFF. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx) +{ + /* Set power state to OFF */ + SDMMCx->POWER = (uint32_t)0x00000000; + + return HAL_OK; +} + +/** + * @brief Get SDMMC Power state. + * @param SDMMCx: Pointer to SDMMC register base + * @retval Power status of the controller. The returned value can be one of the + * following values: + * - 0x00: Power OFF + * - 0x02: Power UP + * - 0x03: Power ON + */ +uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx) +{ + return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL); +} + +/** + * @brief Configure the SDMMC command path according to the specified parameters in + * SDMMC_CmdInitTypeDef structure and send the command + * @param SDMMCx: Pointer to SDMMC register base + * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains + * the configuration information for the SDMMC command + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex)); + assert_param(IS_SDMMC_RESPONSE(Command->Response)); + assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt)); + assert_param(IS_SDMMC_CPSM(Command->CPSM)); + + /* Set the SDMMC Argument value */ + SDMMCx->ARG = Command->Argument; + + /* Set SDMMC command parameters */ + tmpreg |= (uint32_t)(Command->CmdIndex |\ + Command->Response |\ + Command->WaitForInterrupt |\ + Command->CPSM); + + /* Write to SDMMC CMD register */ + MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, tmpreg); + + return HAL_OK; +} + +/** + * @brief Return the command index of last command for which response received + * @param SDMMCx: Pointer to SDMMC register base + * @retval Command index of the last command response received + */ +uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx) +{ + return (uint8_t)(SDMMCx->RESPCMD); +} + + +/** + * @brief Return the response received from the card for the last command + * @param SDMMCx: Pointer to SDMMC register base + * @param Response: Specifies the SDMMC response register. + * This parameter can be one of the following values: + * @arg SDMMC_RESP1: Response Register 1 + * @arg SDMMC_RESP2: Response Register 2 + * @arg SDMMC_RESP3: Response Register 3 + * @arg SDMMC_RESP4: Response Register 4 + * @retval The Corresponding response register value + */ +uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response) +{ + uint32_t tmp; + + /* Check the parameters */ + assert_param(IS_SDMMC_RESP(Response)); + + /* Get the response */ + tmp = (uint32_t)(&(SDMMCx->RESP1)) + Response; + + return (*(__IO uint32_t *) tmp); +} + +/** + * @brief Configure the SDMMC data path according to the specified + * parameters in the SDMMC_DataInitTypeDef. + * @param SDMMCx: Pointer to SDMMC register base + * @param Data : pointer to a SDMMC_DataInitTypeDef structure + * that contains the configuration information for the SDMMC data. + * @retval HAL status + */ +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength)); + assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize)); + assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir)); + assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode)); + assert_param(IS_SDMMC_DPSM(Data->DPSM)); + + /* Set the SDMMC Data TimeOut value */ + SDMMCx->DTIMER = Data->DataTimeOut; + + /* Set the SDMMC DataLength value */ + SDMMCx->DLEN = Data->DataLength; + + /* Set the SDMMC data configuration parameters */ + tmpreg |= (uint32_t)(Data->DataBlockSize |\ + Data->TransferDir |\ + Data->TransferMode |\ + Data->DPSM); + + /* Write to SDMMC DCTRL */ + MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, tmpreg); + + return HAL_OK; + +} + +/** + * @brief Returns number of remaining data bytes to be transferred. + * @param SDMMCx: Pointer to SDMMC register base + * @retval Number of remaining data bytes to be transferred + */ +uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx) +{ + return (SDMMCx->DCOUNT); +} + +/** + * @brief Get the FIFO data + * @param SDMMCx: Pointer to SDMMC register base + * @retval Data received + */ +uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx) +{ + return (SDMMCx->FIFO); +} + +/** + * @brief Sets one of the two options of inserting read wait interval. + * @param SDMMCx: Pointer to SDMMC register base + * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode. + * This parameter can be: + * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK + * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2 + * @retval None + */ +HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode) +{ + /* Check the parameters */ + assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode)); + + /* Set SDMMC read wait mode */ + MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); + + return HAL_OK; +} + +/** + * @} + */ + + +/** @defgroup HAL_SDMMC_LL_Group4 Command management functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### Commands management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed commands. + +@endverbatim + * @{ + */ + +/** + * @brief Send the Data Block Length command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)BlockSize; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_BLOCKLEN; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_BLOCKLEN, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Single Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Read Multi Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)ReadAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_READ_MULT_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_READ_MULT_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Single Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_SINGLE_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_SINGLE_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Write Multi Block command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)WriteAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_WRITE_MULT_BLOCK; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_WRITE_MULT_BLOCK, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command for SD and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)StartAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_START; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_START, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = (uint32_t)EndAdd; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE_GRP_END; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE_GRP_END, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Erase command and check the response + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Set Block Size for Card */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ERASE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_ERASE, SDMMC_MAXERASETIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD12 STOP_TRANSMISSION */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_STOP_TRANSMISSION; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_STOP_TRANSMISSION, SDMMC_STOPTRANSFERTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param addr: Address of the card to be selected + * @retval HAL status + */ +uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD7 SDMMC_SEL_DESEL_CARD */ + sdmmc_cmdinit.Argument = (uint32_t)Addr; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEL_DESEL_CARD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEL_DESEL_CARD, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_GO_IDLE_STATE; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_NO; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdError(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Operating Condition command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD8 to verify SD card interface operating condition */ + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + /* CMD Response: R7 */ + sdmmc_cmdinit.Argument = SDMMC_CHECK_PATTERN; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp7(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific com-mand rather than a standard command + * and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = (uint32_t)Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_CMD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + /* If there is a HAL_ERROR, it is a MMC card, else + it is a SD card: SD card 2.0 (voltage range mismatch) + or SD card 1.x */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_CMD, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the command asking the accessed card to send its operating + * condition register (OCR) + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = SDMMC_VOLTAGE_WINDOW_SD | Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param BusWidth: BusWidth + * @retval HAL status + */ +uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = (uint32_t)BusWidth; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_APP_SD_SET_BUSWIDTH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_APP_SD_SET_BUSWIDTH, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD51 SD_APP_SEND_SCR */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_SEND_SCR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_SEND_SCR, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send CID command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD2 ALL_SEND_CID */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_ALL_SEND_CID; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_LONG; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp2(SDMMCx); + + return errorstate; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param pRCA: Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp6(SDMMCx, SDMMC_CMD_SET_REL_ADDR, pRCA); + + return errorstate; +} + +/** + * @brief Send the Set Relative Address command to MMC card (not SD card). + * @param SDMMCx Pointer to SDMMC register base + * @param RCA Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAddMmc(SDMMC_TypeDef *SDMMCx, uint16_t RCA) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SET_REL_ADDR, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Status command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_STATUS; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SEND_STATUS, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Status register command and check the response. + * @param SDMMCx: Pointer to SDMMC register base + * @retval HAL status + */ +uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = 0U; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SD_APP_STATUS; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_SD_APP_STATUS, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Sends host capacity support information and activates the card's + * initialization process. Send SDMMC_CMD_SEND_OP_COND command + * @param SDMMCx: Pointer to SDMMC register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SEND_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp3(SDMMCx); + + return errorstate; +} + +/** + * @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH command + * @param SDMMCx: Pointer to SDMMC register base + * @parame Argument: Argument used for the command + * @retval HAL status + */ +uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD6 to activate SDR50 Mode and Power Limit 1.44W */ + /* CMD Response: R1 */ + sdmmc_cmdinit.Argument = Argument; /* SDMMC_SDR25_SWITCH_PATTERN */ + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SWITCH; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SWITCH, SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @brief Send the Send EXT_CSD command and check the response. + * @param SDMMCx Pointer to SDMMC register base + * @param Argument Command Argument + * @retval HAL status + */ +uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDMMCx, SDMMC_CMD_HS_SEND_EXT_CSD,SDMMC_CMDTIMEOUT); + + return errorstate; +} + +/** + * @} + */ + +/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions + * @brief Responses functions + * +@verbatim + =============================================================================== + ##### Responses management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed responses. + +@endverbatim + * @{ + */ +/** + * @brief Checks for error conditions for R1 response. + * @param SDMMCx Pointer to SDMMC register base + * @param SD_CMD: The sent command index + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout) +{ + uint32_t response_r1; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The Timeout is expressed in ms */ + uint32_t count = Timeout * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* Check response received is of desired command */ + if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* We have received response, retrieve it for analysis */ + response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if((response_r1 & SDMMC_OCR_ERRORBITS) == SDMMC_ALLZERO) + { + return SDMMC_ERROR_NONE; + } + else if((response_r1 & SDMMC_OCR_ADDR_OUT_OF_RANGE) == SDMMC_OCR_ADDR_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if((response_r1 & SDMMC_OCR_ADDR_MISALIGNED) == SDMMC_OCR_ADDR_MISALIGNED) + { + return SDMMC_ERROR_ADDR_MISALIGNED; + } + else if((response_r1 & SDMMC_OCR_BLOCK_LEN_ERR) == SDMMC_OCR_BLOCK_LEN_ERR) + { + return SDMMC_ERROR_BLOCK_LEN_ERR; + } + else if((response_r1 & SDMMC_OCR_ERASE_SEQ_ERR) == SDMMC_OCR_ERASE_SEQ_ERR) + { + return SDMMC_ERROR_ERASE_SEQ_ERR; + } + else if((response_r1 & SDMMC_OCR_BAD_ERASE_PARAM) == SDMMC_OCR_BAD_ERASE_PARAM) + { + return SDMMC_ERROR_BAD_ERASE_PARAM; + } + else if((response_r1 & SDMMC_OCR_WRITE_PROT_VIOLATION) == SDMMC_OCR_WRITE_PROT_VIOLATION) + { + return SDMMC_ERROR_WRITE_PROT_VIOLATION; + } + else if((response_r1 & SDMMC_OCR_LOCK_UNLOCK_FAILED) == SDMMC_OCR_LOCK_UNLOCK_FAILED) + { + return SDMMC_ERROR_LOCK_UNLOCK_FAILED; + } + else if((response_r1 & SDMMC_OCR_COM_CRC_FAILED) == SDMMC_OCR_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else if((response_r1 & SDMMC_OCR_ILLEGAL_CMD) == SDMMC_OCR_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_FAILED) == SDMMC_OCR_CARD_ECC_FAILED) + { + return SDMMC_ERROR_CARD_ECC_FAILED; + } + else if((response_r1 & SDMMC_OCR_CC_ERROR) == SDMMC_OCR_CC_ERROR) + { + return SDMMC_ERROR_CC_ERR; + } + else if((response_r1 & SDMMC_OCR_STREAM_READ_UNDERRUN) == SDMMC_OCR_STREAM_READ_UNDERRUN) + { + return SDMMC_ERROR_STREAM_READ_UNDERRUN; + } + else if((response_r1 & SDMMC_OCR_STREAM_WRITE_OVERRUN) == SDMMC_OCR_STREAM_WRITE_OVERRUN) + { + return SDMMC_ERROR_STREAM_WRITE_OVERRUN; + } + else if((response_r1 & SDMMC_OCR_CID_CSD_OVERWRITE) == SDMMC_OCR_CID_CSD_OVERWRITE) + { + return SDMMC_ERROR_CID_CSD_OVERWRITE; + } + else if((response_r1 & SDMMC_OCR_WP_ERASE_SKIP) == SDMMC_OCR_WP_ERASE_SKIP) + { + return SDMMC_ERROR_WP_ERASE_SKIP; + } + else if((response_r1 & SDMMC_OCR_CARD_ECC_DISABLED) == SDMMC_OCR_CARD_ECC_DISABLED) + { + return SDMMC_ERROR_CARD_ECC_DISABLED; + } + else if((response_r1 & SDMMC_OCR_ERASE_RESET) == SDMMC_OCR_ERASE_RESET) + { + return SDMMC_ERROR_ERASE_RESET; + } + else if((response_r1 & SDMMC_OCR_AKE_SEQ_ERROR) == SDMMC_OCR_AKE_SEQ_ERROR) + { + return SDMMC_ERROR_AKE_SEQ_ERR; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R2 (CID or CSD) response. + * @param SDMMCx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* No error flag set */ + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R3 (OCR) response. + * @param SDMMCx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + { + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + } + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R6 (RCA) response. + * @param SDMMCx Pointer to SDMMC register base + * @param SD_CMD: The sent command index + * @param pRCA: Pointer to the variable that will contain the SD card relative + * address RCA + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA) +{ + uint32_t response_r1; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Check response received is of desired command */ + if(SDMMC_GetCommandResponse(SDMMCx) != SD_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + response_r1 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if((response_r1 & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED)) == SDMMC_ALLZERO) + { + *pRCA = (uint16_t) (response_r1 >> 16); + + return SDMMC_ERROR_NONE; + } + else if((response_r1 & SDMMC_R6_ILLEGAL_CMD) == SDMMC_R6_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if((response_r1 & SDMMC_R6_COM_CRC_FAILED) == SDMMC_R6_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + +/** + * @brief Checks for error conditions for R7 response. + * @param SDMMCx Pointer to SDMMC register base + * @retval SD Card error state + */ +uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx) +{ + uint32_t sta_reg; + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + }while(((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U )); + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + if(__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDREND)) + { + /* Card is SD V2.0 compliant */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CMDREND); + } + + return SDMMC_ERROR_NONE; + +} + +/** + * @} + */ + +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Checks for error conditions for CMD0. + * @param SDMMCx Pointer to SDMMC register base + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CMDSENT)); + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + return SDMMC_ERROR_NONE; +} + + +/** + * @} + */ + +#endif /* HAL_SD_MODULE_ENABLED || HAL_MMC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +#endif /* SDMMC1 */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c deleted file mode 100644 index 718c038c..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c +++ /dev/null @@ -1,577 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_spi.c - * @author MCD Application Team - * @brief SPI LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_spi.h" -#include "stm32f7xx_ll_bus.h" -#include "stm32f7xx_ll_rcc.h" - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) - -/** @addtogroup SPI_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SPI_LL_Private_Constants SPI Private Constants - * @{ - */ -/* SPI registers Masks */ -#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ - SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ - SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \ - SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ - SPI_CR1_BIDIMODE) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SPI_LL_Private_Macros SPI Private Macros - * @{ - */ -#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ - || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) - -#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ - || ((__VALUE__) == LL_SPI_MODE_SLAVE)) - -#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) - -#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ - || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) - -#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ - || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) - -#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) - -#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) - -#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ - || ((__VALUE__) == LL_SPI_MSB_FIRST)) - -#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ - || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) - -#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPI_LL_Exported_Functions - * @{ - */ - -/** @addtogroup SPI_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the SPI registers to their default reset values. - * @param SPIx SPI Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: SPI registers are de-initialized - * - ERROR: SPI registers are not de-initialized - */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_INSTANCE(SPIx)); - -#if defined(SPI1) - if (SPIx == SPI1) - { - /* Force reset of SPI clock */ - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); - - /* Release reset of SPI clock */ - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); - - status = SUCCESS; - } -#endif /* SPI1 */ -#if defined(SPI2) - if (SPIx == SPI2) - { - /* Force reset of SPI clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); - - /* Release reset of SPI clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); - - status = SUCCESS; - } -#endif /* SPI2 */ -#if defined(SPI3) - if (SPIx == SPI3) - { - /* Force reset of SPI clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); - - /* Release reset of SPI clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); - - status = SUCCESS; - } -#endif /* SPI3 */ -#if defined(SPI4) - if (SPIx == SPI4) - { - /* Force reset of SPI clock */ - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); - - /* Release reset of SPI clock */ - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); - - status = SUCCESS; - } -#endif /* SPI4 */ -#if defined(SPI5) - if (SPIx == SPI5) - { - /* Force reset of SPI clock */ - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); - - /* Release reset of SPI clock */ - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); - - status = SUCCESS; - } -#endif /* SPI5 */ -#if defined(SPI6) - if (SPIx == SPI6) - { - /* Force reset of SPI clock */ - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6); - - /* Release reset of SPI clock */ - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6); - - status = SUCCESS; - } -#endif /* SPI6 */ - - return status; -} - -/** - * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @param SPIx SPI Instance - * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure - * @retval An ErrorStatus enumeration value. (Return always SUCCESS) - */ -ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the SPI Instance SPIx*/ - assert_param(IS_SPI_ALL_INSTANCE(SPIx)); - - /* Check the SPI parameters from SPI_InitStruct*/ - assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); - assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); - assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); - assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); - assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); - assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); - assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); - assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); - assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); - - if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) - { - /*---------------------------- SPIx CR1 Configuration ------------------------ - * Configure SPIx CR1 with parameters: - * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits - * - Master/Slave Mode: SPI_CR1_MSTR bit - * - ClockPolarity: SPI_CR1_CPOL bit - * - ClockPhase: SPI_CR1_CPHA bit - * - NSS management: SPI_CR1_SSM bit - * - BaudRate prescaler: SPI_CR1_BR[2:0] bits - * - BitOrder: SPI_CR1_LSBFIRST bit - * - CRCCalculation: SPI_CR1_CRCEN bit - */ - MODIFY_REG(SPIx->CR1, - SPI_CR1_CLEAR_MASK, - SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | - SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | - SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | - SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); - - /*---------------------------- SPIx CR2 Configuration ------------------------ - * Configure SPIx CR2 with parameters: - * - DataWidth: DS[3:0] bits - * - NSS management: SSOE bit - */ - MODIFY_REG(SPIx->CR2, - SPI_CR2_DS | SPI_CR2_SSOE, - SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U)); - - /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ - if (SPI_InitStruct->DataWidth < LL_SPI_DATAWIDTH_9BIT) - { - LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); - } - - /*---------------------------- SPIx CRCPR Configuration ---------------------- - * Configure SPIx CRCPR with parameters: - * - CRCPoly: CRCPOLY[15:0] bits - */ - if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) - { - assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); - LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); - } - status = SUCCESS; - } - - /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ - CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); - return status; -} - -/** - * @brief Set each @ref LL_SPI_InitTypeDef field to default value. - * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) -{ - /* Set SPI_InitStruct fields to default values */ - SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; - SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; - SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; - SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; - SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; - SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; - SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; - SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; - SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; - SPI_InitStruct->CRCPoly = 7U; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2S_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2S_LL_Private_Constants I2S Private Constants - * @{ - */ -/* I2S registers Masks */ -#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ - SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ - SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) - -#define I2S_I2SPR_CLEAR_MASK 0x0002U -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2S_LL_Private_Macros I2S Private Macros - * @{ - */ - -#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) - -#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ - || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) - -#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ - || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) - -#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ - || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) - -#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ - || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) - -#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ - && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ - || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) - -#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) - -#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ - || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2S_LL_Exported_Functions - * @{ - */ - -/** @addtogroup I2S_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the SPI/I2S registers to their default reset values. - * @param SPIx SPI Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: SPI registers are de-initialized - * - ERROR: SPI registers are not de-initialized - */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) -{ - return LL_SPI_DeInit(SPIx); -} - -/** - * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @param SPIx SPI Instance - * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: SPI registers are Initialized - * - ERROR: SPI registers are not Initialized - */ -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) -{ - uint32_t i2sdiv = 2U; - uint32_t i2sodd = 0U; - uint32_t packetlength = 1U; - uint32_t tmp; - uint32_t sourceclock; - ErrorStatus status = ERROR; - - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(SPIx)); - assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); - assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); - assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); - assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); - assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); - assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); - - if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) - { - /*---------------------------- SPIx I2SCFGR Configuration -------------------- - * Configure SPIx I2SCFGR with parameters: - * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit - * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits - * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits - * - ClockPolarity: SPI_I2SCFGR_CKPOL bit - */ - - /* Write to SPIx I2SCFGR */ - MODIFY_REG(SPIx->I2SCFGR, - I2S_I2SCFGR_CLEAR_MASK, - I2S_InitStruct->Mode | I2S_InitStruct->Standard | - I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | - SPI_I2SCFGR_I2SMOD); - - /*---------------------------- SPIx I2SPR Configuration ---------------------- - * Configure SPIx I2SPR with parameters: - * - MCLKOutput: SPI_I2SPR_MCKOE bit - * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits - */ - - /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) - * else, default values are used: i2sodd = 0U, i2sdiv = 2U. - */ - if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) - { - /* Check the frame length (For the Prescaler computing) - * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). - */ - if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) - { - /* Packet length is 32 bits */ - packetlength = 2U; - } - - /* If an external I2S clock has to be used, the specific define should be set - in the project configuration or in the stm32f7xx_ll_rcc.h file */ - /* Get the I2S source clock value */ - sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE); - - /* Compute the Real divider depending on the MCLK output state with a floating point */ - if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) - { - /* MCLK output is enabled */ - tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); - } - else - { - /* MCLK output is disabled */ - tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); - } - - /* Remove the floating point */ - tmp = tmp / 10U; - - /* Check the parity of the divider */ - i2sodd = (tmp & (uint16_t)0x0001U); - - /* Compute the i2sdiv prescaler */ - i2sdiv = ((tmp - i2sodd) / 2U); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (i2sodd << 8U); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) - { - /* Set the default values */ - i2sdiv = 2U; - i2sodd = 0U; - } - - /* Write to SPIx I2SPR register the computed value */ - WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); - - status = SUCCESS; - } - return status; -} - -/** - * @brief Set each @ref LL_I2S_InitTypeDef field to default value. - * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) -{ - /*--------------- Reset I2S init structure parameters values -----------------*/ - I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; - I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; - I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; - I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; - I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; - I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; -} - -/** - * @brief Set linear and parity prescaler. - * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n - * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). - * @param SPIx SPI Instance - * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. - * @param PrescalerParity This parameter can be one of the following values: - * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN - * @arg @ref LL_I2S_PRESCALER_PARITY_ODD - * @retval None - */ -void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) -{ - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(SPIx)); - assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); - assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); - - /* Write to SPIx I2SPR */ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c deleted file mode 100644 index 1e69b77c..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c +++ /dev/null @@ -1,1380 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_tim.c - * @author MCD Application Team - * @brief TIM LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_tim.h" -#include "stm32f7xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7) - -/** @addtogroup TIM_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup TIM_LL_Private_Macros - * @{ - */ -#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) - -#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) - -#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ - || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_ASYMMETRIC_PWM2)) - -#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ - || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) - -#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ - || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) - -#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ - || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) - -#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) - -#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) - -#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) - -#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) - -#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) - -#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) - -#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) - -#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) - -#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) - -#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) - -#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) - -#define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8)) - -#define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK2_ENABLE)) - -#define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH)) - -#define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8)) - -#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ - || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) -/** - * @} - */ - - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup TIM_LL_Private_Functions TIM Private Functions - * @{ - */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_LL_Exported_Functions - * @{ - */ - -/** @addtogroup TIM_LL_EF_Init - * @{ - */ - -/** - * @brief Set TIMx registers to their reset values. - * @param TIMx Timer instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: invalid TIMx instance - */ -ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) -{ - ErrorStatus result = SUCCESS; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(TIMx)); - - if (TIMx == TIM1) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); - } - else if (TIMx == TIM2) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); - } -#if defined(TIM3) - else if (TIMx == TIM3) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); - } -#endif /* TIM3 */ -#if defined(TIM4) - else if (TIMx == TIM4) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); - } -#endif /* TIM4 */ -#if defined(TIM5) - else if (TIMx == TIM5) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); - } -#endif /* TIM5 */ -#if defined(TIM6) - else if (TIMx == TIM6) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); - } -#endif /* TIM6 */ -#if defined (TIM7) - else if (TIMx == TIM7) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); - } -#endif /* TIM7 */ -#if defined(TIM8) - else if (TIMx == TIM8) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); - } -#endif /* TIM8 */ -#if defined(TIM9) - else if (TIMx == TIM9) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); - } -#endif /* TIM9 */ -#if defined(TIM10) - else if (TIMx == TIM10) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); - } -#endif /* TIM10 */ -#if defined(TIM11) - else if (TIMx == TIM11) - { - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); - } -#endif /* TIM11 */ -#if defined(TIM12) - else if (TIMx == TIM12) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); - } -#endif /* TIM12 */ -#if defined(TIM13) - else if (TIMx == TIM13) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); - } -#endif /* TIM13 */ -#if defined(TIM14) - else if (TIMx == TIM14) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); - } -#endif /* TIM14 */ - else - { - result = ERROR; - } - - return result; -} - -/** - * @brief Set the fields of the time base unit configuration data structure - * to their default values. - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) - * @retval None - */ -void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) -{ - /* Set the default configuration */ - TIM_InitStruct->Prescaler = (uint16_t)0x0000; - TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; - TIM_InitStruct->Autoreload = 0xFFFFFFFFU; - TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = 0x00000000U; -} - -/** - * @brief Configure the TIMx time base unit. - * @param TIMx Timer Instance - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure - * (TIMx time base unit configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) -{ - uint32_t tmpcr1; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); - assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); - - tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); - - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); - } - - if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); - } - - /* Write to TIMx CR1 */ - LL_TIM_WriteReg(TIMx, CR1, tmpcr1); - - /* Set the Autoreload value */ - LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); - - /* Set the Prescaler value */ - LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); - } - - /* Generate an update event to reload the Prescaler - and the repetition counter value (if applicable) immediately */ - LL_TIM_GenerateEvent_UPDATE(TIMx); - - return SUCCESS; -} - -/** - * @brief Set the fields of the TIMx output channel configuration data - * structure to their default values. - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure - * (the output channel configuration data structure) - * @retval None - */ -void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) -{ - /* Set the default configuration */ - TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; - TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; - TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; - TIM_OC_InitStruct->CompareValue = 0x00000000U; - TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; - TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; - TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; - TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; -} - -/** - * @brief Configure the TIMx output channel. - * @param TIMx Timer Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @arg @ref LL_TIM_CHANNEL_CH5 - * @arg @ref LL_TIM_CHANNEL_CH6 - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration - * data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx output channel is initialized - * - ERROR: TIMx output channel is not initialized - */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) -{ - ErrorStatus result = ERROR; - - switch (Channel) - { - case LL_TIM_CHANNEL_CH1: - result = OC1Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH2: - result = OC2Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH3: - result = OC3Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH4: - result = OC4Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH5: - result = OC5Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH6: - result = OC6Config(TIMx, TIM_OC_InitStruct); - break; - default: - break; - } - - return result; -} - -/** - * @brief Set the fields of the TIMx input channel configuration data - * structure to their default values. - * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration - * data structure) - * @retval None - */ -void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; - TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; - TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; -} - -/** - * @brief Configure the TIMx input channel. - * @param TIMx Timer Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data - * structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx output channel is initialized - * - ERROR: TIMx output channel is not initialized - */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) -{ - ErrorStatus result = ERROR; - - switch (Channel) - { - case LL_TIM_CHANNEL_CH1: - result = IC1Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH2: - result = IC2Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH3: - result = IC3Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH4: - result = IC4Config(TIMx, TIM_IC_InitStruct); - break; - default: - break; - } - - return result; -} - -/** - * @brief Fills each TIM_EncoderInitStruct field with its default value - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface - * configuration data structure) - * @retval None - */ -void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) -{ - /* Set the default configuration */ - TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; - TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; - TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; - TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; - TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; -} - -/** - * @brief Configure the encoder interface of the timer instance. - * @param TIMx Timer Instance - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface - * configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); - - /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ - TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Configure TI1 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); - - /* Configure TI2 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); - - /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ - tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Set encoder mode */ - LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Set the fields of the TIMx Hall sensor interface configuration data - * structure to their default values. - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface - * configuration data structure) - * @retval None - */ -void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) -{ - /* Set the default configuration */ - TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; - TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; - TIM_HallSensorInitStruct->CommutationDelay = 0U; -} - -/** - * @brief Configure the Hall sensor interface of the timer instance. - * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR - * to the TI1 input channel - * @note TIMx slave mode controller is configured in reset mode. - Selected internal trigger is TI1F_ED. - * @note Channel 1 is configured as input, IC1 is mapped on TRC. - * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed - * between 2 changes on the inputs. It gives information about motor speed. - * @note Channel 2 is configured in output PWM 2 mode. - * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. - * @note OC2REF is selected as trigger output on TRGO. - * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used - * when TIMx operates in Hall sensor interface mode. - * @param TIMx Timer Instance - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor - * interface configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) -{ - uint32_t tmpcr2; - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); - assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); - - /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ - TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx SMCR register value */ - tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); - - /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ - tmpcr2 |= TIM_CR2_TI1S; - - /* OC2REF signal is used as trigger output (TRGO) */ - tmpcr2 |= LL_TIM_TRGO_OC2REF; - - /* Configure the slave mode controller */ - tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); - tmpsmcr |= LL_TIM_TS_TI1F_ED; - tmpsmcr |= LL_TIM_SLAVEMODE_RESET; - - /* Configure input channel 1 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); - tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); - tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); - tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); - - /* Configure input channel 2 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); - tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); - - /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ - tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx SMCR */ - LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - /* Write to TIMx CCR2 */ - LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); - - return SUCCESS; -} - -/** - * @brief Set the fields of the Break and Dead Time configuration data structure - * to their default values. - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration - * data structure) - * @retval None - */ -void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; - TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; - TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; - TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; - TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; - TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; - TIM_BDTRInitStruct->BreakFilter = LL_TIM_BREAK_FILTER_FDIV1; - TIM_BDTRInitStruct->Break2State = LL_TIM_BREAK2_DISABLE; - TIM_BDTRInitStruct->Break2Polarity = LL_TIM_BREAK2_POLARITY_LOW; - TIM_BDTRInitStruct->Break2Filter = LL_TIM_BREAK2_FILTER_FDIV1; - TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; -} - -/** - * @brief Configure the Break and Dead Time feature of the timer instance. - * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR - * and DTG[7:0] can be write-locked depending on the LOCK configuration, it - * can be necessary to configure all of them during the first write access to - * the TIMx_BDTR register. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a second break input. - * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration - * data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Break and Dead Time is initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) -{ - uint32_t tmpbdtr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); - assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); - assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); - assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); - assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); - assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); - assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter); - - if (IS_TIM_BKIN2_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State)); - assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity)); - assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter)); - - /* Set the BREAK2 input related BDTR bit-fields */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity); - } - - /* Set TIMx_BDTR */ - LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); - - return SUCCESS; -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup TIM_LL_Private_Functions TIM Private Functions - * @brief Private functions - * @{ - */ -/** - * @brief Configure the TIMx output channel 1. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); - - /* Set the Output Compare Mode */ - MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 2. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 3. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - - /* Disable the Channel 3: Reset the CC3E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR2 */ - LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 4. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR2 */ - LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 5. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr3; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - - /* Disable the Channel 5: Reset the CC5E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CCMR3 register value */ - tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the Output Idle state */ - MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U); - - } - - /* Write to TIMx CCMR3 */ - LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 6. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr3; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - - /* Disable the Channel 5: Reset the CC6E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CCMR3 register value */ - tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the Output Idle state */ - MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U); - } - - /* Write to TIMx CCMR3 */ - LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 1. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR1, - (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); - - /* Select the Polarity and set the CC1E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC1P | TIM_CCER_CC1NP), - (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 2. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR1, - (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - - /* Select the Polarity and set the CC2E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC2P | TIM_CCER_CC2NP), - ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 3. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR2, - (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); - - /* Select the Polarity and set the CC3E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC3P | TIM_CCER_CC3NP), - ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 4. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR2, - (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - - /* Select the Polarity and set the CC4E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC4P | TIM_CCER_CC4NP), - ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); - - return SUCCESS; -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c deleted file mode 100644 index 8e341123..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c +++ /dev/null @@ -1,451 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_usart.c - * @author MCD Application Team - * @brief USART LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_usart.h" -#include "stm32f7xx_ll_rcc.h" -#include "stm32f7xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -#if defined(USART1) || defined(USART2) || defined(USART3) || defined(USART6) \ - || defined(UART4) || defined(UART5) || defined(UART7) || defined(UART8) - -/** @addtogroup USART_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Constants - * @{ - */ - -/* Definition of default baudrate value used for USART initialisation */ -#define USART_DEFAULT_BAUDRATE (9600U) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Macros - * @{ - */ - -/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available - * divided by the smallest oversampling used on the USART (i.e. 8) */ -#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U) - -/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ -#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) - -#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) - -#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) - -#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) - -#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) - -#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) - -#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) - -#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) - -#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) - -#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) - -#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USART_LL_Exported_Functions - * @{ - */ - -/** @addtogroup USART_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize USART registers (Registers restored to their default values). - * @param USARTx USART Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers are de-initialized - * - ERROR: USART registers are not de-initialized - */ -ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - - if (USARTx == USART1) - { - /* Force reset of USART clock */ - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1); - - /* Release reset of USART clock */ - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1); - } - else if (USARTx == USART2) - { - /* Force reset of USART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); - - /* Release reset of USART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); - } - else if (USARTx == USART3) - { - /* Force reset of USART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3); - - /* Release reset of USART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3); - } - else if (USARTx == UART4) - { - /* Force reset of UART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4); - - /* Release reset of UART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4); - } - else if (USARTx == UART5) - { - /* Force reset of UART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5); - - /* Release reset of UART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5); - } - else if (USARTx == USART6) - { - /* Force reset of USART clock */ - LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6); - - /* Release reset of USART clock */ - LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6); - } - else if (USARTx == UART7) - { - /* Force reset of UART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7); - - /* Release reset of UART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7); - } - else if (USARTx == UART8) - { - /* Force reset of UART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8); - - /* Release reset of UART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8); - } - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize USART registers according to the specified - * parameters in USART_InitStruct. - * @note As some bits in USART configuration registers can only be written when - * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling - * this function. Otherwise, ERROR result will be returned. - * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). - * @param USARTx USART Instance - * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure - * that contains the configuration information for the specified USART peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers are initialized according to USART_InitStruct content - * - ERROR: Problem occurred during USART Registers initialization - */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) -{ - ErrorStatus status = ERROR; - uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); - assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); - assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); - assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); - assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); - assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); - assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); - - /* USART needs to be in disabled state, in order to be able to configure some bits in - CRx registers */ - if (LL_USART_IsEnabled(USARTx) == 0U) - { - /*---------------------------- USART CR1 Configuration --------------------- - * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: - * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value - * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value - * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value - * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value. - */ - MODIFY_REG(USARTx->CR1, - (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | - USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), - (USART_InitStruct->DataWidth | USART_InitStruct->Parity | - USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling)); - - /*---------------------------- USART CR2 Configuration --------------------- - * Configure USARTx CR2 (Stop bits) with parameters: - * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. - * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). - */ - LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); - - /*---------------------------- USART CR3 Configuration --------------------- - * Configure USARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to - * USART_InitStruct->HardwareFlowControl value. - */ - LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); - - /*---------------------------- USART BRR Configuration --------------------- - * Retrieve Clock frequency used for USART Peripheral - */ - if (USARTx == USART1) - { - periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE); - } - else if (USARTx == USART2) - { - periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE); - } - else if (USARTx == USART3) - { - periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE); - } - else if (USARTx == UART4) - { - periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE); - } - else if (USARTx == UART5) - { - periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE); - } - else if (USARTx == USART6) - { - periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE); - } - else if (USARTx == UART7) - { - periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE); - } - else if (USARTx == UART8) - { - periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART8_CLKSOURCE); - } - else - { - /* Nothing to do, as error code is already assigned to ERROR value */ - } - - /* Configure the USART Baud Rate : - - valid baud rate value (different from 0) is required - - Peripheral clock as returned by RCC service, should be valid (different from 0). - */ - if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) - && (USART_InitStruct->BaudRate != 0U)) - { - status = SUCCESS; - LL_USART_SetBaudRate(USARTx, - periphclk, - USART_InitStruct->OverSampling, - USART_InitStruct->BaudRate); - - /* Check BRR is greater than or equal to 16d */ - assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - } - } - /* Endif (=> USART not in Disabled state => return ERROR) */ - - return (status); -} - -/** - * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) -{ - /* Set USART_InitStruct fields to default values */ - USART_InitStruct->BaudRate = USART_DEFAULT_BAUDRATE; - USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; - USART_InitStruct->StopBits = LL_USART_STOPBITS_1; - USART_InitStruct->Parity = LL_USART_PARITY_NONE ; - USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; - USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; - USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; -} - -/** - * @brief Initialize USART Clock related settings according to the - * specified parameters in the USART_ClockInitStruct. - * @note As some bits in USART configuration registers can only be written when - * the USART is disabled (USART_CR1_UE bit =0), USART Peripheral should be in disabled state prior calling - * this function. Otherwise, ERROR result will be returned. - * @param USARTx USART Instance - * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure - * that contains the Clock configuration information for the specified USART peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers related to Clock settings are initialized according - * to USART_ClockInitStruct content - * - ERROR: Problem occurred during USART Registers initialization - */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check USART Instance and Clock signal output parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); - - /* USART needs to be in disabled state, in order to be able to configure some bits in - CRx registers */ - if (LL_USART_IsEnabled(USARTx) == 0U) - { - /* If USART Clock signal is disabled */ - if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) - { - /* Deactivate Clock signal delivery : - * - Disable Clock Output: USART_CR2_CLKEN cleared - */ - LL_USART_DisableSCLKOutput(USARTx); - } - else - { - /* Ensure USART instance is USART capable */ - assert_param(IS_USART_INSTANCE(USARTx)); - - /* Check clock related parameters */ - assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); - assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); - assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); - - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Clock signal related bits) with parameters: - * - Enable Clock Output: USART_CR2_CLKEN set - * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value - * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value - * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. - */ - MODIFY_REG(USARTx->CR2, - USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, - USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | - USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); - } - } - /* Else (USART not in Disabled state => return ERROR */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - /* Set LL_USART_ClockInitStruct fields with default values */ - USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; - USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = - LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = - LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = - LL_USART_CLOCK_DISABLE */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - - diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c index 12c9ede7..9b4673d9 100644 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c +++ b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c @@ -1,2396 +1,2403 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_usb.c - * @author MCD Application Team - * @brief USB Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Fill parameters of Init structure in USB_CfgTypeDef structure. - - (#) Call USB_CoreInit() API to initialize the USB Core peripheral. - - (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. - - @endverbatim - - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_hal.h" - -/** @addtogroup STM32F7xx_LL_USB_DRIVER - * @{ - */ - -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); -#ifdef USBPHYC -static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); -#endif /* USBPHYC */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions - * @{ - */ - -/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the USB Core - * @param USBx USB Instance - * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - HAL_StatusTypeDef ret; - - if (cfg.phy_itface == USB_OTG_ULPI_PHY) - { - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); - - /* Init The ULPI Interface */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); - -#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) \ - || defined(STM32F732xx) || defined(STM32F733xx) - /* Select ULPI Interface */ - USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL; -#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || - defined(STM32F732xx) || defined(STM32F733xx) */ - - /* Select vbus source */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); - if (cfg.use_external_vbus == 1U) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; - } - - /* Reset after a PHY select */ - ret = USB_CoreReset(USBx); - } -#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) \ - || defined(STM32F732xx) || defined(STM32F733xx) - else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) - { - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); - - /* Init The UTMI Interface */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); - - /* Select vbus source */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); - - /* Select UTMI Interface */ - USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; -#ifdef USBPHYC - /* Enable USB HS PHY */ - USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN; - - /* Enables control of a High Speed USB PHY */ - if (USB_HS_PHYCInit(USBx) != HAL_OK) - { - return HAL_ERROR; - } -#endif /* USBPHYC */ - - if (cfg.use_external_vbus == 1U) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; - } - - /* Reset after a PHY select */ - ret = USB_CoreReset(USBx); - } -#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || - defined(STM32F732xx) || defined(STM32F733xx) */ - else /* FS interface (embedded Phy) */ - { - /* Select FS Embedded PHY */ - USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - - /* Reset after a PHY select */ - ret = USB_CoreReset(USBx); - - /* Activate the USB Transceiver */ - USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; - } - - if (cfg.dma_enable == 1U) - { - USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; - USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; - } - - return ret; -} - - -/** - * @brief Set the USB turnaround time - * @param USBx USB Instance - * @param hclk: AHB clock frequency - * @retval USB turnaround time In PHY Clocks number - */ -HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, - uint32_t hclk, uint8_t speed) -{ - uint32_t UsbTrd; - - /* The USBTRD is configured according to the tables below, depending on AHB frequency - used by application. In the low AHB frequency range it is used to stretch enough the USB response - time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access - latency to the Data FIFO */ - if (speed == USBD_FS_SPEED) - { - if ((hclk >= 14200000U) && (hclk < 15000000U)) - { - /* hclk Clock Range between 14.2-15 MHz */ - UsbTrd = 0xFU; - } - else if ((hclk >= 15000000U) && (hclk < 16000000U)) - { - /* hclk Clock Range between 15-16 MHz */ - UsbTrd = 0xEU; - } - else if ((hclk >= 16000000U) && (hclk < 17200000U)) - { - /* hclk Clock Range between 16-17.2 MHz */ - UsbTrd = 0xDU; - } - else if ((hclk >= 17200000U) && (hclk < 18500000U)) - { - /* hclk Clock Range between 17.2-18.5 MHz */ - UsbTrd = 0xCU; - } - else if ((hclk >= 18500000U) && (hclk < 20000000U)) - { - /* hclk Clock Range between 18.5-20 MHz */ - UsbTrd = 0xBU; - } - else if ((hclk >= 20000000U) && (hclk < 21800000U)) - { - /* hclk Clock Range between 20-21.8 MHz */ - UsbTrd = 0xAU; - } - else if ((hclk >= 21800000U) && (hclk < 24000000U)) - { - /* hclk Clock Range between 21.8-24 MHz */ - UsbTrd = 0x9U; - } - else if ((hclk >= 24000000U) && (hclk < 27700000U)) - { - /* hclk Clock Range between 24-27.7 MHz */ - UsbTrd = 0x8U; - } - else if ((hclk >= 27700000U) && (hclk < 32000000U)) - { - /* hclk Clock Range between 27.7-32 MHz */ - UsbTrd = 0x7U; - } - else /* if(hclk >= 32000000) */ - { - /* hclk Clock Range between 32-200 MHz */ - UsbTrd = 0x6U; - } - } - else if (speed == USBD_HS_SPEED) - { - UsbTrd = USBD_HS_TRDT_VALUE; - } - else - { - UsbTrd = USBD_DEFAULT_TRDT_VALUE; - } - - USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); - - return HAL_OK; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode Set functional mode - * @param USBx Selected device - * @param mode current core mode - * This parameter can be one of these values: - * @arg USB_DEVICE_MODE Peripheral mode - * @arg USB_HOST_MODE Host mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) -{ - uint32_t ms = 0U; - - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - - if (mode == USB_HOST_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; - - do - { - HAL_Delay(10U); - ms += 10U; - } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); - } - else if (mode == USB_DEVICE_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; - - do - { - HAL_Delay(10U); - ms += 10U; - } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); - } - else - { - return HAL_ERROR; - } - - if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief USB_DevInit Initializes the USB_OTG controller registers - * for device mode - * @param USBx Selected device - * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i; - - for (i = 0U; i < 15U; i++) - { - USBx->DIEPTXF[i] = 0U; - } - - /* VBUS Sensing setup */ - if (cfg.vbus_sensing_enable == 0U) - { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; - - /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; - - /* B-peripheral session valid override enable */ - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; - } - else - { - /* Enable HW VBUS sensing */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - } - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0U; - - if (cfg.phy_itface == USB_OTG_ULPI_PHY) - { - if (cfg.speed == USBD_HS_SPEED) - { - /* Set Core speed to High speed mode */ - (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); - } - else - { - /* Set Core speed to Full speed mode */ - (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); - } - } -#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) \ - || defined(STM32F732xx) || defined(STM32F733xx) - else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) - { - if (cfg.speed == USBD_HS_SPEED) - { - /* Set Core speed to High speed mode */ - (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); - } - else - { - /* Set Core speed to Full speed mode */ - (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); - } - } -#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || - defined(STM32F732xx) || defined(STM32F733xx) */ - else - { - /* Set Core speed to Full speed mode */ - (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); - } - - /* Flush the FIFOs */ - if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ - { - ret = HAL_ERROR; - } - - if (USB_FlushRxFifo(USBx) != HAL_OK) - { - ret = HAL_ERROR; - } - - /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0U; - USBx_DEVICE->DOEPMSK = 0U; - USBx_DEVICE->DAINTMSK = 0U; - - for (i = 0U; i < cfg.dev_endpoints; i++) - { - if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - if (i == 0U) - { - USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; - } - else - { - USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; - } - } - else - { - USBx_INEP(i)->DIEPCTL = 0U; - } - - USBx_INEP(i)->DIEPTSIZ = 0U; - USBx_INEP(i)->DIEPINT = 0xFB7FU; - } - - for (i = 0U; i < cfg.dev_endpoints; i++) - { - if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - if (i == 0U) - { - USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; - } - else - { - USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; - } - } - else - { - USBx_OUTEP(i)->DOEPCTL = 0U; - } - - USBx_OUTEP(i)->DOEPTSIZ = 0U; - USBx_OUTEP(i)->DOEPINT = 0xFB7FU; - } - - USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - - /* Disable all interrupts. */ - USBx->GINTMSK = 0U; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFFU; - - /* Enable the common interrupts */ - if (cfg.dma_enable == 0U) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; - - if (cfg.Sof_enable != 0U) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; - } - - if (cfg.vbus_sensing_enable == 1U) - { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); - } - - return ret; -} - -/** - * @brief USB_FlushTxFifo Flush a Tx FIFO - * @param USBx Selected device - * @param num FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) -{ - __IO uint32_t count = 0U; - - /* Wait for AHB master IDLE state. */ - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); - - /* Flush TX Fifo */ - count = 0U; - USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); - - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo Flush Rx FIFO - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t count = 0U; - - /* Wait for AHB master IDLE state. */ - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); - - /* Flush RX Fifo */ - count = 0U; - USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - - return HAL_OK; -} - -/** - * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register - * depending the PHY type and the enumeration speed of the device. - * @param USBx Selected device - * @param speed device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @retval Hal status - */ -HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - USBx_DEVICE->DCFG |= speed; - return HAL_OK; -} - -/** - * @brief USB_GetDevSpeed Return the Dev Speed - * @param USBx Selected device - * @retval speed device speed - * This parameter can be one of these values: - * @arg USBD_HS_SPEED: High speed mode - * @arg USBD_FS_SPEED: Full speed mode - */ -uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint8_t speed; - uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; - - if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) - { - speed = USBD_HS_SPEED; - } - else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || - (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) - { - speed = USBD_FS_SPEED; - } - else - { - speed = 0xFU; - } - - return speed; -} - -/** - * @brief Activate and configure an endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); - - if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | - ((uint32_t)ep->type << 18) | (epnum << 22) | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DIEPCTL_USBAEP; - } - } - else - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); - - if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) - { - USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | - ((uint32_t)ep->type << 18) | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DOEPCTL_USBAEP; - } - } - return HAL_OK; -} - -/** - * @brief Activate and configure a dedicated endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* Read DEPCTLn register */ - if (ep->is_in == 1U) - { - if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | - ((uint32_t)ep->type << 18) | (epnum << 22) | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DIEPCTL_USBAEP; - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); - } - else - { - if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) - { - USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | - ((uint32_t)ep->type << 18) | (epnum << 22) | - USB_OTG_DOEPCTL_USBAEP; - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); - } - - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* Read DEPCTLn register */ - if (ep->is_in == 1U) - { - if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; - } - - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); - USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | - USB_OTG_DIEPCTL_MPSIZ | - USB_OTG_DIEPCTL_TXFNUM | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DIEPCTL_EPTYP); - } - else - { - if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; - } - - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); - USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | - USB_OTG_DOEPCTL_MPSIZ | - USB_OTG_DOEPCTL_SD0PID_SEVNFRM | - USB_OTG_DOEPCTL_EPTYP); - } - - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* Read DEPCTLn register */ - if (ep->is_in == 1U) - { - if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; - } - - USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); - } - else - { - if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; - } - - USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); - } - - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - uint16_t pktcnt; - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if (epnum == 0U) - { - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - } - else - { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); - } - - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } - } - - if (dma == 1U) - { - if ((uint32_t)ep->dma_addr != 0U) - { - USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - else - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else - { - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0U) - { - USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); - } - } - else - { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - else - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - - (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); - } - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (epnum == 0U) - { - if (ep->xfer_len > 0U) - { - ep->xfer_len = ep->maxpacket; - } - - /* Store transfer size, for EP0 this is equal to endpoint max packet size */ - ep->xfer_size = ep->maxpacket; - - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - } - else - { - if (ep->xfer_len == 0U) - { - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - } - else - { - pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); - ep->xfer_size = ep->maxpacket * pktcnt; - - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; - } - } - - if (dma == 1U) - { - if ((uint32_t)ep->xfer_buff != 0U) - { - USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); - } - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; - } - else - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - } - } - /* EP enable */ - USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - - return HAL_OK; -} - - -/** - * @brief USB_EPStoptXfer Stop transfer on an EP - * @param USBx usb device instance - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - __IO uint32_t count = 0U; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /* EP enable, IN data in FIFO */ - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); - - do - { - count++; - - if (count > 10000U) - { - ret = HAL_ERROR; - break; - } - } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); - } - } - else /* OUT endpoint */ - { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); - - do - { - count++; - - if (count > 10000U) - { - ret = HAL_ERROR; - break; - } - } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); - } - } - - return ret; -} - - -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx Selected device - * @param src pointer to source buffer - * @param ch_ep_num endpoint or host channel number - * @param len Number of bytes to write - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, - uint8_t ch_ep_num, uint16_t len, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint8_t *pSrc = src; - uint32_t count32b; - uint32_t i; - - if (dma == 0U) - { - count32b = ((uint32_t)len + 3U) / 4U; - for (i = 0U; i < count32b; i++) - { - USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); - pSrc++; - pSrc++; - pSrc++; - pSrc++; - } - } - - return HAL_OK; -} - -/** - * @brief USB_ReadPacket : read a packet from the RX FIFO - * @param USBx Selected device - * @param dest source pointer - * @param len Number of bytes to read - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint8_t *pDest = dest; - uint32_t pData; - uint32_t i; - uint32_t count32b = (uint32_t)len >> 2U; - uint16_t remaining_bytes = len % 4U; - - for (i = 0U; i < count32b; i++) - { - __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); - pDest++; - pDest++; - pDest++; - pDest++; - } - - /* When Number of data is not word aligned, read the remaining byte */ - if (remaining_bytes != 0U) - { - i = 0U; - __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); - - do - { - *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); - i++; - pDest++; - remaining_bytes--; - } while (remaining_bytes != 0U); - } - - return ((void *)pDest); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; - } - else - { - if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; - } - - return HAL_OK; -} - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - else - { - USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - return HAL_OK; -} - -/** - * @brief USB_StopDevice : Stop the usb device mode - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) -{ - HAL_StatusTypeDef ret; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i; - - /* Clear Pending interrupt */ - for (i = 0U; i < 15U; i++) - { - USBx_INEP(i)->DIEPINT = 0xFB7FU; - USBx_OUTEP(i)->DOEPINT = 0xFB7FU; - } - - /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0U; - USBx_DEVICE->DOEPMSK = 0U; - USBx_DEVICE->DAINTMSK = 0U; - - /* Flush the FIFO */ - ret = USB_FlushRxFifo(USBx); - if (ret != HAL_OK) - { - return ret; - } - - ret = USB_FlushTxFifo(USBx, 0x10U); - if (ret != HAL_OK) - { - return ret; - } - - return ret; -} - -/** - * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx Selected device - * @param address new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; - - return HAL_OK; -} - -/** - * @brief USB_DevConnect : Connect the USB device by enabling Rpu - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - /* In case phy is stopped, ensure to ungate and restore the phy CLK */ - USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); - - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - /* In case phy is stopped, ensure to ungate and restore the phy CLK */ - USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); - - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx Selected device - * @retval USB Global Interrupt status - */ -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) -{ - uint32_t tmpreg; - - tmpreg = USBx->GINTSTS; - tmpreg &= USBx->GINTMSK; - - return tmpreg; -} - -/** - * @brief USB_ReadChInterrupts: return USB channel interrupt status - * @param USBx Selected device - * @param chnum Channel number - * @retval USB Channel Interrupt status - */ -uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - tmpreg = USBx_HC(chnum)->HCINT; - tmpreg &= USBx_HC(chnum)->HCINTMSK; - - return tmpreg; -} - -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx Selected device - * @retval USB Device OUT EP interrupt status - */ -uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - tmpreg = USBx_DEVICE->DAINT; - tmpreg &= USBx_DEVICE->DAINTMSK; - - return ((tmpreg & 0xffff0000U) >> 16); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx Selected device - * @retval USB Device IN EP interrupt status - */ -uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - tmpreg = USBx_DEVICE->DAINT; - tmpreg &= USBx_DEVICE->DAINTMSK; - - return ((tmpreg & 0xFFFFU)); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx Selected device - * @param epnum endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; - tmpreg &= USBx_DEVICE->DOEPMSK; - - return tmpreg; -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx Selected device - * @param epnum endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - uint32_t msk; - uint32_t emp; - - msk = USBx_DEVICE->DIEPMSK; - emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; - tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; - - return tmpreg; -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx Selected device - * @param interrupt flag - * @retval None - */ -void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) -{ - USBx->GINTSTS &= interrupt; -} - -/** - * @brief Returns USB core mode - * @param USBx Selected device - * @retval return core mode : Host or Device - * This parameter can be one of these values: - * 0 : Host - * 1 : Device - */ -uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) -{ - return ((USBx->GINTSTS) & 0x1U); -} - -/** - * @brief Activate EP0 for Setup transactions - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - /* Set the MPS of the IN EP0 to 64 bytes */ - USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - - USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; - - return HAL_OK; -} - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx Selected device - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @param psetup pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); - - if (gSNPSiD > USB_OTG_CORE_ID_300A) - { - if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - return HAL_OK; - } - } - - USBx_OUTEP(0U)->DOEPTSIZ = 0U; - USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); - USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - - if (dma == 1U) - { - USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; - /* EP enable */ - USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; - } - - return HAL_OK; -} - -/** - * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t count = 0U; - - /* Wait for AHB master IDLE state. */ - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); - - /* Core Soft Reset */ - count = 0U; - USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - - return HAL_OK; -} - -#ifdef USBPHYC -/** - * @brief Enables control of a High Speed USB PHY - * Init the low level hardware : GPIO, CLOCK, NVIC... - * @param USBx Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) -{ - UNUSED(USBx); - __IO uint32_t count = 0U; - - /* Enable LDO */ - USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; - - /* wait for LDO Ready */ - while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U) - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } - - /* Controls PHY frequency operation selection */ - if (HSE_VALUE == PHYC_12_MHZ) /* HSE = 12MHz */ - { - USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1); - } - else if (HSE_VALUE == PHYC_12_5_MHZ) /* HSE = 12.5MHz */ - { - USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1); - } - else if (HSE_VALUE == PHYC_16_MHZ) /* HSE = 16MHz */ - { - USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1); - } - else if (HSE_VALUE == PHYC_24_MHZ) /* HSE = 24MHz */ - { - USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1); - } - else if (HSE_VALUE == PHYC_25_MHZ) /* HSE = 25MHz */ - { - USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1); - } - else if (HSE_VALUE == PHYC_32_MHZ) /* HSE = 32MHz */ - { - USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1); - } - else - { - /* ... */ - } - - /* Control the tuning interface of the High Speed PHY */ - USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE; - - /* Enable PLL internal PHY */ - USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; - - - /* 2ms Delay required to get internal phy clock stable */ - HAL_Delay(2U); - - return HAL_OK; -} - -#endif /* USBPHYC */ -/** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode - * @param USBx Selected device - * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i; - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0U; - - /* Disable VBUS sensing */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); - - if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) - { - if (cfg.speed == USBH_FSLS_SPEED) - { - /* Force Device Enumeration to FS/LS mode only */ - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; - } - else - { - /* Set default Max speed support */ - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); - } - } - else - { - /* Set default Max speed support */ - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); - } - - /* Make sure the FIFOs are flushed. */ - if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ - { - ret = HAL_ERROR; - } - - if (USB_FlushRxFifo(USBx) != HAL_OK) - { - ret = HAL_ERROR; - } - - /* Clear all pending HC Interrupts */ - for (i = 0U; i < cfg.Host_channels; i++) - { - USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; - USBx_HC(i)->HCINTMSK = 0U; - } - - /* Disable all interrupts. */ - USBx->GINTMSK = 0U; - - /* Clear any pending interrupts */ - USBx->GINTSTS = CLEAR_INTERRUPT_MASK; -#if defined (USB_OTG_HS) - if (USBx == USB_OTG_HS) - { - /* set Rx FIFO size */ - USBx->GRXFSIZ = 0x200U; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); - USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); - } - else -#endif /* defined (USB_OTG_HS) */ - { - /* set Rx FIFO size */ - USBx->GRXFSIZ = 0x80U; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); - USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); - } - - /* Enable the common interrupts */ - if (cfg.dma_enable == 0U) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Host mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ - USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - - return ret; -} - -/** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the - * HCFG register on the PHY type and set the right frame interval - * @param USBx Selected device - * @param freq clock frequency - * This parameter can be one of these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock - * @retval HAL status - */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; - - if (freq == HCFG_48_MHZ) - { - USBx_HOST->HFIR = HFIR_48_MHZ; - } - else if (freq == HCFG_6_MHZ) - { - USBx_HOST->HFIR = HFIR_6_MHZ; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx Selected device - * @retval HAL status - * @note (1)The application must wait at least 10 ms - * before clearing the reset bit. - */ -HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - __IO uint32_t hprt0 = 0U; - - hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay(100U); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); - HAL_Delay(10U); - - return HAL_OK; -} - -/** - * @brief USB_DriveVbus : activate or de-activate vbus - * @param state VBUS state - * This parameter can be one of these values: - * 0 : Deactivate VBUS - * 1 : Activate VBUS - * @retval HAL status - */ -HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t hprt0 = 0U; - - hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) - { - USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); - } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) - { - USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); - } - return HAL_OK; -} - -/** - * @brief Return Host Core speed - * @param USBx Selected device - * @retval speed : Host speed - * This parameter can be one of these values: - * @arg HCD_SPEED_HIGH: High speed mode - * @arg HCD_SPEED_FULL: Full speed mode - * @arg HCD_SPEED_LOW: Low speed mode - */ -uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t hprt0 = 0U; - - hprt0 = USBx_HPRT0; - return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); -} - -/** - * @brief Return Host Current Frame number - * @param USBx Selected device - * @retval current frame number - */ -uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); -} - -/** - * @brief Initialize a host channel - * @param USBx Selected device - * @param ch_num Channel number - * This parameter can be a value from 1 to 15 - * @param epnum Endpoint number - * This parameter can be a value from 1 to 15 - * @param dev_address Current device address - * This parameter can be a value from 0 to 255 - * @param speed Current device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type Endpoint Type - * This parameter can be one of these values: - * @arg EP_TYPE_CTRL: Control type - * @arg EP_TYPE_ISOC: Isochronous type - * @arg EP_TYPE_BULK: Bulk type - * @arg EP_TYPE_INTR: Interrupt type - * @param mps Max Packet Size - * This parameter can be a value from 0 to 32K - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, - uint8_t epnum, uint8_t dev_address, uint8_t speed, - uint8_t ep_type, uint16_t mps) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t HCcharEpDir; - uint32_t HCcharLowSpeed; - uint32_t HostCoreSpeed; - - /* Clear old interrupt conditions for this host channel. */ - USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; - - /* Enable channel interrupts required for this transfer. */ - switch (ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | - USB_OTG_HCINTMSK_STALLM | - USB_OTG_HCINTMSK_TXERRM | - USB_OTG_HCINTMSK_DTERRM | - USB_OTG_HCINTMSK_AHBERR | - USB_OTG_HCINTMSK_NAKM; - - if ((epnum & 0x80U) == 0x80U) - { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - else - { -#if defined (USB_OTG_HS) - if (USBx == USB_OTG_HS) - { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | - USB_OTG_HCINTMSK_ACKM; - } -#endif /* defined (USB_OTG_HS) */ - } - break; - - case EP_TYPE_INTR: - USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | - USB_OTG_HCINTMSK_STALLM | - USB_OTG_HCINTMSK_TXERRM | - USB_OTG_HCINTMSK_DTERRM | - USB_OTG_HCINTMSK_NAKM | - USB_OTG_HCINTMSK_AHBERR | - USB_OTG_HCINTMSK_FRMORM; - - if ((epnum & 0x80U) == 0x80U) - { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - - break; - - case EP_TYPE_ISOC: - USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | - USB_OTG_HCINTMSK_ACKM | - USB_OTG_HCINTMSK_AHBERR | - USB_OTG_HCINTMSK_FRMORM; - - if ((epnum & 0x80U) == 0x80U) - { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); - } - break; - - default: - ret = HAL_ERROR; - break; - } - - /* Clear Hub Start Split transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; - - /* Enable host channel Halt interrupt */ - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; - - /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); - - /* Make sure host channel interrupts are enabled. */ - USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - - /* Program the HCCHAR register */ - if ((epnum & 0x80U) == 0x80U) - { - HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; - } - else - { - HCcharEpDir = 0U; - } - - HostCoreSpeed = USB_GetHostSpeed(USBx); - - /* LS device plugged to HUB */ - if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) - { - HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; - } - else - { - HCcharLowSpeed = 0U; - } - - USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | - ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | - (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | - ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | - USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; - - if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) - { - USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - } - - return ret; -} - -/** - * @brief Start a transfer over a host channel - * @param USBx Selected device - * @param hc pointer to host channel structure - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)hc->ch_num; - __IO uint32_t tmpreg; - uint8_t is_oddframe; - uint16_t len_words; - uint16_t num_packets; - uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; - -#if defined (USB_OTG_HS) - if (USBx == USB_OTG_HS) - { - /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ - if (dma == 1U) - { - if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) - { - - USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | - USB_OTG_HCINTMSK_ACKM | - USB_OTG_HCINTMSK_NAKM); - } - } - else - { - if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) - { - (void)USB_DoPing(USBx, hc->ch_num); - return HAL_OK; - } - } - } -#endif /* defined (USB_OTG_HS) */ - - if (hc->do_ssplit == 1U) - { - /* Set number of packet to 1 for Split transaction */ - num_packets = 1U; - - if (hc->ep_is_in != 0U) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; - } - else - { - if (hc->ep_type == EP_TYPE_ISOC) - { - if (hc->xfer_len > ISO_SPLT_MPS) - { - /* Isochrone Max Packet Size for Split mode */ - hc->XferSize = hc->max_packet; - hc->xfer_len = hc->XferSize; - - if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) - { - hc->iso_splt_xactPos = HCSPLT_MIDDLE; - } - else - { - hc->iso_splt_xactPos = HCSPLT_BEGIN; - } - } - else - { - hc->XferSize = hc->xfer_len; - - if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) - { - hc->iso_splt_xactPos = HCSPLT_FULL; - } - else - { - hc->iso_splt_xactPos = HCSPLT_END; - } - } - } - else - { - if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; - } - else - { - hc->XferSize = hc->xfer_len; - } - } - } - } - else - { - /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0U) - { - num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - hc->XferSize = (uint32_t)num_packets * hc->max_packet; - } - } - else - { - num_packets = 1U; - } - - /* - * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of - * max_packet size. - */ - if (hc->ep_is_in != 0U) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; - } - else - { - hc->XferSize = hc->xfer_len; - } - } - - /* Initialize the HCTSIZn register */ - USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | - (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | - (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); - - if (dma != 0U) - { - /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; - } - - is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; - USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; - - if (hc->do_ssplit == 1U) - { - /* Set Hub start Split transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | - (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; - - /* unmask ack & nyet for IN/OUT transactions */ - USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | - USB_OTG_HCINTMSK_NYET); - - if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) - { - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; - } - - if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && - (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) - { - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; - } - - /* Position management for iso out transaction on split mode */ - if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) - { - /* Set data payload position */ - switch (hc->iso_splt_xactPos) - { - case HCSPLT_BEGIN: - /* First data payload for OUT Transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; - break; - - case HCSPLT_MIDDLE: - /* Middle data payload for OUT Transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; - break; - - case HCSPLT_END: - /* End data payload for OUT Transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; - break; - - case HCSPLT_FULL: - /* Entire data payload for OUT Transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; - break; - - default: - break; - } - } - } - else - { - /* Clear Hub Start Split transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; - } - - /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - - /* make sure to set the correct ep direction */ - if (hc->ep_is_in != 0U) - { - tmpreg |= USB_OTG_HCCHAR_EPDIR; - } - else - { - tmpreg &= ~USB_OTG_HCCHAR_EPDIR; - } - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - - if (dma != 0U) /* dma mode */ - { - return HAL_OK; - } - - if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) - { - switch (hc->ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - - /* check if there is enough space in FIFO space */ - if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; - - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - /* check if there is enough space in FIFO space */ - if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); - } - - return HAL_OK; -} - -/** - * @brief Read all host channel interrupts status - * @param USBx Selected device - * @retval HAL state - */ -uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - return ((USBx_HOST->HAINT) & 0xFFFFU); -} - -/** - * @brief Halt a host channel - * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t hcnum = (uint32_t)hc_num; - __IO uint32_t count = 0U; - uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; - uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; - uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; - - /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. - At the end of the next uframe/frame (in the worst case), the core generates a channel halted - and disables the channel automatically. */ - - if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && - ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) - { - return HAL_OK; - } - - /* Check for space in the request queue to issue the halt. */ - if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) - { - if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) - { - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - do - { - count++; - - if (count > 1000U) - { - break; - } - } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) - { - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - do - { - count++; - - if (count > 1000U) - { - break; - } - } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - - return HAL_OK; -} - -/** - * @brief Initiate Do Ping protocol - * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t chnum = (uint32_t)ch_num; - uint32_t num_packets = 1U; - uint32_t tmpreg; - - USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | - USB_OTG_HCTSIZ_DOPING; - - /* Set host channel enable */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - - return HAL_OK; -} - -/** - * @brief Stop Host Core - * @param USBx Selected device - * @retval HAL state - */ -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t count = 0U; - uint32_t value; - uint32_t i; - - (void)USB_DisableGlobalInt(USBx); - - /* Flush USB FIFO */ - if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ - { - ret = HAL_ERROR; - } - - if (USB_FlushRxFifo(USBx) != HAL_OK) - { - ret = HAL_ERROR; - } - - /* Flush out any leftover queued requests. */ - for (i = 0U; i <= 15U; i++) - { - value = USBx_HC(i)->HCCHAR; - value |= USB_OTG_HCCHAR_CHDIS; - value &= ~USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(i)->HCCHAR = value; - } - - /* Halt all channels to put them into a known state. */ - for (i = 0U; i <= 15U; i++) - { - value = USBx_HC(i)->HCCHAR; - value |= USB_OTG_HCCHAR_CHDIS; - value |= USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(i)->HCCHAR = value; - - do - { - count++; - - if (count > 1000U) - { - break; - } - } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - - /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; - USBx->GINTSTS = CLEAR_INTERRUPT_MASK; - - (void)USB_EnableGlobalInt(USBx); - - return ret; -} - -/** - * @brief USB_ActivateRemoteWakeup active remote wakeup signalling - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; - } - - return HAL_OK; -} - -/** - * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); - - return HAL_OK; -} -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ - -/** - * @} - */ +/** + ****************************************************************************** + * @file stm32f7xx_ll_usb.c + * @author MCD Application Team + * @brief USB Low Layer HAL module driver. + * + * This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + I/O operation functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_CfgTypeDef structure. + + (#) Call USB_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + + @endverbatim + + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/** @addtogroup STM32F7xx_LL_USB_DRIVER + * @{ + */ + +#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) || defined (USB_OTG_HS) +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); +#ifdef USBPHYC +static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx); +#endif /* USBPHYC */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the USB Core + * @param USBx USB Instance + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The ULPI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) \ + || defined(STM32F732xx) || defined(STM32F733xx) + /* Select ULPI Interface */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPI_UTMI_SEL; +#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || + defined(STM32F732xx) || defined(STM32F733xx) */ + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + } +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) \ + || defined(STM32F732xx) || defined(STM32F733xx) + else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); + + /* Init The UTMI Interface */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + + /* Select UTMI Interface */ + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_ULPI_UTMI_SEL; +#ifdef USBPHYC + /* Enable USB HS PHY */ + USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN; + + /* Enables control of a High Speed USB PHY */ + if (USB_HS_PHYCInit(USBx) != HAL_OK) + { + return HAL_ERROR; + } +#endif /* USBPHYC */ + + if (cfg.use_external_vbus == 1U) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + } + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + } +#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || + defined(STM32F732xx) || defined(STM32F733xx) */ + else /* FS interface (embedded Phy) */ + { + /* Select FS Embedded PHY */ + USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select */ + ret = USB_CoreReset(USBx); + + /* Activate the USB Transceiver */ + USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + } + + if (cfg.dma_enable == 1U) + { + USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; + USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + } + + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USBx USB Instance + * @param hclk: AHB clock frequency + * @retval USB turnaround time In PHY Clocks number + */ +HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, + uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else if (speed == USBD_HS_SPEED) + { + UsbTrd = USBD_HS_TRDT_VALUE; + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); + + return HAL_OK; +} + +/** + * @brief USB_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_DisableGlobalInt + * Disable the controller's Global Int in the AHB Config reg + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) +{ + USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + return HAL_OK; +} + +/** + * @brief USB_SetCurrentMode Set functional mode + * @param USBx Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) +{ + uint32_t ms = 0U; + + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else if (mode == USB_DEVICE_MODE) + { + USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(10U); + ms += 10U; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); + } + else + { + return HAL_ERROR; + } + + if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_DevInit Initializes the USB_OTG controller registers + * for device mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + for (i = 0U; i < 15U; i++) + { + USBx->DIEPTXF[i] = 0U; + } + + /* VBUS Sensing setup */ + if (cfg.vbus_sensing_enable == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + /* Deactivate VBUS Sensing B */ + USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; + + /* B-peripheral session valid override enable */ + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + } + else + { + /* Enable HW VBUS sensing */ + USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; + } + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + if (cfg.phy_itface == USB_OTG_ULPI_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) \ + || defined(STM32F732xx) || defined(STM32F733xx) + else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) + { + if (cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); + } + } +#endif /* defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || + defined(STM32F732xx) || defined(STM32F733xx) */ + else + { + /* Set Core speed to Full speed mode */ + (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); + } + + /* Flush the FIFOs */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending Device Interrupts */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + if (i == 0U) + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + } + else + { + USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; + } + } + else + { + USBx_INEP(i)->DIEPCTL = 0U; + } + + USBx_INEP(i)->DIEPTSIZ = 0U; + USBx_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + if (i == 0U) + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } + else + { + USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; + } + } + else + { + USBx_OUTEP(i)->DOEPCTL = 0U; + } + + USBx_OUTEP(i)->DOEPTSIZ = 0U; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Device mode ONLY */ + USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | + USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; + + if (cfg.Sof_enable != 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; + } + + if (cfg.vbus_sensing_enable == 1U) + { + USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); + } + + return ret; +} + +/** + * @brief USB_FlushTxFifo Flush a Tx FIFO + * @param USBx Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX Fifo */ + count = 0U; + USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_FlushRxFifo Flush Rx FIFO + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; + USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return HAL_OK; +} + +/** + * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USBx Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @retval Hal status + */ +HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG |= speed; + return HAL_OK; +} + +/** + * @brief USB_GetDevSpeed Return the Dev Speed + * @param USBx Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg USBD_HS_SPEED: High speed mode + * @arg USBD_FS_SPEED: Full speed mode + */ +uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t speed; + uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief Activate and configure an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + } + else + { + USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } + return HAL_OK; +} + +/** + * @brief Activate and configure a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + USB_OTG_DOEPCTL_USBAEP; + } + + USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | + USB_OTG_DIEPCTL_MPSIZ | + USB_OTG_DIEPCTL_TXFNUM | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_EPTYP); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | + USB_OTG_DOEPCTL_MPSIZ | + USB_OTG_DOEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_EPTYP); + } + + return HAL_OK; +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + /* Read DEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + } + + USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + } + + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; + USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } + + return HAL_OK; +} + +/** + * @brief USB_EPStartXfer : setup and starts a transfer over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19)); + + if (ep->type == EP_TYPE_ISOC) + { + USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & ((uint32_t)pktcnt << 29)); + } + } + + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); + } + + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + } + + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + else + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + + (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + if (ep->xfer_len == 0U) + { + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + + if (ep->type == EP_TYPE_ISOC) + { + if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + else + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + } + + return HAL_OK; +} + + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + +/** + * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USBx Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL status + */ +HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, + uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + pSrc++; + pSrc++; + pSrc++; + } + } + + return HAL_OK; +} + +/** + * @brief USB_ReadPacket : read a packet from the RX FIFO + * @param USBx Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint8_t *pDest = dest; + uint32_t pData; + uint32_t i; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); + pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); + } + + return ((void *)pDest); +} + +/** + * @brief USB_EPSetStall : set a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } + else + { + if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } + + return HAL_OK; +} + +/** + * @brief USB_EPClearStall : Clear a stall condition over an EP + * @param USBx Selected device + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return HAL_OK; +} + +/** + * @brief USB_StopDevice : Stop the usb device mode + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USBx_INEP(i)->DIEPINT = 0xFB7FU; + USBx_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USBx_DEVICE->DIEPMSK = 0U; + USBx_DEVICE->DOEPMSK = 0U; + USBx_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_FlushRxFifo(USBx); + if (ret != HAL_OK) + { + return ret; + } + + ret = USB_FlushTxFifo(USBx, 0x10U); + if (ret != HAL_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_SetDevAddress : Stop the usb device mode + * @param USBx Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval HAL status + */ +HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); + USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; + + return HAL_OK; +} + +/** + * @brief USB_DevConnect : Connect the USB device by enabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; + + return HAL_OK; +} + +/** + * @brief USB_ReadInterrupts: return the global USB interrupt status + * @param USBx Selected device + * @retval USB Global Interrupt status + */ +uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t tmpreg; + + tmpreg = USBx->GINTSTS; + tmpreg &= USBx->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadChInterrupts: return USB channel interrupt status + * @param USBx Selected device + * @param chnum Channel number + * @retval USB Channel Interrupt status + */ +uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_HC(chnum)->HCINT; + tmpreg &= USBx_HC(chnum)->HCINTMSK; + + return tmpreg; +} + +/** + * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USBx Selected device + * @retval USB Device OUT EP interrupt status + */ +uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USBx Selected device + * @retval USB Device IN EP interrupt status + */ +uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_DEVICE->DAINT; + tmpreg &= USBx_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + + tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USBx_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USBx Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; + + msk = USBx_DEVICE->DIEPMSK; + emp = USBx_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_ClearInterrupts: clear a USB interrupt + * @param USBx Selected device + * @param interrupt flag + * @retval None + */ +void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) +{ + USBx->GINTSTS &= interrupt; +} + +/** + * @brief Returns USB core mode + * @param USBx Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 1 : Host + * 0 : Device + */ +uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) +{ + return ((USBx->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* Set the MPS of the IN EP0 to 64 bytes */ + USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; + + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; + + return HAL_OK; +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USBx Selected device + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @param psetup pointer to setup packet + * @retval HAL status + */ +HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); + + if (gSNPSiD > USB_OTG_CORE_ID_300A) + { + if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + return HAL_OK; + } + } + + USBx_OUTEP(0U)->DOEPTSIZ = 0U; + USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + + if (dma == 1U) + { + USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; + } + + return HAL_OK; +} + +/** + * @brief Reset the USB Core (needed after USB clock settings change) + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + count = 10U; + + /* few cycles before setting core reset */ + while (count > 0U) + { + count--; + } + + /* Core Soft Reset */ + USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return HAL_OK; +} + +#ifdef USBPHYC +/** + * @brief Enables control of a High Speed USB PHY + * Init the low level hardware : GPIO, CLOCK, NVIC... + * @param USBx Selected device + * @retval HAL status + */ +static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx) +{ + UNUSED(USBx); + __IO uint32_t count = 0U; + + /* Enable LDO */ + USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + /* wait for LDO Ready */ + while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U) + { + count++; + + if (count > HAL_USB_TIMEOUT) + { + return HAL_TIMEOUT; + } + } + + /* Controls PHY frequency operation selection */ + if (HSE_VALUE == PHYC_12_MHZ) /* HSE = 12MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1); + } + else if (HSE_VALUE == PHYC_12_5_MHZ) /* HSE = 12.5MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1); + } + else if (HSE_VALUE == PHYC_16_MHZ) /* HSE = 16MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1); + } + else if (HSE_VALUE == PHYC_24_MHZ) /* HSE = 24MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1); + } + else if (HSE_VALUE == PHYC_25_MHZ) /* HSE = 25MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1); + } + else if (HSE_VALUE == PHYC_32_MHZ) /* HSE = 32MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1); + } + else + { + /* ... */ + } + + /* Control the tuning interface of the High Speed PHY */ + USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE; + + /* Enable PLL internal PHY */ + USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + + /* 2ms Delay required to get internal phy clock stable */ + HAL_Delay(2U); + + return HAL_OK; +} + +#endif /* USBPHYC */ +/** + * @brief USB_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USBx Selected device + * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains + * the configuration information for the specified USBx peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t i; + + /* Restart the Phy Clock */ + USBx_PCGCCTL = 0U; + + /* Disable VBUS sensing */ + USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); + + if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) + { + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force Device Enumeration to FS/LS mode only */ + USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + } + else + { + /* Set default Max speed support */ + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + } + + /* Make sure the FIFOs are flushed. */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; + USBx_HC(i)->HCINTMSK = 0U; + } + + /* Disable all interrupts. */ + USBx->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x200U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); + USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); + } + else +#endif /* defined (USB_OTG_HS) */ + { + /* set Rx FIFO size */ + USBx->GRXFSIZ = 0x80U; + USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); + USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); + } + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; + } + + /* Enable interrupts matching to the Host mode ONLY */ + USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ + USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ + USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); + + return ret; +} + +/** + * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USBx Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval HAL status + */ +HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); + USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USBx_HOST->HFIR = HFIR_48_MHZ; + } + else if (freq == HCFG_6_MHZ) + { + USBx_HOST->HFIR = HFIR_6_MHZ; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; +} + +/** + * @brief USB_OTG_ResetPort : Reset Host Port + * @param USBx Selected device + * @retval HAL status + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); + HAL_Delay(100U); /* See Note #1 */ + USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); + HAL_Delay(10U); + + return HAL_OK; +} + +/** + * @brief USB_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate VBUS + * 1 : Activate VBUS + * @retval HAL status + */ +HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) + { + USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) + { + USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); + } + return HAL_OK; +} + +/** + * @brief Return Host Port speed + * @param USBx Selected device + * @retval speed : Host port device speed + * This parameter can be one of these values: + * @arg HCD_DEVICE_SPEED_HIGH: High speed mode + * @arg HCD_DEVICE_SPEED_FULL: Full speed mode + * @arg HCD_DEVICE_SPEED_LOW: Low speed mode + */ +uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t hprt0 = 0U; + + hprt0 = USBx_HPRT0; + return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USBx Selected device + * @retval current frame number + */ +uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USBx Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, uint8_t speed, + uint8_t ep_type, uint16_t mps) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; + uint32_t HostCoreSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + else + { +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM; + } +#endif /* defined (USB_OTG_HS) */ + } + break; + + case EP_TYPE_INTR: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_STALLM | + USB_OTG_HCINTMSK_TXERRM | + USB_OTG_HCINTMSK_DTERRM | + USB_OTG_HCINTMSK_NAKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_AHBERR | + USB_OTG_HCINTMSK_FRMORM; + + if ((epnum & 0x80U) == 0x80U) + { + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); + } + break; + + default: + ret = HAL_ERROR; + break; + } + + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + + /* Enable the top level host channel interrupt. */ + USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + HostCoreSpeed = USB_GetHostSpeed(USBx); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) + { + HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | + ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | + USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; + + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) + { + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USBx Selected device + * @param hc pointer to host channel structure + * @param dma USB dma enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t ch_num = (uint32_t)hc->ch_num; + __IO uint32_t tmpreg; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; + +#if defined (USB_OTG_HS) + if (USBx == USB_OTG_HS) + { + /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ + if (dma == 1U) + { + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) + { + + USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | + USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NAKM); + } + } + else + { + if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) + { + (void)USB_DoPing(USBx, hc->ch_num); + return HAL_OK; + } + } + } +#endif /* defined (USB_OTG_HS) */ + + if (hc->do_ssplit == 1U) + { + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; + + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; + + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } + } + else + { + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + + /* Initialize the HCTSIZn register */ + USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; + + /* unmask ack & nyet for IN/OUT transactions */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | + USB_OTG_HCINTMSK_NYET); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch (hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + + /* Set host channel enable */ + tmpreg = USBx_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= USB_OTG_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~USB_OTG_HCCHAR_EPDIR; + } + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(ch_num)->HCCHAR = tmpreg; + + if (dma != 0U) /* dma mode */ + { + return HAL_OK; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + + /* Write packet into the Tx FIFO. */ + (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } + + return HAL_OK; +} + +/** + * @brief Read all host channel interrupts status + * @param USBx Selected device + * @retval HAL state + */ +uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + return ((USBx_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t hcnum = (uint32_t)hc_num; + __IO uint32_t count = 0U; + uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; + + /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. + At the end of the next uframe/frame (in the worst case), the core generates a channel halted + and disables the channel automatically. */ + + if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) + { + return HAL_OK; + } + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) + { + if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; + + if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + else + { + USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; + } + } + + return HAL_OK; +} + +/** + * @brief Initiate Do Ping protocol + * @param USBx Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + * @retval HAL state + */ +HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + USB_OTG_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USBx_HC(chnum)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USBx_HC(chnum)->HCCHAR = tmpreg; + + return HAL_OK; +} + +/** + * @brief Stop Host Core + * @param USBx Selected device + * @retval HAL state + */ +HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) +{ + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + __IO uint32_t count = 0U; + uint32_t value; + uint32_t i; + + (void)USB_DisableGlobalInt(USBx); + + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USBx_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USBx_HC(i)->HCCHAR = value; + + do + { + count++; + + if (count > 1000U) + { + break; + } + } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USBx->GINTSTS = CLEAR_INTERRUPT_MASK; + + (void)USB_EnableGlobalInt(USBx); + + return ret; +} + +/** + * @brief USB_ActivateRemoteWakeup active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; + } + + return HAL_OK; +} + +/** + * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USBx Selected device + * @retval HAL status + */ +HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) +{ + uint32_t USBx_BASE = (uint32_t)USBx; + + /* active Remote wakeup signalling */ + USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); + + return HAL_OK; +} +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ +#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ + +/** + * @} + */ diff --git a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c b/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c deleted file mode 100644 index 263566e9..00000000 --- a/src/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c +++ /dev/null @@ -1,752 +0,0 @@ -/** - ****************************************************************************** - * @file stm32f7xx_ll_utils.c - * @author MCD Application Team - * @brief UTILS LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2017 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32f7xx_ll_utils.h" -#include "stm32f7xx_ll_rcc.h" -#include "stm32f7xx_ll_system.h" -#include "stm32f7xx_ll_pwr.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32F7xx_LL_Driver - * @{ - */ - -/** @addtogroup UTILS_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Constants - * @{ - */ -#define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ - -/* Defines used for PLL range */ -#define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */ -#define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */ -#define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */ -#define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */ - -/* Defines used for HSE range */ -#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ -#define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */ - -/* Defines used for FLASH latency according to HCLK Frequency */ -#define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ -#define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ -#define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ -#define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ -#define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ -#define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 with over-drive mode */ -#define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 with over-drive mode */ -#define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ -#define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ -#define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ -#define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ -#define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */ -#define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ -#define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ -#define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ -#define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Macros - * @{ - */ -#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) - -#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_16)) - -#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_16)) - -#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \ - || ((__VALUE__) == LL_RCC_PLLM_DIV_63)) - -#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432)) - -#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \ - || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \ - || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \ - || ((__VALUE__) == LL_RCC_PLLP_DIV_8)) - -#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) - -#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) - -#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ - (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ - ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) - -#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ - || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) - -#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Functions UTILS Private functions - * @{ - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -static ErrorStatus UTILS_PLL_IsBusy(void); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Exported_Functions - * @{ - */ - -/** @addtogroup UTILS_LL_EF_DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base. - * @note When a RTOS is used, it is recommended to avoid changing the Systick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param HCLKFrequency HCLK frequency in Hz - * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq - * @retval None - */ -void LL_Init1msTick(uint32_t HCLKFrequency) -{ - /* Use frequency provided in argument */ - LL_InitTick(HCLKFrequency, 1000U); -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on SysTick counter flag - * @note When a RTOS is used, it is recommended to avoid using blocking delay - * and use rather osDelay service. - * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which - * will configure Systick to 1ms - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -void LL_mDelay(uint32_t Delay) -{ - __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ - /* Add this code to indicate that local variable is not used */ - ((void)tmp); - - /* Add a period to guaranty minimum wait */ - if(Delay < LL_MAX_DELAY) - { - Delay++; - } - - while (Delay) - { - if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) - { - Delay--; - } - } -} - -/** - * @} - */ - -/** @addtogroup UTILS_EF_SYSTEM - * @brief System Configuration functions - * - @verbatim - =============================================================================== - ##### System Configuration functions ##### - =============================================================================== - [..] - System, AHB and APB buses clocks configuration - - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz. - @endverbatim - @internal - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: - (++) +------------------------------------------------------------------------------------------------+ - (++) | Wait states | HCLK clock frequency (MHz) | - (++) | |-------------------------------------------------------------------------------| - (++) | (Latency) | voltage range | voltage range | voltage range | voltage range | - (++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | 1.8V - 2.1V | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | 0 < HCLK <= 20 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 20 < HCLK <= 44 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 40 < HCLK <= 60 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 60 < HCLK <= 80 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 80 < HCLK <= 100 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 | - (++) |----------------|-------------------|-------------------|-------------------|-------------------| - (++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | -- | - (++) +------------------------------------------------------------------------------------------------+ - - @endinternal - * @{ - */ - -/** - * @brief This function sets directly SystemCoreClock CMSIS variable. - * @note Variable can be calculated also through SystemCoreClockUpdate function. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @retval None - */ -void LL_SetSystemCoreClock(uint32_t HCLKFrequency) -{ - /* HCLK clock frequency */ - SystemCoreClock = HCLKFrequency; -} - -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V - * @param HCLK_Frequency HCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) -{ - uint32_t timeout; - uint32_t getlatency; - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - ErrorStatus status = SUCCESS; - - /* Frequency cannot be equal to 0 */ - if(HCLK_Frequency == 0U) - { - status = ERROR; - } - else - { - if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) - { - if(LL_PWR_IsEnabledOverDriveMode() != 0U) - { - if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ) - { - /* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */ - latency = LL_FLASH_LATENCY_7; - } - else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */ - { - /* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */ - latency = LL_FLASH_LATENCY_6; - } - } - if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; - } - else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0)) - { - /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ) - { - /* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */ - latency = LL_FLASH_LATENCY_5; - } - else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ) - { - /* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ) - { - /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ) - { - /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ) - { - /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - else /* Scale 3 */ - { - if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ) - { - /* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ) - { - /* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ) - { - /* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ) - { - /* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - /* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - - if (status != ERROR) - { - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - timeout = 2; - do - { - /* Wait for Flash latency to be updated */ - getlatency = LL_FLASH_GetLatency(); - timeout--; - } while ((getlatency != latency) && (timeout > 0)); - - if(getlatency != latency) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - } - } - return status; -} - -/** - * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @note Function is based on the following formula: - * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP) - * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM) - * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN) - * - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP) - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; - - /* Check if one of the PLL is enabled */ - if(UTILS_PLL_IsBusy() == SUCCESS) - { - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); - - /* Enable HSI if not enabled */ - if(LL_RCC_HSI_IsReady() != 1U) - { - LL_RCC_HSI_Enable(); - while (LL_RCC_HSI_IsReady() != 1U) - { - /* Wait for HSI ready */ - } - } - - /* Configure PLL */ - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, - UTILS_PLLInitStruct->PLLP); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @brief This function configures system clock with HSE as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @note Function is based on the following formula: - * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP) - * - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM) - * - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN) - * - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP) - * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000 - * @param HSEBypass This parameter can be one of the following values: - * @arg @ref LL_UTILS_HSEBYPASS_ON - * @arg @ref LL_UTILS_HSEBYPASS_OFF - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq = 0U; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); - assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); - - /* Check if one of the PLL is enabled */ - if(UTILS_PLL_IsBusy() == SUCCESS) - { - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); - - /* Enable HSE if not enabled */ - if(LL_RCC_HSE_IsReady() != 1U) - { - /* Check if need to enable HSE bypass feature or not */ - if(HSEBypass == LL_UTILS_HSEBYPASS_ON) - { - LL_RCC_HSE_EnableBypass(); - } - else - { - LL_RCC_HSE_DisableBypass(); - } - - /* Enable HSE */ - LL_RCC_HSE_Enable(); - while (LL_RCC_HSE_IsReady() != 1U) - { - /* Wait for HSE ready */ - } - } - - /* Configure PLL */ - LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, - UTILS_PLLInitStruct->PLLP); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UTILS_LL_Private_Functions - * @{ - */ -/** - * @brief Function to check that PLL can be modified - * @param PLL_InputFrequency PLL input frequency (in Hz) - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @retval PLL output frequency (in Hz) - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) -{ - uint32_t pllfreq = 0U; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); - assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); - assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP)); - - /* Check different PLL parameters according to RM */ - /* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */ - pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos)); - assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); - - /* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/ - pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos)); - assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); - - /* - PLLP: ensure that max frequency at 216000000 Hz is reached */ - pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2); - assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); - - return pllfreq; -} - -/** - * @brief Function to check that PLL can be modified - * @retval An ErrorStatus enumeration value: - * - SUCCESS: PLL modification can be done - * - ERROR: PLL is busy - */ -static ErrorStatus UTILS_PLL_IsBusy(void) -{ - ErrorStatus status = SUCCESS; - - /* Check if PLL is busy*/ - if(LL_RCC_PLL_IsReady() != 0U) - { - /* PLL configuration cannot be modified */ - status = ERROR; - } - - /* Check if PLLSAI is busy*/ - if(LL_RCC_PLLSAI_IsReady() != 0U) - { - /* PLLSAI1 configuration cannot be modified */ - status = ERROR; - } - /* Check if PLLI2S is busy*/ - if(LL_RCC_PLLI2S_IsReady() != 0U) - { - /* PLLI2S configuration cannot be modified */ - status = ERROR; - } - return status; -} - -/** - * @brief Function to enable PLL and switch system clock to PLL - * @param SYSCLK_Frequency SYSCLK frequency - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: No problem to switch system to PLL - * - ERROR: Problem to switch system to PLL - */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t hclk_frequency = 0U; - - assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); - assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); - assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); - - /* Calculate HCLK frequency */ - hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); - - /* Increasing the number of wait states because of higher CPU frequency */ - if(SystemCoreClock < hclk_frequency) - { - /* Set FLASH latency to highest latency */ - status = LL_SetFlashLatency(hclk_frequency); - } - - /* Update system clock configuration */ - if(status == SUCCESS) - { - /* Enable PLL */ - LL_RCC_PLL_Enable(); - while (LL_RCC_PLL_IsReady() != 1U) - { - /* Wait for PLL ready */ - } - - /* Sysclk activation on the main PLL */ - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) - { - /* Wait for system clock switch to PLL */ - } - - /* Set APB1 & APB2 prescaler*/ - LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); - LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if(SystemCoreClock > hclk_frequency) - { - /* Set FLASH latency to lowest latency */ - status = LL_SetFlashLatency(hclk_frequency); - } - - /* Update SystemCoreClock variable */ - if(status == SUCCESS) - { - LL_SetSystemCoreClock(hclk_frequency); - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/src/FileX/App/app_filex.c b/src/FileX/App/app_filex.c new file mode 100644 index 00000000..0819c52c --- /dev/null +++ b/src/FileX/App/app_filex.c @@ -0,0 +1,76 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_filex.c + * @author MCD Application Team + * @brief FileX applicative file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "app_filex.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/** + * @brief Application FileX Initialization. + * @param memory_ptr: memory pointer + * @retval int + */ +UINT MX_FileX_Init(VOID *memory_ptr) +{ + UINT ret = FX_SUCCESS; + TX_BYTE_POOL *byte_pool = (TX_BYTE_POOL*)memory_ptr; + + /* USER CODE BEGIN MX_FileX_MEM_POOL */ + (void)byte_pool; + /* USER CODE END MX_FileX_MEM_POOL */ + + /* USER CODE BEGIN MX_FileX_Init */ + fx_system_initialize(); + /* USER CODE END MX_FileX_Init */ + return ret; +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/FileX/App/app_filex.h b/src/FileX/App/app_filex.h new file mode 100644 index 00000000..1e7c6f9e --- /dev/null +++ b/src/FileX/App/app_filex.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_filex.h + * @author MCD Application Team + * @brief FileX applicative header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __APP_FILEX_H__ +#define __APP_FILEX_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "fx_api.h" + +#include "fx_stm32_sd_driver.h" +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +UINT MX_FileX_Init(VOID *memory_ptr); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ +#ifdef __cplusplus +} +#endif +#endif /* __APP_FILEX_H__ */ diff --git a/src/FileX/App/fx_user.h b/src/FileX/App/fx_user.h new file mode 100644 index 00000000..1e444b95 --- /dev/null +++ b/src/FileX/App/fx_user.h @@ -0,0 +1,212 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* fx_user.h PORTABLE C */ +/* 6.1.8 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring FileX in specific */ +/* ways. This file will have an effect only if the application and */ +/* FileX library are built with FX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building FileX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added product constants */ +/* to enable code */ +/* size optimization, */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), and */ +/* added standalone support, */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ + +#ifndef FX_USER_H +#define FX_USER_H + +/* Define various build options for the FileX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ + +/* Override various options with default values already assigned in fx_api.h or fx_port.h. + Please also refer to fx_port.h for descriptions on each of these options. */ + +/* Defined, Filex will be used in standalone mode (without ThreadX) */ + +/* #define FX_STANDALONE_ENABLE */ + +/* Defined, the direct read sector update of cache is disabled. */ + +/* #define FX_DISABLE_DIRECT_DATA_READ_CACHE_FILL */ + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +/* #define FX_DISABLE_ERROR_CHECKING */ + +/* Defined, FileX does not update already opened files. */ + +/* #define FX_DONT_UPDATE_OPEN_FILES */ + +/* Defined, enables 64-bits sector addresses used in I/O driver. */ + +/* #define FX_DRIVER_USE_64BIT_LBA */ + +/* Defined, FileX is able to access exFAT file system. + + FileX supports the Microsoft exFAT file system format. + Your use of exFAT technology in your products requires a separate + license from Microsoft. Please see the following link for further + details on exFAT licensing: + + https://www.microsoft.com/en-us/legal/intellectualproperty/mtl/exfat-licensing.aspx +*/ + +/* #define FX_ENABLE_EXFAT */ + +/* Defined, enables FileX fault tolerant service. */ + +/* #define FX_ENABLE_FAULT_TOLERANT */ + +/* Defines the size in bytes of the bit map used to update the secondary FAT sectors. + The larger the value the less unnecessary secondary FAT sector writes. */ + +/* #define FX_FAT_MAP_SIZE 128 */ + +/* Defined, data sector write requests are flushed immediately to the driver. */ + +/* #define FX_FAULT_TOLERANT */ + +/* Define byte offset in boot sector where the cluster number of the Fault Tolerant Log file is. + Note that this field (byte 116 to 119) is marked as reserved by FAT 12/16/32/exFAT specification. */ + +/* #define FX_FAULT_TOLERANT_BOOT_INDEX 116 */ + +/* Defined, data sector write requests are flushed immediately to the driver. */ + +/* #define FX_FAULT_TOLERANT_DATA */ + +/* Defines the number of entries in the FAT cache. */ + +/* #define FX_MAX_FAT_CACHE 16 */ + +/* Defines the maximum size of long file names supported by FileX. + The minimum value is 13 and the maximum value is 256. */ + +/* #define FX_MAX_LAST_NAME_LEN 256 */ +/* #define FX_MAX_LONG_NAME_LEN 256 */ + +/* Defines the maximum number of logical sectors that can be cached by FileX. The cache memory + supplied to FileX at fx_media_open determines how many sectors can actually be cached. */ + +/* #define FX_MAX_SECTOR_CACHE 256 */ + +/* Defined, the file search cache optimization is disabled. */ + +/* #define FX_MEDIA_DISABLE_SEARCH_CACHE */ + +/* Defined, gathering of media statistics is disabled. */ + +/* #define FX_MEDIA_STATISTICS_DISABLE */ + +/* Defined, local path logic is disabled. */ + +/* #define FX_NO_LOCAL_PATH */ + +/* Defined, FileX is built without update to the time parameters. */ + +/* #define FX_NO_TIMER */ + +/* Defined, renaming inherits path information. */ + +/* #define FX_RENAME_PATH_INHERIT */ + +/* Defined, legacy single open logic for the same file is enabled. */ + +/* #define FX_SINGLE_OPEN_LEGACY */ + +/* Define FileX internal protection macros. If FX_SINGLE_THREAD is defined, + these protection macros are effectively disabled. However, for multi-thread + uses, the macros are setup to utilize a ThreadX mutex for multiple thread + access control into an open media. */ + +/* #define FX_SINGLE_THREAD */ + +/* Defines the number of seconds the time parameters are updated in FileX. */ + +/* #define FX_UPDATE_RATE_IN_SECONDS 10 */ + +/* Defines the number of ThreadX timer ticks required to achieve the update rate specified by + FX_UPDATE_RATE_IN_SECONDS defined previously. By default, the ThreadX timer tick is 10ms, + so the default value for this constant is 1000. */ + +#define FX_UPDATE_RATE_IN_TICKS 10000 + +/* If defined, cache is disabled. */ + +#define FX_DISABLE_CACHE + +/* If defined, file close is disabled. */ + +/* #define FX_DISABLE_FILE_CLOSE */ + +/* If defined, fast open is disabled. */ + +/* #define FX_DISABLE_FAST_OPEN */ + +/* If defined, force memory operations are disabled. */ + +/* #define FX_DISABLE_FORCE_MEMORY_OPERATION */ + +/* If defined, build options is disabled. */ + +/* #define FX_DISABLE_BUILD_OPTIONS */ + +/* If defined, one line function is disabled. */ + +/* #define FX_DISABLE_ONE_LINE_FUNCTION */ + +/* If defined, FAT entry refresh is disabled. */ + +/* #define FX_DISABLE_FAT_ENTRY_REFRESH */ + +/* If defined, consecutive detect is disabled. */ + +/* #define FX_DISABLE_CONSECUTIVE_DETECT */ + +#endif diff --git a/src/FileX/Target/fx_stm32_sd_driver.h b/src/FileX/Target/fx_stm32_sd_driver.h new file mode 100644 index 00000000..e882dca9 --- /dev/null +++ b/src/FileX/Target/fx_stm32_sd_driver.h @@ -0,0 +1,218 @@ + +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef FX_STM32_SD_DRIVER_H +#define FX_STM32_SD_DRIVER_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "fx_api.h" +#include "stm32f7xx_hal.h" + +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +extern TX_SEMAPHORE sd_tx_semaphore; +extern TX_SEMAPHORE sd_rx_semaphore; + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ +/* Default timeout used to wait for fx operations */ +#define FX_STM32_SD_DEFAULT_TIMEOUT (10 * TX_TIMER_TICKS_PER_SECOND) + +/* Let the filex low-level driver initialize the SD driver */ +#define FX_STM32_SD_INIT 1 + +/* Enable the cache mainatenance, required when using the SD DMA */ +#define FX_STM32_SD_CACHE_MAINTENANCE 1 + +/* Use the SD DMA API */ +#define FX_STM32_SD_DMA_API 1 + +/* SDIO instance to be used by FileX */ +#define FX_STM32_SD_INSTANCE 0 + +/* Default sector size, used by the driver */ +#define FX_STM32_SD_DEFAULT_SECTOR_SIZE 512 + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Define the CPU Cache maintenance macros */ +#if (FX_STM32_SD_CACHE_MAINTENANCE == 1) +#define invalidate_cache_by_addr(__ptr__, __size__) SCB_InvalidateDCache_by_Addr((void *)__ptr__, (int32_t)__size__) +#define clean_cache_by_addr(__ptr__, __size__) SCB_CleanDCache_by_Addr((uint32_t *)__ptr__, (int32_t)__size__) +#endif + +/* Define the macro to get the current time in ticks */ +/* USER CODE BEGIN FX_STM32_SD_CURRENT_TIME_TX */ + +#define FX_STM32_SD_CURRENT_TIME() tx_time_get() + +/* USER CODE END FX_STM32_SD_CURRENT_TIME_TX */ + +/* Macro called before initializing the SD driver + * e.g. create a semaphore used for transfer notification */ +/* USER CODE BEGIN FX_STM32_SD_PRE_INIT_TX */ + +#define FX_STM32_SD_PRE_INIT(_media_ptr) \ + do \ + { \ + if ((tx_semaphore_create(&sd_rx_semaphore, "sd rx transfer semaphore", 0) != TX_SUCCESS) || \ + (tx_semaphore_create(&sd_tx_semaphore, "sd tx transfer semaphore", 0) != TX_SUCCESS)) \ + { \ + _media_ptr->fx_media_driver_status = FX_IO_ERROR; \ + } \ + } while (0) + +/* USER CODE END FX_STM32_SD_PRE_INIT_TX */ + +/* Macro called after initializing the SD driver */ +/* USER CODE BEGIN FX_STM32_SD_POST_INIT */ + +#define FX_STM32_SD_POST_INIT(_media_ptr) + +/* USER CODE END FX_STM32_SD_POST_INIT */ + +/* Macro called after the SD deinit */ +/* USER CODE BEGIN FX_STM32_SD_POST_DEINIT_TX */ + +#define FX_STM32_SD_POST_DEINIT(_media_ptr) \ + do \ + { \ + tx_semaphore_delete(&sd_rx_semaphore); \ + tx_semaphore_delete(&sd_tx_semaphore); \ + } while (0) + +/* USER CODE END FX_STM32_SD_POST_DEINIT_TX */ + +/* Macro called after the abort request */ +/* USER CODE BEGIN FX_STM32_SD_POST_ABORT */ + +#define FX_STM32_SD_POST_ABORT(_media_ptr) + +/* USER CODE END FX_STM32_SD_POST_ABORT */ + +/* Macro called before performing read operation */ +/* USER CODE BEGIN FX_STM32_SD_PRE_READ_TRANSFER_DMA */ + +#define FX_STM32_SD_PRE_READ_TRANSFER(_media_ptr) + +/* USER CODE END FX_STM32_SD_PRE_READ_TRANSFER_DMA */ + +/* Macro called after performing read operation */ +/* USER CODE BEGIN FX_STM32_SD_POST_READ_TRANSFER_TX */ + +#define FX_STM32_SD_POST_READ_TRANSFER(_media_ptr) + +/* USER CODE END FX_STM32_SD_POST_READ_TRANSFER_TX */ + +/* Macro for read error handling */ +/* USER CODE BEGIN FX_STM32_SD_READ_TRANSFER_ERROR_TX */ + +#define FX_STM32_SD_READ_TRANSFER_ERROR(_status_) + +/* USER CODE END FX_STM32_SD_READ_TRANSFER_ERROR_TX */ + +/* Define how to notify about Read completion operation */ +/* USER CODE BEGIN FX_STM32_SD_READ_CPLT_NOTIFY_TX */ + +#define FX_STM32_SD_READ_CPLT_NOTIFY() \ + do \ + { \ + if (tx_semaphore_get(&sd_rx_semaphore, FX_STM32_SD_DEFAULT_TIMEOUT) != TX_SUCCESS) \ + { \ + return FX_IO_ERROR; \ + } \ + } while (0) + +/* USER CODE END FX_STM32_SD_READ_CPLT_NOTIFY_TX */ + +/* Define how to notify about write completion operation */ +/* USER CODE BEGIN FX_STM32_SD_WRITE_CPLT_NOTIFY_TX */ + +#define FX_STM32_SD_WRITE_CPLT_NOTIFY() \ + do \ + { \ + if (tx_semaphore_get(&sd_tx_semaphore, FX_STM32_SD_DEFAULT_TIMEOUT) != TX_SUCCESS) \ + { \ + return FX_IO_ERROR; \ + } \ + } while (0) + +/* USER CODE END FX_STM32_SD_WRITE_CPLT_NOTIFY_TX */ + +/* Macro called before performing write operation */ +/* USER CODE BEGIN FX_STM32_SD_PRE_WRITE_TRANSFER_TX */ + +#define FX_STM32_SD_PRE_WRITE_TRANSFER(_media_ptr) + +/* USER CODE END FX_STM32_SD_PRE_WRITE_TRANSFER_TX */ + +/* Macro called after performing write operation */ +/* USER CODE BEGIN FX_STM32_SD_POST_WRITE_TRANSFER */ + +#define FX_STM32_SD_POST_WRITE_TRANSFER(_media_ptr) + +/* USER CODE END FX_STM32_SD_POST_WRITE_TRANSFER */ + +/* Macro for write error handling */ +/* USER CODE BEGIN FX_STM32_SD_WRITE_TRANSFER_ERROR */ + +#define FX_STM32_SD_WRITE_TRANSFER_ERROR(_status_) + +/* USER CODE END FX_STM32_SD_WRITE_TRANFSER_ERROR */ + +/* Exported functions prototypes ---------------------------------------------*/ + +INT fx_stm32_sd_init(UINT instance); +INT fx_stm32_sd_deinit(UINT instance); + +INT fx_stm32_sd_get_status(UINT instance); + +INT fx_stm32_sd_read_blocks(UINT instance, UINT *buffer, UINT start_block, UINT total_blocks); +INT fx_stm32_sd_write_blocks(UINT instance, UINT *buffer, UINT start_block, UINT total_blocks); + +VOID fx_stm32_sd_driver(FX_MEDIA *media_ptr); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* FX_STM32_SD_DRIVER_H */ diff --git a/src/FileX/Target/fx_stm32_sd_driver_glue.c b/src/FileX/Target/fx_stm32_sd_driver_glue.c new file mode 100644 index 00000000..8b11f6de --- /dev/null +++ b/src/FileX/Target/fx_stm32_sd_driver_glue.c @@ -0,0 +1,194 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +#include "fx_stm32_sd_driver.h" + +TX_SEMAPHORE sd_tx_semaphore; +TX_SEMAPHORE sd_rx_semaphore; + +extern SD_HandleTypeDef hsd1; +#if (FX_STM32_SD_INIT == 1) +extern void MX_SDMMC1_SD_Init(void); +#endif + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** +* @brief Initializes the SD IP instance +* @param UINT instance SD instance to initialize +* @retval 0 on success error value otherwise +*/ +INT fx_stm32_sd_init(UINT instance) +{ + INT ret = 0; + + /* USER CODE BEGIN PRE_FX_SD_INIT */ + UNUSED(instance); + /* USER CODE END PRE_FX_SD_INIT */ + +#if (FX_STM32_SD_INIT == 1) + MX_SDMMC1_SD_Init(); +#endif + + /* USER CODE BEGIN POST_FX_SD_INIT */ + + /* USER CODE END POST_FX_SD_INIT */ + + return ret; +} + +/** +* @brief Deinitializes the SD IP instance +* @param UINT instance SD instance to deinitialize +* @retval 0 on success error value otherwise +*/ +INT fx_stm32_sd_deinit(UINT instance) +{ + INT ret = 0; + + /* USER CODE BEGIN PRE_FX_SD_DEINIT */ + UNUSED(instance); + /* USER CODE END PRE_FX_SD_DEINIT */ + + if(HAL_SD_DeInit(&hsd1) != HAL_OK) + { + ret = 1; + } + + /* USER CODE BEGIN POST_FX_SD_DEINIT */ + + /* USER CODE END POST_FX_SD_DEINIT */ + + return ret; +} + +/** +* @brief Check the SD IP status. +* @param UINT instance SD instance to check +* @retval 0 when ready 1 when busy +*/ +INT fx_stm32_sd_get_status(UINT instance) +{ + INT ret = 0; + + /* USER CODE BEGIN PRE_GET_STATUS */ + UNUSED(instance); + /* USER CODE END PRE_GET_STATUS */ + + if(HAL_SD_GetCardState(&hsd1) != HAL_SD_CARD_TRANSFER) + { + ret = 1; + } + + /* USER CODE BEGIN POST_GET_STATUS */ + + /* USER CODE END POST_GET_STATUS */ + + return ret; +} + +/** +* @brief Read Data from the SD device into a buffer. +* @param UINT instance SD IP instance to read from. +* @param UINT *buffer buffer into which the data is to be read. +* @param UINT start_block the first block to start reading from. +* @param UINT total_blocks total number of blocks to read. +* @retval 0 on success error code otherwise +*/ +INT fx_stm32_sd_read_blocks(UINT instance, UINT *buffer, UINT start_block, UINT total_blocks) +{ + INT ret = 0; + + /* USER CODE BEGIN PRE_READ_BLOCKS */ + UNUSED(instance); + /* USER CODE END PRE_READ_BLOCKS */ + + if(HAL_SD_ReadBlocks_DMA(&hsd1, (uint8_t *)buffer, start_block, total_blocks) != HAL_OK) + { + ret = 1; + } + + /* USER CODE BEGIN POST_READ_BLOCKS */ + + /* USER CODE END POST_READ_BLOCKS */ + + return ret; +} + +/** +* @brief Write data buffer into the SD device. +* @param UINT instance SD IP instance to write into. +* @param UINT *buffer buffer to write into the SD device. +* @param UINT start_block the first block to start writing into. +* @param UINT total_blocks total number of blocks to write. +* @retval 0 on success error code otherwise +*/ +INT fx_stm32_sd_write_blocks(UINT instance, UINT *buffer, UINT start_block, UINT total_blocks) +{ + INT ret = 0; + + /* USER CODE BEGIN PRE_WRITE_BLOCKS */ + UNUSED(instance); + /* USER CODE END PRE_WRITE_BLOCKS */ + + if(HAL_SD_WriteBlocks_DMA(&hsd1, (uint8_t *)buffer, start_block, total_blocks) != HAL_OK) + { + ret = 1; + } + + /* USER CODE BEGIN POST_WRITE_BLOCKS */ + + /* USER CODE END POST_WRITE_BLOCKS */ + + return ret; +} + +/** +* @brief SD DMA Tx Transfer completed callbacks +* @param Instance the sd instance +* @retval None +*/ +void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd) +{ + /* USER CODE BEGIN PRE_TX_CMPLT */ + + /* USER CODE END PRE_TX_CMPLT */ + + tx_semaphore_put(&sd_tx_semaphore); + + /* USER CODE BEGIN POST_TX_CMPLT */ + + /* USER CODE END POST_TX_CMPLT */ +} + +/** +* @brief SD DMA Rx Transfer completed callbacks +* @param Instance the sd instance +* @retval None +*/ +void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd) +{ + /* USER CODE BEGIN PRE_RX_CMPLT */ + + /* USER CODE END PRE_RX_CMPLT */ + + tx_semaphore_put(&sd_rx_semaphore); + + /* USER CODE BEGIN POST_RX_CMPLT */ + + /* USER CODE END POST_RX_CMPLT */ +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/Middlewares/ST/filex/LICENSE.txt b/src/Middlewares/ST/filex/LICENSE.txt new file mode 100644 index 00000000..7fe33120 --- /dev/null +++ b/src/Middlewares/ST/filex/LICENSE.txt @@ -0,0 +1,246 @@ +MICROSOFT SOFTWARE LICENSE TERMS + +MICROSOFT AZURE RTOS + +Shape + +These license terms are an agreement between you and Microsoft Corporation (or +one of its affiliates). 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Vous +pourriez avoir d’autres droits prévus par les lois de votre pays. Le présent +contrat ne modifie pas les droits que vous confèrent les lois de votre pays si +celles-ci ne le permettent pas. \ No newline at end of file diff --git a/src/Middlewares/ST/filex/LICENSED-HARDWARE.txt b/src/Middlewares/ST/filex/LICENSED-HARDWARE.txt new file mode 100644 index 00000000..5573bcb0 --- /dev/null +++ b/src/Middlewares/ST/filex/LICENSED-HARDWARE.txt @@ -0,0 +1,37 @@ +LICENSED HARDWARE LIST + +Last Updated January 28, 2022 + +Microsoft has entered into OEM Agreements with manufacturers of the following microprocessors and +microcontrollers (the “hardware”) to enable those manufacturers to include and distribute Azure RTOS +in certain hardware. By purchasing and using hardware on this list you inherit the “Distribution and +Production Use” rights in Section 2 of the Microsoft Software License Terms for Microsoft Azure RTOS. If +hardware is not listed below, you do not have those rights. + +Manufacturer: + + STMicroelectronics + +Licensed Microcontrollers and Microprocessors: + + STM32H7 Series + + STM32U5 Series + + STM32F4 Series + + STM32L4/STM32L4+ series + + STM32G4 Series + + STM32F7 Series + + STM32L5 Series + + STM32G0 Series + + STM32WL Series + + STM32WB Series + + STM32C0 Series diff --git a/src/Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c b/src/Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c new file mode 100644 index 00000000..cb5978b8 --- /dev/null +++ b/src/Middlewares/ST/filex/common/drivers/fx_stm32_sd_driver.c @@ -0,0 +1,411 @@ +/**************************************************************************/ +/* */ +/* Partial Copyright (c) Microsoft Corporation. All rights reserved.*/ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* Partial Copyright (c) STMicroelctronics 2020. All rights reserved */ +/**************************************************************************/ + + +/* Include necessary system files. */ +#include "fx_stm32_sd_driver.h" + +/* + * the scratch buffer is required when performing DMA transfers using unaligned addresses + * When CPU cache is enabled, the scratch buffer should be 32-byte aligned to match a whole cache line + * otherwise it is 4-byte aligned to match the DMA alignment constraints + */ + +#if (FX_STM32_SD_CACHE_MAINTENANCE == 1) +static UCHAR scratch[FX_STM32_SD_DEFAULT_SECTOR_SIZE] __attribute__ ((aligned (32))); +#else +static UCHAR scratch[FX_STM32_SD_DEFAULT_SECTOR_SIZE] __attribute__ ((aligned (4))); +#endif + +UINT _fx_partition_offset_calculate(void *partition_sector, UINT partition, ULONG *partition_start, ULONG *partition_size); + +static UINT sd_read_data(FX_MEDIA *media_ptr, ULONG sector, UINT num_sectors, UINT use_scratch_buffer); +static UINT sd_write_data(FX_MEDIA *media_ptr, ULONG sector, UINT num_sectors, UINT use_scratch_buffer); + +static UINT is_initialized = 0; + + +static INT check_sd_status(uint32_t instance) +{ + uint32_t start = FX_STM32_SD_CURRENT_TIME(); + + while (FX_STM32_SD_CURRENT_TIME() - start < FX_STM32_SD_DEFAULT_TIMEOUT) + { + if (fx_stm32_sd_get_status(instance) == 0) + { + return 0; + } + } + + return 1; +} + +/** +* @brief This function is the entry point to the STM32 SD disk driver. +* It relies on the STM32 peripheral library from ST. +* @param media_ptr: FileX's Media Config Block +* @retval None +*/ +VOID fx_stm32_sd_driver(FX_MEDIA *media_ptr) +{ + UINT status; + UINT unaligned_buffer; + ULONG partition_start; + ULONG partition_size; + +#if (FX_STM32_SD_INIT == 0) + /* the SD was initialized by the application */ + is_initialized = 1; +#endif + /* before performing any operation, check the status of the SD IP */ + if (is_initialized == 1) + { + if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) + { + media_ptr->fx_media_driver_status = FX_IO_ERROR; + return; + } + } + +#if (FX_STM32_SD_DMA_API == 1) + /* the SD DMA requires a 4-byte aligned buffers */ + unaligned_buffer = (UINT)(media_ptr->fx_media_driver_buffer) & 0x3; +#else + /* if the DMA is not used there isn't any constraint on buffer alignment */ + unaligned_buffer = 0; +#endif + /* Process the driver request specified in the media control block. */ + switch(media_ptr->fx_media_driver_request) + { + case FX_DRIVER_INIT: + { + media_ptr->fx_media_driver_status = FX_SUCCESS; + + FX_STM32_SD_PRE_INIT(media_ptr); + +#if (FX_STM32_SD_INIT == 1) + /* Initialize the SD instance */ + if (is_initialized == 0) + { + status = fx_stm32_sd_init(FX_STM32_SD_INSTANCE); + + if (status == 0) + { + is_initialized = 1; + } + else + { + media_ptr->fx_media_driver_status = FX_IO_ERROR; + } + } +#endif + /* call post init user macro */ + FX_STM32_SD_POST_INIT(media_ptr); + break; + } + + case FX_DRIVER_UNINIT: + { + media_ptr->fx_media_driver_status = FX_SUCCESS; + +#if (FX_STM32_SD_INIT == 1) + status = fx_stm32_sd_deinit(FX_STM32_SD_INSTANCE); + + if (status != 0) + { + media_ptr->fx_media_driver_status = FX_IO_ERROR; + } + else + { + is_initialized = 0; + } +#endif + /* call post deinit processing */ + FX_STM32_SD_POST_DEINIT(media_ptr); + + break; + } + + case FX_DRIVER_READ: + { + media_ptr->fx_media_driver_status = FX_IO_ERROR; + + if (sd_read_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors, + media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) + { + media_ptr->fx_media_driver_status = FX_SUCCESS; + } + + break; + } + + case FX_DRIVER_WRITE: + { + media_ptr->fx_media_driver_status = FX_IO_ERROR; + + if (sd_write_data(media_ptr, media_ptr->fx_media_driver_logical_sector + media_ptr->fx_media_hidden_sectors, + media_ptr->fx_media_driver_sectors, unaligned_buffer) == FX_SUCCESS) + { + media_ptr->fx_media_driver_status = FX_SUCCESS; + } + + break; + } + + case FX_DRIVER_FLUSH: + { + /* Return driver success. */ + media_ptr->fx_media_driver_status = FX_SUCCESS; + break; + } + + case FX_DRIVER_ABORT: + { + /* Return driver success. */ + media_ptr->fx_media_driver_status = FX_SUCCESS; + + FX_STM32_SD_POST_ABORT(media_ptr); + break; + } + + case FX_DRIVER_BOOT_READ: + { + /* the boot sector is the sector zero */ + status = sd_read_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer); + + if (status != FX_SUCCESS) + { + media_ptr->fx_media_driver_status = status; + break; + } + + /* Check if the sector 0 is the actual boot sector, otherwise calculate the offset into it. + Please note that this should belong to higher level of MW to do this check and it is here + as a temporary work solution */ + + partition_start = 0; + + status = _fx_partition_offset_calculate(media_ptr -> fx_media_driver_buffer, 0, + &partition_start, &partition_size); + + /* Check partition read error. */ + if (status) + { + /* Unsuccessful driver request. */ + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + break; + } + + /* Now determine if there is a partition... */ + if (partition_start) + { + + if (check_sd_status(FX_STM32_SD_INSTANCE) != 0) + { + media_ptr->fx_media_driver_status = FX_IO_ERROR; + break; + } + + /* Yes, now lets read the actual boot record. */ + status = sd_read_data(media_ptr, partition_start, media_ptr->fx_media_driver_sectors, unaligned_buffer); + + if (status != FX_SUCCESS) + { + media_ptr->fx_media_driver_status = status; + break; + } + } + + /* Successful driver request. */ + media_ptr -> fx_media_driver_status = FX_SUCCESS; + break; + } + + case FX_DRIVER_BOOT_WRITE: + { + status = sd_write_data(media_ptr, 0, media_ptr->fx_media_driver_sectors, unaligned_buffer); + + media_ptr->fx_media_driver_status = status; + + break; + } + + default: + { + media_ptr->fx_media_driver_status = FX_IO_ERROR; + break; + } + } +} + +/** +* @brief Read data from uSD into destination buffer +* @param FX_MEDIA *media_ptr a pointer the main FileX structure +* @param ULONG start_sector first sector to start reading from +* @param UINT num_sectors number of sectors to be read +* @param UINT use_scratch_buffer to enable scratch buffer usage or not. +* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise +*/ + +static UINT sd_read_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer) +{ + INT i = 0; + UINT status; + UCHAR *read_addr; + + /* perform the Pre read operations */ + FX_STM32_SD_PRE_READ_TRANSFER(media_ptr); + + if (use_scratch_buffer) + { + read_addr = media_ptr->fx_media_driver_buffer; + + for (i = 0; i < num_sectors; i++) + { + /* Start reading into the scratch buffer */ + status = fx_stm32_sd_read_blocks(FX_STM32_SD_INSTANCE, (UINT *)scratch, (UINT)start_sector++, 1); + + if (status != 0) + { + /* read error occurred, call the error handler code then return immediately */ + FX_STM32_SD_READ_TRANSFER_ERROR(status); + return FX_IO_ERROR; + } + + /* wait for read transfer notification */ + FX_STM32_SD_READ_CPLT_NOTIFY(); + +#if (FX_STM32_SD_CACHE_MAINTENANCE == 1) + invalidate_cache_by_addr((uint32_t*)scratch, FX_STM32_SD_DEFAULT_SECTOR_SIZE); +#endif + + _fx_utility_memory_copy(scratch, read_addr, FX_STM32_SD_DEFAULT_SECTOR_SIZE); + read_addr += FX_STM32_SD_DEFAULT_SECTOR_SIZE; + } + + /* Check if all sectors were read */ + if (i == num_sectors) + { + status = FX_SUCCESS; + } + else + { + status = FX_BUFFER_ERROR; + } + } + else + { + + status = fx_stm32_sd_read_blocks(FX_STM32_SD_INSTANCE, (UINT *)media_ptr->fx_media_driver_buffer, (UINT)start_sector, num_sectors); + + if (status != 0) + { + /* read error occurred, call the error handler code then return immediately */ + FX_STM32_SD_READ_TRANSFER_ERROR(status); + + return FX_IO_ERROR; + } + + /* wait for read transfer notification */ + FX_STM32_SD_READ_CPLT_NOTIFY(); + +#if (FX_STM32_SD_CACHE_MAINTENANCE == 1) + invalidate_cache_by_addr((uint32_t*)media_ptr->fx_media_driver_buffer, num_sectors * FX_STM32_SD_DEFAULT_SECTOR_SIZE); +#endif + + status = FX_SUCCESS; + } + + /* Operation finished, call the post read macro if defined */ + + FX_STM32_SD_POST_READ_TRANSFER(media_ptr); + return status; +} + +/** +* @brief write data buffer into the uSD +* @param FX_MEDIA *media_ptr a pointer the main FileX structure +* @param ULONG start_sector first sector to start writing from +* @param UINT num_sectors number of sectors to be written +* @param UINT use_scratch_buffer to enable scratch buffer usage or not. +* @retval FX_SUCCESS on success FX_BUFFER_ERROR / FX_ACCESS_ERROR / FX_IO_ERROR otherwise +*/ + +static UINT sd_write_data(FX_MEDIA *media_ptr, ULONG start_sector, UINT num_sectors, UINT use_scratch_buffer) +{ + INT i = 0; + UINT status; + UCHAR *write_addr; + + /* call Pre write operation macro */ + FX_STM32_SD_PRE_WRITE_TRANSFER(media_ptr); + + if (use_scratch_buffer) + { + write_addr = media_ptr->fx_media_driver_buffer; + + for (i = 0; i < num_sectors; i++) + { + _fx_utility_memory_copy(write_addr, scratch, FX_STM32_SD_DEFAULT_SECTOR_SIZE); + write_addr += FX_STM32_SD_DEFAULT_SECTOR_SIZE; + +#if (FX_STM32_SD_CACHE_MAINTENANCE == 1) + /* Clean the DCache to make the SD DMA see the actual content of the scratch buffer */ + clean_cache_by_addr((uint32_t*)scratch, FX_STM32_SD_DEFAULT_SECTOR_SIZE); +#endif + + status = fx_stm32_sd_write_blocks(FX_STM32_SD_INSTANCE, (UINT *)scratch, (UINT)start_sector++, 1); + + if (status != 0) + { + /* in case of error call the error handling macro */ + FX_STM32_SD_WRITE_TRANSFER_ERROR(status); + return FX_IO_ERROR; + } + + /* */ + FX_STM32_SD_WRITE_CPLT_NOTIFY(); + } + + if (i == num_sectors) + { + status = FX_SUCCESS; + } + else + { + status = FX_BUFFER_ERROR; + } + } + else + { +#if (FX_STM32_SD_CACHE_MAINTENANCE == 1) + clean_cache_by_addr((uint32_t*)media_ptr->fx_media_driver_buffer, num_sectors * FX_STM32_SD_DEFAULT_SECTOR_SIZE); +#endif + status = fx_stm32_sd_write_blocks(FX_STM32_SD_INSTANCE, (UINT *)media_ptr->fx_media_driver_buffer, (UINT)start_sector, num_sectors); + + if (status != 0) + { + FX_STM32_SD_WRITE_TRANSFER_ERROR(status); + return FX_IO_ERROR; + } + + /* when defined, wait for the write notification */ + FX_STM32_SD_WRITE_CPLT_NOTIFY(); + + status = FX_SUCCESS; + } + + /* perform post write operations */ + FX_STM32_SD_POST_WRITE_TRANSFER(media_ptr); + + + return status; +} diff --git a/src/Middlewares/ST/filex/common/inc/fx_api.h b/src/Middlewares/ST/filex/common/inc/fx_api.h new file mode 100644 index 00000000..eb63b9de --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_api.h @@ -0,0 +1,1671 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Application Interface */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* fx_api.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic Application Interface (API) to the */ +/* high-performance FileX FAT compatible embedded file system. */ +/* All service prototypes and data structure definitions are defined */ +/* in this file. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* updated product constants, */ +/* and added conditionals to */ +/* disable few declarations */ +/* for code size reduction, */ +/* resulting in version 6.1 */ +/* 11-09-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.2 */ +/* 12-31-2020 William E. Lamie Modified comment(s), and */ +/* updated product constants, */ +/* resulting in version 6.1.3 */ +/* 03-02-2021 William E. Lamie Modified comment(s), and */ +/* added standalone support, */ +/* resulting in version 6.1.5 */ +/* 04-02-2021 William E. Lamie Modified comment(s), and */ +/* updated product constants, */ +/* resulting in version 6.1.6 */ +/* 06-02-2021 William E. Lamie Modified comment(s), and */ +/* updated product constants, */ +/* resulting in version 6.1.7 */ +/* 08-02-2021 William E. Lamie Modified comment(s), and */ +/* updated product constants, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), and */ +/* removed fixed sector */ +/* size in exFAT, fixed */ +/* errors without cache, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef FX_API_H +#define FX_API_H + + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Disable warning of parameter not used. */ +#ifndef FX_PARAMETER_NOT_USED +#define FX_PARAMETER_NOT_USED(p) ((void)(p)) +#endif /* FX_PARAMETER_NOT_USED */ + + +/* Disable ThreadX error checking for internal FileX source code. */ + +#ifdef FX_SOURCE_CODE +#ifndef TX_DISABLE_ERROR_CHECKING +#define TX_DISABLE_ERROR_CHECKING +#endif +#endif + + +/* Include the FileX port-specific file. */ + +#include "fx_port.h" + +/* Define compiler library include files */ + +#ifdef FX_STANDALONE_ENABLE +#include "string.h" +#endif + +/* Define the major/minor version information that can be used by the application + and the FileX source as well. */ + +#define AZURE_RTOS_FILEX +#define FILEX_MAJOR_VERSION 6 +#define FILEX_MINOR_VERSION 1 +#define FILEX_PATCH_VERSION 10 + +/* Define the following symbols for backward compatibility */ +#define EL_PRODUCT_FILEX + +#ifdef FX_STANDALONE_ENABLE + +/* FileX will be used without Azure RTOS ThreadX */ + +#ifndef FX_SINGLE_THREAD +#define FX_SINGLE_THREAD +#endif /* !FX_SINGLE_THREAD */ + + +/* FileX will be used with local path logic disabled */ + +#ifndef FX_NO_LOCAL_PATH +#define FX_NO_LOCAL_PATH +#endif /* !FX_NO_LOCAL_PATH */ + + +/* FileX is built without update to the time parameters. */ + +#ifndef FX_NO_TIMER +#define FX_NO_TIMER +#endif /* !FX_NO_TIMER */ + +#endif + + +/* Override the interrupt protection provided in FileX port files to simply use ThreadX protection, + which is often in-line assembly. */ + +#ifndef FX_LEGACY_INTERRUPT_PROTECTION +#undef FX_INT_SAVE_AREA +#undef FX_DISABLE_INTS +#undef FX_RESTORE_INTS +#define FX_INT_SAVE_AREA TX_INTERRUPT_SAVE_AREA +#define FX_DISABLE_INTS TX_DISABLE +#define FX_RESTORE_INTS TX_RESTORE +#endif + + +/* Define the update rate of the system timer. These values may also be defined at the command + line when compiling the fx_system_initialize.c module in the FileX library build. Alternatively, they can + be modified in this file. Note: the update rate must be an even number of seconds greater + than or equal to 2, which is the minimal update rate for FAT time. */ + +#ifndef FX_UPDATE_RATE_IN_SECONDS +#define FX_UPDATE_RATE_IN_SECONDS 10 /* Update time at 10 second intervals */ +#endif + +#ifndef FX_UPDATE_RATE_IN_TICKS +#define FX_UPDATE_RATE_IN_TICKS 1000 /* Same update rate, but in ticks */ +#endif + + +/* Determine if fault tolerance is selected. If so, turn on the old fault tolerant options - + if they are not defined already. */ + +#ifdef FX_ENABLE_FAULT_TOLERANT +#ifndef FX_FAULT_TOLERANT_DATA +#define FX_FAULT_TOLERANT_DATA +#endif +#ifndef FX_FAULT_TOLERANT +#define FX_FAULT_TOLERANT +#endif +#endif + + +/* Determine if cache is disabled. If so, disable direct read sector cache. */ +#ifdef FX_DISABLE_CACHE +#ifndef FX_DISABLE_DIRECT_DATA_READ_CACHE_FILL +#define FX_DISABLE_DIRECT_DATA_READ_CACHE_FILL +#endif +#endif + + +/* Determine if local paths are enabled and if the local path setup code has not been defined. + If so, define the default local path setup code for files that reference the local path. */ + +#ifndef FX_NO_LOCAL_PATH +#ifndef FX_LOCAL_PATH_SETUP +#ifndef FX_SINGLE_THREAD +#define FX_LOCAL_PATH_SETUP extern TX_THREAD *_tx_thread_current_ptr; +#else +#define FX_NO_LOCAL_PATH +#endif +#endif +#endif + +/* Determine if tracing is enabled. */ + +#if defined(TX_ENABLE_EVENT_TRACE) && !defined(FX_STANDALONE_ENABLE) + + +/* Trace is enabled. Remap calls so that interrupts can be disabled around the actual event logging. */ + +#include "tx_trace.h" + + +/* Define the object types in FileX, if not defined. */ + +#ifndef FX_TRACE_OBJECT_TYPE_MEDIA +#define FX_TRACE_OBJECT_TYPE_MEDIA 9 /* P1 = FAT cache size, P2 = sector cache size */ +#define FX_TRACE_OBJECT_TYPE_FILE 10 /* none */ +#endif + + +/* Define event filters that can be used to selectively disable certain events or groups of events. */ + +#define FX_TRACE_ALL_EVENTS 0x00007800 /* All FileX events */ +#define FX_TRACE_INTERNAL_EVENTS 0x00000800 /* FileX internal events */ +#define FX_TRACE_MEDIA_EVENTS 0x00001000 /* FileX media events */ +#define FX_TRACE_DIRECTORY_EVENTS 0x00002000 /* FileX directory events */ +#define FX_TRACE_FILE_EVENTS 0x00004000 /* FileX file events */ + + +/* Define the trace events in FileX, if not defined. */ + +/* Define FileX Trace Events, along with a brief description of the additional information fields, + where I1 -> Information Field 1, I2 -> Information Field 2, etc. */ + +/* Define the FileX internal events first. */ + +#ifndef FX_TRACE_INTERNAL_LOG_SECTOR_CACHE_MISS +#define FX_TRACE_INTERNAL_LOG_SECTOR_CACHE_MISS 201 /* I1 = media ptr, I2 = sector, I3 = total misses, I4 = cache size */ +#define FX_TRACE_INTERNAL_DIR_CACHE_MISS 202 /* I1 = media ptr, I2 = total misses */ +#define FX_TRACE_INTERNAL_MEDIA_FLUSH 203 /* I1 = media ptr, I2 = dirty sectors */ +#define FX_TRACE_INTERNAL_DIR_ENTRY_READ 204 /* I1 = media ptr */ +#define FX_TRACE_INTERNAL_DIR_ENTRY_WRITE 205 /* I1 = media ptr */ +#define FX_TRACE_INTERNAL_IO_DRIVER_READ 206 /* I1 = media ptr, I2 = sector, I3 = number of sectors, I4 = buffer */ +#define FX_TRACE_INTERNAL_IO_DRIVER_WRITE 207 /* I1 = media ptr, I2 = sector, I3 = number of sectors, I4 = buffer */ +#define FX_TRACE_INTERNAL_IO_DRIVER_FLUSH 208 /* I1 = media ptr */ +#define FX_TRACE_INTERNAL_IO_DRIVER_ABORT 209 /* I1 = media ptr */ +#define FX_TRACE_INTERNAL_IO_DRIVER_INIT 210 /* I1 = media ptr */ +#define FX_TRACE_INTERNAL_IO_DRIVER_BOOT_READ 211 /* I1 = media ptr, I2 = buffer */ +#define FX_TRACE_INTERNAL_IO_DRIVER_RELEASE_SECTORS 212 /* I1 = media ptr, I2 = sector, I3 = number of sectors */ +#define FX_TRACE_INTERNAL_IO_DRIVER_BOOT_WRITE 213 /* I1 = media ptr, I2 = buffer */ +#define FX_TRACE_INTERNAL_IO_DRIVER_UNINIT 214 /* I1 = media ptr */ + + +/* Define the FileX API events. */ + +#define FX_TRACE_DIRECTORY_ATTRIBUTES_READ 220 /* I1 = media ptr, I2 = directory name, I3 = attributes */ +#define FX_TRACE_DIRECTORY_ATTRIBUTES_SET 221 /* I1 = media ptr, I2 = directory name, I3 = attributes */ +#define FX_TRACE_DIRECTORY_CREATE 222 /* I1 = media ptr, I2 = directory name */ +#define FX_TRACE_DIRECTORY_DEFAULT_GET 223 /* I1 = media ptr, I2 = return path name */ +#define FX_TRACE_DIRECTORY_DEFAULT_SET 224 /* I1 = media ptr, I2 = new path name */ +#define FX_TRACE_DIRECTORY_DELETE 225 /* I1 = media ptr, I2 = directory name */ +#define FX_TRACE_DIRECTORY_FIRST_ENTRY_FIND 226 /* I1 = media ptr, I2 = directory name */ +#define FX_TRACE_DIRECTORY_FIRST_FULL_ENTRY_FIND 227 /* I1 = media ptr, I2 = directory name */ +#define FX_TRACE_DIRECTORY_INFORMATION_GET 228 /* I1 = media ptr, I2 = directory name */ +#define FX_TRACE_DIRECTORY_LOCAL_PATH_CLEAR 229 /* I1 = media ptr */ +#define FX_TRACE_DIRECTORY_LOCAL_PATH_GET 230 /* I1 = media ptr, I2 = return path name */ +#define FX_TRACE_DIRECTORY_LOCAL_PATH_RESTORE 231 /* I1 = media ptr, I2 = local path ptr */ +#define FX_TRACE_DIRECTORY_LOCAL_PATH_SET 232 /* I1 = media ptr, I2 = local path ptr, I3 = new path name */ +#define FX_TRACE_DIRECTORY_LONG_NAME_GET 233 /* I1 = media ptr, I2 = short file name, I3 = long file name */ +#define FX_TRACE_DIRECTORY_NAME_TEST 234 /* I1 = media ptr, I2 = directory name */ +#define FX_TRACE_DIRECTORY_NEXT_ENTRY_FIND 235 /* I1 = media ptr, I2 = directory name */ +#define FX_TRACE_DIRECTORY_NEXT_FULL_ENTRY_FIND 236 /* I1 = media ptr, I2 = directory name */ +#define FX_TRACE_DIRECTORY_RENAME 237 /* I1 = media ptr, I2 = old directory name, I3 = new directory name */ +#define FX_TRACE_DIRECTORY_SHORT_NAME_GET 238 /* I1 = media ptr, I2 = long file name, I3 = short file name */ +#define FX_TRACE_FILE_ALLOCATE 239 /* I1 = file ptr, I2 = size I3 = previous size, I4 = new size */ +#define FX_TRACE_FILE_ATTRIBUTES_READ 240 /* I1 = media ptr, I2 = file name, I3 = attributes */ +#define FX_TRACE_FILE_ATTRIBUTES_SET 241 /* I1 = media ptr, I2 = file name, I3 = attributes */ +#define FX_TRACE_FILE_BEST_EFFORT_ALLOCATE 242 /* I1 = file ptr, I2 = size, I3 = actual_size_allocated */ +#define FX_TRACE_FILE_CLOSE 243 /* I1 = file ptr, I3 = file size */ +#define FX_TRACE_FILE_CREATE 244 /* I1 = media ptr, I2 = file name */ +#define FX_TRACE_FILE_DATE_TIME_SET 245 /* I1 = media ptr, I2 = file name, I3 = year, I4 = month */ +#define FX_TRACE_FILE_DELETE 246 /* I1 = media ptr, I2 = file name */ +#define FX_TRACE_FILE_OPEN 247 /* I1 = media ptr, I2 = file ptr, I3 = file name, I4 = open type */ +#define FX_TRACE_FILE_READ 248 /* I1 = file ptr, I2 = buffer ptr, I3 = request size I4 = actual size */ +#define FX_TRACE_FILE_RELATIVE_SEEK 249 /* I1 = file ptr, I2 = byte offset, I3 = seek from, I4 = previous offset */ +#define FX_TRACE_FILE_RENAME 250 /* I1 = media ptr, I2 = old file name, I3 = new file name */ +#define FX_TRACE_FILE_SEEK 251 /* I1 = file ptr, I2 = byte offset, I3 = previous offset */ +#define FX_TRACE_FILE_TRUNCATE 252 /* I1 = file ptr, I2 = size, I3 = previous size, I4 = new size */ +#define FX_TRACE_FILE_TRUNCATE_RELEASE 253 /* I1 = file ptr, I2 = size, I3 = previous size, I4 = new size */ +#define FX_TRACE_FILE_WRITE 254 /* I1 = file ptr, I2 = buffer ptr, I3 = size, I4 = bytes written */ +#define FX_TRACE_MEDIA_ABORT 255 /* I1 = media ptr */ +#define FX_TRACE_MEDIA_CACHE_INVALIDATE 256 /* I1 = media ptr */ +#define FX_TRACE_MEDIA_CHECK 257 /* I1 = media ptr, I2 = scratch memory, I3 = scratch memory size, I4 =errors*/ +#define FX_TRACE_MEDIA_CLOSE 258 /* I1 = media ptr */ +#define FX_TRACE_MEDIA_FLUSH 259 /* I1 = media ptr */ +#define FX_TRACE_MEDIA_FORMAT 260 /* I1 = media ptr, I2 = root entries, I3 = sectors, I4 = sectors per cluster*/ +#define FX_TRACE_MEDIA_OPEN 261 /* I1 = media ptr, I2 = media driver, I3 = memory ptr, I4 = memory size */ +#define FX_TRACE_MEDIA_READ 262 /* I1 = media ptr, I2 = logical sector, I3 = buffer ptr, I4 = bytes read */ +#define FX_TRACE_MEDIA_SPACE_AVAILABLE 263 /* I1 = media ptr, I2 = available bytes ptr, I3 = available clusters */ +#define FX_TRACE_MEDIA_VOLUME_GET 264 /* I1 = media ptr, I2 = volume name, I3 = volume source */ +#define FX_TRACE_MEDIA_VOLUME_SET 265 /* I1 = media ptr, I2 = volume name */ +#define FX_TRACE_MEDIA_WRITE 266 /* I1 = media ptr, I2 = logical_sector, I3 = buffer_ptr, I4 = byte written */ +#define FX_TRACE_SYSTEM_DATE_GET 267 /* I1 = year, I2 = month, I3 = day */ +#define FX_TRACE_SYSTEM_DATE_SET 268 /* I1 = year, I2 = month, I3 = day */ +#define FX_TRACE_SYSTEM_INITIALIZE 269 /* None */ +#define FX_TRACE_SYSTEM_TIME_GET 270 /* I1 = hour, I2 = minute, I3 = second */ +#define FX_TRACE_SYSTEM_TIME_SET 271 /* I1 = hour, I2 = minute, I3 = second */ +#define FX_TRACE_UNICODE_DIRECTORY_CREATE 272 /* I1 = media ptr, I2 = source unicode, I3 = source length, I4 = short_name */ +#define FX_TRACE_UNICODE_DIRECTORY_RENAME 273 /* I1 = media ptr, I2 = source unicode, I3 = source length, I4 = new_name */ +#define FX_TRACE_UNICODE_FILE_CREATE 274 /* I1 = media ptr, I2 = source unicode, I3 = source length, I4 = short name */ +#define FX_TRACE_UNICODE_FILE_RENAME 275 /* I1 = media ptr, I2 = source unicode, I3 = source length, I4 = new name */ +#define FX_TRACE_UNICODE_LENGTH_GET 276 /* I1 = unicode name, I2 = length */ +#define FX_TRACE_UNICODE_NAME_GET 277 /* I1 = media ptr, I2 = source short name, I3 = unicode name, I4 = length */ +#define FX_TRACE_UNICODE_SHORT_NAME_GET 278 /* I1 = media ptr, I2 = source unicode name, I3 = length, I4 = short name */ +#endif + + +/* Map the trace macros to internal FileX versions so we can get interrupt protection. */ + +#ifdef FX_SOURCE_CODE + +#define FX_TRACE_OBJECT_REGISTER(t, p, n, a, b) _fx_trace_object_register(t, (VOID *)p, (CHAR *)n, (ULONG)a, (ULONG)b); +#define FX_TRACE_OBJECT_UNREGISTER(o) _fx_trace_object_unregister((VOID *)o); +#define FX_TRACE_IN_LINE_INSERT(i, a, b, c, d, f, g, h) _fx_trace_event_insert((ULONG)i, (ULONG)a, (ULONG)b, (ULONG)c, (ULONG)d, (ULONG)f, g, h); +#define FX_TRACE_EVENT_UPDATE(e, t, i, a, b, c, d) _fx_trace_event_update((TX_TRACE_BUFFER_ENTRY *)e, (ULONG)t, (ULONG)i, (ULONG)a, (ULONG)b, (ULONG)c, (ULONG)d); + + +/* Define FileX trace prototypes. */ + +VOID _fx_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2); +VOID _fx_trace_object_unregister(VOID *object_ptr); +VOID _fx_trace_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, TX_TRACE_BUFFER_ENTRY **current_event, ULONG *current_timestamp); +VOID _fx_trace_event_update(TX_TRACE_BUFFER_ENTRY *event, ULONG timestamp, ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4); + +#endif + +#else +#define FX_TRACE_OBJECT_REGISTER(t, p, n, a, b) +#define FX_TRACE_OBJECT_UNREGISTER(o) +#define FX_TRACE_IN_LINE_INSERT(i, a, b, c, d, f, g, h) +#define FX_TRACE_EVENT_UPDATE(e, t, i, a, b, c, d) +#endif + + +/* Define basic constants for FileX. */ + +#define FX_MEDIA_ID ((ULONG)0x4D454449) +#define FX_MEDIA_CLOSED_ID ((ULONG)0x4D454443) +#define FX_MEDIA_ABORTED_ID ((ULONG)0x4D454441) + +#define FX_FILE_ID ((ULONG)0x46494C45) +#define FX_FILE_CLOSED_ID ((ULONG)0x46494C43) +#define FX_FILE_ABORTED_ID ((ULONG)0x46494C41) + + +/* The maximum path includes the entire path and the file name. */ + +#ifndef FX_MAXIMUM_PATH +#define FX_MAXIMUM_PATH 256 +#endif + + +/* Define directory entry name sizes. Directory entries are found in the + root directory and in directory files (sub-directories). Each directory + entry has a short file name which is a fixed maximum of 13 characters and + and optional 255 character long file name. */ + +#ifndef FX_MAX_LONG_NAME_LEN +#define FX_MAX_LONG_NAME_LEN 256 /* Minimum value is 13, Maximum value is 256. */ +#endif + +#define FX_MAX_SHORT_NAME_LEN 13 /* Only allowed value is 13. */ + +#ifndef FX_MAX_LAST_NAME_LEN +#define FX_MAX_LAST_NAME_LEN 256 /* Should be as large or larger than FX_MAX_LONG_NAME_LEN. */ +#endif + + +/* Define constants related to the logical sector cache. These constants represent the maximum + number of logical sectors that can be cached. The actual number of logical sectors in the + cache is determined by the amount of memory supplied to fx_media_open for the FX_MEDIA + instance. */ + +#ifndef FX_MAX_SECTOR_CACHE +#define FX_MAX_SECTOR_CACHE 256 /* Maximum size of logical sector cache, + minimum value of 2 all other values must + be a power of 2. */ +#endif + +/* Define the mask for the hash index into the logical sector cache. If the logical sector cache + determined by the amount of memory supplied by the application to fx_media_open is larger than + FX_SECTOR_CACHE_HASH_ENABLE (usually 16) and can satisfy FX_MAX_SECTOR_CACHE sectors, the cache + is divided into 4 entry pieces (FX_SECTOR_CACHE_DEPTH) that are indexed by the formula: + + index = (cluster & media_ptr -> fx_media_sector_cache_hash_mask) * FX_SECTOR_CACHE_LEVELS + + The FX_SECTOR_CACHE_DEPTH define must not be changed unless the logical sector read/write + code is also changed. */ + +#define FX_SECTOR_CACHE_HASH_ENABLE 16 +#define FX_SECTOR_CACHE_DEPTH 4 + +#ifndef FX_FAT_MAP_SIZE +#define FX_FAT_MAP_SIZE 128 /* Minimum 1, maximum any. This represents how many 32-bit words used for the written FAT sector bit map. */ +#endif + +#ifndef FX_MAX_FAT_CACHE +#define FX_MAX_FAT_CACHE 16 /* Minimum value is 8, all values must be a power of 2. */ +#endif + + +/* Define the size of fault tolerant cache, which is used when freeing FAT chain. */ + +#ifndef FX_FAULT_TOLERANT_CACHE_SIZE +#define FX_FAULT_TOLERANT_CACHE_SIZE 1024 +#endif /* FX_FAULT_TOLERANT_CACHE_SIZE */ + + +/* Define the mask for the hash index into the FAT table. The FAT cache is divided into 4 entry pieces + that are indexed by the formula: + + index = (cluster & FX_FAT_CACHE_HASH_MASK) * FX_FAT_CACHE_LEVELS + + The FX_FAT_CACHE_DEPTH define must not be changed unless the FAT entry read/write code is also changed. */ + +#define FX_FAT_CACHE_DEPTH 4 +#define FX_FAT_CACHE_HASH_MASK ((FX_MAX_FAT_CACHE / FX_FAT_CACHE_DEPTH) - 1) + + +/* FileX API input parameters and general constants. */ + +#define FX_TRUE 1 +#define FX_FALSE 0 +#define FX_NULL 0 +#define FX_OPEN_FOR_READ 0 +#define FX_OPEN_FOR_WRITE 1 +#define FX_OPEN_FOR_READ_FAST 2 + +#define FX_12_BIT_FAT_SIZE 4086 +#define FX_16_BIT_FAT_SIZE 65525 +#define FX_MAX_12BIT_CLUST 0x0FF0 +#define FX_SIGN_EXTEND 0xF000 +#define FX_12BIT_SIZE 3 /* 2 FAT entries per 3 bytes */ + +#define FX_FAT_ENTRY_START 2 +#define FX_DIR_ENTRY_SIZE 32 +#define FX_DIR_NAME_SIZE 8 +#define FX_DIR_EXT_SIZE 3 +#define FX_DIR_RESERVED 8 +#define FX_DIR_ENTRY_FREE 0xE5 +#define FX_DIR_ENTRY_DONE 0x00 +#define FX_READ_ONLY 0x01 +#define FX_HIDDEN 0x02 +#define FX_SYSTEM 0x04 +#define FX_VOLUME 0x08 +#define FX_DIRECTORY 0x10 +#define FX_ARCHIVE 0x20 +#define FX_LONG_NAME (FX_READ_ONLY | FX_HIDDEN | FX_SYSTEM | FX_VOLUME) +#define FX_LONG_NAME_ENTRY_LEN 13 + + +/* Define FAT FAT entry values. */ + +#define FX_FREE_CLUSTER 0x0000 +#define FX_NOT_USED 0x0001 +#define FX_RESERVED_1 0xFFF0 +#define FX_RESERVED_2 0xFFF6 +#define FX_BAD_CLUSTER 0xFFF7 +#define FX_LAST_CLUSTER_1 0xFFF8 +#define FX_LAST_CLUSTER_2 0xFFFF + +#define FX_RESERVED_1_32 0x0FFFFFF0 +#define FX_RESERVED_2_32 0x0FFFFFF6 +#define FX_BAD_CLUSTER_32 0x0FFFFFF7 +#define FX_LAST_CLUSTER_1_32 0x0FFFFFF8 +#define FX_LAST_CLUSTER_2_32 0x0FFFFFFF + + +/* Define time/date FAT constants. */ + +#define FX_YEAR_SHIFT 9 +#define FX_MONTH_SHIFT 5 +#define FX_HOUR_SHIFT 11 +#define FX_MINUTE_SHIFT 5 +#define FX_YEAR_MASK 0x7F +#define FX_MONTH_MASK 0x0F +#define FX_DAY_MASK 0x1F +#define FX_HOUR_MASK 0x1F +#define FX_MINUTE_MASK 0x3F +#define FX_SECOND_MASK 0x1F +#define FX_BASE_YEAR 1980 +#define FX_MAXIMUM_YEAR 2107 +#define FX_MAXIMUM_MONTH 12 +#define FX_MAXIMUM_HOUR 23 +#define FX_MAXIMUM_MINUTE 59 +#define FX_MAXIMUM_SECOND 59 +#define FX_INITIAL_DATE 0x4A21 /* 01-01-2017 */ +#define FX_INITIAL_TIME 0x0000 /* 12:00 am */ + +/* FileX API return values. */ + +#define FX_SUCCESS 0x00 +#define FX_BOOT_ERROR 0x01 +#define FX_MEDIA_INVALID 0x02 +#define FX_FAT_READ_ERROR 0x03 +#define FX_NOT_FOUND 0x04 +#define FX_NOT_A_FILE 0x05 +#define FX_ACCESS_ERROR 0x06 +#define FX_NOT_OPEN 0x07 +#define FX_FILE_CORRUPT 0x08 +#define FX_END_OF_FILE 0x09 +#define FX_NO_MORE_SPACE 0x0A +#define FX_ALREADY_CREATED 0x0B +#define FX_INVALID_NAME 0x0C +#define FX_INVALID_PATH 0x0D +#define FX_NOT_DIRECTORY 0x0E +#define FX_NO_MORE_ENTRIES 0x0F +#define FX_DIR_NOT_EMPTY 0x10 +#define FX_MEDIA_NOT_OPEN 0x11 +#define FX_INVALID_YEAR 0x12 +#define FX_INVALID_MONTH 0x13 +#define FX_INVALID_DAY 0x14 +#define FX_INVALID_HOUR 0x15 +#define FX_INVALID_MINUTE 0x16 +#define FX_INVALID_SECOND 0x17 +#define FX_PTR_ERROR 0x18 +#define FX_INVALID_ATTR 0x19 +#define FX_CALLER_ERROR 0x20 +#define FX_BUFFER_ERROR 0x21 +#define FX_NOT_IMPLEMENTED 0x22 +#define FX_WRITE_PROTECT 0x23 +#define FX_INVALID_OPTION 0x24 +#define FX_SECTOR_INVALID 0x89 +#define FX_IO_ERROR 0x90 +#define FX_NOT_ENOUGH_MEMORY 0x91 +#define FX_ERROR_FIXED 0x92 +#define FX_ERROR_NOT_FIXED 0x93 +#define FX_NOT_AVAILABLE 0x94 +#define FX_INVALID_CHECKSUM 0x95 +#define FX_READ_CONTINUE 0x96 +#define FX_INVALID_STATE 0x97 + + +/* FileX driver interface constants. */ + +#define FX_DRIVER_READ 0 +#define FX_DRIVER_WRITE 1 +#define FX_DRIVER_FLUSH 2 +#define FX_DRIVER_ABORT 3 +#define FX_DRIVER_INIT 4 +#define FX_DRIVER_BOOT_READ 5 +#define FX_DRIVER_RELEASE_SECTORS 6 +#define FX_DRIVER_BOOT_WRITE 7 +#define FX_DRIVER_UNINIT 8 + + +/* Define relative seek constants. */ + +#define FX_SEEK_BEGIN 0 +#define FX_SEEK_END 1 +#define FX_SEEK_FORWARD 2 +#define FX_SEEK_BACK 3 + + +/* Define types for logical sectors. This information is passed to the driver + as additional information. */ + +#define FX_UNKNOWN_SECTOR 0 +#define FX_BOOT_SECTOR 1 +#define FX_FAT_SECTOR 2 +#define FX_DIRECTORY_SECTOR 3 +#define FX_DATA_SECTOR 4 + + +/* Define media diagnostic constants. */ + +#define FX_FAT_CHAIN_ERROR 0x01 +#define FX_DIRECTORY_ERROR 0x02 +#define FX_LOST_CLUSTER_ERROR 0x04 +#define FX_FILE_SIZE_ERROR 0x08 + + +/* Define boot record offset constants. */ + +#define FX_JUMP_INSTR 0x000 +#define FX_OEM_NAME 0x003 +#define FX_BYTES_SECTOR 0x00B +#define FX_SECTORS_CLUSTER 0x00D +#define FX_RESERVED_SECTORS 0x00E +#define FX_NUMBER_OF_FATS 0x010 +#define FX_ROOT_DIR_ENTRIES 0x011 +#define FX_SECTORS 0x013 +#define FX_MEDIA_TYPE 0x015 +#define FX_SECTORS_PER_FAT 0x016 +#define FX_SECTORS_PER_TRK 0x018 +#define FX_HEADS 0x01A +#define FX_HIDDEN_SECTORS 0x01C +#define FX_HUGE_SECTORS 0x020 +#define FX_DRIVE_NUMBER 0x024 +#define FX_RESERVED 0x025 +#define FX_BOOT_SIG 0x026 +#define FX_BOOT_SIG_32 0x042 +#define FX_VOLUME_ID 0x027 +#define FX_VOLUME_ID_32 0x043 +#define FX_VOLUME_LABEL 0x02B +#define FX_VOLUME_LABEL_32 0x047 +#define FX_FILE_SYSTEM_TYPE 0x036 +#define FX_SIG_OFFSET 0x1FE +#define FX_ROOT_CLUSTER_32 0x02C +#define FX_SECTORS_PER_FAT_32 0x024 +#define FX_SIG_BYTE_1 0x55 +#define FX_SIG_BYTE_2 0xAA + + +/* If not-defined, default port-specific processing extensions to white space. */ + +#ifndef FX_FILE_OPEN_EXTENSION +#define FX_FILE_OPEN_EXTENSION +#endif + +#ifndef FX_DIRECTORY_ENTRY_READ_EXTENSION +#define FX_DIRECTORY_ENTRY_READ_EXTENSION +#endif + +#ifndef FX_DIRECTORY_ENTRY_WRITE_EXTENSION +#define FX_DIRECTORY_ENTRY_WRITE_EXTENSION +#endif + +#ifndef FX_UTILITY_FAT_ENTRY_READ_EXTENSION +#define FX_UTILITY_FAT_ENTRY_READ_EXTENSION +#endif + +#ifndef FX_UTILITY_FAT_ENTRY_WRITE_EXTENSION +#define FX_UTILITY_FAT_ENTRY_WRITE_EXTENSION +#endif + +#ifndef FX_UTILITY_LOGICAL_SECTOR_FLUSH_EXTENSION +#define FX_UTILITY_LOGICAL_SECTOR_FLUSH_EXTENSION +#endif + +#ifndef FX_UTILITY_LOGICAL_SECTOR_READ_EXTENSION +#define FX_UTILITY_LOGICAL_SECTOR_READ_EXTENSION +#endif + +#ifndef FX_UTILITY_LOGICAL_SECTOR_READ_EXTENSION_1 +#define FX_UTILITY_LOGICAL_SECTOR_READ_EXTENSION_1 +#endif + +#ifndef FX_UTILITY_LOGICAL_SECTOR_WRITE_EXTENSION +#define FX_UTILITY_LOGICAL_SECTOR_WRITE_EXTENSION +#endif + + +#ifdef FX_ENABLE_EXFAT + + +/* Define exFAT specific constants. */ + +#define FX_EF_MUST_BE_ZERO 11 /* Must be Zero Area 053 bytes */ +#define FX_EF_PARTITION_OFFSET 64 /* Partition Offset 008 bytes */ +#define FX_EF_VOLUME_LENGTH 72 /* Number of sectors on the Partition 008 bytes */ +#define FX_EF_FAT_OFFSET 80 /* Number of sectors before exFAT 004 bytes */ +#define FX_EF_FAT_LENGTH 84 /* Each FAT length in Sectors 004 bytes */ +#define FX_EF_CLUSTER_HEAP_OFFSET 88 /* Number of Sectors Before Cluster 004 bytes + Heap */ +#define FX_EF_CLUSTER_COUNT 92 /* Number of Clusters in the Cluster 004 bytes + Heap */ +#define FX_EF_FIRST_CLUSTER_OF_ROOT_DIR 96 /* Cluster index of the First 004 bytes + Cluster of the ROOT Directory */ +#define FX_EF_VOLUME_SERIAL_NUMBER 100 /* Volume Serial Number 004 bytes */ +#define FX_EF_FILE_SYSTEM_REVISION 104 /* File System Revision 002 bytes */ +#define FX_EF_VOLUME_FLAGS 106 /* Status of exFAT structures 002 bytes */ +#define FX_EF_BYTE_PER_SECTOR_SHIFT 108 /* log2(N),where N is the Number of 001 byte + Bytes per Sector */ +#define FX_EF_SECTOR_PER_CLUSTER_SHIFT 109 /* log2(N),where N is the Number of 001 byte + Sectors per Cluster */ +#define FX_EF_NUMBER_OF_FATS 110 /* Number of FATs 001 byte */ +#define FX_EF_DRIVE_SELECT 111 /* Extended INT13h driver number 001 byte */ +#define FX_EF_PERCENT_IN_USE 112 /* Percentage of Allocated Clusters 001 byte */ +#define FX_EF_RESERVED 113 /* Reserved 007 bytes */ +#define FX_EF_BOOT_CODE 120 /* Boot code area 390 bytes */ + +#define FX_RESERVED_1_exFAT 0xFFFFFFF8 +#define FX_RESERVED_2_exFAT 0xFFFFFFFE +#define FX_BAD_CLUSTER_exFAT 0xFFFFFFF7 +#define FX_LAST_CLUSTER_exFAT 0xFFFFFFFF + +#ifndef FX_MAX_EX_FAT_NAME_LEN +#define FX_MAX_EX_FAT_NAME_LEN 255 /* Only allowed value is 255 */ +#endif + +#ifndef BITS_PER_BYTE +#define BITS_PER_BYTE 8 +#endif +#define BITS_PER_BYTE_SHIFT 3 + + +#define FX_EXFAT_MAX_DIRECTORY_SIZE (256 * 1024 * 1024) /* 256 MB */ +#define FX_EXFAT_SIZE_OF_FAT_ELEMENT_SHIFT 2 + +#define FX_EXFAT_BIT_MAP_NUM_OF_CACHED_SECTORS 1 + +#define FX_EXFAT_BITMAP_CLUSTER_FREE 0 +#define FX_EXFAT_BITMAP_CLUSTER_OCCUPIED 1 + +#ifndef FX_EXFAT_MAX_CACHE_SIZE +#define FX_EXFAT_MAX_CACHE_SIZE 512 +#endif +#define FX_EXFAT_BITMAP_CACHE_SIZE FX_EXFAT_MAX_CACHE_SIZE + +/* exFAT System Area Layout */ + +#define FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE 12 + +#define FX_EXFAT_FAT_MAIN_BOOT_SECTOR_OFFSET 0 +#define FX_EXFAT_FAT_BACKUP_BOOT_SECTOR_OFFSET FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE + +#define FX_EXFAT_FAT_EXT_BOOT_SECTOR_OFFSET 1 +#define FX_EXFAT_FAT_OEM_PARAM_OFFSET 9 +#define FX_EXFAT_FAT_CHECK_SUM_OFFSET 11 + +#define FX_EXFAT_FAT_NUM_OF_SYSTEM_AREAS 2 + + +/* Define exFAT format parameters. */ + +#define EXFAT_MIN_NUM_OF_RESERVED_SECTORS 1 +#define EXFAT_BOOT_REGION_SIZE 24 +#define EXFAT_FAT_BITS 32 +#define EXFAT_FAT_FILE_SYS_REVISION 0x100 +#define EXFAT_FAT_VOLUME_FLAG 0x000 +#define EXFAT_FAT_NUM_OF_FATS 0x001 +#define EXFAT_FAT_DRIVE_SELECT 0x080 +#define EXFAT_FAT_VOLUME_NAME_FIELD_SIZE 11 +#define EXFAT_BIT_MAP_FIRST_TABLE 0 +#define EXFAT_LAST_CLUSTER_MASK 0xFFFFFFFF +#define EXFAT_DEFAULT_BOUNDARY_UNIT 128 +#define EXFAT_NUM_OF_DIR_ENTRIES 2 + + +#define DIVIDE_TO_CEILING(a, b) (((a) + (b) - 1) / (b)) +#define ALIGN_UP(a, b) (DIVIDE_TO_CEILING(a, b) * (b)) + +#define FX_FAT12 0x01 +#define FX_FAT16 0x04 +#define FX_BIGDOS 0x06 +#define FX_exFAT 0x07 +#define FX_FAT32 0x0B +#define FX_NO_FAT 0xFF + +#endif /* FX_ENABLE_EXFAT */ + + +/* Define the control block definitions for all system objects. */ + + +/* Define a single entry in the FAT cache. The FAT cache is used to reduce the + number of times the actual FAT sectors need to be accessed, thereby improving + performance. */ + +typedef struct FX_FAT_CACHE_ENTRY_STRUCT +{ + ULONG fx_fat_cache_entry_cluster; + ULONG fx_fat_cache_entry_value; + ULONG fx_fat_cache_entry_dirty; +} FX_FAT_CACHE_ENTRY; + + +/* Define the directory entry structure that contains information about a specific + directory entry. */ + +typedef struct FX_DIR_ENTRY_STRUCT +{ + + CHAR *fx_dir_entry_name; + CHAR fx_dir_entry_short_name[FX_MAX_SHORT_NAME_LEN]; /* Short file name, if LFN is present */ + UINT fx_dir_entry_long_name_present; /* 0 (default) => LFN not present; 1 => LFN present */ + UINT fx_dir_entry_long_name_shorted; /* LFN too large, file name was made shorter */ + UCHAR fx_dir_entry_attributes; /* Directory entry attributes */ + UCHAR fx_dir_entry_reserved; /* NT reserved, write 0 at create, otherwise ignore */ + UCHAR fx_dir_entry_created_time_ms; /* Create time in milliseconds, always write 0 */ + UINT fx_dir_entry_created_time; /* Created time */ + UINT fx_dir_entry_created_date; /* Created date */ + UINT fx_dir_entry_last_accessed_date; /* Last accessed date */ + UINT fx_dir_entry_time; /* Modified time */ + UINT fx_dir_entry_date; /* Modified cluster */ + ULONG fx_dir_entry_cluster; /* File/directory's starting cluster */ + ULONG64 fx_dir_entry_file_size; /* Size of the file in bytes */ + ULONG64 fx_dir_entry_log_sector; /* Logical sector of this directory entry */ + ULONG fx_dir_entry_byte_offset; /* Offset in logical sector of this directory entry */ + ULONG fx_dir_entry_number; /* Index into the directory */ + ULONG fx_dir_entry_last_search_cluster; /* Last cluster searched */ + ULONG fx_dir_entry_last_search_relative_cluster; /* Last relative cluster searched */ + ULONG64 fx_dir_entry_last_search_log_sector; /* Last logical sector searched */ + ULONG fx_dir_entry_last_search_byte_offset; /* Last offset in logical sector searched */ + ULONG64 fx_dir_entry_next_log_sector; + +#ifdef FX_ENABLE_EXFAT + /* for exFAT */ + CHAR fx_dir_entry_dont_use_fat; /* 0 bit - for current, 1st bit - for parent */ + UCHAR fx_dir_entry_type; + ULONG64 fx_dir_entry_available_file_size; + ULONG fx_dir_entry_secondary_count; +#endif /* FX_ENABLE_EXFAT */ +} FX_DIR_ENTRY; + +typedef FX_DIR_ENTRY *FX_DIR_ENTRY_PTR; + + +/* Define the path data structure. This structure will contain + the current path and the information for performing directory + entry operations. */ + +typedef struct FX_PATH_STRUCT +{ + /* Define the path information. */ + FX_DIR_ENTRY fx_path_directory; + CHAR fx_path_string[FX_MAXIMUM_PATH]; + CHAR fx_path_name_buffer[FX_MAX_LONG_NAME_LEN]; + ULONG fx_path_current_entry; +} FX_PATH; + +typedef FX_PATH FX_LOCAL_PATH; + + +/* Define the cache control data structure. There are FX_MAX_SECTOR_CACHE + of these structures defined inside the FX_MEDIA structure. Each entry + maintains a cache representation of a media sector. */ + +typedef struct FX_CACHED_SECTOR_STRUCT +{ + + /* Define the buffer pointer associated with this cache entry. */ + UCHAR *fx_cached_sector_memory_buffer; + + /* Define the sector number that is cached. */ + ULONG64 fx_cached_sector; + + /* Define the flag that indicates whether or not the cached sector + has been modified and needs to be written to the media. */ + UCHAR fx_cached_sector_buffer_dirty; + + /* Define the valid flag that indicates whether or not this entry is + still valid. */ + UCHAR fx_cached_sector_valid; + + /* Define the sector type, which indicates what type of sector is present. */ + UCHAR fx_cached_sector_type; + + /* Define a reserved byte, reserved for future use. */ + UCHAR fx_cached_sector_reserved; + + /* Define the next cached sector pointer. This is used to implement + the "last used" algorithm when looking for cache entry to swap out to + the physical media. */ + struct FX_CACHED_SECTOR_STRUCT + *fx_cached_sector_next_used; + +} FX_CACHED_SECTOR; + + +/* Determine if the media control block has an extension defined. If not, + define the extension to whitespace. */ + +#ifndef FX_MEDIA_MODULE_EXTENSION +#define FX_MEDIA_MODULE_EXTENSION +#endif + + +/* Define the media control block. All information about each open + media device are maintained in by the FX_MEDIA data type. */ + +typedef struct FX_MEDIA_STRUCT +{ + + /* Define the media ID used for error checking. */ + ULONG fx_media_id; + + /* Define the media's name. */ + CHAR *fx_media_name; + + /* Remember the memory buffer area. */ + UCHAR *fx_media_memory_buffer; + ULONG fx_media_memory_size; + +#ifdef FX_DISABLE_CACHE + ULONG64 fx_media_memory_buffer_sector; +#else + + /* Define the flag that indicates whether the logical cache utilizes + a hash function or is a linear search. If set, the logical cache + is accessed via a hash function on the requested sector. */ + UINT fx_media_sector_cache_hashed; + + /* Define the number of sectors that can actually be cached based on the + user supplied buffer at media open time. */ + ULONG fx_media_sector_cache_size; + + /* Define the end of the cache area. This is used to determine + if the I/O is for the internal memory of the media. */ + UCHAR *fx_media_sector_cache_end; + + /* Define the list head of the cached sector entries. This + pointer points to the most recently used cache sector. */ + struct FX_CACHED_SECTOR_STRUCT + *fx_media_sector_cache_list_ptr; + + /* Define the bit map that represents the hashed cache sectors that are + valid. This bit map will help optimize the invalidation of the hashed + sector cache. */ + ULONG fx_media_sector_cache_hashed_sector_valid; + + /* Define the outstanding dirty sector counter. This is used to optimize + the searching of sectors to flush to the media. */ + ULONG fx_media_sector_cache_dirty_count; +#endif /* FX_DISABLE_CACHE */ + + /* Define the basic information about the associated media. */ + UINT fx_media_bytes_per_sector; + UINT fx_media_sectors_per_track; + UINT fx_media_heads; + + ULONG64 fx_media_total_sectors; + ULONG fx_media_total_clusters; + +#ifdef FX_ENABLE_EXFAT + /* Define exFAT media information. */ + ULONG fx_media_exfat_volume_serial_number; + UINT fx_media_exfat_file_system_revision; + UINT fx_media_exfat_volume_flag; + USHORT fx_media_exfat_drive_select; + USHORT fx_media_exfat_percent_in_use; + UINT fx_media_exfat_bytes_per_sector_shift; + UINT fx_media_exfat_sector_per_clusters_shift; + + /* exFAT: Bitmap cache */ + /* Pointer to Bitmap cache */ + UCHAR fx_media_exfat_bitmap_cache[FX_EXFAT_BITMAP_CACHE_SIZE]; + + /* Define beginning sector of Bitmap table. */ + ULONG fx_media_exfat_bitmap_start_sector; + + /* Define the cache size in sectors. Used for flash operation. */ + ULONG fx_media_exfat_bitmap_cache_size_in_sectors; + + /* Define the number of first cached cluster. */ + ULONG fx_media_exfat_bitmap_cache_start_cluster; + + /* Define the number of last cached cluster. */ + ULONG fx_media_exfat_bitmap_cache_end_cluster; + + /* Define how many clusters mapped in one sector. */ + UINT fx_media_exfat_bitmap_clusters_per_sector_shift; + + /* Define is Bitmap table was changed or not. */ + UINT fx_media_exfat_bitmap_cache_dirty; +#endif /* FX_ENABLE_EXFAT */ + + UINT fx_media_reserved_sectors; + UINT fx_media_root_sector_start; + UINT fx_media_root_sectors; + UINT fx_media_data_sector_start; + UINT fx_media_sectors_per_cluster; + UINT fx_media_sectors_per_FAT; + UINT fx_media_number_of_FATs; + UINT fx_media_12_bit_FAT; + UINT fx_media_32_bit_FAT; + ULONG fx_media_FAT32_additional_info_sector; + UINT fx_media_FAT32_additional_info_last_available; +#ifdef FX_DRIVER_USE_64BIT_LBA + ULONG64 fx_media_hidden_sectors; +#else + ULONG fx_media_hidden_sectors; +#endif + ULONG fx_media_root_cluster_32; + UINT fx_media_root_directory_entries; + ULONG fx_media_available_clusters; + ULONG fx_media_cluster_search_start; + + /* Define the information pertinent to the I/O driver interface. */ + + VOID *fx_media_driver_info; + UINT fx_media_driver_request; + UINT fx_media_driver_status; + UCHAR *fx_media_driver_buffer; +#ifdef FX_DRIVER_USE_64BIT_LBA + ULONG64 fx_media_driver_logical_sector; +#else + ULONG fx_media_driver_logical_sector; +#endif + ULONG fx_media_driver_sectors; + ULONG fx_media_driver_physical_sector; + UINT fx_media_driver_physical_track; + UINT fx_media_driver_physical_head; + UINT fx_media_driver_write_protect; /* The driver sets this to FX_TRUE when media is write protected. */ + UINT fx_media_driver_free_sector_update; /* The driver sets this to FX_TRUE when it needs to know freed clusters. */ + UINT fx_media_driver_system_write; + UINT fx_media_driver_data_sector_read; + UINT fx_media_driver_sector_type; + + /* Define the driver entry point. */ + VOID (*fx_media_driver_entry)(struct FX_MEDIA_STRUCT *); + + /* Define notify function called when media is open. */ + VOID (*fx_media_open_notify)(struct FX_MEDIA_STRUCT *); + + /* Define notify function called when media is closed. */ + VOID (*fx_media_close_notify)(struct FX_MEDIA_STRUCT *); + + /* Define the head pointer for the open files of this media. */ + struct FX_FILE_STRUCT + *fx_media_opened_file_list; + + /* Define the counter for keeping track of how many open files are + present. */ + ULONG fx_media_opened_file_count; + + /* Define the next and previous link pointers for the open media list. */ + struct FX_MEDIA_STRUCT + *fx_media_opened_next, + *fx_media_opened_previous; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Define various statistics for this media instance. This information + should be useful in performance tuning and optimizing the application. */ + + ULONG fx_media_directory_attributes_reads; + ULONG fx_media_directory_attributes_sets; + ULONG fx_media_directory_creates; + ULONG fx_media_directory_default_gets; + ULONG fx_media_directory_default_sets; + ULONG fx_media_directory_deletes; + ULONG fx_media_directory_first_entry_finds; + ULONG fx_media_directory_first_full_entry_finds; + ULONG fx_media_directory_information_gets; + ULONG fx_media_directory_local_path_clears; + ULONG fx_media_directory_local_path_gets; + ULONG fx_media_directory_local_path_restores; + ULONG fx_media_directory_local_path_sets; + ULONG fx_media_directory_name_tests; + ULONG fx_media_directory_next_entry_finds; + ULONG fx_media_directory_next_full_entry_finds; + ULONG fx_media_directory_renames; + ULONG fx_media_file_allocates; + ULONG fx_media_file_attributes_reads; + ULONG fx_media_file_attributes_sets; + ULONG fx_media_file_best_effort_allocates; + ULONG fx_media_file_closes; + ULONG fx_media_file_creates; + ULONG fx_media_file_deletes; + ULONG fx_media_file_opens; + ULONG fx_media_file_reads; + ULONG fx_media_file_relative_seeks; + ULONG fx_media_file_renames; + ULONG fx_media_file_seeks; + ULONG fx_media_file_truncates; + ULONG fx_media_file_truncate_releases; + ULONG fx_media_file_writes; + ULONG fx_media_aborts; + ULONG fx_media_flushes; + ULONG fx_media_reads; + ULONG fx_media_writes; + ULONG fx_media_directory_entry_reads; + ULONG fx_media_directory_entry_writes; + ULONG fx_media_directory_searches; + ULONG fx_media_directory_free_searches; + ULONG fx_media_fat_entry_reads; + ULONG fx_media_fat_entry_writes; + ULONG fx_media_fat_entry_cache_read_hits; + ULONG fx_media_fat_entry_cache_read_misses; + ULONG fx_media_fat_entry_cache_write_hits; + ULONG fx_media_fat_entry_cache_write_misses; + ULONG fx_media_fat_cache_flushes; + ULONG fx_media_fat_sector_reads; + ULONG fx_media_fat_sector_writes; + ULONG fx_media_logical_sector_reads; + ULONG fx_media_logical_sector_writes; + ULONG fx_media_logical_sector_cache_read_hits; + ULONG fx_media_logical_sector_cache_read_misses; + ULONG fx_media_driver_read_requests; + ULONG fx_media_driver_write_requests; + ULONG fx_media_driver_boot_read_requests; + ULONG fx_media_driver_boot_write_requests; + ULONG fx_media_driver_release_sectors_requests; + ULONG fx_media_driver_flush_requests; +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + ULONG fx_media_directory_search_cache_hits; +#endif +#endif + + /* Define the media's protection object, which is a ThreadX mutex. + Only one thread is allowed to access any media or associated files + at a time. If FX_SINGLE_THREAD is defined, the FileX services are + going to be called from only one thread, hence the protection is + not needed. */ +#ifndef FX_SINGLE_THREAD + TX_MUTEX fx_media_protect; +#endif + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Define the information used to remember the last directory entry found through + searching or walking the directory via directory entry next. This information + will be used to eliminate multiple searches for the same directory entry if + the accesses are done sequentially. */ + UINT fx_media_last_found_directory_valid; + FX_DIR_ENTRY fx_media_last_found_directory; + FX_DIR_ENTRY fx_media_last_found_entry; + CHAR fx_media_last_found_file_name[FX_MAX_LONG_NAME_LEN]; + CHAR fx_media_last_found_name[FX_MAX_LAST_NAME_LEN]; +#endif + + /* Define the current directory information for the media. */ + FX_PATH fx_media_default_path; + + /* Define FAT entry cache and the variable used to index the cache. */ + FX_FAT_CACHE_ENTRY fx_media_fat_cache[FX_MAX_FAT_CACHE]; + + /* Define the FAT secondary update map. This will be used on flush and + close to update sectors of any secondary FATs in the media. */ + UCHAR fx_media_fat_secondary_update_map[FX_FAT_MAP_SIZE]; + + /* Define a variable for the application's use. */ + ALIGN_TYPE fx_media_reserved_for_user; + + /* Define an area to allocate long file names so that local storage on + calling thread's stack is not used for long file names. This helps + reduce the amount of thread stack space needed when using FileX. */ + CHAR fx_media_name_buffer[4*FX_MAX_LONG_NAME_LEN]; + +#ifdef FX_RENAME_PATH_INHERIT + + /* Define the file and directory rename buffer that will be used to prepend + paths when necessary to the target file name. */ + CHAR fx_media_rename_buffer[FX_MAXIMUM_PATH]; +#endif + +#ifndef FX_DISABLE_CACHE + /* Define the sector cache control structures for this media. */ + struct FX_CACHED_SECTOR_STRUCT + fx_media_sector_cache[FX_MAX_SECTOR_CACHE]; + + /* Define the sector cache hash mask so that the hash algorithm can be used with + any power of 2 number of cache sectors. */ + ULONG fx_media_sector_cache_hash_mask; +#endif /* FX_DISABLE_CACHE */ + + /* Define a variable to disable burst cache. This is used by the underlying + driver. */ + ULONG fx_media_disable_burst_cache; + +#ifdef FX_ENABLE_FAULT_TOLERANT + + /* Fault tolerant information */ + /* Indicate whether fault tolerant is enabled. */ + + UCHAR fx_media_fault_tolerant_enabled; + + /* State of fault tolerant operation. */ + UCHAR fx_media_fault_tolerant_state; + + /* Transaction recursive count. */ + USHORT fx_media_fault_tolerant_transaction_count; + + /* Start cluster of log. */ + ULONG fx_media_fault_tolerant_start_cluster; + + /* Count of consecutive clusters of log. */ + ULONG fx_media_fault_tolerant_clusters; + + /* Count of total logs. */ + ULONG fx_media_fault_tolerant_total_logs; + + /* Pointer to the memory buffer area used for fault tolerant operations. */ + UCHAR *fx_media_fault_tolerant_memory_buffer; + + /* Size of memory buffer area used for fault tolerant operations. */ + ULONG fx_media_fault_tolerant_memory_buffer_size; + + /* Size of log file. */ + ULONG fx_media_fault_tolerant_file_size; + + /* Memory space used during the release of FAT list. */ + ULONG fx_media_fault_tolerant_cache[FX_FAULT_TOLERANT_CACHE_SIZE >> 2]; + + /* Sector number of cached FAT entries. */ + ULONG fx_media_fault_tolerant_cached_FAT_sector; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Reserved value of FAT table. */ + ULONG fx_media_fat_reserved; + + /* Last value of FAT table. */ + ULONG fx_media_fat_last; + + /* Media geometry structure */ + UCHAR fx_media_FAT_type; + + /* Define the module port extension in the media control block. This + is typically defined to whitespace in fx_port.h. */ + FX_MEDIA_MODULE_EXTENSION + +} FX_MEDIA; + +typedef FX_MEDIA * FX_MEDIA_PTR; + + +/* Determine if the file control block has an extension defined. If not, + define the extension to whitespace. */ + +#ifndef FX_FILE_MODULE_EXTENSION +#define FX_FILE_MODULE_EXTENSION +#endif + + +/* Define the FileX file control block. All information about open + files are found in this data type. */ + +typedef struct FX_FILE_STRUCT +{ + + /* Define the file ID used for error checking. */ + ULONG fx_file_id; + + /* Define the file's name. */ + CHAR *fx_file_name; + + /* Define the open mode request. */ + ULONG fx_file_open_mode; + + /* Define the file modified field. */ + UCHAR fx_file_modified; + + /* Define the data storage parameters. */ + ULONG fx_file_total_clusters; + ULONG fx_file_first_physical_cluster; + ULONG fx_file_consecutive_cluster; + ULONG fx_file_last_physical_cluster; + ULONG fx_file_current_physical_cluster; + ULONG64 fx_file_current_logical_sector; + ULONG fx_file_current_logical_offset; + ULONG fx_file_current_relative_cluster; + ULONG fx_file_current_relative_sector; + ULONG64 fx_file_current_file_offset; + ULONG64 fx_file_current_file_size; + ULONG64 fx_file_current_available_size; +#ifdef FX_ENABLE_FAULT_TOLERANT + ULONG64 fx_file_maximum_size_used; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Remember the media that is associated with this file. */ + FX_MEDIA *fx_file_media_ptr; + + /* Define the pointers necessary to maintain the open file on + the list of open files. */ + struct FX_FILE_STRUCT + *fx_file_opened_next, + *fx_file_opened_previous; + + /* Define the complete directory entry structure. */ + FX_DIR_ENTRY fx_file_dir_entry; + CHAR fx_file_name_buffer[FX_MAX_LONG_NAME_LEN]; + + /* Define a variable for the application's use */ + ULONG fx_file_disable_burst_cache; + + /* Define a notify function called when file is written to. */ + VOID (*fx_file_write_notify)(struct FX_FILE_STRUCT *); + + /* Define the module port extension in the file control block. This + is typically defined to whitespace in fx_port.h. */ + FX_FILE_MODULE_EXTENSION + +} FX_FILE; + +typedef FX_FILE *FX_FILE_PTR; + + +/* Define the FileX API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the FileX source. */ + +#ifndef FX_SOURCE_CODE + +#ifdef FX_DISABLE_ONE_LINE_FUNCTION +#define fx_file_seek(f, b) fx_file_extended_seek(f, (ULONG64)b) +#define fx_file_allocate(f, s) fx_file_extended_allocate(f, (ULONG64)s); +#define fx_file_truncate(f, s) fx_file_extended_truncate(f, (ULONG64)s); +#define fx_file_relative_seek(f, b, sf) fx_file_extended_relative_seek(f, (ULONG64)b, sf); +#define fx_file_truncate_release(f, s) fx_file_extended_truncate_release(f, (ULONG64)s); +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ + +/* Determine if error checking is desired. If so, map API functions + to the appropriate error checking front-ends. Otherwise, map API + functions to the core functions that actually perform the work. + Note: error checking is enabled by default. */ + +#ifdef FX_DISABLE_ERROR_CHECKING + +/* Services without error checking. */ + +#define fx_directory_attributes_read _fx_directory_attributes_read +#define fx_directory_attributes_set _fx_directory_attributes_set +#define fx_directory_create _fx_directory_create +#define fx_directory_default_get _fx_directory_default_get +#define fx_directory_default_get_copy _fx_directory_default_get_copy +#define fx_directory_default_set _fx_directory_default_set +#define fx_directory_delete _fx_directory_delete +#define fx_directory_first_entry_find _fx_directory_first_entry_find +#define fx_directory_first_full_entry_find _fx_directory_first_full_entry_find +#define fx_directory_information_get _fx_directory_information_get +#define fx_directory_local_path_clear _fx_directory_local_path_clear +#define fx_directory_local_path_get _fx_directory_local_path_get +#define fx_directory_local_path_get_copy _fx_directory_local_path_get_copy +#define fx_directory_local_path_restore _fx_directory_local_path_restore +#define fx_directory_local_path_set _fx_directory_local_path_set +#define fx_directory_long_name_get _fx_directory_long_name_get +#define fx_directory_long_name_get_extended _fx_directory_long_name_get_extended +#define fx_directory_name_test _fx_directory_name_test +#define fx_directory_next_entry_find _fx_directory_next_entry_find +#define fx_directory_next_full_entry_find _fx_directory_next_full_entry_find +#define fx_directory_rename _fx_directory_rename +#define fx_directory_short_name_get _fx_directory_short_name_get +#define fx_directory_short_name_get_extended _fx_directory_short_name_get_extended + +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +#define fx_file_allocate _fx_file_allocate +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +#define fx_file_attributes_read _fx_file_attributes_read +#define fx_file_attributes_set _fx_file_attributes_set +#define fx_file_best_effort_allocate _fx_file_best_effort_allocate +#define fx_file_close _fx_file_close +#define fx_file_create _fx_file_create +#define fx_file_date_time_set _fx_file_date_time_set +#define fx_file_delete _fx_file_delete +#define fx_file_open _fx_file_open +#define fx_file_read _fx_file_read +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +#define fx_file_relative_seek _fx_file_relative_seek +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +#define fx_file_rename _fx_file_rename +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +#define fx_file_seek _fx_file_seek +#define fx_file_truncate _fx_file_truncate +#define fx_file_truncate_release _fx_file_truncate_release +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +#define fx_file_write _fx_file_write +#define fx_file_write_notify_set _fx_file_write_notify_set +#define fx_file_extended_allocate _fx_file_extended_allocate +#define fx_file_extended_best_effort_allocate _fx_file_extended_best_effort_allocate +#define fx_file_extended_relative_seek _fx_file_extended_relative_seek +#define fx_file_extended_seek _fx_file_extended_seek +#define fx_file_extended_truncate _fx_file_extended_truncate +#define fx_file_extended_truncate_release _fx_file_extended_truncate_release + +#define fx_media_abort _fx_media_abort +#define fx_media_cache_invalidate _fx_media_cache_invalidate +#define fx_media_check _fx_media_check +#define fx_media_close _fx_media_close +#define fx_media_flush _fx_media_flush +#define fx_media_format _fx_media_format +#ifdef FX_ENABLE_EXFAT +#define fx_media_exFAT_format _fx_media_exFAT_format +#endif /* FX_ENABLE_EXFAT */ +#define fx_media_open _fx_media_open +#define fx_media_read _fx_media_read +#define fx_media_space_available _fx_media_space_available +#define fx_media_volume_get _fx_media_volume_get +#define fx_media_volume_get_extended _fx_media_volume_get_extended +#define fx_media_volume_set _fx_media_volume_set +#define fx_media_write _fx_media_write +#define fx_media_open_notify_set _fx_media_open_notify_set +#define fx_media_close_notify_set _fx_media_close_notify_set +#define fx_media_extended_space_available _fx_media_extended_space_available + +#define fx_unicode_directory_create _fx_unicode_directory_create +#define fx_unicode_directory_rename _fx_unicode_directory_rename +#define fx_unicode_file_create _fx_unicode_file_create +#define fx_unicode_file_rename _fx_unicode_file_rename +#define fx_unicode_length_get _fx_unicode_length_get +#define fx_unicode_length_get_extended _fx_unicode_length_get_extended +#define fx_unicode_name_get _fx_unicode_name_get +#define fx_unicode_name_get_extended _fx_unicode_name_get_extended +#define fx_unicode_short_name_get _fx_unicode_short_name_get +#define fx_unicode_short_name_get_extended _fx_unicode_short_name_get_extended + +#define fx_system_date_get _fx_system_date_get +#define fx_system_date_set _fx_system_date_set +#define fx_system_time_get _fx_system_time_get +#define fx_system_time_set _fx_system_time_set +#define fx_system_initialize _fx_system_initialize + +#ifdef FX_ENABLE_FAULT_TOLERANT +#define fx_fault_tolerant_enable _fx_fault_tolerant_enable +#endif /* FX_ENABLE_FAULT_TOLERANT */ + +#else + +/* Services with error checking. */ + +#define fx_directory_attributes_read _fxe_directory_attributes_read +#define fx_directory_attributes_set _fxe_directory_attributes_set +#define fx_directory_create _fxe_directory_create +#define fx_directory_default_get _fxe_directory_default_get +#define fx_directory_default_get_copy _fxe_directory_default_get_copy +#define fx_directory_default_set _fxe_directory_default_set +#define fx_directory_delete _fxe_directory_delete +#define fx_directory_first_entry_find _fxe_directory_first_entry_find +#define fx_directory_first_full_entry_find _fxe_directory_first_full_entry_find +#define fx_directory_information_get _fxe_directory_information_get +#define fx_directory_local_path_clear _fxe_directory_local_path_clear +#define fx_directory_local_path_get _fxe_directory_local_path_get +#define fx_directory_local_path_get_copy _fxe_directory_local_path_get_copy +#define fx_directory_local_path_restore _fxe_directory_local_path_restore +#define fx_directory_local_path_set(m, l, n) _fxe_directory_local_path_set(m, l, n, sizeof(FX_LOCAL_PATH)) +#define fx_directory_long_name_get _fxe_directory_long_name_get +#define fx_directory_long_name_get_extended _fxe_directory_long_name_get_extended +#define fx_directory_name_test _fxe_directory_name_test +#define fx_directory_next_entry_find _fxe_directory_next_entry_find +#define fx_directory_next_full_entry_find _fxe_directory_next_full_entry_find +#define fx_directory_rename _fxe_directory_rename +#define fx_directory_short_name_get _fxe_directory_short_name_get +#define fx_directory_short_name_get_extended _fxe_directory_short_name_get_extended + +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +#define fx_file_allocate _fxe_file_allocate +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +#define fx_file_attributes_read _fxe_file_attributes_read +#define fx_file_attributes_set _fxe_file_attributes_set +#define fx_file_best_effort_allocate _fxe_file_best_effort_allocate +#define fx_file_close _fxe_file_close +#define fx_file_create _fxe_file_create +#define fx_file_date_time_set _fxe_file_date_time_set +#define fx_file_delete _fxe_file_delete +#define fx_file_open(m, f, n, t) _fxe_file_open(m, f, n, t, sizeof(FX_FILE)) +#define fx_file_read _fxe_file_read +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +#define fx_file_relative_seek _fxe_file_relative_seek +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +#define fx_file_rename _fxe_file_rename +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +#define fx_file_seek _fxe_file_seek +#define fx_file_truncate _fxe_file_truncate +#define fx_file_truncate_release _fxe_file_truncate_release +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +#define fx_file_write _fxe_file_write +#define fx_file_write_notify_set _fxe_file_write_notify_set +#define fx_file_extended_allocate _fxe_file_extended_allocate +#define fx_file_extended_best_effort_allocate _fxe_file_extended_best_effort_allocate +#define fx_file_extended_relative_seek _fxe_file_extended_relative_seek +#define fx_file_extended_seek _fxe_file_extended_seek +#define fx_file_extended_truncate _fxe_file_extended_truncate +#define fx_file_extended_truncate_release _fxe_file_extended_truncate_release + +#define fx_media_abort _fxe_media_abort +#define fx_media_cache_invalidate _fxe_media_cache_invalidate +#define fx_media_check _fxe_media_check +#define fx_media_close _fxe_media_close +#define fx_media_flush _fxe_media_flush +#define fx_media_format _fxe_media_format +#ifdef FX_ENABLE_EXFAT +#define fx_media_exFAT_format _fxe_media_exFAT_format +#endif /* FX_ENABLE_EXFAT */ +#define fx_media_open(m, n, d, i, p, s) _fxe_media_open(m, n, d, i, p, s, sizeof(FX_MEDIA)) +#define fx_media_read _fxe_media_read +#define fx_media_space_available _fxe_media_space_available +#define fx_media_volume_get _fxe_media_volume_get +#define fx_media_volume_get_extended _fxe_media_volume_get_extended +#define fx_media_volume_set _fxe_media_volume_set +#define fx_media_write _fxe_media_write +#define fx_media_open_notify_set _fxe_media_open_notify_set +#define fx_media_close_notify_set _fxe_media_close_notify_set +#define fx_media_extended_space_available _fxe_media_extended_space_available + +#define fx_unicode_directory_create _fxe_unicode_directory_create +#define fx_unicode_directory_rename _fxe_unicode_directory_rename +#define fx_unicode_file_create _fxe_unicode_file_create +#define fx_unicode_file_rename _fxe_unicode_file_rename +#define fx_unicode_length_get _fx_unicode_length_get +#define fx_unicode_length_get_extended _fx_unicode_length_get_extended +#define fx_unicode_name_get _fxe_unicode_name_get +#define fx_unicode_name_get_extended _fxe_unicode_name_get_extended +#define fx_unicode_short_name_get _fxe_unicode_short_name_get +#define fx_unicode_short_name_get_extended _fxe_unicode_short_name_get_extended + +#define fx_system_date_get _fxe_system_date_get +#define fx_system_date_set _fxe_system_date_set +#define fx_system_time_get _fxe_system_time_get +#define fx_system_time_set _fxe_system_time_set +#define fx_system_initialize _fx_system_initialize + +#ifdef FX_ENABLE_FAULT_TOLERANT +#define fx_fault_tolerant_enable _fxe_fault_tolerant_enable +#endif /* FX_ENABLE_FAULT_TOLERANT */ + +#endif + +/* Define the function prototypes of the FileX API. */ + +UINT fx_directory_attributes_read(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes_ptr); +UINT fx_directory_attributes_set(FX_MEDIA *media_ptr, CHAR *directory_name, UINT attributes); +UINT fx_directory_create(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT fx_directory_default_get(FX_MEDIA *media_ptr, CHAR **return_path_name); +UINT fx_directory_default_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size); +UINT fx_directory_default_set(FX_MEDIA *media_ptr, CHAR *new_path_name); +UINT fx_directory_delete(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT fx_directory_first_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT fx_directory_first_full_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, + ULONG *size, UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT fx_directory_information_get(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT fx_directory_local_path_clear(FX_MEDIA *media_ptr); +UINT fx_directory_local_path_get(FX_MEDIA *media_ptr, CHAR **return_path_name); +UINT fx_directory_local_path_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size); +UINT fx_directory_local_path_restore(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr); +#ifdef FX_DISABLE_ERROR_CHECKING +UINT _fx_directory_local_path_set(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr, CHAR *new_path_name); +#else +UINT _fxe_directory_local_path_set(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr, CHAR *new_path_name, UINT local_path_control_block_size); +#endif +UINT fx_directory_long_name_get(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name); +UINT fx_directory_long_name_get_extended(FX_MEDIA* media_ptr, CHAR* short_file_name, CHAR* long_file_name, UINT long_file_name_buffer_length); +UINT fx_directory_name_test(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT fx_directory_next_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT fx_directory_next_full_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, + ULONG *size, UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT fx_directory_rename(FX_MEDIA *media_ptr, CHAR *old_directory_name, CHAR *new_directory_name); +UINT fx_directory_short_name_get(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name); +UINT fx_directory_short_name_get_extended(FX_MEDIA* media_ptr, CHAR* long_file_name, CHAR* short_file_name, UINT short_file_name_length); + +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT fx_file_allocate(FX_FILE *file_ptr, ULONG size); +#endif /* FX_DISABLE_ONE_LINE_FUNCTION*/ +UINT fx_file_attributes_read(FX_MEDIA *media_ptr, CHAR *file_name, UINT *attributes_ptr); +UINT fx_file_attributes_set(FX_MEDIA *media_ptr, CHAR *file_name, UINT attributes); +UINT fx_file_best_effort_allocate(FX_FILE *file_ptr, ULONG size, ULONG *actual_size_allocated); +UINT fx_file_close(FX_FILE *file_ptr); +UINT fx_file_create(FX_MEDIA *media_ptr, CHAR *file_name); +UINT fx_file_date_time_set(FX_MEDIA *media_ptr, CHAR *file_name, + UINT year, UINT month, UINT day, UINT hour, UINT minute, UINT second); +UINT fx_file_delete(FX_MEDIA *media_ptr, CHAR *file_name); +#ifdef FX_DISABLE_ERROR_CHECKING +UINT _fx_file_open(FX_MEDIA *media_ptr, FX_FILE *file_ptr, CHAR *file_name, + UINT open_type); +#else +UINT _fxe_file_open(FX_MEDIA *media_ptr, FX_FILE *file_ptr, CHAR *file_name, + UINT open_type, UINT file_control_block_size); +#endif +UINT fx_file_read(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG request_size, ULONG *actual_size); +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT fx_file_relative_seek(FX_FILE *file_ptr, ULONG byte_offset, UINT seek_from); +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +UINT fx_file_rename(FX_MEDIA *media_ptr, CHAR *old_file_name, CHAR *new_file_name); +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT fx_file_seek(FX_FILE *file_ptr, ULONG byte_offset); +UINT fx_file_truncate(FX_FILE *file_ptr, ULONG size); +UINT fx_file_truncate_release(FX_FILE *file_ptr, ULONG size); +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +UINT fx_file_write(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG size); +UINT fx_file_write_notify_set(FX_FILE *file_ptr, VOID (*file_write_notify)(FX_FILE *)); +UINT fx_file_extended_allocate(FX_FILE *file_ptr, ULONG64 size); +UINT fx_file_extended_best_effort_allocate(FX_FILE *file_ptr, ULONG64 size, ULONG64 *actual_size_allocated); +UINT fx_file_extended_relative_seek(FX_FILE *file_ptr, ULONG64 byte_offset, UINT seek_from); +UINT fx_file_extended_seek(FX_FILE *file_ptr, ULONG64 byte_offset); +UINT fx_file_extended_truncate(FX_FILE *file_ptr, ULONG64 size); +UINT fx_file_extended_truncate_release(FX_FILE *file_ptr, ULONG64 size); + +UINT fx_media_abort(FX_MEDIA *media_ptr); +UINT fx_media_cache_invalidate(FX_MEDIA *media_ptr); +UINT fx_media_check(FX_MEDIA *media_ptr, UCHAR *scratch_memory_ptr, ULONG scratch_memory_size, ULONG error_correction_option, ULONG *errors_detected); +UINT fx_media_close(FX_MEDIA *media_ptr); +UINT fx_media_flush(FX_MEDIA *media_ptr); +UINT fx_media_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, UCHAR *memory_ptr, UINT memory_size, + CHAR *volume_name, UINT number_of_fats, UINT directory_entries, UINT hidden_sectors, + ULONG total_sectors, UINT bytes_per_sector, UINT sectors_per_cluster, + UINT heads, UINT sectors_per_track); +#ifdef FX_ENABLE_EXFAT +UINT fx_media_exFAT_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, UCHAR *memory_ptr, UINT memory_size, + CHAR *volume_name, UINT number_of_fats, ULONG64 hidden_sectors, ULONG64 total_sectors, + UINT bytes_per_sector, UINT sectors_per_cluster, UINT volume_serial_number, UINT boundary_unit); +#endif /* FX_ENABLE_EXFAT */ +#ifdef FX_DISABLE_ERROR_CHECKING +UINT _fx_media_open(FX_MEDIA *media_ptr, CHAR *media_name, + VOID (*media_driver)(FX_MEDIA *), VOID *driver_info_ptr, + VOID *memory_ptr, ULONG memory_size); +#else +UINT _fxe_media_open(FX_MEDIA *media_ptr, CHAR *media_name, + VOID (*media_driver)(FX_MEDIA *), VOID *driver_info_ptr, + VOID *memory_ptr, ULONG memory_size, UINT media_control_block_size); +#endif +UINT fx_media_read(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr); +UINT fx_media_space_available(FX_MEDIA *media_ptr, ULONG *available_bytes_ptr); +UINT fx_media_volume_get(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_source); +UINT fx_media_volume_get_extended(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_name_buffer_length, UINT volume_source); +UINT fx_media_volume_set(FX_MEDIA *media_ptr, CHAR *volume_name); +UINT fx_media_write(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr); +UINT fx_media_open_notify_set(FX_MEDIA *media_ptr, VOID (*media_open_notify)(FX_MEDIA *)); +UINT fx_media_close_notify_set(FX_MEDIA *media_ptr, VOID (*media_close_notify)(FX_MEDIA *)); +UINT fx_media_extended_space_available(FX_MEDIA *media_ptr, ULONG64 *available_bytes_ptr); + +UINT fx_system_date_get(UINT *year, UINT *month, UINT *day); +UINT fx_system_date_set(UINT year, UINT month, UINT day); +VOID fx_system_initialize(VOID); +UINT fx_system_time_get(UINT *hour, UINT *minute, UINT *second); +UINT fx_system_time_set(UINT hour, UINT minute, UINT second); + +UINT fx_unicode_directory_create(FX_MEDIA *media_ptr, + UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *short_name); +UINT fx_unicode_directory_rename(FX_MEDIA *media_ptr, + UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, + CHAR *new_short_name); +UINT fx_unicode_file_create(FX_MEDIA *media_ptr, + UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *short_name); +UINT fx_unicode_file_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name); +ULONG fx_unicode_length_get(UCHAR *unicode_name); +ULONG fx_unicode_length_get_extended(UCHAR *unicode_name, UINT buffer_length); +UINT fx_unicode_name_get(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length); +UINT fx_unicode_name_get_extended(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length, ULONG unicode_name_buffer_length); +UINT fx_unicode_short_name_get(FX_MEDIA *media_ptr, + UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name); +UINT fx_unicode_short_name_get_extended(FX_MEDIA *media_ptr, + UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name, ULONG short_name_buffer_length); + +#ifdef FX_ENABLE_FAULT_TOLERANT +UINT fx_fault_tolerant_enable(FX_MEDIA *media_ptr, VOID *memory_buffer, UINT memory_size); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/* Define prototype for utility services commonly used by FileX I/O Drivers. This eliminates the + need to include internal FileX component files in I/O drivers. */ + +UINT _fx_utility_16_unsigned_read(UCHAR *source_ptr); +VOID _fx_utility_16_unsigned_write(UCHAR *dest_ptr, UINT value); +ULONG _fx_utility_32_unsigned_read(UCHAR *source_ptr); +VOID _fx_utility_32_unsigned_write(UCHAR *dest_ptr, ULONG value); +ULONG64 _fx_utility_64_unsigned_read(UCHAR *source_ptr); +VOID _fx_utility_64_unsigned_write(UCHAR *dest_ptr, ULONG64 value); +VOID _fx_utility_memory_copy(UCHAR *source_ptr, UCHAR *dest_ptr, ULONG size); +VOID _fx_utility_memory_set(UCHAR *dest_ptr, UCHAR value, ULONG size); + +#endif + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/Middlewares/ST/filex/common/inc/fx_directory.h b/src/Middlewares/ST/filex/common/inc/fx_directory.h new file mode 100644 index 00000000..2d35dc39 --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_directory.h @@ -0,0 +1,137 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* fx_directory.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the FileX Directory component constants, data */ +/* definitions, and external references. It is assumed that fx_api.h */ +/* (and fx_port.h) have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef FX_DIRECTORY_H +#define FX_DIRECTORY_H + + +/* Define the external Directory component function prototypes. */ + +UINT _fx_directory_attributes_read(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes_ptr); +UINT _fx_directory_attributes_set(FX_MEDIA *media_ptr, CHAR *directory_name, UINT attributes); +UINT _fx_directory_create(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fx_directory_default_get(FX_MEDIA *media_ptr, CHAR **return_path_name); +UINT _fx_directory_default_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size); +UINT _fx_directory_default_set(FX_MEDIA *media_ptr, CHAR *new_path_name); +UINT _fx_directory_delete(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fx_directory_entry_read_FAT(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, ULONG *entry_ptr, + FX_DIR_ENTRY *destination_ptr); +UINT _fx_directory_first_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fx_directory_first_full_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, + ULONG *size, UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT _fx_directory_information_get(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT _fx_directory_local_path_clear(FX_MEDIA *media_ptr); +UINT _fx_directory_local_path_get(FX_MEDIA *media_ptr, CHAR **return_path_name); +UINT _fx_directory_local_path_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size); +UINT _fx_directory_local_path_restore(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr); +UINT _fx_directory_local_path_set(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr, CHAR *new_path_name); +UINT _fx_directory_long_name_get(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name); +UINT _fx_directory_long_name_get_extended(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name, UINT long_file_name_buffer_length); +UINT _fx_directory_name_test(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fx_directory_next_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fx_directory_next_full_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, + ULONG *size, UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT _fx_directory_rename(FX_MEDIA *media_ptr, CHAR *old_directory_name, CHAR *new_directory_name); +UINT _fx_directory_short_name_get(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name); +UINT _fx_directory_short_name_get_extended(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name, UINT short_file_name_length); + +UINT _fxe_directory_attributes_read(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes_ptr); +UINT _fxe_directory_attributes_set(FX_MEDIA *media_ptr, CHAR *directory_name, UINT attributes); +UINT _fxe_directory_create(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fxe_directory_default_get(FX_MEDIA *media_ptr, CHAR **return_path_name); +UINT _fxe_directory_default_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size); +UINT _fxe_directory_default_set(FX_MEDIA *media_ptr, CHAR *new_path_name); +UINT _fxe_directory_delete(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fxe_directory_first_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fxe_directory_first_full_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, + ULONG *size, UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT _fxe_directory_information_get(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT _fxe_directory_local_path_clear(FX_MEDIA *media_ptr); +UINT _fxe_directory_local_path_get(FX_MEDIA *media_ptr, CHAR **return_path_name); +UINT _fxe_directory_local_path_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size); +UINT _fxe_directory_local_path_restore(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr); +UINT _fxe_directory_local_path_set(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr, CHAR *new_path_name, UINT local_path_control_block_size); +UINT _fxe_directory_long_name_get(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name); +UINT _fxe_directory_long_name_get_extended(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name, UINT long_file_name_buffer_length); +UINT _fxe_directory_name_test(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fxe_directory_next_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name); +UINT _fxe_directory_next_full_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes, + ULONG *size, UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second); +UINT _fxe_directory_rename(FX_MEDIA *media_ptr, CHAR *old_directory_name, CHAR *new_directory_name); +UINT _fxe_directory_short_name_get(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name); +UINT _fxe_directory_short_name_get_extended(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name, UINT short_file_name_length); + + +/* Define the internal Directory component function prototypes. */ +#ifdef FX_ENABLE_EXFAT +#define UPDATE_DELETE (0) +#define UPDATE_FILE (1) +#define UPDATE_STREAM (2) +#define UPDATE_NAME (3) +#define UPDATE_FULL (4) + +UINT _fx_directory_entry_read_ex(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, ULONG *entry, FX_DIR_ENTRY *destination_ptr, UINT hash); +UINT _fx_directory_exFAT_entry_read(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, ULONG *entry_ptr, FX_DIR_ENTRY *destination_ptr, UINT hash, UINT skip, UCHAR *unicode_name, UINT *unicode_len); +UINT _fx_directory_exFAT_entry_write(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr, UCHAR update_level); +UINT _fx_directory_exFAT_unicode_entry_write(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr, UCHAR update_level, USHORT *unicode_name, + UINT unicode_len); +UINT _fx_directory_exFAT_free_search(FX_MEDIA *media_ptr, FX_DIR_ENTRY *directory_ptr, FX_DIR_ENTRY *entry_ptr); + +#endif /* FX_ENABLE_EXFAT */ + +UINT _fx_directory_entry_read(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, ULONG *entry, FX_DIR_ENTRY *destination_ptr); +UINT _fx_directory_entry_write(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr); +UINT _fx_directory_free_search(FX_MEDIA *media_ptr, FX_DIR_ENTRY *directory_ptr, FX_DIR_ENTRY *entry_ptr); +CHAR *_fx_directory_name_extract(CHAR *source_ptr, CHAR *dest_ptr); +UINT _fx_directory_search(FX_MEDIA *media_ptr, CHAR *name_ptr, FX_DIR_ENTRY *entry_ptr, FX_DIR_ENTRY *last_dir_ptr, CHAR **last_name_ptr); + +#endif + diff --git a/src/Middlewares/ST/filex/common/inc/fx_directory_exFAT.h b/src/Middlewares/ST/filex/common/inc/fx_directory_exFAT.h new file mode 100644 index 00000000..ad4bccc7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_directory_exFAT.h @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* fx_directory_exFAT.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the exFAT Directory entry component constants, */ +/* data definitions, and external references. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef FX_DIRECTORY_EXFAT_H +#define FX_DIRECTORY_EXFAT_H + +#include "fx_api.h" + +#define FX_EXFAT_DIR_ENTRY_TYPE_ALLOCATION_BITMAP 0x81 +#define FX_EXFAT_DIR_ENTRY_TYPE_UP_CASE_TABLE 0x82 +#define FX_EXFAT_DIR_ENTRY_TYPE_VOLUME_LABEL 0x83 +#define FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY 0x85 +#define FX_EXFAT_DIR_ENTRY_TYPE_VOLUME_GUID 0xA0 +#define FX_EXFAT_DIR_ENTRY_TYPE_STREAM_EXTENSION 0xC0 +#define FX_EXFAT_DIR_ENTRY_TYPE_FILE_NAME 0xC1 +#define FX_EXFAT_DIR_ENTRY_TYPE_CONTINUOUS_INFO_MANAGE 0xE0 +#define FX_EXFAT_DIR_ENTRY_TYPE_CONTINUOUS_INFO 0xE1 +#define FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER 0x00 +#define FX_EXFAT_DIR_ENTRY_TYPE_FREE 0xFF + + +/* Define the directory entry size. */ + +#define FX_EXFAT_DIR_ENTRY_SIZE 32 + + +/* Define bit masks. */ + +#define FX_EXFAT_ENTRY_TYPE_CODE_MASK 0x1F +#define FX_EXFAT_ENTRY_TYPE_IMPORTANCE_MASK 0x20 +#define FX_EXFAT_ENTRY_TYPE_CATEGORY_MASK 0x40 +#define FX_EXFAT_ENTRY_TYPE_IN_USE_MASK 0x80 +#define FX_EXFAT_SECOND_FLAG_ALLOCATION_POSSIBLE_MASK 0x01 + + +/* Define common primary and secondary directory entry structure. */ + +#define FX_EXFAT_ENTRY_TYPE 0 /* Size 1 byte */ + + +/* Define primary-specific directory entry structure. */ + +#define FX_EXFAT_SECOND_COUNT 1 /* Size 1 byte */ +#define FX_EXFAT_CHECK_SUM 2 /* Size 2 bytes */ +#define FX_EXFAT_PRIM_FLAG 4 /* Size 2 bytes */ + + +/* Define secondary-specific directory entry structure. */ + +#define FX_EXFAT_SECOND_FLAG 1 /* Size 1 byte */ + + +/* Define common primary and secondary directory entry structure. */ + +#define FX_EXFAT_FIRST_CLUSTER 20 /* Size 4 bytes */ +#define FX_EXFAT_DATA_LENGTH 24 /* Size 8 bytes */ + + +/* Define Allocation Bitmap directory entry. */ + +#define FX_EXFAT_BIT_MAP_FLAGS 1 /* Size 1 byte */ + + +/* Define UP-case Table Entry specific. */ + +#define FX_EXFAT_UP_CASE_TABLE_CHECK_SUM 4 /* Size 4 bytes */ + + +/* Define Volume Label Entry specific. */ + +#define FX_EXFAT_CHAR_COUNT 1 /* Size 1 byte */ +#define FX_EXFAT_VOLUME_LABEL 2 /* Size 22 bytes */ + + +/* Define File directory entry specific. This is a primary item. */ + +#define FX_EXFAT_FILE_ATTR 4 /* Size 2 bytes */ +#define FX_EXFAT_CREATE_TIME 8 /* Size 4 bytes */ +#define FX_EXFAT_LAST_MODIFIED_TIME 12 /* Size 4 bytes */ +#define FX_EXFAT_LAST_ACCESSED_TIME 16 /* Size 4 bytes */ +#define FX_EXFAT_LAST_CREATE_10MS_INC 20 /* Size 1 byte */ +#define FX_EXFAT_LAST_MODIFIED_10MS_INC 21 /* Size 1 byte */ +#define FX_EXFAT_CREATE_UTC_OFFSET 22 /* Size 1 byte */ +#define FX_EXFAT_LAST_MODIFIED_UTC_OFFSET 23 /* Size 1 byte */ +#define FX_EXFAT_LAST_ACCESSED_UTC_OFFSET 24 /* Size 1 byte */ + + +/* Define Volume GUID directory entry specific. This is a primary item. */ + +#define FX_EXFAT_VOLUME_GUID 6 /* Size 16 bytes */ + + +/* Define Stream extension directory entry specific. This is a secondary item. */ + +#define FX_EXFAT_NAME_LENGTH 3 /* Size 1 byte */ +#define FX_EXFAT_NAME_HASH 4 /* Size 2 bytes */ +#define FX_EXFAT_VALID_DATA_LENGTH 8 /* Size 8 bytes */ + + +/* Define File Name directory entry specific. This is a secondary item. */ + +#define FX_EXFAT_FILE_NAME 2 /* Size 30 bytes */ + + +/* Define Continuous Information Manage directory entry specific. This is a secondary item. */ + +#define FX_EXFAT_VENDOR_GUID 2 /* Size 16 bytes */ +#define FX_EXFAT_FAT_CHECKSUM 20 /* Size 4 bytes */ + + +/* Define Continuous Information directory entry specific. This is a secondary item. */ + +#define FX_EXFAT_SET_CHECKSUM 18 /* Size 2 bytes */ + +#endif + diff --git a/src/Middlewares/ST/filex/common/inc/fx_fault_tolerant.h b/src/Middlewares/ST/filex/common/inc/fx_fault_tolerant.h new file mode 100644 index 00000000..8a535139 --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_fault_tolerant.h @@ -0,0 +1,414 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* fx_fault_tolerant.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the FileX Fault Tolerant component constants, */ +/* data definitions, and external references. It is assumed that */ +/* fx_api.h (and fx_port.h) have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef _FX_FAULT_TOLERANT_H_ +#define _FX_FAULT_TOLERANT_H_ + +#ifdef FX_ENABLE_FAULT_TOLERANT + +#ifndef FX_FAULT_TOLERANT +#error "FX_FAULT_TOLERANT must be defined with FX_ENABLE_FAULT_TOLERANT" +#endif /* FX_FAULT_TOLERANT */ + +/* Define ID of fault tolerant. */ +#define FX_FAULT_TOLERANT_ID 0x46544C52 + +/* Define fault tolerant version. */ +#define FX_FAULT_TOLERANT_VERSION_MAJOR 0x01 +#define FX_FAULT_TOLERANT_VERSION_MINOR 0x00 + +/* Define byte offset in boot sector where the cluster number of the Fault Tolerant Log file is. + Note that this field (byte 116 to 119) is marked as reserved by FAT 12/16/32/exFAT specification. */ +#ifndef FX_FAULT_TOLERANT_BOOT_INDEX +#define FX_FAULT_TOLERANT_BOOT_INDEX 116 +#endif /* FX_FAULT_TOLERANT_BOOT_INDEX */ + +/* Define the extension invoked when fault tolerant log is recovered or applied during enable API. */ +#ifndef FX_FAULT_TOLERANT_ENABLE_EXTENSION +#define FX_FAULT_TOLERANT_ENABLE_EXTENSION +#endif /* FX_FAULT_TOLERANT_ENABLE_EXTENSION */ + +/* Define the extension invoked when fault tolerant log is applied. */ +#ifndef FX_FAULT_TOLERANT_APPLY_LOGS_EXTENSION +#define FX_FAULT_TOLERANT_APPLY_LOGS_EXTENSION +#endif /* FX_FAULT_TOLERANT_APPLY_LOGS_EXTENSION */ + +/* If not-defined, default port-specific processing extensions to white space. */ +#ifndef FX_FAULT_TOLERANT_WRITE_LOG_FILE_EXTENSION +#define FX_FAULT_TOLERANT_WRITE_LOG_FILE_EXTENSION +#endif /* FX_FAULT_TOLERANT_WRITE_LOG_FILE_EXTENSION */ + +/* Define the maximum size of log file. */ +#define FX_FAULT_TOLERANT_MAXIMUM_LOG_FILE_SIZE 3072 + +/* For backward compatibility, map the symbols deprecated to FX_FAULT_TOLERANT_MINIMAL_BUFFER_SIZE. */ +#ifndef FX_FAULT_TOLERANT_MINIMAL_CLUSTER +#define FX_FAULT_TOLERANT_MINIMAL_CLUSTER FX_FAULT_TOLERANT_MAXIMUM_LOG_FILE_SIZE +#endif /* FX_FAULT_TOLERANT_MINIMAL_CLUSTER */ +#ifndef FX_FAULT_TOLERANT_MINIMAL_BUFFER_SIZE +#define FX_FAULT_TOLERANT_MINIMAL_BUFFER_SIZE FX_FAULT_TOLERANT_MAXIMUM_LOG_FILE_SIZE +#endif /* FX_FAULT_TOLERANT_MINIMAL_BUFFER_SIZE */ + +/* Define the states of the fault tolerant module. */ +#define FX_FAULT_TOLERANT_STATE_IDLE 0x00u +#define FX_FAULT_TOLERANT_STATE_STARTED 0x01u +#define FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN 0x02u + +/* Define types of logs. */ +#define FX_FAULT_TOLERANT_FAT_LOG_TYPE 1 +#define FX_FAULT_TOLERANT_DIR_LOG_TYPE 2 +#define FX_FAULT_TOLERANT_BITMAP_LOG_TYPE 3 + +/* Define operations of FAT chain. */ +#define FX_FAULT_TOLERANT_FAT_CHAIN_RECOVER 0 /* Recover new FAT chain. */ +#define FX_FAULT_TOLERANT_FAT_CHAIN_CLEANUP 1 /* Cleanup old FAT chain. */ + +/* Define flags for FAT chain log. */ +#define FX_FAULT_TOLERANT_FLAG_FAT_CHAIN_VALID 0x01 +#define FX_FAULT_TOLERANT_FLAG_BITMAP_USED 0x02 + +/* Define size of each section in log file. */ +#define FX_FAULT_TOLERANT_LOG_HEADER_SIZE sizeof(FX_FAULT_TOLERANT_LOG_HEADER) +#define FX_FAULT_TOLERANT_FAT_CHAIN_SIZE sizeof(FX_FAULT_TOLERANT_FAT_CHAIN) +#define FX_FAULT_TOLERANT_LOG_CONTENT_HEADER_SIZE sizeof(FX_FAULT_TOLERANT_LOG_CONTENT) + +/* Define offset of each section in log file. */ +#define FX_FAULT_TOLERANT_FAT_CHAIN_OFFSET (FX_FAULT_TOLERANT_LOG_HEADER_SIZE) +#define FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET (FX_FAULT_TOLERANT_LOG_HEADER_SIZE + FX_FAULT_TOLERANT_FAT_CHAIN_SIZE) + +/* Define size of log entries. */ +/* The total size of DIR log entry is variable. 16 is the fixed size of DIR log entry. */ +#define FX_FAULT_TOLERANT_FAT_LOG_ENTRY_SIZE sizeof(FX_FAULT_TOLERANT_FAT_LOG) +#define FX_FAULT_TOLERANT_BITMAP_LOG_ENTRY_SIZE sizeof(FX_FAULT_TOLERANT_BITMAP_LOG) +#define FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE sizeof(FX_FAULT_TOLERANT_DIR_LOG) + +#ifdef FX_FAULT_TOLERANT_TRANSACTION_FAIL_FUNCTION +#define FX_FAULT_TOLERANT_TRANSACTION_FAIL _fx_fault_tolerant_transaction_fail +#else +/* Define transaction fail for fault tolerant. */ +#define FX_FAULT_TOLERANT_TRANSACTION_FAIL(m) \ + if ((m) -> fx_media_fault_tolerant_enabled == FX_TRUE) \ + { \ + (m) -> fx_media_fault_tolerant_transaction_count--; \ + if ((m) -> fx_media_fault_tolerant_transaction_count == 0) \ + { \ + _fx_fault_tolerant_recover(m); \ + _fx_fault_tolerant_reset_log_file(m); \ + } \ + } + +#endif /* FX_FAULT_TOLERANT_TRANSACTION_FAIL_FUNCTION */ + +/* Log file format + * The entire log file fits into one cluster. + * + * 1 2 3 + * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 + * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + ID + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + Total Log Size (in Bytes) + Header Checksum + Log Header + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + version major + version minor + reserved + + * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + Checksum of FAT chain + Flag | Reserved + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + Insertion Point - Front + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + Head cluster of newly created FAT chain + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ FAT Chain + * + Head cluster of original FAT chain + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + Insertion Point - Back + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + Next Deletion Point + + * ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + checksum of log content + count of log entries + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + (log 0) . + + * + . + + * + . + + * + . + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + (log 1) . + + * + . + Log Entries + * + . + + * + . + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + ... + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + (log N) . + + * + . + + * + . + + * + . + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + * + * Log Header + * + * * ID: It is fixed value FX_FAULT_TOLERANT_ID. + * * Total Size: Total size (in bytes) of the log file, including Log Header, FAT Chain and Log Entries + * * Header Checksum: It is the checksum of all data in log header. + * * Version Major: The major version number. + * * Version Minor: The minor version number. + * * Reserved: Reserved for future use. + * + * FAT Chain + * + * * Checksum of FAT chain: It is the checksum of all data in the FAT Chain section. + * * Flag: 8 bits. The 1-6 bits are not used (from left to right). + * bit 7: When set, bitmap is used in old FAT chain. + * bit 8: When set, FAT chain is valid. + * * Reserved: Reserved for future use. + * * Insertion Point - Front: The cluster where the newly created chain is attached to + * * Head cluster of new FAT chain. It is the head cluster of new FAT chain. + * * Head cluster of oritinal FAT chain. It is the head cluster of the original FAT chain, + * which will be removed. + * * Inswertion Point - Back: The original cluster right after the newly created chain is inserted. + * * Next Deletion Point: next session of cluster to delete. It is used during deleting FAT chain. + * The deltion is carried out in stages for perofmrance reasons. When delting a FAT chain, the + * Next Deletion Point is chosen, and the chain between head and the Next Deletion Point is deleted. + * + * Log Entries: + * + * * Checksum of log entries: It is the checksum of all data in Log Entries + * * Counter of log entries: It is the counter of all log entries in Log content. + * * log 0 ... log N: Log entries. The formats are described below. + */ + +/* Defined structure of log header. + + + */ +typedef struct FX_FAULT_TOLERANT_LOG_HEADER_STRUCT +{ + ULONG fx_fault_tolerant_log_header_id; + USHORT fx_fault_tolerant_log_header_total_size; + USHORT fx_fault_tolerant_log_header_checksum; + UCHAR fx_fault_tolerant_log_header_version_major; + UCHAR fx_fault_tolerant_log_header_version_minor; + USHORT fx_fault_tolerant_log_header_reserved; +} FX_FAULT_TOLERANT_LOG_HEADER; + +/* Define structure of FAT chain. */ +typedef struct FX_FAULT_TOLERANT_FAT_CHAIN_STRUCT +{ + USHORT fx_fault_tolerant_FAT_chain_checksumm; + UCHAR fx_fault_tolerant_FAT_chain_flag; + UCHAR fx_fault_tolerant_FAT_chain_reserved; + + ULONG fx_fault_tolerant_FAT_chain_insertion_front; + ULONG fx_fault_tolerant_FAT_chain_head_new; + ULONG fx_fault_tolerant_FAT_chain_head_original; + ULONG fx_fault_tolerant_FAT_chain_insertion_back; + ULONG fx_fault_tolerant_FAT_chain_next_deletion; +} FX_FAULT_TOLERANT_FAT_CHAIN; + + +/* Define structure of Log content. */ +typedef struct FX_FAULT_TOLERANT_LOG_CONTENT_STRUCT +{ + USHORT fx_fault_tolerant_log_content_checksum; + USHORT fx_fault_tolerant_log_content_count; +} FX_FAULT_TOLERANT_LOG_CONTENT; + + +/* 3 types of log entries are defined. */ +/* FAT log format + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + type + size + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + cluster + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + value + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + * Description: + * + * Type: FX_FAULT_TOLERANT_FAT_LOG. + * Size: The size of this log entry. + * Cluster: The cluster number in FAT. + * Value: The value of cluster in FAT. + * + */ +typedef struct FX_FAULT_TOLERANT_FAT_LOG_STRUCT +{ + USHORT fx_fault_tolerant_FAT_log_type; + USHORT fx_fault_tolerant_FAT_log_size; + ULONG fx_fault_tolerant_FAT_log_cluster; + ULONG fx_fault_tolerant_FAT_log_value; +} FX_FAULT_TOLERANT_FAT_LOG; + +/* DIR log format + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + type + size + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + sector offset + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + log sector + + * + + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + log data + + * + . + + * + . + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + * Fields description, + * + * Type: FX_FAULT_TOLERANT_DIRECTORY_LOG + * Size: The size of this log entry. + * Sector Offset: The offset in original sector this DIR is trying to write to. + * Log Sector: The original sector this DIR is trying to write to. + * Log Data: Content of DIR entries. + * + */ +typedef struct FX_FAULT_TOLERANT_DIR_LOG_STRUCT +{ + USHORT fx_fault_tolerant_dir_log_type; + USHORT fx_fault_tolerant_dir_log_size; + ULONG fx_fault_tolerant_dir_log_offset; + ULONG64 fx_fault_tolerant_dir_log_sector; +} FX_FAULT_TOLERANT_DIR_LOG; + +/* Bitmap log format + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + type + size + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + cluster + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + value + + * +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + * + * Description, + * + * Type: FX_FAULT_TOLERANT_BITMAP_LOG. + * Size: The size of this log entry. + * Cluster: The cluster number in FAT. + * Value: The value of cluster in FAT. + */ +typedef struct FX_FAULT_TOLERANT_BITMAP_LOG_STRUCT +{ + USHORT fx_fault_tolerant_bitmap_log_type; + USHORT fx_fault_tolerant_bitmap_log_size; + ULONG fx_fault_tolerant_bitmap_log_cluster; + ULONG fx_fault_tolerant_bitmap_log_value; +} FX_FAULT_TOLERANT_BITMAP_LOG; + + +/* This function checks whether or not the log file exists, and creates the log file if it does not exist. */ +UINT _fx_fault_tolerant_enable(FX_MEDIA *media_ptr, VOID *memory_buffer, UINT memory_size); +UINT _fxe_fault_tolerant_enable(FX_MEDIA *media_ptr, VOID *memory_buffer, UINT memory_size); + +/* This function resets statistics and marks the start of a transaction. */ +UINT _fx_fault_tolerant_transaction_start(FX_MEDIA *media_ptr); + +/* This function marks the end of a transaction and completes the log file. + * Then it applies all data in the log file to the file system. + * Finally it resets the log header section. */ +UINT _fx_fault_tolerant_transaction_end(FX_MEDIA *media_ptr); + +/* This function resets the log file. */ +UINT _fx_fault_tolerant_reset_log_file(FX_MEDIA *media_ptr); + +/* This function applies the log file to the file system. */ +UINT _fx_fault_tolerant_apply_logs(FX_MEDIA *media_ptr); + +/* This function recovers FAT chain. */ +UINT _fx_fault_tolerant_recover(FX_MEDIA *media_ptr); + +/* This function adds a FAT log entry. */ +UINT _fx_fault_tolerant_add_FAT_log(FX_MEDIA *media_ptr, ULONG cluster, ULONG value); + +/* This function adds a directory log entry. */ +UINT _fx_fault_tolerant_add_dir_log(FX_MEDIA *media_ptr, ULONG64 logical_sector, ULONG offset, + UCHAR *data, ULONG data_size); +#ifdef FX_ENABLE_EXFAT +/* This function adds a bitmap log entry. */ +UINT _fx_fault_tolerant_add_bitmap_log(FX_MEDIA *media_ptr, ULONG cluster, ULONG value); + +/* This function adds a checksum log entry. */ +UINT _fx_fault_tolerant_add_checksum_log(FX_MEDIA *media_ptr, ULONG64 logical_sector, ULONG offset, USHORT checksum); +#endif /* FX_ENABLE_EXFAT */ + +/* This function sets the FAT chain. */ +UINT _fx_fault_tolerant_set_FAT_chain(FX_MEDIA *media_ptr, UINT use_bitmap, ULONG insertion_front, + ULONG new_head_cluster, ULONG original_head_cluster, ULONG insertion_back); + +/* This function reads a FAT entry from log file. If it doesn't exist in log file, return and read from FAT entry directly. */ +UINT _fx_fault_tolerant_read_FAT(FX_MEDIA *media_ptr, ULONG cluster, ULONG *value, ULONG log_type); + +/* This function reads directory sector from log file. */ +UINT _fx_fault_tolerant_read_directory_sector(FX_MEDIA *media_ptr, ULONG64 logical_sector, + VOID *buffer_ptr, ULONG64 sectors); + +/* This function calculates the checksum of the log header. */ +USHORT _fx_fault_tolerant_calculate_checksum(UCHAR *data, UINT len); + +/* This function cleans up FAT chain. */ +UINT _fx_fault_tolerant_cleanup_FAT_chain(FX_MEDIA *media_ptr, UINT operation); + +/* This function reads log file from file system to memory buffer. */ +UINT _fx_fault_tolerant_read_log_file(FX_MEDIA *media_ptr); + +/* This function writes data of one sector from memory to log file in file system. */ +UINT _fx_fault_tolerant_write_log_file(FX_MEDIA *media_ptr, ULONG relative_sector); + +/* This function creates log file. */ +UINT _fx_fault_tolerant_create_log_file(FX_MEDIA *media_ptr); + +#ifdef FX_FAULT_TOLERANT_TRANSACTION_FAIL_FUNCTION +/* This function cleans up resources created by fault tolerant when transaction fails. */ +UINT _fx_fault_tolerant_transaction_fail(FX_MEDIA *media_ptr); +#endif /* FX_FAULT_TOLERANT_TRANSACTION_FAIL_FUNCTION */ + + +#endif /* FX_ENABLE_FAULT_TOLERANT */ + +#endif /* _FX_FAULT_TOLERANT_H_ */ + diff --git a/src/Middlewares/ST/filex/common/inc/fx_file.h b/src/Middlewares/ST/filex/common/inc/fx_file.h new file mode 100644 index 00000000..ce8bad78 --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_file.h @@ -0,0 +1,125 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* fx_file.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the FileX File component constants, data */ +/* definitions, and external references. It is assumed that fx_api.h */ +/* (and fx_port.h) have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable one line function, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef FX_FILE_H +#define FX_FILE_H + + +/* Define the external File component function prototypes. */ + +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT _fx_file_allocate(FX_FILE *file_ptr, ULONG size); +#else +#define _fx_file_allocate(f, s) _fx_file_extended_allocate(f, (ULONG64)s); +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +UINT _fx_file_attributes_read(FX_MEDIA *media_ptr, CHAR *file_name, UINT *attributes_ptr); +UINT _fx_file_attributes_set(FX_MEDIA *media_ptr, CHAR *file_name, UINT attributes); +UINT _fx_file_best_effort_allocate(FX_FILE *file_ptr, ULONG size, ULONG *actual_size_allocated); +UINT _fx_file_close(FX_FILE *file_ptr); +UINT _fx_file_create(FX_MEDIA *media_ptr, CHAR *file_name); +UINT _fx_file_date_time_set(FX_MEDIA *media_ptr, CHAR *file_name, + UINT year, UINT month, UINT day, UINT hour, UINT minute, UINT second); +UINT _fx_file_delete(FX_MEDIA *media_ptr, CHAR *file_name); +UINT _fx_file_open(FX_MEDIA *media_ptr, FX_FILE *file_ptr, CHAR *file_name, + UINT open_type); +UINT _fx_file_read(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG request_size, ULONG *actual_size); +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT _fx_file_relative_seek(FX_FILE *file_ptr, ULONG byte_offset, UINT seek_from); +#else +#define _fx_file_relative_seek(f, b, sf) _fx_file_extended_relative_seek(f, (ULONG64)b, sf); +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +UINT _fx_file_rename(FX_MEDIA *media_ptr, CHAR *old_file_name, CHAR *new_file_name); +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT _fx_file_seek(FX_FILE *file_ptr, ULONG byte_offset); +UINT _fx_file_truncate(FX_FILE *file_ptr, ULONG size); +UINT _fx_file_truncate_release(FX_FILE *file_ptr, ULONG size); +#else +#define _fx_file_seek(f, b) _fx_file_extended_seek(f, (ULONG64)b) +#define _fx_file_truncate(f, s) _fx_file_extended_truncate(f, (ULONG64)s); +#define _fx_file_truncate_release(f, s) _fx_file_extended_truncate_release(f, (ULONG64)s); +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ +UINT _fx_file_write(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG size); +UINT _fx_file_write_notify_set(FX_FILE *file_ptr, VOID (*file_write_notify)(FX_FILE *)); +UINT _fx_file_extended_allocate(FX_FILE *file_ptr, ULONG64 size); +UINT _fx_file_extended_best_effort_allocate(FX_FILE *file_ptr, ULONG64 size, ULONG64 *actual_size_allocated); +UINT _fx_file_extended_relative_seek(FX_FILE *file_ptr, ULONG64 byte_offset, UINT seek_from); +UINT _fx_file_extended_seek(FX_FILE *file_ptr, ULONG64 byte_offset); +UINT _fx_file_extended_truncate(FX_FILE *file_ptr, ULONG64 size); +UINT _fx_file_extended_truncate_release(FX_FILE *file_ptr, ULONG64 size); + +UINT _fxe_file_allocate(FX_FILE *file_ptr, ULONG size); +UINT _fxe_file_attributes_read(FX_MEDIA *media_ptr, CHAR *file_name, UINT *attributes_ptr); +UINT _fxe_file_attributes_set(FX_MEDIA *media_ptr, CHAR *file_name, UINT attributes); +UINT _fxe_file_best_effort_allocate(FX_FILE *file_ptr, ULONG size, ULONG *actual_size_allocated); +UINT _fxe_file_close(FX_FILE *file_ptr); +UINT _fxe_file_create(FX_MEDIA *media_ptr, CHAR *file_name); +UINT _fxe_file_date_time_set(FX_MEDIA *media_ptr, CHAR *file_name, + UINT year, UINT month, UINT day, UINT hour, UINT minute, UINT second); +UINT _fxe_file_delete(FX_MEDIA *media_ptr, CHAR *file_name); +UINT _fxe_file_open(FX_MEDIA *media_ptr, FX_FILE *file_ptr, CHAR *file_name, + UINT open_type, UINT file_control_block_size); +UINT _fxe_file_read(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG request_size, ULONG *actual_size); +UINT _fxe_file_relative_seek(FX_FILE *file_ptr, ULONG byte_offset, UINT seek_from); +UINT _fxe_file_rename(FX_MEDIA *media_ptr, CHAR *old_file_name, CHAR *new_file_name); +UINT _fxe_file_seek(FX_FILE *file_ptr, ULONG byte_offset); +UINT _fxe_file_truncate(FX_FILE *file_ptr, ULONG size); +UINT _fxe_file_truncate_release(FX_FILE *file_ptr, ULONG size); +UINT _fxe_file_write(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG size); +UINT _fxe_file_write_notify_set(FX_FILE *file_ptr, VOID (*file_write_notify)(FX_FILE *)); +UINT _fxe_file_extended_allocate(FX_FILE *file_ptr, ULONG64 size); +UINT _fxe_file_extended_best_effort_allocate(FX_FILE *file_ptr, ULONG64 size, ULONG64 *actual_size_allocated); +UINT _fxe_file_extended_relative_seek(FX_FILE *file_ptr, ULONG64 byte_offset, UINT seek_from); +UINT _fxe_file_extended_seek(FX_FILE *file_ptr, ULONG64 byte_offset); +UINT _fxe_file_extended_truncate(FX_FILE *file_ptr, ULONG64 size); +UINT _fxe_file_extended_truncate_release(FX_FILE *file_ptr, ULONG64 size); + +#endif + diff --git a/src/Middlewares/ST/filex/common/inc/fx_media.h b/src/Middlewares/ST/filex/common/inc/fx_media.h new file mode 100644 index 00000000..de6c8a32 --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_media.h @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* fx_media.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the FileX Media component constants, data */ +/* definitions, and external references. It is assumed that fx_api.h */ +/* (and fx_port.h) have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef FX_MEDIA_H +#define FX_MEDIA_H + + +/* Define the external Media component function prototypes. */ + +UINT _fx_media_abort(FX_MEDIA *media_ptr); +UINT _fx_media_cache_invalidate(FX_MEDIA *media_ptr); +UINT _fx_media_check(FX_MEDIA *media_ptr, UCHAR *scratch_memory_ptr, ULONG scratch_memory_size, ULONG error_correction_option, ULONG *errors_detected); +UINT _fx_media_close(FX_MEDIA *media_ptr); +UINT _fx_media_flush(FX_MEDIA *media_ptr); +UINT _fx_media_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, UCHAR *memory_ptr, UINT memory_size, + CHAR *volume_name, UINT number_of_fats, UINT directory_entries, UINT hidden_sectors, + ULONG total_sectors, UINT bytes_per_sector, UINT sectors_per_cluster, + UINT heads, UINT sectors_per_track); +UINT _fx_media_exFAT_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, UCHAR *memory_ptr, UINT memory_size, + CHAR *volume_name, UINT number_of_fats, ULONG64 hidden_sectors, ULONG64 total_sectors, UINT bytes_per_sector, UINT sectors_per_cluster, UINT volume_serial_number, UINT boundary_unit); +UINT _fx_media_open(FX_MEDIA *media_ptr, CHAR *media_name, + VOID (*media_driver)(FX_MEDIA *), VOID *driver_info_ptr, + VOID *memory_ptr, ULONG memory_size); +UINT _fx_media_read(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr); +UINT _fx_media_space_available(FX_MEDIA *media_ptr, ULONG *available_bytes_ptr); +UINT _fx_media_volume_get(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_source); +UINT _fx_media_volume_get_extended(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_name_buffer_length, UINT volume_source); +UINT _fx_media_volume_set(FX_MEDIA *media_ptr, CHAR *volume_name); +UINT _fx_media_write(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr); +UINT _fx_media_open_notify_set(FX_MEDIA *media_ptr, VOID (*media_open_notify)(FX_MEDIA *)); +UINT _fx_media_close_notify_set(FX_MEDIA *media_ptr, VOID (*media_close_notify)(FX_MEDIA *)); +UINT _fx_media_extended_space_available(FX_MEDIA *media_ptr, ULONG64 *available_bytes_ptr); + + +UINT _fxe_media_abort(FX_MEDIA *media_ptr); +UINT _fxe_media_cache_invalidate(FX_MEDIA *media_ptr); +UINT _fxe_media_check(FX_MEDIA *media_ptr, UCHAR *scratch_memory_ptr, ULONG scratch_memory_size, ULONG error_correction_option, ULONG *errors_detected); +UINT _fxe_media_close(FX_MEDIA *media_ptr); +UINT _fxe_media_flush(FX_MEDIA *media_ptr); +UINT _fxe_media_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, UCHAR *memory_ptr, UINT memory_size, + CHAR *volume_name, UINT number_of_fats, UINT directory_entries, UINT hidden_sectors, + ULONG total_sectors, UINT bytes_per_sector, UINT sectors_per_cluster, + UINT heads, UINT sectors_per_track); +UINT _fxe_media_exFAT_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, UCHAR *memory_ptr, UINT memory_size, + CHAR *volume_name, UINT number_of_fats, ULONG64 hidden_sectors, ULONG64 total_sectors, UINT bytes_per_sector, UINT sectors_per_cluster, UINT volume_serial_number, UINT boundary_unit); +UINT _fxe_media_open(FX_MEDIA *media_ptr, CHAR *media_name, + VOID (*media_driver)(FX_MEDIA *), VOID *driver_info_ptr, + VOID *memory_ptr, ULONG memory_size, UINT media_control_block_size); +UINT _fxe_media_read(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr); +UINT _fxe_media_space_available(FX_MEDIA *media_ptr, ULONG *available_bytes_ptr); +UINT _fxe_media_volume_get(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_source); +UINT _fxe_media_volume_get_extended(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_name_buffer_length, UINT volume_source); +UINT _fxe_media_volume_set(FX_MEDIA *media_ptr, CHAR *volume_name); +UINT _fxe_media_write(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr); +UINT _fxe_media_open_notify_set(FX_MEDIA *media_ptr, VOID (*media_open_notify)(FX_MEDIA *)); +UINT _fxe_media_close_notify_set(FX_MEDIA *media_ptr, VOID (*media_close_notify)(FX_MEDIA *)); +UINT _fxe_media_extended_space_available(FX_MEDIA *media_ptr, ULONG64 *available_bytes_ptr); + + +/* Define the internal Media component function prototypes. */ + +ULONG _fx_media_check_FAT_chain_check(FX_MEDIA *media_ptr, ULONG starting_cluster, ULONG *last_valid_cluster, ULONG *total_valid_clusters, UCHAR *logical_fat); +ULONG _fx_media_check_lost_cluster_check(FX_MEDIA *media_ptr, UCHAR *logical_fat, ULONG total_clusters, ULONG error_correction_option); +ULONG _fx_media_check_exFAT_lost_cluster_check(FX_MEDIA *media_ptr, UCHAR *logical_fat, ULONG total_clusters, ULONG error_correction_option); +UINT _fx_media_boot_info_extract(FX_MEDIA *media_ptr); + +#endif + diff --git a/src/Middlewares/ST/filex/common/inc/fx_system.h b/src/Middlewares/ST/filex/common/inc/fx_system.h new file mode 100644 index 00000000..dd5f0d8f --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_system.h @@ -0,0 +1,175 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* fx_system.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the FileX system constants and global data */ +/* definitions, including external references. It is assumed that */ +/* fx_api.h (and fx_port.h) have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef FX_SYSTEM_H +#define FX_SYSTEM_H + + +/* Define System component constants. */ + +#define FX_TIMER_ID ((ULONG) 0x46585359) + + +/* Define the external System component function prototypes. */ + +VOID _fx_system_initialize(VOID); +UINT _fx_system_date_set(UINT year, UINT month, UINT day); +UINT _fx_system_time_set(UINT hour, UINT minute, UINT second); +UINT _fx_system_date_get(UINT *year, UINT *month, UINT *day); +UINT _fx_system_time_get(UINT *hour, UINT *minute, UINT *second); +VOID _fx_system_timer_entry(ULONG id); + +UINT _fxe_system_date_set(UINT year, UINT month, UINT day); +UINT _fxe_system_time_set(UINT hour, UINT minute, UINT second); +UINT _fxe_system_date_get(UINT *year, UINT *month, UINT *day); +UINT _fxe_system_time_get(UINT *hour, UINT *minute, UINT *second); + + +/* System Component data declarations follow. */ + +/* Determine if the initialization function of this component is including + this file. If so, make the data definitions really happen. Otherwise, + make them extern so other functions in the component can access them. */ + +#ifdef FX_SYSTEM_INIT +#define SYSTEM_DECLARE +#else +#define SYSTEM_DECLARE extern +#endif + + +/* Define the head pointer of the opened media list. */ + +SYSTEM_DECLARE FX_MEDIA *_fx_system_media_opened_ptr; + + +/* Define the variable that holds the number of open media. */ + +SYSTEM_DECLARE ULONG _fx_system_media_opened_count; + + +/* Define the system date variable. */ + +SYSTEM_DECLARE UINT _fx_system_date; + + +/* Define the system time variable. */ + +SYSTEM_DECLARE UINT _fx_system_time; + + +/* Define the variable that holds the maximum size of the sector cache. */ + +SYSTEM_DECLARE ULONG _fx_system_media_max_sector_cache; + + +/* Define the variable that holds the maximum size of the FAT cache. */ + +SYSTEM_DECLARE ULONG _fx_system_media_max_fat_cache; + + +/* Define the global FileX build options variables. These variables contain a bit + map representing how the FileX library was built. The following are the bit + field definitions: + + _fx_system_build_options_1: + + Bit(s) Meaning + + 31-24 FX_MAX_LONG_NAME_LEN + 23-16 FX_MAX_LAST_NAME_LEN + 15-11 Reserved + 10 FX_NO_TIMER defined + 9 FX_SINGLE_THREAD defined + 8 FX_DONT_UPDATE_OPEN_FILES defined + 7 FX_MEDIA_DISABLE_SEARCH_CACHE defined + 6 FX_MEDIA_STATISTICS_DISABLE defined + 5 Reserved + 4 FX_SINGLE_OPEN_LEGACY defined + 3 FX_RENAME_PATH_INHERIT defined + 2 FX_NO_LOCAL_PATH defined + 1 FX_FAULT_TOLERANT_DATA defined + 0 FX_FAULT_TOLERANT defined + + _fx_system_build_options_2: + + Bit(s) Meaning + + 31-16 FX_MAX_SECTOR_CACHE + 15-8 FX_FAT_MAP_SIZE + 7-0 FX_MAX_FAT_CACHE + + _fx_system_build_options_3: + + Bit(s) Meaning + + 31-24 Reserved + 23-16 FX_UPDATE_RATE_IN_SECONDS + 15-0 FX_UPDATE_RATE_IN_TICKS + + Note that values greater than the value that can be represented in the build options + bit field are represented as all ones in the bit field. For example, if FX_MAX_LONG_NAME_LEN + is 256, the value in the bits 31-24 of _fx_system_build_options_1 is 0xFF, which is 255 + decimal. */ + +SYSTEM_DECLARE ULONG _fx_system_build_options_1; +SYSTEM_DECLARE ULONG _fx_system_build_options_2; +SYSTEM_DECLARE ULONG _fx_system_build_options_3; + + +/* Define system timer control block. If accurate date/time stamps on + files is not needed, the define FX_NO_TIMER should be used when + compiling fx_system_initialize.c to eliminate the FileX timer. */ + +#ifndef FX_NO_TIMER +SYSTEM_DECLARE TX_TIMER _fx_system_timer; +#endif + +#endif + diff --git a/src/Middlewares/ST/filex/common/inc/fx_unicode.h b/src/Middlewares/ST/filex/common/inc/fx_unicode.h new file mode 100644 index 00000000..d4035b7e --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_unicode.h @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* fx_unicode.h PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the FileX Unicode component constants, data */ +/* definitions, and external references. It is assumed that fx_api.h */ +/* (and fx_port.h) have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ + +#ifndef FX_UNICODE_H +#define FX_UNICODE_H + + +/* Define external data for the Unicode component. */ + +extern UCHAR _fx_unicode_temp_long_file_name[FX_MAX_LONG_NAME_LEN]; +extern UCHAR _fx_unicode_search_name[FX_MAX_LONG_NAME_LEN * 2]; + + +/* Define the external Unicode component function prototypes. */ + +UINT _fx_unicode_directory_create(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *short_name); +UINT _fx_unicode_directory_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name); +UINT _fx_unicode_file_create(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *short_name); +ULONG _fx_unicode_length_get(UCHAR *unicode_name); +ULONG _fx_unicode_length_get_extended(UCHAR *unicode_name, UINT buffer_length); +UINT _fx_unicode_name_get(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length); +UINT _fx_unicode_name_get_extended(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length, ULONG unicode_name_buffer_length); +UINT _fx_unicode_file_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name); +UINT _fx_unicode_short_name_get(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name); +UINT _fx_unicode_short_name_get_extended(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name, ULONG short_name_buffer_length); + +UINT _fxe_unicode_directory_create(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *short_name); +UINT _fxe_unicode_directory_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name); +UINT _fxe_unicode_file_create(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *short_name); +UINT _fxe_unicode_file_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name); +UINT _fxe_unicode_name_get(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length); +UINT _fxe_unicode_name_get_extended(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length, ULONG unicode_name_buffer_length); +UINT _fxe_unicode_short_name_get(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name); +UINT _fxe_unicode_short_name_get_extended(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name, ULONG short_name_buffer_length); + +/* Define the internal Unicode component function prototypes. */ + +UINT _fx_unicode_directory_search(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr, + UCHAR *short_name, ULONG short_name_buffer_length, + UCHAR *unicode_name, ULONG *unicode_name_length, ULONG unicode_name_buffer_length); +UINT _fx_unicode_directory_entry_read(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, + ULONG *entry_ptr, FX_DIR_ENTRY *destination_ptr, + UCHAR *unicode_name, ULONG *unicode_size); +UINT _fx_unicode_directory_entry_change(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr, UCHAR *unicode_name, ULONG unicode_name_length); + + +#endif + diff --git a/src/Middlewares/ST/filex/common/inc/fx_user_sample.h b/src/Middlewares/ST/filex/common/inc/fx_user_sample.h new file mode 100644 index 00000000..68d92810 --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_user_sample.h @@ -0,0 +1,261 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* fx_user.h PORTABLE C */ +/* 6.1.10 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring FileX in specific */ +/* ways. This file will have an effect only if the application and */ +/* FileX library are built with FX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building FileX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added product constants */ +/* to enable code */ +/* size optimization, */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), and */ +/* added standalone support, */ +/* resulting in version 6.1.5 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), and */ +/* added product constant to */ +/* support variable sector */ +/* size in exFAT, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef FX_USER_H +#define FX_USER_H + + +/* Define various build options for the FileX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ + + +/* Override various options with default values already assigned in fx_api.h or fx_port.h. Please + also refer to fx_port.h for descriptions on each of these options. */ + + +/* Defines the maximum size of long file names supported by FileX. The default value is 33. The + minimum value is 13 and the maximum value is 256. */ + +/*#define FX_MAX_LONG_NAME_LEN 256 */ +/*#define FX_MAX_LAST_NAME_LEN 256 */ /* Must be as large or larger than FX_MAX_LONG_NAME_LEN */ + + +/* Defines the maximum number of logical sectors that can be cached by FileX. The cache memory + supplied to FileX at fx_media_open determines how many sectors can actually be cached. */ + +/*#define FX_MAX_SECTOR_CACHE 256 */ /* Minimum value is 2, all other values must be power of 2. */ + + +/* Defines the size in bytes of the bit map used to update the secondary FAT sectors. The larger the value the + less unnecessary secondary FAT sector writes. */ + +/*#define FX_FAT_MAP_SIZE 128 */ /* Minimum value is 1, no maximum value. */ + + +/* Defines the number of entries in the FAT cache. */ + +/*#define FX_MAX_FAT_CACHE 16 */ /* Minimum value is 8, all values must be a power of 2. */ + + +/* Defines the number of seconds the time parameters are updated in FileX. */ + +/*#define FX_UPDATE_RATE_IN_SECONDS 10 */ + + +/* Defines the number of ThreadX timer ticks required to achieve the update rate specified by + FX_UPDATE_RATE_IN_SECONDS defined previously. By default, the ThreadX timer tick is 10ms, + so the default value for this constant is 1000. */ + +/*#define FX_UPDATE_RATE_IN_TICKS 1000 */ + + +/* Defined, FileX is built without update to the time parameters. */ + +/*#define FX_NO_TIMER */ + + +/* Defined, FileX does not update already opened files. */ + +/*#define FX_DONT_UPDATE_OPEN_FILES */ + + +/* Defined, the file search cache optimization is disabled. */ + +/*#define FX_MEDIA_DISABLE_SEARCH_CACHE */ + + +/* Defined, the direct read sector update of cache is disabled. */ + +/*#define FX_DISABLE_DIRECT_DATA_READ_CACHE_FILL */ + + +/* Defined, gathering of media statistics is disabled. */ + +/*#define FX_MEDIA_STATISTICS_DISABLE */ + + +/* Defined, legacy single open logic for the same file is enabled. */ + +/*#define FX_SINGLE_OPEN_LEGACY */ + + +/* Defined, renaming inherits path information. */ + +/*#define FX_RENAME_PATH_INHERIT */ + + +/* Defined, local path logic is disabled. */ + +/*#define FX_NO_LOCAL_PATH */ + + +/* Defined, FileX is able to access exFAT file system. + + FileX supports the Microsoft exFAT file system format. + Your use of exFAT technology in your products requires a separate + license from Microsoft. Please see the following link for further + details on exFAT licensing: + + https://www.microsoft.com/en-us/legal/intellectualproperty/mtl/exfat-licensing.aspx +*/ + +/* #define FX_ENABLE_EXFAT */ + + +/* Define bitmap cache size for exFAT. Size should be minimum one sector size and maximum 4096. + For applications using muliple media devices with varing sector size, the value should be set to the + size of largest sector size */ + +/* #define FX_EXFAT_MAX_CACHE_SIZE 512 */ + + +/* Define FileX internal protection macros. If FX_SINGLE_THREAD is defined, + these protection macros are effectively disabled. However, for multi-thread + uses, the macros are setup to utilize a ThreadX mutex for multiple thread + access control into an open media. */ + +/* #define FX_SINGLE_THREAD */ + + +/* Defined, Filex will be used in standalone mode (without ThreadX) */ + +/* #define FX_STANDALONE_ENABLE */ + + +/* Defined, data sector write requests are flushed immediately to the driver. */ + +/*#define FX_FAULT_TOLERANT_DATA */ + + +/* Defined, system sector write requests (including FAT and directory entry requests) + are flushed immediately to the driver. */ + +/*#define FX_FAULT_TOLERANT */ + + +/* Defined, enables 64-bits sector addresses used in I/O driver. */ + +/*#define FX_DRIVER_USE_64BIT_LBA */ + + +/* Defined, enables FileX fault tolerant service. */ + +/*#define FX_ENABLE_FAULT_TOLERANT */ + + +/* Define byte offset in boot sector where the cluster number of the Fault Tolerant Log file is. + Note that this field (byte 116 to 119) is marked as reserved by FAT 12/16/32/exFAT specification. */ + +/*#define FX_FAULT_TOLERANT_BOOT_INDEX 116 */ + +/* Below FX_DISABLE_XXX macros can be used for code size optimization required for memory + critical aplications */ + +/* Defined, error checking is disabled. */ + +/*#define FX_DISABLE_ERROR_CHECKING */ + + +/* Defined, cache is disabled. */ + +/*#define FX_DISABLE_CACHE */ + + +/* Defined, file close is disabled. */ + +/*#define FX_DISABLE_FILE_CLOSE */ + + +/* Defined, fast open is disabled. */ + +/*#define FX_DISABLE_FAST_OPEN */ + + +/* Defined, force memory operations are disabled. */ + +/*#define FX_DISABLE_FORCE_MEMORY_OPERATION */ + + +/* Defined, build options is disabled. */ + +/*#define FX_DISABLE_BUILD_OPTIONS */ + + +/* Defined, one line function is disabled. */ + +/*#define FX_DISABLE_ONE_LINE_FUNCTION */ + + +/* Defined, FAT entry refresh is disabled. */ + +/*#define FX_DIABLE_FAT_ENTRY_REFRESH */ + + +/* Defined, consecutive detect is disabled. */ + +/*#define FX_DISABLE_CONSECUTIVE_DETECT */ + + +#endif + diff --git a/src/Middlewares/ST/filex/common/inc/fx_utility.h b/src/Middlewares/ST/filex/common/inc/fx_utility.h new file mode 100644 index 00000000..ada80c78 --- /dev/null +++ b/src/Middlewares/ST/filex/common/inc/fx_utility.h @@ -0,0 +1,126 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* fx_utility.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the FileX Utility component constants, data */ +/* definitions, and external references. It is assumed that fx_api.h */ +/* (and fx_port.h) have already been included. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), and */ +/* changed prototype for */ +/* exFAT size calculate */ +/* utility function, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef FX_UTILITY_H +#define FX_UTILITY_H + + +/* Define the internal Utility component function prototypes. */ + +UINT _fx_utility_16_unsigned_read(UCHAR *source_ptr); +VOID _fx_utility_16_unsigned_write(UCHAR *dest_ptr, UINT value); +ULONG _fx_utility_32_unsigned_read(UCHAR *source_ptr); +VOID _fx_utility_32_unsigned_write(UCHAR *dest_ptr, ULONG value); +ULONG64 _fx_utility_64_unsigned_read(UCHAR *source_ptr); +VOID _fx_utility_64_unsigned_write(UCHAR *dest_ptr, ULONG64 value); +VOID _fx_utility_memory_copy(UCHAR *source_ptr, UCHAR *dest_ptr, ULONG size); +VOID _fx_utility_memory_set(UCHAR *dest_ptr, UCHAR value, ULONG size); +FX_CACHED_SECTOR + *_fx_utility_logical_sector_cache_entry_read(FX_MEDIA *media_ptr, ULONG64 logical_sector, FX_CACHED_SECTOR **previous_cache_entry); +UINT _fx_utility_logical_sector_read(FX_MEDIA *media_ptr, ULONG64 logical_sector, + VOID *buffer_ptr, ULONG sectors, UCHAR sector_type); +UINT _fx_utility_logical_sector_write(FX_MEDIA *media_ptr, ULONG64 logical_sector, + VOID *buffer_ptr, ULONG sectors, UCHAR sector_type); +UINT _fx_utility_logical_sector_flush(FX_MEDIA *media_ptr, ULONG64 starting_sector, ULONG64 sectors, UINT invalidate); +UINT _fx_utility_FAT_entry_read(FX_MEDIA *media_ptr, ULONG cluster, ULONG *entry_ptr); +UINT _fx_utility_FAT_entry_write(FX_MEDIA *media_ptr, ULONG cluster, ULONG next_cluster); +UINT _fx_utility_FAT_flush(FX_MEDIA *media_ptr); +UINT _fx_utility_FAT_map_flush(FX_MEDIA *media_ptr); +ULONG _fx_utility_FAT_sector_get(FX_MEDIA *media_ptr, ULONG cluster); +UINT _fx_utility_string_length_get(CHAR *string, UINT max_length); + + +#ifdef FX_ENABLE_EXFAT + +/* Define the exFAT Utility function prototypes. */ + +UINT _fx_utility_exFAT_cluster_free(FX_MEDIA *media_ptr, UCHAR *work_ptr); +UINT _fx_utility_exFAT_geometry_check(FX_MEDIA *media_ptr, UCHAR *sector_buffer); +UINT _fx_utility_exFAT_system_area_checksum_verify(FX_MEDIA_PTR media_ptr, + UCHAR *sector_buffer, ULONG boot_sector_offset, + ULONG *calculated_checksum); +VOID _fx_utility_exFAT_size_calculate(UINT bytes_per_sector, ULONG boundary_unit, ULONG64 size_in_sectors, ULONG sectors_per_cluster, + ULONG *sectors_per_fat_ptr, ULONG *fat_offset_ptr, ULONG *cluster_heap_offset_ptr); +UINT _fx_utility_exFAT_system_area_format(FX_MEDIA *media_ptr, ULONG boundary_unit, + ULONG *system_area_checksum_ptr, UCHAR *memory_ptr, UINT memory_size); +UINT _fx_utility_exFAT_system_sector_write(FX_MEDIA *media_ptr, UCHAR *data_buffer, ULONG64 logical_sector, + ULONG sector_count, ULONG sector_type); +UINT _fx_utility_exFAT_system_area_checksum_write(FX_MEDIA *media_ptr, UCHAR *sector_buffer, + ULONG *system_area_checksum_ptr); + + +/* Define the exFAT utility function prototypes. */ + +UINT _fx_utility_exFAT_bitmap_start_sector_get(FX_MEDIA *media_ptr, ULONG *start_sector); +UINT _fx_utility_exFAT_bitmap_cache_update(FX_MEDIA *media_ptr, ULONG cluster); +UINT _fx_utility_exFAT_bitmap_flush(FX_MEDIA *media_ptr); +UINT _fx_utility_exFAT_bitmap_initialize(FX_MEDIA *media_ptr); +UINT _fx_utility_exFAT_bitmap_cache_prepare(FX_MEDIA *media_ptr, ULONG cluster); +UINT _fx_utility_exFAT_cluster_state_get(FX_MEDIA *media_ptr, ULONG cluster, UCHAR *cluster_state); +UINT _fx_utility_exFAT_cluster_state_set(FX_MEDIA *media_ptr, ULONG cluster, UCHAR new_cluster_state); +UINT _fx_utility_exFAT_bitmap_free_cluster_find(FX_MEDIA *media_ptr, ULONG start, ULONG *free_cluster); +USHORT _fx_utility_exFAT_upcase_get(USHORT character); +USHORT _fx_utility_exFAT_name_hash_get(CHAR *name); +USHORT _fx_utility_exFAT_unicode_name_hash_get(CHAR *unicode_name, ULONG unicode_length); +USHORT _fx_utility_exFAT_upcase_get(USHORT character); +UINT _fx_utility_absolute_path_get(CHAR *base_path, CHAR *new_path, CHAR *absolute_path); +UINT _fx_utility_token_length_get(CHAR *path); +UINT _fx_utility_exFAT_allocate_new_cluster(FX_MEDIA *media_ptr, FX_DIR_ENTRY *directory_ptr, ULONG *last_cluster, ULONG *cluster); + + +#endif /* FX_ENABLE_EXFAT */ + + +#endif + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_attributes_read.c b/src/Middlewares/ST/filex/common/src/fx_directory_attributes_read.c new file mode 100644 index 00000000..a155f5ed --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_attributes_read.c @@ -0,0 +1,156 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_attributes_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified directory. If */ +/* found, the attribute read request is valid and the directory entry */ +/* will be read in order to pickup the directory's attributes. */ +/* Otherwise, if the directory is not found, the appropriate error */ +/* code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name pointer */ +/* attributes_ptr Return attributes pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_attributes_read(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes_ptr) +{ + +UINT status; +FX_DIR_ENTRY dir_entry; + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_attributes_reads++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_ATTRIBUTES_READ, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, directory_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check to make sure the found entry is a file. */ + if ((dir_entry.fx_dir_entry_attributes & (UCHAR)(FX_DIRECTORY)) == 0) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_NOT_DIRECTORY); + } + + /* Place the current attributes into the destination. */ + *attributes_ptr = (UINT)dir_entry.fx_dir_entry_attributes; + + /* Update the trace event with the attributes read. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_DIRECTORY_ATTRIBUTES_READ, 0, 0, dir_entry.fx_dir_entry_attributes, 0) + + /* Release media protection. */ + FX_UNPROTECT + + /* File attribute read is complete, return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_attributes_set.c b/src/Middlewares/ST/filex/common/src/fx_directory_attributes_set.c new file mode 100644 index 00000000..e69bb52e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_attributes_set.c @@ -0,0 +1,205 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_attributes_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified directory. If */ +/* found, the attribute set request is valid and the directory will */ +/* be modified with the new attributes. Otherwise, if the directory */ +/* is not found, the appropriate error code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name pointer */ +/* attributes New dir attributes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the new directory entry */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_attributes_set(FX_MEDIA *media_ptr, CHAR *directory_name, UINT attributes) +{ + +UINT status; +FX_DIR_ENTRY dir_entry; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_attributes_sets++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_ATTRIBUTES_SET, media_ptr, directory_name, attributes, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, directory_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check to make sure the found entry is a directory. */ + if ((dir_entry.fx_dir_entry_attributes & (UCHAR)(FX_DIRECTORY)) == 0) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_NOT_DIRECTORY); + } + + /* Place the new attributes in the directory entry. Make sure that the + directory bit of the attributes is never changed. */ + dir_entry.fx_dir_entry_attributes = (UCHAR)(attributes | FX_DIRECTORY); + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Now write out the directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &dir_entry, UPDATE_FILE); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + status = _fx_directory_entry_write(media_ptr, &dir_entry); + +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. If the return status is not FX_SUCCESS, finish + the fault tolerant transaction without flushing the logs. */ + if (status != FX_SUCCESS) + { + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + } + else + { + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); + } + +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* File attribute set is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_create.c b/src/Middlewares/ST/filex/common/src/fx_directory_create.c new file mode 100644 index 00000000..088616f7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_create.c @@ -0,0 +1,904 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified directory. */ +/* If found, the create request is invalid and an error is returned */ +/* to the caller. After the file name verification is made, a search */ +/* for a free directory entry will be made. If nothing is available, */ +/* an error will be returned to the caller. Otherwise, if all is */ +/* okay, an empty directory will be created. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the new directory entry */ +/* _fx_directory_name_extract Pickup next part of name */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_directory_free_search Search for a free directory */ +/* entry */ +/* _fx_utility_exFAT_bitmap_free_cluster_find */ +/* Find exFAT free cluster */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_logical_sector_flush Flush the written log sector */ +/* _fx_utility_logical_sector_read Read logical sector */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_create(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; +ULONG FAT_index; +ULONG FAT_value; +UINT sectors; +ULONG total_clusters; +CHAR *work_ptr; +ULONG64 logical_sector; +ULONG i; +FX_DIR_ENTRY dir_entry; +FX_DIR_ENTRY sub_dir_entry; +FX_DIR_ENTRY search_directory; + +#ifdef FX_ENABLE_EXFAT +ULONG64 dir_size; +#endif /* FX_ENABLE_EXFAT */ +FX_INT_SAVE_AREA + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_creates++; +#endif + + /* Determine if the supplied name is less than the maximum supported name size. The + maximum name (FX_MAX_LONG_NAME_LEN) is defined in fx_api.h. */ + i = 0; + work_ptr = (CHAR *)directory_name; + while (*work_ptr && (i < FX_MAX_LONG_NAME_LEN)) + { + + /* Determine if the character designates a new path. */ + if ((*work_ptr == '\\') || (*work_ptr == '/')) + { + /* Yes, reset the name size. */ + i = 0; + } + /* Check for leading spaces. */ + else if ((*work_ptr != ' ') || (i != 0)) + { + + /* No leading spaces, increment the name size. */ + i++; + } + + /* Move to the next character. */ + work_ptr++; + } + + /* Determine if the supplied name is valid. */ + if ((i == 0) || (i >= FX_MAX_LONG_NAME_LEN)) + { + + /* Return an invalid name value. */ + return(FX_INVALID_NAME); + } + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Setup search directory pointer to another media name buffer. */ + search_directory.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN * 2; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Clear the search short name string. */ + search_directory.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_CREATE, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Make sure there is at least one cluster remaining for the new file. */ + if (!media_ptr -> fx_media_available_clusters) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return a no-space error. */ + return(FX_NO_MORE_SPACE); + } + + /* Search the system for the supplied directory name. */ + status = _fx_directory_search(media_ptr, directory_name, &dir_entry, &search_directory, &work_ptr); + + /* Determine if the search was successful. */ + if (status == FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Directory found - Return the error code. */ + return(FX_ALREADY_CREATED); + } + + /* Determine if there is anything left after the name. */ + if (_fx_directory_name_extract(work_ptr, &dir_entry.fx_dir_entry_name[0])) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Extra information after the file name, return an invalid name + error. */ + return(FX_INVALID_PATH); + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + if (((dir_entry.fx_dir_entry_name[0] == '.') && (dir_entry.fx_dir_entry_name[1] == 0)) || + ((dir_entry.fx_dir_entry_name[0] == '.') && (dir_entry.fx_dir_entry_name[1] == '.') && (dir_entry.fx_dir_entry_name[2] == 0))) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* We don't need '.' or '..' dirs for exFAT. */ + return(FX_ALREADY_CREATED); + } + } + + /* Save the directory entry size. */ + dir_size = search_directory.fx_dir_entry_file_size; +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Find a free slot for the new directory. */ + status = _fx_directory_free_search(media_ptr, &search_directory, &dir_entry); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Now allocate a cluster for our new sub-directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Find free cluster from exFAT media. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, + media_ptr -> fx_media_cluster_search_start, + &FAT_index); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + FAT_index = media_ptr -> fx_media_cluster_search_start; + total_clusters = media_ptr -> fx_media_total_clusters; + + /* Loop to find the first available cluster. */ + do + { + + /* Make sure we don't go past the FAT table. */ + if (!total_clusters) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Something is wrong with the media - the desired clusters were + not found in the FAT table. */ + return(FX_NO_MORE_SPACE); + } + + /* Read FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, FAT_index, &FAT_value); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* Decrement the total cluster count. */ + total_clusters--; + + /* Determine if the FAT entry is free. */ + if (FAT_value == FX_FREE_CLUSTER) + { + + /* Move cluster search pointer forward. */ + media_ptr -> fx_media_cluster_search_start = FAT_index + 1; + + /* Determine if this needs to be wrapped. */ + if (media_ptr -> fx_media_cluster_search_start >= (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Wrap the search to the beginning FAT entry. */ + media_ptr -> fx_media_cluster_search_start = FX_FAT_ENTRY_START; + } + + /* Break this loop. */ + break; + } + else + { + + /* FAT entry is not free... Advance the FAT index. */ + FAT_index++; + + /* Determine if we need to wrap the FAT index around. */ + if (FAT_index >= (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Wrap the search to the beginning FAT entry. */ + FAT_index = FX_FAT_ENTRY_START; + } + } + } while (FX_TRUE); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Decrease the number of available clusters for the media. */ + media_ptr -> fx_media_available_clusters--; + + /* Defer the writing of the FAT entry until the directory's first sector + has been properly written. If a power loss occurs prior to writing + the FAT entry, it will not result in a lost cluster. */ + + /* Populate the directory entry. */ + + /* Isolate the file name. */ + _fx_directory_name_extract(work_ptr, &dir_entry.fx_dir_entry_name[0]); + + /* Lockout interrupts for time/date access. */ + FX_DISABLE_INTS + + /* Set time and date stamps. */ + dir_entry.fx_dir_entry_time = _fx_system_time; + dir_entry.fx_dir_entry_date = _fx_system_date; + + /* Restore interrupts. */ + FX_RESTORE_INTS + + /* Set the attributes for the file. */ + dir_entry.fx_dir_entry_attributes = FX_DIRECTORY; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + dir_entry.fx_dir_entry_file_size = + media_ptr -> fx_media_sectors_per_cluster * media_ptr -> fx_media_bytes_per_sector; + dir_entry.fx_dir_entry_available_file_size = dir_entry.fx_dir_entry_file_size; + + /* Don't use FAT by default. */ + dir_entry.fx_dir_entry_dont_use_fat = (CHAR)((INT)((search_directory.fx_dir_entry_dont_use_fat & 1) << 1) | 1); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Set file size to 0. */ + dir_entry.fx_dir_entry_file_size = 0; + +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Set the cluster to EOF. */ + dir_entry.fx_dir_entry_cluster = FAT_index; + + /* Is there a leading dot? */ + if (dir_entry.fx_dir_entry_name[0] == '.') + { + + /* Yes, toggle the hidden attribute bit. */ + dir_entry.fx_dir_entry_attributes |= FX_HIDDEN; + } + + /* In previous versions, the new directory was written here. It + is now at the bottom of the file - after the FAT and the initial + sub-directory is written out. This makes the directory create + more fault tolerant. */ + + /* Calculate the first sector of the sub-directory file. */ + logical_sector = ((ULONG) media_ptr -> fx_media_data_sector_start) + + (((ULONG64) FAT_index - FX_FAT_ENTRY_START) * + ((ULONG) media_ptr -> fx_media_sectors_per_cluster)); + + /* Pickup the number of sectors for the initial sub-directory cluster. */ + sectors = media_ptr -> fx_media_sectors_per_cluster; + + /* Read the first logical sector associated with the allocated + cluster. */ + status = _fx_utility_logical_sector_read(media_ptr, logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error code. */ + return(status); + } + + /* Clear the entire first sector of the new sub-directory cluster. */ + work_ptr = (CHAR *)media_ptr -> fx_media_memory_buffer; + i = 0; + while (i < media_ptr -> fx_media_bytes_per_sector) + { + + /* Clear 4 bytes. */ + *((ULONG *)work_ptr) = (ULONG)0; + + /* Increment pointer. */ + work_ptr = work_ptr + sizeof(ULONG); + + /* Increment counter. */ + i = i + (ULONG)sizeof(ULONG); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled == FX_TRUE) + { + + /* Write back. */ + status = _fx_utility_logical_sector_write(media_ptr, logical_sector, + media_ptr -> fx_media_memory_buffer, (ULONG)1, FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error code. */ + return(status); + } + + /* Force flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, logical_sector, sectors, FX_TRUE); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if there are more sectors to clear in the first cluster of the new + sub-directory. */ + if (sectors > 1) + { + + /* Yes, invalidate all cached sectors that are contained in the newly allocated first + cluster of the directory. */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled == FX_FALSE) +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + + /* Flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, logical_sector + 1, ((ULONG64)(sectors - 1)), FX_TRUE); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + } + + /* Clear all additional sectors of new sub-directory. */ + sectors--; + while (sectors) + { + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build Write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = logical_sector + ((ULONG)sectors); +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector + ((ULONG)sectors); +#endif + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + + /* Set the system write flag since we are writing a directory sector. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, ((ULONG)logical_sector) + ((ULONG)sectors), 1, media_ptr -> fx_media_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if an error occurred. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error code. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Decrease the number of sectors to clear. */ + sectors--; + } + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Build Write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + + /* Set the system write flag since we are writing a directory sector. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, ((ULONG)logical_sector) + ((ULONG)sectors), 1, media_ptr -> fx_media_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if an error occurred. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error code. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Mark the cluster as used. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, FAT_index, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* Move cluster search pointer forward. */ + media_ptr -> fx_media_cluster_search_start = FAT_index + 1; + + /* Determine if this needs to be wrapped. */ + if (media_ptr -> fx_media_cluster_search_start >= media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) + { + + /* Wrap the search to the beginning FAT entry. */ + media_ptr -> fx_media_cluster_search_start = FX_FAT_ENTRY_START; + } + + if (search_directory.fx_dir_entry_name[0]) + { + + /* Not root directory. */ + /* Copy the date and time from the actual sub-directory. */ + search_directory.fx_dir_entry_time = dir_entry.fx_dir_entry_time; + search_directory.fx_dir_entry_date = dir_entry.fx_dir_entry_date; + + /* Check if the directory size has changed. */ + if (search_directory.fx_dir_entry_file_size == dir_size) + { + + /* Not changed, we need only update time stamps. */ + status = _fx_directory_exFAT_entry_write(media_ptr, &search_directory, UPDATE_FILE); + } + else + { + + /* Directory size changed, update time stamps and the stream size. */ + status = _fx_directory_exFAT_entry_write(media_ptr, &search_directory, UPDATE_STREAM); + } + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Now setup the first sector with the initial sub-directory information. */ + + /* Copy the base directory entry to the sub-directory entry. */ + sub_dir_entry = dir_entry; + + /* Setup pointer to media name buffer. */ + sub_dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + (FX_MAX_LONG_NAME_LEN * 3); + + /* Set the directory entry name to all blanks. */ + work_ptr = &sub_dir_entry.fx_dir_entry_name[0]; + for (i = 0; i < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); i++) + { + *work_ptr++ = ' '; + } + + sub_dir_entry.fx_dir_entry_long_name_present = 0; + + /* Now build the "." directory entry. */ + sub_dir_entry.fx_dir_entry_name[0] = '.'; + sub_dir_entry.fx_dir_entry_name[1] = 0; + sub_dir_entry.fx_dir_entry_log_sector = logical_sector; + sub_dir_entry.fx_dir_entry_byte_offset = 0; + + /* Write the directory's first entry. */ + status = _fx_directory_entry_write(media_ptr, &sub_dir_entry); + + /* Check for error condition. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error status. */ + return(status); + } + + /* Now build the ".." directory entry. */ + + /* Determine if the search directory is the root. */ + if (search_directory.fx_dir_entry_name[0]) + { + + /* Previous directory is not the root directory. */ + + /* Copy into the working directory entry. */ + sub_dir_entry = search_directory; + + /* Copy the date and time from the actual sub-directory. */ + sub_dir_entry.fx_dir_entry_time = dir_entry.fx_dir_entry_time; + sub_dir_entry.fx_dir_entry_date = dir_entry.fx_dir_entry_date; + + /* Adjust pointer to media name buffer. */ + sub_dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + (FX_MAX_LONG_NAME_LEN * 3); + + /* Change the name to ".." */ + work_ptr = &sub_dir_entry.fx_dir_entry_name[0]; + for (i = 0; i < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); i++) + { + *work_ptr++ = ' '; + } + + sub_dir_entry.fx_dir_entry_name[0] = '.'; + sub_dir_entry.fx_dir_entry_name[1] = '.'; + sub_dir_entry.fx_dir_entry_name[2] = 0; + + sub_dir_entry.fx_dir_entry_long_name_present = 0; + + /* Set file size to 0. */ + sub_dir_entry.fx_dir_entry_file_size = 0; + + /* Change the logical sector for this entry. */ + sub_dir_entry.fx_dir_entry_log_sector = logical_sector; + } + else + { + + /* Just modify the current directory since the parent + directory is the root. */ + sub_dir_entry.fx_dir_entry_name[1] = '.'; + sub_dir_entry.fx_dir_entry_name[2] = 0; + + /* Clear the cluster to indicate the root directory. */ + sub_dir_entry.fx_dir_entry_cluster = 0; + } + + /* Setup the byte offset. */ + sub_dir_entry.fx_dir_entry_byte_offset = FX_DIR_ENTRY_SIZE; + + /* Write the directory's second entry. */ + status = _fx_directory_entry_write(media_ptr, &sub_dir_entry); + + /* Check for error condition. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error status. */ + return(status); + } + + /* Write an EOF in the found FAT entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_index, media_ptr -> fx_media_fat_last); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + + /* Now write out the new directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write(media_ptr, &dir_entry, UPDATE_FULL); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + status = _fx_directory_entry_write(media_ptr, &dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Directory create is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_default_get.c b/src/Middlewares/ST/filex/common/src/fx_directory_default_get.c new file mode 100644 index 00000000..7973842b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_default_get.c @@ -0,0 +1,106 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_default_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the pointer of the last path provided to the */ +/* fx_directory_default_set function. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* return_path_name Destination string pointer */ +/* address */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_default_get(FX_MEDIA *media_ptr, CHAR **return_path_name) +{ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_default_gets++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_DEFAULT_GET, media_ptr, return_path_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Return the last pointer supplied to the set default directory function. */ + *return_path_name = media_ptr -> fx_media_default_path.fx_path_string; + + /* Release media protection. */ + FX_UNPROTECT + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c b/src/Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c new file mode 100644 index 00000000..46c3eff4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_default_get_copy.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" +#include "fx_utility.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_default_get_copy PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function copies the last path provided to the */ +/* fx_directory_default_set function into the specified buffer. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* return_path_name_buffer Destination buffer for name */ +/* return_path_name_buffer_size Size of buffer pointed to by */ +/* return_path_name_buffer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* 04-02-2021 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_default_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size) +{ + +UINT status; +CHAR *return_path_name; +UINT path_name_length_with_null_terminator; + + + /* Get the pointer to the path. */ + status = _fx_directory_default_get(media_ptr, &return_path_name); + if (status == FX_SUCCESS) + { + + /* Get the length of the path. */ + path_name_length_with_null_terminator = _fx_utility_string_length_get(return_path_name, FX_MAXIMUM_PATH) + 1; + + /* Can it fit in the user's buffer? */ + if (path_name_length_with_null_terminator <= return_path_name_buffer_size) + { + + /* Copy the path name into the user's buffer. */ + _fx_utility_memory_copy((UCHAR *) return_path_name, (UCHAR *) return_path_name_buffer, path_name_length_with_null_terminator); /* Use case of memcpy is verified. */ + } + else + { + + /* Buffer is too small. Return error. */ + return(FX_BUFFER_ERROR); + } + + } + + /* Return successful status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_default_set.c b/src/Middlewares/ST/filex/common/src/fx_directory_default_set.c new file mode 100644 index 00000000..aee0d433 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_default_set.c @@ -0,0 +1,453 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_default_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the default directory of the media to the path */ +/* specified by the caller. If this path is not found, an error code */ +/* is returned. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* new_path_name New path to set current */ +/* working directory to */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the directory name */ +/* in the directory structure */ +/* _fx_utility_absolute_path_get Get absolute path */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_default_set(FX_MEDIA *media_ptr, CHAR *new_path_name) +{ + +UINT status; +FX_DIR_ENTRY dir_entry; +CHAR *path_string_ptr; +UINT path_string_capacity; +FX_PATH *path_ptr; +UINT i; + +#ifdef FX_ENABLE_EXFAT +CHAR abs_str[FX_MAXIMUM_PATH]; /* TODO: possible will be better to use dynamic memory for exFAT only. */ +#endif /* FX_ENABLE_EXFAT */ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_default_sets++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Clear the long name string. */ + dir_entry.fx_dir_entry_name[0] = (CHAR)0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_DEFAULT_SET, media_ptr, new_path_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Setup the path string pointer to the start of the current path. */ + path_string_ptr = &(media_ptr -> fx_media_default_path.fx_path_string[0]); + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Get the absolute path. */ + if (_fx_utility_absolute_path_get(path_string_ptr, new_path_name, abs_str) == FX_SUCCESS) + { + + new_path_name = &(abs_str[0]); + } + else + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid Path - Return the error code. */ + return(FX_INVALID_PATH); + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* Look for a root directory selection. */ + if ((!new_path_name) || (((new_path_name[0] == '\\') || (new_path_name[0] == '/')) && (new_path_name[1] == (CHAR)0))) + { + + /* Set the media current working directory to the root. */ + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name[0] = (CHAR) 0; + media_ptr -> fx_media_default_path.fx_path_string[0] = (CHAR) 0; + media_ptr -> fx_media_default_path.fx_path_string[FX_MAXIMUM_PATH - 2] = (CHAR) 0; + } + else + { + + /* Search the system for the supplied path and directory name. */ + status = _fx_directory_search(media_ptr, new_path_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search failed or if the entry found is not a + directory. */ + if ((status != FX_SUCCESS) || (!(dir_entry.fx_dir_entry_attributes & FX_DIRECTORY))) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid Path - Return the error code. */ + return(FX_INVALID_PATH); + } + + /* Now update the current path string. */ + + /* Setup the path string's capacity. */ + path_string_capacity = FX_MAXIMUM_PATH - 1; + + /* Determine if the new path is relative from the current path. */ + if ((new_path_name[0] != '\\') && (new_path_name[0] != '/')) + { + + /* Yes, a relative path was found. */ + + /* First check for a local path pointer stored in the thread control block. + This is only available in ThreadX Version 4 and above. */ +#ifndef FX_NO_LOCAL_PATH + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + CHAR *saved_name_ptr; + + /* First, save the name pointer of the default path. */ + saved_name_ptr = media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name; + + /* Setup the default path pointer to the local path. */ + path_ptr = (FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr; + + /* Copy the local path to the default path. */ + media_ptr -> fx_media_default_path = *path_ptr; + + /* Restore the name pointer of the default path. */ + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name = saved_name_ptr; + + /* Set the path pointer to the default pointer. */ + path_ptr = &media_ptr -> fx_media_default_path; + } + else + { + + /* Setup the default path to the global media path. */ + path_ptr = &media_ptr -> fx_media_default_path; + } +#else + + /* Setup the default path to the global media path. */ + path_ptr = &media_ptr -> fx_media_default_path; +#endif + + /* First, check the current path for string overflow. If this is set, + don't attempt to update the current path with relative information. + The path won't be valid again until a complete path is given. */ + if (path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] == '*') + { + + /* Yes, don't update the string, just finish the path set processing. */ + + /* Determine if we are at the root directory. */ + if (!dir_entry.fx_dir_entry_cluster) + { + /* Set the current directory back to the root directory. */ + path_ptr -> fx_path_directory.fx_dir_entry_name[0] = (CHAR) 0; + + /* Set name to NULL. */ + dir_entry.fx_dir_entry_name[0] = (CHAR) 0; + + /* Clear the current path string. */ + path_ptr -> fx_path_string[0] = (CHAR)0; + + /* Clear the overflow flag in the current path string... just in + case! */ + path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] = (CHAR)0; + } + + /* Copy the new directory entry into the media control block. */ + path_ptr -> fx_path_directory = dir_entry; + + /* Copy the name into the path name buffer. */ + for (i = 0; dir_entry.fx_dir_entry_name[i]; i++) + { + path_ptr -> fx_path_name_buffer[i] = dir_entry.fx_dir_entry_name[i]; + } + + /* Reassign the pointer. */ + path_ptr -> fx_path_directory.fx_dir_entry_name = path_ptr -> fx_path_name_buffer; + + /* Release media protection. */ + FX_UNPROTECT + + /* Default directory set is complete, return status. */ + return(FX_SUCCESS); + } + + /* Move the current path starting pointer to the end of the current + path string. */ + while ((path_string_capacity) && (*path_string_ptr != FX_NULL)) + { + path_string_ptr++; + path_string_capacity--; + } + + /* If room, place the \ character in the path string. */ + if (path_string_capacity) + { + + /* There is room, place the directory marker in the string. */ + *path_string_ptr++ = '\\'; + path_string_capacity--; + } + } + else + { + + /* Setup the default path pointer. */ + + /* First check for a local path pointer stored in the thread control block. + This is only available in ThreadX Version 4 and above. */ +#ifndef FX_NO_LOCAL_PATH + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + CHAR *saved_name_ptr; + + /* First, save the name pointer of the default path. */ + saved_name_ptr = media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name; + + /* Setup the default path pointer to the local path. */ + path_ptr = (FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr; + + /* Copy the local path to the default path. */ + media_ptr -> fx_media_default_path = *path_ptr; + + /* Restore the name pointer of the default path. */ + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name = saved_name_ptr; + + /* Set the path pointer to the default pointer. */ + path_ptr = &media_ptr -> fx_media_default_path; + } + else + { + + /* Setup the default path to the global media path. */ + path_ptr = &media_ptr -> fx_media_default_path; + } +#else + + /* Setup the default path to the global media path. */ + path_ptr = &media_ptr -> fx_media_default_path; +#endif + + /* Complete path name given. Check to see if we need to clear an + overflow character from a previous current path string update. */ + if (path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] == '*') + { + path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] = (CHAR)0; + } + } + + /* Copy what we can into the current path. */ + while (*new_path_name) + { + + /* Determine if there is a ".." character sequence that specifies the + previous path. */ + if ((*new_path_name == '.') && (*(new_path_name + 1) == '.')) + { + + /* Yes, a backward path is found. The current path pointer + must be moved back to just after the previous \ character. */ + + /* Skip the current \0 that is at the end of the current path. */ + path_string_capacity = path_string_capacity + 2; + path_string_ptr = path_string_ptr - 2; + + while (path_string_capacity <= (FX_MAXIMUM_PATH - 1)) + { + + /* Move the current path pointer backwards until + a \ character is found. */ + + if ((*path_string_ptr == '\\') || (*path_string_ptr == '/')) + { + + /* Yes, we have successfully backed up one directory. */ + break; + } + + /* Backup another character. */ + path_string_capacity++; + path_string_ptr--; + } + + /* Adjust the new directory pointer past the .. characters */ + new_path_name = new_path_name + 2; + } + else + { + + /* Normal characters that need to be copied into the current path. */ + + if (path_string_capacity) + { + + /* Copy character from the new path into the current path string. */ + *path_string_ptr++ = *new_path_name++; + + path_string_capacity--; + } + else + { + + /* No more room in the current path string! */ + break; + } + } + } + + /* Determine if there is still room in the current path string. */ + if (path_string_capacity) + { + + /* Yes, there is still room, place a NULL character at the + end of the path. */ + *path_string_ptr = (CHAR)FX_NULL; + } + else + { + + /* No more room. Determine if the entire path was successfully + copied into the current path. */ + if (*new_path_name) + { + + /* No, we couldn't fit the entire path. Place a "*" character + at the end to indicate that we had overflow. Note that + the path is kept just the the directory default get call, so + the new default path is valid. */ + path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] = '*'; + } + } + + /* Determine if we are at the root directory. */ +#ifdef FX_ENABLE_EXFAT + if ((!dir_entry.fx_dir_entry_cluster) && (media_ptr -> fx_media_FAT_type != FX_exFAT)) +#else + if (!dir_entry.fx_dir_entry_cluster) +#endif + { + + /* Set the current directory back to the root directory. */ + dir_entry.fx_dir_entry_name[0] = (CHAR)0; + path_ptr -> fx_path_name_buffer[0] = (CHAR)0; + } + + /* Copy the new directory entry into the media control block. */ + path_ptr -> fx_path_directory = dir_entry; + + /* Copy the name. */ + for (i = 0; dir_entry.fx_dir_entry_name[i]; i++) + { + path_ptr -> fx_path_name_buffer[i] = dir_entry.fx_dir_entry_name[i]; + } + + /* Reassign the pointer. */ + path_ptr -> fx_path_directory.fx_dir_entry_name = path_ptr -> fx_path_name_buffer; + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Default directory set is complete, return status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_delete.c b/src/Middlewares/ST/filex/common/src/fx_directory_delete.c new file mode 100644 index 00000000..61a9bda8 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_delete.c @@ -0,0 +1,589 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified directory. */ +/* If found, the directory is examined to make sure it is empty. If */ +/* the directory is not empty, an error code is returned to the */ +/* caller. Otherwise, the directory will be deleted and its clusters */ +/* will be made available. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name to delete */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_read Read a directory entry */ +/* _fx_directory_entry_write Write the new directory entry */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_utility_logical_sector_flush Flush the written log sector */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state */ +/* _fx_utility_FAT_entry_read Read FAT entries to calculate */ +/* the sub-directory size */ +/* _fx_utility_FAT_entry_write Write FAT entry */ +/* _fx_utility_FAT_flush Flush FAT cache */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_delete(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; +ULONG cluster, next_cluster; +ULONG i, directory_size; +FX_DIR_ENTRY dir_entry; +FX_DIR_ENTRY search_directory; +FX_DIR_ENTRY search_entry; + +#ifdef FX_ENABLE_EXFAT +ULONG clusters_count; +ULONG bytes_per_cluster; +#endif /* FX_ENABLE_EXFAT */ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_deletes++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Setup search pointer to media name buffer. */ + search_directory.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN * 2; + + /* Setup search entry pointer to media name buffer. */ + search_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN * 3; + + /* Clear the short name string of the three file names that will be worked with. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + search_directory.fx_dir_entry_short_name[0] = 0; + search_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_DELETE, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Search the system for the supplied directory name. */ + status = _fx_directory_search(media_ptr, directory_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check to make sure the found entry is a directory. */ + if (!(dir_entry.fx_dir_entry_attributes & (UCHAR)(FX_DIRECTORY))) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a directory error code. */ + return(FX_NOT_DIRECTORY); + } + + /* Check if the entry is read only */ + if (dir_entry.fx_dir_entry_attributes & (UCHAR)(FX_READ_ONLY)) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a directory error code. */ + return(FX_WRITE_PROTECT); + } + + /* Copy the directory entry to the search directory structure for + looking at the specified sub-directory contents. */ + search_directory = dir_entry; + + /* Ensure that the search directory's last search cluster is cleared. */ + search_directory.fx_dir_entry_last_search_cluster = 0; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + directory_size = (ULONG)search_directory.fx_dir_entry_file_size / FX_DIR_ENTRY_SIZE; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Calculate the directory size by counting the allocated + clusters for it. */ + i = 0; + cluster = search_directory.fx_dir_entry_cluster; + while (cluster < media_ptr -> fx_media_fat_reserved) + { + + /* Increment the cluster count. */ + i++; + + /* Read the next FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + if ((cluster < FX_FAT_ENTRY_START) || (cluster == next_cluster) || (i > media_ptr -> fx_media_total_clusters)) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + cluster = next_cluster; + } + + /* Now we can calculate the directory size. */ + directory_size = (((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster) * i) / + (ULONG)FX_DIR_ENTRY_SIZE; + + /* Also save this in the directory entry so we don't have to + calculate it later. */ + search_directory.fx_dir_entry_file_size = directory_size; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Make sure the new name is not in the current directory. */ +#ifdef FX_ENABLE_EXFAT + if (directory_size > 0) + { + + /* exFAT directories do not record '.' and '..' directories. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + i = 0; + } + else + { + i = 2; + } +#else + /* The first two entries are skipped because they are just part of the sub-directory. */ + i = 2; +#endif /* FX_ENABLE_EXFAT */ + + do + { + + /* Read an entry from the directory. */ + status = _fx_directory_entry_read(media_ptr, &search_directory, &i, &search_entry); + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error condition. */ + return(status); + } + + /* Determine if this is the last directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (search_entry.fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER) +#else + if (search_entry.fx_dir_entry_name[0] == FX_DIR_ENTRY_DONE) +#endif /* FX_ENABLE_EXFAT */ + { + break; + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Skip '.' and '..' folders if exists. */ + if ((i == 1) && (search_entry.fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY) && + (search_entry.fx_dir_entry_name[0] == '.') && + (search_entry.fx_dir_entry_name[1] == 0)) + { + + continue; + } + if ((i == 2) && (search_entry.fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY) && + (search_entry.fx_dir_entry_name[0] == '.') && (search_entry.fx_dir_entry_name[1] == '.') && + (search_entry.fx_dir_entry_name[2] == 0)) + { + + continue; + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if this is an empty entry. */ +#ifdef FX_ENABLE_EXFAT + if (search_entry.fx_dir_entry_type != FX_EXFAT_DIR_ENTRY_TYPE_FREE) +#else + if ((UCHAR)search_entry.fx_dir_entry_name[0] != (UCHAR)FX_DIR_ENTRY_FREE) +#endif /* FX_ENABLE_EXFAT */ + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error status. */ + return(FX_DIR_NOT_EMPTY); + } + + i++; + } while (i < directory_size); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* At this point, we are going to delete the empty directory. */ + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Invalidate the directory search saved information. */ + media_ptr -> fx_media_last_found_name[0] = FX_NULL; +#endif + + /* Mark the sub-directory entry as available. */ + dir_entry.fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + dir_entry.fx_dir_entry_short_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + + /* Now write out the directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &dir_entry, UPDATE_DELETE); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + i = 0; + + clusters_count = (ULONG)((search_directory.fx_dir_entry_file_size + bytes_per_cluster - 1) / bytes_per_cluster - 1); +#endif /* FX_ENABLE_EXFAT */ + + /* Walk through the directory's clusters and release them. */ + cluster = search_directory.fx_dir_entry_cluster; + + while (cluster < media_ptr -> fx_media_fat_reserved) + { + + /* Increment the cluster count. */ + i++; + +#ifdef FX_ENABLE_EXFAT + + /* Read the next FAT entry. */ + if (search_directory.fx_dir_entry_dont_use_fat & 1) + { + + /* Check for file size range */ + if (i - 1 >= clusters_count) + { + next_cluster = FX_LAST_CLUSTER_exFAT; + } + else + { + next_cluster = cluster + 1; + } + } + else + { + +#endif /* FX_ENABLE_EXFAT */ + + /* Read the next FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + if ((cluster < FX_FAT_ENTRY_START) || (cluster == next_cluster) || (i > media_ptr -> fx_media_total_clusters)) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + /* Release the current cluster. */ +#ifdef FX_ENABLE_EXFAT + if (!(search_directory.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + + status = _fx_utility_FAT_entry_write(media_ptr, cluster, FX_FREE_CLUSTER); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as free. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, cluster, FX_EXFAT_BITMAP_CLUSTER_FREE); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* Increment the number of available clusters for the media. */ + media_ptr -> fx_media_available_clusters++; + + /* Copy next cluster to current cluster. */ + cluster = next_cluster; + } + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + + /* Flush the logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, ((ULONG64) 1), (ULONG64)(media_ptr -> fx_media_sectors_per_FAT), FX_FALSE); + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Directory delete is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_entry_read.c b/src/Middlewares/ST/filex/common/src/fx_directory_entry_read.c new file mode 100644 index 00000000..8ea0eab2 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_entry_read.c @@ -0,0 +1,786 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" + + + +#endif /* FX_ENABLE_EXFAT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_entry_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the supplied directory entry from the supplied */ +/* source directory. If the supplied directory entry is NULL, then */ +/* the root directory is assumed. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* source_dir Source directory entry */ +/* entry_ptr Directory entry number */ +/* destination_ptr Pointer to destination for */ +/* the directory entry */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* *entry_ptr should point to the 8:3 entry if it is a long name */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_exFAT_entry_read Read exFAT entries */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_logical_sector_read Read directory sector */ +/* _fx_utility_16_unsigned_read Read a UINT from memory */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +#ifdef FX_ENABLE_EXFAT +UINT _fx_directory_entry_read_FAT(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, + ULONG *entry_ptr, FX_DIR_ENTRY *destination_ptr) +#else +UINT _fx_directory_entry_read(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, + ULONG *entry_ptr, FX_DIR_ENTRY *destination_ptr) +#endif /* FX_ENABLE_EXFAT */ +{ + +UINT i, j, card, dotflag, get_short_name; +UINT number_of_lfns; +UINT status; +ULONG cluster, next_cluster = 0; +UINT relative_cluster; +UINT relative_sector; +ULONG logical_sector; +ULONG byte_offset; +ULONG bytes_per_cluster; +UCHAR *read_ptr; +CHAR *short_name_ptr; +ULONG entry = *entry_ptr; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of directory entry read requests. */ + media_ptr -> fx_media_directory_entry_reads++; +#endif + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_DIRECTORY_ENTRY_READ_EXTENSION + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_DIR_ENTRY_READ, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Calculate the byte offset of this directory entry. */ + byte_offset = entry * FX_DIR_ENTRY_SIZE; + + /* Determine if a sub-directory or FAT32 root directory is specified. */ +#ifdef FX_ENABLE_EXFAT + if ((source_dir) || (media_ptr -> fx_media_FAT_type == FX_FAT32)) +#else + if ((source_dir) || (media_ptr -> fx_media_32_bit_FAT)) +#endif + { + + /* Yes, a sub-directory is present. */ + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check for invalid value. */ + if (bytes_per_cluster == 0) + { + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Now determine the relative cluster in the sub-directory file. */ + relative_cluster = (UINT)(byte_offset / bytes_per_cluster); + + /* Calculate the byte offset within the cluster. */ + byte_offset = byte_offset % bytes_per_cluster; + + /* Now figure out the relative sector within the cluster. */ + relative_sector = (UINT)(byte_offset / ((ULONG)media_ptr -> fx_media_bytes_per_sector)); + + /* Read the directory sector into the internal memory buffer. */ + + /* Determine if there is a sub-directory. */ + if (source_dir) + { + + /* Determine if this source directory has valid information from the previous call. */ + if ((source_dir -> fx_dir_entry_last_search_cluster) && + (source_dir -> fx_dir_entry_last_search_relative_cluster <= relative_cluster) && + (source_dir -> fx_dir_entry_last_search_log_sector == source_dir -> fx_dir_entry_log_sector) && + (source_dir -> fx_dir_entry_last_search_byte_offset == source_dir -> fx_dir_entry_byte_offset)) + { + + /* Use the previous information to start the search. */ + cluster = source_dir -> fx_dir_entry_last_search_cluster; + + /* Setup the relative cluster index to the saved relative cluster. */ + i = source_dir -> fx_dir_entry_last_search_relative_cluster; + + /* Clear the search cluster. It will be updated prior to successful return. */ + source_dir -> fx_dir_entry_last_search_cluster = 0; + } + else + { + + /* Nothing from the previous directory read, just setup the starting cluster to the + beginning of the sub-directory. */ + cluster = source_dir -> fx_dir_entry_cluster; + + /* Setup the relative cluster index to zero. */ + i = 0; + } + } + else + { + + /* No, setup the starting cluster to the FAT32 root cluster. */ + cluster = media_ptr -> fx_media_root_cluster_32; + + /* Setup the relative cluster index to zero. */ + i = 0; + } + + /* Loop to position to the appropriate cluster. */ + while (i < relative_cluster) + { + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster >= media_ptr -> fx_media_fat_reserved)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Read the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* There is a potential for loop, but hardly anything can be done */ + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Setup the actual cluster. */ + cluster = next_cluster; + + /* Increment the relative cluster number. */ + i++; + } + + /* At this point, the directory data sector needs to be read. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + relative_sector; + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Calculate the byte offset within this sector. */ + byte_offset = byte_offset % media_ptr -> fx_media_bytes_per_sector; + } + else + { + + /* Read the entry from the root directory. */ + + /* Determine which sector the requested root directory entry is in. */ + logical_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_root_sector_start; + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Set the cluster and relative variables (not used in this case) to avoid any compiler + warnings. */ + relative_cluster = relative_sector = cluster = 0; + + /* Now calculate the byte offset into this sector. */ + byte_offset = byte_offset - + ((logical_sector - (ULONG)media_ptr -> fx_media_root_sector_start) * + media_ptr -> fx_media_bytes_per_sector); + } + + /* Setup a pointer into the buffer. */ + read_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Save the logical sector and byte offset in the returned directory entry. */ + destination_ptr -> fx_dir_entry_log_sector = logical_sector; + destination_ptr -> fx_dir_entry_byte_offset = byte_offset; + + /* Clear the short file name information. */ + destination_ptr -> fx_dir_entry_long_name_shorted = 0; + destination_ptr -> fx_dir_entry_short_name[0] = 0; + + /* Setup short name pointer. */ + short_name_ptr = destination_ptr -> fx_dir_entry_name; + + /* Check if long file name exists. */ + get_short_name = 0; + if ((*(read_ptr + 11) == (UCHAR)FX_LONG_NAME) && (*read_ptr != (UCHAR)FX_DIR_ENTRY_FREE)) + { + + /* Collate the long name. */ + + /* Pickup the file name length. */ + i = (((UINT)(*read_ptr & (UCHAR)0x1f) - 1) * FX_LONG_NAME_ENTRY_LEN) & 0xFFFFFFFF; + + /* Save the number of LFN entries. */ + number_of_lfns = (UINT)(*read_ptr & (UCHAR)0x1f); + + /* Check the file name size. */ + if (i >= (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Name is too big, shorten it. */ + get_short_name = 1; + destination_ptr -> fx_dir_entry_long_name_shorted = (UINT)(*read_ptr & (UCHAR)0x1f); + } + else + { + + /* Size of name is fine, save pointer to short file name. */ + short_name_ptr = destination_ptr -> fx_dir_entry_short_name; + + /* Loop to make sure the long file name is NULL terminated. */ + j = i + FX_LONG_NAME_ENTRY_LEN + 1; + do + { + /* Place a NULL in the long name. */ + destination_ptr -> fx_dir_entry_name[i] = 0; + + /* Position to the next entry. */ + i++; + } while ((i < j) && (i < FX_MAX_LONG_NAME_LEN)); + } + + /* Loop to pickup the rest of the name. */ + do + { + + /* Get the lower 5 bit containing the cardinality. */ + card = (UINT)(*read_ptr & (UCHAR)0x1f) - 1; + + /* For simplicity no checksum or cardinality checking is done */ + if (get_short_name == 0) + { + + /* Loop to pickup name. */ + for (i = 1, j = 0; i < FX_DIR_ENTRY_SIZE; i += 2) + { + + if ((i == 11) || (i == 26)) + { + continue; + } + + /* i = 12, 27 is not generated due to +=2 */ + if (i == 13) + { + i = 12; + continue; /* this time next unicode is byte offset 14*/ + } + + /* Determine if there is an actual unicode character present. */ + if (read_ptr[i + 1]) + { + + /* Extended byte is non-zero, make sure both bytes of the unicode entry are not + all ones, since this is a normal case. */ + if ((read_ptr[i + 1] != (UCHAR)0xFF) || (read_ptr[i] != (UCHAR)0xFF)) + { + + /* Name is an actual unicode name, shorten it. */ + get_short_name = 1; + + /* Save the number of directory entries the LFN has. This will be + used later when updating the 8.3 portion of the LFN. */ + destination_ptr -> fx_dir_entry_long_name_shorted = number_of_lfns; + + /* Setup short name pointer. */ + short_name_ptr = destination_ptr -> fx_dir_entry_name; + } + } + + /* Determine if the character is NULL. */ + if ((read_ptr[i] == FX_NULL) || (read_ptr[i] == (UCHAR)0xFF)) + { + continue; + } + + /* Determine if the name is too big. */ + if ((card * 13 + j) >= (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Name is actually too big, shorten it. */ + get_short_name = 1; + + /* Save the number of directory entries the LFN has. This will be + used later when updating the 8.3 portion of the LFN. */ + destination_ptr -> fx_dir_entry_long_name_shorted = number_of_lfns; + + /* Also reposition the short name pointer. */ + short_name_ptr = destination_ptr -> fx_dir_entry_name; + + break; + } + + /* Each entry contains 13 unicode and first byte ASCII, second byte is extended. */ + destination_ptr -> fx_dir_entry_name[13 * card + j] = (CHAR)read_ptr[i]; + + j++; + } + } + + /* Determine if a new sector needs to be read. */ + if (byte_offset + FX_DIR_ENTRY_SIZE >= media_ptr -> fx_media_bytes_per_sector) + { + + /* Determine if a sub-directory or FAT32 root directory is specified. */ + if ((source_dir) || (media_ptr -> fx_media_32_bit_FAT)) + { + + /* Determine the next sector of the directory entry. */ + if (relative_sector < (media_ptr -> fx_media_sectors_per_cluster - 1)) + { + + /* More sectors in this cluster. */ + + /* Simply increment the logical sector. */ + logical_sector++; + + /* Increment the relative sector. */ + relative_sector++; + } + else + { + + /* We need to move to the next cluster. */ + + /* Pickup the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Copy next cluster to the current cluster. */ + cluster = next_cluster; + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster >= media_ptr -> fx_media_fat_reserved)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Now increment the relative cluster. */ + relative_cluster++; + + /* Setup the relative sector (this is zero for subsequent cluster. */ + relative_sector = 0; + + /* Calculate the next logical sector. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + } + } + else + { + + /* Non-FAT 32 root directory. */ + + /* Advance to the next sector. */ + logical_sector++; + + /* Determine if the logical sector is valid. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_root_sector_start + media_ptr -> fx_media_root_sectors)) + { + + /* Trying to read past root directory - send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + } + + /* Read the new sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Check I/O status. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Set the byte offset to 0 for new sector. */ + byte_offset = 0; + } + else + { + + /* Calculate the new byte offset. */ + byte_offset += FX_DIR_ENTRY_SIZE; + } + + /* Calculate the next read pointer. */ + read_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT) byte_offset; + + /* Move to the next entry. */ + entry++; + } while (card > 0); + + /* Set flag indicating long file name is present. */ + destination_ptr -> fx_dir_entry_long_name_present = 1; + } + else + { + /* No long file name is present. */ + get_short_name = 1; + } + + /* Determine if we need to clear the long name flag. */ + if (get_short_name == 1) + { + + /* Clear the long name flag. */ + destination_ptr -> fx_dir_entry_long_name_present = 0; + } + + /* Pickup the short file name. */ + short_name_ptr[0] = 0; + dotflag = 0; + for (i = 0, j = 0; i < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); i++) + { + + /* Check for a NULL. */ + if ((CHAR)read_ptr[i] == 0) + { + break; + } + + /* Check for a dot. This happens for the first two directory entries, no + extra dot is needed. */ + if ((CHAR)read_ptr[i] == '.') + { + dotflag = 2; + } + + /* Check for a space. */ + if ((CHAR)read_ptr[i] == ' ') + { + /* Put a dot if a character comes after space. */ + if (dotflag == 0) + { + dotflag = 1; + } + continue; + } + + /* Check for the main short file name size. */ + if (i == FX_DIR_NAME_SIZE) + { + /* Check to see if we need to insert a dot. */ + if (dotflag == 0) + { + dotflag = 1; + } + } + + /* Check to see if we need to add a dot. */ + if (dotflag == 1) + { + /* Add dot to short file name. */ + short_name_ptr[j++] = '.'; + dotflag = 2; /* no more dot for spaces */ + } + + /* Copy a character. */ + short_name_ptr[j] = (CHAR)read_ptr[i]; + + /* Increment size. */ + j++; + } + + /* Determine if a long file name is present and its associated short file + name is actually free. */ + if ((destination_ptr -> fx_dir_entry_long_name_present) && (((UCHAR)short_name_ptr[0]) == (UCHAR)FX_DIR_ENTRY_FREE)) + { + + /* Yes, the short file name is really free even though long file name entries directly precede it. + In this case, simply place the free directory marker at the front of the long file name. */ + destination_ptr -> fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + short_name_ptr[0] = (CHAR)0; + } + + /* Determine if the short name pointer is NULL while the read pointer is + non-NULL. */ + if ((short_name_ptr[0] == 0) && (read_ptr[0] == ' ')) + { + + /* This condition can occur with an all blank volume name. Simply + copy the volume name to the short name in this case. */ + for (j = 0; j < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); j++) + { + + /* Copy a byte of the volume name. */ + short_name_ptr[j] = (CHAR)read_ptr[j]; + } + } + + /* Set end of string to null. */ + short_name_ptr[j] = 0; + + /* Load up the destination directory entry. */ + read_ptr += (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); + + /* Copy the attribute into the destination. */ + destination_ptr -> fx_dir_entry_attributes = *read_ptr++; + + /* Pickup the reserved byte. */ + destination_ptr -> fx_dir_entry_reserved = *read_ptr++; + + /* Check for an undocumented NT file name feature for optimizing the storage + of all lower case file names that otherwise are valid 8.3 file names. The + following reserved bit definitions are present: + + BIT3 - set if 8.3 is all in lower case and no extended filename. + BIT4 - set for file, clear for directory entry if no extended filename. + + This is true for all NT systems. Prior to NT follows MSDOS FAT documentation and + is set to 0x00, all bits cleared. Therefore if BIT3 is set force lowercase. */ + if ((get_short_name) && (destination_ptr -> fx_dir_entry_reserved & 0x08)) + { + + /* Microsoft undocumented NT file name feature... convert short name to lower + case. */ + for (j = 0; j <= (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE) && (short_name_ptr[j] != 0x00); j++) + { + + /* Determine if an upper case character is present. */ + if ((short_name_ptr[j] >= 'A') && (short_name_ptr[j] <= 'Z')) + { + + /* Yes, an upper case character is present. Force it to lower case. */ + short_name_ptr[j] = (CHAR)(short_name_ptr[j] + 32); + } + } + } + + /* Pickup the created time in milliseconds. */ + destination_ptr -> fx_dir_entry_created_time_ms = *read_ptr++; + + /* Pickup the created time. */ + destination_ptr -> fx_dir_entry_created_time = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Pickup the created date. */ + destination_ptr -> fx_dir_entry_created_date = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Pickup the last accessed date. */ + destination_ptr -> fx_dir_entry_last_accessed_date = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* read the upper 2 bytes of starting cluster - required only for 32 bit FAT */ + if (media_ptr -> fx_media_32_bit_FAT) + { + + /* FAT32 only. */ + destination_ptr -> fx_dir_entry_cluster = _fx_utility_16_unsigned_read(read_ptr); + destination_ptr -> fx_dir_entry_cluster <<= 16; + } + else + { + /* Not required for non FAT32. */ + destination_ptr -> fx_dir_entry_cluster = 0; + } + + /* Advance the read pointer. */ + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Copy the time into the destination. */ + destination_ptr -> fx_dir_entry_time = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Copy the date into the destination. */ + destination_ptr -> fx_dir_entry_date = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Copy the starting cluster into the destination. */ + destination_ptr -> fx_dir_entry_cluster += _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Copy the file size into the destination. */ + destination_ptr -> fx_dir_entry_file_size = _fx_utility_32_unsigned_read(read_ptr); + + /* Clear the destination search specific fields. */ + destination_ptr -> fx_dir_entry_last_search_cluster = 0; + destination_ptr -> fx_dir_entry_last_search_relative_cluster = 0; + destination_ptr -> fx_dir_entry_last_search_log_sector = 0; + destination_ptr -> fx_dir_entry_last_search_byte_offset = 0; + + /* Remember the entry number. */ + destination_ptr -> fx_dir_entry_number = entry; + + /* Return entry number. */ + *entry_ptr = entry; + + /* Determine if we should remember the last cluster and relative cluster. */ + if (source_dir) + { + + /* Yes, remember the last cluster and relative cluster for a subsequent call + to read a directory entry. */ + source_dir -> fx_dir_entry_last_search_cluster = cluster; + source_dir -> fx_dir_entry_last_search_relative_cluster = relative_cluster; + + /* Also remember several other items that are unique to the directory... just to verify that the + search information can be used. */ + source_dir -> fx_dir_entry_last_search_log_sector = source_dir -> fx_dir_entry_log_sector; + source_dir -> fx_dir_entry_last_search_byte_offset = source_dir -> fx_dir_entry_byte_offset; + } +#ifdef FX_ENABLE_EXFAT + destination_ptr -> fx_dir_entry_dont_use_fat = 0; + + /* If a file whose first byte of long name is read, fx_dir_entry_short_name will not be empty. */ + /* If a free dir_entry is obtained, fx_dir_entry_short_name[0] will not be assigned as 0 around Line 623 in this file. */ + /* If there is only a free dir_entry without front long name dir_entries, fx_dir_entry_name[0] will be assigned by the loop around Line 568. */ + if (((UCHAR)destination_ptr -> fx_dir_entry_name[0] == FX_DIR_ENTRY_FREE) && ((UCHAR)destination_ptr -> fx_dir_entry_short_name[0] == 0)) + { + destination_ptr -> fx_dir_entry_type = FX_EXFAT_DIR_ENTRY_TYPE_FREE; + } + else if ((UCHAR)destination_ptr -> fx_dir_entry_name[0] == FX_DIR_ENTRY_DONE) + { + destination_ptr -> fx_dir_entry_type = FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER; + } + else + { + destination_ptr -> fx_dir_entry_type = FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Return success to the caller. */ + return(FX_SUCCESS); +} + + +#ifdef FX_ENABLE_EXFAT +UINT _fx_directory_entry_read_ex(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, + ULONG *entry_ptr, FX_DIR_ENTRY *destination_ptr, UINT hash) +{ +UINT status = FX_SUCCESS; + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = + _fx_directory_exFAT_entry_read( + media_ptr, source_dir, entry_ptr, destination_ptr, hash, FX_FALSE, NULL, NULL); + } + else + { + status = + _fx_directory_entry_read_FAT(media_ptr, source_dir, entry_ptr, destination_ptr); + } + + return(status); +} + + +UINT _fx_directory_entry_read(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, + ULONG *entry_ptr, FX_DIR_ENTRY *destination_ptr) +{ + + return(_fx_directory_entry_read_ex(media_ptr, source_dir, entry_ptr, destination_ptr, 0)); +} +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_entry_write.c b/src/Middlewares/ST/filex/common/src/fx_directory_entry_write.c new file mode 100644 index 00000000..79624701 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_entry_write.c @@ -0,0 +1,1152 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_entry_write PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes the supplied directory entry to the specified */ +/* logical sector and offset. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* entry_ptr Pointer to directory entry */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a new FAT entry */ +/* _fx_utility_logical_sector_read Read directory sector */ +/* _fx_utility_logical_sector_write Write directory sector */ +/* _fx_utility_16_unsigned_write Write a UINT from memory */ +/* _fx_utility_32_unsigned_write Write a ULONG from memory */ +/* _fx_fault_tolerant_add_dir_log Add directory redo log */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_entry_write(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr) +{ + +UCHAR *work_ptr, *sector_base_ptr; +UINT status, temp, entry, delete_flag; +UINT i, j, k, l, card, len, dotfound, dotpos, match; +UCHAR checksum, eof_marker; +CHAR alpha; +CHAR shortname[FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE + 1]; +ULONG logical_sector, relative_sector; +ULONG byte_offset; +ULONG cluster, next_cluster; + + +#ifdef FX_ENABLE_FAULT_TOLERANT +UCHAR *changed_ptr; +UINT changed_size; +ULONG changed_offset; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of directory entry write requests. */ + media_ptr -> fx_media_directory_entry_writes++; +#endif + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_DIRECTORY_ENTRY_WRITE_EXTENSION + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_DIR_ENTRY_WRITE, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Determine if this is entry is being deleted. */ + if (((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_FREE) && + ((UCHAR)entry_ptr -> fx_dir_entry_short_name[0] == (UCHAR)FX_DIR_ENTRY_FREE)) + { + + /* Yes, this is a request to delete the entry. Set the flag to remember this. */ + delete_flag = FX_TRUE; + + /* Null the short file name. */ + entry_ptr -> fx_dir_entry_short_name[0] = 0; + } + else + { + + /* Not a deleted entry. Set the flag to false. */ + delete_flag = FX_FALSE; + } + + /* Pickup the byte offset of the entry. */ + byte_offset = entry_ptr -> fx_dir_entry_byte_offset; + + /* Pickup the logical sector of the entry. */ + logical_sector = (ULONG)entry_ptr -> fx_dir_entry_log_sector; + + /* Figure out where what cluster we are in. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_data_sector_start)) + { + + /* Calculate the cluster that this logical sector is in. */ + cluster = (logical_sector - media_ptr -> fx_media_data_sector_start) / (media_ptr -> fx_media_sectors_per_cluster) + FX_FAT_ENTRY_START; + + /* Calculate the relative cluster. */ + relative_sector = logical_sector - (((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster))); + } + else + { + + /* Clear the cluster and the relative sector. */ + cluster = 0; + relative_sector = 0; + } + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) entry_ptr -> fx_dir_entry_log_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Setup a pointer into the buffer. */ + sector_base_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer; + work_ptr = sector_base_ptr + (UINT)entry_ptr -> fx_dir_entry_byte_offset; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize data for fault tolerant. */ + changed_ptr = work_ptr; + changed_size = 0; + changed_offset = entry_ptr -> fx_dir_entry_byte_offset; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if a long file name is present. */ + if (entry_ptr -> fx_dir_entry_long_name_present) + { + + /* Yes, long name is present - prepare short name and write out this name. */ + for (len = 0, i = 0, dotpos = 0, dotfound = 0; entry_ptr -> fx_dir_entry_name[len]; len++) + { + + /* Check for a dot. */ + if (entry_ptr -> fx_dir_entry_name[len] == '.') + { + + /* Check for leading dot. */ + if (len == 0) + { + /* Yes, this is a leading dot. */ + continue; + } + + /* Yes, a dot is present. From this position the extension will + be written. */ + dotfound = i; + dotpos = len + 1; + continue; + } + + /* Check for non-space and within the short file name length. */ + if ((entry_ptr -> fx_dir_entry_name[len] != ' ') && (i < 8)) + { + + /* Copy characters into the short file name area. */ + shortname[i] = entry_ptr -> fx_dir_entry_name[len]; + i++; + } + } + + /* Fill remaining short file name with spaces. */ + for (j = i; j < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE; j++) + { + shortname[j] = ' '; + } + + /* Determine if a dot was encountered. */ + if (dotpos) + { + + /* Process relative to the dot position. */ + if (entry_ptr -> fx_dir_entry_name[dotpos]) + { + shortname[8] = entry_ptr -> fx_dir_entry_name[dotpos++]; + } + if (entry_ptr -> fx_dir_entry_name[dotpos]) + { + shortname[9] = entry_ptr -> fx_dir_entry_name[dotpos++]; + } + if (entry_ptr -> fx_dir_entry_name[dotpos]) + { + shortname[10] = entry_ptr -> fx_dir_entry_name[dotpos++]; + } + + /* Determine if additional spaces are needed. */ + i = dotfound; + + for (; dotfound <= 7; dotfound++) + { + /* Add space... */ + shortname[dotfound] = ' '; + } + } + + /* Each entry contains 13 unicode entries. Calculate the remainder. */ + if (len % 13 == 0) + { + card = len / 13; + } + else + { + card = len / 13 + 1; + } + + /* Default the name match to true. */ + match = FX_TRUE; + + /* Loop through the newly derived short name and the original name and look + for a non-matching character. */ + l = 0; + k = 0; + while (k < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE) + { + + /* Determine if a space is detected in the short name. If so, + advance to the extension index. */ + if (shortname[k] == ' ') + { + + /* The first pad space was detected. First, check for a name + without an extension. */ + if (entry_ptr -> fx_dir_entry_name[l] == FX_NULL) + { + + /* All is okay, get out of the loop! */ + break; + } + + /* Now check for a period in the long name... if not, there is a non-match! */ + if (entry_ptr -> fx_dir_entry_name[l] != '.') + { + + /* Set the match flag to false and exit the loop. */ + match = FX_FALSE; + break; + } + + /* Otherwise move short file name index to the extension area and + increment the long file name index. */ + k = 8; + l++; + + /* Restart the loop at the top. */ + continue; + } + + /* Check for the dot for the 8.3 match... it is no longer in the + shortname but possibly still present in the long name. */ + if ((k == 8) && (entry_ptr -> fx_dir_entry_name[l] == '.')) + { + + /* Yes, handle the implicit dot in the shortname by + positioning past it in the long name. */ + l++; + } + + /* Do the names match? */ + if (shortname[k] != entry_ptr -> fx_dir_entry_name[l]) + { + + /* No, the names do not match, set the match flag to false and + exit the loop. */ + match = FX_FALSE; + break; + } + + /* Move the indices forward. */ + k++; + l++; + } + + /* Check if there is a dot in the name, but no extension in the short name. In this case, + we should create a mangled short name. */ + if ((dotpos) && (shortname[8] == ' ')) + { + + /* Something left.. the names do not match! */ + match = FX_FALSE; + } + + /* One final check to make sure there is nothing left on the long file name. */ + if (entry_ptr -> fx_dir_entry_name[l]) + { + + /* Something left.. the names do not match! */ + match = FX_FALSE; + } + + /* Determine if the derived short name matches exactly the long file name. If so + we don't need to mangle the name with a numeric value based on its entry. */ + if (match == FX_FALSE) + { + + /* Name does not match, create a mangled name. */ + + /* Generate short file name from LFN. */ + entry = entry_ptr -> fx_dir_entry_number; + + /* Name suffice is between 000 and FFFF in hex, calculate this short file + name's numeric component. */ + entry = entry % 0x10000; + + /* Build short name of the format xxx~NNNN.ext. */ + if (i > 3) + { + i = 3; + } + shortname[i++] = '~'; + + /* Loop to build the numeric part of the name. */ + for (l = 0; l < 4; l++) + { + + /* Shift down the entry number based on the numeric position. */ + if (l == 0) + { + temp = ((entry >> 12) & 0xf); + } + else if (l == 1) + { + temp = ((entry >> 8) & 0xf); + } + else if (l == 2) + { + temp = ((entry >> 4) & 0xf); + } + else + { + temp = ((entry) & 0xf); + } + + /* Now build hex value. */ + if (temp > 9) + shortname[i++] = (CHAR)('A' + (temp - 10)); + else + shortname[i++] = (CHAR)('0' + temp); + } + } + + /* Set end of short string to NULL. */ + shortname[11] = 0; + + /* Determine if the first character of the short file name is the directory free + value. If so, it must be changed. */ + if (((UCHAR)shortname[0] == (UCHAR)FX_DIR_ENTRY_FREE) && (delete_flag == FX_FALSE)) + { + + /* Change to 0x8F to be compatible with what DOS does. */ + shortname[0] = (CHAR)0x8F; + } + + /* Loop to convert the new short file name to upper case. */ + for (i = 0; i < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); i++) + { + + /* Pickup shortname character. */ + alpha = shortname[i]; + + /* Determine if character is lower case. */ + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Store the character - converted to upper case. */ + alpha = (CHAR)(alpha - ((CHAR)0x20)); + } + + /* Now store the short name character. */ + shortname[i] = alpha; + } + + /* Determine if there already is a short name and we are not deleting the entry. */ + if (entry_ptr -> fx_dir_entry_short_name[0] != 0) + { + + /* Yes, override the calculated shortname with the original 8.3 name. */ + + /* Clear the short file name area. */ + for (i = 0; i < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE; i++) + { + shortname[i] = ' '; + } + + /* Loop to copy the original short file name. */ + for (i = 0, j = 0; j < FX_DIR_NAME_SIZE; i++, j++) + { + + /* Check for end of copy conditions. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_short_name[i] == '.') + { + break; + } + if ((UCHAR)entry_ptr -> fx_dir_entry_short_name[i] == 0) + { + break; + } + + /* Pickup the character. */ + alpha = entry_ptr -> fx_dir_entry_short_name[i]; + + /* Copy file name character. */ + shortname[j] = alpha; + } + + /* Determine if there is anything left in the short file name. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_short_name[i] != 0) + { + + /* Pickup remaining characters. */ + for (i++, j = FX_DIR_NAME_SIZE; j < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE; i++, j++) + { + + /* If NULL is encountered, stop the copying. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_short_name[i] == 0) + { + break; + } + + /* Pickup the character. */ + alpha = entry_ptr -> fx_dir_entry_short_name[i]; + + /* Copy file name character. */ + shortname[j] = alpha; + } + } + + /* Loop to make sure the short name is upper case. */ + for (j = 0; j < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); j++) + { + + /* Pickup the character. */ + alpha = shortname[j]; + + /* Determine if character is lower case. */ + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Store the character - converted to upper case. */ + alpha = (CHAR)(alpha - ((CHAR)0x20)); + } + + /* Copy file name character. */ + shortname[j] = alpha; + } + + /* Determine if the first character of the short file name is the directory free + value. If so, it must be changed. */ + if (((UCHAR)shortname[0]) == ((UCHAR)FX_DIR_ENTRY_FREE)) + { + + /* Change to 0x8F to be compatible with what DOS does. */ + shortname[0] = (CHAR)0x8F; + } + } + + /* Loop to calculate the checksum. */ + for (i = checksum = 0; i < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE; i++) + { + + /* Calculate the checksum. */ + checksum = (UCHAR)((UCHAR)(((checksum & 1) << 7) | ((checksum & (UCHAR)0xfe) >> 1)) + shortname[i]); + } + + /* Set the last entry mark. */ + work_ptr[0] = (UCHAR)(0x40 | card); + + /* Loop to process remainder of long file name entry. */ + while (card > 0) + { + + /* Clear eof marker. */ + eof_marker = 0; + + /* Determine if the entry is free. */ + if ((UCHAR)shortname[0] == (UCHAR)FX_DIR_ENTRY_FREE) + { + /* Yes, place delete marker. */ + work_ptr[0] = (UCHAR)FX_DIR_ENTRY_FREE; + } + + /* Setup various long file name fields. */ + work_ptr[11] = FX_LONG_NAME; + work_ptr[12] = 0; + work_ptr[13] = checksum; + work_ptr[26] = 0; + work_ptr[27] = 0; + + /* Loop through file name fields. */ + for (i = 1, j = 13 * (card - 1); i < FX_DIR_ENTRY_SIZE; i += 2) + { + + /* Process relative to specific fields. */ + if ((i == 11) || (i == 26)) + { + continue; + } + + if (i == 13) + { + i = 12; + continue; + } + + /* Determine if the EOF marker is present. */ + if (eof_marker) + { + + work_ptr[i] = eof_marker; + work_ptr[i + 1] = eof_marker; + } + else + { + work_ptr[i] = (UCHAR)entry_ptr -> fx_dir_entry_name[j]; + work_ptr[i + 1] = 0; + } + + if (entry_ptr -> fx_dir_entry_name[j] == 0) + { + + /* end of name, pad with 0xff. */ + eof_marker = (UCHAR)0xff; + } + + j++; + } + + /* Move to the next directory entry. */ + work_ptr += FX_DIR_ENTRY_SIZE; + byte_offset += FX_DIR_ENTRY_SIZE; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Update changed_size. */ + changed_size += FX_DIR_ENTRY_SIZE; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if the entry overlaps into the next sector. */ + if (byte_offset >= media_ptr -> fx_media_bytes_per_sector) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_dir_log(media_ptr, logical_sector, changed_offset, changed_ptr, changed_size); + } + else + { +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Write current logical sector out. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); +#ifdef FX_ENABLE_FAULT_TOLERANT + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Determine if we are in the root directory. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_data_sector_start)) + { + + /* Determine the next sector of the directory entry. */ + if (relative_sector < (media_ptr -> fx_media_sectors_per_cluster - 1)) + { + + /* More sectors in this cluster. */ + + /* Simply increment the logical sector. */ + logical_sector++; + + /* Increment the relative sector. */ + relative_sector++; + } + else + { + + /* We need to move to the next cluster. */ + + /* Pickup the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Copy next cluster to the current cluster. */ + cluster = next_cluster; + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster >= media_ptr -> fx_media_fat_reserved)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Setup the relative sector (this is zero for subsequent cluster. */ + relative_sector = 0; + + /* Calculate the next logical sector. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + } + } + else + { + + /* Increment the logical sector. */ + logical_sector++; + + /* Determine if the logical sector is valid. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_data_sector_start)) + { + + /* We have exceeded the root directory. */ + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + } + + /* Read the sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Setup logical sector. */ + sector_base_ptr = media_ptr -> fx_media_memory_buffer; + + /* Setup a fresh byte offset. */ + byte_offset = 0; + + /* Setup a new pointer into the buffer. */ + work_ptr = sector_base_ptr; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize data for fault tolerant. */ + changed_ptr = work_ptr; + changed_size = 0; + changed_offset = 0; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + + /* Decrement loop control. */ + card--; + work_ptr[0] = (UCHAR)card; + } + + /* Determine if there is a short name. */ + if (entry_ptr -> fx_dir_entry_short_name[0] == 0) + { + + /* Loop to copy the new short file name. */ + for (i = 0; i < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); i++) + { + + /* Pickup shortname character. */ + alpha = shortname[i]; + + /* Now store the short name character. */ + *work_ptr++ = (UCHAR)alpha; + } + } + else + { + + /* Clear the short file name area. */ + for (i = 0; i < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE; i++) + { + work_ptr[i] = ' '; + } + + /* Loop to copy the old short file name. */ + for (i = 0, j = 0; j < FX_DIR_NAME_SIZE; i++, j++) + { + + /* Check for end of copy conditions. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_short_name[i] == '.') + { + break; + } + if ((UCHAR)entry_ptr -> fx_dir_entry_short_name[i] == 0) + { + break; + } + + /* Copy file name character. */ + work_ptr[j] = (UCHAR)entry_ptr -> fx_dir_entry_short_name[i]; + } + + /* Determine if there is anything left in the short file name. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_short_name[i] != 0) + { + + /* Pickup remaining characters. */ + for (i++, j = FX_DIR_NAME_SIZE; j < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE; i++, j++) + { + + /* If NULL is encountered, stop the copying. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_short_name[i] == 0) + { + break; + } + + /* Copy file name character. */ + work_ptr[j] = (UCHAR)entry_ptr -> fx_dir_entry_short_name[i]; + } + } + + /* Adjust the work pointer accordingly. */ + work_ptr += (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); + } + } + else + { + + /* Determine if long name was shorted. */ + if (entry_ptr -> fx_dir_entry_long_name_shorted > 0) + { + + /* Check for a valid short name. */ + if ((UCHAR)(0x40 | entry_ptr -> fx_dir_entry_long_name_shorted) == (UCHAR)(*work_ptr)) + { + + /* Loop through the file name. */ + for (j = 0; j < entry_ptr -> fx_dir_entry_long_name_shorted; j++) + { + + /* Check for a free entry to be written. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_FREE) + { + /* Delete long parts. */ + work_ptr[0] = (UCHAR)FX_DIR_ENTRY_FREE; + } + + /* Setup pointers for the name write. */ + work_ptr += FX_DIR_ENTRY_SIZE; + byte_offset += FX_DIR_ENTRY_SIZE; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Update changed_size. */ + changed_size += FX_DIR_ENTRY_SIZE; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if the write is within the current sector. */ + if (byte_offset >= media_ptr -> fx_media_bytes_per_sector) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_dir_log(media_ptr, (ULONG64) logical_sector, changed_offset, changed_ptr, changed_size); + } + else + { +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Write the current sector out. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); +#ifdef FX_ENABLE_FAULT_TOLERANT + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Determine if we are in the root directory. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_data_sector_start)) + { + + /* Determine the next sector of the directory entry. */ + if (relative_sector < (media_ptr -> fx_media_sectors_per_cluster - 1)) + { + + /* More sectors in this cluster. */ + + /* Simply increment the logical sector. */ + logical_sector++; + + /* Increment the relative sector. */ + relative_sector++; + } + else + { + + /* We need to move to the next cluster. */ + + /* Pickup the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Copy next cluster to the current cluster. */ + cluster = next_cluster; + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster >= media_ptr -> fx_media_fat_reserved)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Setup the relative sector (this is zero for subsequent cluster. */ + relative_sector = 0; + + /* Calculate the next logical sector. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + } + } + else + { + + /* Increment the logical sector. */ + logical_sector++; + + /* Determine if the logical sector is valid. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_data_sector_start)) + { + + /* We have exceeded the root directory. */ + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + } + + /* Read the next logical sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Move to the next sector buffer. */ + sector_base_ptr = media_ptr -> fx_media_memory_buffer; + + /* Setup new buffer pointers. */ + byte_offset = 0; + work_ptr = sector_base_ptr; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize data for fault tolerant. */ + changed_ptr = work_ptr; + changed_size = 0; + changed_offset = 0; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + } + } + } + + /* This is an 8.3 name. First clear the directory name. */ + for (j = 0; j < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE; j++) + { + work_ptr[j] = ' '; + } + + /* Copy leading dots in case of first two entries of a directory. */ + for (i = 0; (UCHAR)entry_ptr -> fx_dir_entry_name[i] == '.'; i++) + { + work_ptr[i] = '.'; + } + + /* Determine if there are more characters to copy. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_name[i] != 0) + { + + /* Copy directory name. */ + for (i = 0, j = 0; j < FX_DIR_NAME_SIZE; i++, j++) + { + + /* Check for end of copy conditions. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_name[i] == '.') + { + break; + } + if ((UCHAR)entry_ptr -> fx_dir_entry_name[i] == 0) + { + break; + } + + /* Pickup shortname character. */ + alpha = entry_ptr -> fx_dir_entry_name[i]; + + /* Determine if character is lower case. */ + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Store the character - converted to upper case. */ + alpha = (CHAR)(alpha - ((CHAR)0x20)); + } + + /* Copy a name character. */ + work_ptr[j] = (UCHAR)alpha; + } + } + + /* Determine if there are more characters in the name. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_name[i] != 0) + { + + /* Loop to copy the remainder of the name. */ + for (i++, j = FX_DIR_NAME_SIZE; j < FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE; i++, j++) + { + + /* Check for end of copy conditions. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_name[i] == 0) + { + break; + } + + /* Pickup shortname character. */ + alpha = entry_ptr -> fx_dir_entry_name[i]; + + /* Determine if character is lower case. */ + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Store the character - converted to upper case. */ + alpha = (CHAR)(alpha - ((CHAR)0x20)); + } + + /* Copy a name character. */ + work_ptr[j] = (UCHAR)alpha; + } + } + + /* Move to the next entry. */ + work_ptr += (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); + } + + /* Write out the 8.3 part of the name. */ + + /* Copy the attribute into the destination. */ + *work_ptr++ = entry_ptr -> fx_dir_entry_attributes; + + /* Copy the reserved byte. */ + *work_ptr++ = entry_ptr -> fx_dir_entry_reserved; + + /* Copy the created time in milliseconds. */ + *work_ptr++ = entry_ptr -> fx_dir_entry_created_time_ms; + + /* Copy the created time. */ + _fx_utility_16_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_created_time); + work_ptr = work_ptr + 2; /* Always 2 bytes */ + + /* Copy the created date. */ + _fx_utility_16_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_created_date); + work_ptr = work_ptr + 2; /* Always 2 bytes */ + + /* Copy the last accessed date. */ + _fx_utility_16_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_last_accessed_date); + work_ptr = work_ptr + 2; /* Always 2 bytes */ + + /* Determine if a FAT32 entry is present. */ + if (media_ptr -> fx_media_32_bit_FAT) + { + + /* Yes, FAT32 is present, store upper half of cluster. */ + temp = (entry_ptr -> fx_dir_entry_cluster >> 16); + _fx_utility_16_unsigned_write(work_ptr, temp); + } + else + { + + /* No, FAT16 or FAT12 is present, just write a 0 for + the upper half of the cluster. */ + _fx_utility_16_unsigned_write(work_ptr, 0); + } + + /* Advance the entry pointer. */ + work_ptr = work_ptr + 2; /* Always 2 bytes */ + + /* Copy the time into the destination. */ + _fx_utility_16_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_time); + work_ptr = work_ptr + 2; /* Always 2 bytes */ + + /* Copy the date into the destination. */ + _fx_utility_16_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_date); + work_ptr = work_ptr + 2; /* Always 2 bytes */ + + /* Copy the starting cluster into the destination. */ + _fx_utility_16_unsigned_write(work_ptr, (UINT)entry_ptr -> fx_dir_entry_cluster); + work_ptr = work_ptr + 2; /* Always 2 bytes */ + + /* Copy the file size into the destination. */ + _fx_utility_32_unsigned_write(work_ptr, (ULONG)entry_ptr -> fx_dir_entry_file_size); + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Update changed_size. */ + changed_size += FX_DIR_ENTRY_SIZE; + + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED)) + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_dir_log(media_ptr, (ULONG64) logical_sector, changed_offset, changed_ptr, changed_size); + } + else + { +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Write the directory sector to the media. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); +#ifdef FX_ENABLE_FAULT_TOLERANT + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Determine if there is a previously found directory entry in the directory + search cache. */ + if (media_ptr -> fx_media_last_found_name[0]) + { + + /* Determine if the cached search directory entry matches the directory entry being + written. */ + if ((entry_ptr -> fx_dir_entry_log_sector == media_ptr -> fx_media_last_found_entry.fx_dir_entry_log_sector) && + (entry_ptr -> fx_dir_entry_byte_offset == media_ptr -> fx_media_last_found_entry.fx_dir_entry_byte_offset)) + { + + /* Yes, this entry is the same as the one currently in the directory search cache. + Update various fields in the directory search cache with the information being + written now. */ + media_ptr -> fx_media_last_found_entry.fx_dir_entry_cluster = entry_ptr -> fx_dir_entry_cluster; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_file_size = entry_ptr -> fx_dir_entry_file_size; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_attributes = entry_ptr -> fx_dir_entry_attributes; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_time = entry_ptr -> fx_dir_entry_time; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_date = entry_ptr -> fx_dir_entry_date; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_reserved = entry_ptr -> fx_dir_entry_reserved; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_created_time_ms = entry_ptr -> fx_dir_entry_created_time_ms; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_created_time = entry_ptr -> fx_dir_entry_created_time; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_created_date = entry_ptr -> fx_dir_entry_created_date; + } + } +#endif + + /* Return success to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c b/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c new file mode 100644 index 00000000..06f995e8 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_read.c @@ -0,0 +1,718 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_utility.h" +#include "fx_directory_exFAT.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_exFAT_entry_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the supplied directory entry from the supplied */ +/* source directory. If the supplied directory entry is NULL, then */ +/* the root directory is assumed. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* source_dir Source directory entry */ +/* entry_ptr Directory entry number */ +/* destination_ptr Pointer to destination for */ +/* the directory entry */ +/* hash Hash value of the file name */ +/* skip Skip reading file name */ +/* unicode_name Destination for unicode name */ +/* unicode_length Destination for unicode name */ +/* length */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* *entry_ptr should point to the 8:3 entry if it is a long name */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_logical_sector_read Read directory sector */ +/* _fx_utility_16_unsigned_read Read a USHORT from memory */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* _fx_utility_64_unsigned_read Read a ULONG64 from memory */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_entry_read */ +/* _fx_directory_free_search */ +/* _fx_directory_next_full_entry_find */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_exFAT_entry_read(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, + ULONG *entry_ptr, FX_DIR_ENTRY *destination_ptr, + UINT hash, UINT skip, UCHAR *unicode_name, UINT *unicode_length) +{ + +UINT status = FX_SUCCESS; +UCHAR i; +UCHAR j; +ULONG cluster = 0, next_cluster = 0; +ULONG64 next_logical_sector; +UINT relative_cluster; +UINT relative_sector = 0; +ULONG64 logical_sector; +ULONG byte_offset; +ULONG bytes_per_cluster; +UCHAR *read_ptr; +UCHAR secondary_count; +UCHAR name_length = 0; +UCHAR name_pos = 0; +UCHAR copy_size = 0; +USHORT checksum = 0; +USHORT file_checksum; +ULONG date_time; +UCHAR dont_use_fat; +ULONG clusters_count = 0; + + + /* Calculate the byte offset of this directory entry. */ + byte_offset = (*entry_ptr) * FX_DIR_ENTRY_SIZE; + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Now determine the relative cluster in the sub-directory file. */ + relative_cluster = (UINT)(byte_offset / bytes_per_cluster); + + /* Calculate the byte offset within the cluster. */ + byte_offset = byte_offset % bytes_per_cluster; + + /* Now figure out the relative sector within the cluster. */ + relative_sector = (UINT)(byte_offset / ((ULONG)media_ptr -> fx_media_bytes_per_sector)); + + /* Read the directory sector into the internal memory buffer. */ + + /* Determine if there is a sub-directory. */ + if (source_dir) + { + + /* Yes, setup the starting cluster to that of the sub-directory. */ + cluster = source_dir -> fx_dir_entry_cluster; + + /* Save the cluster count for the directory entry. */ + clusters_count = (ULONG)((source_dir -> fx_dir_entry_file_size + bytes_per_cluster - 1) / bytes_per_cluster - 1); + } + else + { + + /* No, setup the starting cluster to the exFAT root directory cluster. */ + cluster = media_ptr -> fx_media_root_cluster_32; + } + + /* Loop to position to the appropriate cluster. */ + for (i = 0;; i++) + { + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster > FX_RESERVED_1_exFAT)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Read the next cluster. First check if FAT is used. */ + if ((source_dir) && (source_dir -> fx_dir_entry_dont_use_fat & 1)) + { + + /* FAT is not used. Check for file size range. */ + if (i >= clusters_count) + { + + /* We are at the last cluster, set next cluster to LAST CLUSTER. */ + next_cluster = FX_LAST_CLUSTER_exFAT; + } + else + { + + /* The next cluster is just after the current cluster. */ + next_cluster = cluster + 1; + } + } + else + { + + /* FAT is used, call FAT read function to get the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + } + + /* Are we positioned to the appropriate cluster? */ + if (i < relative_cluster) + { + cluster = next_cluster; + } + else + { + break; + } + } + + /* At this point, the directory data sector needs to be read. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + relative_sector; + + /* Determine if next sector is in next cluster or in next sector. */ + if ((bytes_per_cluster - byte_offset) >= (ULONG)media_ptr -> fx_media_bytes_per_sector) + { + + /* Move to the next logical sector. */ + next_logical_sector = logical_sector + 1; + } + else + { + /* No, calculate the next logical sector. */ + if ((next_cluster >= FX_FAT_ENTRY_START) && (next_cluster <= FX_RESERVED_1_exFAT)) + { + next_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)next_cluster - FX_FAT_ENTRY_START) * ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + } + else + { + next_logical_sector = 0; /* No such sector possible. */ + } + } + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, ((ULONG64) logical_sector), + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Calculate the byte offset within this sector. */ + byte_offset = byte_offset % media_ptr -> fx_media_bytes_per_sector; + + + /* Setup a pointer into the buffer. */ + read_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Save the logical sector and byte offset in the returned directory entry. */ + destination_ptr -> fx_dir_entry_log_sector = logical_sector; + destination_ptr -> fx_dir_entry_next_log_sector = next_logical_sector; + destination_ptr -> fx_dir_entry_byte_offset = byte_offset; + + /* Clear the short file name information. */ + destination_ptr -> fx_dir_entry_long_name_shorted = 0; + destination_ptr -> fx_dir_entry_short_name[0] = 0; + + /* Check if the directory entry type has InUse bit set, or if it is an end marker. */ + if ((*read_ptr & FX_EXFAT_ENTRY_TYPE_IN_USE_MASK) || (*read_ptr == FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER)) + { + + /* Set the directory entry type. */ + destination_ptr -> fx_dir_entry_type = *read_ptr; + } + else + { + + /* This is a free entry. */ + destination_ptr -> fx_dir_entry_type = FX_EXFAT_DIR_ENTRY_TYPE_FREE; + } + + /* Check if the entry is a file directory entry. */ + if (destination_ptr -> fx_dir_entry_type != FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY) + { + + /* The entry is not directory entry, check if we know the type. */ + if ((destination_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_ALLOCATION_BITMAP) || + (destination_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_UP_CASE_TABLE) || + (destination_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_VOLUME_LABEL) || + (destination_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_FREE) || + (destination_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER)) + { + + /* Known critical primary or free, just skip it. */ + return(FX_SUCCESS); + } + + /* Check if the entry is unknown critical primary directory entry. */ + if ((destination_ptr -> fx_dir_entry_type & (FX_EXFAT_ENTRY_TYPE_IMPORTANCE_MASK | FX_EXFAT_ENTRY_TYPE_CATEGORY_MASK)) == 0) + { + + /* Yes, it is an unknown critical primary entry. Return error. */ + return(FX_MEDIA_INVALID); + } + + /* Just ignore. */ + return(FX_SUCCESS); + } + + /* Calculate checksum for file entry. */ + for (j = 0; j < FX_DIR_ENTRY_SIZE; ++j) + { + + /* Skip the checksum field. */ + if ((j == 2) || (j == 3)) + { + continue; + } + + /* Calculate the checksum using the algorithm described in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + checksum = (USHORT)(((checksum >> 1) | (checksum << 15)) + read_ptr[j]); + } + + /* Read secondary count field. */ + read_ptr++; + secondary_count = *read_ptr; + + /* Validate the secondary count field. */ + if (secondary_count < 2) + { + + /* Something wrong, file entry should have at least 2 entries: stream and filename. */ + return(FX_FILE_CORRUPT); + } + + /* Save secondary count. */ + destination_ptr -> fx_dir_entry_secondary_count = secondary_count; + + /* exFAT has no short/long name concept, set long name present for compatibility. */ + destination_ptr -> fx_dir_entry_long_name_present = 1; + + /* Advance the pointer to the checksum field. */ + read_ptr++; + + /* Read checksum field. */ + file_checksum = (USHORT)_fx_utility_16_unsigned_read(read_ptr); + read_ptr += 2; + + /* Read FileAttributes field. */ + destination_ptr -> fx_dir_entry_attributes = (UCHAR)_fx_utility_16_unsigned_read(read_ptr); /* The same order as FAT32 but more unused bits. */ + + /* Skip Reserved1. */ + read_ptr += 4; + + /* Read CreatedTimestamp field. */ + date_time = _fx_utility_32_unsigned_read(read_ptr); + destination_ptr -> fx_dir_entry_created_time = date_time & 0xffff; + destination_ptr -> fx_dir_entry_created_date = date_time >> 16; + read_ptr += 4; + + /* Read LastModifiedTimestamp. */ + date_time = _fx_utility_32_unsigned_read(read_ptr); + destination_ptr -> fx_dir_entry_time = date_time & 0xffff; + destination_ptr -> fx_dir_entry_date = date_time >> 16; + read_ptr += 4; + + /* Read LastAccessedTimestamp. */ + date_time = _fx_utility_32_unsigned_read(read_ptr); + destination_ptr -> fx_dir_entry_last_accessed_date = date_time >> 16; + read_ptr += 4; + + /* Read Create10msIncrement. */ + destination_ptr -> fx_dir_entry_created_time_ms = *read_ptr; + read_ptr++; + + /* LastModified10msIncrement field is currently ignored. */ + read_ptr++; + + /* CreateUtcOffset field is currently ignored. */ + read_ptr++; + + /* LastModifiedUtcOffset field is currently ignored. */ + read_ptr++; + + /* LastAccessedUtcOffset field is currently ignored. */ + + /* Process all the secondary directory entries. */ + for (i = 0; i < secondary_count; ++i) + { + + /* Determine if a new sector needs to be read. */ + if (byte_offset + FX_DIR_ENTRY_SIZE >= media_ptr -> fx_media_bytes_per_sector) + { + + /* Determine the next sector of the directory entry. */ + if (relative_sector < (media_ptr -> fx_media_sectors_per_cluster - 1)) + { + + /* More sectors in this cluster. */ + + /* Simply increment the logical sector. */ + logical_sector++; + + /* Increment the relative sector. */ + relative_sector++; + } + else + { + + /* We need to move to the next cluster. */ + + /* Read the next cluster. First check if FAT is used. */ + if ((source_dir) && (source_dir -> fx_dir_entry_dont_use_fat & 1)) + { + + /* FAT is not used. Check for file size range. */ + if (relative_cluster >= clusters_count) + { + + /* We are at the last cluster, set next cluster to LAST CLUSTER. */ + next_cluster = FX_LAST_CLUSTER_exFAT; + } + else + { + + /* The next cluster is just after the current cluster. */ + next_cluster = cluster + 1; + } + } + else + { + + /* FAT is used, call FAT read function to get the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + } + + /* Copy next cluster to the current cluster. */ + cluster = next_cluster; + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster > FX_RESERVED_1_exFAT)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Now increment the relative cluster. */ + relative_cluster++; + + /* Setup the relative sector (this is zero for subsequent cluster. */ + relative_sector = 0; + + /* Calculate the next logical sector. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + } + + /* Read the new sector. */ + status = _fx_utility_logical_sector_read(media_ptr, ((ULONG64) logical_sector), + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Check I/O status. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Set the byte offset to 0 for new sector. */ + byte_offset = 0; + } + else + { + + /* Calculate the new byte offset. */ + byte_offset += FX_DIR_ENTRY_SIZE; + } + + /* Read sub entry. */ + read_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Calculate checksum for sub entry. */ + for (j = 0; j < FX_DIR_ENTRY_SIZE; ++j) + { + + /* Right rotate the checksum by one bit position and add the data. */ + checksum = (USHORT)(((checksum >> 1) | (checksum << 15)) + read_ptr[j]); + } + + /* Add the entry number to the next entry. */ + (*entry_ptr)++; + + /* Check if we are processing the first secondary directory entry. */ + if (i == 0) + { + + /* Make sure the directory entry type is stream extension. */ + if (*read_ptr != FX_EXFAT_DIR_ENTRY_TYPE_STREAM_EXTENSION) + { + + /* Something wrong, stream entry should be next to file entry. */ + return(FX_FILE_CORRUPT); + } + + /* Read stream entry. */ + + /* Advance the pointer to general secondary flags field. */ + read_ptr++; + + /* Read NoFatChain field. */ + dont_use_fat = ((*read_ptr) >> 1) & 1; /* 0 bit - current */ + + /* Check if we have a parent directory. */ + if (source_dir) + { + + /* Save the dont_use_fat flag for parent directory. */ + dont_use_fat = (UCHAR)(dont_use_fat | ((source_dir -> fx_dir_entry_dont_use_fat & 1) << 1)); /* 1st bit parent */ + } + + /* Put the dont_use_fat flag to the destination. */ + destination_ptr -> fx_dir_entry_dont_use_fat = (CHAR)dont_use_fat; + + /* Skip the reserved1 field. */ + read_ptr += 2; + + /* Read the name length field. */ + name_length = *read_ptr; + + /* Check if name_length is invalid. */ + if (name_length == 0) + { + + /* Name length should be at least 1. Return error. */ + return(FX_FILE_CORRUPT); + } + + /* Advance the pointer to the name hash field. */ + read_ptr++; + + /* Hash search */ + if (skip || (hash && (hash != _fx_utility_16_unsigned_read(read_ptr)))) + { + + /* Wrong hash, skip filename. */ + destination_ptr -> fx_dir_entry_type = FX_EXFAT_DIR_ENTRY_TYPE_STREAM_EXTENSION; + name_length = 0; + (*entry_ptr) += (ULONG)(secondary_count - 1); + + /* Return success. */ + return(FX_SUCCESS); + } + + /* Skip name hash and reserved2. */ + read_ptr += 4; + + /* Read Valid Data Len. */ + destination_ptr -> fx_dir_entry_file_size = _fx_utility_64_unsigned_read(read_ptr); + + /* Skip ValidDataLen and reserved3. */ + read_ptr += 12; + destination_ptr -> fx_dir_entry_cluster = _fx_utility_32_unsigned_read(read_ptr); + read_ptr += 4; + + /* Read Data Len. */ + destination_ptr -> fx_dir_entry_available_file_size = _fx_utility_64_unsigned_read(read_ptr); + + /* Checks for corruption */ + if (((destination_ptr -> fx_dir_entry_available_file_size == 0) && + (destination_ptr -> fx_dir_entry_cluster != 0)) || + ((destination_ptr -> fx_dir_entry_available_file_size != 0) && + (destination_ptr -> fx_dir_entry_cluster == 0))) + { + + /* Return file corrupt error. */ + return(FX_FILE_CORRUPT); + } + + /* File System Specification Ver 3.00 */ + if (destination_ptr -> fx_dir_entry_cluster == 0) + { + + /* Don't use FAT by default. */ + destination_ptr -> fx_dir_entry_dont_use_fat |= 1; + } + + /* Check for directory restrictions. */ + if ((destination_ptr -> fx_dir_entry_attributes & FX_DIRECTORY) && + (destination_ptr -> fx_dir_entry_available_file_size != destination_ptr -> fx_dir_entry_file_size)) + { + + /* Return file corrupt error. */ + return(FX_FILE_CORRUPT); + } + + /* Check if the directory size exceed file system limits. */ + if ((destination_ptr -> fx_dir_entry_attributes & FX_DIRECTORY) && + (destination_ptr -> fx_dir_entry_available_file_size > FX_EXFAT_MAX_DIRECTORY_SIZE)) + { + + /* Return the no more space error. */ + return(FX_NO_MORE_SPACE); + } + } + else + { + + /* Check if the entry type is file name directory entry. */ + if (*read_ptr == FX_EXFAT_DIR_ENTRY_TYPE_FILE_NAME) + { + + /* Skip the entry type and flags field. */ + read_ptr += 2; + + /* There are 15 characters in one file name directory entry. */ + if (name_length > 15) + { + + /* Set copy size to the max size of one entry. */ + copy_size = 15; + } + else + { + + /* Set copy size to the acutal remaining length. */ + copy_size = name_length; + } + + /* Check if we are requested to return the unicode name. */ + if (unicode_name) + { + + /* Loop to copy the unicode file name. from the file name directory entry. */ + for (j = 0; j < copy_size * 2; ++j) + { + + /* Copy the unicode file name from the file name directory entry. */ + unicode_name[name_pos * 2 + j] = *read_ptr++; + } + + /* Revert the read pointer for later use. */ + read_ptr -= copy_size * 2; + } + + /* Loop to copy the non-unicode file name. */ + for (j = 0; j < copy_size; ++j) + { + + /* Copy and convert the file name from the file name directory entry. */ + destination_ptr -> fx_dir_entry_name[name_pos++] = (CHAR)_fx_utility_16_unsigned_read(read_ptr); + read_ptr += 2; + } + + /* Modify the name_length to indicate the remaining length. */ + name_length = (UCHAR)(name_length - copy_size); + } + else if (((*read_ptr & (FX_EXFAT_ENTRY_TYPE_IN_USE_MASK | FX_EXFAT_ENTRY_TYPE_IMPORTANCE_MASK | FX_EXFAT_ENTRY_TYPE_CATEGORY_MASK)) == + (FX_EXFAT_ENTRY_TYPE_IN_USE_MASK | FX_EXFAT_ENTRY_TYPE_CATEGORY_MASK))) + { + + /* Unknown critical secondary, we can't work with this directory. */ + return(FX_FILE_CORRUPT); + } + } + } + + /* Terminate the entry name string. */ + destination_ptr -> fx_dir_entry_name[name_pos] = 0; + + /* Check if we are requested to return the unicode name. */ + if (unicode_name) + { + + /* Terminate the unicode name string. */ + unicode_name[name_pos * 2] = 0; + unicode_name[name_pos * 2 + 1] = 0; + + /* Check if we are requested to return the unicode name length. */ + if (unicode_length) + { + + /* Return the unicode name length. */ + *unicode_length = name_pos; + } + } + + /* Verify checksum. */ + if (checksum != file_checksum) + { + + /* Return corrupted file error. */ + return(FX_FILE_CORRUPT); + } + + /* Check if we have found all the file name directory entries. */ + if (name_length != 0) + { + + /* Return file corrupted error. */ + return(FX_FILE_CORRUPT); + } + + /* Return success. */ + return(FX_SUCCESS); +} + +#endif + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c b/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c new file mode 100644 index 00000000..e5550593 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_entry_write.c @@ -0,0 +1,102 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + +#ifdef FX_ENABLE_EXFAT +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_exFAT_entry_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes the supplied directory entry to the specified */ +/* logical sector and offset. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* entry_ptr Pointer to directory entry */ +/* update_level Update level for entry write */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_exFAT_unicode_entry_write */ +/* */ +/* CALLED BY */ +/* */ +/* fx_directory_attributes_set */ +/* fx_directory_create */ +/* fx_directory_delete */ +/* fx_directory_exFAT_unicode_entry_write */ +/* fx_directory_rename */ +/* fx_file_allocate */ +/* fx_file_attributes_set */ +/* fx_file_best_effort_allocate */ +/* fx_file_close */ +/* fx_file_create */ +/* fx_file_date_time_set */ +/* fx_file_delete */ +/* fx_file_rename */ +/* fx_file_truncate_release */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_exFAT_entry_write(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr, UCHAR update_level) +{ + +UINT status; + + + /* Call the unicode director entry write function. */ + status = _fx_directory_exFAT_unicode_entry_write(media_ptr, entry_ptr, update_level, NULL, 0); + + /* Return completion status. */ + return(status); +} + +#endif + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c b/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c new file mode 100644 index 00000000..2546e1c9 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_free_search.c @@ -0,0 +1,516 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_free_search PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function searches the media for a free directory entry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_ptr Pointer to directory to */ +/* search in */ +/* entry_ptr Pointer to directory entry */ +/* record */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_exFAT_entry_read Read entries from directory */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_utility_logical_sector_flush Flush logical sector cache */ +/* _fx_utility_logical_sector_read Read logical sector */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state in bitmap */ +/* _fx_utility_exFAT_bitmap_flush Flush written exFAT bitmap */ +/* _fx_utility_exFAT_allocate_new_cluster */ +/* Allocate new cluster */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 William E. Lamie Modified comment(s), fixed */ +/* errors without cache, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_exFAT_free_search(FX_MEDIA *media_ptr, FX_DIR_ENTRY *directory_ptr, FX_DIR_ENTRY *entry_ptr) +{ + +ULONG i; +UCHAR *work_ptr; +UINT status, total_entries; +ULONG64 entry_sector = 0; +ULONG64 entry_next_sector = 0; +ULONG entry_offset = 0; +ULONG cluster; +ULONG last_cluster; +ULONG directory_entries; +ULONG64 logical_sector; +FX_DIR_ENTRY *search_dir_ptr; +ULONG free_entry_start; +UINT sectors; +#ifndef FX_DISABLE_CACHE +FX_CACHED_SECTOR *cache_entry_ptr; +#endif +ULONG bytes_per_cluster; + + + /* Get name length. */ + i = _fx_utility_string_length_get(entry_ptr -> fx_dir_entry_name, FX_MAX_EX_FAT_NAME_LEN); + + /* Check if name is valid. */ + if (entry_ptr -> fx_dir_entry_name[i] != 0) + { + + /* Invalid name, return error. */ + return(FX_INVALID_NAME); + } + /* Determine the total entries. */ + total_entries = 2 + (i + 14) / 15; + + /* Determine if the search is in the root directory or in a + sub-directory. Note: the directory search function clears the + first character of the name for the root directory. */ + if (directory_ptr -> fx_dir_entry_name[0]) + { + + /* Search for a free entry in a sub-directory. */ + directory_entries = (ULONG)directory_ptr -> fx_dir_entry_file_size / FX_DIR_ENTRY_SIZE; + + /* Point the search directory pointer to this entry. */ + search_dir_ptr = directory_ptr; + } + else + { + + /* Find a free entry in the root directory. */ + + /* Setup the number of directory entries. */ + directory_entries = (ULONG)media_ptr -> fx_media_root_directory_entries; + + /* Set the search pointer to NULL since we are working off of the + root directory. */ + search_dir_ptr = FX_NULL; + + /* Clear dont_use_fat for root directory. */ + directory_ptr -> fx_dir_entry_dont_use_fat = 0; + } + + /* Loop through entries in the search directory. Yes, this is a + linear search! */ + i = 0; + free_entry_start = directory_entries; + + if (directory_entries > 0) + { + do + { + /* Read an entry from the directory. */ + status = + _fx_directory_exFAT_entry_read(media_ptr, + search_dir_ptr, &i, entry_ptr, 0, FX_TRUE, NULL, NULL); + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Determine if this is an empty entry. */ + if ((entry_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_FREE) || + (entry_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER)) + { + /* Determine if we are at the first free entry. */ + if (free_entry_start == directory_entries) + { + + /* Remember the start of the free entry. */ + free_entry_start = i; + entry_sector = entry_ptr -> fx_dir_entry_log_sector; + entry_next_sector = entry_ptr -> fx_dir_entry_next_log_sector; + entry_offset = entry_ptr -> fx_dir_entry_byte_offset; + } + + /* Determine if there are enough free entries to satisfy the request. */ + if ((i - free_entry_start + 1) >= total_entries) + { + FX_INT_SAVE_AREA + + /* Found an empty slot. All the pertinent information is already + in the entry structure. */ + entry_ptr -> fx_dir_entry_log_sector = entry_sector; + entry_ptr -> fx_dir_entry_next_log_sector = entry_next_sector; + entry_ptr -> fx_dir_entry_byte_offset = entry_offset; + + /* Initialize the additional directory entries. */ + entry_ptr -> fx_dir_entry_created_time_ms = 0; + + /* Lockout interrupts for time/date access. */ + FX_DISABLE_INTS + + entry_ptr -> fx_dir_entry_created_time = _fx_system_time; + entry_ptr -> fx_dir_entry_created_date = _fx_system_date; + entry_ptr -> fx_dir_entry_last_accessed_date = _fx_system_date; + + /* Restore interrupts. */ + FX_RESTORE_INTS + + /* Return a successful completion. */ + return(FX_SUCCESS); + } + } + else + { + + /* Reset the free entry start. */ + free_entry_start = directory_entries; + } + + /* Move to the next entry. */ + i++; + } while (i < directory_entries); + } + + /* No empty entries were found. If the specified directory is a sub-directory, + attempt to allocate another cluster to it. */ + if (media_ptr -> fx_media_available_clusters) + { + ULONG64 size; + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check if it is a sub directory. */ + if (search_dir_ptr) + { + + /* Set size to the available file size. */ + size = search_dir_ptr -> fx_dir_entry_available_file_size; + } + else + { + + /* Root directory, set size to root directory size. */ + size = media_ptr -> fx_media_root_directory_entries * FX_DIR_ENTRY_SIZE; + } + + /* Check for directory restriction */ + if (size + bytes_per_cluster > FX_EXFAT_MAX_DIRECTORY_SIZE) + { + return(FX_NO_MORE_SPACE); + } + + /* Search the FAT for the next available cluster. */ + status = _fx_utility_exFAT_allocate_new_cluster(media_ptr, search_dir_ptr, &last_cluster, &cluster); + + if (status != FX_SUCCESS) + { + return(status); + } + + /* Decrease the available clusters in the media. */ + media_ptr -> fx_media_available_clusters--; + + /* Defer the update of the FAT entry and the last cluster of the current + directory entry until after the new cluster is initialized and written out. */ + + /* Update entry size. */ + if (search_dir_ptr) + { + search_dir_ptr -> fx_dir_entry_file_size += bytes_per_cluster; + search_dir_ptr -> fx_dir_entry_available_file_size = search_dir_ptr -> fx_dir_entry_file_size; + } + else + { + + /* Change root directory entry count - FAT32 has a variable sized root directory. */ + media_ptr -> fx_media_root_directory_entries += bytes_per_cluster / FX_DIR_ENTRY_SIZE; + } + + /* Calculate the logical sector of this cluster. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + ((((ULONG64)cluster) - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + + /* Pickup the number of sectors for the next directory cluster. */ + sectors = media_ptr -> fx_media_sectors_per_cluster; + + /* Read the logical sector just for cache reasons. */ + status = _fx_utility_logical_sector_read(media_ptr, logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Clear the entire first sector of the new sub-directory cluster. */ + work_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer; + i = 0; + while (i < media_ptr -> fx_media_bytes_per_sector) + { + + /* Clear 4 bytes. */ + *((ULONG *)work_ptr) = (ULONG)0; + + /* Increment pointer. */ + work_ptr = work_ptr + sizeof(ULONG); + + /* Increment counter. */ + i = i + sizeof(ULONG); + } + +#ifndef FX_DISABLE_CACHE + /* Invalidate all cached sectors that are contained in the newly allocated first + cluster of the directory. */ + + /* Pickup the total number of cache entries. */ + i = (UINT)media_ptr -> fx_media_sector_cache_size; + + /* Setup pointer to first cache entry (not in list order). */ + cache_entry_ptr = media_ptr -> fx_media_sector_cache; + + /* Examine all the logical sector cache entries. */ + while (i--) + { + + /* Determine if the cached entry is a sector in the first cluster of the + new directory. We don't need to worry about the first sector since it + was read using the logical sector read utility earlier. */ + if ((cache_entry_ptr -> fx_cached_sector >= (logical_sector + 1)) && + (cache_entry_ptr -> fx_cached_sector < (logical_sector + sectors))) + { + + /* Yes, we have found a logical sector in the cache that is one of the directory + sectors that will be written with zeros. Because of this, simply make this + cache entry invalid. */ + cache_entry_ptr -> fx_cached_sector = 0; + cache_entry_ptr -> fx_cached_sector_buffer_dirty = FX_FALSE; + } + + /* Move to next entry in the cached sector list. */ + if (cache_entry_ptr -> fx_cached_sector_next_used) + { + cache_entry_ptr = cache_entry_ptr -> fx_cached_sector_next_used; + } + } +#endif + + /* Clear all sectors of new sub-directory cluster. */ + do + { + + /* Decrease the number of sectors to clear. */ + sectors--; + + /* Build Write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector + ((ULONG)sectors); + media_ptr -> fx_media_driver_sectors = 1; + + /* Set the system write flag since we are writing a directory sector. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + + /* Invoke the driver to write the sector. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if an error occurred. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + } while (sectors); + +#ifdef FX_FAULT_TOLERANT + + /* Flush the internal logical sector. */ + _fx_utility_logical_sector_flush(media_ptr, logical_sector, media_ptr -> fx_media_sectors_per_cluster, FX_FALSE); +#endif + + if ((!search_dir_ptr) || (!(search_dir_ptr -> fx_dir_entry_dont_use_fat & 1))) + { + + /* At this point, link up the last cluster with the new cluster. */ + + /* Setup the last cluster to indicate the end of the chain. */ + status = _fx_utility_FAT_entry_write(media_ptr, cluster, FX_LAST_CLUSTER_exFAT); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Link the last cluster of the directory to the new cluster. */ + if (last_cluster) + { + + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, cluster); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + } + } + + if (!last_cluster && search_dir_ptr) + { + + search_dir_ptr -> fx_dir_entry_cluster = cluster; + } + + /* Mark the cluster as used. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, cluster, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Move cluster search pointer forward. */ + media_ptr -> fx_media_cluster_search_start = cluster + 1; + + /* Determine if this needs to be wrapped. */ + if (media_ptr -> fx_media_cluster_search_start >= media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) + { + + /* Wrap the search to the beginning FAT entry. */ + media_ptr -> fx_media_cluster_search_start = FX_FAT_ENTRY_START; + } + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); + + /* Flush the bitmap and its logical sector. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + _fx_utility_logical_sector_flush(media_ptr, media_ptr -> fx_media_exfat_bitmap_start_sector + + (cluster >> media_ptr -> fx_media_exfat_bitmap_clusters_per_sector_shift), ((ULONG64) 1), FX_FALSE); +#endif + + /* Finally load up the directory entry with information for the + beginning of the new cluster. */ + { + FX_INT_SAVE_AREA + + entry_ptr -> fx_dir_entry_name[0] = 0; + if (free_entry_start == directory_entries) + { + + /* start from begining of new cluster */ + entry_ptr -> fx_dir_entry_log_sector = logical_sector; + + /* There are more sectors in this cluster. */ + entry_ptr -> fx_dir_entry_next_log_sector = logical_sector + 1; + + /* Clear the byte offset since this is a new entry. */ + entry_ptr -> fx_dir_entry_byte_offset = 0; + } + else + { + + /* start from end of last cluster */ + entry_ptr -> fx_dir_entry_log_sector = entry_sector; + + /* Next sector in new cluster */ + entry_ptr -> fx_dir_entry_next_log_sector = logical_sector; + + /* Set byte offset */ + entry_ptr -> fx_dir_entry_byte_offset = entry_offset; + } + + /* Lockout interrupts for time/date access. */ + FX_DISABLE_INTS + + entry_ptr -> fx_dir_entry_created_time = _fx_system_time; + entry_ptr -> fx_dir_entry_created_date = _fx_system_date; + entry_ptr -> fx_dir_entry_last_accessed_date = _fx_system_date; + + /* Restore interrupts. */ + FX_RESTORE_INTS + } + + entry_ptr -> fx_dir_entry_type = FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER; + + /* Return a successful status. */ + return(FX_SUCCESS); + } + + /* Return "not found" status to the caller. */ + return(FX_NOT_FOUND); +} +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c b/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c new file mode 100644 index 00000000..5d8b83d7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_exFAT_unicode_entry_write.c @@ -0,0 +1,946 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_utility.h" +#include "fx_directory_exFAT.h" +#include "fx_directory.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_exFAT_unicode_entry_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes the supplied directory entry to the specified */ +/* logical sector and offset. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* entry_ptr Pointer to directory entry */ +/* update_level Update level for entry write */ +/* unicode_name Unicode file name */ +/* unicode_length Length of unicode file name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_cluster_free Release unused clusters */ +/* _fx_utility_exFAT_name_hash_get Get name hash */ +/* _fx_utility_FAT_entry_read Read a new FAT entry */ +/* _fx_utility_logical_sector_flush Flush the written log sector */ +/* _fx_utility_logical_sector_read Read directory sector */ +/* _fx_utility_logical_sector_write Write directory sector */ +/* _fx_utility_string_length_get Get string's length */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* _fx_utility_32_unsigned_write Write a ULONG from memory */ +/* _fx_utility_64_unsigned_read Read a ULONG64 from memory */ +/* _fx_fault_tolerant_add_dir_log Add directory redo log */ +/* _fx_fault_tolerant_add_checksum_log Add checksum redo log */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_exFAT_unicode_entry_write(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr, + UCHAR update_level, USHORT *unicode_name, UINT unicode_length) +{ + +UCHAR *work_ptr; +UCHAR *sector_base_ptr; +UINT status; +UINT i, j; +ULONG64 logical_sector; +ULONG relative_sector; +ULONG byte_offset; +ULONG cluster, next_cluster; +UINT total_entries; +UINT name_length; +UINT name_pos = 0; +UINT copy_size; +USHORT checksum = 0; +ULONG date_time; +UINT use_unicode = FX_FALSE; + +#ifdef FX_ENABLE_FAULT_TOLERANT +UCHAR *changed_ptr; /* Points to the directory entry that needs to be updated. */ +UINT changed_size; /* The amount of bytes changed */ +ULONG changed_offset; /* Offset from the beginning of the sector. */ +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + + + /* Check if we have unicode file name available. */ + if (unicode_name && unicode_length) + { + + /* Set use unicode flag. */ + use_unicode = FX_TRUE; + + /* Save the length of the name. */ + name_length = unicode_length; + } + else + { + + /* Calculate the length of the name from the name string. */ + name_length = _fx_utility_string_length_get(entry_ptr -> fx_dir_entry_name, FX_MAX_EX_FAT_NAME_LEN); + + /* Check if name is valid. */ + if (entry_ptr -> fx_dir_entry_name[name_length] != 0) + { + + /* Invalid name, return error. */ + return(FX_INVALID_NAME); + } + } + + /* Pickup the byte offset of the entry. */ + byte_offset = entry_ptr -> fx_dir_entry_byte_offset; + + /* Pickup the logical sector of the entry. */ + logical_sector = entry_ptr -> fx_dir_entry_log_sector; + + /* Calculate the cluster that this logical sector is in. */ + cluster = (ULONG)((logical_sector - media_ptr -> fx_media_data_sector_start) / (media_ptr -> fx_media_sectors_per_cluster)) + FX_FAT_ENTRY_START; + + /* Calculate the relative cluster. */ + relative_sector = (ULONG)(logical_sector - (((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)))); + + /* Read the sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Setup a pointer into the buffer. */ + sector_base_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer; + work_ptr = sector_base_ptr + (UINT)entry_ptr -> fx_dir_entry_byte_offset; + + /* Build file entry fields. */ + + /* Check if we need to update EntryType field. */ + if (update_level == UPDATE_FULL) + { + + /* Set EntryType field to file directory. */ + *work_ptr = FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY; + } + /* Check if we are request to delete the file. */ + else if (update_level == UPDATE_DELETE) + { + + /* Clear InUse bit. */ + *work_ptr &= 0x7f; + } + + /* Advance the pointer to the next field: SecondaryCount. */ + work_ptr++; + + /* Update SecondaryCount field. */ + if (update_level == UPDATE_FULL) + { + + /* Calculate the secondary entry count from file name length. */ + total_entries = 1 + (name_length + 14) / 15; + + /* Save SecondaryCount field. */ + *work_ptr = (UCHAR)total_entries; + } + else + { + + /* We are not performing a full update, read back the secondary entry count. */ + total_entries = *work_ptr; + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Skip SetChecksum field. */ + work_ptr += 2; + + /* Check if we need to update FileAttributes field. */ + if (update_level >= UPDATE_FILE) + { + + /* Write the file attributes field. */ + _fx_utility_16_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_attributes); + } + + /* Advance the pointer to the next field. */ + work_ptr += 2; + + /* Check if we need to perform full entry update. */ + if (update_level == UPDATE_FULL) + { + + /* Clear Reserved1 field. */ + _fx_utility_16_unsigned_write(work_ptr, 0); + } + + /* Advance the pointer to the next field. */ + work_ptr += 2; + + /* Check if we need to update the CreateTimestamp field. */ + if (update_level >= UPDATE_FILE) + { + + /* Calculate and update CreateTimestamp field. */ + date_time = ((ULONG)entry_ptr -> fx_dir_entry_created_date << 16) | + (ULONG)entry_ptr -> fx_dir_entry_created_time; + _fx_utility_32_unsigned_write(work_ptr, date_time); + } + + /* Advance the pointer to the next field. */ + work_ptr += 4; + + /* Check if we need to update LastModifiedTimestamp field. */ + if (update_level >= UPDATE_FILE) + { + + /* Calculate and update LastModifiedTimestamp field. */ + date_time = ((ULONG)entry_ptr -> fx_dir_entry_date << 16) | + (ULONG)entry_ptr -> fx_dir_entry_time; + _fx_utility_32_unsigned_write(work_ptr, date_time); + } + + /* Advance the pointer to the next field. */ + work_ptr += 4; + + /* Check if we need to update LastAccessedTimestamp field. */ + if (update_level >= UPDATE_FILE) + { + + /* Calculate and update LastAccessedTimestamp field. */ + date_time = ((ULONG)entry_ptr -> fx_dir_entry_date << 16) | + (ULONG)entry_ptr -> fx_dir_entry_time; /* use modified as accessed */ + _fx_utility_32_unsigned_write(work_ptr, date_time); + } + + /* Advance the pointer to the next field. */ + work_ptr += 4; + + /* Check if we need to update Create10msIncrement field. */ + if (update_level >= UPDATE_FILE) + { + + /* Update Create10msIncrement field. */ + *work_ptr = entry_ptr -> fx_dir_entry_created_time_ms; + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Check if we need to perform full entry update. */ + if (update_level >= UPDATE_FILE) + { + + /* 10ms increment field is not supported, clear this field. */ + *work_ptr = 0; + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Check if we need to perform full entry update. */ + if (update_level == UPDATE_FULL) + { + + /*CreateUtcOffset field is not supported, clear this field. */ + *work_ptr = 0; + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Check if we need to perform full entry update. */ + if (update_level >= UPDATE_FILE) + { + + /* LastModifiedUtcOffset field is not supported, clear this field. */ + *work_ptr = 0; + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Check if we need to perform full entry update. */ + if (update_level == UPDATE_FULL) + { + + /* LastModifiedUtcOffset field is not supported, clear this field. */ + *work_ptr = 0; /* Not supported. */ + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Clear Reserved2 field. */ + if (update_level == UPDATE_FULL) + { + + /* Loop to clear the reserved field. */ + for (i = 0; i < 7; ++i) + { + + /* Clear the reserved field. */ + *work_ptr = 0; + work_ptr++; + } + } + else + { + + /* Skip the reserved field. */ + work_ptr += 7; + } + + /* Calculate checksum. */ + work_ptr -= FX_DIR_ENTRY_SIZE; + + /* Loop to calculate the entry checksum. */ + for (j = 0; j < FX_DIR_ENTRY_SIZE; ++j) + { + + /* Skip the checksum field. */ + if ((j == 2) || (j == 3)) + { + + continue; + } + + /* Calculate the checksum using the algorithm described in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + checksum = (USHORT)(((checksum >> 1) | (checksum << 15)) + work_ptr[j]); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize variables for fault tolerant. */ + changed_ptr = work_ptr; + changed_offset = entry_ptr -> fx_dir_entry_byte_offset; + changed_size = 0; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Update second entries. */ + for (i = 0; i < total_entries; ++i) + { + + /* Advance the pointer and offset to next directory entry. */ + work_ptr += FX_DIR_ENTRY_SIZE; + byte_offset += FX_DIR_ENTRY_SIZE; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Update changed_size. */ + changed_size += FX_DIR_ENTRY_SIZE; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if the entry overlaps into the next sector. */ + if (byte_offset >= media_ptr -> fx_media_bytes_per_sector) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED)) + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_dir_log(media_ptr, logical_sector, changed_offset, changed_ptr, changed_size); + } + else +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + + /* Write current logical sector out. */ + status = _fx_utility_logical_sector_write(media_ptr, logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); + } + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Determine the next sector of the directory entry. */ + if (relative_sector < (media_ptr -> fx_media_sectors_per_cluster - 1)) + { + + /* More sectors in this cluster. */ + + /* Simply increment the logical sector. */ + logical_sector++; + + /* Increment the relative sector. */ + relative_sector++; + } + else + { + + /* We need to move to the next cluster. */ + if ((entry_ptr -> fx_dir_entry_dont_use_fat >> 1) & 1) /* Check parent dont_use_fat flag. */ + { + + /* FAT is not used, next cluster is after the current cluster. */ + next_cluster = cluster + 1; + } + else + { + + /* FAT is used, read FAT to get the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + } + + /* Copy next cluster to the current cluster. */ + cluster = next_cluster; + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster > FX_RESERVED_1_exFAT)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Setup the relative sector (this is zero for subsequent cluster. */ + relative_sector = 0; + + /* Calculate the next logical sector. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + } + + /* Read the sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Setup logical sector. */ + sector_base_ptr = media_ptr -> fx_media_memory_buffer; + + /* Setup a fresh byte offset. */ + byte_offset = 0; + + /* Setup a new pointer into the buffer. */ + work_ptr = sector_base_ptr; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize data for fault tolerant. */ + changed_ptr = work_ptr; + changed_size = 0; + changed_offset = 0; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + + /* Check if we are processing the first secondary entry. */ + if (i == 0) + { + + /* First sub entry is stream entry. */ + + /* Check if we need to perform full entry update. */ + if (update_level == UPDATE_FULL) + { + + /* Set the EntryType field to stream extension type. */ + *work_ptr = FX_EXFAT_DIR_ENTRY_TYPE_STREAM_EXTENSION; + } + else if (update_level == UPDATE_DELETE) + { + + /* Clear InUse bit. */ + *work_ptr &= 0x7f; + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Update GeneralSecondaryFlags field. */ + if (update_level >= UPDATE_STREAM) + { + + /* Check if FAT is used and the entry has associated cluster. */ + if ((entry_ptr -> fx_dir_entry_dont_use_fat & 1) && (entry_ptr -> fx_dir_entry_cluster != 0)) + { + + /* Set the flags to don't use FAT. */ + *work_ptr = 3; + } + else + { + + /* FAT is used. */ + *work_ptr = 1; + } + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Check if we need to perform full entry update. */ + if (update_level == UPDATE_FULL) + { + + /* Clear Reserved1 field. */ + *work_ptr = 0; + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Check if we need to update NameLength field. */ + if (update_level >= UPDATE_NAME) + { + + /* Update NameLength field. */ + *work_ptr = (UCHAR)name_length; + } + + /* Advance the pointer to the next field. */ + work_ptr++; + + /* Check if we need to update NameHash field. */ + if (update_level >= UPDATE_NAME) + { + /* Check if the supplied file name is in unicode format. */ + if (use_unicode) + { + + /* Update NameHash field. */ + _fx_utility_16_unsigned_write(work_ptr, _fx_utility_exFAT_unicode_name_hash_get((CHAR *)unicode_name, name_length)); + } + else + { + + /* Update NameHash field. */ + _fx_utility_16_unsigned_write(work_ptr, _fx_utility_exFAT_name_hash_get(entry_ptr -> fx_dir_entry_name)); + } + } + + /* Advance the pointer to the next field. */ + work_ptr += 2; + + /* Check if we need to perform full entry update. */ + if (update_level == UPDATE_FULL) + { + + /* Clear Reserved2 field. */ + _fx_utility_16_unsigned_write(work_ptr, 0); + } + + /* Advance the pointer to the next field. */ + work_ptr += 2; + + /* Check if we need to update ValidDataLength field. */ + if (update_level >= UPDATE_STREAM) + { + + /* Update ValidDataLength field. */ + _fx_utility_64_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_file_size); + } + + /* Advance the pointer to the next field. */ + work_ptr += 8; + + /* Check if we need to perform full entry update. */ + if (update_level == UPDATE_FULL) + { + + /* Clear Reserved3 field. */ + _fx_utility_32_unsigned_write(work_ptr, 0); + } + + /* Advance the pointer to the next field. */ + work_ptr += 4; + + /* Check if we need to update FirstCluster field. */ + if (update_level >= UPDATE_STREAM) + { + + /* Update FirstCluster field. */ + _fx_utility_32_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_cluster); + } + + /* Advance the pointer to the next field. */ + work_ptr += 4; + + /* Update DataLength fields. */ + if (update_level >= UPDATE_STREAM) + { + + /* Update DataLength fields. */ + _fx_utility_64_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_available_file_size); + _fx_utility_64_unsigned_write(work_ptr, entry_ptr -> fx_dir_entry_file_size); + } + + /* Advance the pointer to the next field. */ + work_ptr += 8; + } + else + { + + /* Check if we are requested to delete the entries. */ + if (update_level == UPDATE_DELETE) + { + + /* Check the directory entry type. */ + if ((*work_ptr != FX_EXFAT_DIR_ENTRY_TYPE_FILE_NAME) && (*work_ptr != FX_EXFAT_DIR_ENTRY_TYPE_STREAM_EXTENSION)) + { + + /* Unknown secondary, we should free used clusters if any. */ + status = _fx_utility_exFAT_cluster_free(media_ptr, work_ptr); + if (status != FX_SUCCESS) + { + + /* Return completion status. */ + return(status); + } + } + + /* Clear InUse bit. */ + *work_ptr &= 0x7f; + work_ptr += FX_DIR_ENTRY_SIZE; + } + /* Check if we need to update the file name. */ + else if ((update_level == UPDATE_FULL) || + ((update_level == UPDATE_NAME) && (*work_ptr == FX_EXFAT_DIR_ENTRY_TYPE_FILE_NAME))) + { + + /* Build Name entry. */ + + /* Update EntryType field. */ + *work_ptr = FX_EXFAT_DIR_ENTRY_TYPE_FILE_NAME; + work_ptr++; + + /* Update GeneralSecondaryFlags field. */ + *work_ptr = 0; + work_ptr++; + + /* Update FileName field. */ + + /* One name entry can hold up to 15 characters. Set how many characters to copy. */ + if (name_length > 15) + { + copy_size = 15; + } + else + { + copy_size = name_length; + } + + /* Check if the supplied file name is in unicode format. */ + if (use_unicode) + { + + /* Loop to copy the unicode file name. */ + for (j = 0; j < copy_size; ++j) + { + + /* Copy unicode file name to the file name entry. */ + _fx_utility_16_unsigned_write(work_ptr, (UINT)unicode_name[name_pos++]); + work_ptr += 2; + } + } + else + { + + /* Loop to copy non-unicode file name. */ + for (j = 0; j < copy_size; ++j) + { + + /* Copy and convert non-unicode file name. */ + _fx_utility_16_unsigned_write(work_ptr, (UINT)entry_ptr -> fx_dir_entry_name[name_pos++]); + work_ptr += 2; + } + } + + /* Loop to clear remaining bytes. */ + for (j = copy_size; j < 15; ++j) + { + + /* Clear the remaining bytes. */ + _fx_utility_16_unsigned_write(work_ptr, 0); + work_ptr += 2; + } + + /* Modify the name_length to indicate the remaining length. */ + name_length -= copy_size; + } + else + { + + /* The entry does need to be updated, move to next entry. */ + work_ptr += FX_DIR_ENTRY_SIZE; + } + } + + /* Set pointer back for checksum calculation. */ + work_ptr -= FX_DIR_ENTRY_SIZE; + + /* Loop to calculate the checksum. */ + for (j = 0; j < FX_DIR_ENTRY_SIZE; ++j) + { + + /* Calculate the checksum. */ + /* Right rotate the checksum by one bit position and add the data. */ + checksum = (USHORT)(((checksum >> 1) | (checksum << 15)) + work_ptr[j]); + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Update changed_size. */ + changed_size += FX_DIR_ENTRY_SIZE; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Go back to file entry. */ + if (byte_offset < total_entries * FX_DIR_ENTRY_SIZE) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED)) + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_dir_log(media_ptr, logical_sector, changed_offset, changed_ptr, changed_size); + } + else +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + + /* Write current logical sector out. */ + status = _fx_utility_logical_sector_write(media_ptr, logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); + } + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Pickup the byte offset of the entry. */ + byte_offset = entry_ptr -> fx_dir_entry_byte_offset; + + /* Pickup the logical sector of the entry. */ + logical_sector = entry_ptr -> fx_dir_entry_log_sector; + + /* Calculate the cluster that this logical sector is in. */ + cluster = (ULONG)((logical_sector - media_ptr -> fx_media_data_sector_start) / (media_ptr -> fx_media_sectors_per_cluster)) + FX_FAT_ENTRY_START; + + /* Calculate the relative cluster. */ + relative_sector = (ULONG)(logical_sector - (((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)))); + + /* Read the sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Setup logical sector. */ + sector_base_ptr = media_ptr -> fx_media_memory_buffer; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize data for fault tolerant. */ + /* A log for checksum. */ + changed_ptr = sector_base_ptr + byte_offset + 2; + changed_size = 2; + changed_offset = byte_offset + 2; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + else + { + + /* The directory entries are not crossing sector boundary, just adjust the pointer to go back to the first entry. */ + byte_offset -= total_entries * FX_DIR_ENTRY_SIZE; + } + + /* Setup work pointer to the directory entry. */ + work_ptr = sector_base_ptr + byte_offset; + + /* Store SetChecksum field. */ + work_ptr += 2; + _fx_utility_16_unsigned_write(work_ptr, checksum); + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED)) + { + + if (changed_size == 2) + { + + /* Only checksum. */ + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_checksum_log(media_ptr, logical_sector, changed_offset, checksum); + } + else + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_dir_log(media_ptr, logical_sector, changed_offset, changed_ptr, changed_size); + } + } + else +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + + /* Write current logical sector out. */ + status = _fx_utility_logical_sector_write(media_ptr, logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); + } + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Check if there is a default path. */ + if (media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name[0]) + { + + /* Check default path directory was updated. */ + if ((media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_log_sector == + entry_ptr -> fx_dir_entry_log_sector) && + (media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_byte_offset == + entry_ptr -> fx_dir_entry_byte_offset)) + { + + /* Update default path. */ + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_file_size = + entry_ptr -> fx_dir_entry_file_size; + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_available_file_size = + entry_ptr -> fx_dir_entry_available_file_size; + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_dont_use_fat = + entry_ptr -> fx_dir_entry_dont_use_fat; + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_cluster = + entry_ptr -> fx_dir_entry_cluster; + } + } + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Determine if there is a previously found directory entry in the directory + search cache. */ + if (media_ptr -> fx_media_last_found_name[0]) + { + + /* Determine if the cached search directory entry matches the directory entry being + written. */ + if ((entry_ptr -> fx_dir_entry_log_sector == media_ptr -> fx_media_last_found_entry.fx_dir_entry_log_sector) && + (entry_ptr -> fx_dir_entry_byte_offset == media_ptr -> fx_media_last_found_entry.fx_dir_entry_byte_offset)) + { + + /* Yes, this entry is the same as the one currently in the directory search cache. + Update various fields in the directory search cache with the information being + written now. */ + media_ptr -> fx_media_last_found_entry.fx_dir_entry_cluster = entry_ptr -> fx_dir_entry_cluster; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_file_size = entry_ptr -> fx_dir_entry_file_size; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_attributes = entry_ptr -> fx_dir_entry_attributes; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_time = entry_ptr -> fx_dir_entry_time; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_date = entry_ptr -> fx_dir_entry_date; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_reserved = entry_ptr -> fx_dir_entry_reserved; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_created_time_ms = entry_ptr -> fx_dir_entry_created_time_ms; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_created_time = entry_ptr -> fx_dir_entry_created_time; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_created_date = entry_ptr -> fx_dir_entry_created_date; + + media_ptr -> fx_media_last_found_entry.fx_dir_entry_dont_use_fat = entry_ptr -> fx_dir_entry_dont_use_fat; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_type = entry_ptr -> fx_dir_entry_type; + media_ptr -> fx_media_last_found_entry.fx_dir_entry_available_file_size = entry_ptr -> fx_dir_entry_available_file_size; + } + } +#endif + + /* Return success to the caller. */ + return(status); +} + +#endif + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c b/src/Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c new file mode 100644 index 00000000..a923e2f5 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_first_entry_find.c @@ -0,0 +1,136 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_first_entry_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the first directory entry of the current */ +/* working directory. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Destination for directory */ +/* name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_next_entry_find Find next directory entry */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_first_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_first_entry_finds++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_FIRST_ENTRY_FIND, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Determine if a local path is in effect at this point. */ +#ifndef FX_NO_LOCAL_PATH + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* Yes, there is a local path. Set the current entry to zero. */ + ((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_current_entry = 0; + } + else + { + + /* Use global default directory. Set the current entry to 0 in + order to pickup the first entry. */ + media_ptr -> fx_media_default_path.fx_path_current_entry = 0; + } +#else + + /* Set the current entry to 0 in order to pickup the first entry. */ + media_ptr -> fx_media_default_path.fx_path_current_entry = 0; +#endif + + /* Release media protection. */ + FX_UNPROTECT + + /* Call the next directory entry to pickup the first entry. */ + status = _fx_directory_next_entry_find(media_ptr, directory_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c b/src/Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c new file mode 100644 index 00000000..900a1f9c --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_first_full_entry_find.c @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_first_full_entry_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the first directory entry of the current */ +/* working directory and selected information about the entry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Destination for directory */ +/* name */ +/* attributes Destination for attributes */ +/* size Destination for size */ +/* year Destination for year */ +/* month Destination for month */ +/* day Destination for day */ +/* hour Destination for hour */ +/* minute Destination for minute */ +/* second Destination for second */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_next_full_entry_find Find next full directory entry*/ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_first_full_entry_find(FX_MEDIA *media_ptr, + CHAR *directory_name, UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second) +{ + +UINT status; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_first_full_entry_finds++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_FIRST_FULL_ENTRY_FIND, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Determine if a local path is in effect at this point. */ +#ifndef FX_NO_LOCAL_PATH + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* Yes, there is a local path. Set the current entry to zero. */ + ((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_current_entry = 0; + } + else + { + + /* Use global default directory. Set the current entry to 0 in + order to pickup the first entry. */ + media_ptr -> fx_media_default_path.fx_path_current_entry = 0; + } +#else + + /* Set the current entry to 0 in order to pickup the first entry. */ + media_ptr -> fx_media_default_path.fx_path_current_entry = 0; +#endif + + /* Release media protection. */ + FX_UNPROTECT + + /* Call the next directory full entry service to pickup the first entry. */ + status = _fx_directory_next_full_entry_find(media_ptr, directory_name, attributes, + size, year, month, day, hour, minute, second); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_free_search.c b/src/Middlewares/ST/filex/common/src/fx_directory_free_search.c new file mode 100644 index 00000000..7427930d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_free_search.c @@ -0,0 +1,778 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_free_search PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function searches the media for a free directory entry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_ptr Pointer to directory to */ +/* search in */ +/* entry_ptr Pointer to directory entry */ +/* record */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_read Read entries from directory */ +/* _fx_directory_entry_write Write entries to directory */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_utility_logical_sector_flush Flush logical sector cache */ +/* _fx_utility_logical_sector_read Read logical sector */ +/* _fx_utility_logical_sector_write Write logical sector */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_free_search(FX_MEDIA *media_ptr, FX_DIR_ENTRY *directory_ptr, FX_DIR_ENTRY *entry_ptr) +{ + +ULONG i, j; +UCHAR *work_ptr; +UINT status, total_entries; +ULONG entry_sector, entry_offset; +ULONG FAT_index, FAT_value; +ULONG cluster, total_clusters, clusters_needed; +ULONG first_new_cluster, last_cluster, clusters; +ULONG directory_index; +ULONG directory_entries; +ULONG logical_sector; +FX_DIR_ENTRY *search_dir_ptr; +ULONG free_entry_start; +UINT sectors; + +FX_INT_SAVE_AREA + + +#ifdef FX_ENABLE_EXFAT + /* Check if media format is exFAT. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Call exFAT specific function. */ + return(_fx_directory_exFAT_free_search(media_ptr, directory_ptr, entry_ptr)); + } +#endif /* FX_ENABLE_EXFAT */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of directory free entry search requests. */ + media_ptr -> fx_media_directory_free_searches++; +#endif + + /* Initialize the entry sector values. */ + entry_sector = entry_offset = 0; + + /* Set the long file name flag to false. */ + entry_ptr -> fx_dir_entry_long_name_present = 0; + + /* Are there leading dots? */ + if (entry_ptr -> fx_dir_entry_name[0] == '.') + { + + /* Is there more than 1 dot? */ + if (entry_ptr -> fx_dir_entry_name[1] == '.') + { + /* Yes, consider the name invalid. */ + return(FX_INVALID_NAME); + } + } + + /* Determine if a long file name is present. */ + for (i = 0, j = 0; entry_ptr -> fx_dir_entry_name[i]; i++) + { + + /* Check for upper-case characters. */ + if ((entry_ptr -> fx_dir_entry_name[i] >= 'A') && (entry_ptr -> fx_dir_entry_name[i] <= 'Z')) + { + continue; + } + /* Check for numeric characters. */ + else if ((entry_ptr -> fx_dir_entry_name[i] >= '0') && (entry_ptr -> fx_dir_entry_name[i] <= '9')) + { + continue; + } + /* Check for any lower-case characters. */ + else if ((entry_ptr -> fx_dir_entry_name[i] >= 'a') && (entry_ptr -> fx_dir_entry_name[i] <= 'z')) + { + entry_ptr -> fx_dir_entry_long_name_present = 1; + } + /* Check for a space in the middle of the name. */ + else if (entry_ptr -> fx_dir_entry_name[i] == ' ') + { + entry_ptr -> fx_dir_entry_long_name_present = 1; + } + /* Check for a dot in the name. */ + else if (entry_ptr -> fx_dir_entry_name[i] == '.') + { + /* Determine if this is the first dot detected. */ + if (j == 0) + { + /* First dot, remember where it was. */ + j = i; + + /* Determine if this is a leading dot. */ + if (i == 0) + { + + /* Leading dot detected, treat as a long filename. */ + entry_ptr -> fx_dir_entry_long_name_present = 1; + } + } + else + { + /* Second dot detected, must have a long file name. */ + entry_ptr -> fx_dir_entry_long_name_present = 1; + } + } + /* Check for a special 0xE5 character. */ + else if ((UCHAR)entry_ptr -> fx_dir_entry_name[i] == (UCHAR)0xE5) + { + entry_ptr -> fx_dir_entry_long_name_present = 1; + } + /* Check for code point value greater than 127. */ + else if ((UCHAR)entry_ptr -> fx_dir_entry_name[i] > (UCHAR)127) + { + continue; + } + /* Check for any special characters. */ + else if ((entry_ptr -> fx_dir_entry_name[i] == '~') || + (entry_ptr -> fx_dir_entry_name[i] == '-') || + (entry_ptr -> fx_dir_entry_name[i] == '_') || + (entry_ptr -> fx_dir_entry_name[i] == '}') || + (entry_ptr -> fx_dir_entry_name[i] == '{') || + (entry_ptr -> fx_dir_entry_name[i] == '(') || + (entry_ptr -> fx_dir_entry_name[i] == ')') || + (entry_ptr -> fx_dir_entry_name[i] == '`') || + (entry_ptr -> fx_dir_entry_name[i] == '\'') || + (entry_ptr -> fx_dir_entry_name[i] == '!') || + (entry_ptr -> fx_dir_entry_name[i] == '#') || + (entry_ptr -> fx_dir_entry_name[i] == '$') || + (entry_ptr -> fx_dir_entry_name[i] == '&') || + (entry_ptr -> fx_dir_entry_name[i] == '@') || + (entry_ptr -> fx_dir_entry_name[i] == '^') || + (entry_ptr -> fx_dir_entry_name[i] == '%')) + { + continue; + } + /* Check for long filename special characters. */ + else if ((entry_ptr -> fx_dir_entry_name[i] == '+') || + (entry_ptr -> fx_dir_entry_name[i] == ',') || + (entry_ptr -> fx_dir_entry_name[i] == ';') || + (entry_ptr -> fx_dir_entry_name[i] == '=') || + (entry_ptr -> fx_dir_entry_name[i] == '[') || + (entry_ptr -> fx_dir_entry_name[i] == ']')) + { + entry_ptr -> fx_dir_entry_long_name_present = 1; + } + /* Something is wrong with the supplied name. */ + else + { + return(FX_INVALID_NAME); + } + } + + /* Determine if a dot was found. */ + if (j != 0) + { + + /* Yes, Determine if the extension exceeds a 3 character extension. */ + if ((i - j) > 4) + { + + /* Yes, long file name is present. */ + entry_ptr -> fx_dir_entry_long_name_present = 1; + } + } + + /* Calculate the total entries needed. */ + if ((i <= 12) && (entry_ptr -> fx_dir_entry_long_name_present == 0)) + { + + /* Initialize the total entries to 1. */ + total_entries = 1; + + /* Check for special instance of long file name. */ + if ((j >= 9) || ((i - j) >= 9)) + { + + /* The dot is after 8 character or there is no dot and the name + is greater than 8 character. */ + entry_ptr -> fx_dir_entry_long_name_present = 1; + total_entries = 2; + } + } + else + { + + /* Long file name is present, calculate how many entries are needed + to represent it. */ + if (i % 13 == 0) + { + /* Exact fit, just add one for the 8.3 short name. */ + total_entries = i / 13 + 1; + } + else + { + /* Non-exact fit, add two for 8.3 short name and overlap. */ + total_entries = i / 13 + 2; + } + } + + /* Determine if the search is in the root directory or in a + sub-directory. Note: the directory search function clears the + first character of the name for the root directory. */ + if (directory_ptr -> fx_dir_entry_name[0]) + { + + /* Search for a free entry in a sub-directory. */ + + /* Pickup the number of entries in this directory. This was placed + into the unused file size field. */ + directory_entries = (ULONG)directory_ptr -> fx_dir_entry_file_size; + + /* Point the search directory pointer to this entry. */ + search_dir_ptr = directory_ptr; + + /* Ensure that the search directory's last search cluster is cleared. */ + search_dir_ptr -> fx_dir_entry_last_search_cluster = 0; + + /* Set the initial index to 2, since the first two directory entries are + always allocated. */ + directory_index = 2; + } + else + { + + /* Find a free entry in the root directory. */ + + /* Setup the number of directory entries. */ + directory_entries = (ULONG)media_ptr -> fx_media_root_directory_entries; + + /* Set the search pointer to NULL since we are working off of the + root directory. */ + search_dir_ptr = FX_NULL; + + /* Set the initial index to 0, since the first entry of the root directory is valid. */ + directory_index = 0; + } + + /* Loop through entries in the search directory. Yes, this is a + linear search! */ + free_entry_start = directory_entries; + do + { + + /* Read an entry from the directory. */ + status = _fx_directory_entry_read(media_ptr, search_dir_ptr, &directory_index, entry_ptr); + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Determine if this is an empty entry. */ + if ((((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_FREE) && (entry_ptr -> fx_dir_entry_short_name[0] == 0)) || + ((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_DONE)) + { + + /* Determine how many entries are needed. */ + if (total_entries > 1) + { + + /* Multiple entries are needed for long file names. Mark this + entry as free. */ + if (entry_ptr -> fx_dir_entry_name[0] == FX_DIR_ENTRY_DONE) + { + + entry_ptr -> fx_dir_entry_long_name_present = 0; + entry_ptr -> fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + entry_ptr -> fx_dir_entry_name[1] = (CHAR)0; + + /* Write out the directory entry. */ + status = _fx_directory_entry_write(media_ptr, entry_ptr); + if(status != FX_SUCCESS) + { + return(status); + } + + /* Note that for long names we need to avoid holes in the middle, + i.e. entries must be logically contiguous. */ + } + } + + /* Determine if we are at the first free entry. */ + if (free_entry_start == directory_entries) + { + + /* Remember the start of the free entry. */ + free_entry_start = directory_index; + entry_sector = (ULONG)entry_ptr -> fx_dir_entry_log_sector; + entry_offset = entry_ptr -> fx_dir_entry_byte_offset; + } + + /* Determine if there are enough free entries to satisfy the request. */ + if ((directory_index - free_entry_start + 1) >= total_entries) + { + + /* Found an empty slot. Most pertinent information is already + in the entry structure. */ + + /* Setup the the sector and the offset. */ + entry_ptr -> fx_dir_entry_log_sector = entry_sector; + entry_ptr -> fx_dir_entry_byte_offset = entry_offset; + + /* Initialize the additional directory entries. */ + entry_ptr -> fx_dir_entry_reserved = 0; + entry_ptr -> fx_dir_entry_created_time_ms = 0; + + /* Lockout interrupts for time/date access. */ + FX_DISABLE_INTS + + entry_ptr -> fx_dir_entry_created_time = _fx_system_time; + entry_ptr -> fx_dir_entry_created_date = _fx_system_date; + entry_ptr -> fx_dir_entry_last_accessed_date = _fx_system_date; + + /* Restore interrupts. */ + FX_RESTORE_INTS + + /* Determine if a long file name is present. */ + if (total_entries == 1) + { + entry_ptr -> fx_dir_entry_long_name_present = 0; + } + else + { + entry_ptr -> fx_dir_entry_long_name_present = 1; + } + + /* Return a successful completion. */ + return(FX_SUCCESS); + } + } + else + { + + /* Reset the free entry start. */ + free_entry_start = directory_entries; + } + + /* Move to the next entry. */ + directory_index++; + + /* Determine if we have exceeded the number of entries in the current directory. */ + if (directory_index >= directory_entries) + { + + /* Calculate how many sectors we need for the new directory entry. */ + sectors = ((total_entries * FX_DIR_ENTRY_SIZE) + (media_ptr -> fx_media_bytes_per_sector - 1))/ + media_ptr -> fx_media_bytes_per_sector; + + /* Now calculate how many clusters we need for the new directory entry. */ + clusters_needed = (sectors + (media_ptr -> fx_media_sectors_per_cluster - 1)) / media_ptr -> fx_media_sectors_per_cluster; + + /* Not enough empty entries were found. If the specified directory is a sub-directory, + attempt to allocate another cluster to it. */ + if (((search_dir_ptr) || (media_ptr -> fx_media_32_bit_FAT)) && (media_ptr -> fx_media_available_clusters > clusters_needed)) + { + + /* Search for the additional clusters we need. */ + first_new_cluster = 0; + total_clusters = media_ptr -> fx_media_total_clusters; + last_cluster = 0; + FAT_index = media_ptr -> fx_media_cluster_search_start; + clusters = clusters_needed; + + /* Loop to find the needed clusters. */ + while (clusters) + { + + /* Decrease the cluster count. */ + clusters--; + + /* Loop to find the first available cluster. */ + do + { + + /* Make sure we stop looking after one pass through the FAT table. */ + if (!total_clusters) + { + + /* Something is wrong with the media - the desired clusters were + not found in the FAT table. */ + return(FX_NO_MORE_SPACE); + } + + /* Read FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, FAT_index, &FAT_value); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + + /* Decrement the total cluster count. */ + total_clusters--; + + /* Determine if the FAT entry is free. */ + if (FAT_value == FX_FREE_CLUSTER) + { + + /* Move cluster search pointer forward. */ + media_ptr -> fx_media_cluster_search_start = FAT_index + 1; + + /* Determine if this needs to be wrapped. */ + if (media_ptr -> fx_media_cluster_search_start >= (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Wrap the search to the beginning FAT entry. */ + media_ptr -> fx_media_cluster_search_start = FX_FAT_ENTRY_START; + } + + /* Break this loop. */ + break; + } + else + { + + /* FAT entry is not free... Advance the FAT index. */ + FAT_index++; + + /* Determine if we need to wrap the FAT index around. */ + if (FAT_index >= (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Wrap the search to the beginning FAT entry. */ + FAT_index = FX_FAT_ENTRY_START; + } + } + } while (FX_TRUE); + + /* We found an available cluster. We now need to clear all of entries in + each of the cluster's sectors. */ + + /* Calculate the logical sector of this cluster. */ + logical_sector = ((ULONG) media_ptr -> fx_media_data_sector_start) + + ((((ULONG) FAT_index) - FX_FAT_ENTRY_START) * + ((ULONG) media_ptr -> fx_media_sectors_per_cluster)); + + /* Pickup the number of sectors for the next directory cluster. */ + sectors = media_ptr -> fx_media_sectors_per_cluster; + + /* Read the logical sector just for cache reasons. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Clear the entire first sector of the new sub-directory cluster. */ + work_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer; + i = 0; + while (i < media_ptr -> fx_media_bytes_per_sector) + { + + /* Clear 4 bytes. */ + *((ULONG *)work_ptr) = (ULONG)0; + + /* Increment pointer. */ + work_ptr = work_ptr + sizeof(ULONG); + + /* Increment counter. */ + i = i + (ULONG)sizeof(ULONG); + } + + /* Write the logical sector to ensure the zeros are written. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Return the error code. */ + return(status); + } + + /* Determine if there are more sectors to clear in the first cluster of the new + sub-directory. */ + if (sectors > 1) + { + + /* Yes, invalidate all cached sectors that are contained in the newly allocated first + cluster of the directory. */ + + /* Flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, (ULONG64) (logical_sector + 1), (ULONG64) (sectors - 1), FX_TRUE); + + /* Determine if the flush was successful. */ + if (status != FX_SUCCESS) + { + + /* Return the error code. */ + return(status); + } + + /* Clear all additional sectors of new sub-directory. */ + sectors--; + while (sectors) + { + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build Write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector + ((ULONG)sectors); + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + + /* Set the system write flag since we are writing a directory sector. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, ((ULONG)logical_sector) + ((ULONG)sectors), 1, media_ptr -> fx_media_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if an error occurred. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Return error code. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Decrease the number of sectors to clear. */ + sectors--; + } + } + + /* Determine if we have found the first new cluster yet. */ + if (first_new_cluster == 0) + { + + /* Remember the first new cluster. */ + first_new_cluster = FAT_index; + } + + /* Check for a valid last cluster to link. */ + if (last_cluster) + { + + /* Normal condition - link the last cluster with the new + found cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, FAT_index); + + /* Check for a bad FAT write status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + } + + /* Otherwise, remember the new FAT index as the last. */ + last_cluster = FAT_index; + + /* Move to the next FAT entry. */ + FAT_index = media_ptr -> fx_media_cluster_search_start; + } + + /* Place an end-of-file marker on the last cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, media_ptr -> fx_media_fat_last); + + /* Check for a bad FAT write status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + +#ifdef FX_FAULT_TOLERANT + + /* Ensure the new FAT chain is properly written to the media. */ + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + + /* Now the new cluster needs to be linked to the sub-directory. */ + if (search_dir_ptr) + { + cluster = search_dir_ptr -> fx_dir_entry_cluster; + } + else + { + cluster = media_ptr -> fx_media_root_cluster_32; + } + + /* Initialize loop variables. */ + last_cluster = 0; + i = 0; + + /* Follow the link of FAT entries. */ + while (cluster < media_ptr -> fx_media_fat_reserved) + { + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &FAT_value); + i++; + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Determine if the FAT read was invalid. */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster == FAT_value) || (i > media_ptr -> fx_media_total_clusters)) + { + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + /* Save the last valid cluster. */ + last_cluster = cluster; + + /* Setup for the next cluster. */ + cluster = FAT_value; + } + + /* Decrease the available clusters in the media. */ + media_ptr -> fx_media_available_clusters = media_ptr -> fx_media_available_clusters - clusters_needed; + + /* Increase the number of directory entries. */ + directory_entries = directory_entries + ((clusters_needed * media_ptr -> fx_media_sectors_per_cluster) * media_ptr -> fx_media_bytes_per_sector) / FX_DIR_ENTRY_SIZE; + + /* Determine if we need to reset the free entry start since we changed the + number of directory entries. If the last entry was not free, then we + should definitely reset the free entry start. */ + if (!(((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR) FX_DIR_ENTRY_FREE) && (entry_ptr -> fx_dir_entry_short_name[0] == 0))) + { + + /* Reset the free entry start to indicate we haven't found a starting free entry yet. */ + free_entry_start = directory_entries; + } + + /* Update the directory size field. */ + directory_ptr -> fx_dir_entry_file_size = directory_entries; + + /* Defer the update of the FAT entry and the last cluster of the current + directory entry until after the new cluster is initialized and written out. */ + + /* Determine if a FAT32 is present. */ + if ((media_ptr -> fx_media_32_bit_FAT) && (search_dir_ptr == FX_NULL)) + { + + /* Change root directory entry count - FAT32 has a variable sized root directory. */ + media_ptr -> fx_media_root_directory_entries = directory_entries; + } + + /* At this point, link up the last cluster with the new cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, first_new_cluster); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + } + } + } while (directory_index < directory_entries); + + /* Return FX_NO_MORE_SPACE status to the caller. */ + return(FX_NO_MORE_SPACE); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_information_get.c b/src/Middlewares/ST/filex/common/src/fx_directory_information_get.c new file mode 100644 index 00000000..bed44050 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_information_get.c @@ -0,0 +1,235 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_information_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified directory name. */ +/* If found, the complete file parameters are placed in all non-NULL */ +/* return parameters. If the file name is not found, the appropriate */ +/* error code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name pointer */ +/* attributes Pointer to attributes */ +/* size Pointer to size */ +/* year Pointer to year */ +/* month Pointer to month */ +/* day Pointer to day */ +/* hour Pointer to hour */ +/* minute Pointer to minute */ +/* second Pointer to second */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_information_get(FX_MEDIA *media_ptr, CHAR *directory_name, + UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, + UINT *hour, UINT *minute, UINT *second) +{ + +UINT status; +FX_DIR_ENTRY dir_entry; +ULONG open_count; +FX_FILE *search_ptr; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_information_gets++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_INFORMATION_GET, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied directory name. */ + status = _fx_directory_search(media_ptr, directory_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check the list of open files for others open for writing. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Look at each opened file to see if the same file is opened + for writing. */ + if ((search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == dir_entry.fx_dir_entry_byte_offset) && + (search_ptr -> fx_file_open_mode)) + { + + /* The file has been opened for writing by a previous call. Use the information used by + the writer instead of what is currently on the media. */ + _fx_utility_memory_copy((UCHAR *)&search_ptr -> fx_file_dir_entry, (UCHAR *)&dir_entry, sizeof(FX_DIR_ENTRY)); /* Use case of memcpy is verified. */ + break; + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } + + /* Check to see if attributes are required. */ + if (attributes) + { + + /* Pickup the attributes. */ + *attributes = dir_entry.fx_dir_entry_attributes; + } + + /* Check to see if the size is required. */ + if (size) + { + + /* Pickup the size. */ + *size = (ULONG)dir_entry.fx_dir_entry_file_size; + } + + /* Check to see if the year is required. */ + if (year) + { + + /* Pickup the year. */ + *year = ((dir_entry.fx_dir_entry_date >> FX_YEAR_SHIFT) & FX_YEAR_MASK) + + FX_BASE_YEAR; + } + + /* Check to see if the month is required. */ + if (month) + { + + /* Pickup the month. */ + *month = (dir_entry.fx_dir_entry_date >> FX_MONTH_SHIFT) & FX_MONTH_MASK; + } + + /* Check to see if the day is required. */ + if (day) + { + + /* Pickup the day. */ + *day = dir_entry.fx_dir_entry_date & FX_DAY_MASK; + } + + /* Check to see if the hour is required. */ + if (hour) + { + + /* Pickup the hour. */ + *hour = (dir_entry.fx_dir_entry_time >> FX_HOUR_SHIFT) & FX_HOUR_MASK; + } + + /* Check to see if the minute is required. */ + if (minute) + { + + /* Pickup the minute. */ + *minute = (dir_entry.fx_dir_entry_time >> FX_MINUTE_SHIFT) & FX_MINUTE_MASK; + } + + /* Check to see if the second is required. */ + if (second) + { + + /* Pickup the second. */ + *second = (dir_entry.fx_dir_entry_time & FX_SECOND_MASK) * 2; + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Directory information get is complete, return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c new file mode 100644 index 00000000..c95db417 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_clear.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_local_path_clear PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function clears the local default directory of the media so */ +/* any path relative operations will start using the media's global */ +/* default path again. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_local_path_clear(FX_MEDIA *media_ptr) +{ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_local_path_clears++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_NO_LOCAL_PATH + + /* Error, return to caller. */ + return(FX_NOT_IMPLEMENTED); +#else + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_LOCAL_PATH_CLEAR, media_ptr, 0, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Clear this thread's local path pointer. */ + _tx_thread_current_ptr -> tx_thread_filex_ptr = FX_NULL; + + /* Local default directory clear is complete, return status. */ + return(FX_SUCCESS); +#endif +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_local_path_get.c b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_get.c new file mode 100644 index 00000000..c678d6bd --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_get.c @@ -0,0 +1,129 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_local_path_get PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns a pointer to the local default directory */ +/* for this thread. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* return_path_name Return local path name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_local_path_get(FX_MEDIA *media_ptr, CHAR **return_path_name) +{ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_local_path_gets++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_NO_LOCAL_PATH + + FX_PARAMETER_NOT_USED(return_path_name); + + /* Error, return to caller. */ + return(FX_NOT_IMPLEMENTED); +#else + + /* Determine if there is a local path. */ + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* Return a pointer to the current local directory path string. */ + *return_path_name = ((FX_LOCAL_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_string; + } + else + { + + /* Just set the return value to FX_NULL to indicate there is no + local path setup. */ + *return_path_name = FX_NULL; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_LOCAL_PATH_GET, media_ptr, return_path_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Local default directory has been returned, return status. */ + return(FX_SUCCESS); +#endif +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c new file mode 100644 index 00000000..bce29a51 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_get_copy.c @@ -0,0 +1,123 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_local_path_get_copy PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function copies the local default directory for this thread */ +/* into the specified buffer. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* return_path_name_buffer Destination buffer for name */ +/* return_path_name_buffer_size Size of buffer pointed to by */ +/* return_path_name_buffer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_local_path_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size) +{ + +UINT status; +CHAR *return_path_name; +UINT path_name_length_with_null_terminator; + + + /* Get the pointer to the path. */ + status = _fx_directory_local_path_get(media_ptr, &return_path_name); + if (status == FX_SUCCESS) + { + + /* Was a path set? */ + if (return_path_name != FX_NULL) + { + + /* Get the length of the path. */ + path_name_length_with_null_terminator = _fx_utility_string_length_get(return_path_name, FX_MAXIMUM_PATH) + 1; + + /* Can it fit in the user's buffer? */ + if (path_name_length_with_null_terminator <= return_path_name_buffer_size) + { + + /* Copy the path name into the user's buffer. */ + _fx_utility_memory_copy((UCHAR *) return_path_name, (UCHAR *) return_path_name_buffer, path_name_length_with_null_terminator); /* Use case of memcpy is verified. */ + } + else + { + + /* Buffer is too small. Return error. */ + return(FX_BUFFER_ERROR); + } + } + else + { + + /* Set zero-length string. */ + return_path_name_buffer[0] = '\0'; + } + } + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c new file mode 100644 index 00000000..d7a3b062 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_restore.c @@ -0,0 +1,117 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_local_path_restore PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function restores the local default directory of the media to */ +/* the previous path specified by the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* local_path_ptr Local path control block ptr */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_local_path_restore(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr) +{ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_local_path_restores++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_NO_LOCAL_PATH + + FX_PARAMETER_NOT_USED(local_path_ptr); + + /* Error, return to caller. */ + return(FX_NOT_IMPLEMENTED); +#else + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_LOCAL_PATH_RESTORE, media_ptr, local_path_ptr, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Setup thread control block to use this local path pointer. */ + _tx_thread_current_ptr -> tx_thread_filex_ptr = (VOID *)local_path_ptr; + + /* Default directory restore is complete, return status. */ + return(FX_SUCCESS); +#endif +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_local_path_set.c b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_set.c new file mode 100644 index 00000000..fb7a9c92 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_local_path_set.c @@ -0,0 +1,451 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_local_path_set PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the local default directory of the media to the */ +/* path specified by the caller. If this path is not found, an error */ +/* code is returned. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* local_path Local path control block ptr */ +/* new_path_name New path to set current local */ +/* working directory to */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the directory name */ +/* in the directory structure */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_local_path_set(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr, CHAR *new_path_name) +{ + +#ifndef FX_NO_LOCAL_PATH +UINT status; +CHAR *path_string_ptr; +UINT path_string_capacity; +FX_PATH *path_ptr; +UINT i, j; +#endif +FX_DIR_ENTRY dir_entry; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_local_path_sets++; +#endif + + /* Setup pointer to a name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Setup the local path name buffer pointer. */ + local_path_ptr -> fx_path_directory.fx_dir_entry_name = local_path_ptr -> fx_path_name_buffer; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = (CHAR)0; + + /* Clear the long name string. */ + dir_entry.fx_dir_entry_name[0] = (CHAR)0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_NO_LOCAL_PATH + + FX_PARAMETER_NOT_USED(new_path_name); + + /* Error, return to caller. */ + return(FX_NOT_IMPLEMENTED); +#else + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_LOCAL_PATH_SET, media_ptr, local_path_ptr, new_path_name, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Look for a root directory selection. */ + if ((!new_path_name) || (((new_path_name[0] == '\\') || (new_path_name[0] == '/')) && (new_path_name[1] == (CHAR)0))) + { + + /* Set the default local directory to the root. */ + local_path_ptr -> fx_path_directory.fx_dir_entry_name[0] = (CHAR)0; + local_path_ptr -> fx_path_string[0] = (CHAR)0; + local_path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] = (CHAR)0; + + /* Setup thread control block to use this local path pointer. */ + _tx_thread_current_ptr -> tx_thread_filex_ptr = (VOID *)local_path_ptr; + } + else + { + + /* Search the system for the supplied path and directory name. */ + status = _fx_directory_search(media_ptr, new_path_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search failed or if the entry found is not a + directory. */ + if ((status != FX_SUCCESS) || (!(dir_entry.fx_dir_entry_attributes & FX_DIRECTORY))) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid Path - Return the error code. */ + return(FX_INVALID_PATH); + } + + /* Now update the current path string. */ + + /* Setup the path string pointer to the start of the current path. */ + path_string_ptr = &(local_path_ptr -> fx_path_string[0]); + + /* Setup the path string's capacity. */ + path_string_capacity = FX_MAXIMUM_PATH - 1; + + /* Determine if the new path is relative from the current path. */ + if ((new_path_name[0] != '\\') && (new_path_name[0] != '/')) + { + + /* Yes, a relative path was found. */ + + /* Setup the default path pointer to the local path. */ + path_ptr = local_path_ptr; + + /* Determine if the local path is different than the current local path. */ + if (local_path_ptr != (FX_LOCAL_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* Yes, there is a difference. */ + + /* Should we copy from the default media path or from the previous default + path. */ + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* There is a local path so copy the relative path info from it. */ + i = 0; + do + { + + /* Copy from previous local to new local path. */ + local_path_ptr -> fx_path_string[i] = + ((FX_LOCAL_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_string[i]; + + /* Determine if we are done. */ + if (local_path_ptr -> fx_path_string[i] == 0) + { + + /* Are we not at the end of the string? */ + if (i < (FX_MAXIMUM_PATH - 1)) + { + + /* Yes, break the loop. */ + break; + } + } + + /* Move to the next character. */ + i++; + + } while (i < FX_MAXIMUM_PATH); + } + else + { + + /* No local path, so copy the relative path information from the media + default. */ + i = 0; + do + { + + /* Copy from the media default to new local path. */ + local_path_ptr -> fx_path_string[i] = + media_ptr -> fx_media_default_path.fx_path_string[i]; + + /* Determine if we are done. */ + if (local_path_ptr -> fx_path_string[i] == 0) + { + + /* Are we not at the end of the string? */ + if (i < (FX_MAXIMUM_PATH - 1)) + { + + /* Yes, break the loop. */ + break; + } + } + + /* Move to the next character. */ + i++; + + } while (i < FX_MAXIMUM_PATH); + } + } + + /* First, check the current path for string overflow. If this is set, + don't attempt to update the current path with relative information. + The path won't be valid again until a complete path is given. */ + if (path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] == '*') + { + + /* Yes, don't update the string, just finish the path set processing. */ + + /* Determine if we are at the root directory. */ + if (!dir_entry.fx_dir_entry_cluster) + { + /* Set the current directory back to the root directory. */ + dir_entry.fx_dir_entry_name[0] = (CHAR)0; + + /* Clear the current path string. */ + path_ptr -> fx_path_string[0] = (CHAR)0; + + /* Clear the overflow flag in the current path string... just in + case! */ + path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] = (CHAR)0; + } + + /* Copy the new directory entry into the media control block. */ + path_ptr -> fx_path_directory = dir_entry; + + /* Reset the local path name buffer pointer, since it was clobbered earlier. */ + local_path_ptr -> fx_path_directory.fx_dir_entry_name = local_path_ptr -> fx_path_name_buffer; + + /* Copy the directory name entry to the local path name area. */ + for (j = 0; j < FX_MAX_LONG_NAME_LEN; j++) + { + + /* Copy the name buffer. */ + local_path_ptr -> fx_path_directory.fx_dir_entry_name[j] = dir_entry.fx_dir_entry_name[j]; + } + + /* Setup thread control block to use this local path pointer. */ + _tx_thread_current_ptr -> tx_thread_filex_ptr = (VOID *)local_path_ptr; + + /* Release media protection. */ + FX_UNPROTECT + + /* Default directory set is complete, return status. */ + return(FX_SUCCESS); + } + + /* Move the current path starting pointer to the end of the current + path string. */ + while ((path_string_capacity) && (*path_string_ptr != FX_NULL)) + { + path_string_ptr++; + path_string_capacity--; + } + + /* If room, place the \ character in the path string. */ + if (path_string_capacity) + { + + /* There is room, place the directory marker in the string. */ + *path_string_ptr++ = '\\'; + path_string_capacity--; + } + } + else + { + + /* Setup the default path pointer. */ + + /* Setup the default path pointer to the local path. */ + path_ptr = local_path_ptr; + + /* Complete path name given. Check to see if we need to clear an + overflow character from a previous current path string update. */ + if (path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] == '*') + { + path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] = (CHAR)0; + } + } + + /* Copy what we can into the current path. */ + while (*new_path_name) + { + + /* Determine if there is a ".." character sequence that specifies the + previous path. */ + if ((*new_path_name == '.') && (*(new_path_name + 1) == '.')) + { + + /* Yes, a backward path is found. The current path pointer + must be moved back to just after the previous \ character. */ + + /* Skip the current \0 that is at the end of the current path. */ + path_string_capacity = path_string_capacity + 2; + path_string_ptr = path_string_ptr - 2; + + while (path_string_capacity <= (FX_MAXIMUM_PATH - 1)) + { + + /* Move the current path pointer backwards until + a \ character is found. */ + + if ((*path_string_ptr == '\\') || (*path_string_ptr == '/')) + { + + /* Yes, we have successfully backed up one directory. */ + break; + } + + /* Backup another character. */ + path_string_capacity++; + path_string_ptr--; + } + + /* Adjust the new directory pointer past the .. characters */ + new_path_name = new_path_name + 2; + } + else + { + + /* Normal characters that need to be copied into the current path. */ + + if (path_string_capacity) + { + + /* Copy character from the new path into the current path string. */ + *path_string_ptr++ = *new_path_name++; + + path_string_capacity--; + } + else + { + + /* No more room in the current path string! */ + break; + } + } + } + + /* Determine if there is still room in the current path string. */ + if (path_string_capacity) + { + + /* Yes, there is still room, place a NULL character at the + end of the path. */ + *path_string_ptr = (CHAR)FX_NULL; + } + else + { + + /* No more room. Determine if the entire path was successfully + copied into the current path. */ + if (*new_path_name) + { + + /* No, we couldn't fit the entire path. Place a "*" character + at the end to indicate that we had overflow. Note that + the path is kept just the the directory default get call, so + the new default path is valid. */ + path_ptr -> fx_path_string[FX_MAXIMUM_PATH - 2] = '*'; + } + } + + /* Determine if we are at the root directory. */ + if (!dir_entry.fx_dir_entry_cluster) + { + /* Set the current directory back to the root directory. */ + dir_entry.fx_dir_entry_name[0] = (CHAR)0; + local_path_ptr -> fx_path_name_buffer[0] = (CHAR)0; + } + + /* Copy the new directory entry into the media control block. */ + path_ptr -> fx_path_directory = dir_entry; + + /* Reset the local path name buffer pointer, since it was clobbered earlier. */ + local_path_ptr -> fx_path_directory.fx_dir_entry_name = local_path_ptr -> fx_path_name_buffer; + + /* Copy the directory name entry to the local path name area. */ + for (j = 0; j < FX_MAX_LONG_NAME_LEN; j++) + { + + /* Copy the name buffer. */ + local_path_ptr -> fx_path_directory.fx_dir_entry_name[j] = dir_entry.fx_dir_entry_name[j]; + } + + /* Setup thread control block to use this local path pointer. */ + _tx_thread_current_ptr -> tx_thread_filex_ptr = (VOID *)local_path_ptr; + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Default directory set is complete, return status. */ + return(FX_SUCCESS); +#endif +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_long_name_get.c b/src/Middlewares/ST/filex/common/src/fx_directory_long_name_get.c new file mode 100644 index 00000000..e58a1802 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_long_name_get.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_long_name_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the long file name via the supplied short file */ +/* name. If there is no long file name, the short file name will be */ +/* returned. */ +/* */ +/* Note, this API is deprecated as fx_directory_long_name_get_extended */ +/* should be used. The maximum written size to long_file_name could be */ +/* FX_MAX_LONG_NAME_LEN. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* short_file_name Pointer to short (8.3) name */ +/* long_file_name Pointer to long (max 255) name*/ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_long_name_get_extended Actual long name get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_long_name_get(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name) +{ + + /* Call the extended version with maximum long name length. */ + return(_fx_directory_long_name_get_extended(media_ptr, short_file_name, long_file_name, FX_MAX_LONG_NAME_LEN)); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c b/src/Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c new file mode 100644 index 00000000..3d26bf3f --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_long_name_get_extended.c @@ -0,0 +1,139 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_long_name_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the long file name via the supplied short file */ +/* name. If there is no long file name, the short file name will be */ +/* returned. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* short_file_name Pointer to short (8.3) name */ +/* long_file_name Pointer to long (max 255) name*/ +/* long_file_name_buffer_length Buffer length for long name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the file name in */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_long_name_get_extended(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name, UINT long_file_name_buffer_length) +{ + +UINT status; +UINT i; +FX_DIR_ENTRY dir_entry; + + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_LONG_NAME_GET, media_ptr, short_file_name, long_file_name, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied short directory name. */ + status = _fx_directory_search(media_ptr, short_file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Copy the long name portion into the destination string. */ + i = 0; + while ((i < (FX_MAX_LONG_NAME_LEN - 1)) && (dir_entry.fx_dir_entry_name[i]) && (i < (long_file_name_buffer_length - 1))) + { + + /* Copy a character of the long name into the destination name. */ + long_file_name[i] = dir_entry.fx_dir_entry_name[i]; + + /* Move to next character. */ + i++; + } + + /* Ensure the long file name is NULL terminated. */ + long_file_name[i] = FX_NULL; + + /* Check if the buffer is too short for the name. */ + if ((i == (long_file_name_buffer_length - 1)) && (dir_entry.fx_dir_entry_name[i])) + { + + /* Buffer too short, return error. */ + status = FX_BUFFER_ERROR; + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_name_extract.c b/src/Middlewares/ST/filex/common/src/fx_directory_name_extract.c new file mode 100644 index 00000000..1a62b8ea --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_name_extract.c @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_name_extract PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function extracts the file name from the supplied input */ +/* string. If there is nothing left after the extracted name, a NULL */ +/* is returned to the caller. Otherwise, if something is left, a */ +/* pointer to it is returned. */ +/* */ +/* INPUT */ +/* */ +/* source_ptr Source string pointer */ +/* dest_ptr Destination string pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Pointer to Next Name (if multiple directories) */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +CHAR *_fx_directory_name_extract(CHAR *source_ptr, CHAR *dest_ptr) +{ + +UINT i; + + + /* Set the destination string to NULL. */ + dest_ptr[0] = 0; + + /* Is a backslash present? */ + if ((*source_ptr == '\\') || (*source_ptr == '/')) + { + + /* Advance the string pointer. */ + source_ptr++; + } + + /* Loop to remove any leading spaces. */ + while (*source_ptr == ' ') + { + + /* Position past leading space. */ + source_ptr++; + } + + /* Loop to extract the name. */ + i = 0; + while (*source_ptr) + { + + /* If another backslash is present, break the loop. */ + if ((*source_ptr == '\\') || (*source_ptr == '/')) + { + break; + } + + /* Long name can be at most 255 characters, but are further limited by the + FX_MAX_LONG_NAME_LEN define. */ + if (i == FX_MAX_LONG_NAME_LEN - 1) + { + break; + } + + /* Store the character. */ + dest_ptr[i] = *source_ptr++; + + /* Increment the character counter. */ + i++; + } + + /* NULL-terminate the string. */ + dest_ptr[i] = 0; + + /* Determine if we can backup to the previous character. */ + if (i) + { + + /* Yes, we can move backwards. */ + i--; + } + + /* Get rid of trailing blanks in the destination string. */ + while (dest_ptr[i] == ' ') + { + + /* Set this entry to NULL. */ + dest_ptr[i] = 0; + + /* Backup to the next character. Since leading spaces have been removed, + we know that the index is always greater than 1. */ + i--; + } + + /* Determine if the source string is now at the end. */ + if (*source_ptr == 0) + { + + /* Yes, return a NULL pointer. */ + source_ptr = FX_NULL; + } + + /* Return the last pointer position in the source. */ + return(source_ptr); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_name_test.c b/src/Middlewares/ST/filex/common/src/fx_directory_name_test.c new file mode 100644 index 00000000..603d5d33 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_name_test.c @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_name_test PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified directory name. */ +/* If found, the attributes are checked to see if the entry is a */ +/* directory. If not, the appropriate error code is returned to the */ +/* caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_name_test(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; +FX_DIR_ENTRY dir_entry; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_name_tests++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_NAME_TEST, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied directory name. */ + status = _fx_directory_search(media_ptr, directory_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check to see if the entry is a directory. */ + if (!(dir_entry.fx_dir_entry_attributes & (UCHAR)FX_DIRECTORY)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a directory error code. */ + return(FX_NOT_DIRECTORY); + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Directory name test is complete, return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c b/src/Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c new file mode 100644 index 00000000..11f31c0d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_next_entry_find.c @@ -0,0 +1,471 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_next_entry_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the name of the next entry in the current */ +/* working directory. The function that returns the first name in the */ +/* current directory must be called prior to this function. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Destination for directory */ +/* name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_read Read entries from root dir */ +/* _fx_utility_FAT_entry_read Read FAT entries to calculate */ +/* the sub-directory size */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code and */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_next_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +ULONG i; +UINT status; +UINT temp_status; +ULONG cluster, next_cluster = 0; +ULONG64 directory_size; +FX_DIR_ENTRY entry; +FX_DIR_ENTRY *search_dir_ptr; +FX_PATH *path_ptr; +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE +UINT index; +CHAR *path_string_ptr = FX_NULL; +#endif + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_next_entry_finds++; +#endif + + /* Setup pointer to media name buffer. */ + entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_NEXT_ENTRY_FIND, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* First check for a local path pointer stored in the thread control block. This + is only available in ThreadX Version 4 and above. */ + +#ifndef FX_NO_LOCAL_PATH + + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* Setup the default path pointer. */ + path_ptr = (FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr; + + /* Determine if we are at the root directory. */ + if (path_ptr -> fx_path_directory.fx_dir_entry_name[0]) + { + + /* No, we are not at the root directory. */ + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Setup pointer to the path. */ + path_string_ptr = ((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_string; +#endif + + /* Set the internal pointer to the search directory as well. */ + search_dir_ptr = &(path_ptr -> fx_path_directory); + } + else + { + + /* The current default directory is the root so just set the + search directory pointer to NULL. */ + search_dir_ptr = FX_NULL; + } + } + else +#endif + + /* Set the initial search directory to the current working + directory - if there is one. */ + if (media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name[0]) + { + + /* Setup the path pointer to the global media path. */ + path_ptr = &media_ptr -> fx_media_default_path; + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Setup pointer to the path. */ + path_string_ptr = media_ptr -> fx_media_default_path.fx_path_string; +#endif + + /* Set the internal pointer to the search directory as well. */ + search_dir_ptr = &(path_ptr -> fx_path_directory); + } + else + { + + /* Setup the path pointer to the global media path. */ + path_ptr = &media_ptr -> fx_media_default_path; + + /* The current default directory is the root so just set the + search directory pointer to NULL. */ + search_dir_ptr = FX_NULL; + } + + /* Calculate the directory size. */ + if (search_dir_ptr) + { +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + directory_size = search_dir_ptr -> fx_dir_entry_file_size / FX_DIR_ENTRY_SIZE; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + /* Determine the directory size. */ + if (path_ptr -> fx_path_current_entry != 0) + { + + /* Pickup the previously saved directory size. */ + directory_size = search_dir_ptr -> fx_dir_entry_file_size; + } + else + { + + /* This should only be done on the first time into next directory find. */ + + /* Ensure that the search directory's last search cluster is cleared. */ + search_dir_ptr -> fx_dir_entry_last_search_cluster = 0; + + /* Calculate the directory size by counting the allocated + clusters for it. */ + i = 0; + cluster = search_dir_ptr -> fx_dir_entry_cluster; + while (cluster < media_ptr -> fx_media_fat_reserved) + { + + /* Increment the cluster count. */ + i++; + + /* Read the next FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + if ((cluster < FX_FAT_ENTRY_START) || (cluster == next_cluster) || (i > media_ptr -> fx_media_total_clusters)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + cluster = next_cluster; + } + + /* Now we can calculate the directory size. */ + directory_size = (((ULONG64)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG64)media_ptr -> fx_media_sectors_per_cluster) * i) / + (ULONG64)FX_DIR_ENTRY_SIZE; + + /* Save how many entries there are in the directory. */ + search_dir_ptr -> fx_dir_entry_file_size = directory_size; + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + else + { + + /* Directory size is the number of entries in the root directory. */ + directory_size = (ULONG)media_ptr -> fx_media_root_directory_entries; + } + + /* Preset status with an error return. */ + status = FX_NO_MORE_ENTRIES; + + /* Determine if the current entry is inside of the directory's range. */ + while (path_ptr -> fx_path_current_entry < directory_size) + { + + /* Read an entry from the directory. */ + temp_status = _fx_directory_entry_read(media_ptr, search_dir_ptr, + &(path_ptr -> fx_path_current_entry), &entry); + + /* Check for error status. */ + if (temp_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error status. */ + return(temp_status); + } +#ifdef FX_ENABLE_EXFAT + if (entry.fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER) + { + /* Set the error code. */ + status = FX_NO_MORE_ENTRIES; + + /* Get out of the loop. */ + break; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check to see if the entry has something in it. */ +#ifdef FX_ENABLE_EXFAT + else if (entry.fx_dir_entry_type != FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY) +#else + if (((UCHAR)entry.fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_FREE) && (entry.fx_dir_entry_short_name[0] == 0)) +#endif /* FX_ENABLE_EXFAT */ + { + + /* Current entry is free, skip to next entry and continue the loop. */ + path_ptr -> fx_path_current_entry++; + continue; + } +#ifdef FX_ENABLE_EXFAT + else /* FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY */ +#else + else if ((UCHAR)entry.fx_dir_entry_name[0] != (UCHAR)FX_DIR_ENTRY_DONE) +#endif /* FX_ENABLE_EXFAT */ + { + + /* A valid directory entry is present. */ + + /* Copy the name into the destination. */ + for (i = 0; entry.fx_dir_entry_name[i]; i++) + { + + *directory_name = entry.fx_dir_entry_name[i]; + directory_name++; + } + + /* Place a NULL at the end of the directory name. */ + *directory_name = (CHAR)0; + + /* Increment the current entry for the media. */ + path_ptr -> fx_path_current_entry++; + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + { + UINT v, j; + + + /* If a subsequent search for the same name is done, it will find it immediately. */ + + /* Set the index of the saved name string. */ + v = 0; + + /* First, build the full path and name. */ + if (path_string_ptr) + { + + /* Copy the path into the destination. */ + while ((v < (FX_MAX_LAST_NAME_LEN - 1)) && (path_string_ptr[v])) + { + + /* Copy one character. */ + media_ptr -> fx_media_last_found_name[v] = path_string_ptr[v]; + + /* Move to next character. */ + v++; + } + } + + /* We know there is room at this point, place a directory separator character. */ + media_ptr -> fx_media_last_found_name[v++] = '/'; + + /* Now append the name to the path. */ + j = 0; + while ((v < FX_MAX_LAST_NAME_LEN) && (entry.fx_dir_entry_name[j])) + { + + /* Copy one character. */ + media_ptr -> fx_media_last_found_name[v] = entry.fx_dir_entry_name[j]; + + /* Move to next character. */ + v++; + j++; + } + + /* Null terminate the last name string. */ + if (v < FX_MAX_LAST_NAME_LEN) + { + + /* Null terminate. */ + media_ptr -> fx_media_last_found_name[v] = FX_NULL; + } + else + { + + /* The string is too big, NULL the string so it won't be used in searching. */ + media_ptr -> fx_media_last_found_name[0] = FX_NULL; + } + + /* Determine if there is a search pointer. */ + if (search_dir_ptr) + { + + /* Yes, there is a search directory pointer so save it! */ + media_ptr -> fx_media_last_found_directory = *search_dir_ptr; + + /* Indicate the search directory is valid. */ + media_ptr -> fx_media_last_found_directory_valid = FX_TRUE; + } + else + { + + /* Indicate the search directory is not valid. */ + media_ptr -> fx_media_last_found_directory_valid = FX_FALSE; + } + + /* Copy the directory entry. */ + media_ptr -> fx_media_last_found_entry = entry; + + /* Setup the last found directory entry to point at the last found internal file name. */ + media_ptr -> fx_media_last_found_entry.fx_dir_entry_name = media_ptr -> fx_media_last_found_file_name; + + /* Copy the actual directory name into the cached directory name. */ + for (index = 0; index < FX_MAX_LONG_NAME_LEN; index++) + { + + /* Copy character into the cached directory name. */ + media_ptr -> fx_media_last_found_file_name[index] = entry.fx_dir_entry_name[index]; + + /* See if we have copied the NULL termination character. */ + if (entry.fx_dir_entry_name[index] == (CHAR)FX_NULL) + { + + /* Check to see if we use the break to get out of the loop. */ + if (v < (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Yes, not at the end of the string, break. */ + break; + } + } + } + } +#endif + + /* Set return status to success. */ + status = FX_SUCCESS; + + /* Get out of the loop. */ + break; + } +#ifndef FX_ENABLE_EXFAT + else + { + + /* Set the error code. */ + status = FX_NO_MORE_ENTRIES; + + /* Get out of the loop. */ + break; + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c b/src/Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c new file mode 100644 index 00000000..588066d6 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_next_full_entry_find.c @@ -0,0 +1,573 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_next_full_entry_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the name of the next entry in the current */ +/* working directory and various information about the name. The */ +/* function that returns the first name in the current directory must */ +/* be called prior to this function. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Destination for directory */ +/* name */ +/* attributes Destination for attributes */ +/* size Destination for size */ +/* year Destination for year */ +/* month Destination for month */ +/* day Destination for day */ +/* hour Destination for hour */ +/* minute Destination for minute */ +/* second Destination for second */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_read Read entries from root dir */ +/* _fx_utility_FAT_entry_read Read FAT entries */ +/* _fx_directory_exFAT_entry_read Read exFAT entries */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code and */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_next_full_entry_find(FX_MEDIA *media_ptr, + CHAR *directory_name, UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second) +{ + +ULONG i; +UINT status; +UINT temp_status; +ULONG cluster, next_cluster = 0; +ULONG64 directory_size; +FX_DIR_ENTRY entry; +FX_DIR_ENTRY *search_dir_ptr; +FX_PATH *path_ptr; +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE +UINT index; +CHAR *path_string_ptr = FX_NULL; +#endif +#ifdef FX_ENABLE_EXFAT +/* TODO: maybe will be better to use dynamic memory, just because unicode_name is not needed in case of not exFAT. */ +UCHAR unicode_name[FX_MAX_LONG_NAME_LEN * 2]; +UINT unicode_len = 0; +#endif /* FX_ENABLE_EXFAT */ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_next_full_entry_finds++; +#endif + + /* Setup pointer to media name buffer. */ + entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + entry.fx_dir_entry_short_name[0] = 0; + +#ifdef FX_ENABLE_EXFAT + /* Will be set by exFAT. */ + entry.fx_dir_entry_secondary_count = 0; +#endif /* FX_ENABLE_EXFAT */ + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_NEXT_FULL_ENTRY_FIND, media_ptr, directory_name, 0, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* First check for a local path pointer stored in the thread control block. This + is only available in ThreadX Version 4 and above. */ +#ifndef FX_NO_LOCAL_PATH + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* Setup the default path pointer. */ + path_ptr = (FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr; + + /* Determine if we are at the root directory. */ + if (path_ptr -> fx_path_directory.fx_dir_entry_name[0]) + { + + /* No, we are not at the root directory. */ + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Setup pointer to the path. */ + path_string_ptr = ((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_string; +#endif + + /* Set the internal pointer to the search directory as well. */ + search_dir_ptr = &path_ptr -> fx_path_directory; + } + else + { + + /* The current default directory is the root so just set the + search directory pointer to NULL. */ + search_dir_ptr = FX_NULL; + } + } + else +#endif + + /* Set the initial search directory to the current working + directory - if there is one. */ + if (media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name[0]) + { + + /* Setup the path pointer to the global media path. */ + path_ptr = &media_ptr -> fx_media_default_path; + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Setup pointer to the path. */ + path_string_ptr = media_ptr -> fx_media_default_path.fx_path_string; +#endif + + /* Set the internal pointer to the search directory as well. */ + search_dir_ptr = &path_ptr -> fx_path_directory; + } + else + { + + /* Setup the path pointer to the global media path. */ + path_ptr = &media_ptr -> fx_media_default_path; + + /* The current default directory is the root so just set the + search directory pointer to NULL. */ + search_dir_ptr = FX_NULL; + } + + /* Calculate the directory size. */ + if (search_dir_ptr) + { + +#ifdef FX_ENABLE_EXFAT + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + directory_size = search_dir_ptr -> fx_dir_entry_file_size / FX_DIR_ENTRY_SIZE; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Determine the directory size. */ + if (path_ptr -> fx_path_current_entry != 0) + { + + /* Pickup the previously saved directory size. */ + directory_size = search_dir_ptr -> fx_dir_entry_file_size; + } + else + { + + /* This should only be done on the first time into next directory find. */ + + /* Ensure that the search directory's last search cluster is cleared. */ + search_dir_ptr -> fx_dir_entry_last_search_cluster = 0; + + /* Calculate the directory size by counting the allocated + clusters for it. */ + i = 0; + cluster = search_dir_ptr -> fx_dir_entry_cluster; + while (cluster < media_ptr -> fx_media_fat_reserved) + { + + /* Increment the cluster count. */ + i++; + + /* Read the next FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + if ((cluster < FX_FAT_ENTRY_START) || (cluster == next_cluster) || (i > media_ptr -> fx_media_total_clusters)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + cluster = next_cluster; + } + + /* Now we can calculate the directory size. */ + directory_size = (((ULONG64) media_ptr -> fx_media_bytes_per_sector) * + ((ULONG64) media_ptr -> fx_media_sectors_per_cluster) * i) + / (ULONG64) FX_DIR_ENTRY_SIZE; + + /* Save how many entries there are in the directory. */ + search_dir_ptr -> fx_dir_entry_file_size = directory_size; + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + else + { + + /* Directory size is the number of entries in the root directory. */ + directory_size = (ULONG)media_ptr -> fx_media_root_directory_entries; + } + + /* Preset status with an error return. */ + status = FX_NO_MORE_ENTRIES; + + /* Determine if the current entry is inside of the directory's range. */ + while (path_ptr -> fx_path_current_entry < directory_size) + { + + /* Read an entry from the directory. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + temp_status = _fx_directory_exFAT_entry_read(media_ptr, search_dir_ptr, + &(path_ptr -> fx_path_current_entry), &entry, + 0, FX_FALSE, unicode_name, &unicode_len); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + temp_status = _fx_directory_entry_read(media_ptr, search_dir_ptr, + &(path_ptr -> fx_path_current_entry), &entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for error status. */ + if (temp_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error status. */ + return(temp_status); + } + +#ifdef FX_ENABLE_EXFAT + if (entry.fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER) + { + /* Set the error code. */ + status = FX_NO_MORE_ENTRIES; + + /* Get out of the loop. */ + break; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check to see if the entry has something in it. */ +#ifdef FX_ENABLE_EXFAT + else if (entry.fx_dir_entry_type != FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY) +#else + if (((UCHAR)entry.fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_FREE) && (entry.fx_dir_entry_short_name[0] == 0)) +#endif /* FX_ENABLE_EXFAT */ + { + + /* Current entry is free, skip to next entry and continue the loop. */ + path_ptr -> fx_path_current_entry++; + continue; + } + + /* Determine if a valid directory entry is present. */ +#ifdef FX_ENABLE_EXFAT + else /* FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY */ +#else + else if ((UCHAR)entry.fx_dir_entry_name[0] != (UCHAR)FX_DIR_ENTRY_DONE) +#endif /* FX_ENABLE_EXFAT */ + { + + /* A valid directory entry is present. */ + + /* Copy the name into the destination. */ + for (i = 0; entry.fx_dir_entry_name[i]; i++) + { + + *directory_name = entry.fx_dir_entry_name[i]; + directory_name++; + } + + /* Place a NULL at the end of the directory name. */ + *directory_name = (CHAR)0; + + /* Determine if the entry's attributes are required. */ + if (attributes) + { + + /* Pickup the entry's attributes. */ + *attributes = entry.fx_dir_entry_attributes; + } + + /* Determine if the entry's size is required. */ + if (size) + { + + /* Pickup the entry's size. */ + *size = (ULONG)entry.fx_dir_entry_file_size; + } + + /* Determine if the entry's year is required. */ + if (year) + { + + /* Pickup the entry's year. */ + *year = ((entry.fx_dir_entry_date >> FX_YEAR_SHIFT) & FX_YEAR_MASK) + FX_BASE_YEAR; + } + + /* Determine if the entry's month is required. */ + if (month) + { + + /* Pickup the entry's month. */ + *month = (entry.fx_dir_entry_date >> FX_MONTH_SHIFT) & FX_MONTH_MASK; + } + + /* Determine if the entry's day is required. */ + if (day) + { + + /* Pickup the entry's day. */ + *day = entry.fx_dir_entry_date & FX_DAY_MASK; + } + + /* Determine if the entry's hour is required. */ + if (hour) + { + + /* Pickup the entry's hour. */ + *hour = (entry.fx_dir_entry_time >> FX_HOUR_SHIFT) & FX_HOUR_MASK; + } + + /* Determine if the entry's minute is required. */ + if (minute) + { + + /* Pickup the entry's minute. */ + *minute = (entry.fx_dir_entry_time >> FX_MINUTE_SHIFT) & FX_MINUTE_MASK; + } + + /* Determine if the entry's second is required. */ + if (second) + { + + /* Pickup the entry's second. */ + *second = (entry.fx_dir_entry_time & FX_SECOND_MASK) * 2; + } + + /* Increment the current entry for the media. */ + path_ptr -> fx_path_current_entry++; + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + { + UINT v, j; + + + /* If a subsequent search for the same name is done, it will find it immediately. */ + + /* Set the index of the saved name string. */ + v = 0; + + /* First, build the full path and name. */ + if (path_string_ptr) + { + + /* Copy the path into the destination. */ + while ((v < (FX_MAX_LAST_NAME_LEN - 1)) && (path_string_ptr[v])) + { + + /* Copy one character. */ + media_ptr -> fx_media_last_found_name[v] = path_string_ptr[v]; + + /* Move to next character. */ + v++; + } + } + + /* We know there is room at this point, place a directory separator character. */ + media_ptr -> fx_media_last_found_name[v++] = '/'; + + /* Now append the name to the path. */ + j = 0; + while ((v < FX_MAX_LAST_NAME_LEN) && (entry.fx_dir_entry_name[j])) + { + + /* Copy one character. */ + media_ptr -> fx_media_last_found_name[v] = entry.fx_dir_entry_name[j]; + + /* Move to next character. */ + v++; + j++; + } + + /* Null terminate the last name string. */ + if (v < FX_MAX_LAST_NAME_LEN) + { + + /* Null terminate. */ + media_ptr -> fx_media_last_found_name[v] = FX_NULL; + } + else + { + + /* The string is too big, NULL the string so it won't be used in searching. */ + media_ptr -> fx_media_last_found_name[0] = FX_NULL; + } + + /* Determine if there is a search pointer. */ + if (search_dir_ptr) + { + + /* Yes, there is a search directory pointer so save it! */ + media_ptr -> fx_media_last_found_directory = *search_dir_ptr; + + /* Indicate the search directory is valid. */ + media_ptr -> fx_media_last_found_directory_valid = FX_TRUE; + } + else + { + + /* Indicate the search directory is not valid. */ + media_ptr -> fx_media_last_found_directory_valid = FX_FALSE; + } + + /* Copy the directory entry. */ + media_ptr -> fx_media_last_found_entry = entry; + + /* Setup the last found directory entry to point at the last found internal file name. */ + media_ptr -> fx_media_last_found_entry.fx_dir_entry_name = media_ptr -> fx_media_last_found_file_name; + + /* Copy the actual directory name into the cached directory name. */ + for (index = 0; index < FX_MAX_LONG_NAME_LEN; index++) + { + + /* Copy character into the cached directory name. */ + media_ptr -> fx_media_last_found_file_name[index] = entry.fx_dir_entry_name[index]; + + /* See if we have copied the NULL termination character. */ + if (entry.fx_dir_entry_name[index] == (CHAR)FX_NULL) + { + + /* Check to see if we use the break to get out of the loop. */ + if (v < (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Yes, not at the end of the string, break. */ + break; + } + } + } + } +#endif + + /* Set return status to success. */ + status = FX_SUCCESS; + + /* Get out of the loop. */ + break; + } +#ifndef FX_ENABLE_EXFAT + else + { + /* Set the error code. */ + status = FX_NO_MORE_ENTRIES; + + /* Get out of the loop. */ + break; + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_rename.c b/src/Middlewares/ST/filex/common/src/fx_directory_rename.c new file mode 100644 index 00000000..cdb41a57 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_rename.c @@ -0,0 +1,523 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_rename PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified directory. */ +/* If found, the rename request is valid and the directory will be */ +/* changed to the new name. Otherwise, if the directory is not found, */ +/* the appropriate error code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* old_directory_name Old file directory pointer */ +/* new_directory_name New file directory pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the new directory entry */ +/* _fx_directory_free_search Search for a free directory */ +/* entry */ +/* _fx_directory_name_extract Extract directory name */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_rename(FX_MEDIA *media_ptr, CHAR *old_directory_name, CHAR *new_directory_name) +{ + +UINT status; +FX_DIR_ENTRY old_dir_entry; +FX_DIR_ENTRY new_dir_entry; +FX_DIR_ENTRY search_directory; +CHAR *new_name_ptr; +ULONG i; +CHAR *work_ptr; +CHAR alpha, beta; +#ifdef FX_RENAME_PATH_INHERIT +UINT j; +#endif + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_directory_renames++; +#endif + + /* Setup pointers to media name buffers. */ + old_dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + new_dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN * 2; + search_directory.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN * 3; + + /* Clear the short name strings. */ + old_dir_entry.fx_dir_entry_short_name[0] = 0; + new_dir_entry.fx_dir_entry_short_name[0] = 0; + search_directory.fx_dir_entry_short_name[0] = 0; + + /* Determine if the supplied name is less than the maximum supported name size. The + maximum name (FX_MAX_LONG_NAME_LEN) is defined in fx_api.h. */ + i = 0; + work_ptr = (CHAR *)new_directory_name; + while (*work_ptr && (i < FX_MAX_LONG_NAME_LEN)) + { + + /* Determine if the character designates a new path. */ + if ((*work_ptr == '\\') || (*work_ptr == '/')) + { + /* Yes, reset the name size. */ + i = 0; + } + /* Check for leading spaces. */ + else if ((*work_ptr != ' ') || (i != 0)) + { + + /* No leading spaces, increment the name size. */ + i++; + } + + /* Move to the next character. */ + work_ptr++; + } + + /* Determine if the supplied name is valid. */ + if ((i == 0) || (i >= FX_MAX_LONG_NAME_LEN)) + { + + /* Return an invalid name value. */ + return(FX_INVALID_NAME); + } + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_RENAME, media_ptr, old_directory_name, new_directory_name, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Search the system for the supplied directory name. */ + status = _fx_directory_search(media_ptr, old_directory_name, &old_dir_entry, &search_directory, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check to make sure the found entry is a directory. */ + if (!(old_dir_entry.fx_dir_entry_attributes & (UCHAR)(FX_DIRECTORY))) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a directory error code. */ + return(FX_NOT_DIRECTORY); + } + +#ifdef FX_RENAME_PATH_INHERIT + + /* Determine if the source directory name has a path and the target directory name does not. */ + if (((old_directory_name[0] == '/') || (old_directory_name[0] == '\\')) && (new_directory_name[0] != '/') && (new_directory_name[0] != '\\')) + { + + /* In this case, we need to prepend the path of the old directory name to that of the new directory name. */ + + /* Setup pointer to the rename buffer. */ + work_ptr = (CHAR *)media_ptr -> fx_media_rename_buffer; + + /* First, copy the path of the old directory name. */ + i = 0; + j = 0; + while ((old_directory_name[i]) && (i < FX_MAXIMUM_PATH)) + { + + /* Copy a character into the rename buffer. */ + *work_ptr++ = old_directory_name[i]; + + /* Determine if this character is directory separator. */ + if ((old_directory_name[i] == '/') || (old_directory_name[i] == '\\')) + { + + /* Yes, directory separator has been found - remember the index. */ + j = i; + } + + /* Move to next position in the old directory name. */ + i++; + } + + /* At this point, we have the path stored in the rename buffer. */ + + /* Position past the last slash or backslash. */ + j++; + + /* Reset the working pointer to the position after the last directory separator. */ + work_ptr = (CHAR *)&(media_ptr -> fx_media_rename_buffer[j]); + + /* Now copy the new directory name into the rename buffer. */ + i = 0; + while ((new_directory_name[i]) && (j < FX_MAXIMUM_PATH)) + { + + /* Copy a character into the rename buffer. */ + *work_ptr++ = new_directory_name[i]; + + /* Move to next character. */ + i++; + j++; + } + + /* Determine if the path was successfully prepended. */ + if (new_directory_name[i]) + { + + /* No, there was not enough room in the destination buffer. */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the invalid path error code. */ + return(FX_INVALID_PATH); + } + + /* Place a NULL at the end of the string. */ + *work_ptr = (CHAR)FX_NULL; + + /* At this point, we have successfully prepended the path in the new directory name, override + the new directory name so it is used from now on. */ + new_directory_name = (CHAR *)media_ptr -> fx_media_rename_buffer; + } +#endif + + /* Search the media for the new directory name - including any supplied path. */ + status = _fx_directory_search(media_ptr, new_directory_name, &new_dir_entry, &search_directory, &new_name_ptr); + + /* Determine if the search found anything. */ + if (status == FX_SUCCESS) + { + + /* Determine if the new name simply has an ASCII case change. If so, simply let the processing + continue. */ + i = 0; + do + { + + /* Pickup an old name and new name character and convert to upper case if necessary. */ + alpha = old_directory_name[i]; + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Lower case, convert to upper case! */ + alpha = (CHAR)((INT)alpha - 0x20); + } + beta = new_directory_name[i]; + if ((beta >= 'a') && (beta <= 'z')) + { + + /* Lower case, convert to upper case! */ + beta = (CHAR)((INT)beta - 0x20); + } + + /* Now compare the characters. */ + if ((alpha != beta) || (alpha == 0)) + { + + /* Get out of this loop! */ + break; + } + + /* Move to next character. */ + i++; + } while (i < (FX_MAXIMUM_PATH-1)); + + /* Now determine if the names match. */ + if (alpha != beta) + { + + /* Yes, the directory name already exists in the target location. */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(FX_ALREADY_CREATED); + } + } + + /* Make sure the name is valid. */ + if (_fx_directory_name_extract(new_name_ptr, &new_dir_entry.fx_dir_entry_name[0])) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection */ + FX_UNPROTECT + + /* Return the error code */ + return(FX_INVALID_NAME); + } + + /* Look for a free slot in the target directory. */ + status = _fx_directory_free_search(media_ptr, &search_directory, &new_dir_entry); + + /* Was a free slot found? */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* No, release protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Extract the new directory name. */ + _fx_directory_name_extract(new_name_ptr, &new_dir_entry.fx_dir_entry_name[0]); + + /* Determine if the name was a long directory name. */ + if (new_dir_entry.fx_dir_entry_long_name_present) + { + + /* Yes, clear the short directory name to force a new one. */ + new_dir_entry.fx_dir_entry_short_name[0] = 0; + } + + /* Setup new attributes for the new directory entry. */ + new_dir_entry.fx_dir_entry_attributes = old_dir_entry.fx_dir_entry_attributes; + new_dir_entry.fx_dir_entry_cluster = old_dir_entry.fx_dir_entry_cluster; + new_dir_entry.fx_dir_entry_file_size = old_dir_entry.fx_dir_entry_file_size; + + /* Save the reserved field. */ + new_dir_entry.fx_dir_entry_reserved = old_dir_entry.fx_dir_entry_reserved; + + /* Set time and date stamps. */ + new_dir_entry.fx_dir_entry_created_time_ms = old_dir_entry.fx_dir_entry_created_time_ms; + new_dir_entry.fx_dir_entry_created_time = old_dir_entry.fx_dir_entry_created_time; + new_dir_entry.fx_dir_entry_created_date = old_dir_entry.fx_dir_entry_created_date; + new_dir_entry.fx_dir_entry_last_accessed_date = old_dir_entry.fx_dir_entry_last_accessed_date; + new_dir_entry.fx_dir_entry_time = old_dir_entry.fx_dir_entry_time; + new_dir_entry.fx_dir_entry_date = old_dir_entry.fx_dir_entry_date; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + new_dir_entry.fx_dir_entry_dont_use_fat = old_dir_entry.fx_dir_entry_dont_use_fat; + new_dir_entry.fx_dir_entry_type = old_dir_entry.fx_dir_entry_type; + new_dir_entry.fx_dir_entry_available_file_size = old_dir_entry.fx_dir_entry_available_file_size; + new_dir_entry.fx_dir_entry_secondary_count = old_dir_entry.fx_dir_entry_secondary_count; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Is there a leading dot? */ + if (new_dir_entry.fx_dir_entry_name[0] == '.') + { + + /* Yes, toggle the hidden attribute bit. */ + new_dir_entry.fx_dir_entry_attributes |= FX_HIDDEN; + } + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Invalidate the directory cache. */ + media_ptr -> fx_media_last_found_name[0] = FX_NULL; +#endif + + /* Now write out the directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &new_dir_entry, UPDATE_FULL); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &new_dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Set the old directory entry to free. */ + old_dir_entry.fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + old_dir_entry.fx_dir_entry_short_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + + /* Now wipe out the old directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &old_dir_entry, UPDATE_DELETE); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &old_dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Directory rename is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_search.c b/src/Middlewares/ST/filex/common/src/fx_directory_search.c new file mode 100644 index 00000000..2eb64308 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_search.c @@ -0,0 +1,984 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_search PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function searches the media for the supplied name. The search */ +/* routine will find files as well as directory names. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* name_ptr Name pointer */ +/* entry_ptr Pointer to directory entry */ +/* record */ +/* last_dir_ptr Pointer to destination for */ +/* the last directory entry */ +/* last_name_ptr Pointer to the last name */ +/* token that was searched for */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_name_extract Extract directory name from */ +/* input string */ +/* _fx_directory_entry_read Read entries from root dir */ +/* _fx_utility_exFAT_name_hash_get Get name hash */ +/* _fx_utility_FAT_entry_read Read FAT entries to calculate */ +/* the sub-directory size */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable media search cache, */ +/* resulting in version 6.1 */ +/* 06-02-2021 Bhupendra Naphade Modified comment(s), and */ +/* added check for */ +/* volume label, */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 William E. Lamie Modified comment(s), and */ +/* fixed path compare, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_search(FX_MEDIA *media_ptr, CHAR *name_ptr, FX_DIR_ENTRY *entry_ptr, + FX_DIR_ENTRY *last_dir_ptr, CHAR **last_name_ptr) +{ + +ULONG i, n; +UINT found; +UINT status; +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE +UINT v, j; +#endif /* FX_MEDIA_DISABLE_SEARCH_CACHE */ +ULONG cluster, next_cluster = 0; +ULONG64 directory_size; +CHAR *dir_name_ptr; +CHAR *work_ptr; +CHAR *source_name_ptr; +CHAR *destination_name_ptr; +FX_DIR_ENTRY search_dir; +FX_DIR_ENTRY *search_dir_ptr; +CHAR *name, alpha, name_alpha; +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE +UINT index; +CHAR *path_ptr = FX_NULL; +CHAR *original_name = name_ptr; +#endif +#ifdef FX_ENABLE_EXFAT +USHORT hash = 0; +#endif /* FX_ENABLE_EXFAT */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of directory search requests. */ + media_ptr -> fx_media_directory_searches++; +#endif + + /* Setup pointer to media name buffer. */ + name = media_ptr -> fx_media_name_buffer; + + /* Setup the last directory, if required. */ + if (last_dir_ptr) + { + + /* Set the first character of the directory entry to NULL to + indicate root or no directory. */ + last_dir_ptr -> fx_dir_entry_name[0] = 0; + } + + /* Determine if the file name has a full directory path. */ + if ((*name_ptr == '\\') || (*name_ptr == '/')) + { + + /* Directory name has full path, set the search pointer to NULL. */ + search_dir_ptr = FX_NULL; + } + else + { + + /* Set the initial search directory to the current working + directory - if there is one. */ + + /* First check for a local path pointer stored in the thread control block. This + is only available in ThreadX Version 4 and above. */ +#ifndef FX_NO_LOCAL_PATH + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* Determine if the local directory is not the root directory. */ + if (((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_directory.fx_dir_entry_name[0]) + { + + /* Start at the current working directory of the media. */ + search_dir = ((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_directory; + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Setup pointer to the path. */ + path_ptr = ((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_string; +#endif + + /* Set the internal pointer to the search directory as well. */ + search_dir_ptr = &search_dir; + } + else + { + + /* We are searching in the root directory. */ + search_dir_ptr = FX_NULL; + } + } + else +#endif + if (media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name[0]) + { + + /* Start at the current working directory of the media. */ + search_dir = media_ptr -> fx_media_default_path.fx_path_directory; + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Setup pointer to the path. */ + path_ptr = media_ptr -> fx_media_default_path.fx_path_string; +#endif + + /* Set the internal pointer to the search directory as well. */ + search_dir_ptr = &search_dir; + } + else + { + + /* The current default directory is the root so just set the + search directory pointer to NULL. */ + search_dir_ptr = FX_NULL; + } + } + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Determine if there is a previously found directory entry. */ + if (media_ptr -> fx_media_last_found_name[0]) + { + + UINT match; + CHAR *temp_ptr, beta; + + /* Yes, there is a previously found directory in our cache. */ + + /* Initialize the index. */ + v = 0; + + /* Determine if there is a full path. */ + if ((*name_ptr == '\\') || (*name_ptr == '/')) + { + + /* Yes, the full path is in the name buffer. Simply compare with what is in + the last search buffer. */ + while ((v < (FX_MAX_LAST_NAME_LEN - 1)) && (name_ptr[v])) + { + + /* Pickup the respective name characters. */ + alpha = name_ptr[v]; + beta = media_ptr -> fx_media_last_found_name[v]; + + /* Ensure directory markers are the same. */ + if (alpha == '\\') + { + alpha = '/'; + } + if (beta == '\\') + { + beta = '/'; + } + + /* Is the name the same? */ + if (alpha != beta) + { + + /* Break out of loop! */ + break; + } + + /* Move to next character. */ + v++; + } + + /* Determine if we have a match. */ + if (name_ptr[v] != media_ptr -> fx_media_last_found_name[v]) + { + match = FX_FALSE; + } + else + { + match = FX_TRUE; + } + } + else + { + + /* Default to found. */ + match = FX_TRUE; + + /* Determine if there is a default path to compare with. */ + if (path_ptr) + { + + /* Yes, compare the current path with what is contained in the last + found buffer. Note that the last found name must have at least one + path separator as well as room for at least one character for a name. */ + while ((v < (FX_MAX_LAST_NAME_LEN - 1)) && (path_ptr[v])) + { + + /* Pickup the respective name characters. */ + alpha = media_ptr -> fx_media_last_found_name[v]; + beta = path_ptr[v]; + + /* Ensure directory markers are the same. */ + if (alpha == '\\') + { + alpha = '/'; + } + if (beta == '\\') + { + beta = '/'; + } + + /* Is the name the same? */ + if (alpha != beta) + { + + /* Break out of loop! */ + break; + } + + /* Move to next character. */ + v++; + } + + /* Determine if we don't have a match... The relative path must be exhausted. */ + if (path_ptr[v]) + { + match = FX_FALSE; + } + } + + /* Determine if we still have a match. */ + if (match) + { + + /* Now examine the rest of the last name and the newly supplied + input name. */ + + /* Determine if a valid directory separator is present. */ + if ((media_ptr -> fx_media_last_found_name[v] != '\\') && + (media_ptr -> fx_media_last_found_name[v] != '/')) + { + + /* Set match to false - invalid directory path separator. */ + match = FX_FALSE; + } + else + { + /* Position past the next directory separator in the + last name string. */ + v++; + } + + /* Yes, the full path is in the name buffer. Simply compare with what is in + the last search buffer. */ + j = 0; + while ((v < (FX_MAX_LAST_NAME_LEN - 1)) && (name_ptr[j]) && (match)) + { + + /* Pickup the respective name characters. */ + alpha = name_ptr[j]; + beta = media_ptr -> fx_media_last_found_name[v]; + + /* Ensure directory markers are the same. */ + if (alpha == '\\') + { + alpha = '/'; + } + if (beta == '\\') + { + beta = '/'; + } + + /* Is the name the same? */ + if (alpha != beta) + { + + /* Break out of loop! */ + break; + } + + /* Move to next character. */ + v++; + j++; + } + + /* Avoid accessing fx_media_last_found_name out of bounds. */ + if (v >= 256) + { + match = FX_FALSE; + } + else if ((match) && (name_ptr[j] != media_ptr -> fx_media_last_found_name[v])) + { + + /* We don't have a match. */ + match = FX_FALSE; + } + } + } + + /* Now determine if we actually found a match. */ + if (match) + { + + /* Save the directory entry name pointer. */ + temp_ptr = entry_ptr -> fx_dir_entry_name; + + /* Copy the saved directory entry. */ + *entry_ptr = media_ptr -> fx_media_last_found_entry; + + /* Restore the directory entry name pointer. */ + entry_ptr -> fx_dir_entry_name = temp_ptr; + + /* Copy the directory name into the destination directory name. */ + for (index = 0; index < FX_MAX_LONG_NAME_LEN; index++) + { + + /* Copy character into the destination. */ + temp_ptr[index] = media_ptr -> fx_media_last_found_file_name[index]; + + /* See if we have copied the NULL termination character. */ + if (temp_ptr[index] == (CHAR)FX_NULL) + { + + /* Determine if we should break here or at the top of the loop. */ + if (index < (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Yes, break out of the loop early. */ + break; + } + } + } + + /* Determine if there is a search directory to copy. */ + if ((last_dir_ptr) && (media_ptr -> fx_media_last_found_directory_valid)) + { + + /* Yes, there was a search directory... and one is requested in this request as well. + Simply copy it into the destination. */ + + /* First, save the name pointer from the list directory pointer. */ + destination_name_ptr = last_dir_ptr -> fx_dir_entry_name; + + /* Copy the entire directory entry structure. */ + *last_dir_ptr = media_ptr -> fx_media_last_found_directory; + + /* Restore the original name buffer pointer. */ + last_dir_ptr -> fx_dir_entry_name = destination_name_ptr; + + /* Pickup pointer to name to copy. */ + source_name_ptr = media_ptr -> fx_media_last_found_directory.fx_dir_entry_name; + + /* Loop to copy the name into the last directory name buffer. */ + for (n = 0; n < FX_MAX_LONG_NAME_LEN; n++) + { + + /* Copy a character. */ + destination_name_ptr[n] = source_name_ptr[n]; + + /* See if we have copied the NULL termination character. */ + if (source_name_ptr[n] == (CHAR)FX_NULL) + { + + /* Determine if we should break here or at the top of the loop. */ + if (n < (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Yes, break out of the loop early. */ + break; + } + } + } + } + + /* Return the last name pointer, if required. */ + if (last_name_ptr) + { + + /* Just set the last name to initial name string. */ + *last_name_ptr = temp_ptr; + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of directory search cache hits. */ + media_ptr -> fx_media_directory_search_cache_hits++; +#endif + + /* Return success. */ + return(FX_SUCCESS); + } + } + + /* Not a sequential search, invalidate the saved information. */ + media_ptr -> fx_media_last_found_name[0] = FX_NULL; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_DIR_CACHE_MISS, media_ptr, media_ptr -> fx_media_directory_searches - media_ptr -> fx_media_directory_search_cache_hits, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) +#else + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_DIR_CACHE_MISS, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) +#endif +#endif + + /* Loop to traverse the directory paths to find the specified file. */ + do + { + + /* Remember the last name pointer, if required. */ + if (last_name_ptr) + { + + /* Just set the last name to initial name string. */ + *last_name_ptr = name_ptr; + } + + /* Extract file name. */ + name_ptr = _fx_directory_name_extract(name_ptr, name); + + /* Calculate the directory size. */ + if (search_dir_ptr) + { +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + directory_size = search_dir_ptr -> fx_dir_entry_file_size / FX_DIR_ENTRY_SIZE; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Ensure that the search directory's last search cluster is cleared. */ + search_dir_ptr -> fx_dir_entry_last_search_cluster = 0; + + /* Calculate the directory size by counting the allocated + clusters for it. */ + i = 0; + cluster = search_dir_ptr -> fx_dir_entry_cluster; + while (cluster < media_ptr -> fx_media_fat_reserved) + { + + /* Increment the cluster count. */ + i++; + + /* Read the next FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + + /* Check for error situation. */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster == next_cluster) || (i > media_ptr -> fx_media_total_clusters)) + { + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + cluster = next_cluster; + } + + /* Now we can calculate the directory size. */ + directory_size = (((ULONG64) media_ptr -> fx_media_bytes_per_sector) * + ((ULONG64) media_ptr -> fx_media_sectors_per_cluster) * i) + / (ULONG64) FX_DIR_ENTRY_SIZE; + + /* Also save this in the directory entry so we don't have to + calculate it later. */ + search_dir_ptr -> fx_dir_entry_file_size = directory_size; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* If required, copy the last search directory entry into the + destination. */ + if (last_dir_ptr) + { + + /* Copy the last search directory into the destination. */ + + /* First, save the name pointer from the list directory pointer. */ + destination_name_ptr = last_dir_ptr -> fx_dir_entry_name; + + /* Copy the entire directory entry structure. */ + *last_dir_ptr = *search_dir_ptr; + + /* Restore the original name buffer pointer. */ + last_dir_ptr -> fx_dir_entry_name = destination_name_ptr; + + /* Pickup pointer to name to copy. */ + source_name_ptr = search_dir_ptr -> fx_dir_entry_name; + + /* Loop to copy the name into the last directory name buffer. */ + for (n = 0; n < FX_MAX_LONG_NAME_LEN; n++) + { + + /* Copy a character. */ + destination_name_ptr[n] = source_name_ptr[n]; + + /* See if we have copied the NULL termination character. */ + if (source_name_ptr[n] == (CHAR) FX_NULL) + { + + /* Determine if we should break here or at the top of the loop. */ + if (n < (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Yes, break out of the loop early. */ + break; + } + } + } + } + } + else + { + + /* Directory size is the number of entries in the root directory. */ + directory_size = (ULONG)media_ptr -> fx_media_root_directory_entries; + } + + /* Loop through entries in the directory. Yes, this is a + linear search! */ + i = 0; + found = FX_FALSE; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Get name hash. */ + hash = _fx_utility_exFAT_name_hash_get(name); + } +#endif /* FX_ENABLE_EXFAT */ + + do + { + + /* Read an entry from the directory. */ +#ifdef FX_ENABLE_EXFAT + status = _fx_directory_entry_read_ex(media_ptr, search_dir_ptr, &i, entry_ptr, hash); +#else + status = _fx_directory_entry_read(media_ptr, search_dir_ptr, &i, entry_ptr); +#endif /* FX_ENABLE_EXFAT */ + + i++; + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Determine if this is the last directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (entry_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER) +#else + if ((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_DONE) +#endif /* FX_ENABLE_EXFAT */ + { + break; + } + + /* Determine if the entry is a volume label entry */ + if ((entry_ptr -> fx_dir_entry_attributes & FX_VOLUME)) + { + continue; + } + + /* Determine if this is an empty entry. */ +#ifdef FX_ENABLE_EXFAT + if (entry_ptr -> fx_dir_entry_type != FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY) +#else + if (((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_FREE) && (entry_ptr -> fx_dir_entry_short_name[0] == 0)) +#endif /* FX_ENABLE_EXFAT */ + { + continue; + } + + /* Compare the input name and extension with the directory + entry. */ + work_ptr = &name[0]; + dir_name_ptr = &(entry_ptr -> fx_dir_entry_name[0]); + + /* Loop to compare names. */ + do + { + + /* Pickup character of directory name. */ + alpha = *dir_name_ptr; + + /* Pickup character of name. */ + name_alpha = *work_ptr; + + /* Determine if its case needs to be changed. */ + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Yes, make upper case. */ + alpha = (CHAR)((INT)alpha - 0x20); + } + + /* Determine if its case needs to be changed. */ + if ((name_alpha >= 'a') && (name_alpha <= 'z')) + { + + /* Yes, make upper case. */ + name_alpha = (CHAR)((INT)name_alpha - 0x20); + } + + /* Compare name with directory name. */ + if (alpha != name_alpha) + { + + /* The names don't match, get out of the loop. */ + break; + } + + /* Otherwise, increment the name pointers. */ + work_ptr++; + dir_name_ptr++; + } while (*dir_name_ptr); + + /* Determine if the requested name has been found. If so, + return success to the caller. */ + if ((*dir_name_ptr == 0) && (*work_ptr == *dir_name_ptr)) + { + + /* Yes, the name was located. All pertinent directory + information is in the directory entry field. */ + found = FX_TRUE; + } + /* Determine if there is a short name to check. */ +#ifdef FX_ENABLE_EXFAT + else if ((media_ptr -> fx_media_FAT_type != FX_exFAT) && + (entry_ptr -> fx_dir_entry_short_name[0] != 0)) +#else + else if (entry_ptr -> fx_dir_entry_short_name[0] != 0) +#endif /* FX_ENABLE_EXFAT */ + { + + /* Yes, check for the short part of the name. */ + + /* Compare the input name and extension with the directory entry. */ + work_ptr = &name[0]; + dir_name_ptr = &(entry_ptr -> fx_dir_entry_short_name[0]); + + /* Loop to compare names. */ + do + { + + /* Pickup character of directory name. */ + alpha = *dir_name_ptr; + + /* Pickup character of name. */ + name_alpha = *work_ptr; + + /* Determine if its case needs to be changed. */ + if ((name_alpha >= 'a') && (name_alpha <= 'z')) + { + + /* Yes, make upper case. */ + name_alpha = (CHAR)((INT)name_alpha - 0x20); + } + + /* Compare name with directory name. */ + if (alpha != name_alpha) + { + + /* The names don't match, get out of the loop. */ + break; + } + + /* Otherwise, move the name pointers and increment the + count. */ + work_ptr++; + dir_name_ptr++; + } while (*dir_name_ptr); + + /* Determine if the names match. */ + if ((*dir_name_ptr == 0) && (*work_ptr == *dir_name_ptr)) + { + + /* Yes, the name was located. All pertinent directory + information is in the directory entry field. */ + found = FX_TRUE; + } + } + } while ((i < directory_size) && (!found)); + + /* Now determine if we have a match. */ + if (!found) + { + + /* Return a "not found" status to the caller. */ + return(FX_NOT_FOUND); + } + + /* Determine if the found entry is indeed a sub-directory. */ + if (entry_ptr -> fx_dir_entry_attributes & FX_DIRECTORY) + { + + /* Move the directory search pointer to this entry. */ + search_dir = *entry_ptr; + search_dir_ptr = &search_dir; + + /* Ensure that the search directory's last search cluster is cleared. */ + search_dir_ptr -> fx_dir_entry_last_search_cluster = 0; + + /* Now determine if the new search directory is the root + directory. */ +#ifdef FX_ENABLE_EXFAT + if ((!search_dir_ptr -> fx_dir_entry_cluster) + && (media_ptr -> fx_media_FAT_type != FX_exFAT)) +#else + if (!search_dir_ptr -> fx_dir_entry_cluster) +#endif /* FX_ENABLE_EXFAT */ + { + + /* This is a backward link to the root directory. Make + sure this is indicated in the search directory + information. */ + search_dir_ptr -> fx_dir_entry_name[0] = 0; + + /* Determine if we need to remember this in the last + directory searched return area. */ + if (last_dir_ptr) + { + + /* Yes, return this value to the caller. */ + + /* First, save the name pointer from the list directory pointer. */ + destination_name_ptr = last_dir_ptr -> fx_dir_entry_name; + + /* Copy the entire directory entry structure. */ + *last_dir_ptr = *search_dir_ptr; + + /* Restore the original name buffer pointer. */ + last_dir_ptr -> fx_dir_entry_name = destination_name_ptr; + + /* Pickup pointer to name to copy. */ + source_name_ptr = search_dir_ptr -> fx_dir_entry_name; + + /* Loop to copy the name into the last directory name buffer. */ + for (n = 0; n < FX_MAX_LONG_NAME_LEN; n++) + { + + /* Copy a character. */ + destination_name_ptr[n] = source_name_ptr[n]; + } + } + + /* Set the search directory pointer to NULL to indicate + we are at the root directory. */ + search_dir_ptr = FX_NULL; + } + } + else + { + + /* This is not a directory, we better return not found + since we can't continue the search. */ + if (name_ptr) + { + + /* Return not-found status to caller. */ + return(FX_NOT_FOUND); + } + } + } while (name_ptr); + + /* If you reach this point, the directory is found absolutely, since !found will return directly in the loop above. */ +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + + /* At this point, cache the found information. If a subsequent search for the same name is done, + it will return immediately. */ + + /* Set the index of the saved name string. */ + v= 0; + + /* First, build the full path and name. */ + if ((*original_name != '\\') && (*original_name != '/') && (path_ptr)) + { + + /* Copy the path into the destination. */ + while ((v< (FX_MAX_LAST_NAME_LEN - 1)) && (path_ptr[v])) + { + + /* Copy one character. */ + media_ptr -> fx_media_last_found_name[v] = path_ptr[v]; + + /* Move to next character. */ + v++; + } + } + + /* Now see if there is no directory path symbol in the name itself. */ + if ((*original_name != '\\') && (*original_name != '/')) + { + + /* If there is room, place a directory separator character. */ + if (v < (FX_MAX_LAST_NAME_LEN - 1)) + { + media_ptr -> fx_media_last_found_name[v++] = '/'; + } + } + + /* Now append the name to the path. */ + j = 0; + while ((v < FX_MAX_LAST_NAME_LEN) && (original_name[j])) + { + + /* Copy one character. */ + media_ptr -> fx_media_last_found_name[v] = original_name[j]; + + /* Move to next character. */ + v++; + j++; + } + + /* Null terminate the last name string. */ + if (v< FX_MAX_LAST_NAME_LEN) + { + + /* Null terminate. */ + media_ptr -> fx_media_last_found_name[v] = FX_NULL; + } + else + { + + /* The string is too big, NULL the string so it won't be used in searching. */ + media_ptr -> fx_media_last_found_name[0] = FX_NULL; + } + + /* Determine if there is a search pointer. */ + if (search_dir_ptr) + { + + /* Yes, there is a search directory pointer so save it! */ + media_ptr -> fx_media_last_found_directory = *search_dir_ptr; + + /* Indicate the search directory is valid. */ + media_ptr -> fx_media_last_found_directory_valid = FX_TRUE; + } + else + { + + /* Indicate the search directory is not valid. */ + media_ptr -> fx_media_last_found_directory_valid = FX_FALSE; + } + + /* Copy the directory entry. */ + media_ptr -> fx_media_last_found_entry = *entry_ptr; + + /* Setup the directory entry for the last found internal file name. */ + media_ptr -> fx_media_last_found_entry.fx_dir_entry_name = media_ptr -> fx_media_last_found_file_name; + + /* Copy the actual directory name into the cached directory name. */ + for (index = 0; index < FX_MAX_LONG_NAME_LEN; index++) + { + + /* Copy character into the cached directory name. */ + media_ptr -> fx_media_last_found_file_name[index] = entry_ptr -> fx_dir_entry_name[index]; + + /* See if we have copied the NULL termination character. */ + if (entry_ptr -> fx_dir_entry_name[index] == (CHAR)FX_NULL) + { + + /* Check to see if we use the break to get out of the loop. */ + if (index < (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Yes, not at the end of the string, break. */ + break; + } + } + } +#endif + + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_short_name_get.c b/src/Middlewares/ST/filex/common/src/fx_directory_short_name_get.c new file mode 100644 index 00000000..2a840375 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_short_name_get.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_short_name_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the short file name via the supplied long file */ +/* name. If the long file name is really a short file name, the short */ +/* file name will be returned. */ +/* */ +/* Note, this API is deprecated as fx_directory_short_name_get_extended*/ +/* should be used. The maximum written size to short_file_name could */ +/* be FX_MAX_SHORT_NAME_LEN. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* long_file_name Pointer to long (max 255) name*/ +/* short_file_name Pointer to short (8.3) name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_short_name_get_extended Actual short name get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_short_name_get(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name) +{ + + /* Call the extended version with maximum short name length. */ + return(_fx_directory_short_name_get_extended(media_ptr, long_file_name, short_file_name, FX_MAX_SHORT_NAME_LEN)); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c b/src/Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c new file mode 100644 index 00000000..a52b9836 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_directory_short_name_get_extended.c @@ -0,0 +1,170 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_directory_short_name_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the short file name via the supplied long file */ +/* name. If the long file name is really a short file name, the short */ +/* file name will be returned. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* long_file_name Pointer to long (max 255) name*/ +/* short_file_name Pointer to short (8.3) name */ +/* short_file_name_length Buffer length for short name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the file name in */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_directory_short_name_get_extended(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name, UINT short_file_name_length) +{ + +UINT status; +UINT i; +FX_DIR_ENTRY dir_entry; + + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_DIRECTORY_SHORT_NAME_GET, media_ptr, long_file_name, short_file_name, 0, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied short directory name. */ + status = _fx_directory_search(media_ptr, long_file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Determine if there is a short name. */ + if (dir_entry.fx_dir_entry_short_name[0]) + { + + /* Yes, there is a short name. Copy the short file name portion into the destination string. */ + i = 0; + while ((i < (FX_MAX_SHORT_NAME_LEN - 1)) && (dir_entry.fx_dir_entry_short_name[i]) && (i < (short_file_name_length - 1))) + { + + /* Copy a character of the long file name into the destination name. */ + short_file_name[i] = dir_entry.fx_dir_entry_short_name[i]; + + /* Move to next character. */ + i++; + } + + /* Ensure the short file name is NULL terminated. */ + short_file_name[i] = FX_NULL; + + /* Check if the buffer is too short for the name. */ + if ((i == (short_file_name_length - 1)) && (dir_entry.fx_dir_entry_short_name[i])) + { + + /* Buffer too short, return error. */ + status = FX_BUFFER_ERROR; + } + } + else + { + + /* There is no long file name, simply copy the long file name into the short file name destination. */ + i = 0; + while ((i < (FX_MAX_SHORT_NAME_LEN - 1)) && (dir_entry.fx_dir_entry_name[i]) && (i < (short_file_name_length - 1))) + { + + /* Copy a character of the file name into the destination name. */ + short_file_name[i] = dir_entry.fx_dir_entry_name[i]; + + /* Move to next character. */ + i++; + } + + /* Ensure the short file name is NULL terminated. */ + short_file_name[i] = FX_NULL; + + /* Check if the buffer is too short for the name. */ + if ((i == (short_file_name_length - 1)) && (dir_entry.fx_dir_entry_name[i])) + { + + /* Buffer too short, return error. */ + status = FX_BUFFER_ERROR; + } + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c new file mode 100644 index 00000000..2d037677 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_FAT_log.c @@ -0,0 +1,113 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_add_FAT_log PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts FAT write into log entry and add it into */ +/* log file. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster entry number */ +/* value Next cluster value */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* _fx_utility_32_unsigned_write Write a UINT from memory */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_utility_FAT_entry_write */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_add_FAT_log(FX_MEDIA *media_ptr, ULONG cluster, ULONG value) +{ +ULONG file_size; +FX_FAULT_TOLERANT_FAT_LOG *fat_log; + + /* Increment the size of the log file. */ + file_size = media_ptr -> fx_media_fault_tolerant_file_size + FX_FAULT_TOLERANT_FAT_LOG_ENTRY_SIZE; + + /* Check whether log file exceeds the buffer. */ + if (file_size > media_ptr -> fx_media_fault_tolerant_memory_buffer_size) + { + + /* Log file exceeds the size of the log buffer. This is a failure. */ + return(FX_NO_MORE_SPACE); + } + + /* Set log pointer. */ + fat_log = (FX_FAULT_TOLERANT_FAT_LOG *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + + media_ptr -> fx_media_fault_tolerant_file_size); + + /* Set log type. */ + _fx_utility_16_unsigned_write((UCHAR *)&fat_log -> fx_fault_tolerant_FAT_log_type, + FX_FAULT_TOLERANT_FAT_LOG_TYPE); + + /* Size of log. */ + _fx_utility_16_unsigned_write((UCHAR *)&fat_log -> fx_fault_tolerant_FAT_log_size, + FX_FAULT_TOLERANT_FAT_LOG_ENTRY_SIZE); + + /* Set cluster and value. */ + _fx_utility_32_unsigned_write((UCHAR *)&fat_log -> fx_fault_tolerant_FAT_log_cluster, cluster); + _fx_utility_32_unsigned_write((UCHAR *)&fat_log -> fx_fault_tolerant_FAT_log_value, value); + + /* Update log information. */ + media_ptr -> fx_media_fault_tolerant_file_size = (USHORT)file_size; + media_ptr -> fx_media_fault_tolerant_total_logs += 1; + + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c new file mode 100644 index 00000000..a676db35 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_bitmap_log.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#if defined(FX_ENABLE_FAULT_TOLERANT) && defined(FX_ENABLE_EXFAT) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_add_bitmap_log PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts bitmap write into log entries and add them */ +/* into log file. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster entry number */ +/* value Valud of cluster state */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* _fx_utility_32_unsigned_write Write a UINT from memory */ +/* memcpy Memory Copy */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_exFAT_unicode_entry_write */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_add_bitmap_log(FX_MEDIA *media_ptr, ULONG cluster, ULONG value) +{ +ULONG file_size; +FX_FAULT_TOLERANT_BITMAP_LOG *bitmap_log; + + /* Increment the size of the log file. */ + file_size = media_ptr -> fx_media_fault_tolerant_file_size + FX_FAULT_TOLERANT_BITMAP_LOG_ENTRY_SIZE; + + /* Check whether log file exceeds the buffer. */ + if (file_size > media_ptr -> fx_media_fault_tolerant_memory_buffer_size) + { + + /* Log file exceeds the size of the log buffer. This is a failure. */ + return(FX_NO_MORE_SPACE); + } + + /* Set log pointer. */ + bitmap_log = (FX_FAULT_TOLERANT_BITMAP_LOG *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + + media_ptr -> fx_media_fault_tolerant_file_size); + + /* Set log type. */ + _fx_utility_16_unsigned_write((UCHAR *)&bitmap_log -> fx_fault_tolerant_bitmap_log_type, + FX_FAULT_TOLERANT_BITMAP_LOG_TYPE); + + /* Size of log. */ + _fx_utility_16_unsigned_write((UCHAR *)&bitmap_log -> fx_fault_tolerant_bitmap_log_size, + FX_FAULT_TOLERANT_BITMAP_LOG_ENTRY_SIZE); + + /* Set cluster and value. */ + _fx_utility_32_unsigned_write((UCHAR *)&bitmap_log -> fx_fault_tolerant_bitmap_log_cluster, cluster); + _fx_utility_32_unsigned_write((UCHAR *)&bitmap_log -> fx_fault_tolerant_bitmap_log_value, value); + + /* Update log information. */ + media_ptr -> fx_media_fault_tolerant_file_size = (USHORT)file_size; + media_ptr -> fx_media_fault_tolerant_total_logs += 1; + + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_FAULT_TOLERANT && FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c new file mode 100644 index 00000000..10c0269b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_checksum_log.c @@ -0,0 +1,155 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#if defined(FX_ENABLE_FAULT_TOLERANT) && defined(FX_ENABLE_EXFAT) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_add_checksum_log PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts checksum of exFAT directory entry write into */ +/* log entries and add it into log file. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Original sector to write to */ +/* offset Offset in original sector */ +/* checksum Value of checksum */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_read Read a USHORT from memory */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* _fx_utility_64_unsigned_read Read a ULONG64 from memory */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* memcpy Memory Copy */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_exFAT_unicode_entry_write */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_add_checksum_log(FX_MEDIA *media_ptr, ULONG64 logical_sector, ULONG offset, USHORT checksum) +{ +ULONG logs_remaining; +UCHAR *current_ptr; +ULONG size; +USHORT type; +ULONG log_len; +ULONG64 log_sector; +ULONG log_offset; +FX_FAULT_TOLERANT_DIR_LOG *dir_log; + + /* Get fault tolerant data. */ + logs_remaining = media_ptr -> fx_media_fault_tolerant_total_logs; + + /* Get size of all logs. */ + size = media_ptr -> fx_media_fault_tolerant_file_size - FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET; + + /* Get the first log pointer. */ + current_ptr = media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET + + FX_FAULT_TOLERANT_LOG_CONTENT_HEADER_SIZE; + + /* Loop throught all DIR logs. */ + while (logs_remaining) + { + + /* Check log type. */ + type = (USHORT)_fx_utility_16_unsigned_read(current_ptr); + + /* Get log length. */ + log_len = _fx_utility_16_unsigned_read(current_ptr + 2); + + /* Validate the size value. */ + if (log_len > size) + { + + /* Log file is corrupted. Nothing can be done. Return.*/ + return(FX_FILE_CORRUPT); + } + size -= log_len; + + /* Check log type. */ + if (type == FX_FAULT_TOLERANT_DIR_LOG_TYPE) + { + + /* Set the log pointer. */ + dir_log = (FX_FAULT_TOLERANT_DIR_LOG *)current_ptr; + + /* Get the sector of log. */ + log_sector = _fx_utility_64_unsigned_read((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_sector); + + /* Get the offset of log. */ + log_offset = _fx_utility_32_unsigned_read((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_offset); + + /* Is the checksum for this directory log? */ + if ((log_sector == logical_sector) && (offset == log_offset + 2)) + { + + /* Yes. Update the checksum field. */ + _fx_utility_16_unsigned_write(current_ptr + FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE + 2, checksum); + + /* Return success. */ + return(FX_SUCCESS); + } + } + + /* Decrease the logs_remaining counter. */ + logs_remaining--; + + /* Move to start position of next log entry. */ + current_ptr += log_len; + } + + /* The directory is not found. Log file is corrupted. */ + return(FX_FILE_CORRUPT); +} +#endif /* FX_ENABLE_FAULT_TOLERANT && FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c new file mode 100644 index 00000000..be9ba3da --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_add_dir_log.c @@ -0,0 +1,133 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_add_dir_log PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts directory entry write into log entry and add */ +/* it into log file. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Original sector to write to */ +/* offset Offset in original sector */ +/* data Data of log */ +/* data_size Size of data */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* _fx_utility_32_unsigned_write Write a ULONG from memory */ +/* _fx_utility_64_unsigned_write Write a ULONG64 from memory */ +/* memcpy Memory Copy */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_entry_write */ +/* _fx_directory_exFAT_unicode_entry_write */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_add_dir_log(FX_MEDIA *media_ptr, ULONG64 logical_sector, ULONG offset, + UCHAR *data, ULONG data_size) +{ +ULONG file_size; +FX_FAULT_TOLERANT_DIR_LOG *dir_log; + + /* Increment the size of the log file. */ + file_size = media_ptr -> fx_media_fault_tolerant_file_size + data_size + FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE; + + /* Check whether log file exceeds the buffer. */ + if (file_size > media_ptr -> fx_media_fault_tolerant_memory_buffer_size) + { + + /* Log file exceeds the size of the log buffer. This is a failure. */ + return(FX_NO_MORE_SPACE); + } + + /* Any data to write? */ + if (data_size == 0) + { + + /* No. Just return. */ + return FX_SUCCESS; + } + + /* Set log pointer. */ + dir_log = (FX_FAULT_TOLERANT_DIR_LOG *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + + media_ptr -> fx_media_fault_tolerant_file_size); + + /* Set log type. */ + _fx_utility_16_unsigned_write((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_type, + FX_FAULT_TOLERANT_DIR_LOG_TYPE); + + /* Size of log. */ + _fx_utility_16_unsigned_write((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_size, + data_size + FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE); + + /* Set sector and offset. */ + _fx_utility_64_unsigned_write((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_sector, logical_sector); + _fx_utility_32_unsigned_write((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_offset, offset); + + memcpy(media_ptr -> fx_media_fault_tolerant_memory_buffer + /* Use case of memcpy is verified. */ + media_ptr -> fx_media_fault_tolerant_file_size + FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE, + data, data_size); + + + /* Update log information. */ + media_ptr -> fx_media_fault_tolerant_file_size = (USHORT)file_size; + media_ptr -> fx_media_fault_tolerant_total_logs += 1; + + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c new file mode 100644 index 00000000..bd6b88e7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_apply_logs.c @@ -0,0 +1,335 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_apply_logs PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function applies changes to the file system. The changes are */ +/* already recorded in the fault tolerant log file. Therefore this */ +/* function reads the content of the log entries and apply these */ +/* changes to the file system. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_write Write a logical sector */ +/* _fx_utility_logical_sector_read Read a logical sector */ +/* _fx_utility_16_unsigned_read Read a USHORT from memory */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* _fx_utility_64_unsigned_read Read a ULONG64 from memory */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_exFAT_cluster_state_set Set state of exFAT cluster */ +/* _fx_fault_tolerant_cleanup_FAT_chain Cleanup FAT chain */ +/* memcpy Memory Copy */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_utility_logical_sector_flush Flush written logical sectors */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_fault_tolerant_enable */ +/* _fx_fault_tolerant_transaction_end */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_apply_logs(FX_MEDIA *media_ptr) +{ +UINT status; +ULONG64 log_sector; +ULONG remaining_logs; +ULONG copy_size; +ULONG copy_offset; +UCHAR *current_ptr; +ULONG size; +USHORT log_type; +ULONG log_len; +FX_FAULT_TOLERANT_LOG_HEADER *log_header; +FX_FAULT_TOLERANT_FAT_CHAIN *FAT_chain; +FX_FAULT_TOLERANT_LOG_CONTENT *log_content; +FX_FAULT_TOLERANT_FAT_LOG *fat_log; +FX_FAULT_TOLERANT_DIR_LOG *dir_log; +#ifdef FX_ENABLE_EXFAT +FX_FAULT_TOLERANT_BITMAP_LOG *bitmap_log; +ULONG current_cluster; +ULONG head_cluster; +ULONG tail_cluster; +#endif /* FX_ENABLE_EXFAT */ + + /* Set log header, FAT chain and log content pointer. */ + log_header = (FX_FAULT_TOLERANT_LOG_HEADER *)media_ptr -> fx_media_fault_tolerant_memory_buffer; + FAT_chain = (FX_FAULT_TOLERANT_FAT_CHAIN *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + FX_FAULT_TOLERANT_FAT_CHAIN_OFFSET); + log_content = (FX_FAULT_TOLERANT_LOG_CONTENT *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET); + + /* Find the size of the log file. */ + size = _fx_utility_16_unsigned_read((UCHAR *)&log_header -> fx_fault_tolerant_log_header_total_size); + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_FAULT_TOLERANT_APPLY_LOGS_EXTENSION + + size -= FX_FAULT_TOLERANT_LOG_CONTENT_HEADER_SIZE; + + /* Find the number of log entries. */ + remaining_logs = _fx_utility_16_unsigned_read((UCHAR *)&log_content -> fx_fault_tolerant_log_content_count); + + /* Get start address of logs. */ + current_ptr = (UCHAR *)log_content + FX_FAULT_TOLERANT_LOG_CONTENT_HEADER_SIZE; + + /* Loop through all the logs to apply the changes. */ + while (remaining_logs) + { + + /* Obtain log type of this entry. */ + log_type = (USHORT)_fx_utility_16_unsigned_read(current_ptr); + + /* Read log length. */ + log_len = _fx_utility_16_unsigned_read(current_ptr + 2); + + + /* Validate log entry size. */ + if (log_len > size) + { + + /* Something wrong with log file. */ + return(FX_FILE_CORRUPT); + } + + /* Reduce the total log file size. */ + size -= log_len; + + /* Process log entry by type. */ + switch (log_type) + { + case FX_FAULT_TOLERANT_FAT_LOG_TYPE: + + /* This is a FAT log. */ + fat_log = (FX_FAULT_TOLERANT_FAT_LOG *)current_ptr; + + /* Write FAT entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, + _fx_utility_32_unsigned_read((UCHAR *)&fat_log -> fx_fault_tolerant_FAT_log_cluster), + _fx_utility_32_unsigned_read((UCHAR *)&fat_log -> fx_fault_tolerant_FAT_log_value)); + + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + break; + +#ifdef FX_ENABLE_EXFAT + case FX_FAULT_TOLERANT_BITMAP_LOG_TYPE: + + /* This is a bitmap log. */ + bitmap_log = (FX_FAULT_TOLERANT_BITMAP_LOG *)current_ptr; + + /* Set bitmap entry. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, + _fx_utility_32_unsigned_read((UCHAR *)&bitmap_log -> fx_fault_tolerant_bitmap_log_cluster), + (UCHAR)_fx_utility_32_unsigned_read((UCHAR *)&bitmap_log -> fx_fault_tolerant_bitmap_log_value)); + + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + break; + +#endif /* FX_ENABLE_EXFAT */ + case FX_FAULT_TOLERANT_DIR_LOG_TYPE: + + /* This is a DIR log. */ + dir_log = (FX_FAULT_TOLERANT_DIR_LOG *)current_ptr; + + log_sector = _fx_utility_64_unsigned_read((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_sector); + + /* Get the destination sector. */ + status = _fx_utility_logical_sector_read(media_ptr, + log_sector, + media_ptr -> fx_media_memory_buffer, + ((ULONG) 1), FX_DATA_SECTOR); + + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Set copy information. */ + copy_offset = _fx_utility_32_unsigned_read((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_offset); + + + copy_size = log_len - FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE; + + if ((copy_offset + copy_size) > media_ptr -> fx_media_memory_size) + { + return(FX_FILE_CORRUPT); + } + + /* Copy data into destination sector. */ + memcpy(media_ptr -> fx_media_memory_buffer + copy_offset, /* Use case of memcpy is verified. */ + current_ptr + FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE, copy_size); + + + /* Write back the current logical sector. */ + status = _fx_utility_logical_sector_write(media_ptr, + log_sector, + media_ptr -> fx_media_memory_buffer, + ((ULONG) 1), FX_DIRECTORY_SECTOR); + + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + break; + + default: + + /* Wrong type. */ + return(FX_SECTOR_INVALID); + } + + /* Decrement the remaining log counter. */ + remaining_logs--; + + /* Move to start position of next log entry. */ + current_ptr += log_len; + } + + /* Check whether or not to process FAT chain. */ + if (FAT_chain -> fx_fault_tolerant_FAT_chain_flag & FX_FAULT_TOLERANT_FLAG_FAT_CHAIN_VALID) + { + + /* Free old link of FAT. */ +#ifdef FX_ENABLE_EXFAT + if (FAT_chain -> fx_fault_tolerant_FAT_chain_flag & FX_FAULT_TOLERANT_FLAG_BITMAP_USED) + { + + /* Process FAT chain. */ + /* Get head and tail cluster from FAT chain. */ + head_cluster = _fx_utility_32_unsigned_read((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_original); + tail_cluster = _fx_utility_32_unsigned_read((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_insertion_back); + + if ((head_cluster >= FX_FAT_ENTRY_START) && (head_cluster < media_ptr -> fx_media_fat_reserved)) + { + for (current_cluster = head_cluster; current_cluster < tail_cluster; current_cluster++) + { + + /* Free bitmap. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, current_cluster, FX_EXFAT_BITMAP_CLUSTER_FREE); + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Increase the available clusters in the media control block. */ + media_ptr -> fx_media_available_clusters++; + } + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_fault_tolerant_cleanup_FAT_chain(media_ptr, FX_FAULT_TOLERANT_FAT_CHAIN_CLEANUP); + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, 1, (ULONG64) media_ptr -> fx_media_total_sectors, FX_FALSE); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + + /* Flush FAT table. */ +#ifdef FX_FAULT_TOLERANT +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Flush exFAT bitmap. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + + /* Ensure the new FAT chain is properly written to the media. */ + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + + /* Return success. */ + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c new file mode 100644 index 00000000..ad8faaa1 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_calculate_checksum.c @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_fault_tolerant.h" +#include "fx_utility.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_calculate_checksum PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates checksum for consecutive data. The size */ +/* of the log file is required to be 4-byte aligned. Therefore this */ +/* checksum routine is able to perform 4-byte access. */ +/* */ +/* INPUT */ +/* */ +/* data Pointer to data */ +/* len Data length */ +/* */ +/* OUTPUT */ +/* */ +/* Computed checksum value */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_32_unsigned_read Read a UINT from memory */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_fault_tolerant_enable */ +/* _fx_fault_tolerant_cleanup_FAT_chain */ +/* _fx_fault_tolerant_reset_log_file */ +/* _fx_fault_tolerant_set_FAT_chain */ +/* _fx_fault_tolerant_transaction_end */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +USHORT _fx_fault_tolerant_calculate_checksum(UCHAR *data, UINT len) +{ +ULONG checksum = 0; +ULONG long_value; + + while (len >= 4) + { + + /* Read first long value. */ + long_value = _fx_utility_32_unsigned_read(data); + + /* Calculate checksum. */ + checksum += (long_value >> 16) + (long_value & 0xFFFF); + + /* Decrease length. */ + len -= sizeof(ULONG); + data += sizeof(ULONG); + } + + /* Trim high 16 bits of checksum. */ + checksum = (checksum & 0xFFFF) + (checksum >> 16); + checksum = (checksum & 0xFFFF) + (checksum >> 16); + + return((USHORT)((~checksum) & 0xFFFF)); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c new file mode 100644 index 00000000..bdc0613a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_cleanup_FAT_chain.c @@ -0,0 +1,292 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_cleanup_FAT_chain PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function cleans up FAT chain. In order to prevent failures */ +/* during the link-list walk, and to improve efficiency, this function */ +/* frees the FAT entry chain in sections. For each section, it frees */ +/* FAT entry from the last entry in the chain and works backwards. */ +/* Using this method, if the system fails in the middle of the free */ +/* operation, the head is preserved, and fault tolerant module can */ +/* "redo" this operation next time it starts up. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* operation Recover a failure operation or*/ +/* cleanup old FAT chain */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_cluster_state_get Get state of exFAT cluster */ +/* _fx_utility_exFAT_cluster_state_set Set state of exFAT cluster */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* _fx_utility_32_unsigned_write Write a ULONG from memory */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_fault_tolerant_calculate_checksum Compute Checksum of data */ +/* _fx_fault_tolerant_write_log_file Write log file */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_fault_tolerant_apply_logs */ +/* _fx_fault_tolerant_recover */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_cleanup_FAT_chain(FX_MEDIA *media_ptr, UINT operation) +{ +UINT status; +ULONG current_cluster; +ULONG next_cluster = 0; +ULONG head_cluster; +ULONG tail_cluster; +ULONG cache_count; +ULONG cache_max = FX_FAULT_TOLERANT_CACHE_SIZE >> 2; +ULONG *cache_ptr = media_ptr -> fx_media_fault_tolerant_cache; +ULONG next_session; +USHORT checksum; +ULONG i; +FX_FAULT_TOLERANT_FAT_CHAIN *FAT_chain; +ULONG FAT_sector; +ULONG last_FAT_sector; + + /* Set FAT chain pointer. */ + FAT_chain = (FX_FAULT_TOLERANT_FAT_CHAIN *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + FX_FAULT_TOLERANT_FAT_CHAIN_OFFSET); + + /* Get head and tail cluster. */ + if (operation == FX_FAULT_TOLERANT_FAT_CHAIN_RECOVER) + { + + /* Recover phase. Cleanup (remove) new FAT chain. */ + head_cluster = _fx_utility_32_unsigned_read((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_new); + } + else + { + + /* Cleanup phase. Cleanup (remove) old FAT chain. */ + head_cluster = _fx_utility_32_unsigned_read((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_original); + } + + /* At this point, the head_cluster points to the cluster chain that is to be removed. */ + + /* Tail cluster points to the back of the origianl FAT chain where the new chain is attached to. + The remove process terminates once this cluster is encountered. */ + tail_cluster = _fx_utility_32_unsigned_read((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_insertion_back); + + /* Are there any clusters to free? */ + if ((head_cluster < FX_FAT_ENTRY_START) || (head_cluster >= media_ptr -> fx_media_fat_reserved)) + { + return(FX_SUCCESS); + } + + /* To opimize the deletion process of a long FAT chain, the deletion is done in sessions. During one session, + a set of FAT entries are removed. If one session is interrupted, after restart the deletion process resumes and + picks up from where it left. + + During one deletion session, all FAT entries are between head_cluster(inclusive) and next_session (exclusive). + */ + next_session = _fx_utility_32_unsigned_read((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_next_deletion); + + /* Loop to cleanup all FAT entries. */ + while ((head_cluster >= FX_FAT_ENTRY_START) && (head_cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Initialize. */ + current_cluster = head_cluster; + cache_count = 0; + + /* Loop from head cluster to find entries to cleanup and store this information into cache. */ + do + { + + /* Get the next FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, current_cluster, &next_cluster); + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Whether or not the cluster is occupied. */ + if (next_cluster == FX_FREE_CLUSTER) + { + + /* Current cluster has already been released. */ + break; + } + + /* Cache the FAT list. */ + cache_ptr[cache_count++] = current_cluster; + + /* Move to next cluster. */ + current_cluster = next_cluster; + } while ((next_cluster >= FX_FAT_ENTRY_START) && + (next_cluster < media_ptr -> fx_media_fat_reserved) && + (next_cluster != tail_cluster) && + (cache_count < cache_max)); + + /* Get next session. */ + if (cache_count == cache_max) + { + next_session = next_cluster; + } + + /* Update head cluster and next session into log file. */ + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_next_deletion, next_session); + if (operation == FX_FAULT_TOLERANT_FAT_CHAIN_RECOVER) + { + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_new, head_cluster); + } + else + { + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_original, head_cluster); + } + + /* Update checksum. */ + _fx_utility_16_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_checksumm, 0); + checksum = _fx_fault_tolerant_calculate_checksum((UCHAR *)FAT_chain, FX_FAULT_TOLERANT_FAT_CHAIN_SIZE); + _fx_utility_16_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_checksumm, checksum); + + /* Flush the fault tolerant log into the file system. */ + _fx_fault_tolerant_write_log_file(media_ptr, 0); + + /* Loop to free FAT in cache from back to front. */ + if (cache_count > 0) + { + + /* Get sector of last FAT entry. */ + last_FAT_sector = _fx_utility_FAT_sector_get(media_ptr, cache_ptr[cache_count - 1]); + i = cache_count; + while (i > 0) + { + i--; + + /* Get sector of current FAT entry. */ + FAT_sector = _fx_utility_FAT_sector_get(media_ptr, cache_ptr[i]); + if (FAT_sector != last_FAT_sector) + { + + /* Current FAT entry is located in different sector. Force flush. */ + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Flush exFAT bitmap. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + + /* Update sector of current FAT entry. */ + last_FAT_sector = FAT_sector; + } + + /* Free current_cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, cache_ptr[i], FX_FREE_CLUSTER); + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Free bitmap. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, cache_ptr[i], FX_EXFAT_BITMAP_CLUSTER_FREE); + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Increase the available clusters in the media control block. */ + media_ptr -> fx_media_available_clusters += cache_count; + } + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Flush exFAT bitmap. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + + + /* Get head cluster. */ + if (head_cluster == next_session) + { + break; + } + head_cluster = next_session; + } + + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c new file mode 100644 index 00000000..d165af69 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_create_log_file.c @@ -0,0 +1,415 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_directory.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_create_log_file PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function finds an available cluster used by log file. Then it */ +/* sets the cluster number to boot sector. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_cluster_state_set Set state of exFAT cluster */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_utility_32_unsigned_write Write a ULONG from memory */ +/* _fx_utility_exFAT_system_sector_write Write data into boot sector */ +/* _fx_utility_exFAT_system_area_checksum_write */ +/* Write checksum of boot sector */ +/* _fx_utility_exFAT_bitmap_free_cluster_find */ +/* Find a free cluster */ +/* _fx_utility_logical_sector_read Read a logical sector */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_fault_tolerant_enable */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), replaced */ +/* sector size constant, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_create_log_file(FX_MEDIA *media_ptr) +{ +ULONG clusters; +ULONG FAT_index; +ULONG FAT_value = 0; +UINT found; +UINT status; +UINT i; +#ifdef FX_ENABLE_EXFAT +ULONG checksum; +UINT count; +UCHAR *byte_ptr; +UCHAR cluster_state; +#endif /* FX_ENABLE_EXFAT */ + + /* Yes. Create a log file. */ + /* First find a free cluster. */ + if (media_ptr -> fx_media_available_clusters < media_ptr -> fx_media_fault_tolerant_clusters) + { + + /* Out of disk space. */ + return(FX_NO_MORE_SPACE); + } + + /* Now we need to find the consecutive clusters. */ + clusters = media_ptr -> fx_media_fault_tolerant_clusters; + FAT_index = FX_FAT_ENTRY_START; + found = FX_FALSE; + while (FAT_index <= (media_ptr -> fx_media_total_clusters - clusters + FX_FAT_ENTRY_START)) + { + + /* Determine if enough consecutive FAT entries are available. */ + i = 0; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + do + { + + /* Get cluster state. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, (FAT_index + i), &cluster_state); + + /* Check for a successful status. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Determine if the entry is free. */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_OCCUPIED) + { + break; + } + + /* Otherwise, increment the consecutive FAT indices. */ + i++; + } while (i < clusters); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + do + { + + /* Read a FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, (FAT_index + i), &FAT_value); + + /* Check for a successful status. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Determine if the entry is free. */ + if (FAT_value != FX_FREE_CLUSTER) + { + break; + } + + /* Otherwise, increment the consecutive FAT indices. */ + i++; + } while (i < clusters); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if we found enough FAT entries. */ + if (i >= clusters) + { + + /* Yes, we have found enough FAT entries - set the found + flag and get out of this loop. */ + found = FX_TRUE; + break; + } + else + { +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Find free cluster from exFAT media. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, + FAT_index + i + 1, + &FAT_value); + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + if (FAT_value < FAT_index + i + 1) + { + + /* If we wrapped. */ + FAT_index = media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START; + } + else + { + FAT_index = FAT_value; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + /* Position to the next possibly free FAT entry. */ + FAT_index = FAT_index + i + 1; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + } + + /* Determine if we found enough consecutive clusters to satisfy the + request. */ + if (!found) + { + + /* Not enough contiguous space on the media. Return error status. */ + return(FX_NO_MORE_SPACE); + } + + /* Update the link pointers in the new clusters. */ + for (i = 0; i < (clusters - 1); i++) + { + + /* Update the cluster links. Since the allocation is + sequential, we just have to link each FAT entry to the + next one. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_index + i, FAT_index + i + 1); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as used. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, FAT_index + i, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Now place an EOF in the last cluster entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_index + clusters - 1, media_ptr -> fx_media_fat_last); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as used. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, FAT_index + clusters - 1, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ +#endif + + /* Write start cluster for the file tolerant log file into the boot sector. */ + _fx_utility_32_unsigned_write(media_ptr -> fx_media_fault_tolerant_memory_buffer + FX_FAULT_TOLERANT_BOOT_INDEX, FAT_index); + + /* Write the boot sector. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_BOOT_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_fault_tolerant_memory_buffer; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_BOOT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_BOOT_WRITE, media_ptr, media_ptr -> fx_media_fault_tolerant_memory_buffer, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the boot sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the boot sector was read correctly. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Return the boot sector error status. */ + return(FX_BOOT_ERROR); + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Write backup. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, media_ptr -> fx_media_fault_tolerant_memory_buffer, + FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE, + 1, FX_BOOT_SECTOR); + + /* Determine if the boot sector was read correctly. */ + if (status != FX_SUCCESS) + { + + /* Return the boot sector error status. */ + return(FX_BOOT_ERROR); + } + + /* Calculate checksum. */ + checksum = 0; + byte_ptr = media_ptr -> fx_media_fault_tolerant_memory_buffer; + + /* Calculate Boot Sector Check Sum. */ + for (i = 0; i < media_ptr -> fx_media_bytes_per_sector; i++) + { + if ((FX_EF_VOLUME_FLAGS == i) || + (FX_EF_VOLUME_FLAGS + 1 == i) || + (FX_EF_PERCENT_IN_USE == i)) + { + continue; + } + + checksum = ((checksum >> 1) | (checksum << 31)) + (ULONG)byte_ptr[i]; + } + + for (count = 1; count < FX_EXFAT_FAT_CHECK_SUM_OFFSET; count++) + { + + /* Read sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) count, + media_ptr -> fx_media_fault_tolerant_memory_buffer, ((ULONG) 1), FX_BOOT_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Calculate Check Sum for System Area */ + for (i = 0; i < media_ptr -> fx_media_bytes_per_sector; i++) + { + checksum = ((checksum >> 1) | (checksum << 31)) + (ULONG)byte_ptr[i]; + } + } + + /* Write System Area CheckSum. */ + status = _fx_utility_exFAT_system_area_checksum_write(media_ptr, media_ptr -> fx_media_fault_tolerant_memory_buffer, + &checksum); + + if (status != FX_SUCCESS) + { + + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* Set the start cluster. */ + media_ptr -> fx_media_fault_tolerant_start_cluster = FAT_index; + + /* Decrease available cluster. */ + media_ptr -> fx_media_available_clusters = + media_ptr -> fx_media_available_clusters - clusters; + + /* Return success. */ + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c new file mode 100644 index 00000000..2d699f66 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_enable.c @@ -0,0 +1,519 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_directory.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_enable PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function enables the FileX Fault Tolerant feature. It first */ +/* searches for a valid log file. A valid log file indicates the */ +/* previous write operation failed, and appropriate action now must */ +/* be taken to restore the integrity of the file system. Once the */ +/* recovery effort is completed, the file system is properly restored. */ +/* An empty log file indicates the previous write operaiton was */ +/* successfully completed and no action needs to be taken at this */ +/* point. If the file system does not have a log file, or the */ +/* checksum is not valid, it is an indication either the file system */ +/* is not under the protection of FileX Fault Tolerant. A new log */ +/* file is created. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* memory_buffer Pointer to memory buffer. */ +/* memory_size Size of memory buffer. */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_fault_tolerant_calculate_checksum Compute Checksum of data */ +/* _fx_fault_tolerant_apply_logs Apply logs into file system */ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* _fx_fault_tolerant_read_log_file Read log file to cache */ +/* _fx_utility_exFAT_cluster_state_get Get state of exFAT cluster */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_16_unsigned_read Read a USHORT from memory */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_enable(FX_MEDIA *media_ptr, VOID *memory_buffer, UINT memory_size) +{ +ULONG start_cluster; +ULONG FAT_value; +UINT status; +ULONG checksum; +ULONG total_size; +FX_FAULT_TOLERANT_LOG_HEADER *log_header; +FX_FAULT_TOLERANT_FAT_CHAIN *FAT_chain; +ULONG cluster_number; +ULONG i, j; +ULONG FAT_entry, FAT_sector, FAT_read_sectors; +ULONG bytes_in_buffer; +ULONG clusters; +ULONG bytes_per_sector; +ULONG bytes_per_cluster; + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Calculate clusters needed for fault tolerant log. */ + bytes_per_sector = media_ptr -> fx_media_bytes_per_sector; + bytes_per_cluster = bytes_per_sector * media_ptr -> fx_media_sectors_per_cluster; + + if (bytes_per_cluster == 0) + { + + /* Release media protection. */ + FX_UNPROTECT + + return(FX_MEDIA_INVALID); + } + + clusters = (FX_FAULT_TOLERANT_MAXIMUM_LOG_FILE_SIZE + bytes_per_cluster - 1) / bytes_per_cluster; + media_ptr -> fx_media_fault_tolerant_clusters = clusters; + + /* Check buffer size requirement. */ + if (memory_size < bytes_per_sector) + { + + /* Release media protection. */ + FX_UNPROTECT + + return(FX_NOT_ENOUGH_MEMORY); + } + + + if (media_ptr -> fx_media_FAT32_additional_info_sector) + { + + /* A 32-bit FAT is present. Read directly into the logical sector + cache memory to optimize I/O on larger devices. Since we are looking for + values of zero, endian issues are not important. */ + /* Force update the available cluster. */ + + /* Invalidate the current logical sector cache. */ + _fx_utility_logical_sector_flush(media_ptr, ((ULONG64) 1), (ULONG64) (media_ptr -> fx_media_total_sectors), FX_TRUE); + + /* Reset the memory pointer. */ + media_ptr -> fx_media_memory_buffer = media_ptr -> fx_media_sector_cache[0].fx_cached_sector_memory_buffer; + + /* Reset the available cluster. */ + media_ptr -> fx_media_available_clusters = 0; + + /* Loop through all FAT sectors in the primary FAT. The first two entries are + examined in this loop, but they are always unavailable. */ + cluster_number = 0; + for (i = 0; i < media_ptr -> fx_media_sectors_per_FAT; i = i + media_ptr -> fx_media_sector_cache_size) + { + + /* Calculate the starting next FAT sector. */ + FAT_sector = media_ptr -> fx_media_reserved_sectors + i; + + /* Calculate how many sectors to read. */ + FAT_read_sectors = media_ptr -> fx_media_sectors_per_FAT - i; + + /* Determine if there is not enough memory to read the remaining FAT sectors. */ + if (FAT_read_sectors > media_ptr -> fx_media_sector_cache_size) + { + FAT_read_sectors = media_ptr -> fx_media_sector_cache_size; + } + + /* Read the FAT sectors directly from the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; + media_ptr -> fx_media_driver_logical_sector = FAT_sector; + media_ptr -> fx_media_driver_sectors = FAT_read_sectors; + media_ptr -> fx_media_driver_sector_type = FX_FAT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_READ, media_ptr, FAT_sector, FAT_read_sectors, media_ptr -> fx_media_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the FAT sectors. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the read was successful. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + return(FX_FAT_READ_ERROR); + } + + /* Calculate the number of bytes in the buffer. */ + bytes_in_buffer = (media_ptr -> fx_media_bytes_per_sector * FAT_read_sectors); + + /* Walk through the sector cache memory to search for available clusters and the first + available if not already found. */ + for (j = 0; j < bytes_in_buffer;) + { + + /* Pickup 32-bit FAT entry. */ + FAT_entry = *((ULONG *)&(media_ptr -> fx_media_memory_buffer[j])); + + /* Advance to next FAT entry. */ + j = j + 4; + + /* Determine if the FAT entry is free. */ + if (FAT_entry == FX_FREE_CLUSTER) + { + + /* Entry is free, increment available clusters. */ + media_ptr -> fx_media_available_clusters++; + + /* Determine if the starting free cluster has been found yet. */ + if (media_ptr -> fx_media_cluster_search_start == 0) + { + + /* Remember the first free cluster to start further searches from. */ + media_ptr -> fx_media_cluster_search_start = cluster_number; + } + } + + /* Increment the cluster number. */ + cluster_number++; + + /* Determine if we have reviewed all FAT entries. */ + if (cluster_number >= (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Yes, we have looked at all the FAT entries. */ + + /* Ensure that the outer loop terminates as well. */ + i = media_ptr -> fx_media_sectors_per_FAT; + break; + } + } + } + } + + /* Store memory buffer and size. */ + media_ptr -> fx_media_fault_tolerant_memory_buffer = (UCHAR *)memory_buffer; + if (memory_size > (clusters * bytes_per_cluster)) + { + media_ptr -> fx_media_fault_tolerant_memory_buffer_size = clusters * bytes_per_cluster; + } + else + { + media_ptr -> fx_media_fault_tolerant_memory_buffer_size = memory_size / bytes_per_sector * bytes_per_sector; + } + + /* Read the boot sector from the device. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_BOOT_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = (UCHAR *)memory_buffer; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_BOOT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_BOOT_READ, media_ptr, memory_buffer, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the boot sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the boot sector was read correctly. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the boot sector error status. */ + return(FX_BOOT_ERROR); + } + + /* Check whether the boot index is used. */ + start_cluster = _fx_utility_32_unsigned_read((UCHAR *)memory_buffer + FX_FAULT_TOLERANT_BOOT_INDEX); + if (start_cluster != 0) + { + + /* The location of the fault tolerant log file is found. Need to verify the integrity of the log file. */ + if ((start_cluster >= FX_FAT_ENTRY_START) && (start_cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Check whether this cluster is used. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + UCHAR cluste_state; + + for (i = 0; i < clusters; i++) + { + + /* Update Bitmap */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, start_cluster + i, &cluste_state); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + if (cluste_state != FX_EXFAT_BITMAP_CLUSTER_OCCUPIED) + { + + /* Mark invalid. */ + start_cluster = 0; + break; + } + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + for (i = 0; i < clusters; i++) + { + + /* Read FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, start_cluster + i, &FAT_value); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + if (i < clusters - 1) + { + if (FAT_value != (start_cluster + i + 1)) + { + + /* Mark invalid. */ + start_cluster = 0; + break; + } + } + else if (FAT_value != media_ptr -> fx_media_fat_last) + { + + /* Mark invalid. */ + start_cluster = 0; + break; + } + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Is this FAT entry occupied by log file? */ + if (start_cluster) + { + + /* Set the start cluster. */ + media_ptr -> fx_media_fault_tolerant_start_cluster = start_cluster; + + /* Read log file from file system to memory. */ + status = _fx_fault_tolerant_read_log_file(media_ptr); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Set log header and FAT chain pointer. */ + log_header = (FX_FAULT_TOLERANT_LOG_HEADER *)media_ptr -> fx_media_fault_tolerant_memory_buffer; + FAT_chain = (FX_FAULT_TOLERANT_FAT_CHAIN *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_FAT_CHAIN_OFFSET); + + /* Verify ID field. */ + if (_fx_utility_32_unsigned_read((UCHAR *)&log_header -> fx_fault_tolerant_log_header_id) == FX_FAULT_TOLERANT_ID) + { + + /* Calculate checksum of log header. */ + checksum = _fx_fault_tolerant_calculate_checksum((UCHAR *)log_header, + FX_FAULT_TOLERANT_LOG_HEADER_SIZE); + + if (checksum == 0) + { + + /* Fault tolerant log file is valid. */ + /* Initialize file size. */ + total_size = _fx_utility_16_unsigned_read((UCHAR *)&log_header -> fx_fault_tolerant_log_header_total_size); + media_ptr -> fx_media_fault_tolerant_file_size = total_size; + + + /* Verify the checksum of the FAT chain. */ + checksum = _fx_fault_tolerant_calculate_checksum((UCHAR *)FAT_chain, + FX_FAULT_TOLERANT_FAT_CHAIN_SIZE); + + if (checksum == 0) + { + + /* Checksum of FAT chain is correct. */ + + if (total_size > (FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET + FX_FAULT_TOLERANT_LOG_HEADER_SIZE)) + { + + /* Log content is present. */ + /* Now verify the checksum of log content. */ + checksum = _fx_fault_tolerant_calculate_checksum((media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET), + (total_size - FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET)); + if (checksum == 0) + { + + /* Checksum of log content is correct. */ + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_FAULT_TOLERANT_ENABLE_EXTENSION + + /* This is the situation where the log file contains log entries. This is an indication + that previous write operation did not complete successfully. Need to apply the log entries + to recover the previous write operation, effectively to finish up the previous write operation. */ + status = _fx_fault_tolerant_apply_logs(media_ptr); + } + } + else + { + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_FAULT_TOLERANT_ENABLE_EXTENSION + + /* The log file does not contain log content but the FAT chain operation information is present. + This is the situation where the FAT chain has been modified but the rest of the content of these + clusters are not updated yet. In this situation, the previous FAT chain operation needs to be + reverted to restore the file system back to its state prior to the write operation. */ + status = _fx_fault_tolerant_recover(media_ptr); + } + + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } + } + } + } + } + else + { + + /* Not a valid cluster number. Set the flag to create a new log file. */ + start_cluster = 0; + } + } + + /* Check whether or not to create a log file. */ + if (start_cluster == 0) + { + + /* Create log file. */ + status = _fx_fault_tolerant_create_log_file(media_ptr); + + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } + + /* Reset log file. */ + status = _fx_fault_tolerant_reset_log_file(media_ptr); + + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Mark fault tolerant feature is enabled. */ + media_ptr -> fx_media_fault_tolerant_enabled = FX_TRUE; + + /* Reset the transaction count. */ + media_ptr -> fx_media_fault_tolerant_transaction_count = 0; + + /* Initialize the sector number of cached FAT entries. */ + media_ptr -> fx_media_fault_tolerant_cached_FAT_sector = 0; + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(FX_SUCCESS); +} + +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c new file mode 100644 index 00000000..e983c970 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_FAT.c @@ -0,0 +1,193 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_read_FAT PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads value of a FAT entry from log file if it */ +/* exists. During file or directory operations with Fault Tolerant */ +/* protection, intermediate operations are written to the fault */ +/* tolerant log files. Therefore, FAT-entry read should search for */ +/* fault tolerant log before the request can be passed to normal FAT */ +/* entry read routine. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster entry number */ +/* value Pointer to value for the entry*/ +/* log_type FAT or bitmap */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_read Read a USHORT from memory */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_utility_exFAT_cluster_state_get */ +/* _fx_utility_FAT_entry_read */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_read_FAT(FX_MEDIA *media_ptr, ULONG cluster, ULONG *value, ULONG log_type) +{ +ULONG logs_remaining; +UCHAR *current_ptr; +UCHAR found = FX_FALSE; +ULONG size; +USHORT type; +ULONG log_len; +FX_FAULT_TOLERANT_FAT_LOG *fat_log; +#ifdef FX_ENABLE_EXFAT +FX_FAULT_TOLERANT_BITMAP_LOG *bitmap_log; +#endif + + + /* Get fault tolerant data. */ + logs_remaining = media_ptr -> fx_media_fault_tolerant_total_logs; + + /* Any redo logs? */ + if (logs_remaining == 0) + { + + /* No. Just return. */ + return(FX_READ_CONTINUE); + } + + /* Get size of all logs. */ + size = media_ptr -> fx_media_fault_tolerant_file_size - FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET; + + /* Get the first log pointer. */ + current_ptr = media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET + + FX_FAULT_TOLERANT_LOG_CONTENT_HEADER_SIZE; + + /* Loop throught all FAT logs. */ + while (logs_remaining) + { + + /* Check log type. */ + type = (USHORT)_fx_utility_16_unsigned_read(current_ptr); + + /* Get log length. */ + log_len = _fx_utility_16_unsigned_read(current_ptr + 2); + + /* Validate the size value. */ + if (log_len > size) + { + + /* Log file is corrupted. Nothing can be done. Return.*/ + return(FX_FILE_CORRUPT); + } + size -= log_len; + + /* Check log type. */ + if (type == log_type) + { + + /* This is the log with same type . */ + /* Get the log pointer. */ +#ifdef FX_ENABLE_EXFAT + if (type == FX_FAULT_TOLERANT_BITMAP_LOG_TYPE) + { + bitmap_log = (FX_FAULT_TOLERANT_BITMAP_LOG *)current_ptr; + + /* Is this bitmap log entry the one looking for? */ + if (_fx_utility_32_unsigned_read((UCHAR *)&bitmap_log -> fx_fault_tolerant_bitmap_log_cluster) == cluster) + { + + /* Yes, it is. */ + *value = _fx_utility_32_unsigned_read((UCHAR *)&bitmap_log -> fx_fault_tolerant_bitmap_log_value); + + /* Do not return since there may be more than one log for this cluster. */ + found = FX_TRUE; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + fat_log = (FX_FAULT_TOLERANT_FAT_LOG *)current_ptr; + + /* Is this FAT log entry the one looking for? */ + if (_fx_utility_32_unsigned_read((UCHAR *)&fat_log -> fx_fault_tolerant_FAT_log_cluster) == cluster) + { + + /* Yes, it is. */ + *value = _fx_utility_32_unsigned_read((UCHAR *)&fat_log -> fx_fault_tolerant_FAT_log_value); + + /* Do not return since there may be more than one log for this cluster. */ + found = FX_TRUE; + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Decrease the logs_remaining counter. */ + logs_remaining--; + + /* Get next log pointer. */ + current_ptr += log_len; + } + + if (found != FX_TRUE) + { + + /* Pass the request to FAT entry read. */ + return(FX_READ_CONTINUE); + } + + /* Return success. */ + return(FX_SUCCESS); +} + +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c new file mode 100644 index 00000000..89e32bc4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_directory_sector.c @@ -0,0 +1,178 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_read_directory_sector PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles directory sector read requests. During file or*/ +/* directory operations with Fault Tolerant protection, intermediate */ +/* operations are written to the fault tolerant log files. Therefore, */ +/* sector read should search for fault tolerant log before the request */ +/* can be passed to normal directory entry read routine. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Logical sector number */ +/* buffer_ptr Pointer of receiving buffer */ +/* sectors Number of sectors to read */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_read Read a USHORT from memory */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* memcpy Memory Copy */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_utility_logical_sector_read */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_read_directory_sector(FX_MEDIA *media_ptr, ULONG64 logical_sector, + VOID *buffer_ptr, ULONG64 sectors) +{ +ULONG logs_remaining; +ULONG copy_offset; +ULONG copy_size; +UCHAR *current_ptr; +UCHAR *current_buffer_ptr; +ULONG size; +USHORT type; +ULONG log_len; +ULONG64 log_sector; +FX_FAULT_TOLERANT_DIR_LOG *dir_log; + + /* Get fault tolerant data. */ + logs_remaining = media_ptr -> fx_media_fault_tolerant_total_logs; + + /* Any redo logs? */ + if (logs_remaining == 0) + { + + /* No. Just return. */ + return(FX_SUCCESS); + } + + /* Get size of all logs. */ + size = media_ptr -> fx_media_fault_tolerant_file_size - FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET; + + /* Get the first log pointer. */ + current_ptr = media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET + + FX_FAULT_TOLERANT_LOG_CONTENT_HEADER_SIZE; + + /* Loop throught all FAT logs. */ + while (logs_remaining) + { + + /* Check log type. */ + type = (USHORT)_fx_utility_16_unsigned_read(current_ptr); + + /* Get log length. */ + log_len = _fx_utility_16_unsigned_read(current_ptr + 2); + + /* Validate the size value. */ + if (log_len > size) + { + + /* Log file is corrupted. Nothing can be done. Return.*/ + return(FX_FILE_CORRUPT); + } + size -= log_len; + + /* Check log type. */ + if (type == FX_FAULT_TOLERANT_DIR_LOG_TYPE) + { + + /* Get the log pointer. */ + dir_log = (FX_FAULT_TOLERANT_DIR_LOG *)current_ptr; + + /* Get the sector of log. */ + log_sector = _fx_utility_64_unsigned_read((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_sector); + + /* Is this log sector in the range of sectors to read? */ + if ((log_sector >= logical_sector) && (log_sector < logical_sector + sectors)) + { + + /* Yes. Update the content in this sector. */ + current_buffer_ptr = ((UCHAR *)buffer_ptr) + (log_sector - logical_sector) * + media_ptr -> fx_media_bytes_per_sector; + + /* Set copy information. */ + copy_offset = _fx_utility_32_unsigned_read((UCHAR *)&dir_log -> fx_fault_tolerant_dir_log_offset); + + copy_size = log_len - FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE; + + if ((copy_offset + copy_size) > media_ptr -> fx_media_bytes_per_sector) + { + return(FX_FILE_CORRUPT); + } + + /* Copy data into destination sector. */ + memcpy(current_buffer_ptr + copy_offset, /* Use case of memcpy is verified. */ + current_ptr + FX_FAULT_TOLERANT_DIR_LOG_ENTRY_SIZE, copy_size); + } + } + + /* Decrease the logs_remaining counter. */ + logs_remaining--; + + /* Move to start position of next log entry. */ + current_ptr += log_len; + } + + /* Return success. */ + return(FX_SUCCESS); +} + +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c new file mode 100644 index 00000000..a66c59ec --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_read_log_file.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_read_log_file PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the entire log file from file system into the */ +/* fault tolerant cache. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_read Read a logical sector */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_fault_tolerant_enable */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_read_log_file(FX_MEDIA *media_ptr) +{ +UINT status; +ULONG sectors; +ULONG start_sector; + + /* Calculate count of sectors to read. */ + sectors = media_ptr -> fx_media_fault_tolerant_memory_buffer_size / media_ptr -> fx_media_bytes_per_sector; + + /* Calculate the start sector of log file. */ + start_sector = (media_ptr -> fx_media_fault_tolerant_start_cluster - FX_FAT_ENTRY_START) * + media_ptr -> fx_media_sectors_per_cluster + + media_ptr -> fx_media_data_sector_start; + + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) start_sector, + media_ptr -> fx_media_fault_tolerant_memory_buffer, + sectors, FX_DATA_SECTOR); + + /* Return the status. */ + return(status); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c new file mode 100644 index 00000000..fc736c2e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_recover.c @@ -0,0 +1,168 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_recover PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called after the FAT chain is been updated but */ +/* the rest of the write operation fails. At this point, there is */ +/* need to undo the FAT chain operation, which includes: */ +/* (1) Remove newly allocated FAT entries; */ +/* (2) Restore the origianl FAT chain removed during the FAT chain */ +/* update; */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_fault_tolerant_cleanup_FAT_chain Cleanup FAT chain */ +/* _fx_utility_32_unsigned_read Read a ULONG from memory */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_attributes_set */ +/* _fx_directory_create */ +/* _fx_directory_delete */ +/* _fx_directory_rename */ +/* _fx_file_allocate */ +/* _fx_file_attributes_set */ +/* _fx_file_best_effort_allocate */ +/* _fx_file_create */ +/* _fx_file_delete */ +/* _fx_file_rename */ +/* _fx_file_truncate */ +/* _fx_file_truncate_release */ +/* _fx_file_write */ +/* _fx_unicode_directory_create */ +/* _fx_unicode_file_create */ +/* _fx_fault_tolerant_enable */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_recover(FX_MEDIA *media_ptr) +{ +UINT status; +ULONG insertion_front; +ULONG origianl_head_cluster; +FX_FAULT_TOLERANT_FAT_CHAIN *FAT_chain; + + + /* Set fault tolerant state to IDLE. */ + media_ptr -> fx_media_fault_tolerant_state = FX_FAULT_TOLERANT_STATE_IDLE; + + /* Set FAT chain pointer. */ + FAT_chain = (FX_FAULT_TOLERANT_FAT_CHAIN *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + FX_FAULT_TOLERANT_FAT_CHAIN_OFFSET); + + /* Whether or not the supplied FAT chain is valid. */ + if (!(FAT_chain -> fx_fault_tolerant_FAT_chain_flag & FX_FAULT_TOLERANT_FLAG_FAT_CHAIN_VALID)) + { + + /* Invalid, which indiates the FAT chain has been cleaned up already. In this case, just return. */ + return(FX_SUCCESS); + } + + /* Set FAT chain pointer. */ + FAT_chain = (FX_FAULT_TOLERANT_FAT_CHAIN *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + FX_FAULT_TOLERANT_FAT_CHAIN_OFFSET); + + /* Recover FAT chain. */ + status = _fx_fault_tolerant_cleanup_FAT_chain(media_ptr, FX_FAULT_TOLERANT_FAT_CHAIN_RECOVER); + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Now, link the front of the insertion point back to the origianl FAT chain. */ + insertion_front = _fx_utility_32_unsigned_read((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_insertion_front); + origianl_head_cluster = _fx_utility_32_unsigned_read((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_original); + + if (insertion_front != FX_FREE_CLUSTER) + { + + /* Front of the insertion point exists. Link the origianl chain back to the front of the insertion point. */ + status = _fx_utility_FAT_entry_write(media_ptr, insertion_front, origianl_head_cluster); + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + } + + /* New FAT chain is always linked by FAT entries. */ + + /* Flush FAT table. */ +#ifdef FX_FAULT_TOLERANT +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Flush exFAT bitmap. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + + /* Ensure the new FAT chain is properly written to the media. */ + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + + /* Return success. */ + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c new file mode 100644 index 00000000..94d06d08 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_reset_log_file.c @@ -0,0 +1,142 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_directory.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_reset_log_file PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function removes all log entries from the log file, and */ +/* it to its initial state. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* _fx_utility_32_unsigned_write Write a ULONG from memory */ +/* _fx_fault_tolerant_calculate_checksum Compute Checksum of data */ +/* _fx_fault_tolerant_write_log_file Write log file */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_attributes_set */ +/* _fx_directory_create */ +/* _fx_directory_delete */ +/* _fx_directory_rename */ +/* _fx_file_allocate */ +/* _fx_file_attributes_set */ +/* _fx_file_best_effort_allocate */ +/* _fx_file_create */ +/* _fx_file_delete */ +/* _fx_file_rename */ +/* _fx_file_truncate */ +/* _fx_file_truncate_release */ +/* _fx_file_write */ +/* _fx_unicode_directory_create */ +/* _fx_unicode_file_create */ +/* _fx_fault_tolerant_enable */ +/* _fx_fault_tolerant_transaction_end */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ + +UINT _fx_fault_tolerant_reset_log_file(FX_MEDIA *media_ptr) +{ +UINT status; +USHORT checksum; +FX_FAULT_TOLERANT_LOG_HEADER *log_header; +FX_FAULT_TOLERANT_FAT_CHAIN *FAT_chain; +FX_FAULT_TOLERANT_LOG_CONTENT *log_content; + + /* Set log header, FAT chain and log content pointer. */ + log_header = (FX_FAULT_TOLERANT_LOG_HEADER *)media_ptr -> fx_media_fault_tolerant_memory_buffer; + FAT_chain = (FX_FAULT_TOLERANT_FAT_CHAIN *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_FAT_CHAIN_OFFSET); + log_content = (FX_FAULT_TOLERANT_LOG_CONTENT *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET); + + /* Reset the log file header. */ + _fx_utility_32_unsigned_write((UCHAR *)&log_header -> fx_fault_tolerant_log_header_id, FX_FAULT_TOLERANT_ID); + _fx_utility_16_unsigned_write((UCHAR *)&log_header -> fx_fault_tolerant_log_header_total_size, + (FX_FAULT_TOLERANT_LOG_HEADER_SIZE + FX_FAULT_TOLERANT_FAT_CHAIN_SIZE)); + _fx_utility_16_unsigned_write((UCHAR *)&log_header -> fx_fault_tolerant_log_header_checksum, 0); + log_header -> fx_fault_tolerant_log_header_version_major = FX_FAULT_TOLERANT_VERSION_MAJOR; + log_header -> fx_fault_tolerant_log_header_version_minor = FX_FAULT_TOLERANT_VERSION_MINOR; + _fx_utility_16_unsigned_write((UCHAR *)&log_header -> fx_fault_tolerant_log_header_reserved, 0); + checksum = _fx_fault_tolerant_calculate_checksum((UCHAR *)log_header, FX_FAULT_TOLERANT_LOG_HEADER_SIZE); + _fx_utility_16_unsigned_write((UCHAR *)&log_header -> fx_fault_tolerant_log_header_checksum, checksum); + + /* Reset the undo log section. */ + _fx_utility_16_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_checksumm, 0xFFFF); + FAT_chain -> fx_fault_tolerant_FAT_chain_flag = 0; + FAT_chain -> fx_fault_tolerant_FAT_chain_reserved = 0; + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_insertion_front, 0); + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_new, 0); + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_original, 0); + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_insertion_back, 0); + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_next_deletion, 0); + + /* Reset log content header. */ + _fx_utility_16_unsigned_write((UCHAR *)&log_content -> fx_fault_tolerant_log_content_checksum, 0xFFFF); + _fx_utility_16_unsigned_write((UCHAR *)&log_content -> fx_fault_tolerant_log_content_count, 0xFFFF); + + /* No matter success or fail, close this transaction. */ + media_ptr -> fx_media_fault_tolerant_state = FX_FAULT_TOLERANT_STATE_IDLE; + + /* Write the log header and FAT chain. */ + status = _fx_fault_tolerant_write_log_file(media_ptr, 0); + + /* Return the status. */ + return(status); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c new file mode 100644 index 00000000..5f1f2e60 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_set_FAT_chain.c @@ -0,0 +1,133 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_set_FAT_chain PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets data of FAT chain. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* use_bitmap Whether or not the orignal */ +/* FAT chain uses bitmap */ +/* insertion_front Previous cluster of head */ +/* new_head_cluster Head cluster of new chain */ +/* origianl_head_cluster Head cluster of the original */ +/* chain */ +/* insertion_back next cluster of chain tail */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* _fx_utility_32_unsigned_write Write a ULONG from memory */ +/* _fx_fault_tolerant_calculate_checksum Compute Checksum of data */ +/* _fx_fault_tolerant_write_log_file Write log file */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_file_allocate */ +/* _fx_file_best_effort_allocate */ +/* _fx_file_delete */ +/* _fx_file_truncate_release */ +/* _fx_file_write */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_set_FAT_chain(FX_MEDIA *media_ptr, UINT use_bitmap, ULONG insertion_front, + ULONG new_head_cluster, ULONG original_head_cluster, + ULONG insertion_back) +{ +UINT status; +USHORT checksum; +UCHAR flag = FX_FAULT_TOLERANT_FLAG_FAT_CHAIN_VALID; +FX_FAULT_TOLERANT_FAT_CHAIN *FAT_chain; + + /* Set FAT chain pointer. */ + FAT_chain = (FX_FAULT_TOLERANT_FAT_CHAIN *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + FX_FAULT_TOLERANT_FAT_CHAIN_OFFSET); + +#ifdef FX_ENABLE_EXFAT + /* Check flag for bitmap. */ + if (use_bitmap == FX_TRUE) + { + flag |= FX_FAULT_TOLERANT_FLAG_BITMAP_USED; + } +#else + /* Parameters not used. Avoid compiler warnings. */ + FX_PARAMETER_NOT_USED(use_bitmap); +#endif /* FX_ENABLE_EXFAT */ + + + /* Reset checksum first. */ + _fx_utility_16_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_checksumm, 0); + + /* Set clusters. */ + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_insertion_front, insertion_front); + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_new, new_head_cluster); + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_head_original, original_head_cluster); + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_insertion_back, insertion_back); + _fx_utility_32_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_next_deletion, FX_FREE_CLUSTER); + + /* Set flag and reserved. */ + FAT_chain -> fx_fault_tolerant_FAT_chain_flag = flag; + FAT_chain -> fx_fault_tolerant_FAT_chain_reserved = (UCHAR)0; + + /* Calculate checksum. */ + checksum = _fx_fault_tolerant_calculate_checksum((UCHAR *)FAT_chain, FX_FAULT_TOLERANT_FAT_CHAIN_SIZE); + _fx_utility_16_unsigned_write((UCHAR *)&FAT_chain -> fx_fault_tolerant_FAT_chain_checksumm, checksum); + + /* Write the log header and FAT chain. */ + status = _fx_fault_tolerant_write_log_file(media_ptr, 0); + + /* Return the status. */ + return(status); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c new file mode 100644 index 00000000..1b26dfc7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_end.c @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_fault_tolerant.h" +#include "fx_utility.h" + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_transaction_end PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function completes a file system update operation protected */ +/* by fault tolerant. This function first computes the checksum */ +/* for the log entries, flush the log file to the file system (a */ +/* necessary step to record vital information for the file system to */ +/* recover, in case the update operation fails midway). After the */ +/* log entries are written to the physical medium, the actualy file */ +/* system changes (FAT table, directory entries) are applied. */ +/* */ +/* If the file system changes are successfully applied, the log */ +/* entries can be removed. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_write Write a USHORT from memory */ +/* _fx_fault_tolerant_apply_logs Apply logs into file system */ +/* _fx_fault_tolerant_calculate_checksum Compute Checksum of data */ +/* _fx_fault_tolerant_write_log_file Write log file */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_attributes_set */ +/* _fx_directory_create */ +/* _fx_directory_delete */ +/* _fx_directory_rename */ +/* _fx_file_allocate */ +/* _fx_file_attributes_set */ +/* _fx_file_best_effort_allocate */ +/* _fx_file_create */ +/* _fx_file_delete */ +/* _fx_file_rename */ +/* _fx_file_truncate */ +/* _fx_file_truncate_release */ +/* _fx_file_write */ +/* _fx_unicode_directory_create */ +/* _fx_unicode_file_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_transaction_end(FX_MEDIA *media_ptr) +{ +ULONG relative_sector; +UINT status; +USHORT checksum; +UINT offset; +FX_FAULT_TOLERANT_LOG_HEADER *log_header; +FX_FAULT_TOLERANT_LOG_CONTENT *log_content; + + /* Is fault tolerant enabled? */ + if (media_ptr -> fx_media_fault_tolerant_enabled == FX_FALSE) + { + return(FX_SUCCESS); + } + + /* Decrease the transaction. */ + media_ptr -> fx_media_fault_tolerant_transaction_count--; + + /* Is transaction finished? */ + if (media_ptr -> fx_media_fault_tolerant_transaction_count != 0) + { + return(FX_SUCCESS); + } + + /* Close this transaction. */ + media_ptr -> fx_media_fault_tolerant_state = FX_FAULT_TOLERANT_STATE_IDLE; + + /* Set log header and FAT chain pointer. */ + log_header = (FX_FAULT_TOLERANT_LOG_HEADER *)media_ptr -> fx_media_fault_tolerant_memory_buffer; + log_content = (FX_FAULT_TOLERANT_LOG_CONTENT *)(media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET); + + /* Reset checksum field and update log entry counter field. */ + _fx_utility_16_unsigned_write((UCHAR *)&log_content -> fx_fault_tolerant_log_content_checksum, 0); + _fx_utility_16_unsigned_write((UCHAR *)&log_content -> fx_fault_tolerant_log_content_count, + media_ptr -> fx_media_fault_tolerant_total_logs); + + /* Now calculate the checksum of log content. */ + checksum = _fx_fault_tolerant_calculate_checksum((media_ptr -> fx_media_fault_tolerant_memory_buffer + + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET), + (media_ptr -> fx_media_fault_tolerant_file_size - + FX_FAULT_TOLERANT_LOG_CONTENT_OFFSET)); + + /* Record checksum field of log content. */ + _fx_utility_16_unsigned_write((UCHAR *)&log_content -> fx_fault_tolerant_log_content_checksum, checksum); + + /* Record log header. */ + _fx_utility_16_unsigned_write((UCHAR *)&log_header -> fx_fault_tolerant_log_header_total_size, + media_ptr -> fx_media_fault_tolerant_file_size); + _fx_utility_16_unsigned_write((UCHAR *)&log_header -> fx_fault_tolerant_log_header_checksum, 0); + + /* Calculate checksum of the header. */ + checksum = _fx_fault_tolerant_calculate_checksum((UCHAR *)log_header, FX_FAULT_TOLERANT_LOG_HEADER_SIZE); + + /* Record checksum field of the header. */ + _fx_utility_16_unsigned_write((UCHAR *)&log_header -> fx_fault_tolerant_log_header_checksum, checksum); + + /* Flush log content and flush first sector at last. The first sector contains size of total log file. + * The log file will contain wrong value of size when it is interrupted after first sector flushed to file system. */ + relative_sector = 1; + offset = media_ptr -> fx_media_bytes_per_sector; + while (offset < media_ptr -> fx_media_fault_tolerant_file_size) + { + + /* Write back the log. */ + status = _fx_fault_tolerant_write_log_file(media_ptr, relative_sector); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + /* Error. */ + return(status); + } + + /* Increase relative sector and offset. */ + relative_sector++; + offset += media_ptr -> fx_media_bytes_per_sector; + } + + /* Flush first sector. */ + status = _fx_fault_tolerant_write_log_file(media_ptr, 0); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + /* Error. */ + return(status); + } + + /* At this pointer, the vital information has been flushed to the physical medium. + Update the file system (FAT table, directory entry) using information recorded in the + log file. */ + status = _fx_fault_tolerant_apply_logs(media_ptr); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + + /* The file system has been updated successfully. Remove and reset the fault tolerant + log file. */ + status = _fx_fault_tolerant_reset_log_file(media_ptr); + + return(status); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c new file mode 100644 index 00000000..2a42182a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_fail.c @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOUCE_CODE + +#include "fx_api.h" +#include "fx_fault_tolerant.h" + +#if defined(FX_ENABLE_FAULT_TOLERANT) && defined(FX_FAULT_TOLERANT_TRANSACTION_FAIL_FUNCTION) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_transaction_fail PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function cleans up resources created by fault tolerant when */ +/* transaction fails. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_attributes_set */ +/* _fx_directory_create */ +/* _fx_directory_delete */ +/* _fx_directory_rename */ +/* _fx_file_allocate */ +/* _fx_file_attributes_set */ +/* _fx_file_best_effort_allocate */ +/* _fx_file_create */ +/* _fx_file_delete */ +/* _fx_file_rename */ +/* _fx_file_truncate */ +/* _fx_file_truncate_release */ +/* _fx_file_write */ +/* _fx_unicode_directory_create */ +/* _fx_unicode_file_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_transaction_fail(FX_MEDIA *media_ptr) +{ + + /* Check whether fault tolerant is enabled or not. */ + if (media_ptr -> fx_media_fault_tolerant_enabled == FX_TRUE) + { + + /* Yes. Decrease the counter for transaction. */ + media_ptr -> fx_media_fault_tolerant_transaction_count--; + + /* Is this the last transaction? */ + if (media_ptr -> fx_media_fault_tolerant_transaction_count == 0) + { + + /* Yes. Perform recover and reset the log file. */ + _fx_fault_tolerant_recover(media_ptr); + _fx_fault_tolerant_reset_log_file(media_ptr); + } + } + + return(FX_SUCCESS); +} +#endif diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c new file mode 100644 index 00000000..76e31574 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_transaction_start.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_transaction_start PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called at the beginning of an update to FileX */ +/* file, directory entry, or FAT table. It resets fault tolerant */ +/* internal state information. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_attributes_set */ +/* _fx_directory_create */ +/* _fx_directory_delete */ +/* _fx_directory_rename */ +/* _fx_file_allocate */ +/* _fx_file_attributes_set */ +/* _fx_file_best_effort_allocate */ +/* _fx_file_create */ +/* _fx_file_delete */ +/* _fx_file_rename */ +/* _fx_file_truncate */ +/* _fx_file_truncate_release */ +/* _fx_file_write */ +/* _fx_unicode_directory_create */ +/* _fx_unicode_file_create */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_transaction_start(FX_MEDIA *media_ptr) +{ + + /* Is fault tolerant enabled? */ + if (media_ptr -> fx_media_fault_tolerant_enabled == FX_TRUE) + { + + /* Is this a new transaction? */ + if (media_ptr -> fx_media_fault_tolerant_transaction_count == 0) + { + + /* Yes. Initialize data. */ + media_ptr -> fx_media_fault_tolerant_file_size = FX_FAULT_TOLERANT_LOG_HEADER_SIZE + + FX_FAULT_TOLERANT_FAT_CHAIN_SIZE + + FX_FAULT_TOLERANT_LOG_CONTENT_HEADER_SIZE; + + /* Reset total logs. */ + media_ptr -> fx_media_fault_tolerant_total_logs = 0; + + /* Set state of fault tolerant. */ + media_ptr -> fx_media_fault_tolerant_state = FX_FAULT_TOLERANT_STATE_STARTED; + } + + /* Increase the transaction. */ + media_ptr -> fx_media_fault_tolerant_transaction_count++; + } + + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c new file mode 100644 index 00000000..ae28fe9f --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_fault_tolerant_write_log_file.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" +#include "fx_directory.h" +#include "fx_fault_tolerant.h" + + +#ifdef FX_ENABLE_FAULT_TOLERANT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_fault_tolerant_write_log_file PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes data of one sector of fault tolerant data */ +/* from memory to log file in file system. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* relative_sector Relative sector number of the */ +/* log file to write to */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_write Write a logical sector */ +/* _fx_utility_logical_sector_flush Flush written logical sectors */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_fault_tolerant_cleanup_FAT_chain */ +/* _fx_fault_tolerant_reset_log_file */ +/* _fx_fault_tolerant_set_FAT_chain */ +/* _fx_fault_tolerant_transaction_end */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_fault_tolerant_write_log_file(FX_MEDIA *media_ptr, ULONG relative_sector) +{ +UINT status; +ULONG start_sector; + + /* Calculate the start sector of log file. */ + start_sector = (media_ptr -> fx_media_fault_tolerant_start_cluster - FX_FAT_ENTRY_START) * + media_ptr -> fx_media_sectors_per_cluster + + media_ptr -> fx_media_data_sector_start; + + + /* Write sector directly. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) (start_sector + relative_sector), + media_ptr -> fx_media_fault_tolerant_memory_buffer + + media_ptr -> fx_media_bytes_per_sector * relative_sector, + ((ULONG) 1), FX_DATA_SECTOR); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + + /* Flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, (ULONG64) start_sector, ((ULONG64) 1), FX_FALSE); + + FX_FAULT_TOLERANT_WRITE_LOG_FILE_EXTENSION + + /* Return the status. */ + return(status); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_allocate.c b/src/Middlewares/ST/filex/common/src/fx_file_allocate.c new file mode 100644 index 00000000..92512cc6 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_allocate.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_allocate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function attempts to allocate the number of consecutive */ +/* clusters required to satisfy the user's request. If there are */ +/* enough clusters, the clusters are allocated and linked to the file. */ +/* Otherwise, if there are not enough consecutive clusters, an error */ +/* code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size Number of bytes to allocate */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_allocate Allocate the clusters */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* Added conditional to */ +/* disable one line function, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT _fx_file_allocate(FX_FILE *file_ptr, ULONG size) +{ + + return(_fx_file_extended_allocate(file_ptr, (ULONG64)size)); +} +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ diff --git a/src/Middlewares/ST/filex/common/src/fx_file_attributes_read.c b/src/Middlewares/ST/filex/common/src/fx_file_attributes_read.c new file mode 100644 index 00000000..e8598d88 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_attributes_read.c @@ -0,0 +1,169 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_attributes_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified file. If found, */ +/* the attribute read request is valid and the directory entry will be */ +/* in order to pickup the file's attributes. Otherwise, if the file */ +/* is not found, the appropriate error code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name pointer */ +/* attributes_ptr Return attributes pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_attributes_read(FX_MEDIA *media_ptr, CHAR *file_name, UINT *attributes_ptr) +{ + +UINT status; +FX_DIR_ENTRY dir_entry; + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif +UCHAR not_a_file_attr; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_attributes_reads++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + not_a_file_attr = FX_DIRECTORY; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + not_a_file_attr = FX_DIRECTORY | FX_VOLUME; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_ATTRIBUTES_READ, media_ptr, file_name, 0, 0, FX_TRACE_FILE_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check to make sure the found entry is a file. */ + if (dir_entry.fx_dir_entry_attributes & not_a_file_attr) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_NOT_A_FILE); + } + + /* Place the current attributes into the destination. */ + *attributes_ptr = (UINT)dir_entry.fx_dir_entry_attributes; + + /* Update the trace event with the attributes read. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_ATTRIBUTES_READ, 0, 0, dir_entry.fx_dir_entry_attributes, 0) + + /* Release media protection. */ + FX_UNPROTECT + + /* File attribute read is complete, return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_attributes_set.c b/src/Middlewares/ST/filex/common/src/fx_file_attributes_set.c new file mode 100644 index 00000000..c667b4f0 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_attributes_set.c @@ -0,0 +1,243 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_attributes_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified file. If found, */ +/* the attribute set request is valid and the directory entry will be */ +/* modified with the new attributes. Otherwise, if the file is not */ +/* found, the appropriate error code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name pointer */ +/* attributes New file attributes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the new directory entry */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_attributes_set(FX_MEDIA *media_ptr, CHAR *file_name, UINT attributes) +{ + +UINT status; +ULONG open_count; +FX_FILE *search_ptr; +FX_DIR_ENTRY dir_entry; +UCHAR not_a_file_attr; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_attributes_sets++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + not_a_file_attr = FX_DIRECTORY; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + not_a_file_attr = FX_DIRECTORY | FX_VOLUME; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_ATTRIBUTES_SET, media_ptr, file_name, attributes, 0, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check to make sure the found entry is a file. */ + if (dir_entry.fx_dir_entry_attributes & not_a_file_attr) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_NOT_A_FILE); + } + + /* Search the opened files to see if this file is currently + opened. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Look at each opened file to see if the same file is opened. */ + if ((search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == dir_entry.fx_dir_entry_byte_offset)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* The file is currently open. */ + return(FX_ACCESS_ERROR); + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } + + /* Place the new attributes in the directory entry. */ + dir_entry.fx_dir_entry_attributes = (UCHAR)attributes; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Now write out the directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write(media_ptr, &dir_entry, UPDATE_FILE); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* File attribute set is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c b/src/Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c new file mode 100644 index 00000000..0868da32 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_best_effort_allocate.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_best_effort_allocate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function attempts to allocate the number of consecutive */ +/* clusters required to satisfy the user's request. If there are not */ +/* enough clusters, the largest set of clusters are allocated and */ +/* linked to the file. If there are no free clusters, an error */ +/* code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size Number of bytes to allocate */ +/* actual_size_allocated Number of bytes allocated */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_best_effort_allocate */ +/* Allocate the largest set of */ +/* clusters */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_best_effort_allocate(FX_FILE *file_ptr, ULONG size, ULONG *actual_size_allocated) +{ + +UINT status; +ULONG64 temp_actual_size_allocated; + + /* Call actual best effort file allocate service. */ + status = _fx_file_extended_best_effort_allocate(file_ptr, (ULONG64)size, &temp_actual_size_allocated); + + /* Check status. */ + if (status == FX_SUCCESS) + { + *actual_size_allocated = (ULONG)temp_actual_size_allocated; + } + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_close.c b/src/Middlewares/ST/filex/common/src/fx_file_close.c new file mode 100644 index 00000000..cabaa990 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_close.c @@ -0,0 +1,198 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_close PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function closes the specified file. If the file was written */ +/* to this function will also write the directory entry (with the new */ +/* size and time/date stamp) out to disk. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the directory entry */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_close(FX_FILE *file_ptr) +{ + +UINT status; +FX_MEDIA *media_ptr; +FX_INT_SAVE_AREA + + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + + /* Setup a pointer to the associated media. */ + media_ptr = file_ptr -> fx_file_media_ptr; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_closes++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_CLOSE, file_ptr, file_ptr -> fx_file_current_file_size, 0, 0, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + /* If trace is enabled, unregister this object. */ + FX_TRACE_OBJECT_UNREGISTER(file_ptr) + + /* Remove this file from the opened list for the media. */ + + /* See if the file is the only one on the open list for this media. */ + if (file_ptr == file_ptr -> fx_file_opened_next) + { + + /* Only opened file, just set the opened list to NULL. */ + media_ptr -> fx_media_opened_file_list = FX_NULL; + } + else + { + + /* Otherwise, not the only opened file, link-up the neighbors. */ + (file_ptr -> fx_file_opened_next) -> fx_file_opened_previous = + file_ptr -> fx_file_opened_previous; + (file_ptr -> fx_file_opened_previous) -> fx_file_opened_next = + file_ptr -> fx_file_opened_next; + + /* See if we have to update the opened list head pointer. */ + if (media_ptr -> fx_media_opened_file_list == file_ptr) + { + + /* Yes, move the head pointer to the next opened file. */ + media_ptr -> fx_media_opened_file_list = file_ptr -> fx_file_opened_next; + } + } + + /* Decrement the opened file counter. */ + media_ptr -> fx_media_opened_file_count--; + + /* Finally, Indicate that this file is closed. */ + file_ptr -> fx_file_id = FX_FILE_CLOSED_ID; + + /* Check to see if this file needs to have its directory entry written + back to the media. */ + if ((file_ptr -> fx_file_open_mode == FX_OPEN_FOR_WRITE) && + (file_ptr -> fx_file_modified)) + { + + /* Lockout interrupts for time/date access. */ + FX_DISABLE_INTS + + /* Set the new time and date. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_time = _fx_system_time; + file_ptr -> fx_file_dir_entry.fx_dir_entry_date = _fx_system_date; + + /* Set the last access date. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_last_accessed_date = _fx_system_date; + + /* Restore interrupts. */ + FX_RESTORE_INTS + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = + file_ptr -> fx_file_current_file_size; + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write( + media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Error writing the directory. */ + return(status); + } + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Return status to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_create.c b/src/Middlewares/ST/filex/common/src/fx_file_create.c new file mode 100644 index 00000000..f621879d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_create.c @@ -0,0 +1,392 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified file. If found, */ +/* the create request is invalid and an error is returned to the */ +/* caller. After the file name verification is made, a search for a */ +/* free directory entry will be made. If nothing is available, an */ +/* error will be returned to the caller. Otherwise, if all is okay, a */ +/* file of 0 bytes will be created. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the new directory entry */ +/* _fx_directory_name_extract Extract directory name */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_directory_free_search Search for a free directory */ +/* entry */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_create(FX_MEDIA *media_ptr, CHAR *file_name) +{ + +FX_INT_SAVE_AREA + +UINT status; +CHAR *name_ptr; +UINT i; +CHAR *work_ptr; +FX_DIR_ENTRY dir_entry; +FX_DIR_ENTRY search_directory; +#ifdef FX_ENABLE_EXFAT +ULONG64 dir_size; +#endif /* FX_ENABLE_EXFAT */ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_creates++; +#endif + + /* Determine if the supplied name is less than the maximum supported name size. The + maximum name (FX_MAX_LONG_NAME_LEN) is defined in fx_api.h. */ + i = 0; + work_ptr = (CHAR *)file_name; + while (*work_ptr) + { + + /* Determine if the character designates a new path. */ + if ((*work_ptr == '\\') || (*work_ptr == '/')) + { + /* Yes, reset the name size. */ + i = 0; + } + /* Check for leading spaces. */ + else if ((*work_ptr != ' ') || (i != 0)) + { + + /* No leading spaces, increment the name size. */ + i++; + } + + /* Move to the next character. */ + work_ptr++; + } + + /* Determine if the supplied name is valid. */ + if ((i == 0) || (i >= FX_MAX_LONG_NAME_LEN)) + { + + /* Return an invalid name value. */ + return(FX_INVALID_NAME); + } + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Setup another pointer to another media name buffer. */ + search_directory.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN * 2; + + /* Clear the short name strings. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + search_directory.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_CREATE, media_ptr, file_name, 0, 0, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, file_name, &dir_entry, &search_directory, &name_ptr); + + /* Determine if the search was successful. */ + if (status == FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* File found - Return the error code. */ + return(FX_ALREADY_CREATED); + } + + /* Determine if there is anything left after the name. */ + if (_fx_directory_name_extract(name_ptr, &dir_entry.fx_dir_entry_name[0])) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Extra information after the file name, return an invalid path + error. */ + return(FX_INVALID_PATH); + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + if (((dir_entry.fx_dir_entry_name[0] == '.') && (dir_entry.fx_dir_entry_name[1] == 0)) || + ((dir_entry.fx_dir_entry_name[0] == '.') && (dir_entry.fx_dir_entry_name[1] == '.') && (dir_entry.fx_dir_entry_name[2] == 0))) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* We don't need '.' or '..' for exFAT */ + return(FX_ALREADY_CREATED); + } + } + + /* Save the directory entry size. */ + dir_size = search_directory.fx_dir_entry_file_size; +#endif /* FX_ENABLE_EXFAT */ + + /* Find a free slot for the new file. */ + status = _fx_directory_free_search(media_ptr, &search_directory, &dir_entry); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Populate the directory entry. */ + + /* Isolate the file name. */ + _fx_directory_name_extract(name_ptr, &dir_entry.fx_dir_entry_name[0]); + + /* Disable interrupts for time/date access. */ + FX_DISABLE_INTS + + /* Set time and date stamps. */ + dir_entry.fx_dir_entry_time = _fx_system_time; + dir_entry.fx_dir_entry_date = _fx_system_date; + + /* Restore interrupts. */ + FX_RESTORE_INTS + + /* Set the attributes for the file. */ + dir_entry.fx_dir_entry_attributes = FX_ARCHIVE; + + /* Set file size to 0. */ + dir_entry.fx_dir_entry_file_size = 0; + +#ifdef FX_ENABLE_EXFAT + /* Set available file size to 0. */ + dir_entry.fx_dir_entry_available_file_size = 0; +#endif /* FX_ENABLE_EXFAT */ + + /* Set the cluster to NULL. */ + dir_entry.fx_dir_entry_cluster = FX_NULL; + + /* Is there a leading dot? */ + if (dir_entry.fx_dir_entry_name[0] == '.') + { + + /* Yes, toggle the hidden attribute bit. */ + dir_entry.fx_dir_entry_attributes |= FX_HIDDEN; + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Don't use FAT by default. */ + dir_entry.fx_dir_entry_dont_use_fat = (CHAR)(((search_directory.fx_dir_entry_dont_use_fat & 1) << 1) | 1); + + if (search_directory.fx_dir_entry_name[0]) + { + + /* Not root directory. */ + /* Copy the date and time from the actual sub-directory. */ + search_directory.fx_dir_entry_time = dir_entry.fx_dir_entry_time; + search_directory.fx_dir_entry_date = dir_entry.fx_dir_entry_date; + + /* Check if the directory size has changed. */ + if (search_directory.fx_dir_entry_file_size == dir_size) + { + + /* Not changed, we need only update time stamps. */ + status = _fx_directory_exFAT_entry_write(media_ptr, &search_directory, UPDATE_FILE); + } + else + { + + /* Directory size changed, update time stamps and the stream size. */ + status = _fx_directory_exFAT_entry_write(media_ptr, &search_directory, UPDATE_STREAM); + } + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + } + else + { + dir_entry.fx_dir_entry_dont_use_fat = 0; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Now write out the directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write(media_ptr, &dir_entry, UPDATE_FULL); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* File create is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_date_time_set.c b/src/Middlewares/ST/filex/common/src/fx_file_date_time_set.c new file mode 100644 index 00000000..448aa09d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_date_time_set.c @@ -0,0 +1,148 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" +#include "fx_file.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_date_time_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the specified file's date and time with the */ +/* values provided. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name pointer */ +/* year Year */ +/* month Month */ +/* day Day */ +/* hour Hour */ +/* minute Minute */ +/* second Second */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_directory_entry_write Write the directory entry */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_date_time_set(FX_MEDIA *media_ptr, CHAR *file_name, + UINT year, UINT month, UINT day, UINT hour, UINT minute, UINT second) +{ + +UINT status; +FX_DIR_ENTRY dir_entry; + + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_DATE_TIME_SET, media_ptr, file_name, year, month, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied directory name. */ + status = _fx_directory_search(media_ptr, file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Set the new time and date. */ + dir_entry.fx_dir_entry_time = (hour << FX_HOUR_SHIFT) | (minute << FX_MINUTE_SHIFT) | (second / 2); + dir_entry.fx_dir_entry_date = ((year - FX_BASE_YEAR) << FX_YEAR_SHIFT) | (month << FX_MONTH_SHIFT) | day; + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write(media_ptr, &dir_entry, UPDATE_FILE); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Directory information write is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_delete.c b/src/Middlewares/ST/filex/common/src/fx_file_delete.c new file mode 100644 index 00000000..691c4dd7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_delete.c @@ -0,0 +1,477 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified file. If found, */ +/* the delete request is valid and all of its clusters will be */ +/* released and its directory entry will be marked as available. */ +/* Otherwise, if the file is not found, the appropriate error code is */ +/* returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the new directory entry */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* _fx_fault_tolerant_set_FAT_chain Set data of FAT chain */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_delete(FX_MEDIA *media_ptr, CHAR *file_name) +{ + +UINT status; +ULONG cluster; +ULONG contents; +ULONG open_count; +FX_FILE *search_ptr; +ULONG cluster_count; +FX_DIR_ENTRY dir_entry; +UCHAR not_a_file_attr; +#ifdef FX_ENABLE_EXFAT +ULONG bytes_per_cluster; +ULONG clusters_count; +#endif /* FX_ENABLE_EXFAT */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_deletes++; +#endif + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_DELETE, media_ptr, file_name, 0, 0, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + not_a_file_attr = FX_DIRECTORY; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + not_a_file_attr = FX_DIRECTORY | FX_VOLUME; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check to make sure the found entry is a file. */ + if (dir_entry.fx_dir_entry_attributes & not_a_file_attr) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_NOT_A_FILE); + } + + /* Check if the entry is read only */ + if (dir_entry.fx_dir_entry_attributes & (UCHAR)(FX_READ_ONLY)) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a directory error code. */ + return(FX_WRITE_PROTECT); + } + + /* Search the opened files to see if this file is currently + opened. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Look at each opened file to see if the same file is opened. */ + if ((search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == dir_entry.fx_dir_entry_byte_offset)) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* The file is currently open. */ + return(FX_ACCESS_ERROR); + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } + + /* Pickup the starting cluster of the file. */ + cluster = dir_entry.fx_dir_entry_cluster; + + /* At this point, make the directory entry invalid in order to delete the file. */ + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Invalidate the directory search saved information. */ + media_ptr -> fx_media_last_found_name[0] = FX_NULL; +#endif + + /* Mark the directory entry as available, while leaving the other + information for the sake of posterity. */ + dir_entry.fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + dir_entry.fx_dir_entry_short_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + + /* Now write out the directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write(media_ptr, &dir_entry, UPDATE_DELETE); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Now that the directory entry is no longer valid and pointing at the chain of clusters, + walk the chain of allocated FAT entries and mark each of them as free. */ + cluster_count = 0; + +#ifdef FX_ENABLE_EXFAT + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + clusters_count = + (ULONG)((dir_entry.fx_dir_entry_file_size + bytes_per_cluster - 1) / bytes_per_cluster - 1); +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Note: Directory entries are already written to log files. FAT chain is updated as the last step. + Since there are no others FAT entries written to the log. Therefore there is no need to set + the flag FX_FRAULT_TOLERANT_STATE_SET_FAT_CHAIN here. */ +#ifdef FX_ENABLE_EXFAT + if (dir_entry.fx_dir_entry_dont_use_fat & 1) + { + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, FX_TRUE, 0, + media_ptr -> fx_media_fat_last, cluster, cluster + clusters_count); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, FX_FALSE, 0, + media_ptr -> fx_media_fat_last, cluster, media_ptr -> fx_media_fat_last); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + } + else + { +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Follow the link of FAT entries. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Increment the number of clusters. */ + cluster_count++; + +#ifdef FX_ENABLE_EXFAT + if (dir_entry.fx_dir_entry_dont_use_fat & 1) + { + + /* Check for file size range. */ + if (cluster_count - 1 >= clusters_count) + { + contents = FX_LAST_CLUSTER_exFAT; + } + else + { + contents = cluster + 1; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + if ((cluster == contents) || (cluster_count > media_ptr -> fx_media_total_clusters)) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + +#ifdef FX_ENABLE_EXFAT + if (!(dir_entry.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Make the current cluster available. */ + status = _fx_utility_FAT_entry_write(media_ptr, cluster, FX_FREE_CLUSTER); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as free. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, cluster, FX_EXFAT_BITMAP_CLUSTER_FREE); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* Setup for the next cluster. */ + cluster = contents; + } +#ifdef FX_ENABLE_FAULT_TOLERANT + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Update the free clusters in the media control block. */ + media_ptr -> fx_media_available_clusters = + media_ptr -> fx_media_available_clusters + cluster_count; + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + +#ifdef FX_ENABLE_FAULT_TOLERANT + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* File delete is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_extended_allocate.c b/src/Middlewares/ST/filex/common/src/fx_file_extended_allocate.c new file mode 100644 index 00000000..aafa69f4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_extended_allocate.c @@ -0,0 +1,871 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_extended_allocate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function attempts to allocate the number of consecutive */ +/* clusters required to satisfy the user's request. If there are */ +/* enough clusters, the clusters are allocated and linked to the file. */ +/* Otherwise, if there are not enough consecutive clusters, an error */ +/* code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size Number of bytes to allocate */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Update directory entry */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_exFAT_bitmap_free_cluster_find */ +/* Find exFAT free cluster */ +/* _fx_utility_exFAT_cluster_state_get Get cluster state */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_utility_logical_sector_flush Flush the written log sector */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* _fx_fault_tolerant_set_FAT_chain Set data of FAT chain */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_extended_allocate(FX_FILE *file_ptr, ULONG64 size) +{ + +UINT status; +ULONG i; +UINT found; +ULONG bytes_per_cluster; +ULONG FAT_index; +ULONG FAT_value; +ULONG clusters; +FX_MEDIA *media_ptr; +#ifdef FX_ENABLE_EXFAT +UCHAR cluster_state; +#endif /* FX_ENABLE_EXFAT */ + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + + /* Setup pointer to media structure. */ + media_ptr = file_ptr -> fx_file_media_ptr; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_allocates++; +#endif + + /* Make sure this file is open for writing. */ + if (file_ptr -> fx_file_open_mode != FX_OPEN_FOR_WRITE) + { + + /* Return the access error exception - a write was attempted from + a file opened for reading! */ + return(FX_ACCESS_ERROR); + } + + /* Determine if the requested allocation is for zero bytes. */ + if (size == 0) + { + + /* Return a successful completion - nothing needs to be done. */ + return(FX_SUCCESS); + } + + /* Setup pointer to associated media control block. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_ALLOCATE, file_ptr, size, file_ptr -> fx_file_current_available_size, 0, FX_TRACE_FILE_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check for invalid value. */ + if (bytes_per_cluster == 0) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Calculate the number of consecutive clusters needed to satisfy this + request. */ + clusters = (ULONG)(((size + bytes_per_cluster - 1) / bytes_per_cluster)); + + /* Determine if cluster count is 0. */ + if (clusters == 0) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Size overflow when rounding to the next cluster, return an error status. */ + return(FX_NO_MORE_SPACE); + } + + /* Determine if there are enough available clusters on the media. */ + if (clusters > media_ptr -> fx_media_available_clusters) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Not enough clusters, return an error status. */ + return(FX_NO_MORE_SPACE); + } + + /* Determine if the requested file allocation would exceed the physical limit of the file. */ + if (((file_ptr -> fx_file_current_available_size + (((ULONG64) clusters) * ((ULONG64) bytes_per_cluster))) < file_ptr -> fx_file_current_available_size) || + ((file_ptr -> fx_file_current_available_size + (((ULONG64) clusters) * ((ULONG64) bytes_per_cluster))) > 0xFFFFFFFFULL)) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the no more space error, since the new file size would be larger than + the 32-bit field to represent it in the file's directory entry. */ + return(FX_NO_MORE_SPACE); + } + + /* Now we need to find the consecutive clusters. */ + FAT_index = FX_FAT_ENTRY_START; + found = FX_FALSE; + +#ifdef FX_ENABLE_EXFAT + if ((file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) && + (file_ptr -> fx_file_last_physical_cluster > FX_FAT_ENTRY_START) && + (file_ptr -> fx_file_last_physical_cluster < media_ptr -> fx_media_total_clusters - clusters + FX_FAT_ENTRY_START)) + { + found = FX_TRUE; + /* Try to keep clusters consecutive. */ + for (FAT_index = file_ptr -> fx_file_last_physical_cluster + 1; + FAT_index < clusters + file_ptr -> fx_file_last_physical_cluster + 1; + FAT_index++) + { + + /* Get cluster state. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, FAT_index, &cluster_state); + + /* Check for a successful status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Determine if the entry is free. */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_OCCUPIED) + { + found = FX_FALSE; + break; + } + } + FAT_index = file_ptr -> fx_file_last_physical_cluster + 1; + } + + if (!found) + { +#endif /* FX_ENABLE_EXFAT */ + + while (FAT_index <= (media_ptr -> fx_media_total_clusters - clusters + FX_FAT_ENTRY_START)) + { + + /* Determine if enough consecutive FAT entries are available. */ + i = 0; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + do + { + + /* Get cluster state. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, (FAT_index + i), &cluster_state); + + /* Check for a successful status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Determine if the entry is free. */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_OCCUPIED) + { + break; + } + + /* Otherwise, increment the consecutive FAT indices. */ + i++; + } while (i < clusters); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + do + { + + /* Read a FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, (FAT_index + i), &FAT_value); + + /* Check for a successful status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Determine if the entry is free. */ + if (FAT_value != FX_FREE_CLUSTER) + { + break; + } + + /* Otherwise, increment the consecutive FAT indices. */ + i++; + } while (i < clusters); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if we found enough FAT entries. */ + if (i >= clusters) + { + + /* Yes, we have found enough FAT entries - set the found + flag and get out of this loop. */ + found = FX_TRUE; + break; + } + else + { +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Find free cluster from exFAT media. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, + FAT_index + i + 1, + &FAT_value); + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + if (FAT_value < FAT_index + i + 1) + { + /* If we wrapped. */ + FAT_index = media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START; + } + else + { + FAT_index = FAT_value; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + /* Position to the next possibly free FAT entry. */ + FAT_index = FAT_index + i + 1; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + } +#ifdef FX_ENABLE_EXFAT + } +#endif + + /* Determine if we found enough consecutive clusters to satisfy the + request. */ + if (found) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Record the action that is about to take place. This information + would aid the undo process should fault condition happens. */ + media_ptr -> fx_media_fault_tolerant_state |= FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN; + _fx_fault_tolerant_set_FAT_chain(media_ptr, FX_FALSE, file_ptr -> fx_file_last_physical_cluster, + FAT_index, media_ptr -> fx_media_fat_last, media_ptr -> fx_media_fat_last); + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + if ((file_ptr -> fx_file_total_clusters) && + (FAT_index != file_ptr -> fx_file_last_physical_cluster + 1)) + { + /* Clusters are not consecutive. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat &= (CHAR)0xfe; /* Set 0bit to 0 */ + + /* Rebuild FAT. */ + FAT_value = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster + + file_ptr -> fx_file_total_clusters - 1; /* Last cluster */ + + for (i = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster; i < FAT_value; ++i) + { + status = _fx_utility_FAT_entry_write(media_ptr, i, i + 1); + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + + /* Close chain. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_value, media_ptr -> fx_media_fat_last); + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Clear undo phase. */ + media_ptr -> fx_media_fault_tolerant_state &= (UCHAR)(~FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN & 0xff); + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Update stream. */ + status = _fx_directory_exFAT_entry_write( + media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Set undo phase. */ + media_ptr -> fx_media_fault_tolerant_state |= FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN; + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* Update the link pointers in the new clusters. */ + for (i = 0; i < (clusters - 1); i++) + { +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) +#ifdef FX_ENABLE_FAULT_TOLERANT + || (media_ptr -> fx_media_fault_tolerant_enabled == FX_TRUE) +#endif /* FX_ENABLE_FAULT_TOLERANT */ + ) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Update the cluster links. Since the allocation is + sequential, we just have to link each FAT entry to the + next one. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_index + i, FAT_index + i + 1); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as used. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, FAT_index + i, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + } +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Now place an EOF in the last cluster entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_index + clusters - 1, media_ptr -> fx_media_fat_last); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as used. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, FAT_index + clusters - 1, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ +#endif + + /* Actually link up the new clusters to the file. */ + + /* Determine if there are already clusters allocated for this file. */ + if (file_ptr -> fx_file_total_clusters) + { +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Linkup the last cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, + file_ptr -> fx_file_last_physical_cluster, FAT_index); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if we are adding a sector after a write filled the previously + allocated cluster exactly. */ + if ((file_ptr -> fx_file_current_relative_sector >= + (media_ptr -> fx_media_sectors_per_cluster - 1)) && + (file_ptr -> fx_file_current_logical_offset >= + media_ptr -> fx_media_bytes_per_sector)) + { + + /* Yes, we need to adjust all of the pertinent file parameters for + access into this newly allocated cluster. */ + file_ptr -> fx_file_current_physical_cluster = FAT_index; + file_ptr -> fx_file_current_relative_cluster++; + file_ptr -> fx_file_current_relative_sector = 0; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(FAT_index - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + file_ptr -> fx_file_current_logical_offset = 0; + } + } + else + { + + /* These new clusters are also the first! Setup the initial + file parameters. */ + file_ptr -> fx_file_first_physical_cluster = FAT_index; + file_ptr -> fx_file_current_physical_cluster = file_ptr -> fx_file_first_physical_cluster; + file_ptr -> fx_file_current_relative_cluster = 0; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(file_ptr -> fx_file_first_physical_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + file_ptr -> fx_file_current_logical_offset = 0; + file_ptr -> fx_file_current_file_offset = 0; + + /* Update the first cluster in the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster = FAT_index; + } + + /* Remember the last physical cluster. */ + file_ptr -> fx_file_last_physical_cluster = FAT_index + clusters - 1; + +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_current_available_size > (file_ptr -> fx_file_current_available_size + (bytes_per_cluster * clusters))) + { + /* 64-bit wrap around condition is present. Just set the available file size to all ones, which is + the maximum file size. */ + file_ptr -> fx_file_current_available_size = 0xFFFFFFFFFFFFFFFFULL; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for wrap-around when updating the available size. */ +#ifdef FX_ENABLE_EXFAT + if ((media_ptr -> fx_media_FAT_type != FX_exFAT) && + (file_ptr -> fx_file_current_available_size + (bytes_per_cluster * clusters) > 0xFFFFFFFFUL)) + { + + /* 32-bit wrap around condition is present. Just set the available file size to all ones, which is + the maximum file size. */ + file_ptr -> fx_file_current_available_size = ((ULONG)0xFFFFFFFF); + } + else + { + + /* Normal condition, update the available size. */ + file_ptr -> fx_file_current_available_size = + file_ptr -> fx_file_current_available_size + (bytes_per_cluster * clusters); + } +#else + /* Update the available size. */ + file_ptr -> fx_file_current_available_size = + file_ptr -> fx_file_current_available_size + (bytes_per_cluster * clusters); + +#endif /* FX_ENABLE_EXFAT */ + + /* Increment the total clusters for this file. */ + file_ptr -> fx_file_total_clusters = + file_ptr -> fx_file_total_clusters + clusters; + + /* Decrease the available clusters on the media. */ + media_ptr -> fx_media_available_clusters = + media_ptr -> fx_media_available_clusters - clusters; + +#if defined(FX_UPDATE_FILE_SIZE_ON_ALLOCATE) || defined(FX_ENABLE_FAULT_TOLERANT) + + /* Set the file size the current size plus what what was added. */ + file_ptr -> fx_file_current_file_size += size; + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = file_ptr -> fx_file_current_file_size; +#endif + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Clear undo phase. */ + media_ptr -> fx_media_fault_tolerant_state &= (UCHAR)(~FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN & 0xff); + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Update the trace event with the new size. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_ALLOCATE, 0, 0, 0, file_ptr -> fx_file_current_file_size); + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write( + media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } + else + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Not enough contiguous space on the media. Return error status. */ + return(FX_NO_MORE_SPACE); + } + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + + /* Flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, ((ULONG64) 1), (ULONG64)(media_ptr -> fx_media_sectors_per_FAT), FX_FALSE); + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = file_ptr -> fx_file_current_file_size; + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c b/src/Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c new file mode 100644 index 00000000..a78dfe0c --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_extended_best_effort_allocate.c @@ -0,0 +1,918 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_extended_best_effort_allocate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function attempts to allocate the number of consecutive */ +/* clusters required to satisfy the user's request. If there are not */ +/* enough clusters, the largest set of clusters are allocated and */ +/* linked to the file. If there are no free clusters, an error */ +/* code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size Number of bytes to allocate */ +/* actual_size_allocated Number of bytes allocated */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Update directory entry */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_exFAT_bitmap_free_cluster_find */ +/* Find exFAT free cluster */ +/* _fx_utility_exFAT_cluster_state_get Get cluster state */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_utility_logical_sector_flush Flush the written log sector */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* _fx_fault_tolerant_set_FAT_chain Set data of FAT chain */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_extended_best_effort_allocate(FX_FILE *file_ptr, ULONG64 size, ULONG64 *actual_size_allocated) +{ + +UINT status; +ULONG i; +UINT found; +ULONG bytes_per_cluster; +ULONG FAT_index, start_FAT_index; +ULONG FAT_value; +ULONG clusters, maximum_clusters; +FX_MEDIA *media_ptr; + +#ifdef FX_ENABLE_EXFAT +UCHAR cluster_state; +#endif /* FX_ENABLE_EXFAT */ + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Setup pointer to media structure. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_best_effort_allocates++; +#endif + + /* Make sure this file is open for writing. */ + if (file_ptr -> fx_file_open_mode != FX_OPEN_FOR_WRITE) + { + + /* Return the access error exception - a write was attempted from + a file opened for reading! */ + return(FX_ACCESS_ERROR); + } + + /* Determine if the requested allocation is for zero bytes. */ + if (size == 0) + { + + /* Return a size allocated of zero. */ + *actual_size_allocated = 0; + + /* Return a successful completion - nothing needs to be done. */ + return(FX_SUCCESS); + } + + /* Setup pointer to associated media control block. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_BEST_EFFORT_ALLOCATE, file_ptr, size, 0, 0, FX_TRACE_FILE_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check for invalid value. */ + if (bytes_per_cluster == 0) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Calculate the number of consecutive clusters needed to satisfy this + request. */ + clusters = (ULONG)(((size + bytes_per_cluster - 1) / bytes_per_cluster)); + + /* Determine if cluster count is 0. */ + if (clusters == 0) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Size overflow when rounding to the next cluster, return an error status. */ + return(FX_NO_MORE_SPACE); + } + + /* Determine if there are no available clusters on the media. */ + if (!media_ptr -> fx_media_available_clusters) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return a size allocated of zero, since no clusters were available. */ + *actual_size_allocated = 0; + + /* Not enough clusters, return an error status. */ + return(FX_NO_MORE_SPACE); + } + + /* Determine if the requested file allocation would exceed the physical limit of the file. */ + if (((file_ptr -> fx_file_current_available_size + (((ULONG64) clusters) * ((ULONG64) bytes_per_cluster))) < file_ptr -> fx_file_current_available_size) || + ((file_ptr -> fx_file_current_available_size + (((ULONG64) clusters) * ((ULONG64) bytes_per_cluster))) > 0xFFFFFFFFULL)) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the no more space error, since the new file size would be larger than + the 32-bit field to represent it in the file's directory entry. */ + return(FX_NO_MORE_SPACE); + } + + /* Now we need to find the consecutive clusters. */ + found = FX_FALSE; +#ifdef FX_ENABLE_EXFAT + if ((file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) && + (file_ptr -> fx_file_last_physical_cluster > FX_FAT_ENTRY_START) && + (file_ptr -> fx_file_last_physical_cluster < media_ptr -> fx_media_total_clusters - clusters + FX_FAT_ENTRY_START)) + { + found = FX_TRUE; + + /* Try to keep clusters consecutive. */ + for (FAT_index = file_ptr -> fx_file_last_physical_cluster + 1; + FAT_index < clusters + file_ptr -> fx_file_last_physical_cluster + 1; + FAT_index++) + { + + /* Get cluster state. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, FAT_index, &cluster_state); + + /* Check for a successful status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Determine if the entry is free. */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_OCCUPIED) + { + found = FX_FALSE; + break; + } + } + FAT_index = file_ptr -> fx_file_last_physical_cluster + 1; + } + + if (!found) + { +#endif /* FX_ENABLE_EXFAT */ + FAT_index = FX_FAT_ENTRY_START; + maximum_clusters = 0; + start_FAT_index = FAT_index; + + while (FAT_index < (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Determine if enough consecutive FAT entries are available. */ + i = 0; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + do + { + + /* Get cluster state. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, (FAT_index + i), &cluster_state); + + /* Check for a successful status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Determine if the entry is free. */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_OCCUPIED) + { + break; + } + + /* Otherwise, increment the consecutive FAT indices. */ + i++; + } while ((i < clusters) && ((FAT_index + i) < media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + do + { + + /* Read a FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, (FAT_index + i), &FAT_value); + + /* Check for a successful status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Determine if the entry is free. */ + if (FAT_value != FX_FREE_CLUSTER) + { + break; + } + + /* Otherwise, increment the consecutive FAT indices. */ + i++; + } while ((i < clusters) && ((FAT_index + i) < media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if a new maximum number of clusters has been found. */ + if (i > maximum_clusters) + { + + /* Yes, remember the maximum number of clusters and the starting + cluster. */ + maximum_clusters = i; + start_FAT_index = FAT_index; + } + + /* Determine if we found enough FAT entries. */ + if (i >= clusters) + { + + /* Yes, we have found enough FAT entries - set the found + flag and get out of this loop. */ + found = FX_TRUE; + break; + } + else + { +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Find free cluster from exFAT media. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, + FAT_index + i + 1, + &FAT_value); + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + if (FAT_value < FAT_index + i + 1) + { + + /* If we wrapped. */ + FAT_index = media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START; + } + else + { + FAT_index = FAT_value; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Position to the next possibly free FAT entry. */ + FAT_index = FAT_index + i + 1; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + } + + /* Determine if the total request could not be satisfied, but a partial allocation + could be satisfied. */ + if (maximum_clusters) + { + + /* Yes, there was at least one cluster. Prepare to return this + to the caller. */ + FAT_index = start_FAT_index; + clusters = maximum_clusters; + found = FX_TRUE; + } +#ifdef FX_ENABLE_EXFAT + } +#endif + + /* Determine if we found enough consecutive clusters to satisfy the + request. */ + if (found) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Record the FAT chain being applied to the file system. This information aids + recovery effort if fault happens. */ + media_ptr -> fx_media_fault_tolerant_state |= FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN; + _fx_fault_tolerant_set_FAT_chain(media_ptr, FX_FALSE, file_ptr -> fx_file_last_physical_cluster, + FAT_index, media_ptr -> fx_media_fat_last, media_ptr -> fx_media_fat_last); + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + if ((file_ptr -> fx_file_total_clusters) && + (FAT_index != file_ptr -> fx_file_last_physical_cluster + 1)) + { + + /* Clusters are not consecutive. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat &= (CHAR)0xfe; /* Set 0bit to 0. */ + + /* Rebuild FAT. */ + FAT_value = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster + + file_ptr -> fx_file_total_clusters - 1; /* Last cluster */ + + for (i = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster; i < FAT_value; ++i) + { + status = _fx_utility_FAT_entry_write(media_ptr, i, i + 1); + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + + /* Close chain. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_value, media_ptr -> fx_media_fat_last); + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Clear the Fault Tolerant Set FAT Chain flag. */ + media_ptr -> fx_media_fault_tolerant_state &= (UCHAR)(~FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN & 0xff); + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Update stream. */ + status = _fx_directory_exFAT_entry_write( + media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Set undo phase. */ + media_ptr -> fx_media_fault_tolerant_state |= FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN; + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* Update the link pointers in the new clusters. */ + for (i = 0; i < (clusters - 1); i++) + { +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) +#ifdef FX_ENABLE_FAULT_TOLERANT + || (media_ptr -> fx_media_fault_tolerant_enabled == FX_TRUE) +#endif /* FX_ENABLE_FAULT_TOLERANT */ + ) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Update the cluster links. Since the allocation is + sequential, we just have to link each FAT entry to the + next one. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_index + i, FAT_index + i + 1); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as used. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, FAT_index + i, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + } + +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Now place an EOF in the last cluster entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, FAT_index + clusters - 1, media_ptr -> fx_media_fat_last); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as used. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, FAT_index + clusters - 1, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ +#endif + + /* Actually link up the new clusters to the file. */ + + /* Determine if there are already clusters allocated for this file. */ + if (file_ptr -> fx_file_total_clusters) + { + +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Linkup the last cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, + file_ptr -> fx_file_last_physical_cluster, FAT_index); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if we are adding a sector after a write filled the previously + allocated cluster exactly. */ + if ((file_ptr -> fx_file_current_relative_sector >= + (media_ptr -> fx_media_sectors_per_cluster - 1)) && + (file_ptr -> fx_file_current_logical_offset >= + media_ptr -> fx_media_bytes_per_sector)) + { + + /* Yes, we need to adjust all of the pertinent file parameters for + access into this newly allocated cluster. */ + file_ptr -> fx_file_current_physical_cluster = FAT_index; + file_ptr -> fx_file_current_relative_cluster++; + file_ptr -> fx_file_current_relative_sector = 0; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(FAT_index - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + file_ptr -> fx_file_current_logical_offset = 0; + } + } + else + { + + /* These new clusters are also the first! Setup the initial + file parameters. */ + file_ptr -> fx_file_first_physical_cluster = FAT_index; + file_ptr -> fx_file_current_physical_cluster = file_ptr -> fx_file_first_physical_cluster; + file_ptr -> fx_file_current_relative_cluster = 0; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(file_ptr -> fx_file_first_physical_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + file_ptr -> fx_file_current_logical_offset = 0; + file_ptr -> fx_file_current_file_offset = 0; + + /* Setup the consecutive clusters at the beginning of the file. */ + file_ptr -> fx_file_consecutive_cluster = clusters; + + /* Update the first cluster in the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster = FAT_index; + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Clear undo phase. */ + media_ptr -> fx_media_fault_tolerant_state &= (UCHAR)(~FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN & 0xff); + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + + /* Remember the last physical cluster. */ + file_ptr -> fx_file_last_physical_cluster = FAT_index + clusters - 1; + + /* Update the available size. */ +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_current_available_size > (file_ptr -> fx_file_current_available_size + (bytes_per_cluster * clusters))) + { + /* 64-bit wrap around condition is present. Just set the available file size to all ones, which is + the maximum file size. */ + file_ptr -> fx_file_current_available_size = 0xFFFFFFFFFFFFFFFFULL; + } + + /* Check for wrap-around when updating the available size. */ + if ((media_ptr -> fx_media_FAT_type != FX_exFAT) && + (file_ptr -> fx_file_current_available_size + (bytes_per_cluster * clusters) > 0xFFFFFFFFUL)) + { + + /* 32-bit wrap around condition is present. Just set the available file size to all ones, which is + the maximum file size. */ + file_ptr -> fx_file_current_available_size = 0xFFFFFFFFUL; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Normal condition, update the available size. */ + file_ptr -> fx_file_current_available_size = + file_ptr -> fx_file_current_available_size + bytes_per_cluster * clusters; +#ifdef FX_ENABLE_EXFAT + } + + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + file_ptr -> fx_file_consecutive_cluster += clusters; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Increment the total clusters for this file. */ + file_ptr -> fx_file_total_clusters = + file_ptr -> fx_file_total_clusters + clusters; + + /* Decrease the available clusters on the media. */ + media_ptr -> fx_media_available_clusters = + media_ptr -> fx_media_available_clusters - clusters; + + /* Return the actual size allocated. */ + *actual_size_allocated = ((ULONG64)clusters) * bytes_per_cluster; + +#if defined(FX_UPDATE_FILE_SIZE_ON_ALLOCATE) || defined(FX_ENABLE_FAULT_TOLERANT) + + /* Set the file size the current size plus what what was added. */ + if (size < *actual_size_allocated) + { + file_ptr -> fx_file_current_file_size += size; + } + else + { + file_ptr -> fx_file_current_file_size += *actual_size_allocated; + } + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = file_ptr -> fx_file_current_file_size; +#endif + + /* Update the trace event with the bytes allocated. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_BEST_EFFORT_ALLOCATE, 0, 0, *actual_size_allocated, 0); + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write( + media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } + else + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return a size allocated of zero, since no clusters were available. */ + *actual_size_allocated = 0; + + /* Not enough contiguous space on the media. Return error status. */ + return(FX_NO_MORE_SPACE); + } + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + + /* Flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, ((ULONG64) 1), (ULONG64) (media_ptr -> fx_media_sectors_per_FAT), FX_FALSE); + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c b/src/Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c new file mode 100644 index 00000000..d63e95ba --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_extended_relative_seek.c @@ -0,0 +1,163 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_extended_relative_seek PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function positions the internal file pointers to the specified */ +/* byte relative offset such that the next read or write operation is */ +/* performed there. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* byte_offset Byte offset of the seek */ +/* seek_from Direction for relative seek, */ +/* legal values are: */ +/* */ +/* FX_SEEK_BEGIN */ +/* FX_SEEK_END */ +/* FX_SEEK_FORWARD */ +/* FX_SEEK_BACK */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_seek Seek to specified position */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_extended_relative_seek(FX_FILE *file_ptr, ULONG64 byte_offset, UINT seek_from) +{ + +#ifndef FX_MEDIA_STATISTICS_DISABLE +FX_MEDIA *media_ptr; + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + + /* Setup pointer to media structure. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_relative_seeks++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_RELATIVE_SEEK, file_ptr, byte_offset, seek_from, file_ptr -> fx_file_current_file_offset, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Determine if seeking from the beginning is requested. */ + if (seek_from == FX_SEEK_BEGIN) + { + + /* Yes, use the base file seek routine to seek from the beginning of + the file. */ + return(_fx_file_extended_seek(file_ptr, byte_offset)); + } + /* Otherwise, determine if seeking from the end is requested. */ + else if (seek_from == FX_SEEK_END) + { + + /* Yes, seek from the end of the file. */ + + /* Determine if the requested seek offset is greater than + the file size. */ + if (byte_offset >= file_ptr -> fx_file_current_file_size) + { + + /* Yes, just seek to the beginning of the file. */ + return(_fx_file_extended_seek(file_ptr, ((ULONG64) 0))); + } + else + { + + /* Logically seek from the end of the file. */ + return(_fx_file_extended_seek(file_ptr, file_ptr -> fx_file_current_file_size - byte_offset)); + } + } + /* Otherwise, determine if seeking from the current position is requested. */ + else if (seek_from == FX_SEEK_FORWARD) + { + + /* Yes, just seek ahead from the current file position. */ + return(_fx_file_extended_seek(file_ptr, file_ptr -> fx_file_current_file_offset + byte_offset)); + } + /* Otherwise, seeking backward from the current position is assumed. */ + else + { + + /* Determine if the backward offset is greater than the current file offset. */ + if (byte_offset >= file_ptr -> fx_file_current_file_offset) + { + + /* Yes, just position the file to the beginning. */ + return(_fx_file_extended_seek(file_ptr, ((ULONG64) 0))); + } + else + { + + /* Seek backward relative to the current position. */ + return(_fx_file_extended_seek(file_ptr, file_ptr -> fx_file_current_file_offset - byte_offset)); + } + } +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_extended_seek.c b/src/Middlewares/ST/filex/common/src/fx_file_extended_seek.c new file mode 100644 index 00000000..6437f752 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_extended_seek.c @@ -0,0 +1,328 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_extended_seek PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function positions the internal file pointers to the specified */ +/* byte offset such that the next read or write operation will be */ +/* performed there. If the byte offset is greater than the size, the */ +/* file pointers will be positioned to the end of the file. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* byte_offset Byte offset into the file */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 06-02-2021 Bhupendra Naphade Modified comment(s), fixed */ +/* relative cluster logic, */ +/* resulting in version 6.1.7 */ +/* */ +/**************************************************************************/ +UINT _fx_file_extended_seek(FX_FILE *file_ptr, ULONG64 byte_offset) +{ + +UINT status; +ULONG cluster; +ULONG contents = 0; +ULONG bytes_per_cluster; +ULONG last_cluster; +ULONG cluster_count; +ULONG64 bytes_remaining; +FX_MEDIA *media_ptr; + + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Setup pointer to media structure. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_seeks++; +#endif + + /* Setup pointer to associated media control block. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_SEEK, file_ptr, byte_offset, file_ptr -> fx_file_current_file_offset, 0, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Check if we actually have to do anything. */ + if (byte_offset == file_ptr -> fx_file_current_file_offset) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Seek is complete, return successful status. */ + return(FX_SUCCESS); + } + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check for invalid value. */ + if (bytes_per_cluster == 0) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + /* See if we need to adjust the byte offset. */ + if (byte_offset > file_ptr -> fx_file_current_file_size) + { + + /* Adjust the byte offset down to the file size. */ + byte_offset = file_ptr -> fx_file_current_file_size; + } + + /* Check if the desired position within the leading consecutive clusters. */ + if (byte_offset >= (ULONG64)file_ptr -> fx_file_consecutive_cluster * (ULONG64)bytes_per_cluster) + { +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + if (byte_offset == (ULONG64)file_ptr -> fx_file_consecutive_cluster * (ULONG64)bytes_per_cluster) + { + /* If the file bytes exactly fits the cluster size */ + bytes_remaining = bytes_per_cluster; + + file_ptr -> fx_file_current_relative_cluster = (ULONG)(byte_offset / bytes_per_cluster - 1); + + file_ptr -> fx_file_current_physical_cluster = + file_ptr -> fx_file_first_physical_cluster + file_ptr -> fx_file_current_relative_cluster; + } + else + { + + /* We shouldn't be here if don't using FAT! */ + FX_UNPROTECT + + return(FX_FILE_CORRUPT); + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* At this point, we are ready to walk list of clusters to setup the + seek position of this file. */ + + /* check if byte_offset is greater than where we were left off earlier */ + if ((ULONG64)file_ptr -> fx_file_current_relative_cluster * (ULONG64)bytes_per_cluster < byte_offset) + { + + cluster = file_ptr -> fx_file_current_physical_cluster; + + bytes_remaining = byte_offset - + file_ptr -> fx_file_current_relative_cluster * bytes_per_cluster; + + cluster_count = file_ptr -> fx_file_current_relative_cluster; + } + else + { + + cluster = file_ptr -> fx_file_first_physical_cluster + + (file_ptr -> fx_file_consecutive_cluster - 1); + bytes_remaining = byte_offset - + (file_ptr -> fx_file_consecutive_cluster - 1) * bytes_per_cluster; + cluster_count = (file_ptr -> fx_file_consecutive_cluster - 1); + } + + + /* Follow the link of FAT entries. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Increment the number of clusters. */ + cluster_count++; + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Save the last valid cluster. */ + last_cluster = cluster; + + /* Setup for the next cluster. */ + cluster = contents; + + /* Determine if this is the last written cluster. */ + if (bytes_remaining > bytes_per_cluster) + { + + /* Still more seeking, just decrement the working byte offset. */ + bytes_remaining = bytes_remaining - bytes_per_cluster; + } + else + { + + /* Remember this cluster number. */ + file_ptr -> fx_file_current_physical_cluster = last_cluster; + + /* Remember the relative cluster. */ + file_ptr -> fx_file_current_relative_cluster = cluster_count - 1; + + /* If the remaining bytes exactly fits the cluster size, check for + a possible adjustment to the next cluster. */ + if ((bytes_remaining == bytes_per_cluster) && + (cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* We need to position to next allocated cluster. */ + file_ptr -> fx_file_current_physical_cluster = cluster; + file_ptr -> fx_file_current_relative_cluster++; + + /* Clear the remaining bytes. */ + bytes_remaining = 0; + } + + /* This is the cluster that contains the seek position. */ + break; + } + } + + /* Check for errors in traversal of the FAT chain. */ + if (byte_offset > (((ULONG64) bytes_per_cluster) * ((ULONG64) cluster_count))) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* This is an error that suggests a corrupt file. */ + return(FX_FILE_CORRUPT); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + else + { + + /* we should directly access the desired cluster */ + file_ptr -> fx_file_current_relative_cluster = (ULONG)(byte_offset / bytes_per_cluster); + + file_ptr -> fx_file_current_physical_cluster = + file_ptr -> fx_file_first_physical_cluster + file_ptr -> fx_file_current_relative_cluster; + + bytes_remaining = byte_offset % bytes_per_cluster; + } + + + /* Determine if the remaining bytes fit exactly into the cluster size. */ + if (bytes_remaining == bytes_per_cluster) + { + + /* Position to the end of the cluster. */ + file_ptr -> fx_file_current_logical_sector = (ULONG)(((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)file_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + ((bytes_remaining - 1) / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + file_ptr -> fx_file_current_relative_sector = (UINT)(((bytes_remaining - 1) / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + file_ptr -> fx_file_current_file_offset = byte_offset; + file_ptr -> fx_file_current_logical_offset = media_ptr -> fx_media_bytes_per_sector; + } + else + { + + /* Position the pointers to the new offset. */ + file_ptr -> fx_file_current_logical_sector = (ULONG)(((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)file_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + (bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + file_ptr -> fx_file_current_relative_sector = (UINT)((bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + file_ptr -> fx_file_current_file_offset = byte_offset; + file_ptr -> fx_file_current_logical_offset = (ULONG)(bytes_remaining % ((ULONG)media_ptr -> fx_media_bytes_per_sector)); + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Seek is complete, return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_extended_truncate.c b/src/Middlewares/ST/filex/common/src/fx_file_extended_truncate.c new file mode 100644 index 00000000..0c2987b0 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_extended_truncate.c @@ -0,0 +1,377 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_extended_truncate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the file to the specified size, if smaller than */ +/* the current file size. If the new file size is less than the */ +/* current file read/write position, the internal file pointers will */ +/* also be modified. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size New size of the file in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_extended_truncate(FX_FILE *file_ptr, ULONG64 size) +{ + +UINT status; +ULONG cluster; +ULONG contents = 0; +ULONG bytes_per_cluster; +ULONG last_cluster; +ULONG cluster_count; +ULONG64 bytes_remaining; +FX_MEDIA *media_ptr; + +#ifndef FX_DONT_UPDATE_OPEN_FILES +ULONG open_count; +FX_FILE *search_ptr; +#endif + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Setup pointer to media structure. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_truncates++; +#endif + + /* Setup pointer to associated media control block. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_TRUNCATE, file_ptr, size, file_ptr -> fx_file_current_file_size, 0, FX_TRACE_FILE_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Make sure this file is open for writing. */ + if (file_ptr -> fx_file_open_mode != FX_OPEN_FOR_WRITE) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the access error exception - a write was attempted from + a file opened for reading! */ + return(FX_ACCESS_ERROR); + } + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Setup the new file size - if less than the current size. */ + if (size < file_ptr -> fx_file_current_file_size) + { + + /* Setup the new size. */ + file_ptr -> fx_file_current_file_size = size; + + /* Set the modified flag as well. */ + file_ptr -> fx_file_modified = FX_TRUE; + + /* Update the trace event with the truncated size. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_TRUNCATE, 0, 0, 0, size) + } + else + { + + /* Update the trace event with the truncated size. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_TRUNCATE, 0, 0, 0, file_ptr -> fx_file_current_file_size) + + /* Release media protection. */ + FX_UNPROTECT + + /* Just return, the new size is larger than the current size. */ + return(FX_SUCCESS); + } + +#ifndef FX_DONT_UPDATE_OPEN_FILES + + /* Search the opened files list to see if the same file is opened for reading. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Is this file the same file opened for reading? */ + if ((search_ptr != file_ptr) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == + file_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == + file_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset)) + { + + /* Yes, the same file is opened for reading. */ + + /* Setup the new file size. */ + search_ptr -> fx_file_current_file_size = size; + search_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = size; + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } +#endif + + /* Now check to see if the read/write internal file pointers need + to be adjusted. */ + if (file_ptr -> fx_file_current_file_offset > file_ptr -> fx_file_current_file_size) + { + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* At this point, we are ready to walk list of clusters to setup the + seek position of this file. */ + cluster = file_ptr -> fx_file_first_physical_cluster; + bytes_remaining = size; + last_cluster = 0; + cluster_count = 0; + + /* Follow the link of FAT entries. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Increment the number of clusters. */ + cluster_count++; +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + if (cluster >= file_ptr -> fx_file_last_physical_cluster) + { + contents = FX_LAST_CLUSTER_exFAT; + } + else + { + contents = cluster + 1; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Save the last valid cluster. */ + last_cluster = cluster; + + /* Setup for the next cluster. */ + cluster = contents; + + /* Determine if this is the last written cluster. */ + if (bytes_remaining >= bytes_per_cluster) + { + + /* Still more seeking, just decrement the working byte offset. */ + bytes_remaining = bytes_remaining - bytes_per_cluster; + } + else + { + + /* This is the cluster that contains the seek position. */ + break; + } + } + + /* Check for errors in traversal of the FAT chain. */ + if (size > (((ULONG64) bytes_per_cluster) * ((ULONG64) cluster_count))) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* This is an error that suggests a corrupt file. */ + return(FX_FILE_CORRUPT); + } + + /* Position the pointers to the new offset. */ + file_ptr -> fx_file_current_physical_cluster = last_cluster; + file_ptr -> fx_file_current_relative_cluster = cluster_count - 1; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)file_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + (bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector); + file_ptr -> fx_file_current_relative_sector = (UINT)((bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + file_ptr -> fx_file_current_file_offset = size; + file_ptr -> fx_file_current_logical_offset = (ULONG)bytes_remaining % ((ULONG)media_ptr -> fx_media_bytes_per_sector); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = file_ptr -> fx_file_current_file_size; + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Error writing the directory. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Error writing the directory. */ + return(status); + } + + /* Update maximum size used if necessary. */ + if (size < file_ptr -> fx_file_maximum_size_used) + { + file_ptr -> fx_file_maximum_size_used = size; + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Truncate is complete, return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c b/src/Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c new file mode 100644 index 00000000..3e158d0f --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_extended_truncate_release.c @@ -0,0 +1,973 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_extended_truncate_release PORTABLE C */ +/* 6.1.3 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the file to the specified size, if smaller than */ +/* the current file size. If the new file size is less than the */ +/* current file read/write position, the internal file pointers will */ +/* also be modified. Any unused clusters are released back to the */ +/* media. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size New size of the file in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write directory entry */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* _fx_fault_tolerant_set_FAT_chain Set data of FAT chain */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 12-31-2020 William E. Lamie Modified comment(s), fixed */ +/* available cluster issue, */ +/* resulting in version 6.1.3 */ +/* */ +/**************************************************************************/ +UINT _fx_file_extended_truncate_release(FX_FILE *file_ptr, ULONG64 size) +{ + +UINT status; +ULONG cluster; +ULONG contents; +ULONG bytes_per_cluster; +ULONG last_cluster; +ULONG cluster_count; +ULONG64 bytes_remaining; +FX_MEDIA *media_ptr; + +#ifdef FX_ENABLE_EXFAT +ULONG original_last_physical_cluster; +#endif /* FX_ENABLE_EXFAT */ + +#ifndef FX_DONT_UPDATE_OPEN_FILES +ULONG open_count; +FX_FILE *search_ptr; +#endif + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Setup pointer to media structure. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_truncate_releases++; +#endif + + /* Setup pointer to associated media control block. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_TRUNCATE_RELEASE, file_ptr, size, file_ptr -> fx_file_current_file_size, 0, FX_TRACE_FILE_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Make sure this file is open for writing. */ + if (file_ptr -> fx_file_open_mode != FX_OPEN_FOR_WRITE) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the access error exception - a write was attempted from + a file opened for reading! */ + return(FX_ACCESS_ERROR); + } + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check for invalid value. */ + if (bytes_per_cluster == 0) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Setup the new file available size - if less than the current available size. */ + if (size < file_ptr -> fx_file_current_available_size) + { + + /* Yes, the file needs to be truncated. */ + + /* Update the available file size. */ + file_ptr -> fx_file_current_available_size = ((size + bytes_per_cluster - 1) / bytes_per_cluster) * bytes_per_cluster; + + /* Is the new available size less than the actual file size? */ + if (size < file_ptr -> fx_file_current_file_size) + { + + /* Setup the new file size. */ + file_ptr -> fx_file_current_file_size = size; + + /* Set the modified flag. */ + file_ptr -> fx_file_modified = FX_TRUE; + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = size; + + /* Set the first cluster to NULL. */ + if (size == 0) + { + + /* Yes, the first cluster needs to be cleared since the entire + file is going to be truncated. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster = FX_NULL; + } + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write( + media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Error writing the directory. */ + return(status); + } + } + + /* Update the trace event with the truncated size. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_TRUNCATE_RELEASE, 0, 0, 0, file_ptr -> fx_file_current_file_size) + } + else + { + + /* Update the trace event with the truncated size. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_TRUNCATE_RELEASE, 0, 0, 0, file_ptr -> fx_file_current_file_size) + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Just return, the truncate size is larger than the available size. */ + return(FX_SUCCESS); + } + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Now check to see if the read/write internal file pointers need + to be adjusted. */ + if (file_ptr -> fx_file_current_file_offset > file_ptr -> fx_file_current_file_size) + { + + + /* At this point, we are ready to walk list of clusters to setup the + seek position of this file. */ + cluster = file_ptr -> fx_file_first_physical_cluster; + bytes_remaining = size; + last_cluster = 0; + cluster_count = 0; + + /* Follow the link of FAT entries. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Increment the number of clusters. */ + cluster_count++; + +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + if (cluster >= file_ptr -> fx_file_last_physical_cluster) + { + contents = FX_LAST_CLUSTER_exFAT; + } + else + { + contents = cluster + 1; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Save the last valid cluster. */ + last_cluster = cluster; + + /* Setup for the next cluster. */ + cluster = contents; + + /* Determine if this is the last written cluster. */ + if (bytes_remaining >= bytes_per_cluster) + { + + /* Still more seeking, just decrement the working byte offset. */ + bytes_remaining = bytes_remaining - bytes_per_cluster; + } + else + { + + /* This is the cluster that contains the seek position. */ + break; + } + } + + /* Check for errors in traversal of the FAT chain. */ + if (size > (((ULONG64) bytes_per_cluster) * ((ULONG64) cluster_count))) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* This is an error that suggests a corrupt file. */ + return(FX_FILE_CORRUPT); + } + + /* Position the pointers to the new offset. */ + file_ptr -> fx_file_current_physical_cluster = last_cluster; + file_ptr -> fx_file_current_relative_cluster = cluster_count - 1; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)file_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + (bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector); + file_ptr -> fx_file_current_relative_sector = (UINT)((bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + file_ptr -> fx_file_current_file_offset = size; + file_ptr -> fx_file_current_logical_offset = (ULONG)bytes_remaining % ((ULONG)media_ptr -> fx_media_bytes_per_sector); + } + + /* Determine how many clusters are actually in-use now. */ + cluster_count = (ULONG) (file_ptr -> fx_file_current_available_size + (((ULONG64) bytes_per_cluster) - ((ULONG64) 1)))/bytes_per_cluster; + + /* Save the number of clusters in-use. */ + file_ptr -> fx_file_total_clusters = cluster_count; + + /* At this point, we are ready to walk list of clusters to find the clusters + that can be released. */ + cluster = file_ptr -> fx_file_first_physical_cluster; +#ifdef FX_ENABLE_EXFAT + original_last_physical_cluster = file_ptr -> fx_file_last_physical_cluster; +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Is this the last used cluster? */ + if ((cluster_count == 0) && (media_ptr -> fx_media_fault_tolerant_enabled)) + { +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Set undo log. */ + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, FX_FALSE, FX_FREE_CLUSTER, + media_ptr -> fx_media_fat_last, cluster, media_ptr -> fx_media_fat_last); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } + else + { + + /* Set undo log. */ + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, FX_TRUE, FX_FREE_CLUSTER, + media_ptr -> fx_media_fat_last, cluster, file_ptr -> fx_file_last_physical_cluster + 1); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT && FX_ENABLE_FAULT_TOLERANT */ + + file_ptr -> fx_file_last_physical_cluster = cluster; + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Follow the link of FAT entries. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + if (cluster >= original_last_physical_cluster) + { + contents = FX_LAST_CLUSTER_exFAT; + } + else + { + contents = cluster + 1; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if are more clusters to release. */ + if (cluster_count > 0) + { + + /* Decrement the number of clusters. */ + cluster_count--; + + /* Is this the last used cluster? */ + if (cluster_count == 0) + { +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) +#endif /* FX_ENABLE_EXFAT */ + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Set undo phase. */ + media_ptr -> fx_media_fault_tolerant_state |= FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN; + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Set undo log. */ + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, FX_FALSE, cluster, + media_ptr -> fx_media_fat_last, contents, media_ptr -> fx_media_fat_last); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Yes, it should be designated as last cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, cluster, media_ptr -> fx_media_fat_last); + + /* Check the return value. */ + if (status) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Clear undo phase. */ + media_ptr -> fx_media_fault_tolerant_state &= (UCHAR)(~FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN & 0xff); + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } +#if defined(FX_ENABLE_EXFAT) && defined(FX_ENABLE_FAULT_TOLERANT) + else if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Set undo log. */ + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, FX_TRUE, cluster, + media_ptr -> fx_media_fat_last, contents, file_ptr -> fx_file_last_physical_cluster + 1); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT && FX_ENABLE_FAULT_TOLERANT */ + + file_ptr -> fx_file_last_physical_cluster = cluster; + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries. */ + status = _fx_utility_FAT_flush(media_ptr); + + /* Check the return value. */ + if (status) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#endif + } + } + else + { + + /* This is a cluster after the clusters used by the file, release + it back to the media. */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled == FX_FALSE) + { +#endif /* FX_ENABLE_FAULT_TOLERANT */ + +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_utility_FAT_entry_write(media_ptr, cluster, FX_FREE_CLUSTER); + + /* Check the return value. */ + if (status) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } + + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Mark the cluster as free. */ + _fx_utility_exFAT_cluster_state_set(media_ptr, cluster, FX_EXFAT_BITMAP_CLUSTER_FREE); + } +#endif /* FX_ENABLE_EXFAT */ + + /* Increment the number of available clusters. */ + media_ptr -> fx_media_available_clusters++; + +#ifdef FX_ENABLE_FAULT_TOLERANT + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + + /* Setup for the next cluster. */ + cluster = contents; + } + + /* Determine if we need to adjust the number of leading consecutive clusters. */ + if (file_ptr -> fx_file_consecutive_cluster > file_ptr -> fx_file_total_clusters) + { + + /* Adjust the leading consecutive cluster count. */ + file_ptr -> fx_file_consecutive_cluster = file_ptr -> fx_file_total_clusters; + } + + /* Determine if the file available size has been truncated to zero. */ + if (file_ptr -> fx_file_current_available_size == 0) + { + + /* Yes, the first cluster has already been released. Update the file info + to indicate the file has no clusters. */ + file_ptr -> fx_file_last_physical_cluster = 0; + file_ptr -> fx_file_first_physical_cluster = 0; + file_ptr -> fx_file_current_physical_cluster = 0; + file_ptr -> fx_file_current_logical_sector = 0; + file_ptr -> fx_file_current_relative_cluster = 0; + file_ptr -> fx_file_current_relative_sector = 0; + file_ptr -> fx_file_current_available_size = 0; + file_ptr -> fx_file_consecutive_cluster = 1; + } + +#ifndef FX_DONT_UPDATE_OPEN_FILES + + /* Search the opened files list to see if the same file is opened for reading. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Is this file the same file opened for reading? */ + if ((search_ptr != file_ptr) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == + file_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == + file_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset)) + { + + /* Yes, the same file is opened for reading. */ + + /* Setup the new file size. */ + search_ptr -> fx_file_current_file_size = size; + + /* Setup the new total clusters. */ + search_ptr -> fx_file_total_clusters = file_ptr -> fx_file_total_clusters; + + /* Copy the directory entry. */ + search_ptr -> fx_file_dir_entry.fx_dir_entry_cluster = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster; + search_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size; + search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector = file_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector; + search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset = file_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset; + + /* Setup the other file parameters. */ + search_ptr -> fx_file_last_physical_cluster = file_ptr -> fx_file_last_physical_cluster; + search_ptr -> fx_file_first_physical_cluster = file_ptr -> fx_file_first_physical_cluster; + search_ptr -> fx_file_current_available_size = file_ptr -> fx_file_current_available_size; + search_ptr -> fx_file_consecutive_cluster = file_ptr -> fx_file_consecutive_cluster; + + /* Determine if the truncated file is smaller than the current file offset. */ + if (search_ptr -> fx_file_current_file_offset > size) + { + + /* Yes, the current file parameters need to be changed since the file was + truncated to a position prior to the current file position. */ + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* At this point, we are ready to walk list of clusters to setup the + seek position of this file. */ + cluster = search_ptr -> fx_file_first_physical_cluster; + bytes_remaining = size; + last_cluster = 0; + cluster_count = 0; + + /* Follow the link of FAT entries. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Increment the number of clusters. */ + cluster_count++; + +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + if (cluster >= file_ptr -> fx_file_last_physical_cluster) + { + contents = FX_LAST_CLUSTER_exFAT; + } + else + { + contents = cluster + 1; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Save the last valid cluster. */ + last_cluster = cluster; + + /* Setup for the next cluster. */ + cluster = contents; + + /* Determine if this is the last written cluster. */ + if (bytes_remaining >= bytes_per_cluster) + { + + /* Still more seeking, just decrement the working byte offset. */ + bytes_remaining = bytes_remaining - bytes_per_cluster; + } + else + { + + /* This is the cluster that contains the seek position. */ + break; + } + } + + /* Check for errors in traversal of the FAT chain. */ + if (size > (((ULONG64) bytes_per_cluster) * ((ULONG64) cluster_count))) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* This is an error that suggests a corrupt file. */ + return(FX_FILE_CORRUPT); + } + + /* Position the pointers to the new offset. */ + + /* Determine if there is at least one cluster. */ + if (cluster_count) + { + + /* Calculate real file parameters. */ + search_ptr -> fx_file_current_physical_cluster = last_cluster; + search_ptr -> fx_file_current_relative_cluster = cluster_count - 1; + search_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)search_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + (bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector); + search_ptr -> fx_file_current_relative_sector = (UINT)((bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + search_ptr -> fx_file_current_file_offset = size; + search_ptr -> fx_file_current_logical_offset = (ULONG)bytes_remaining % ((ULONG)media_ptr -> fx_media_bytes_per_sector); + } + else + { + + /* Calculate zero-length file parameters. */ + search_ptr -> fx_file_current_physical_cluster = 0; + search_ptr -> fx_file_current_relative_cluster = 0; + search_ptr -> fx_file_current_logical_sector = 0; + search_ptr -> fx_file_current_relative_sector = 0; + search_ptr -> fx_file_current_file_offset = 0; + search_ptr -> fx_file_current_logical_offset = 0; + } + } + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } +#endif + +#ifdef FX_FAULT_TOLERANT + + /* Flush the cached individual FAT entries */ + status = _fx_utility_FAT_flush(media_ptr); + + /* Check the return value. */ + if (status) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + /* Flush Bit Map. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + +#endif + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED)) + { + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = file_ptr -> fx_file_current_file_size; + } + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Error writing the directory. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* Update maximum size used if necessary. */ + if (size < file_ptr -> fx_file_maximum_size_used) + { + file_ptr -> fx_file_maximum_size_used = size; + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Truncate is complete, return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_open.c b/src/Middlewares/ST/filex/common/src/fx_file_open.c new file mode 100644 index 00000000..89a68b44 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_open.c @@ -0,0 +1,606 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_open PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified file. If found, */ +/* the open request is validated and the file is opened. During the */ +/* opening process, all of the FAT entries for this file are examined */ +/* for their integrity. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_ptr File control block pointer */ +/* file_name Name pointer */ +/* open_type Type of open requested */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable fast open and */ +/* consecutive detect, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_open(FX_MEDIA *media_ptr, FX_FILE *file_ptr, CHAR *file_name, UINT open_type) +{ + +UINT status; +#ifndef FX_DISABLE_CONSECUTIVE_DETECT +UINT leading_consecutive; +#endif /* FX_DISABLE_CONSECUTIVE_DETECT */ +ULONG cluster; +ULONG contents = 0; +ULONG open_count; +FX_FILE *tail_ptr; +FX_FILE *search_ptr; +ULONG bytes_per_cluster; +UINT last_cluster; +ULONG cluster_count; +ULONG64 bytes_available; +ULONG64 bytes_remaining; +ULONG fat_last; +#ifndef FX_DISABLE_FAST_OPEN +UINT fast_open; +#endif /* FX_DISABLE_FAST_OPEN */ +UCHAR not_a_file_attr; + + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_opens++; +#endif + + /* Clear the notify function. */ + file_ptr -> fx_file_write_notify = FX_NULL; + + /* Determine the type of FAT and setup variables accordingly. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + fat_last = FX_LAST_CLUSTER_exFAT; + not_a_file_attr = FX_DIRECTORY; + } + else if (media_ptr -> fx_media_FAT_type == FX_FAT32) +#else + if (media_ptr -> fx_media_32_bit_FAT) +#endif /* FX_ENABLE_EXFAT */ + { + fat_last = FX_LAST_CLUSTER_1_32; + not_a_file_attr = FX_DIRECTORY | FX_VOLUME; + } + else + { + fat_last = FX_LAST_CLUSTER_1; + not_a_file_attr = FX_DIRECTORY | FX_VOLUME; + } + +#ifndef FX_DISABLE_FAST_OPEN + /* Determine if a fast open is selected. */ + if (open_type == FX_OPEN_FOR_READ_FAST) + { + + /* Yes, convert the open type to a standard read. */ + open_type = FX_OPEN_FOR_READ; + + /* Set the open fast flag. */ + fast_open = FX_TRUE; + } + else + { + + /* A fast open is not selected, set the flag to false. */ + fast_open = FX_FALSE; + } +#endif /* FX_DISABLE_FAST_OPEN */ + + /* If trace is enabled, register this object. */ + FX_TRACE_OBJECT_REGISTER(FX_TRACE_OBJECT_TYPE_FILE, file_ptr, file_name, 0, 0) + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_OPEN, media_ptr, file_ptr, file_name, open_type, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Setup file name pointer. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_name = file_ptr -> fx_file_name_buffer; + file_ptr -> fx_file_dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, file_name, &(file_ptr -> fx_file_dir_entry), FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check to make sure the found entry is a file. */ + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_attributes & not_a_file_attr) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_NOT_A_FILE); + } + +#ifdef FX_SINGLE_OPEN_LEGACY + /* Check to make sure the access is okay. */ + if (open_type == FX_OPEN_FOR_READ) + { + + /* Check the list of open files for others open for writing. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Look at each opened file to see if the same file is opened + for writing. */ + if ((search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == + file_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == + file_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset) && + (search_ptr -> fx_file_open_mode)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* The file has been opened for writing by a previous call. */ + return(FX_ACCESS_ERROR); + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } + } + else +#else + if (open_type == FX_OPEN_FOR_WRITE) +#endif + { + + /* A open for write request is present, check the file attributes + and the list of open files for any other open instance of + this file. */ + if (media_ptr -> fx_media_driver_write_protect) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_attributes & (UCHAR)(FX_READ_ONLY)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_ACCESS_ERROR); + } + + /* Also search the opened files to see if this file is currently + opened. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Look at each opened file to see if the same file is already opened. */ +#ifdef FX_SINGLE_OPEN_LEGACY + if ((search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == + file_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == + file_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset)) +#else + /* Look at each opened file to see if the same file is already opened + for writing. */ + if ((search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == + file_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == + file_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset) && + (search_ptr -> fx_file_open_mode == FX_OPEN_FOR_WRITE)) +#endif + { + + /* Release media protection. */ + FX_UNPROTECT + + /* The file is currently open. */ + return(FX_ACCESS_ERROR); + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } + } + + /* At this point, we are ready to walk list of clusters to setup the + initial condition of this file as well as to verify its integrity. */ + cluster = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster; + bytes_remaining = file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size; + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + file_ptr -> fx_file_current_physical_cluster = 0; + + /* Check for invalid value. */ + if (bytes_per_cluster == 0) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + last_cluster = 0; + cluster_count = 0; + +#ifndef FX_DISABLE_CONSECUTIVE_DETECT + leading_consecutive = 1; +#endif /* FX_DISABLE_CONSECUTIVE_DETECT */ + file_ptr -> fx_file_consecutive_cluster = 1; +#ifndef FX_DISABLE_FAST_OPEN + + /* Determine if the file is being open for reading with the fast option. */ + if (fast_open) + { + + /* Calculate the bytes available. */ + bytes_available = ((bytes_remaining + bytes_per_cluster - 1) / bytes_per_cluster) * bytes_per_cluster; + +#ifdef FX_ENABLE_EXFAT + if (bytes_remaining && (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { + cluster_count = + (ULONG)((file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size + bytes_per_cluster - 1) / + bytes_per_cluster); + file_ptr -> fx_file_consecutive_cluster = cluster_count; + } +#endif /* FX_ENABLE_EXFAT */ + } + else +#endif /* FX_DISABLE_FAST_OPEN */ + { +#ifdef FX_ENABLE_EXFAT + + /* File is open for writing... walk the FAT chain to position to the end. */ + + if (bytes_remaining && (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { + cluster_count = + (ULONG)((file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size + bytes_per_cluster - 1) / + bytes_per_cluster); + + last_cluster = cluster + cluster_count - 1; + + file_ptr -> fx_file_consecutive_cluster = cluster_count; + + file_ptr -> fx_file_current_physical_cluster = last_cluster; + + file_ptr -> fx_file_current_relative_cluster = cluster_count - 1; + + bytes_remaining %= bytes_per_cluster; + + if (!bytes_remaining) + { + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_available_file_size > + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size) + { + file_ptr -> fx_file_current_physical_cluster = last_cluster + 1; + file_ptr -> fx_file_current_relative_cluster++; + } + else + { + bytes_remaining = bytes_per_cluster; + } + } + + bytes_available = + (ULONG)((file_ptr -> fx_file_dir_entry.fx_dir_entry_available_file_size + bytes_per_cluster - 1) / + bytes_per_cluster); + bytes_available *= bytes_per_cluster; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Follow the link of FAT entries. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Increment the number of clusters. */ + cluster_count++; + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Determine if the cluster is invalid (points to itself) or the count exceeds the total number of clusters. */ + if ((cluster == contents) || (cluster_count > media_ptr -> fx_media_total_clusters)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + +#ifndef FX_DISABLE_CONSECUTIVE_DETECT + + /* Check if present and next clusters are consecutive */ + if (cluster + 1 == contents) + { + + /* Determine if clusters are consecutive so far. */ + if (leading_consecutive) + { + + /* Yes, increment the number of leading consecutive clusters. */ + file_ptr -> fx_file_consecutive_cluster++; + } + } + else + { + + /* The clusters are no longer consecutive, clear the consecutive flag. */ + leading_consecutive = 0; + } +#endif /* FX_DISABLE_CONSECUTIVE_DETECT */ + + /* Save the last valid cluster. */ + last_cluster = cluster; + + /* Setup for the next cluster. */ + cluster = contents; + + /* Determine if this is the last written cluster. We need to remember this + for open for writing. */ + if (bytes_remaining > bytes_per_cluster) + { + + /* Still more written clusters, just decrement the counter. */ + bytes_remaining = bytes_remaining - bytes_per_cluster; + } + else if (!file_ptr -> fx_file_current_physical_cluster) + { + + /* Remember this cluster number. */ + file_ptr -> fx_file_current_physical_cluster = last_cluster; + + /* Remember the relative cluster. */ + file_ptr -> fx_file_current_relative_cluster = cluster_count - 1; + + /* If the remaining bytes exactly fits the cluster size, check for + a possible adjustment to the next cluster. */ + if ((bytes_remaining == bytes_per_cluster) && + (cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* We need to position to next allocated cluster. */ + file_ptr -> fx_file_current_physical_cluster = cluster; + file_ptr -> fx_file_current_relative_cluster++; + + /* Clear the remaining bytes. */ + bytes_remaining = 0; + } + } + } + + /* Determine if the number of clusters is large enough to support the + specified file size. */ + bytes_available = ((ULONG64)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG64)media_ptr -> fx_media_sectors_per_cluster) * + ((ULONG64)cluster_count); + + /* Check the bytes available in the cluster chain against the directory entry file size. */ + if ((bytes_available < file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size) || + ((cluster_count) && (contents < fat_last))) + { + /* File is corrupt, release media protection. */ + FX_UNPROTECT + + /* Return a corrupt file error status. */ + return(FX_FILE_CORRUPT); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* The file is okay, populate the file control block and complete the + file open process. */ + file_ptr -> fx_file_id = FX_FILE_ID; + file_ptr -> fx_file_name = file_ptr -> fx_file_name_buffer; + file_ptr -> fx_file_media_ptr = media_ptr; + file_ptr -> fx_file_open_mode = open_type; + file_ptr -> fx_file_modified = FX_FALSE; + file_ptr -> fx_file_total_clusters = cluster_count; + file_ptr -> fx_file_first_physical_cluster = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster; + file_ptr -> fx_file_last_physical_cluster = last_cluster; + file_ptr -> fx_file_current_file_size = file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size; + file_ptr -> fx_file_current_available_size = bytes_available; + file_ptr -> fx_file_disable_burst_cache = FX_FALSE; + + /* Set the current settings based on how the file was opened. */ + if (open_type == FX_OPEN_FOR_READ) + { + + /* Position the pointers to the beginning of the file. */ + file_ptr -> fx_file_current_physical_cluster = file_ptr -> fx_file_first_physical_cluster; + file_ptr -> fx_file_current_relative_cluster = 0; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(file_ptr -> fx_file_first_physical_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + file_ptr -> fx_file_current_relative_sector = 0; + file_ptr -> fx_file_current_logical_offset = 0; + file_ptr -> fx_file_current_file_offset = 0; + } + else + { + + /* Open for writing - position the pointers to the end of the file. */ + + /* Determine if the remaining bytes fit exactly into the cluster size. */ + if (bytes_remaining == bytes_per_cluster) + { + + /* Position to the end of the cluster. */ + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)file_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + ((ULONG)(((bytes_remaining - 1) / (ULONG)media_ptr -> fx_media_bytes_per_sector))); + file_ptr -> fx_file_current_relative_sector = (ULONG)(((bytes_remaining - 1) / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + file_ptr -> fx_file_current_file_offset = file_ptr -> fx_file_current_file_size; + file_ptr -> fx_file_current_logical_offset = media_ptr -> fx_media_bytes_per_sector; + } + else + { + + /* Position file parameters at end of last cluster allocation. */ + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)file_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + ((ULONG)((bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector))); + file_ptr -> fx_file_current_relative_sector = (ULONG)((bytes_remaining / (ULONG)media_ptr -> fx_media_bytes_per_sector)); + file_ptr -> fx_file_current_file_offset = file_ptr -> fx_file_current_file_size; + file_ptr -> fx_file_current_logical_offset = (ULONG)bytes_remaining % ((ULONG)media_ptr -> fx_media_bytes_per_sector); + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* By default, the whole file is used. */ + file_ptr -> fx_file_maximum_size_used = file_ptr -> fx_file_current_file_size; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Place newly opened file on the list of open files for + this media. First, check for an empty list. */ + if (media_ptr -> fx_media_opened_file_list) + { + + /* Pickup tail pointer. */ + tail_ptr = (media_ptr -> fx_media_opened_file_list) -> fx_file_opened_previous; + + /* Place the new file in the list. */ + (media_ptr -> fx_media_opened_file_list) -> fx_file_opened_previous = file_ptr; + tail_ptr -> fx_file_opened_next = file_ptr; + + /* Setup this file's opened links. */ + file_ptr -> fx_file_opened_previous = tail_ptr; + file_ptr -> fx_file_opened_next = media_ptr -> fx_media_opened_file_list; + } + else + { + + /* The opened media list is empty. Add the media to empty list. */ + media_ptr -> fx_media_opened_file_list = file_ptr; + file_ptr -> fx_file_opened_next = file_ptr; + file_ptr -> fx_file_opened_previous = file_ptr; + } + + /* Increment the opened file counter. */ + media_ptr -> fx_media_opened_file_count++; + + /* Release media protection. */ + FX_UNPROTECT + + /* Open is complete, return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_read.c b/src/Middlewares/ST/filex/common/src/fx_file_read.c new file mode 100644 index 00000000..79166f27 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_read.c @@ -0,0 +1,463 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the specified number of bytes (or as many as */ +/* possible into the buffer supplied by the caller. The actual number */ +/* of bytes and the status of the read operation is returned to the */ +/* caller. In addition, various internal file pointers in the file */ +/* control block are also updated. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* buffer_ptr Buffer pointer */ +/* request_size Number of bytes requested */ +/* actual_size Pointer to variable for the */ +/* number of bytes read */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_logical_sector_read Read a logical sector */ +/* _fx_utility_memory_copy Fast memory copy routine */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_read(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG request_size, ULONG *actual_size) +{ + +UINT status; +ULONG bytes_remaining, i; +ULONG copy_bytes; +UCHAR *destination_ptr; +ULONG cluster, next_cluster; +UINT sectors; +FX_MEDIA *media_ptr; + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Setup pointer to media structure. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_reads++; +#endif + + /* Setup pointer to associated media control block. */ + media_ptr = file_ptr -> fx_file_media_ptr; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_READ, file_ptr, buffer_ptr, request_size, 0, FX_TRACE_FILE_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Next, determine if there is any more bytes to read in the file. */ + if (file_ptr -> fx_file_current_file_offset >= + file_ptr -> fx_file_current_file_size) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* The file is at the end, return the proper status and set the + actual size to 0. */ + *actual_size = 0; + return(FX_END_OF_FILE); + } + + /* At this point there is something to read. */ + + /* Setup local buffer pointer. */ + destination_ptr = (UCHAR *)buffer_ptr; + + /* Determine if there are less bytes left in the file than that specified + by the request. If so, adjust the requested size. */ + if ((ULONG64)request_size > + (file_ptr -> fx_file_current_file_size - file_ptr -> fx_file_current_file_offset)) + { + + /* Adjust the bytes remaining to what's available. */ + request_size = (ULONG)(file_ptr -> fx_file_current_file_size - file_ptr -> fx_file_current_file_offset); + } + + /* Setup the remaining number of bytes to read. */ + bytes_remaining = request_size; + + /* Loop to read all of the bytes. */ + while (bytes_remaining) + { + + /* Determine if a beginning or ending partial read is required. */ + if ((file_ptr -> fx_file_current_logical_offset) || + (bytes_remaining < media_ptr -> fx_media_bytes_per_sector)) + { + + /* A partial sector read is required. */ + + /* Read the current logical sector. */ + status = _fx_utility_logical_sector_read(media_ptr, + file_ptr -> fx_file_current_logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Copy the appropriate number of bytes into the destination buffer. */ + copy_bytes = media_ptr -> fx_media_bytes_per_sector - + file_ptr -> fx_file_current_logical_offset; + + /* Check to see if only a portion of the read sector needs to be + copied. */ + if (copy_bytes > bytes_remaining) + { + + /* Adjust the number of bytes to copy. */ + copy_bytes = bytes_remaining; + } + + /* Actually perform the memory copy. */ + _fx_utility_memory_copy(((UCHAR *)media_ptr -> fx_media_memory_buffer) + /* Use case of memcpy is verified. */ + file_ptr -> fx_file_current_logical_offset, + destination_ptr, copy_bytes); + + /* Increment the logical sector byte offset. */ + file_ptr -> fx_file_current_logical_offset = + file_ptr -> fx_file_current_logical_offset + copy_bytes; + + /* Adjust the remaining bytes to read. */ + bytes_remaining = bytes_remaining - copy_bytes; + + /* Adjust the pointer to the destination buffer. */ + destination_ptr = destination_ptr + copy_bytes; + } + else + { + + /* Attempt to read multiple sectors directly into the destination + buffer. */ + + /* Calculate the number of whole sectors to read directly into + the destination buffer. */ + sectors = (UINT)(bytes_remaining / media_ptr -> fx_media_bytes_per_sector); + + + next_cluster = cluster = file_ptr -> fx_file_current_physical_cluster; + for (i = (media_ptr -> fx_media_sectors_per_cluster - + file_ptr -> fx_file_current_relative_sector); i < sectors; i += media_ptr -> fx_media_sectors_per_cluster) + { +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + cluster++; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Determine if an error is present. */ + if ((status != FX_SUCCESS) || (next_cluster < FX_FAT_ENTRY_START) || + (next_cluster > media_ptr -> fx_media_fat_reserved)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Send error message back to caller. */ + if (status != FX_SUCCESS) + { + return(status); + } + else + { + return(FX_FILE_CORRUPT); + } + } + + if (next_cluster != cluster + 1) + { + break; + } + else + { + cluster = next_cluster; + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + + if (i < sectors) + { + sectors = i; + } + + /* Determine if this is a single sector read request. If so, read the sector so it will + come from the internal cache. */ + if (sectors == 1) + { + + /* Read the current logical sector. */ + status = _fx_utility_logical_sector_read(media_ptr, + file_ptr -> fx_file_current_logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Actually perform the memory copy. */ + _fx_utility_memory_copy((UCHAR *)media_ptr -> fx_media_memory_buffer, destination_ptr, media_ptr -> fx_media_bytes_per_sector); /* Use case of memcpy is verified. */ + } + else + { + + /* Multiple sector read request. Read all the sectors at once. */ + + /* Perform the data read directly into the user's buffer of + the appropriate number of sectors. */ + media_ptr -> fx_media_disable_burst_cache = file_ptr -> fx_file_disable_burst_cache; + status = _fx_utility_logical_sector_read(media_ptr, file_ptr -> fx_file_current_logical_sector, + destination_ptr, (ULONG) sectors, FX_DATA_SECTOR); + media_ptr -> fx_media_disable_burst_cache = FX_FALSE; + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } + + /* Now adjust the various file pointers. */ + + /* Increment the current logical sector. Subtract one from + the sector count because we are going to use the logical + offset to do additional sector/cluster arithmetic below. */ + file_ptr -> fx_file_current_logical_sector = + file_ptr -> fx_file_current_logical_sector + + (sectors - 1); + + /* Move the relative sector and cluster as well. */ + file_ptr -> fx_file_current_relative_cluster = file_ptr -> fx_file_current_relative_cluster + + (file_ptr -> fx_file_current_relative_sector + (sectors - 1)) / + media_ptr -> fx_media_sectors_per_cluster; + + file_ptr -> fx_file_current_relative_sector = + (file_ptr -> fx_file_current_relative_sector + + (sectors - 1)) % media_ptr -> fx_media_sectors_per_cluster; + + /* Increment the logical sector byte offset. */ + file_ptr -> fx_file_current_logical_offset = + media_ptr -> fx_media_bytes_per_sector; + + file_ptr -> fx_file_current_physical_cluster = cluster; + + /* Adjust the remaining bytes. */ + bytes_remaining = bytes_remaining - + (((ULONG)media_ptr -> fx_media_bytes_per_sector) * sectors); + + /* Adjust the pointer to the destination buffer. */ + destination_ptr = destination_ptr + + (((ULONG)media_ptr -> fx_media_bytes_per_sector) * sectors); + } + + /* At this point, we have either read a partial sector or have successfully + read one or more whole sectors. Determine if we are at the end of + the current logical sector. */ + if (file_ptr -> fx_file_current_logical_offset >= + media_ptr -> fx_media_bytes_per_sector) + { + + /* Determine if we are at the exact physical end of the file at the end of reading. */ + if ((bytes_remaining == 0) && ((file_ptr -> fx_file_current_file_offset + (ULONG64)request_size) >= + file_ptr -> fx_file_current_available_size)) + { + + /* Skip the following file parameter adjustments. The next write will + detect the logical offset out of the range of the sector and reset + all of the pertinent information. */ + break; + } + + /* We need to move to the next logical sector, but first + determine if the next logical sector is within the same + cluster. */ + + /* Increment the current relative sector in the cluster. */ + file_ptr -> fx_file_current_relative_sector++; + + /* Determine if this is in a new cluster. */ + if (file_ptr -> fx_file_current_relative_sector >= + media_ptr -> fx_media_sectors_per_cluster) + { +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + next_cluster = file_ptr -> fx_file_current_physical_cluster + 1; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Read the FAT entry of the current cluster to find + the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, + file_ptr -> fx_file_current_physical_cluster, &next_cluster); + + /* Determine if an error is present. */ + if ((status != FX_SUCCESS) || (next_cluster < FX_FAT_ENTRY_START) || + (next_cluster > media_ptr -> fx_media_fat_reserved)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Send error message back to caller. */ + if (status != FX_SUCCESS) + { + return(status); + } + else + { + return(FX_FILE_CORRUPT); + } + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Otherwise, we have a new cluster. Save it in the file + control block and calculate a new logical sector value. */ + file_ptr -> fx_file_current_physical_cluster = next_cluster; + file_ptr -> fx_file_current_relative_cluster++; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + ((((ULONG64)next_cluster) - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + file_ptr -> fx_file_current_relative_sector = 0; + } + else + { + + /* Still within the same cluster so just increment the + logical sector. */ + file_ptr -> fx_file_current_logical_sector++; + } + + /* In either case, we are now positioned at a new sector so + clear the logical sector offset. */ + file_ptr -> fx_file_current_logical_offset = 0; + } + } + + /* Adjust the current file offset accordingly. */ + file_ptr -> fx_file_current_file_offset = + file_ptr -> fx_file_current_file_offset + (ULONG64)request_size; + + /* Store the number of bytes actually read. */ + *actual_size = request_size; + + /* Update the trace event with the bytes read. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_READ, 0, 0, 0, request_size) + + /* Update the last accessed date. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_last_accessed_date = _fx_system_date; + + /* Release media protection. */ + FX_UNPROTECT + + /* Return a successful status to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_relative_seek.c b/src/Middlewares/ST/filex/common/src/fx_file_relative_seek.c new file mode 100644 index 00000000..b68277ab --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_relative_seek.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_relative_seek PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function positions the internal file pointers to the specified */ +/* byte relative offset such that the next read or write operation is */ +/* performed there. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* byte_offset Byte offset of the seek */ +/* seek_from Direction for relative seek, */ +/* legal values are: */ +/* */ +/* FX_SEEK_BEGIN */ +/* FX_SEEK_END */ +/* FX_SEEK_FORWARD */ +/* FX_SEEK_BACK */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_relative_seek Seek to specified position */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* Added conditional to */ +/* disable one line function, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT _fx_file_relative_seek(FX_FILE *file_ptr, ULONG byte_offset, UINT seek_from) +{ + + return(_fx_file_extended_relative_seek(file_ptr, (ULONG64)byte_offset, seek_from)); +} +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_rename.c b/src/Middlewares/ST/filex/common/src/fx_file_rename.c new file mode 100644 index 00000000..e32b74fe --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_rename.c @@ -0,0 +1,598 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_rename PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified file. If found, */ +/* the rename request is valid and the directory entry will be changed */ +/* to the new file name. Otherwise, if the file is not found, the */ +/* appropriate error code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* old_file_name Old file name pointer */ +/* new_file_name New file name pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the new directory entry */ +/* _fx_directory_free_search Search for a free directory */ +/* entry in target directory */ +/* _fx_directory_name_extract Extract the new filename */ +/* _fx_directory_search Search for the file name in */ +/* the directory structure */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_rename(FX_MEDIA *media_ptr, CHAR *old_file_name, CHAR *new_file_name) +{ + +ULONG i; +CHAR *work_ptr; +CHAR alpha, beta; +UINT status; + +#ifndef FX_DONT_UPDATE_OPEN_FILES +ULONG open_count; +FX_FILE *search_ptr; +#endif +CHAR *new_name_ptr; +FX_DIR_ENTRY old_dir_entry, new_dir_entry; +FX_DIR_ENTRY search_directory; +#ifdef FX_RENAME_PATH_INHERIT +UINT j; +#endif +UCHAR not_a_file_attr; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_renames++; +#endif + + /* Setup pointers to media name buffers. */ + old_dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + new_dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN * 2; + search_directory.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN * 3; + + /* Clear the short name strings. */ + old_dir_entry.fx_dir_entry_short_name[0] = 0; + new_dir_entry.fx_dir_entry_short_name[0] = 0; + search_directory.fx_dir_entry_short_name[0] = 0; + + /* Determine if the supplied name is less than the maximum supported name size. The + maximum name (FX_MAX_LONG_NAME_LEN) is defined in fx_api.h. */ + i = 0; + work_ptr = (CHAR *)new_file_name; + while (*work_ptr) + { + + /* Determine if the character designates a new path. */ + if ((*work_ptr == '\\') || (*work_ptr == '/')) + { + /* Yes, reset the name size. */ + i = 0; + } + /* Check for leading spaces. */ + else if ((*work_ptr != ' ') || (i != 0)) + { + + /* No leading spaces, increment the name size. */ + i++; + } + + /* Move to the next character. */ + work_ptr++; + } + + /* Determine if the supplied name is valid. */ + if ((i == 0) || (i >= FX_MAX_LONG_NAME_LEN)) + { + + /* Return an invalid name value. */ + return(FX_INVALID_NAME); + } + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_RENAME, media_ptr, old_file_name, new_file_name, 0, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, old_file_name, &old_dir_entry, &search_directory, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + not_a_file_attr = FX_DIRECTORY; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + not_a_file_attr = FX_DIRECTORY | FX_VOLUME; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check to make sure the found entry is a file. */ + if (old_dir_entry.fx_dir_entry_attributes & not_a_file_attr) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_NOT_A_FILE); + } + +#ifdef FX_RENAME_PATH_INHERIT + + /* Determine if the source file name has a path and the target file name does not. */ + if (((old_file_name[0] == '/') || (old_file_name[0] == '\\')) && (new_file_name[0] != '/') && (new_file_name[0] != '\\')) + { + + /* In this case, we need to prepend the path of the old file name to that of the new file name. */ + + /* Setup pointer to the rename buffer. */ + work_ptr = (CHAR *)media_ptr -> fx_media_rename_buffer; + + /* First, copy the path of the old file name. */ + i = 0; + j = 0; + while ((old_file_name[i]) && (i < FX_MAXIMUM_PATH)) + { + + /* Copy a character into the rename buffer. */ + *work_ptr++ = old_file_name[i]; + + /* Determine if this character is directory separator. */ + if ((old_file_name[i] == '/') || (old_file_name[i] == '\\')) + { + + /* Yes, directory separator has been found - remember the index. */ + j = i; + } + + /* Move to next position in the old file name. */ + i++; + } + + /* At this point, we have the path stored in the rename buffer. */ + + /* Position past the last slash or backslash. */ + j++; + + /* Reset the working pointer to the position after the last directory separator. */ + work_ptr = (CHAR *)&(media_ptr -> fx_media_rename_buffer[j]); + + /* Now copy the new file name into the rename buffer. */ + i = 0; + while ((new_file_name[i]) && (j < FX_MAXIMUM_PATH)) + { + + /* Copy a character into the rename buffer. */ + *work_ptr++ = new_file_name[i]; + + /* Move to next character. */ + i++; + j++; + } + + /* Determine if the path was successfully prepended. */ + if (new_file_name[i]) + { + + /* No, there was not enough room in the destination buffer. */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the invalid path error code. */ + return(FX_INVALID_PATH); + } + + /* Place a NULL at the end of the string. */ + *work_ptr = (CHAR)FX_NULL; + + /* At this point, we have successfully prepended the path in the new file name, override + the new file name so it is used from now on. */ + new_file_name = (CHAR *)media_ptr -> fx_media_rename_buffer; + } +#endif + + /* Search the target directory for the same file name. */ + status = _fx_directory_search(media_ptr, new_file_name, &new_dir_entry, &search_directory, &new_name_ptr); + + /* Determine if the name already exists. */ + if (status == FX_SUCCESS) + { + + /* Determine if the new name simply has an ASCII case change. If so, simply let the processing + continue. */ + i = 0; + do + { + + /* Pickup an old name and new name character and convert to upper case if necessary. */ + alpha = old_file_name[i]; + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Lower case, convert to upper case! */ + alpha = (CHAR)((INT)alpha - 0x20); + } + beta = new_file_name[i]; + if ((beta >= 'a') && (beta <= 'z')) + { + + /* Lower case, convert to upper case! */ + beta = (CHAR)((INT)beta - 0x20); + } + + /* Now compare the characters. */ + if ((alpha != beta) || (alpha == 0)) + { + + /* Get out of this loop! */ + break; + } + + /* Move to next character. */ + i++; + } while (i < (FX_MAXIMUM_PATH-1)); + + /* Now determine if the names match. */ + if (alpha != beta) + { + + /* No, the names do not match so simply return an error + to the caller. */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_ALREADY_CREATED); + } + } + + /* Change the file name and look for extra stuff at the end. */ + if (_fx_directory_name_extract(new_name_ptr, &new_dir_entry.fx_dir_entry_name[0])) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid name, return error status. */ + return(FX_INVALID_NAME); + } + + /* Search for a free spot in the target directory. */ + status = _fx_directory_free_search(media_ptr, &search_directory, &new_dir_entry); + + /* Determine if a free spot was found. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Extract the new file name. */ + _fx_directory_name_extract(new_name_ptr, &new_dir_entry.fx_dir_entry_name[0]); + + /* Determine if a long name is present. */ + if (new_dir_entry.fx_dir_entry_long_name_present) + { + + /* Yes, clear the short file name. */ + new_dir_entry.fx_dir_entry_short_name[0] = 0; + } + + /* Save the updated directory parameters. */ + new_dir_entry.fx_dir_entry_attributes = old_dir_entry.fx_dir_entry_attributes; + new_dir_entry.fx_dir_entry_cluster = old_dir_entry.fx_dir_entry_cluster; + new_dir_entry.fx_dir_entry_file_size = old_dir_entry.fx_dir_entry_file_size; + + /* Save the reserved field. */ + new_dir_entry.fx_dir_entry_reserved = old_dir_entry.fx_dir_entry_reserved; + + /* Set time and date stamps. */ + new_dir_entry.fx_dir_entry_created_time_ms = old_dir_entry.fx_dir_entry_created_time_ms; + new_dir_entry.fx_dir_entry_created_time = old_dir_entry.fx_dir_entry_created_time; + new_dir_entry.fx_dir_entry_created_date = old_dir_entry.fx_dir_entry_created_date; + new_dir_entry.fx_dir_entry_last_accessed_date = old_dir_entry.fx_dir_entry_last_accessed_date; + new_dir_entry.fx_dir_entry_time = old_dir_entry.fx_dir_entry_time; + new_dir_entry.fx_dir_entry_date = old_dir_entry.fx_dir_entry_date; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + new_dir_entry.fx_dir_entry_dont_use_fat = old_dir_entry.fx_dir_entry_dont_use_fat; + new_dir_entry.fx_dir_entry_type = old_dir_entry.fx_dir_entry_type; + new_dir_entry.fx_dir_entry_available_file_size = old_dir_entry.fx_dir_entry_available_file_size; + new_dir_entry.fx_dir_entry_secondary_count = old_dir_entry.fx_dir_entry_secondary_count; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Is there a leading dot? */ + if (new_dir_entry.fx_dir_entry_name[0] == '.') + { + + /* Yes, toggle the hidden attribute bit. */ + new_dir_entry.fx_dir_entry_attributes |= FX_HIDDEN; + } + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Invalidate the directory cache. */ + media_ptr -> fx_media_last_found_name[0] = FX_NULL; +#endif + + /* Now write out the directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &new_dir_entry, UPDATE_FULL); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &new_dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + +#ifndef FX_DONT_UPDATE_OPEN_FILES + + /* Search the opened files to update any currently opened files. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Look at each opened file to see if it matches the file being renamed. */ + if ((search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == + old_dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == + old_dir_entry.fx_dir_entry_byte_offset)) + { + + /* Yes, the file being renamed is already open. Update the file's + information so that it is kept current. */ + search_ptr -> fx_file_dir_entry.fx_dir_entry_cluster = new_dir_entry.fx_dir_entry_cluster; + search_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = new_dir_entry.fx_dir_entry_file_size; + search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector = new_dir_entry.fx_dir_entry_log_sector; + search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset = new_dir_entry.fx_dir_entry_byte_offset; + + /* Copy the new name into the file's name buffer. */ + i = 0; + while (i < (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Copy byte of the new name. */ + search_ptr -> fx_file_dir_entry.fx_dir_entry_name[i] = new_dir_entry.fx_dir_entry_name[i]; + + /* Move to the next character. */ + i++; + + /* Determine if we are at the end of the name. */ + if (new_dir_entry.fx_dir_entry_name[i] == FX_NULL) + { + + /* Determine if we are not at the maximum name size. */ + if (i < (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Get out of the loop. */ + break; + } + } + } + + /* Set the NULL termination in the copy of the new name. */ + search_ptr -> fx_file_dir_entry.fx_dir_entry_name[i] = FX_NULL; + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } +#endif + + /* Now we are ready to remove the old directory entry. */ + old_dir_entry.fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + old_dir_entry.fx_dir_entry_short_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + + /* Now wipe out the old directory entry. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &old_dir_entry, UPDATE_DELETE); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &old_dir_entry); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* File rename is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_seek.c b/src/Middlewares/ST/filex/common/src/fx_file_seek.c new file mode 100644 index 00000000..a587bb31 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_seek.c @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_seek PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function positions the internal file pointers to the specified */ +/* byte offset such that the next read or write operation will be */ +/* performed there. If the byte offset is greater than the size, the */ +/* file pointers will be positioned to the end of the file. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* byte_offset Byte offset into the file */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_seek Seek to specified position */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* Added conditional to */ +/* disable one line function, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT _fx_file_seek(FX_FILE *file_ptr, ULONG byte_offset) +{ + + return(_fx_file_extended_seek(file_ptr, (ULONG64) byte_offset)); +} +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ diff --git a/src/Middlewares/ST/filex/common/src/fx_file_truncate.c b/src/Middlewares/ST/filex/common/src/fx_file_truncate.c new file mode 100644 index 00000000..677eec5c --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_truncate.c @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_truncate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the file to the specified size, if smaller than */ +/* the current file size. If the new file size is less than the */ +/* current file read/write position, the internal file pointers will */ +/* also be modified. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size New size of the file in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_truncate Truncate the file size */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* Added conditional to */ +/* disable one line function, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT _fx_file_truncate(FX_FILE *file_ptr, ULONG size) +{ + + return(_fx_file_extended_truncate(file_ptr, (ULONG64)size)); +} +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ diff --git a/src/Middlewares/ST/filex/common/src/fx_file_truncate_release.c b/src/Middlewares/ST/filex/common/src/fx_file_truncate_release.c new file mode 100644 index 00000000..677db131 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_truncate_release.c @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_truncate_release PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the file to the specified size, if smaller than */ +/* the current file size. If the new file size is less than the */ +/* current file read/write position, the internal file pointers will */ +/* also be modified. Any unused clusters are released back to the */ +/* media. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size New size of the file in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_truncate_release Truncate the file size and */ +/* released unused clusters */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* Added conditional to */ +/* disable one line function, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +#ifndef FX_DISABLE_ONE_LINE_FUNCTION +UINT _fx_file_truncate_release(FX_FILE *file_ptr, ULONG size) +{ + + return(_fx_file_extended_truncate_release(file_ptr, (ULONG64)size)); +} +#endif /* FX_DISABLE_ONE_LINE_FUNCTION */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_write.c b/src/Middlewares/ST/filex/common/src/fx_file_write.c new file mode 100644 index 00000000..8e54b546 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_write.c @@ -0,0 +1,1770 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes the specified number of bytes into the file's */ +/* data area. The status of the write operation is returned to the */ +/* caller. In addition, various internal file pointers in the file */ +/* control block are also updated. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* buffer_ptr Buffer pointer */ +/* size Number of bytes to write */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Update the file's size */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_exFAT_bitmap_free_cluster_find */ +/* Find exFAT free cluster */ +/* _fx_utility_exFAT_cluster_state_get Get cluster state */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* _fx_utility_FAT_flush Flush written FAT entries */ +/* _fx_utility_logical_sector_flush Flush written logical sectors */ +/* _fx_utility_logical_sector_read Read a logical sector */ +/* _fx_utility_logical_sector_write Write a logical sector */ +/* _fx_utility_memory_copy Fast memory copy routine */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* _fx_fault_tolerant_set_FAT_chain Set data of FAT chain */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_write(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG size) +{ + +UINT status; +ULONG64 bytes_remaining; +ULONG i; +ULONG copy_bytes; +ULONG bytes_per_cluster; +UCHAR *source_ptr; +ULONG first_new_cluster; +ULONG last_cluster; +ULONG cluster, next_cluster; +ULONG FAT_index; +ULONG FAT_value; +ULONG clusters; +ULONG total_clusters; +UINT sectors; +FX_MEDIA *media_ptr; + +#ifdef FX_ENABLE_EXFAT +UCHAR cluster_state; +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_FAULT_TOLERANT_DATA +FX_INT_SAVE_AREA +#endif + +#ifndef FX_DONT_UPDATE_OPEN_FILES +ULONG open_count; +FX_FILE *search_ptr; +#endif + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + +#ifdef FX_ENABLE_FAULT_TOLERANT +UCHAR data_append = FX_FALSE; /* Whether or not new data would extend beyond the size of the original file. + Operations such as append or overwrite could cause the new file to exceed its + original size, resulting in data-appending operation. */ +ULONG copy_head_cluster = 0; /* The first cluster of the original chain that needs to be replaced. */ +ULONG copy_tail_cluster = 0; /* The last cluster of the original chain that needs to be replaced. */ +ULONG insertion_back; /* The insertion point (back) */ +ULONG insertion_front = 0; /* The insertion point (front) */ +ULONG replace_clusters = 0; /* The number of clusters to be replaced. */ +UCHAR dont_use_fat_old = FX_FALSE; /* Used by exFAT logic to indicate whether or not the FAT table should be used. */ +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + + /* First, determine if the file is still open. */ + if (file_ptr -> fx_file_id != FX_FILE_ID) + { + + /* Return the file not open error status. */ + return(FX_NOT_OPEN); + } + + /* Setup pointer to media structure. */ + media_ptr = file_ptr -> fx_file_media_ptr; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_file_writes++; +#endif + + +#ifdef FX_ENABLE_EXFAT + if ((media_ptr -> fx_media_FAT_type != FX_exFAT) && + (file_ptr -> fx_file_current_file_offset + size > 0xFFFFFFFFULL)) +#else + if (file_ptr -> fx_file_current_file_offset + size > 0xFFFFFFFFULL) +#endif /* FX_ENABLE_EXFAT */ + { + + /* Return the no more space error, since the new file size would be larger than + the 32-bit field to represent it in the file's directory entry. */ + return(FX_NO_MORE_SPACE); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize next cluster of tail. */ + insertion_back = media_ptr -> fx_media_fat_last; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_FILE_WRITE, file_ptr, buffer_ptr, size, 0, FX_TRACE_FILE_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Make sure this file is open for writing. */ + if (file_ptr -> fx_file_open_mode != FX_OPEN_FOR_WRITE) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the access error exception - a write was attempted from + a file opened for reading! */ + return(FX_ACCESS_ERROR); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check for invalid value. */ + if (bytes_per_cluster == 0) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Initialized first new cluster. */ + first_new_cluster = 0; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Calculate clusters need to be replaced when fault tolerant is enabled. */ + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + if (file_ptr -> fx_file_current_file_offset == file_ptr -> fx_file_current_file_size) + { + + /* Appending data. No need to replace existing clusters. */ + replace_clusters = 0; + } + else if (file_ptr -> fx_file_current_file_offset == file_ptr -> fx_file_maximum_size_used) + { + + /* Similar to append data. No actual data after fx_file_maximum_size_used. + * No need to replace existing clusters. */ + replace_clusters = 0; + } + else if (((file_ptr -> fx_file_current_file_offset / media_ptr -> fx_media_bytes_per_sector) == + ((file_ptr -> fx_file_current_file_offset + size - 1) / media_ptr -> fx_media_bytes_per_sector)) && + ((file_ptr -> fx_file_current_file_offset + size) <= file_ptr -> fx_file_current_file_size)) + { + + /* Overwriting data in one sector. No need to replace existing clusters. */ + replace_clusters = 0; + } + else if ((file_ptr -> fx_file_current_available_size - file_ptr -> fx_file_current_file_offset) < size) + { + + /* Replace all clusters from current_cluster. */ + replace_clusters = (UINT)(file_ptr -> fx_file_total_clusters - file_ptr -> fx_file_current_relative_cluster); + copy_head_cluster = file_ptr -> fx_file_current_physical_cluster; + + data_append = FX_TRUE; + } + else + { + + /* Replace clusters from current_cluster to the end of written cluster. */ + replace_clusters = (UINT)((file_ptr -> fx_file_current_file_offset + size + bytes_per_cluster - 1) / bytes_per_cluster - + file_ptr -> fx_file_current_relative_cluster); + copy_head_cluster = file_ptr -> fx_file_current_physical_cluster; + data_append = FX_FALSE; + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Next, determine if there is enough room to write the specified number of + bytes to the clusters already allocated to this file. */ + if (((file_ptr -> fx_file_current_available_size - file_ptr -> fx_file_current_file_offset) < size) +#ifdef FX_ENABLE_FAULT_TOLERANT + || (replace_clusters) +#endif /* FX_ENABLE_FAULT_TOLERANT */ + ) + { + + /* The new request will not fit within the currently allocated clusters. */ + + /* Calculate the number of additional clusters that must be allocated for this + write request. */ +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Find the number of clusters that need to be replaced. */ + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Mark the recovery phase. */ + media_ptr -> fx_media_fault_tolerant_state |= FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN; + + bytes_remaining = file_ptr -> fx_file_current_file_offset + size; + + if (replace_clusters > 0) + { + +#ifdef FX_ENABLE_EXFAT + if ((media_ptr -> fx_media_FAT_type == FX_exFAT) && (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { + /* Find the insertion points in the exFAT with bitmap case.. this is a simple case.. */ + /* The previous cluster is not initialized. Find it. */ + if (copy_head_cluster != file_ptr -> fx_file_first_physical_cluster) + { + insertion_front = copy_head_cluster - 1; + } + + /* Find copy tail cluster. */ + if (data_append == FX_FALSE) + { + copy_tail_cluster = file_ptr -> fx_file_first_physical_cluster + (ULONG)((bytes_remaining - 1) / bytes_per_cluster); + if (copy_tail_cluster != file_ptr -> fx_file_last_physical_cluster) + { + insertion_back = copy_tail_cluster + 1; + } + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Find previous cluster of copy head cluster. */ + /* The previous cluster is not initialized. Find it. */ + if (copy_head_cluster != file_ptr -> fx_file_first_physical_cluster) + { + + /* The copy head cluster is not the first cluster of file. */ + /* Copy head is not the first cluster of file. */ + if (file_ptr -> fx_file_current_relative_cluster < file_ptr -> fx_file_consecutive_cluster) + { + + /* Clusters before current cluster are consecutive. */ + insertion_front = copy_head_cluster - 1; + bytes_remaining -= file_ptr -> fx_file_current_relative_cluster * bytes_per_cluster; + } + else + { + + /* Skip consecutive clusters first. */ + cluster = file_ptr -> fx_file_first_physical_cluster; + + /* Loop the link of FAT to find the previous cluster. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Reduce remaining bytes. */ + bytes_remaining -= bytes_per_cluster; + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &FAT_value); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + if (FAT_value == copy_head_cluster) + { + break; + } + + /* Move to next cluster. */ + cluster = FAT_value; + } + + if ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Find the previous cluster. */ + insertion_front = cluster; + } + else + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(FX_NOT_FOUND); + } + } + } + + /* Find copy tail cluster. */ + if (bytes_remaining <= bytes_per_cluster) + { + + /* Only one cluster is modified. */ + copy_tail_cluster = copy_head_cluster; + } + else if (data_append == FX_FALSE) + { + + /* Search from copy head cluster. */ + cluster = copy_head_cluster; + FAT_value = FX_FAT_ENTRY_START; + + /* Loop the link of FAT to find the previous cluster. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + if (bytes_remaining <= bytes_per_cluster) + { + break; + } + + /* Reduce remaining bytes. */ + bytes_remaining -= bytes_per_cluster; + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &FAT_value); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Move to next cluster. */ + cluster = FAT_value; + } + + /* Find the previous cluster. */ + copy_tail_cluster = FAT_value; + } + + /* Get the cluster next to copy tail. */ + if (data_append == FX_FALSE) + { + + /* Read FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, copy_tail_cluster, &insertion_back); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + else + { + insertion_back = media_ptr -> fx_media_fat_last; + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + else + { + insertion_back = media_ptr -> fx_media_fat_last; + } + } + + if (file_ptr -> fx_file_current_available_size - file_ptr -> fx_file_current_file_offset < size) + { +#endif /* FX_ENABLE_FAULT_TOLERANT */ + /* Calculate clusters that are needed for data append except ones overwritten. */ + clusters = (UINT)((size + (bytes_per_cluster - 1) - + (file_ptr -> fx_file_current_available_size - file_ptr -> fx_file_current_file_offset)) / + bytes_per_cluster); +#ifdef FX_ENABLE_FAULT_TOLERANT + } + else + { + clusters = 0; + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if we have enough space left. */ +#ifdef FX_ENABLE_FAULT_TOLERANT + if (clusters + replace_clusters > media_ptr -> fx_media_available_clusters) +#else + if (clusters > media_ptr -> fx_media_available_clusters) +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Out of disk space. */ + return(FX_NO_MORE_SPACE); + } + + /* Update the file total cluster count. */ + file_ptr -> fx_file_total_clusters = file_ptr -> fx_file_total_clusters + clusters; + + /* Check for wrap-around when updating the available size. */ +#ifdef FX_ENABLE_EXFAT + if ((media_ptr -> fx_media_FAT_type != FX_exFAT) && + (file_ptr -> fx_file_current_available_size + (ULONG64)bytes_per_cluster * (ULONG64)clusters > 0xFFFFFFFFULL)) +#else + if (file_ptr -> fx_file_current_available_size + (ULONG64)bytes_per_cluster * (ULONG64)clusters > 0xFFFFFFFFULL) +#endif /* FX_ENABLE_EXFAT */ + { + + /* 32-bit wrap around condition is present. Just set the available file size to all ones, which is + the maximum file size. */ + file_ptr -> fx_file_current_available_size = 0xFFFFFFFFULL; + } + else + { + + /* Normal condition, update the available size. */ + file_ptr -> fx_file_current_available_size = + file_ptr -> fx_file_current_available_size + (ULONG64)bytes_per_cluster * (ULONG64)clusters; + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Account for newly allocated clusters. */ + clusters += replace_clusters; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Decrease the available clusters in the media control block. */ + media_ptr -> fx_media_available_clusters = media_ptr -> fx_media_available_clusters - clusters; + +#if defined(FX_ENABLE_EXFAT) && defined(FX_ENABLE_FAULT_TOLERANT) + /* Get dont_use_fat value. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + dont_use_fat_old = (UCHAR)file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat; + } +#endif /* FX_ENABLE_EXFAT && FX_ENABLE_FAULT_TOLERANT */ + + /* Search for the additional clusters we need. */ + total_clusters = media_ptr -> fx_media_total_clusters; + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (replace_clusters > 0) + { + + /* Reset consecutive cluster. */ + file_ptr -> fx_file_consecutive_cluster = 1; + + last_cluster = insertion_front; + +#ifdef FX_ENABLE_EXFAT + if ((file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) && + (file_ptr -> fx_file_total_clusters > replace_clusters)) + { + + /* Now we should use FAT. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat &= (CHAR)0xfe; /* Clear bit 0. */ + + /* Build FAT chain. */ + for (i = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster; i < file_ptr -> fx_file_last_physical_cluster; ++i) + { + + status = _fx_utility_FAT_entry_write(media_ptr, i, i + 1); + + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + + /* Write the last cluster FAT entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, i, FX_LAST_CLUSTER_exFAT); + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + } + else +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + last_cluster = file_ptr -> fx_file_last_physical_cluster; + } + + FAT_index = media_ptr -> fx_media_cluster_search_start; + + /* Loop to find the needed clusters. */ + while (clusters) + { + + /* Decrease the cluster count. */ + clusters--; +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Find a free cluster. */ + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + + if (last_cluster) + { + + cluster_state = FX_EXFAT_BITMAP_CLUSTER_OCCUPIED; + FAT_index = last_cluster + 1; + + if (FAT_index < media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) + { + + /* Get the state of the cluster. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, FAT_index, &cluster_state); + + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + + /* Check if we still can do not use FAT. */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_FREE) + { + + /* Clusters are still consecutive. */ + file_ptr -> fx_file_consecutive_cluster++; + } + else + { + + /* Now we should use FAT. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat &= (CHAR)0xfe; /* Clear bit 0. */ + + /* Build FAT chain. */ + for (i = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster; i < last_cluster; ++i) + { + + status = _fx_utility_FAT_entry_write(media_ptr, i, i + 1); + + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + + /* Write the last cluster FAT entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, FX_LAST_CLUSTER_exFAT); + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* Find free cluster from exFAT media. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, + media_ptr -> fx_media_cluster_search_start, + &FAT_index); + } + } + else + { + + /* Find the first cluster for file. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, + media_ptr -> fx_media_cluster_search_start, + &FAT_index); + } + } + else + { + + /* Find free cluster from exFAT media. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, + media_ptr -> fx_media_cluster_search_start, + &FAT_index); + } + + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Loop to find the first available cluster. */ + do + { + + /* Make sure we stop looking after one pass through the FAT table. */ + if (!total_clusters) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Something is wrong with the media - the desired clusters were + not found in the FAT table. */ + return(FX_NO_MORE_SPACE); + } + + /* Read FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, FAT_index, &FAT_value); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* Decrement the total cluster count. */ + total_clusters--; + + /* Determine if the FAT entry is free. */ + if (FAT_value == FX_FREE_CLUSTER) + { + + /* Move cluster search pointer forward. */ + media_ptr -> fx_media_cluster_search_start = FAT_index + 1; + + /* Determine if this needs to be wrapped. */ + if (media_ptr -> fx_media_cluster_search_start >= (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Wrap the search to the beginning FAT entry. */ + media_ptr -> fx_media_cluster_search_start = FX_FAT_ENTRY_START; + } + + /* Break this loop. */ + break; + } + else + { + + /* FAT entry is not free... Advance the FAT index. */ + FAT_index++; + + /* Determine if we need to wrap the FAT index around. */ + if (FAT_index >= (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Wrap the search to the beginning FAT entry. */ + FAT_index = FX_FAT_ENTRY_START; + } + } + } while (FX_TRUE); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if we have found the first new cluster yet. */ + if (first_new_cluster == 0) + { + + /* Remember the first new cluster. */ + first_new_cluster = FAT_index; + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Set the undo log now. */ + if (copy_head_cluster == 0) + { + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, dont_use_fat_old, file_ptr -> fx_file_current_physical_cluster, + first_new_cluster, media_ptr -> fx_media_fat_last, media_ptr -> fx_media_fat_last); + } +#ifdef FX_ENABLE_EXFAT + else if (dont_use_fat_old && (insertion_back == media_ptr -> fx_media_fat_last)) + { + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, dont_use_fat_old, insertion_front, first_new_cluster, + copy_head_cluster, file_ptr -> fx_file_last_physical_cluster + 1); + } +#endif /* FX_ENABLE_EXFAT */ + else + { + + status = _fx_fault_tolerant_set_FAT_chain(media_ptr, dont_use_fat_old, insertion_front, first_new_cluster, + copy_head_cluster, insertion_back); + } + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + + /* Make a quick check to see if an empty, cluster-less file + is being written to for the first time. */ + if (last_cluster) + { + + /* Check for the file's cluster. We won't perform this link until the + entire FAT chain is built. */ + if (last_cluster != file_ptr -> fx_file_last_physical_cluster) + { +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) +#ifdef FX_ENABLE_FAULT_TOLERANT + || (media_ptr -> fx_media_fault_tolerant_enabled == FX_TRUE) +#endif /* FX_ENABLE_FAULT_TOLERANT */ + ) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Normal condition - link the last cluster with the new + found cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, FAT_index); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Check for a bad FAT write status. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* Determine if we are adding a sector after a write filled the previously + allocated cluster exactly. */ + if ((file_ptr -> fx_file_current_relative_sector >= + (media_ptr -> fx_media_sectors_per_cluster - 1)) && + (file_ptr -> fx_file_current_logical_offset >= + media_ptr -> fx_media_bytes_per_sector)) + { + + /* Yes, we need to adjust all of the pertinent file parameters for + writing into this newly allocated cluster. */ + file_ptr -> fx_file_current_physical_cluster = FAT_index; + file_ptr -> fx_file_current_relative_cluster++; + file_ptr -> fx_file_current_relative_sector = 0; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(FAT_index - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + file_ptr -> fx_file_current_logical_offset = 0; + } + } + else + { + + /* This is the first cluster allocated for the file. Just + remember it as being the first and setup the other file + pointers accordingly. */ + file_ptr -> fx_file_first_physical_cluster = FAT_index; + file_ptr -> fx_file_current_physical_cluster = FAT_index; + file_ptr -> fx_file_current_relative_cluster = 0; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(FAT_index - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); +#ifdef FX_ENABLE_FAULT_TOLERANT + if (file_ptr -> fx_file_last_physical_cluster == 0) +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + file_ptr -> fx_file_current_logical_offset = 0; + file_ptr -> fx_file_current_file_offset = 0; + } + + /* Also remember this as the first cluster in the directory + entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster = FAT_index; + } +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Update Bitmap */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, FAT_index, FX_EXFAT_BITMAP_CLUSTER_OCCUPIED); + + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* Move cluster search pointer forward. */ + media_ptr -> fx_media_cluster_search_start = FAT_index + 1; + + /* Determine if this needs to be wrapped. */ + if (media_ptr -> fx_media_cluster_search_start >= media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) + { + + /* Wrap the search to the beginning FAT entry. */ + media_ptr -> fx_media_cluster_search_start = FX_FAT_ENTRY_START; + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* Otherwise, remember the new FAT index as the last. */ + last_cluster = FAT_index; + + /* Move to the next FAT entry. */ + FAT_index = media_ptr -> fx_media_cluster_search_start; + } +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) +#ifdef FX_ENABLE_FAULT_TOLERANT + || (media_ptr -> fx_media_fault_tolerant_enabled == FX_TRUE) +#endif /* FX_ENABLE_FAULT_TOLERANT */ + ) + { +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Link the last cluster back to original FAT. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, insertion_back); + } + else +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + + /* Place an end-of-file marker on the last cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, media_ptr -> fx_media_fat_last); + } + + /* Check for a bad FAT write status. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if the file already had clusters. */ + if (file_ptr -> fx_file_last_physical_cluster) + { +#ifdef FX_ENABLE_EXFAT + if (!(file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1)) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Now, link the file's old last cluster to the first cluster of the new chain. */ +#ifdef FX_ENABLE_FAULT_TOLERANT + if (insertion_front) + { + status = _fx_utility_FAT_entry_write(media_ptr, insertion_front, first_new_cluster); + } + else if ((media_ptr -> fx_media_fault_tolerant_enabled == FX_FALSE) || + ((replace_clusters == 0) && (first_new_cluster))) + { + status = _fx_utility_FAT_entry_write(media_ptr, file_ptr -> fx_file_last_physical_cluster, first_new_cluster); + } +#else + status = _fx_utility_FAT_entry_write(media_ptr, file_ptr -> fx_file_last_physical_cluster, first_new_cluster); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for a bad FAT write status. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + +#ifdef FX_FAULT_TOLERANT + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Flush exFAT bitmap. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + + /* Ensure the new FAT chain is properly written to the media. */ + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); +#endif + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Clear undo phase. */ + media_ptr -> fx_media_fault_tolerant_state &= (UCHAR)(~FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN & 0xff); + + /* Update the last cluster? */ + if (insertion_back == media_ptr -> fx_media_fat_last) + { + + /* Yes. Update the file control block with the last physical cluster. */ + file_ptr -> fx_file_last_physical_cluster = last_cluster; + } + } + else +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + + /* Update the file control block with the last physical cluster. */ + file_ptr -> fx_file_last_physical_cluster = last_cluster; + } + } + + /* Check for a need to increment to the next sector within a previously + allocated cluster. */ + if (file_ptr -> fx_file_current_logical_offset >= + media_ptr -> fx_media_bytes_per_sector) + { + + /* Update the sector specific file parameters to start at the + next logical sector. */ + file_ptr -> fx_file_current_logical_sector++; + file_ptr -> fx_file_current_relative_sector++; + file_ptr -> fx_file_current_logical_offset = 0; + } + + /* At this point there is enough room to perform the file write operation. */ + + /* Setup local buffer pointer. */ + source_ptr = (UCHAR *)buffer_ptr; + + /* Setup the remaining number of bytes to write. */ + bytes_remaining = size; + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (replace_clusters > 0) + { + + /* Force update current cluster and sector. */ + file_ptr -> fx_file_current_physical_cluster = first_new_cluster; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(first_new_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + file_ptr -> fx_file_current_relative_sector; + + /* Copy sectors in replaced cluster but not overwritten at the front. */ + for (i = 0; i < file_ptr -> fx_file_current_relative_sector; i++) + { + status = _fx_utility_logical_sector_read(media_ptr, + ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)(copy_head_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + i, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Write back the current logical sector. */ + status = _fx_utility_logical_sector_write(media_ptr, + ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)(file_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + i, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Loop to write all of the bytes. */ + while (bytes_remaining) + { + + /* Determine if a beginning or ending partial write is required. */ + if ((file_ptr -> fx_file_current_logical_offset) || + (bytes_remaining < media_ptr -> fx_media_bytes_per_sector)) + { + + /* A partial sector write is required. */ + + /* Read the current logical sector. */ +#ifdef FX_ENABLE_FAULT_TOLERANT + if (replace_clusters > 0) + { + if (file_ptr -> fx_file_current_physical_cluster == first_new_cluster) + { + + /* It's at beginning. */ + status = _fx_utility_logical_sector_read(media_ptr, + ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)(copy_head_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + file_ptr -> fx_file_current_relative_sector, + media_ptr -> fx_media_memory_buffer, (ULONG)1, FX_DATA_SECTOR); + } + else if (data_append == FX_FALSE) + { + + /* It's at ending. */ + status = _fx_utility_logical_sector_read(media_ptr, + ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)(copy_tail_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + file_ptr -> fx_file_current_relative_sector, + media_ptr -> fx_media_memory_buffer, (ULONG)1, FX_DATA_SECTOR); + } + else + { + + /* It's at ending. */ + status = _fx_utility_logical_sector_read(media_ptr, + file_ptr -> fx_file_current_logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + } + } + else +#endif /* FX_ENABLE_FAULT_TOLERANT */ + { + status = _fx_utility_logical_sector_read(media_ptr, + file_ptr -> fx_file_current_logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + } + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Copy the appropriate number of bytes into the destination buffer. */ + copy_bytes = media_ptr -> fx_media_bytes_per_sector - + file_ptr -> fx_file_current_logical_offset; + + /* Check to see if only a portion of the sector needs to be + copied. */ + if (copy_bytes > bytes_remaining) + { + + /* Adjust the number of bytes to copy. */ + copy_bytes = (ULONG)bytes_remaining; + } + + /* Actually perform the memory copy. */ + _fx_utility_memory_copy(source_ptr, ((UCHAR *)media_ptr -> fx_media_memory_buffer) + /* Use case of memcpy is verified. */ + file_ptr -> fx_file_current_logical_offset, + copy_bytes); + + /* Write back the current logical sector. */ + status = _fx_utility_logical_sector_write(media_ptr, file_ptr -> fx_file_current_logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + + /* Increment the logical sector byte offset. */ + file_ptr -> fx_file_current_logical_offset = + file_ptr -> fx_file_current_logical_offset + copy_bytes; + + /* Adjust the remaining bytes to read. */ + bytes_remaining = bytes_remaining - copy_bytes; + + /* Adjust the pointer to the source buffer. */ + source_ptr = source_ptr + copy_bytes; + } + else + { + + /* Attempt to write multiple sectors directly to the media. */ + + /* Calculate the number of whole sectors to write. */ + sectors = (UINT)(bytes_remaining / media_ptr -> fx_media_bytes_per_sector); + + next_cluster = cluster = file_ptr -> fx_file_current_physical_cluster; + + for (i = (media_ptr -> fx_media_sectors_per_cluster - + file_ptr -> fx_file_current_relative_sector); i < sectors; i += media_ptr -> fx_media_sectors_per_cluster) + { +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + cluster++; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Determine if an error is present. */ + if ((status != FX_SUCCESS) || (next_cluster < FX_FAT_ENTRY_START) || + (next_cluster > media_ptr -> fx_media_fat_reserved)) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Send error message back to caller. */ + if (status != FX_SUCCESS) + { + return(status); + } + else + { + return(FX_FILE_CORRUPT); + } + } + + if (next_cluster != cluster + 1) + { + break; + } + else + { + cluster = next_cluster; + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + + if (i < sectors) + { + sectors = i; + } + + /* Perform the data write directly from the user's buffer of + the appropriate number of sectors. */ + status = _fx_utility_logical_sector_write(media_ptr, file_ptr -> fx_file_current_logical_sector, + source_ptr, (ULONG) sectors, FX_DATA_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Now adjust the various file pointers. */ + + /* Increment the current logical sector. Subtract one from + the sector count because we are going to use the logical + offset to do additional sector/cluster arithmetic below. */ + file_ptr -> fx_file_current_logical_sector = + file_ptr -> fx_file_current_logical_sector + + (sectors - 1); + + /* Move the relative cluster and sector as well. */ + file_ptr -> fx_file_current_relative_cluster = file_ptr -> fx_file_current_relative_cluster + + (file_ptr -> fx_file_current_relative_sector + (sectors - 1)) / + media_ptr -> fx_media_sectors_per_cluster; + + file_ptr -> fx_file_current_relative_sector = + (file_ptr -> fx_file_current_relative_sector + (sectors - 1)) % + media_ptr -> fx_media_sectors_per_cluster; + + /* Increment the logical sector byte offset. */ + file_ptr -> fx_file_current_logical_offset = + media_ptr -> fx_media_bytes_per_sector; + + file_ptr -> fx_file_current_physical_cluster = cluster; + + /* Adjust the remaining bytes. */ + bytes_remaining = bytes_remaining - + (((ULONG)media_ptr -> fx_media_bytes_per_sector) * sectors); + + /* Adjust the pointer to the source buffer. */ + source_ptr = source_ptr + + (((ULONG)media_ptr -> fx_media_bytes_per_sector) * sectors); + } + + /* At this point, we have either written a partial sector or have successfully + written one or more whole sectors. Determine if we are at the end of + the current logical sector. */ + if (file_ptr -> fx_file_current_logical_offset >= + media_ptr -> fx_media_bytes_per_sector) + { + + /* Determine if we are at the exact physical end of the file. */ + if ((bytes_remaining == 0) && + ((file_ptr -> fx_file_current_file_offset + size) >= + file_ptr -> fx_file_current_available_size)) + { + + /* Skip the following file parameter adjustments. The next write will + detect the logical offset out of the range of the sector and reset + all of the pertinent information. */ + break; + } + + /* We need to move to the next logical sector, but first + determine if the next logical sector is within the same + cluster. */ + + /* Increment the current relative sector in the cluster. */ + file_ptr -> fx_file_current_relative_sector++; + + /* Determine if this is in a new cluster. */ + if (file_ptr -> fx_file_current_relative_sector >= + media_ptr -> fx_media_sectors_per_cluster) + { + + /* Yes, we need to move to the next cluster. */ +#ifdef FX_ENABLE_EXFAT + if (file_ptr -> fx_file_dir_entry.fx_dir_entry_dont_use_fat & 1) + { + + next_cluster = file_ptr -> fx_file_current_physical_cluster + 1; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Read the FAT entry of the current cluster to find + the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, + file_ptr -> fx_file_current_physical_cluster, &next_cluster); + + /* Determine if an error is present. */ + if ((status != FX_SUCCESS) || (next_cluster < FX_FAT_ENTRY_START) || + (next_cluster > media_ptr -> fx_media_fat_reserved)) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Send error message back to caller. */ + if (status != FX_SUCCESS) + { + return(status); + } + else + { + return(FX_FILE_CORRUPT); + } + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Otherwise, we have a new cluster. Save it in the file + control block and calculate a new logical sector value. */ + file_ptr -> fx_file_current_physical_cluster = next_cluster; + file_ptr -> fx_file_current_relative_cluster++; + file_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + ((((ULONG64)next_cluster) - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + file_ptr -> fx_file_current_relative_sector = 0; + } + else + { + + /* Still within the same cluster so just increment the + logical sector. */ + file_ptr -> fx_file_current_logical_sector++; + } + + /* In either case, we are now positioned at a new sector so + clear the logical sector offset. */ + file_ptr -> fx_file_current_logical_offset = 0; + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (((replace_clusters > 0) && (data_append == FX_FALSE)) && + (file_ptr -> fx_file_current_logical_offset || file_ptr -> fx_file_current_relative_sector)) + { + + /* Copy sectors in replaced cluster but not overwritten at the end. */ + if (file_ptr -> fx_file_current_logical_offset == 0) + { + i = file_ptr -> fx_file_current_relative_sector; + } + else + { + i = file_ptr -> fx_file_current_relative_sector + 1; + } + for (; i < media_ptr -> fx_media_sectors_per_cluster; i++) + { + status = _fx_utility_logical_sector_read(media_ptr, + ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)(copy_tail_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + i, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Write back the current logical sector. */ + status = _fx_utility_logical_sector_write(media_ptr, + ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)(file_ptr -> fx_file_current_physical_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + i, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check for good completion status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Adjust the current file offset accordingly. */ + file_ptr -> fx_file_current_file_offset = + file_ptr -> fx_file_current_file_offset + size; + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = + file_ptr -> fx_file_current_file_size; + + /* Determine if this write was done past the previous file size. */ + if (file_ptr -> fx_file_current_file_offset > + file_ptr -> fx_file_current_file_size) + { + + /* Yes, we have written past the previous end of the file. Update + the file size. */ + file_ptr -> fx_file_current_file_size = file_ptr -> fx_file_current_file_offset; + +#ifndef FX_DONT_UPDATE_OPEN_FILES + + /* Search the opened files list to see if the same file is opened for reading. */ + open_count = media_ptr -> fx_media_opened_file_count; + search_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Is this file the same file opened for reading? */ + if ((search_ptr != file_ptr) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector == + file_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector) && + (search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset == + file_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset)) + { + + /* Yes, the same file is opened for reading. */ + + /* Setup the new size. */ + search_ptr -> fx_file_current_file_size = file_ptr -> fx_file_current_file_offset; + + /* Setup the new directory entry. */ + search_ptr -> fx_file_dir_entry.fx_dir_entry_cluster = file_ptr -> fx_file_dir_entry.fx_dir_entry_cluster; + search_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size; + search_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector = file_ptr -> fx_file_dir_entry.fx_dir_entry_log_sector; + search_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset = file_ptr -> fx_file_dir_entry.fx_dir_entry_byte_offset; + + /* Setup the last cluster. This really isn't used during reading, but it is nice to keep things + consistent. */ + search_ptr -> fx_file_last_physical_cluster = file_ptr -> fx_file_last_physical_cluster; + + /* Update the available clusters as well. */ + search_ptr -> fx_file_current_available_size = file_ptr -> fx_file_current_available_size; + + /* Determine if an empty file was previously opened. */ + if (search_ptr -> fx_file_total_clusters == 0) + { + + /* Setup initial parameters. */ + search_ptr -> fx_file_total_clusters = file_ptr -> fx_file_total_clusters; + search_ptr -> fx_file_current_physical_cluster = file_ptr -> fx_file_first_physical_cluster; + search_ptr -> fx_file_current_relative_cluster = 0; + search_ptr -> fx_file_current_logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG64)(file_ptr -> fx_file_first_physical_cluster - FX_FAT_ENTRY_START)) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + search_ptr -> fx_file_current_relative_sector = 0; + search_ptr -> fx_file_current_logical_offset = 0; + search_ptr -> fx_file_current_file_offset = 0; + } + } + + /* Adjust the pointer and decrement the search count. */ + search_ptr = search_ptr -> fx_file_opened_next; + open_count--; + } +#endif + } + + /* Finally, mark this file as modified. */ + file_ptr -> fx_file_modified = FX_TRUE; + +#ifdef FX_FAULT_TOLERANT_DATA + + /* Ensure that all file data is flushed out. */ + + /* Flush the internal logical sector cache. */ + _fx_utility_logical_sector_flush(media_ptr, 1, media_ptr -> fx_media_total_sectors, FX_FALSE); + + /* Lockout interrupts for time/date access. */ + FX_DISABLE_INTS + + /* Set the new time and date. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_time = _fx_system_time; + file_ptr -> fx_file_dir_entry.fx_dir_entry_date = _fx_system_date; + + /* Restore interrupts. */ + FX_RESTORE_INTS + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = file_ptr -> fx_file_current_file_size; + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write( + media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Error writing the directory. */ + return(status); + } +#endif + + /* Update the trace event with the bytes written. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_FILE_WRITE, 0, 0, 0, size) + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); + + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* Update maximum size used if necessary. */ + if (file_ptr -> fx_file_current_file_offset > file_ptr -> fx_file_maximum_size_used) + { + file_ptr -> fx_file_maximum_size_used = file_ptr -> fx_file_current_file_offset; + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Invoke file write callback. */ + if (file_ptr -> fx_file_write_notify) + { + file_ptr -> fx_file_write_notify(file_ptr); + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Return a successful status to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_file_write_notify_set.c b/src/Middlewares/ST/filex/common/src/fx_file_write_notify_set.c new file mode 100644 index 00000000..0e83cd02 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_file_write_notify_set.c @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_file_write_notify_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the notify function called whenever file is */ +/* is written to. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* file_write_notify Notify function called when */ +/* file is written to */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_file_write_notify_set(FX_FILE *file_ptr, VOID (*file_write_notify)(FX_FILE *file)) +{ + + /* Set the notify function. */ + file_ptr -> fx_file_write_notify = file_write_notify; + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_abort.c b/src/Middlewares/ST/filex/common/src/fx_media_abort.c new file mode 100644 index 00000000..554f36b6 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_abort.c @@ -0,0 +1,189 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" +#include "fx_file.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_abort PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function marks all open files for the specified media as */ +/* aborted and then removes the media control block from the open */ +/* media list and marks it as aborted as well. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* tx_mutex_delete Delete the mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_abort(FX_MEDIA *media_ptr) +{ + +FX_INT_SAVE_AREA +ULONG open_count; +FX_FILE *file_ptr; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_aborts++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_ABORT, media_ptr, 0, 0, 0, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Loop through the media's open files. */ + open_count = media_ptr -> fx_media_opened_file_count; + file_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Mark the file as aborted. */ + file_ptr -> fx_file_id = FX_FILE_ABORTED_ID; + + /* Adjust the pointer and decrement the file opened count. */ + file_ptr = file_ptr -> fx_file_opened_next; + open_count--; + } + + /* Build the "abort" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_ABORT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_ABORT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the abort request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Now remove this media from the open list. */ + + /* Lockout interrupts for media removal. */ + FX_DISABLE_INTS + + /* See if the media is the only one on the media opened list. */ + if (_fx_system_media_opened_count == ((ULONG) 1)) + { + + /* Only opened media, just set the opened list to NULL. */ + _fx_system_media_opened_ptr = FX_NULL; + } + else + { + + /* Otherwise, not the only opened media, link-up the neighbors. */ + (media_ptr -> fx_media_opened_next) -> fx_media_opened_previous = + media_ptr -> fx_media_opened_previous; + (media_ptr -> fx_media_opened_previous) -> fx_media_opened_next = + media_ptr -> fx_media_opened_next; + + /* See if we have to update the opened list head pointer. */ + if (_fx_system_media_opened_ptr == media_ptr) + { + + /* Yes, move the head pointer to the next opened media. */ + _fx_system_media_opened_ptr = media_ptr -> fx_media_opened_next; + } + } + + /* Decrement the opened media counter. */ + _fx_system_media_opened_count--; + + /* Finally, Indicate that this media is aborted. */ + media_ptr -> fx_media_id = FX_MEDIA_ABORTED_ID; + + /* Restore interrupt posture. */ + FX_RESTORE_INTS + + /* Delete the media protection structure if FX_SINGLE_THREAD is not + defined. */ +#ifndef FX_SINGLE_THREAD + +#ifndef FX_DONT_CREATE_MUTEX + + /* Note that the protection is never released. The mutex delete + service will handle all threads waiting access to this media + control block. */ + tx_mutex_delete(& (media_ptr -> fx_media_protect)); +#endif +#endif + +#ifdef FX_DONT_CREATE_MUTEX + + /* Release media protection. */ + FX_UNPROTECT +#endif + + /* Return status to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c b/src/Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c new file mode 100644 index 00000000..95ea27bc --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_boot_info_extract.c @@ -0,0 +1,331 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_boot_info_extract PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function extracts and validates the information from the boot */ +/* record found in the memory buffer. If the boot record is invalid, */ +/* an FX_MEDIA_INVALID status is returned to the caller. */ +/* */ +/* The FAT boot sector (512 bytes) that is operated on by this */ +/* function must look like the following: */ +/* */ +/* Byte Offset Meaning Size */ +/* */ +/* 0x000 Jump Instructions 3 */ +/* 0x003 OEM Name 8 */ +/* 0x00B *Bytes per Sector 2 */ +/* 0x00D *Sectors per Cluster 1 */ +/* 0x00E *Reserved Sectors 2 */ +/* 0x010 *Number of FATs 1 */ +/* 0x011 *Max Root Dir Entries 2 */ +/* 0x013 *Number of Sectors 2 */ +/* 0x015 Media Type 1 */ +/* 0x016 *Sectors per FAT 2 */ +/* 0x018 *Sectors per Track 2 */ +/* 0x01A *Number of Heads 2 */ +/* 0x01C *Hidden Sectors 4 */ +/* 0x020 *Huge Sectors 4 */ +/* 0x024 Drive Number 1 */ +/* 0x025 Reserved 1 */ +/* 0x026 Boot Signature 1 */ +/* 0x027 Volume ID 4 */ +/* 0x02B Volume Label 11 */ +/* 0x036 File System Type 8 */ +/* ... ... ... */ +/* 0x1FE **Signature (0x55aa) 2 */ +/* */ +/* * Denotes which elements of the boot record */ +/* FileX uses. */ +/* */ +/* **Denotes the element is checked by the I/O */ +/* driver. This eliminates the need for a minimum */ +/* 512-byte buffer for FileX. */ +/* */ +/* Note: All values above are in little endian format, i.e. the LSB is */ +/* in the lowest address. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_read Read a UINT from buffer */ +/* _fx_utility_32_unsigned_read Read a ULONG from buffer */ +/* _fx_utility_64_unsigned_read Read a ULONG64 from memory */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_media_open Media open function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), added */ +/* check for bimap cache size, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_media_boot_info_extract(FX_MEDIA *media_ptr) +{ + +UCHAR *boot_sector; + + + /* Move the buffer pointer into a local copy. */ + boot_sector = media_ptr -> fx_media_driver_buffer; + + /* Extract the number of bytes per sector. */ + media_ptr -> fx_media_bytes_per_sector = _fx_utility_16_unsigned_read(&boot_sector[FX_BYTES_SECTOR]); + if (media_ptr -> fx_media_bytes_per_sector == 0) +#ifdef FX_ENABLE_EXFAT + { + /* Treat as exFAT volume. */ + /* Extract the number of bytes per sector. */ + media_ptr -> fx_media_exfat_bytes_per_sector_shift = boot_sector[FX_EF_BYTE_PER_SECTOR_SHIFT]; + + /* exFAT requires minimal value 9 (512 bytes) and maximum value 12(4096 bytes) for bytes_per_sector_shift */ + if((media_ptr -> fx_media_exfat_bytes_per_sector_shift < 9) || (media_ptr -> fx_media_exfat_bytes_per_sector_shift > 12)) + { + return(FX_MEDIA_INVALID); + } + + media_ptr -> fx_media_bytes_per_sector = (UINT)(1 << media_ptr -> fx_media_exfat_bytes_per_sector_shift); + + /* Validate bytes per sector value: no more than bitmap cache size */ + if (media_ptr -> fx_media_bytes_per_sector > sizeof(media_ptr -> fx_media_exfat_bitmap_cache)) + { + return(FX_NOT_ENOUGH_MEMORY); + } + + media_ptr -> fx_media_total_sectors = _fx_utility_64_unsigned_read(&boot_sector[FX_EF_VOLUME_LENGTH]); + if (media_ptr -> fx_media_total_sectors == 0) + { + return(FX_MEDIA_INVALID); + } + + media_ptr -> fx_media_reserved_sectors = _fx_utility_32_unsigned_read(&boot_sector[FX_EF_FAT_OFFSET]); + if (media_ptr -> fx_media_reserved_sectors == 0) + { + return(FX_MEDIA_INVALID); + } + + media_ptr -> fx_media_sectors_per_FAT = _fx_utility_32_unsigned_read(&boot_sector[FX_EF_FAT_LENGTH]); + if (media_ptr -> fx_media_sectors_per_FAT == 0) + { + return(FX_MEDIA_INVALID); + } + + media_ptr -> fx_media_data_sector_start = _fx_utility_32_unsigned_read(&boot_sector[FX_EF_CLUSTER_HEAP_OFFSET]); + if (media_ptr -> fx_media_data_sector_start == 0) + { + return(FX_MEDIA_INVALID); + } + + media_ptr -> fx_media_total_clusters = _fx_utility_32_unsigned_read(&boot_sector[FX_EF_CLUSTER_COUNT]); + if (media_ptr -> fx_media_total_clusters == 0) + { + return(FX_MEDIA_INVALID); + } + + media_ptr -> fx_media_exfat_sector_per_clusters_shift = boot_sector[FX_EF_SECTOR_PER_CLUSTER_SHIFT]; + if (media_ptr -> fx_media_exfat_sector_per_clusters_shift > 25 - media_ptr -> fx_media_exfat_bytes_per_sector_shift) + { + return(FX_MEDIA_INVALID); + } + media_ptr -> fx_media_sectors_per_cluster = (UINT)(1 << media_ptr -> fx_media_exfat_sector_per_clusters_shift); + + media_ptr -> fx_media_number_of_FATs = boot_sector[FX_EF_NUMBER_OF_FATS]; + if (media_ptr -> fx_media_number_of_FATs == 0) + { + return(FX_MEDIA_INVALID); + } + + media_ptr -> fx_media_root_cluster_32 = _fx_utility_32_unsigned_read(&boot_sector[FX_EF_FIRST_CLUSTER_OF_ROOT_DIR]); + /* Root cluster starts from at least FX_FAT_ENTRY_START (2), or higher. */ + if (media_ptr -> fx_media_root_cluster_32 < FX_FAT_ENTRY_START) + { + return(FX_MEDIA_INVALID); + } + + /* Overflow check. */ + if (((ULONG64)media_ptr -> fx_media_data_sector_start + + (ULONG64)(media_ptr -> fx_media_root_cluster_32 - FX_FAT_ENTRY_START) * + media_ptr -> fx_media_sectors_per_cluster) > 0xFFFFFFFF) + { + + /* Return the invalid media error status. */ + return(FX_MEDIA_INVALID); + } + + /* Calculate logical number of root dir sector. */ + media_ptr -> fx_media_root_sector_start = media_ptr -> fx_media_data_sector_start + + (media_ptr -> fx_media_root_cluster_32 - FX_FAT_ENTRY_START) * + media_ptr -> fx_media_sectors_per_cluster; + + media_ptr -> fx_media_exfat_volume_serial_number = _fx_utility_32_unsigned_read(&boot_sector[FX_EF_VOLUME_SERIAL_NUMBER]); + + media_ptr -> fx_media_exfat_file_system_revision = _fx_utility_16_unsigned_read(&boot_sector[FX_EF_FILE_SYSTEM_REVISION]); + + media_ptr -> fx_media_exfat_volume_flag = _fx_utility_16_unsigned_read(&boot_sector[FX_EF_VOLUME_FLAGS]); + + media_ptr -> fx_media_number_of_FATs = boot_sector[FX_EF_NUMBER_OF_FATS]; + + if (0 == media_ptr -> fx_media_number_of_FATs) + { + return(FX_MEDIA_INVALID); + } + + /* Extract the number of hidden sectors. */ +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_hidden_sectors = _fx_utility_64_unsigned_read(&boot_sector[FX_EF_PARTITION_OFFSET]); +#else + media_ptr -> fx_media_hidden_sectors = _fx_utility_32_unsigned_read(&boot_sector[FX_EF_PARTITION_OFFSET]); +#endif + + media_ptr -> fx_media_exfat_drive_select = boot_sector[FX_EF_DRIVE_SELECT]; + media_ptr -> fx_media_exfat_percent_in_use = boot_sector[FX_EF_PERCENT_IN_USE]; + + media_ptr -> fx_media_12_bit_FAT = FX_FALSE; + media_ptr -> fx_media_32_bit_FAT = FX_FALSE; + + /* Legacy code support: + We will use fx_media_FAT_type for determine FAT type instead of + fx_media_12_bit_FAT and fx_media_32_bit_FAT. */ + media_ptr -> fx_media_12_bit_FAT = FX_FALSE; + media_ptr -> fx_media_32_bit_FAT = FX_FALSE; + + media_ptr -> fx_media_FAT_type = FX_exFAT; + + return(_fx_utility_exFAT_geometry_check(media_ptr, boot_sector)); + } + else + { +#else + return(FX_MEDIA_INVALID); +#endif /* FX_ENABLE_EXFAT */ + + + /* FAT12/16/32 volume. */ + /* Extract the number of sectors per track. */ + media_ptr -> fx_media_sectors_per_track = _fx_utility_16_unsigned_read(&boot_sector[FX_SECTORS_PER_TRK]); + + /* Extract the number of heads. */ + media_ptr -> fx_media_heads = _fx_utility_16_unsigned_read(&boot_sector[FX_HEADS]); + + /* Extract the total number of sectors. */ + media_ptr -> fx_media_total_sectors = _fx_utility_16_unsigned_read(&boot_sector[FX_SECTORS]); + if (media_ptr -> fx_media_total_sectors == 0) + { + media_ptr -> fx_media_total_sectors = _fx_utility_32_unsigned_read(&boot_sector[FX_HUGE_SECTORS]); + } + + if (media_ptr -> fx_media_total_sectors == 0) + { + return(FX_MEDIA_INVALID); + } + + /* Extract the number of reserved sectors before the first FAT. */ + media_ptr -> fx_media_reserved_sectors = _fx_utility_16_unsigned_read(&boot_sector[FX_RESERVED_SECTORS]); + if (media_ptr -> fx_media_reserved_sectors == 0) + { + return(FX_MEDIA_INVALID); + } + + /* Extract the number of sectors per cluster. */ + media_ptr -> fx_media_sectors_per_cluster = ((UINT)boot_sector[FX_SECTORS_CLUSTER] & 0xFF); + + /* There should always be at least one reserved sector, representing the boot record itself. */ + if (media_ptr -> fx_media_sectors_per_cluster == 0) + { + return(FX_MEDIA_INVALID); + } + + /* Extract the number of sectors per FAT. */ + media_ptr -> fx_media_sectors_per_FAT = _fx_utility_16_unsigned_read(&boot_sector[FX_SECTORS_PER_FAT]); + if (media_ptr -> fx_media_sectors_per_FAT == 0) + { + media_ptr -> fx_media_sectors_per_FAT = _fx_utility_32_unsigned_read(&boot_sector[FX_SECTORS_PER_FAT_32]); + } + + if (media_ptr -> fx_media_sectors_per_FAT == 0) + { + return(FX_MEDIA_INVALID); + } + + /* Extract the number of FATs. */ + media_ptr -> fx_media_number_of_FATs = ((UINT)boot_sector[FX_NUMBER_OF_FATS] & 0xFF); + if (media_ptr -> fx_media_number_of_FATs == 0) + { + return(FX_BOOT_ERROR); + } + + /* Extract the number of hidden sectors. */ +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_hidden_sectors = _fx_utility_64_unsigned_read(&boot_sector[FX_HIDDEN_SECTORS]); +#else + media_ptr -> fx_media_hidden_sectors = _fx_utility_32_unsigned_read(&boot_sector[FX_HIDDEN_SECTORS]); +#endif + /* Extract the number of root directory entries. */ + media_ptr -> fx_media_root_directory_entries = _fx_utility_16_unsigned_read(&boot_sector[FX_ROOT_DIR_ENTRIES]); + + /* Extract root directory starting cluster (32 bit only) and compute start sector */ + media_ptr -> fx_media_root_cluster_32 = _fx_utility_32_unsigned_read(&boot_sector[FX_ROOT_CLUSTER_32]); + +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Return a successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c b/src/Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c new file mode 100644 index 00000000..38712961 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_cache_invalidate.c @@ -0,0 +1,134 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_cache_invalidate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function examines the logical cache, flushing written sectors */ +/* out to the media and invalidating all sectors in the logical cache. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_flush Flush cached FAT entries */ +/* _fx_utility_FAT_map_flush Flush primary FAT changes to */ +/* secondary FAT(s) */ +/* _fx_utility_logical_sector_flush Flush logical sector cache */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_cache_invalidate(FX_MEDIA *media_ptr) +{ + +UINT status; +UINT i; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_flushes++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_CACHE_INVALIDATE, media_ptr, 0, 0, 0, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); + + /* Flush changed sector(s) in the primary FAT to secondary FATs. */ + _fx_utility_FAT_map_flush(media_ptr); + + /* Clear the FAT cache entry array. */ + for (i = 0; i < FX_MAX_FAT_CACHE; i++) + { + + /* Clear entry in the FAT cache. */ + media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_cluster = 0; + media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_value = 0; + } + + /* Clear the secondary FAT update map. */ + for (i = 0; i < FX_FAT_MAP_SIZE; i++) + { + + /* Clear bit map entry for secondary FAT update. */ + media_ptr -> fx_media_fat_secondary_update_map[i] = 0; + } + + /* Call the logical sector flush to invalidate the logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, ((ULONG64) 1), (ULONG64) (media_ptr -> fx_media_total_sectors), FX_TRUE); + + /* Release media protection. */ + FX_UNPROTECT + + /* If we get here, return successful status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_check.c b/src/Middlewares/ST/filex/common/src/fx_media_check.c new file mode 100644 index 00000000..c89cc139 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_check.c @@ -0,0 +1,830 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_media.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + + +/* Define parameters for FileX media check utility. */ + +#ifndef FX_MAX_DIRECTORY_NESTING +#define FX_MAX_DIRECTORY_NESTING 20 +#endif + + +/* Define data structures local to the FileX media check utility. */ + +typedef struct CURRENT_DIRECTORY_ENTRY_STRUCT +{ + ULONG current_directory_entry; + ULONG current_total_entries; + ULONG current_start_cluster; +} CURRENT_DIRECTORY_ENTRY; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_check PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks the specified media for basic structural */ +/* errors, including cross linking, invalid FAT chains, and lost */ +/* clusters. The function also provides the capability to correct */ +/* errors. */ +/* */ +/* The algorithm is to follow all sub-directories immediately and */ +/* check their contents. The maximum depth of sub-directories is */ +/* determined by the constant FX_MAX_DIRECTORY_NESTING. */ +/* By default, this is set at 20. Basically, the FAT chain of every */ +/* file and sub-directory is traversed. If valid, clusters are marked */ +/* in a logical FAT bit map to signal they are already in-use. The */ +/* algorithm should detect any broken or cross linked FAT condition. */ +/* */ +/* As for memory usage, the scratch memory supplied to the media check */ +/* function is used to hold several directory entries, a data */ +/* structure to "stack" the current directory entry position before */ +/* diving into the sub-directory, and finally the logical FAT bit map. */ +/* The basic data structures take from 512-1024 bytes and the logical */ +/* FAT bit map requires as many bits as there are clusters in your */ +/* device. For example, a device with 8000 clusters would require */ +/* 1000 bytes to represent. */ +/* */ +/* On the performance end of things, the traversal is reasonably fast */ +/* and is basically linear with the number of files and their sizes. */ +/* The lost cluster checking at the end of media check is a bit more */ +/* performance comprehensive. It basically checks that each unused */ +/* cluster is actually marked as free. You might decide to bypass this */ +/* step if no other errors are found... or there might be ways to */ +/* optimize the search by reading whole FAT sectors. You probably just */ +/* need to see how it behaves in your system. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to a previously */ +/* opened media */ +/* scratch_memory_ptr Pointer to memory area for */ +/* media check to use (as */ +/* mentioned above) */ +/* scratch_memory_size Size of the scratch memory */ +/* error_correction_option Specifies which - if any - */ +/* errors are corrected by */ +/* the media check function. */ +/* Setting the following bit */ +/* causes that error to be */ +/* corrected: */ +/* */ +/* 0x01 -> Fix FAT Chain Errors*/ +/* 0x02 -> Fix Directory Entry */ +/* Errors */ +/* 0x04 -> Fix Lost Clusters */ +/* */ +/* errors_detected Specifies the destination */ +/* ULONG to place the error */ +/* report from media check. */ +/* This has a similar bit map */ +/* as before: */ +/* */ +/* 0x01 -> FAT Chain Error(s) */ +/* 0x02 -> Directory Entry */ +/* Error(s) */ +/* 0x04 -> Lost Cluster(s) */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS Media check performed its */ +/* operation successfully. */ +/* This does not mean that */ +/* there were no errors. The */ +/* errors_detected variable */ +/* needs to be examined. */ +/* FX_MEDIA_NOT_OPEN The media was not open. */ +/* FX_NOT_ENOUGH_MEMORY The scratch memory was not */ +/* large enough or the nesting */ +/* depth was greater than the */ +/* maximum specified. */ +/* FX_IO_ERROR I/O Error reading/writing to */ +/* the media. */ +/* FX_ERROR_NOT_FIXED Fundamental problem with */ +/* media that couldn't be fixed*/ +/* */ +/* CALLS */ +/* */ +/* _fx_media_cache_invalidate Invalidate the cache */ +/* _fx_media_check_FAT_chain_check Walk the supplied FAT chain */ +/* _fx_media_check_lost_cluster_check Check for lost clusters */ +/* _fx_directory_entry_read Directory entry read */ +/* _fx_directory_entry_write Directory entry write */ +/* _fx_media_flush Flush changes to the media */ +/* _fx_utility_FAT_entry_write Write value to FAT entry */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_check(FX_MEDIA *media_ptr, UCHAR *scratch_memory_ptr, ULONG scratch_memory_size, ULONG error_correction_option, ULONG *errors_detected) +{ + +CURRENT_DIRECTORY_ENTRY *current_directory; +ULONG total_entries, last_cluster, valid_clusters; +ULONG bytes_per_cluster, i, current_errors; +UINT status, long_name_size; +UINT current_directory_index; +UCHAR *logical_fat, *working_ptr; +ALIGN_TYPE address_mask; +FX_DIR_ENTRY *temp_dir_ptr, *source_dir_ptr, *dir_entry_ptr; + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + +#ifdef FX_ENABLE_EXFAT + current_errors = 0; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_CHECK, media_ptr, scratch_memory_ptr, scratch_memory_size, 0, FX_TRACE_MEDIA_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Determine if there are any opened files. */ + if (media_ptr -> fx_media_opened_file_count) + { + + /* There are opened files... this is an error! */ + + /* Release protection. */ + FX_UNPROTECT + + /* Return an error. */ + return(FX_ACCESS_ERROR); + } + + /* Invalidate the cache. */ + _fx_media_cache_invalidate(media_ptr); + + /* Initialize the reported error flag. */ + *errors_detected = 0; + + /* Calculate the long name size, rounded up to something that is evenly divisible by 4. */ + long_name_size = (((FX_MAX_LONG_NAME_LEN + 3) >> 2) << 2); + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = media_ptr -> fx_media_sectors_per_cluster * media_ptr -> fx_media_bytes_per_sector; + + /* Setup address mask. */ + address_mask = sizeof(ULONG) - 1; + address_mask = ~address_mask; + + /* Setup working pointer. */ + working_ptr = scratch_memory_ptr + (sizeof(ULONG) - 1); + working_ptr = (UCHAR *)(((ALIGN_TYPE)working_ptr) & address_mask); + + /* Memory is set aside for two FX_DIR_ENTRY structures */ + dir_entry_ptr = (FX_DIR_ENTRY *)working_ptr; + + /* Adjust the scratch memory pointer forward. */ + working_ptr = &working_ptr[sizeof(FX_DIR_ENTRY)]; + + /* Setup the name buffer for the first directory entry. */ + dir_entry_ptr -> fx_dir_entry_name = (CHAR *)working_ptr; + + /* Adjust the scratch memory pointer forward. */ + working_ptr = working_ptr + long_name_size + (sizeof(ULONG) - 1); + working_ptr = (UCHAR *)(((ALIGN_TYPE)working_ptr) & address_mask); + + /* Setup the source directory entry. */ + source_dir_ptr = (FX_DIR_ENTRY *)working_ptr; + + /* Adjust the scratch memory pointer forward. */ + working_ptr = &working_ptr[sizeof(FX_DIR_ENTRY)]; + + /* Setup the name buffer for the source directory entry. */ + source_dir_ptr -> fx_dir_entry_name = (CHAR *)working_ptr; + + /* Adjust the scratch memory pointer forward. */ + working_ptr = working_ptr + long_name_size + (sizeof(ULONG) - 1); + working_ptr = (UCHAR *)(((ALIGN_TYPE)working_ptr) & address_mask); + + /* Setup the current directory stack memory. */ + current_directory = (CURRENT_DIRECTORY_ENTRY *)working_ptr; + + /* Allocate space for the size of the directory entry stack. This basically + defines the maximum level of sub-directories supported. */ + working_ptr = &working_ptr[(FX_MAX_DIRECTORY_NESTING * sizeof(CURRENT_DIRECTORY_ENTRY))]; + + /* Setup the initial current directory entry. */ + current_directory_index = 0; + + /* Adjust the size to account for the header information. */ + if (scratch_memory_size < (ULONG)((working_ptr - scratch_memory_ptr))) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not enough memory error. */ + return(FX_NOT_ENOUGH_MEMORY); + } + + /* Adjust the scratch memory size. */ + scratch_memory_size = scratch_memory_size - (ULONG)(working_ptr - scratch_memory_ptr); + + /* Memory is set aside for logical FAT - one bit per cluster */ + logical_fat = (UCHAR *)working_ptr; + + /* Determine if there is enough memory. */ + if (scratch_memory_size < ((media_ptr -> fx_media_total_clusters >> 3) + 1)) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not enough memory error. */ + return(FX_NOT_ENOUGH_MEMORY); + } + + /* Initialize the logical FAT table. */ + for (i = 0; i < ((media_ptr -> fx_media_total_clusters >> 3) + 1); i++) + { + /* Clear the logical FAT entry, which actually represents eight clusters. */ + logical_fat[i] = 0; + } + +#ifdef FX_ENABLE_EXFAT + + /* Mark the clusters occupied by Allocation Bitmap table, Up-cast table and the first cluster of root directory. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + ULONG offset = 0; + + for (i = ((media_ptr -> fx_media_root_cluster_32 - FX_FAT_ENTRY_START) >> 3); i; i--) + { + logical_fat[offset++] = 0xff; + } + + for (i = ((media_ptr -> fx_media_root_cluster_32 - FX_FAT_ENTRY_START) & 7); i; i--) + { + logical_fat[offset] = (UCHAR)((logical_fat[offset] << 1) | 0x1); + } + } +#endif /* FX_ENABLE_EXFAT */ + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + ULONG cluster, cluster_number; + + /* Mark the cluster used by fault tolerant as valid. */ + for (cluster = media_ptr -> fx_media_fault_tolerant_start_cluster; + cluster < media_ptr -> fx_media_fault_tolerant_start_cluster + media_ptr -> fx_media_fault_tolerant_clusters; + cluster++) + { + + cluster_number = cluster; + +#ifdef FX_ENABLE_EXFAT + + /* For the index of the first cluster in exFAT is 2, adjust the number of clusters to fit Allocation Bitmap Table. */ + /* We will compare logical_fat with Aollcation Bitmap table later to find out lost clusters. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + cluster_number = cluster - FX_FAT_ENTRY_START; + } +#endif /* FX_ENABLE_EXFAT */ + + logical_fat[cluster_number >> 3] = (UCHAR)(logical_fat[cluster_number >> 3] | (1 << (cluster_number & 7))); + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* If FAT32 is present, determine if the root directory is coherent. */ +#ifdef FX_ENABLE_EXFAT + if ((media_ptr -> fx_media_FAT_type == FX_FAT32) || + (media_ptr -> fx_media_FAT_type == FX_exFAT)) +#else + if (media_ptr -> fx_media_32_bit_FAT) +#endif /* FX_ENABLE_EXFAT */ + { + + /* A 32-bit FAT is present. We need to walk the clusters of the root directory to determine if + it is intact. */ + current_errors = _fx_media_check_FAT_chain_check(media_ptr, media_ptr -> fx_media_root_cluster_32, + &last_cluster, &valid_clusters, logical_fat); + + /* Make them part of the errors reported to the caller. */ + *errors_detected = *errors_detected | current_errors; + + /* Update the trace event with the errors detected. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_MEDIA_CHECK, 0, 0, 0, *errors_detected) + + /* Determine if the I/O error is set. */ + if (current_errors & FX_IO_ERROR) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* File I/O Error. */ + return(FX_IO_ERROR); + } + + /* Check the status. */ + if (*errors_detected) + { + + /* Determine if we can fix the FAT32 root directory error. */ + if ((valid_clusters) && (error_correction_option & FX_FAT_CHAIN_ERROR)) + { + + /* Make the chain end at the last cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, media_ptr -> fx_media_fat_last); + + /* Determine if the write was successful. */ + if (status) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Adjust the total entries in the root directory. */ + media_ptr -> fx_media_root_directory_entries = (valid_clusters * bytes_per_cluster) / FX_DIR_ENTRY_SIZE; + } + else + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return an error. */ + return(FX_ERROR_NOT_FIXED); + } + } + } + + /* Pickup total entries in the root directory. */ + total_entries = media_ptr -> fx_media_root_directory_entries; + + /* Set temp directory pointer to NULL. */ + temp_dir_ptr = FX_NULL; + + /* Put the root directory information in the entry stack */ + current_directory[current_directory_index].current_total_entries = total_entries; + current_directory[current_directory_index].current_start_cluster = media_ptr -> fx_media_fat_last; + current_directory[current_directory_index].current_directory_entry = 0; + + /* Now we shall do the checking in depth first manner. */ + do + { + + /* Pickup the directory index. */ + i = current_directory[current_directory_index].current_directory_entry; + + /* Loop to process remaining directory entries. */ + while (i < current_directory[current_directory_index].current_total_entries) + { + + /* Read a directory entry. */ +#ifdef FX_ENABLE_EXFAT + /* Hash value of the file name is not cared. */ + status = _fx_directory_entry_read_ex(media_ptr, temp_dir_ptr, &i, dir_entry_ptr, 0); +#else + status = _fx_directory_entry_read(media_ptr, temp_dir_ptr, &i, dir_entry_ptr); +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if the read was successful. */ + if (status) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Check for the last entry. */ +#ifdef FX_ENABLE_EXFAT + if (dir_entry_ptr -> fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_END_MARKER) +#else + if (dir_entry_ptr -> fx_dir_entry_name[0] == (CHAR)FX_DIR_ENTRY_DONE) +#endif /* FX_ENABLE_EXFAT */ + { + + /* Last entry in this directory - no need to check further. */ + break; + } + + /* Is the entry free? */ +#ifdef FX_ENABLE_EXFAT + if (dir_entry_ptr -> fx_dir_entry_type != FX_EXFAT_DIR_ENTRY_TYPE_FILE_DIRECTORY) +#else + if ((dir_entry_ptr -> fx_dir_entry_name[0] == (CHAR)FX_DIR_ENTRY_FREE) && (dir_entry_ptr -> fx_dir_entry_short_name[0] == 0)) +#endif /* FX_ENABLE_EXFAT */ + { + + /* A deleted entry */ + i++; + continue; + } + +#ifdef FX_ENABLE_EXFAT + + /* Determine whether FAT chain is used. */ + if (dir_entry_ptr -> fx_dir_entry_dont_use_fat & 1) + { + ULONG64 remaining_size = dir_entry_ptr -> fx_dir_entry_file_size; + ULONG cluster = dir_entry_ptr -> fx_dir_entry_cluster, cluster_number; + + valid_clusters = 0; + + while (remaining_size) + { + if (remaining_size >= bytes_per_cluster) + { + remaining_size -= bytes_per_cluster; + } + else + { + remaining_size = 0; + last_cluster = cluster; + } + + cluster_number = cluster - FX_FAT_ENTRY_START; + + /* Is the current cluster already marked? */ + if ((logical_fat[cluster_number / 8] >> (cluster_number % 8)) & 0x01) + { + current_errors = FX_FILE_SIZE_ERROR; + last_cluster = dir_entry_ptr -> fx_dir_entry_cluster + valid_clusters; + break; + } + + /* Mark the current cluster. */ + logical_fat[cluster_number >> 3] = (UCHAR)(logical_fat[cluster_number >> 3] | (1 << (cluster_number & 7))); + + valid_clusters++; + cluster++; + } + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Look for any cross links or errors in the FAT chain of current directory entry. */ + current_errors = _fx_media_check_FAT_chain_check(media_ptr, dir_entry_ptr -> fx_dir_entry_cluster, + &last_cluster, &valid_clusters, logical_fat); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Make them part of the errors reported to the caller. */ + *errors_detected = *errors_detected | current_errors; + + /* Update the trace event with the errors detected. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_MEDIA_CHECK, 0, 0, 0, *errors_detected) + + /* Determine if the I/O error is set. */ + if (current_errors & FX_IO_ERROR) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* File I/O Error. */ + return(FX_IO_ERROR); + } + + /* Check for errors. */ + if (*errors_detected) + { + + /* Determine if we can fix the FAT chain. */ + if (error_correction_option & FX_FAT_CHAIN_ERROR) + { + + /* Determine if there is a valid cluster to write the EOF to. */ + if (valid_clusters) + { + + /* Write EOF in the last FAT entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, last_cluster, media_ptr -> fx_media_fat_last); + + /* Determine if the write was successful. */ + if (status) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + } + } + } + + /* Determine if we need to update the size of the directory entry. */ + if (dir_entry_ptr -> fx_dir_entry_file_size > (valid_clusters * bytes_per_cluster)) + { + + /* Yes, update the directory entry's size. */ + dir_entry_ptr -> fx_dir_entry_file_size = valid_clusters * bytes_per_cluster; + + /* Determine if the new file size is zero. */ + if (dir_entry_ptr -> fx_dir_entry_file_size == 0) + { + + /* Consider this a directory error. */ + *errors_detected = *errors_detected | FX_DIRECTORY_ERROR; + + /* Update the trace event with the errors detected. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_MEDIA_CHECK, 0, 0, 0, *errors_detected) + + /* Clear the starting cluster number of this directory entry. */ + dir_entry_ptr -> fx_dir_entry_cluster = 0; + + /* If directory fixing is required, delete this directory entry as well. */ + if (error_correction_option & FX_DIRECTORY_ERROR) + { + + /* Mark the entry as deleted. */ + dir_entry_ptr -> fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + dir_entry_ptr -> fx_dir_entry_short_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + } + } + + /* Only update the directory if the FAT chain was actually updated. */ + if (error_correction_option & FX_FAT_CHAIN_ERROR) + { + + /* Update the directory entry. */ + status = _fx_directory_entry_write(media_ptr, dir_entry_ptr); + + /* Determine if the write was successful. */ + if (status) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + } + } + + /* Determine if the entry is a sub-directory. */ + if ((dir_entry_ptr -> fx_dir_entry_attributes & FX_DIRECTORY) + && (valid_clusters == 0)) + { + + /* Consider this a directory error. */ + *errors_detected = *errors_detected | FX_DIRECTORY_ERROR; + + /* Update the trace event with the errors detected. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_MEDIA_CHECK, 0, 0, 0, *errors_detected) + + /* Determine if we can fix the error. */ + if (error_correction_option & FX_DIRECTORY_ERROR) + { + + /* Yes, make the directory entry free. */ + dir_entry_ptr -> fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + dir_entry_ptr -> fx_dir_entry_short_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + + /* Delete the sub-directory entry. */ + status = _fx_directory_entry_write(media_ptr, dir_entry_ptr); + + /* Determine if the write was successful. */ + if (status) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Move to next entry. */ + i++; + continue; + } + } + + /* Determine if the entry is a directory. */ + if (dir_entry_ptr -> fx_dir_entry_attributes & FX_DIRECTORY) + { + + /* Current entry is a directory. The algorithm is designed to follow all + sub-directories immediately, i.e., a depth first search. */ + + /* First, save the next entry position. */ + current_directory[current_directory_index].current_directory_entry = i + 1; + + /* Push the current directory entry on the stack. */ + current_directory_index++; + + /* Check for current directory stack overflow. */ + if (current_directory_index >= FX_MAX_DIRECTORY_NESTING) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Current directory stack overflow. Return error. */ + return(FX_NOT_ENOUGH_MEMORY); + } + + /* Otherwise, setup the new directory entry. */ + current_directory[current_directory_index].current_total_entries = (valid_clusters * bytes_per_cluster) / FX_DIR_ENTRY_SIZE; + current_directory[current_directory_index].current_start_cluster = dir_entry_ptr -> fx_dir_entry_cluster; + current_directory[current_directory_index].current_directory_entry = 2; + + /* Setup new source directory. */ + source_dir_ptr -> fx_dir_entry_cluster = dir_entry_ptr -> fx_dir_entry_cluster; + source_dir_ptr -> fx_dir_entry_file_size = current_directory[current_directory_index].current_total_entries; + source_dir_ptr -> fx_dir_entry_last_search_cluster = 0; + temp_dir_ptr = source_dir_ptr; + + /* Skip the first two entries of sub-directories. */ + i = 2; + +#ifdef FX_ENABLE_EXFAT + + /* For exFAT, there is no dir-entries for ".." and ".". */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + current_directory[current_directory_index].current_directory_entry = 0; + i = 0; + } +#endif /* FX_ENABLE_EXFAT */ + } + else + { + + /* Regular file entry. */ + + /* Check for an invalid file size. */ + if (((valid_clusters * bytes_per_cluster) - dir_entry_ptr -> fx_dir_entry_file_size) > bytes_per_cluster) + { + + /* There are more clusters allocated than needed for the file's size. Indicate that this error + is present. */ + *errors_detected = *errors_detected | FX_FILE_SIZE_ERROR; + + /* Update the trace event with the errors detected. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_MEDIA_CHECK, 0, 0, 0, *errors_detected) + + /* For now, don't shorten the cluster chain. */ + } + + /* Look into the next entry in the current directory. */ + i++; + } + } + + /* Once we get here, we have exhausted the current directory and need to return to the previous + directory. */ + + /* Check for being at the root directory. */ + if (current_directory_index == 0) + { + + /* Yes, we have now exhausted searching the root directory so we are done! */ + break; + } + + /* Backup to the place we left off in the previous directory. */ + current_directory_index--; + + /* Determine if we are now back at the root directory. */ + if (current_directory[current_directory_index].current_start_cluster == media_ptr -> fx_media_fat_last) + { + + /* The search directory should be NULL since it is the root directory. */ + temp_dir_ptr = FX_NULL; + } + else + { + + /* Otherwise, we are returning to a sub-directory. Setup the search directory + appropriately. */ + source_dir_ptr -> fx_dir_entry_cluster = current_directory[current_directory_index].current_start_cluster; + source_dir_ptr -> fx_dir_entry_file_size = current_directory[current_directory_index].current_total_entries; + source_dir_ptr -> fx_dir_entry_last_search_cluster = 0; + temp_dir_ptr = source_dir_ptr; + } + } while (1); + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* If exFAT is in use, compare the logical_fat with Allocation Bitmap Table directly. */ + current_errors = _fx_media_check_exFAT_lost_cluster_check(media_ptr, logical_fat, media_ptr -> fx_media_total_clusters, error_correction_option); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* At this point, all the files and sub-directories have been examined. We now need to check for + lost clusters in the logical FAT. A lost cluster is basically anything that is not reported in + the logical FAT that has a non-zero value in the real FAT. */ + current_errors = _fx_media_check_lost_cluster_check(media_ptr, logical_fat, media_ptr -> fx_media_total_clusters, error_correction_option); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Incorporate the error returned by the lost FAT check. */ + *errors_detected = *errors_detected | current_errors; + + /* Update the trace event with the errors detected. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_MEDIA_CHECK, 0, 0, 0, *errors_detected) + + /* Determine if the I/O error is set. */ + if (current_errors & FX_IO_ERROR) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* File I/O Error. */ + return(FX_IO_ERROR); + } + + /* Determine if there was any error and update was selected. */ + if ((*errors_detected) && (error_correction_option)) + { + + /* Flush any unwritten items to the media. */ + _fx_media_flush(media_ptr); + } + + /* Release media protection. */ + FX_UNPROTECT + + /* At this point, we have completed the diagnostic of the media, return success! */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c b/src/Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c new file mode 100644 index 00000000..3052d085 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_check_FAT_chain_check.c @@ -0,0 +1,171 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_check_FAT_chain_check PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function walks the supplied FAT chain looking for cross links */ +/* (FAT entries already used in another FAT chain) and abnormal FAT */ +/* entries and invalid chain termination. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to a previously */ +/* opened media */ +/* starting_cluster Starting cluster of FAT chain */ +/* last_valid_cluster Last valid cluster of chain */ +/* total_valid_clusters Total number of valid clusters*/ +/* logical_fat Pointer to the logical FAT */ +/* bit map */ +/* */ +/* OUTPUT */ +/* */ +/* error Error code */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_check_media Check media function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _fx_media_check_FAT_chain_check(FX_MEDIA *media_ptr, ULONG starting_cluster, ULONG *last_valid_cluster, ULONG *total_valid_clusters, UCHAR *logical_fat) +{ + +ULONG prev_cluster, cluster, next_clust = 0; +ULONG cluster_number; +ULONG count, error; +UINT status; + + + /* Initialize the error code. */ + error = 0; + + /* Setup at the first cluster. */ + cluster = starting_cluster; + + /* Initialize the previous cluster. */ + prev_cluster = 0; + + /* Initialize the count to 0. */ + count = 0; + + /* Loop to walk through the FAT chain. */ + while ((cluster >= (ULONG)FX_FAT_ENTRY_START) && + (cluster < (FX_FAT_ENTRY_START + media_ptr -> fx_media_total_clusters))) + { + + cluster_number = cluster; + +#ifdef FX_ENABLE_EXFAT + + /* For the index of the first cluster in exFAT is 2, adjust the number of clusters to fit Allocation Bitmap Table. */ + /* We will compare logical_fat with Aollcation Bitmap table later to find out lost clusters. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + cluster_number = cluster - FX_FAT_ENTRY_START; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if this cluster is already in the logical FAT bit map. */ + if (logical_fat[cluster_number >> 3] & (1 << (cluster_number & 7))) + { + + /* Yes, the cluster is already being used by another file or + sub-directory. */ + error = FX_FAT_CHAIN_ERROR; + break; + } + + /* Now read the contents of the cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_clust); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + + /* Yes, the cluster is already being used by another file or + sub-directory. */ + error = FX_IO_ERROR; + break; + } + + /* Determine if the link is circular or the count is greater than the + total clusters. */ + if ((cluster == next_clust) || + (next_clust < (ULONG)FX_FAT_ENTRY_START) || + ((next_clust >= (FX_FAT_ENTRY_START + media_ptr -> fx_media_total_clusters)) && + (next_clust != media_ptr -> fx_media_fat_last))) + { + + error = FX_FAT_CHAIN_ERROR; + break; + } + + /* Everything is good with the chain at this point. Mark it as valid. */ + logical_fat[cluster_number >> 3] = (UCHAR)(logical_fat[cluster_number >> 3] | (1 << (cluster_number & 7))); + + /* Move the cluster variable forward. */ + prev_cluster = cluster; + cluster = next_clust; + + /* Increment the number of valid clusters. */ + count++; + } + + /* Return the last valid cluster and the total valid cluster count. */ + *last_valid_cluster = prev_cluster; + *total_valid_clusters = count; + + /* Return error code. */ + return(error); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c b/src/Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c new file mode 100644 index 00000000..1f2b8bd7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_check_lost_cluster_check.c @@ -0,0 +1,282 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_check_lost_cluster_check PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function examines all clusters to see if there are any unused */ +/* clusters that are also unavailable. If specified, this routine will */ +/* also mark the cluster as available. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to a previously */ +/* opened media */ +/* logical_fat Pointer to the logical FAT */ +/* bit map */ +/* total_clusters Total number of clusters */ +/* error_correction_option Option for correcting lost */ +/* cluster errors */ +/* */ +/* OUTPUT */ +/* */ +/* error Error code */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_FAT_entry_write Write a FAT entry */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_check_media Check media function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _fx_media_check_lost_cluster_check(FX_MEDIA *media_ptr, UCHAR *logical_fat, ULONG total_clusters, ULONG error_correction_option) +{ + +ULONG cluster, next_cluster = 0; +ULONG fat_last; +ULONG error; +UINT status; + + + /* Calculate the FAT reserved and last sector values. */ + if (media_ptr -> fx_media_32_bit_FAT) + { + fat_last = FX_LAST_CLUSTER_1_32; + } + else + { + fat_last = FX_LAST_CLUSTER_1; + } + + /* Initialize the error. */ + error = 0; + + /* Loop through all the clusters to see if any clusters NOT in the logical sector FAT have + a non zero value. */ + for (cluster = FX_FAT_ENTRY_START; cluster < total_clusters; cluster++) + { + + /* Determine if this cluster is in the logical FAT. */ + if (logical_fat[cluster >> 3] & (1 << (cluster & 7))) + { + + /* Yes, the cluster is in use by a file or sub-directory. Just continue the loop. */ + continue; + } + + /* Otherwise, the cluster is not in use. */ + + /* Read the contents of what should be a free cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for a good status. */ + if (status) + { + + /* Set the error code. */ + error = error | FX_IO_ERROR; + + /* Return error code. */ + return(error); + } + + /* Determine if the contents of the cluster is valid. */ + if (((next_cluster > (ULONG)FX_FREE_CLUSTER) && (next_cluster < media_ptr -> fx_media_fat_reserved)) || + (next_cluster >= fat_last)) + { + + /* Lost cluster is present. */ + + /* Set the error code status. */ + error = FX_LOST_CLUSTER_ERROR; + + /* Determine if the lost cluster should be recovered. */ + if (error_correction_option & FX_LOST_CLUSTER_ERROR) + { + + /* Make the cluster available again. */ + status = _fx_utility_FAT_entry_write(media_ptr, cluster, FX_FREE_CLUSTER); + + /* Check for a good status. */ + if (status) + { + + /* Increment the available clusters. */ + media_ptr -> fx_media_available_clusters++; + + /* Set the error code. */ + error = error | FX_IO_ERROR; + + /* Return error code. */ + return(error); + } + } + } + } + + /* Return error code. */ + return(error); +} + +#ifdef FX_ENABLE_EXFAT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_check_exFAT_lost_cluster_check PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function examines all clusters in exFAT to see if there are */ +/* any unused clusters that are also unavailable. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to a previously */ +/* opened media */ +/* logical_fat Pointer to the logical FAT */ +/* bit map */ +/* total_clusters Total number of clusters */ +/* error_correction_option Option for correcting lost */ +/* cluster errors */ +/* */ +/* OUTPUT */ +/* */ +/* error Error code */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_bitmap_flush Flush dirty bitmap clusters */ +/* _fx_utility_exFAT_bitmap_cache_update Cache bitmap clusters */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_check_media Check media function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _fx_media_check_exFAT_lost_cluster_check(FX_MEDIA *media_ptr, UCHAR *logical_fat, ULONG total_clusters, ULONG error_correction_option) +{ +ULONG cluster = FX_FAT_ENTRY_START; +ULONG cached_bitmap_bytes = media_ptr -> fx_media_exfat_bitmap_cache_size_in_sectors * media_ptr -> fx_media_bytes_per_sector; +ULONG cached_bitmap_bits = cached_bitmap_bytes << 3; +ULONG offset = 0; +UINT status, i; + + /* This parameter has not been supported yet. */ + FX_PARAMETER_NOT_USED(error_correction_option); + + /* Flush Allocation Bitmap Table first. */ + status = _fx_utility_exFAT_bitmap_flush(media_ptr); + + if (FX_SUCCESS != status) + { + return(status); + } + + while (total_clusters) + { + + /* Read Allocation Bitmap Table from disk. */ + status = _fx_utility_exFAT_bitmap_cache_update(media_ptr, cluster); + + if (FX_SUCCESS != status) + { + return(status); + } + + if (total_clusters >= cached_bitmap_bits) + { + total_clusters -= cached_bitmap_bits; + + /* Compare cached bitmap with logical_fat. */ + for (i = 0; i < media_ptr -> fx_media_bytes_per_sector; i++) + { + if (logical_fat[offset + i] != ((UCHAR *)(media_ptr -> fx_media_exfat_bitmap_cache))[i]) + { + return(FX_LOST_CLUSTER_ERROR); + } + + offset += cached_bitmap_bytes; + cluster += cached_bitmap_bits; + } + } + else + { + + /* Compare cached bitmap with logical_fat. */ + for (i = 0; i < ((total_clusters + 7) >> 3); i++) + { + if (logical_fat[offset + i] != ((UCHAR *)(media_ptr -> fx_media_exfat_bitmap_cache))[i]) + { + return(FX_LOST_CLUSTER_ERROR); + } + } + + total_clusters = 0; + } + } + + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_EXFAT */ diff --git a/src/Middlewares/ST/filex/common/src/fx_media_close.c b/src/Middlewares/ST/filex/common/src/fx_media_close.c new file mode 100644 index 00000000..2d7cb24b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_close.c @@ -0,0 +1,447 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" +#include "fx_file.h" +#include "fx_directory.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_close PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function examines the list of open files for this media and */ +/* closes each file. If a file has been written to, the file's */ +/* directory information is also written out to the media. After */ +/* the files have been closed, the internal logical sector is */ +/* flushed and a flush command is sent to the attached driver. */ +/* Finally, this media control block is removed from the list of */ +/* opened media control blocks and is marked as closed. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the directory entry */ +/* _fx_media_abort Abort the media on error */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_FAT_flush Flush cached FAT entries */ +/* _fx_utility_FAT_map_flush Flush primary FAT changes to */ +/* secondary FAT(s) */ +/* _fx_utility_logical_sector_flush Flush logical sector cache */ +/* _fx_utility_16_unsigned_read Read a 16-bit value */ +/* _fx_utility_32_unsigned_read Read a 32-bit value */ +/* _fx_utility_32_unsigned_write Write a 32-bit value */ +/* tx_mutex_delete Delete protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable file close */ +/* and cache, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_close(FX_MEDIA *media_ptr) +{ + +FX_INT_SAVE_AREA + +#ifndef FX_DISABLE_FILE_CLOSE +ULONG open_count; +FX_FILE *file_ptr; +#endif /* FX_DISABLE_FILE_CLOSE */ +UINT status; + + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_CLOSE, media_ptr, 0, 0, 0, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* If trace is enabled, unregister this object. */ + FX_TRACE_OBJECT_UNREGISTER(media_ptr) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifndef FX_DISABLE_FILE_CLOSE + /* Loop through the media's open files. */ + open_count = media_ptr -> fx_media_opened_file_count; + file_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Look at each opened file to see if the same file is opened + for writing and has been written to. */ + if ((file_ptr -> fx_file_open_mode == FX_OPEN_FOR_WRITE) && + (file_ptr -> fx_file_modified)) + { + + /* Lockout interrupts for time/date access. */ + FX_DISABLE_INTS + + /* Set the new time and date. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_time = _fx_system_time; + file_ptr -> fx_file_dir_entry.fx_dir_entry_date = _fx_system_date; + + /* Restore interrupt posture. */ + FX_RESTORE_INTS + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = + file_ptr -> fx_file_current_file_size; + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + status = _fx_directory_exFAT_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if the status was unsuccessful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Call the media abort routine. */ + _fx_media_abort(media_ptr); + + /* Return the error status. */ + return(FX_IO_ERROR); + } + + /* Clear the file modified flag. */ + file_ptr -> fx_file_modified = FX_FALSE; + } + + /* Mark the file as closed. */ + file_ptr -> fx_file_id = FX_FILE_CLOSED_ID; + + /* Adjust the pointer and decrement the opened count. */ + file_ptr = file_ptr -> fx_file_opened_next; + open_count--; + } +#endif /* FX_DISABLE_FILE_CLOSE */ + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); + + /* Flush changed sector(s) in the primary FAT to secondary FATs. */ + _fx_utility_FAT_map_flush(media_ptr); + +#ifdef FX_ENABLE_EXFAT + if ((media_ptr -> fx_media_FAT_type == FX_exFAT) && + (FX_TRUE == media_ptr -> fx_media_exfat_bitmap_cache_dirty)) + { + + /* Flush bitmap. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + + /* Flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, ((ULONG64) 1), (ULONG64) (media_ptr -> fx_media_total_sectors), FX_FALSE); + + /* Determine if the flush was unsuccessful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Call the media abort routine. */ + _fx_media_abort(media_ptr); + + /* Return the error status. */ + return(FX_IO_ERROR); + } + + /* Determine if the media needs to have the additional information sector updated. This will + only be the case for 32-bit FATs. The logic here only needs to be done if the last reported + available cluster count is different that the currently available clusters. */ + if ((media_ptr -> fx_media_FAT32_additional_info_sector) && + (media_ptr -> fx_media_FAT32_additional_info_last_available != media_ptr -> fx_media_available_clusters) && + (media_ptr -> fx_media_driver_write_protect == FX_FALSE)) + { + + UCHAR *buffer_ptr; + ULONG signature; + + +#ifndef FX_DISABLE_CACHE + /* Setup a pointer to the first cached entry's buffer. */ + buffer_ptr = (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector_memory_buffer; + + /* Invalidate this cache entry. */ + (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector = (~(ULONG64)0); + (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector_valid = FX_FALSE; +#else + buffer_ptr = media_ptr -> fx_media_memory_buffer; +#endif /* FX_DISABLE_CACHE */ + + /* Read the FAT32 additional information sector from the device. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = buffer_ptr; + media_ptr -> fx_media_driver_logical_sector = media_ptr -> fx_media_FAT32_additional_info_sector; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver read sector(s) requests. */ + media_ptr -> fx_media_driver_read_requests++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_READ, media_ptr, media_ptr -> fx_media_FAT32_additional_info_sector, 1, buffer_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the FAT32 additional information sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the FAT32 sector was read correctly. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Call the media abort routine. */ + _fx_media_abort(media_ptr); + + /* Return the error status. */ + return(FX_IO_ERROR); + } + + /* Setup a pointer into the FAT32 additional information sector. */ + buffer_ptr = media_ptr -> fx_media_driver_buffer; + + /* Pickup the first signature long word. */ + signature = _fx_utility_32_unsigned_read(&buffer_ptr[0]); + + /* Determine if the signature is correct. */ + if (signature == 0x41615252) + { + + /* Yes, the first signature is correct, now pickup the next signature. */ + signature = _fx_utility_32_unsigned_read(&buffer_ptr[484]); + + /* Determine if this signature is correct. */ + if (signature == 0x61417272) + { + + /* Yes, we have a good FAT32 additional information sector. */ + + /* Set the free cluster count to the available clusters in the media control block. */ + _fx_utility_32_unsigned_write(&buffer_ptr[488], media_ptr -> fx_media_available_clusters); + + /* Set the next free cluster number hint to starting search cluster in the media control block. */ + _fx_utility_32_unsigned_write(&buffer_ptr[492], media_ptr -> fx_media_cluster_search_start); + + /* Now write the sector back out to the media. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = buffer_ptr; + media_ptr -> fx_media_driver_logical_sector = media_ptr -> fx_media_FAT32_additional_info_sector; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + + /* Set the system write flag since we are writing a directory sector. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, media_ptr -> fx_media_FAT32_additional_info_sector, 1, buffer_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the FAT32 additional information sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if the FAT32 sector was written correctly. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Call the media abort routine. */ + _fx_media_abort(media_ptr); + + /* Return the sector IO error status. */ + return(FX_IO_ERROR); + } + + /* Successful update of the FAT32 additional information sector. Update the + last written available cluster count. */ + media_ptr -> fx_media_FAT32_additional_info_last_available = media_ptr -> fx_media_available_clusters; + } + } + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver flush requests. */ + media_ptr -> fx_media_driver_flush_requests++; +#endif + + /* Build the "flush" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_FLUSH; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_FLUSH, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the flush request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Now remove this media from the open list. */ + + /* Lockout interrupts for media removal. */ + FX_DISABLE_INTS + + /* See if the media is the only one on the media opened list. */ + if (_fx_system_media_opened_count == ((ULONG) 1)) + { + + /* Only opened media, just set the opened list to NULL. */ + _fx_system_media_opened_ptr = FX_NULL; + } + else + { + + /* Otherwise, not the only opened media, link-up the neighbors. */ + (media_ptr -> fx_media_opened_next) -> fx_media_opened_previous = + media_ptr -> fx_media_opened_previous; + (media_ptr -> fx_media_opened_previous) -> fx_media_opened_next = + media_ptr -> fx_media_opened_next; + + /* See if we have to update the opened list head pointer. */ + if (_fx_system_media_opened_ptr == media_ptr) + { + + /* Yes, move the head pointer to the next opened media. */ + _fx_system_media_opened_ptr = media_ptr -> fx_media_opened_next; + } + } + + /* Decrement the opened media counter. */ + _fx_system_media_opened_count--; + + /* Finally, Indicate that this media is closed. */ + media_ptr -> fx_media_id = FX_MEDIA_CLOSED_ID; + + /* Restore interrupt posture. */ + FX_RESTORE_INTS + + /* Delete the media protection structure if FX_SINGLE_THREAD is not + defined. */ +#ifndef FX_SINGLE_THREAD + +#ifndef FX_DONT_CREATE_MUTEX + + /* Note that the protection is never released. The mutex delete + service will handle all threads waiting access to this media + control block. */ + tx_mutex_delete(& (media_ptr -> fx_media_protect)); +#endif +#endif + + /* Invoke media close callback. */ + if (media_ptr -> fx_media_close_notify) + { + media_ptr -> fx_media_close_notify(media_ptr); + } + +#ifdef FX_DONT_CREATE_MUTEX + + /* Release media protection. */ + FX_UNPROTECT +#endif + + /* Return success status to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_close_notify_set.c b/src/Middlewares/ST/filex/common/src/fx_media_close_notify_set.c new file mode 100644 index 00000000..8bb42a82 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_close_notify_set.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_close_notif_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the notify function called when media is open. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* media_close_notify Notify function called when */ +/* media is closed */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_close_notify_set(FX_MEDIA *media_ptr, VOID (*media_close_notify)(FX_MEDIA *media)) +{ + + /* Set the notify function. */ + media_ptr -> fx_media_close_notify = media_close_notify; + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_exFAT_format.c b/src/Middlewares/ST/filex/common/src/fx_media_exFAT_format.c new file mode 100644 index 00000000..5f2e4ec4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_exFAT_format.c @@ -0,0 +1,1231 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/* Define upper case table for exFAT formatting. */ + +const UCHAR _fx_utility_exFAT_upcase_table_compressed[] = +{ + /* Sector 1 */ + + 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x00, 0x06, 0x00, 0x07, 0x00, + 0x08, 0x00, 0x09, 0x00, 0x0a, 0x00, 0x0b, 0x00, 0x0c, 0x00, 0x0d, 0x00, 0x0e, 0x00, 0x0f, 0x00, + 0x10, 0x00, 0x11, 0x00, 0x12, 0x00, 0x13, 0x00, 0x14, 0x00, 0x15, 0x00, 0x16, 0x00, 0x17, 0x00, + 0x18, 0x00, 0x19, 0x00, 0x1a, 0x00, 0x1b, 0x00, 0x1c, 0x00, 0x1d, 0x00, 0x1e, 0x00, 0x1f, 0x00, + 0x20, 0x00, 0x21, 0x00, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00, 0x25, 0x00, 0x26, 0x00, 0x27, 0x00, + 0x28, 0x00, 0x29, 0x00, 0x2a, 0x00, 0x2b, 0x00, 0x2c, 0x00, 0x2d, 0x00, 0x2e, 0x00, 0x2f, 0x00, + 0x30, 0x00, 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00, 0x36, 0x00, 0x37, 0x00, + 0x38, 0x00, 0x39, 0x00, 0x3a, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00, + 0x40, 0x00, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0x00, 0x45, 0x00, 0x46, 0x00, 0x47, 0x00, + 0x48, 0x00, 0x49, 0x00, 0x4a, 0x00, 0x4b, 0x00, 0x4c, 0x00, 0x4d, 0x00, 0x4e, 0x00, 0x4f, 0x00, + 0x50, 0x00, 0x51, 0x00, 0x52, 0x00, 0x53, 0x00, 0x54, 0x00, 0x55, 0x00, 0x56, 0x00, 0x57, 0x00, + 0x58, 0x00, 0x59, 0x00, 0x5a, 0x00, 0x5b, 0x00, 0x5c, 0x00, 0x5d, 0x00, 0x5e, 0x00, 0x5f, 0x00, + 0x60, 0x00, 0x41, 0x00, 0x42, 0x00, 0x43, 0x00, 0x44, 0x00, 0x45, 0x00, 0x46, 0x00, 0x47, 0x00, + 0x48, 0x00, 0x49, 0x00, 0x4a, 0x00, 0x4b, 0x00, 0x4c, 0x00, 0x4d, 0x00, 0x4e, 0x00, 0x4f, 0x00, + 0x50, 0x00, 0x51, 0x00, 0x52, 0x00, 0x53, 0x00, 0x54, 0x00, 0x55, 0x00, 0x56, 0x00, 0x57, 0x00, + 0x58, 0x00, 0x59, 0x00, 0x5a, 0x00, 0x7b, 0x00, 0x7c, 0x00, 0x7d, 0x00, 0x7e, 0x00, 0x7f, 0x00, + 0x80, 0x00, 0x81, 0x00, 0x82, 0x00, 0x83, 0x00, 0x84, 0x00, 0x85, 0x00, 0x86, 0x00, 0x87, 0x00, + 0x88, 0x00, 0x89, 0x00, 0x8a, 0x00, 0x8b, 0x00, 0x8c, 0x00, 0x8d, 0x00, 0x8e, 0x00, 0x8f, 0x00, + 0x90, 0x00, 0x91, 0x00, 0x92, 0x00, 0x93, 0x00, 0x94, 0x00, 0x95, 0x00, 0x96, 0x00, 0x97, 0x00, + 0x98, 0x00, 0x99, 0x00, 0x9a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0x9d, 0x00, 0x9e, 0x00, 0x9f, 0x00, + 0xa0, 0x00, 0xa1, 0x00, 0xa2, 0x00, 0xa3, 0x00, 0xa4, 0x00, 0xa5, 0x00, 0xa6, 0x00, 0xa7, 0x00, + 0xa8, 0x00, 0xa9, 0x00, 0xaa, 0x00, 0xab, 0x00, 0xac, 0x00, 0xad, 0x00, 0xae, 0x00, 0xaf, 0x00, + 0xb0, 0x00, 0xb1, 0x00, 0xb2, 0x00, 0xb3, 0x00, 0xb4, 0x00, 0xb5, 0x00, 0xb6, 0x00, 0xb7, 0x00, + 0xb8, 0x00, 0xb9, 0x00, 0xba, 0x00, 0xbb, 0x00, 0xbc, 0x00, 0xbd, 0x00, 0xbe, 0x00, 0xbf, 0x00, + 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0x00, 0xc3, 0x00, 0xc4, 0x00, 0xc5, 0x00, 0xc6, 0x00, 0xc7, 0x00, + 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb, 0x00, 0xcc, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x00, + 0xd0, 0x00, 0xd1, 0x00, 0xd2, 0x00, 0xd3, 0x00, 0xd4, 0x00, 0xd5, 0x00, 0xd6, 0x00, 0xd7, 0x00, + 0xd8, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x00, 0xdd, 0x00, 0xde, 0x00, 0xdf, 0x00, + 0xc0, 0x00, 0xc1, 0x00, 0xc2, 0x00, 0xc3, 0x00, 0xc4, 0x00, 0xc5, 0x00, 0xc6, 0x00, 0xc7, 0x00, + 0xc8, 0x00, 0xc9, 0x00, 0xca, 0x00, 0xcb, 0x00, 0xcc, 0x00, 0xcd, 0x00, 0xce, 0x00, 0xcf, 0x00, + 0xd0, 0x00, 0xd1, 0x00, 0xd2, 0x00, 0xd3, 0x00, 0xd4, 0x00, 0xd5, 0x00, 0xd6, 0x00, 0xf7, 0x00, + 0xd8, 0x00, 0xd9, 0x00, 0xda, 0x00, 0xdb, 0x00, 0xdc, 0x00, 0xdd, 0x00, 0xde, 0x00, 0x78, 0x01, + + /* Sector 2 */ + + 0x00, 0x01, 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x04, 0x01, 0x04, 0x01, 0x06, 0x01, 0x06, 0x01, + 0x08, 0x01, 0x08, 0x01, 0x0a, 0x01, 0x0a, 0x01, 0x0c, 0x01, 0x0c, 0x01, 0x0e, 0x01, 0x0e, 0x01, + 0x10, 0x01, 0x10, 0x01, 0x12, 0x01, 0x12, 0x01, 0x14, 0x01, 0x14, 0x01, 0x16, 0x01, 0x16, 0x01, + 0x18, 0x01, 0x18, 0x01, 0x1a, 0x01, 0x1a, 0x01, 0x1c, 0x01, 0x1c, 0x01, 0x1e, 0x01, 0x1e, 0x01, + 0x20, 0x01, 0x20, 0x01, 0x22, 0x01, 0x22, 0x01, 0x24, 0x01, 0x24, 0x01, 0x26, 0x01, 0x26, 0x01, + 0x28, 0x01, 0x28, 0x01, 0x2a, 0x01, 0x2a, 0x01, 0x2c, 0x01, 0x2c, 0x01, 0x2e, 0x01, 0x2e, 0x01, + 0x30, 0x01, 0x31, 0x01, 0x32, 0x01, 0x32, 0x01, 0x34, 0x01, 0x34, 0x01, 0x36, 0x01, 0x36, 0x01, + 0x38, 0x01, 0x39, 0x01, 0x39, 0x01, 0x3b, 0x01, 0x3b, 0x01, 0x3d, 0x01, 0x3d, 0x01, 0x3f, 0x01, + 0x3f, 0x01, 0x41, 0x01, 0x41, 0x01, 0x43, 0x01, 0x43, 0x01, 0x45, 0x01, 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0x01, + 0x98, 0x01, 0x98, 0x01, 0x3d, 0x02, 0x9b, 0x01, 0x9c, 0x01, 0x9d, 0x01, 0x20, 0x02, 0x9f, 0x01, + 0xa0, 0x01, 0xa0, 0x01, 0xa2, 0x01, 0xa2, 0x01, 0xa4, 0x01, 0xa4, 0x01, 0xa6, 0x01, 0xa7, 0x01, + 0xa7, 0x01, 0xa9, 0x01, 0xaa, 0x01, 0xab, 0x01, 0xac, 0x01, 0xac, 0x01, 0xae, 0x01, 0xaf, 0x01, + 0xaf, 0x01, 0xb1, 0x01, 0xb2, 0x01, 0xb3, 0x01, 0xb3, 0x01, 0xb5, 0x01, 0xb5, 0x01, 0xb7, 0x01, + 0xb8, 0x01, 0xb8, 0x01, 0xba, 0x01, 0xbb, 0x01, 0xbc, 0x01, 0xbc, 0x01, 0xbe, 0x01, 0xf7, 0x01, + 0xc0, 0x01, 0xc1, 0x01, 0xc2, 0x01, 0xc3, 0x01, 0xc4, 0x01, 0xc5, 0x01, 0xc4, 0x01, 0xc7, 0x01, + 0xc8, 0x01, 0xc7, 0x01, 0xca, 0x01, 0xcb, 0x01, 0xca, 0x01, 0xcd, 0x01, 0xcd, 0x01, 0xcf, 0x01, + 0xcf, 0x01, 0xd1, 0x01, 0xd1, 0x01, 0xd3, 0x01, 0xd3, 0x01, 0xd5, 0x01, 0xd5, 0x01, 0xd7, 0x01, + 0xd7, 0x01, 0xd9, 0x01, 0xd9, 0x01, 0xdb, 0x01, 0xdb, 0x01, 0x8e, 0x01, 0xde, 0x01, 0xde, 0x01, + 0xe0, 0x01, 0xe0, 0x01, 0xe2, 0x01, 0xe2, 0x01, 0xe4, 0x01, 0xe4, 0x01, 0xe6, 0x01, 0xe6, 0x01, + 0xe8, 0x01, 0xe8, 0x01, 0xea, 0x01, 0xea, 0x01, 0xec, 0x01, 0xec, 0x01, 0xee, 0x01, 0xee, 0x01, + 0xf0, 0x01, 0xf1, 0x01, 0xf2, 0x01, 0xf1, 0x01, 0xf4, 0x01, 0xf4, 0x01, 0xf6, 0x01, 0xf7, 0x01, + 0xf8, 0x01, 0xf8, 0x01, 0xfa, 0x01, 0xfa, 0x01, 0xfc, 0x01, 0xfc, 0x01, 0xfe, 0x01, 0xfe, 0x01, + + /* Sector 3 */ + + 0x00, 0x02, 0x00, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0x02, 0x04, 0x02, 0x06, 0x02, 0x06, 0x02, + 0x08, 0x02, 0x08, 0x02, 0x0a, 0x02, 0x0a, 0x02, 0x0c, 0x02, 0x0c, 0x02, 0x0e, 0x02, 0x0e, 0x02, + 0x10, 0x02, 0x10, 0x02, 0x12, 0x02, 0x12, 0x02, 0x14, 0x02, 0x14, 0x02, 0x16, 0x02, 0x16, 0x02, + 0x18, 0x02, 0x18, 0x02, 0x1a, 0x02, 0x1a, 0x02, 0x1c, 0x02, 0x1c, 0x02, 0x1e, 0x02, 0x1e, 0x02, + 0x20, 0x02, 0x21, 0x02, 0x22, 0x02, 0x22, 0x02, 0x24, 0x02, 0x24, 0x02, 0x26, 0x02, 0x26, 0x02, + 0x28, 0x02, 0x28, 0x02, 0x2a, 0x02, 0x2a, 0x02, 0x2c, 0x02, 0x2c, 0x02, 0x2e, 0x02, 0x2e, 0x02, + 0x30, 0x02, 0x30, 0x02, 0x32, 0x02, 0x32, 0x02, 0x34, 0x02, 0x35, 0x02, 0x36, 0x02, 0x37, 0x02, + 0x38, 0x02, 0x39, 0x02, 0x65, 0x2c, 0x3b, 0x02, 0x3b, 0x02, 0x3d, 0x02, 0x66, 0x2c, 0x3f, 0x02, + 0x40, 0x02, 0x41, 0x02, 0x41, 0x02, 0x43, 0x02, 0x44, 0x02, 0x45, 0x02, 0x46, 0x02, 0x46, 0x02, + 0x48, 0x02, 0x48, 0x02, 0x4a, 0x02, 0x4a, 0x02, 0x4c, 0x02, 0x4c, 0x02, 0x4e, 0x02, 0x4e, 0x02, + 0x50, 0x02, 0x51, 0x02, 0x52, 0x02, 0x81, 0x01, 0x86, 0x01, 0x55, 0x02, 0x89, 0x01, 0x8a, 0x01, + 0x58, 0x02, 0x8f, 0x01, 0x5a, 0x02, 0x90, 0x01, 0x5c, 0x02, 0x5d, 0x02, 0x5e, 0x02, 0x5f, 0x02, + 0x93, 0x01, 0x61, 0x02, 0x62, 0x02, 0x94, 0x01, 0x64, 0x02, 0x65, 0x02, 0x66, 0x02, 0x67, 0x02, + 0x97, 0x01, 0x96, 0x01, 0x6a, 0x02, 0x62, 0x2c, 0x6c, 0x02, 0x6d, 0x02, 0x6e, 0x02, 0x9c, 0x01, + 0x70, 0x02, 0x71, 0x02, 0x9d, 0x01, 0x73, 0x02, 0x74, 0x02, 0x9f, 0x01, 0x76, 0x02, 0x77, 0x02, + 0x78, 0x02, 0x79, 0x02, 0x7a, 0x02, 0x7b, 0x02, 0x7c, 0x02, 0x64, 0x2c, 0x7e, 0x02, 0x7f, 0x02, + 0xa6, 0x01, 0x81, 0x02, 0x82, 0x02, 0xa9, 0x01, 0x84, 0x02, 0x85, 0x02, 0x86, 0x02, 0x87, 0x02, + 0xae, 0x01, 0x44, 0x02, 0xb1, 0x01, 0xb2, 0x01, 0x45, 0x02, 0x8d, 0x02, 0x8e, 0x02, 0x8f, 0x02, + 0x90, 0x02, 0x91, 0x02, 0xb7, 0x01, 0x93, 0x02, 0x94, 0x02, 0x95, 0x02, 0x96, 0x02, 0x97, 0x02, + 0x98, 0x02, 0x99, 0x02, 0x9a, 0x02, 0x9b, 0x02, 0x9c, 0x02, 0x9d, 0x02, 0x9e, 0x02, 0x9f, 0x02, + 0xa0, 0x02, 0xa1, 0x02, 0xa2, 0x02, 0xa3, 0x02, 0xa4, 0x02, 0xa5, 0x02, 0xa6, 0x02, 0xa7, 0x02, + 0xa8, 0x02, 0xa9, 0x02, 0xaa, 0x02, 0xab, 0x02, 0xac, 0x02, 0xad, 0x02, 0xae, 0x02, 0xaf, 0x02, + 0xb0, 0x02, 0xb1, 0x02, 0xb2, 0x02, 0xb3, 0x02, 0xb4, 0x02, 0xb5, 0x02, 0xb6, 0x02, 0xb7, 0x02, + 0xb8, 0x02, 0xb9, 0x02, 0xba, 0x02, 0xbb, 0x02, 0xbc, 0x02, 0xbd, 0x02, 0xbe, 0x02, 0xbf, 0x02, + 0xc0, 0x02, 0xc1, 0x02, 0xc2, 0x02, 0xc3, 0x02, 0xc4, 0x02, 0xc5, 0x02, 0xc6, 0x02, 0xc7, 0x02, + 0xc8, 0x02, 0xc9, 0x02, 0xca, 0x02, 0xcb, 0x02, 0xcc, 0x02, 0xcd, 0x02, 0xce, 0x02, 0xcf, 0x02, + 0xd0, 0x02, 0xd1, 0x02, 0xd2, 0x02, 0xd3, 0x02, 0xd4, 0x02, 0xd5, 0x02, 0xd6, 0x02, 0xd7, 0x02, + 0xd8, 0x02, 0xd9, 0x02, 0xda, 0x02, 0xdb, 0x02, 0xdc, 0x02, 0xdd, 0x02, 0xde, 0x02, 0xdf, 0x02, + 0xe0, 0x02, 0xe1, 0x02, 0xe2, 0x02, 0xe3, 0x02, 0xe4, 0x02, 0xe5, 0x02, 0xe6, 0x02, 0xe7, 0x02, + 0xe8, 0x02, 0xe9, 0x02, 0xea, 0x02, 0xeb, 0x02, 0xec, 0x02, 0xed, 0x02, 0xee, 0x02, 0xef, 0x02, + 0xf0, 0x02, 0xf1, 0x02, 0xf2, 0x02, 0xf3, 0x02, 0xf4, 0x02, 0xf5, 0x02, 0xf6, 0x02, 0xf7, 0x02, + 0xf8, 0x02, 0xf9, 0x02, 0xfa, 0x02, 0xfb, 0x02, 0xfc, 0x02, 0xfd, 0x02, 0xfe, 0x02, 0xff, 0x02, + + /* Sector 4 */ + + 0x00, 0x03, 0x01, 0x03, 0x02, 0x03, 0x03, 0x03, 0x04, 0x03, 0x05, 0x03, 0x06, 0x03, 0x07, 0x03, + 0x08, 0x03, 0x09, 0x03, 0x0a, 0x03, 0x0b, 0x03, 0x0c, 0x03, 0x0d, 0x03, 0x0e, 0x03, 0x0f, 0x03, + 0x10, 0x03, 0x11, 0x03, 0x12, 0x03, 0x13, 0x03, 0x14, 0x03, 0x15, 0x03, 0x16, 0x03, 0x17, 0x03, + 0x18, 0x03, 0x19, 0x03, 0x1a, 0x03, 0x1b, 0x03, 0x1c, 0x03, 0x1d, 0x03, 0x1e, 0x03, 0x1f, 0x03, + 0x20, 0x03, 0x21, 0x03, 0x22, 0x03, 0x23, 0x03, 0x24, 0x03, 0x25, 0x03, 0x26, 0x03, 0x27, 0x03, + 0x28, 0x03, 0x29, 0x03, 0x2a, 0x03, 0x2b, 0x03, 0x2c, 0x03, 0x2d, 0x03, 0x2e, 0x03, 0x2f, 0x03, + 0x30, 0x03, 0x31, 0x03, 0x32, 0x03, 0x33, 0x03, 0x34, 0x03, 0x35, 0x03, 0x36, 0x03, 0x37, 0x03, + 0x38, 0x03, 0x39, 0x03, 0x3a, 0x03, 0x3b, 0x03, 0x3c, 0x03, 0x3d, 0x03, 0x3e, 0x03, 0x3f, 0x03, + 0x40, 0x03, 0x41, 0x03, 0x42, 0x03, 0x43, 0x03, 0x44, 0x03, 0x45, 0x03, 0x46, 0x03, 0x47, 0x03, + 0x48, 0x03, 0x49, 0x03, 0x4a, 0x03, 0x4b, 0x03, 0x4c, 0x03, 0x4d, 0x03, 0x4e, 0x03, 0x4f, 0x03, + 0x50, 0x03, 0x51, 0x03, 0x52, 0x03, 0x53, 0x03, 0x54, 0x03, 0x55, 0x03, 0x56, 0x03, 0x57, 0x03, + 0x58, 0x03, 0x59, 0x03, 0x5a, 0x03, 0x5b, 0x03, 0x5c, 0x03, 0x5d, 0x03, 0x5e, 0x03, 0x5f, 0x03, + 0x60, 0x03, 0x61, 0x03, 0x62, 0x03, 0x63, 0x03, 0x64, 0x03, 0x65, 0x03, 0x66, 0x03, 0x67, 0x03, + 0x68, 0x03, 0x69, 0x03, 0x6a, 0x03, 0x6b, 0x03, 0x6c, 0x03, 0x6d, 0x03, 0x6e, 0x03, 0x6f, 0x03, + 0x70, 0x03, 0x71, 0x03, 0x72, 0x03, 0x73, 0x03, 0x74, 0x03, 0x75, 0x03, 0x76, 0x03, 0x77, 0x03, + 0x78, 0x03, 0x79, 0x03, 0x7a, 0x03, 0xfd, 0x03, 0xfe, 0x03, 0xff, 0x03, 0x7e, 0x03, 0x7f, 0x03, + 0x80, 0x03, 0x81, 0x03, 0x82, 0x03, 0x83, 0x03, 0x84, 0x03, 0x85, 0x03, 0x86, 0x03, 0x87, 0x03, + 0x88, 0x03, 0x89, 0x03, 0x8a, 0x03, 0x8b, 0x03, 0x8c, 0x03, 0x8d, 0x03, 0x8e, 0x03, 0x8f, 0x03, + 0x90, 0x03, 0x91, 0x03, 0x92, 0x03, 0x93, 0x03, 0x94, 0x03, 0x95, 0x03, 0x96, 0x03, 0x97, 0x03, + 0x98, 0x03, 0x99, 0x03, 0x9a, 0x03, 0x9b, 0x03, 0x9c, 0x03, 0x9d, 0x03, 0x9e, 0x03, 0x9f, 0x03, + 0xa0, 0x03, 0xa1, 0x03, 0xa2, 0x03, 0xa3, 0x03, 0xa4, 0x03, 0xa5, 0x03, 0xa6, 0x03, 0xa7, 0x03, + 0xa8, 0x03, 0xa9, 0x03, 0xaa, 0x03, 0xab, 0x03, 0x86, 0x03, 0x88, 0x03, 0x89, 0x03, 0x8a, 0x03, + 0xb0, 0x03, 0x91, 0x03, 0x92, 0x03, 0x93, 0x03, 0x94, 0x03, 0x95, 0x03, 0x96, 0x03, 0x97, 0x03, + 0x98, 0x03, 0x99, 0x03, 0x9a, 0x03, 0x9b, 0x03, 0x9c, 0x03, 0x9d, 0x03, 0x9e, 0x03, 0x9f, 0x03, + 0xa0, 0x03, 0xa1, 0x03, 0xa3, 0x03, 0xa3, 0x03, 0xa4, 0x03, 0xa5, 0x03, 0xa6, 0x03, 0xa7, 0x03, + 0xa8, 0x03, 0xa9, 0x03, 0xaa, 0x03, 0xab, 0x03, 0x8c, 0x03, 0x8e, 0x03, 0x8f, 0x03, 0xcf, 0x03, + 0xd0, 0x03, 0xd1, 0x03, 0xd2, 0x03, 0xd3, 0x03, 0xd4, 0x03, 0xd5, 0x03, 0xd6, 0x03, 0xd7, 0x03, + 0xd8, 0x03, 0xd8, 0x03, 0xda, 0x03, 0xda, 0x03, 0xdc, 0x03, 0xdc, 0x03, 0xde, 0x03, 0xde, 0x03, + 0xe0, 0x03, 0xe0, 0x03, 0xe2, 0x03, 0xe2, 0x03, 0xe4, 0x03, 0xe4, 0x03, 0xe6, 0x03, 0xe6, 0x03, + 0xe8, 0x03, 0xe8, 0x03, 0xea, 0x03, 0xea, 0x03, 0xec, 0x03, 0xec, 0x03, 0xee, 0x03, 0xee, 0x03, + 0xf0, 0x03, 0xf1, 0x03, 0xf9, 0x03, 0xf3, 0x03, 0xf4, 0x03, 0xf5, 0x03, 0xf6, 0x03, 0xf7, 0x03, + 0xf7, 0x03, 0xf9, 0x03, 0xfa, 0x03, 0xfa, 0x03, 0xfc, 0x03, 0xfd, 0x03, 0xfe, 0x03, 0xff, 0x03, + + /* Sector 5 */ + + 0x00, 0x04, 0x01, 0x04, 0x02, 0x04, 0x03, 0x04, 0x04, 0x04, 0x05, 0x04, 0x06, 0x04, 0x07, 0x04, + 0x08, 0x04, 0x09, 0x04, 0x0a, 0x04, 0x0b, 0x04, 0x0c, 0x04, 0x0d, 0x04, 0x0e, 0x04, 0x0f, 0x04, + 0x10, 0x04, 0x11, 0x04, 0x12, 0x04, 0x13, 0x04, 0x14, 0x04, 0x15, 0x04, 0x16, 0x04, 0x17, 0x04, + 0x18, 0x04, 0x19, 0x04, 0x1a, 0x04, 0x1b, 0x04, 0x1c, 0x04, 0x1d, 0x04, 0x1e, 0x04, 0x1f, 0x04, + 0x20, 0x04, 0x21, 0x04, 0x22, 0x04, 0x23, 0x04, 0x24, 0x04, 0x25, 0x04, 0x26, 0x04, 0x27, 0x04, + 0x28, 0x04, 0x29, 0x04, 0x2a, 0x04, 0x2b, 0x04, 0x2c, 0x04, 0x2d, 0x04, 0x2e, 0x04, 0x2f, 0x04, + 0x10, 0x04, 0x11, 0x04, 0x12, 0x04, 0x13, 0x04, 0x14, 0x04, 0x15, 0x04, 0x16, 0x04, 0x17, 0x04, + 0x18, 0x04, 0x19, 0x04, 0x1a, 0x04, 0x1b, 0x04, 0x1c, 0x04, 0x1d, 0x04, 0x1e, 0x04, 0x1f, 0x04, + 0x20, 0x04, 0x21, 0x04, 0x22, 0x04, 0x23, 0x04, 0x24, 0x04, 0x25, 0x04, 0x26, 0x04, 0x27, 0x04, + 0x28, 0x04, 0x29, 0x04, 0x2a, 0x04, 0x2b, 0x04, 0x2c, 0x04, 0x2d, 0x04, 0x2e, 0x04, 0x2f, 0x04, + 0x00, 0x04, 0x01, 0x04, 0x02, 0x04, 0x03, 0x04, 0x04, 0x04, 0x05, 0x04, 0x06, 0x04, 0x07, 0x04, + 0x08, 0x04, 0x09, 0x04, 0x0a, 0x04, 0x0b, 0x04, 0x0c, 0x04, 0x0d, 0x04, 0x0e, 0x04, 0x0f, 0x04, + 0x60, 0x04, 0x60, 0x04, 0x62, 0x04, 0x62, 0x04, 0x64, 0x04, 0x64, 0x04, 0x66, 0x04, 0x66, 0x04, + 0x68, 0x04, 0x68, 0x04, 0x6a, 0x04, 0x6a, 0x04, 0x6c, 0x04, 0x6c, 0x04, 0x6e, 0x04, 0x6e, 0x04, + 0x70, 0x04, 0x70, 0x04, 0x72, 0x04, 0x72, 0x04, 0x74, 0x04, 0x74, 0x04, 0x76, 0x04, 0x76, 0x04, + 0x78, 0x04, 0x78, 0x04, 0x7a, 0x04, 0x7a, 0x04, 0x7c, 0x04, 0x7c, 0x04, 0x7e, 0x04, 0x7e, 0x04, + 0x80, 0x04, 0x80, 0x04, 0x82, 0x04, 0x83, 0x04, 0x84, 0x04, 0x85, 0x04, 0x86, 0x04, 0x87, 0x04, + 0x88, 0x04, 0x89, 0x04, 0x8a, 0x04, 0x8a, 0x04, 0x8c, 0x04, 0x8c, 0x04, 0x8e, 0x04, 0x8e, 0x04, + 0x90, 0x04, 0x90, 0x04, 0x92, 0x04, 0x92, 0x04, 0x94, 0x04, 0x94, 0x04, 0x96, 0x04, 0x96, 0x04, + 0x98, 0x04, 0x98, 0x04, 0x9a, 0x04, 0x9a, 0x04, 0x9c, 0x04, 0x9c, 0x04, 0x9e, 0x04, 0x9e, 0x04, + 0xa0, 0x04, 0xa0, 0x04, 0xa2, 0x04, 0xa2, 0x04, 0xa4, 0x04, 0xa4, 0x04, 0xa6, 0x04, 0xa6, 0x04, + 0xa8, 0x04, 0xa8, 0x04, 0xaa, 0x04, 0xaa, 0x04, 0xac, 0x04, 0xac, 0x04, 0xae, 0x04, 0xae, 0x04, + 0xb0, 0x04, 0xb0, 0x04, 0xb2, 0x04, 0xb2, 0x04, 0xb4, 0x04, 0xb4, 0x04, 0xb6, 0x04, 0xb6, 0x04, + 0xb8, 0x04, 0xb8, 0x04, 0xba, 0x04, 0xba, 0x04, 0xbc, 0x04, 0xbc, 0x04, 0xbe, 0x04, 0xbe, 0x04, + 0xc0, 0x04, 0xc1, 0x04, 0xc1, 0x04, 0xc3, 0x04, 0xc3, 0x04, 0xc5, 0x04, 0xc5, 0x04, 0xc7, 0x04, + 0xc7, 0x04, 0xc9, 0x04, 0xc9, 0x04, 0xcb, 0x04, 0xcb, 0x04, 0xcd, 0x04, 0xcd, 0x04, 0xc0, 0x04, + 0xd0, 0x04, 0xd0, 0x04, 0xd2, 0x04, 0xd2, 0x04, 0xd4, 0x04, 0xd4, 0x04, 0xd6, 0x04, 0xd6, 0x04, + 0xd8, 0x04, 0xd8, 0x04, 0xda, 0x04, 0xda, 0x04, 0xdc, 0x04, 0xdc, 0x04, 0xde, 0x04, 0xde, 0x04, + 0xe0, 0x04, 0xe0, 0x04, 0xe2, 0x04, 0xe2, 0x04, 0xe4, 0x04, 0xe4, 0x04, 0xe6, 0x04, 0xe6, 0x04, + 0xe8, 0x04, 0xe8, 0x04, 0xea, 0x04, 0xea, 0x04, 0xec, 0x04, 0xec, 0x04, 0xee, 0x04, 0xee, 0x04, + 0xf0, 0x04, 0xf0, 0x04, 0xf2, 0x04, 0xf2, 0x04, 0xf4, 0x04, 0xf4, 0x04, 0xf6, 0x04, 0xf6, 0x04, + 0xf8, 0x04, 0xf8, 0x04, 0xfa, 0x04, 0xfa, 0x04, 0xfc, 0x04, 0xfc, 0x04, 0xfe, 0x04, 0xfe, 0x04, + + /* Sector 6 */ + + 0x00, 0x05, 0x00, 0x05, 0x02, 0x05, 0x02, 0x05, 0x04, 0x05, 0x04, 0x05, 0x06, 0x05, 0x06, 0x05, + 0x08, 0x05, 0x08, 0x05, 0x0a, 0x05, 0x0a, 0x05, 0x0c, 0x05, 0x0c, 0x05, 0x0e, 0x05, 0x0e, 0x05, + 0x10, 0x05, 0x10, 0x05, 0x12, 0x05, 0x12, 0x05, 0x14, 0x05, 0x15, 0x05, 0x16, 0x05, 0x17, 0x05, + 0x18, 0x05, 0x19, 0x05, 0x1a, 0x05, 0x1b, 0x05, 0x1c, 0x05, 0x1d, 0x05, 0x1e, 0x05, 0x1f, 0x05, + 0x20, 0x05, 0x21, 0x05, 0x22, 0x05, 0x23, 0x05, 0x24, 0x05, 0x25, 0x05, 0x26, 0x05, 0x27, 0x05, + 0x28, 0x05, 0x29, 0x05, 0x2a, 0x05, 0x2b, 0x05, 0x2c, 0x05, 0x2d, 0x05, 0x2e, 0x05, 0x2f, 0x05, + 0x30, 0x05, 0x31, 0x05, 0x32, 0x05, 0x33, 0x05, 0x34, 0x05, 0x35, 0x05, 0x36, 0x05, 0x37, 0x05, + 0x38, 0x05, 0x39, 0x05, 0x3a, 0x05, 0x3b, 0x05, 0x3c, 0x05, 0x3d, 0x05, 0x3e, 0x05, 0x3f, 0x05, + 0x40, 0x05, 0x41, 0x05, 0x42, 0x05, 0x43, 0x05, 0x44, 0x05, 0x45, 0x05, 0x46, 0x05, 0x47, 0x05, + 0x48, 0x05, 0x49, 0x05, 0x4a, 0x05, 0x4b, 0x05, 0x4c, 0x05, 0x4d, 0x05, 0x4e, 0x05, 0x4f, 0x05, + 0x50, 0x05, 0x51, 0x05, 0x52, 0x05, 0x53, 0x05, 0x54, 0x05, 0x55, 0x05, 0x56, 0x05, 0x57, 0x05, + 0x58, 0x05, 0x59, 0x05, 0x5a, 0x05, 0x5b, 0x05, 0x5c, 0x05, 0x5d, 0x05, 0x5e, 0x05, 0x5f, 0x05, + 0x60, 0x05, 0x31, 0x05, 0x32, 0x05, 0x33, 0x05, 0x34, 0x05, 0x35, 0x05, 0x36, 0x05, 0x37, 0x05, + 0x38, 0x05, 0x39, 0x05, 0x3a, 0x05, 0x3b, 0x05, 0x3c, 0x05, 0x3d, 0x05, 0x3e, 0x05, 0x3f, 0x05, + 0x40, 0x05, 0x41, 0x05, 0x42, 0x05, 0x43, 0x05, 0x44, 0x05, 0x45, 0x05, 0x46, 0x05, 0x47, 0x05, + 0x48, 0x05, 0x49, 0x05, 0x4a, 0x05, 0x4b, 0x05, 0x4c, 0x05, 0x4d, 0x05, 0x4e, 0x05, 0x4f, 0x05, + 0x50, 0x05, 0x51, 0x05, 0x52, 0x05, 0x53, 0x05, 0x54, 0x05, 0x55, 0x05, 0x56, 0x05, 0xff, 0xff, + 0xf6, 0x17, 0x63, 0x2c, 0x7e, 0x1d, 0x7f, 0x1d, 0x80, 0x1d, 0x81, 0x1d, 0x82, 0x1d, 0x83, 0x1d, + 0x84, 0x1d, 0x85, 0x1d, 0x86, 0x1d, 0x87, 0x1d, 0x88, 0x1d, 0x89, 0x1d, 0x8a, 0x1d, 0x8b, 0x1d, + 0x8c, 0x1d, 0x8d, 0x1d, 0x8e, 0x1d, 0x8f, 0x1d, 0x90, 0x1d, 0x91, 0x1d, 0x92, 0x1d, 0x93, 0x1d, + 0x94, 0x1d, 0x95, 0x1d, 0x96, 0x1d, 0x97, 0x1d, 0x98, 0x1d, 0x99, 0x1d, 0x9a, 0x1d, 0x9b, 0x1d, + 0x9c, 0x1d, 0x9d, 0x1d, 0x9e, 0x1d, 0x9f, 0x1d, 0xa0, 0x1d, 0xa1, 0x1d, 0xa2, 0x1d, 0xa3, 0x1d, + 0xa4, 0x1d, 0xa5, 0x1d, 0xa6, 0x1d, 0xa7, 0x1d, 0xa8, 0x1d, 0xa9, 0x1d, 0xaa, 0x1d, 0xab, 0x1d, + 0xac, 0x1d, 0xad, 0x1d, 0xae, 0x1d, 0xaf, 0x1d, 0xb0, 0x1d, 0xb1, 0x1d, 0xb2, 0x1d, 0xb3, 0x1d, + 0xb4, 0x1d, 0xb5, 0x1d, 0xb6, 0x1d, 0xb7, 0x1d, 0xb8, 0x1d, 0xb9, 0x1d, 0xba, 0x1d, 0xbb, 0x1d, + 0xbc, 0x1d, 0xbd, 0x1d, 0xbe, 0x1d, 0xbf, 0x1d, 0xc0, 0x1d, 0xc1, 0x1d, 0xc2, 0x1d, 0xc3, 0x1d, + 0xc4, 0x1d, 0xc5, 0x1d, 0xc6, 0x1d, 0xc7, 0x1d, 0xc8, 0x1d, 0xc9, 0x1d, 0xca, 0x1d, 0xcb, 0x1d, + 0xcc, 0x1d, 0xcd, 0x1d, 0xce, 0x1d, 0xcf, 0x1d, 0xd0, 0x1d, 0xd1, 0x1d, 0xd2, 0x1d, 0xd3, 0x1d, + 0xd4, 0x1d, 0xd5, 0x1d, 0xd6, 0x1d, 0xd7, 0x1d, 0xd8, 0x1d, 0xd9, 0x1d, 0xda, 0x1d, 0xdb, 0x1d, + 0xdc, 0x1d, 0xdd, 0x1d, 0xde, 0x1d, 0xdf, 0x1d, 0xe0, 0x1d, 0xe1, 0x1d, 0xe2, 0x1d, 0xe3, 0x1d, + 0xe4, 0x1d, 0xe5, 0x1d, 0xe6, 0x1d, 0xe7, 0x1d, 0xe8, 0x1d, 0xe9, 0x1d, 0xea, 0x1d, 0xeb, 0x1d, + 0xec, 0x1d, 0xed, 0x1d, 0xee, 0x1d, 0xef, 0x1d, 0xf0, 0x1d, 0xf1, 0x1d, 0xf2, 0x1d, 0xf3, 0x1d, + + /* Sector 7 */ + + 0xf4, 0x1d, 0xf5, 0x1d, 0xf6, 0x1d, 0xf7, 0x1d, 0xf8, 0x1d, 0xf9, 0x1d, 0xfa, 0x1d, 0xfb, 0x1d, + 0xfc, 0x1d, 0xfd, 0x1d, 0xfe, 0x1d, 0xff, 0x1d, 0x00, 0x1e, 0x00, 0x1e, 0x02, 0x1e, 0x02, 0x1e, + 0x04, 0x1e, 0x04, 0x1e, 0x06, 0x1e, 0x06, 0x1e, 0x08, 0x1e, 0x08, 0x1e, 0x0a, 0x1e, 0x0a, 0x1e, + 0x0c, 0x1e, 0x0c, 0x1e, 0x0e, 0x1e, 0x0e, 0x1e, 0x10, 0x1e, 0x10, 0x1e, 0x12, 0x1e, 0x12, 0x1e, + 0x14, 0x1e, 0x14, 0x1e, 0x16, 0x1e, 0x16, 0x1e, 0x18, 0x1e, 0x18, 0x1e, 0x1a, 0x1e, 0x1a, 0x1e, + 0x1c, 0x1e, 0x1c, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x20, 0x1e, 0x20, 0x1e, 0x22, 0x1e, 0x22, 0x1e, + 0x24, 0x1e, 0x24, 0x1e, 0x26, 0x1e, 0x26, 0x1e, 0x28, 0x1e, 0x28, 0x1e, 0x2a, 0x1e, 0x2a, 0x1e, + 0x2c, 0x1e, 0x2c, 0x1e, 0x2e, 0x1e, 0x2e, 0x1e, 0x30, 0x1e, 0x30, 0x1e, 0x32, 0x1e, 0x32, 0x1e, + 0x34, 0x1e, 0x34, 0x1e, 0x36, 0x1e, 0x36, 0x1e, 0x38, 0x1e, 0x38, 0x1e, 0x3a, 0x1e, 0x3a, 0x1e, + 0x3c, 0x1e, 0x3c, 0x1e, 0x3e, 0x1e, 0x3e, 0x1e, 0x40, 0x1e, 0x40, 0x1e, 0x42, 0x1e, 0x42, 0x1e, + 0x44, 0x1e, 0x44, 0x1e, 0x46, 0x1e, 0x46, 0x1e, 0x48, 0x1e, 0x48, 0x1e, 0x4a, 0x1e, 0x4a, 0x1e, + 0x4c, 0x1e, 0x4c, 0x1e, 0x4e, 0x1e, 0x4e, 0x1e, 0x50, 0x1e, 0x50, 0x1e, 0x52, 0x1e, 0x52, 0x1e, + 0x54, 0x1e, 0x54, 0x1e, 0x56, 0x1e, 0x56, 0x1e, 0x58, 0x1e, 0x58, 0x1e, 0x5a, 0x1e, 0x5a, 0x1e, + 0x5c, 0x1e, 0x5c, 0x1e, 0x5e, 0x1e, 0x5e, 0x1e, 0x60, 0x1e, 0x60, 0x1e, 0x62, 0x1e, 0x62, 0x1e, + 0x64, 0x1e, 0x64, 0x1e, 0x66, 0x1e, 0x66, 0x1e, 0x68, 0x1e, 0x68, 0x1e, 0x6a, 0x1e, 0x6a, 0x1e, + 0x6c, 0x1e, 0x6c, 0x1e, 0x6e, 0x1e, 0x6e, 0x1e, 0x70, 0x1e, 0x70, 0x1e, 0x72, 0x1e, 0x72, 0x1e, + 0x74, 0x1e, 0x74, 0x1e, 0x76, 0x1e, 0x76, 0x1e, 0x78, 0x1e, 0x78, 0x1e, 0x7a, 0x1e, 0x7a, 0x1e, + 0x7c, 0x1e, 0x7c, 0x1e, 0x7e, 0x1e, 0x7e, 0x1e, 0x80, 0x1e, 0x80, 0x1e, 0x82, 0x1e, 0x82, 0x1e, + 0x84, 0x1e, 0x84, 0x1e, 0x86, 0x1e, 0x86, 0x1e, 0x88, 0x1e, 0x88, 0x1e, 0x8a, 0x1e, 0x8a, 0x1e, + 0x8c, 0x1e, 0x8c, 0x1e, 0x8e, 0x1e, 0x8e, 0x1e, 0x90, 0x1e, 0x90, 0x1e, 0x92, 0x1e, 0x92, 0x1e, + 0x94, 0x1e, 0x94, 0x1e, 0x96, 0x1e, 0x97, 0x1e, 0x98, 0x1e, 0x99, 0x1e, 0x9a, 0x1e, 0x9b, 0x1e, + 0x9c, 0x1e, 0x9d, 0x1e, 0x9e, 0x1e, 0x9f, 0x1e, 0xa0, 0x1e, 0xa0, 0x1e, 0xa2, 0x1e, 0xa2, 0x1e, + 0xa4, 0x1e, 0xa4, 0x1e, 0xa6, 0x1e, 0xa6, 0x1e, 0xa8, 0x1e, 0xa8, 0x1e, 0xaa, 0x1e, 0xaa, 0x1e, + 0xac, 0x1e, 0xac, 0x1e, 0xae, 0x1e, 0xae, 0x1e, 0xb0, 0x1e, 0xb0, 0x1e, 0xb2, 0x1e, 0xb2, 0x1e, + 0xb4, 0x1e, 0xb4, 0x1e, 0xb6, 0x1e, 0xb6, 0x1e, 0xb8, 0x1e, 0xb8, 0x1e, 0xba, 0x1e, 0xba, 0x1e, + 0xbc, 0x1e, 0xbc, 0x1e, 0xbe, 0x1e, 0xbe, 0x1e, 0xc0, 0x1e, 0xc0, 0x1e, 0xc2, 0x1e, 0xc2, 0x1e, + 0xc4, 0x1e, 0xc4, 0x1e, 0xc6, 0x1e, 0xc6, 0x1e, 0xc8, 0x1e, 0xc8, 0x1e, 0xca, 0x1e, 0xca, 0x1e, + 0xcc, 0x1e, 0xcc, 0x1e, 0xce, 0x1e, 0xce, 0x1e, 0xd0, 0x1e, 0xd0, 0x1e, 0xd2, 0x1e, 0xd2, 0x1e, + 0xd4, 0x1e, 0xd4, 0x1e, 0xd6, 0x1e, 0xd6, 0x1e, 0xd8, 0x1e, 0xd8, 0x1e, 0xda, 0x1e, 0xda, 0x1e, + 0xdc, 0x1e, 0xdc, 0x1e, 0xde, 0x1e, 0xde, 0x1e, 0xe0, 0x1e, 0xe0, 0x1e, 0xe2, 0x1e, 0xe2, 0x1e, + 0xe4, 0x1e, 0xe4, 0x1e, 0xe6, 0x1e, 0xe6, 0x1e, 0xe8, 0x1e, 0xe8, 0x1e, 0xea, 0x1e, 0xea, 0x1e, + 0xec, 0x1e, 0xec, 0x1e, 0xee, 0x1e, 0xee, 0x1e, 0xf0, 0x1e, 0xf0, 0x1e, 0xf2, 0x1e, 0xf2, 0x1e, + + /* Sector 8 */ + + 0xf4, 0x1e, 0xf4, 0x1e, 0xf6, 0x1e, 0xf6, 0x1e, 0xf8, 0x1e, 0xf8, 0x1e, 0xfa, 0x1e, 0xfb, 0x1e, + 0xfc, 0x1e, 0xfd, 0x1e, 0xfe, 0x1e, 0xff, 0x1e, 0x08, 0x1f, 0x09, 0x1f, 0x0a, 0x1f, 0x0b, 0x1f, + 0x0c, 0x1f, 0x0d, 0x1f, 0x0e, 0x1f, 0x0f, 0x1f, 0x08, 0x1f, 0x09, 0x1f, 0x0a, 0x1f, 0x0b, 0x1f, + 0x0c, 0x1f, 0x0d, 0x1f, 0x0e, 0x1f, 0x0f, 0x1f, 0x18, 0x1f, 0x19, 0x1f, 0x1a, 0x1f, 0x1b, 0x1f, + 0x1c, 0x1f, 0x1d, 0x1f, 0x16, 0x1f, 0x17, 0x1f, 0x18, 0x1f, 0x19, 0x1f, 0x1a, 0x1f, 0x1b, 0x1f, + 0x1c, 0x1f, 0x1d, 0x1f, 0x1e, 0x1f, 0x1f, 0x1f, 0x28, 0x1f, 0x29, 0x1f, 0x2a, 0x1f, 0x2b, 0x1f, + 0x2c, 0x1f, 0x2d, 0x1f, 0x2e, 0x1f, 0x2f, 0x1f, 0x28, 0x1f, 0x29, 0x1f, 0x2a, 0x1f, 0x2b, 0x1f, + 0x2c, 0x1f, 0x2d, 0x1f, 0x2e, 0x1f, 0x2f, 0x1f, 0x38, 0x1f, 0x39, 0x1f, 0x3a, 0x1f, 0x3b, 0x1f, + 0x3c, 0x1f, 0x3d, 0x1f, 0x3e, 0x1f, 0x3f, 0x1f, 0x38, 0x1f, 0x39, 0x1f, 0x3a, 0x1f, 0x3b, 0x1f, + 0x3c, 0x1f, 0x3d, 0x1f, 0x3e, 0x1f, 0x3f, 0x1f, 0x48, 0x1f, 0x49, 0x1f, 0x4a, 0x1f, 0x4b, 0x1f, + 0x4c, 0x1f, 0x4d, 0x1f, 0x46, 0x1f, 0x47, 0x1f, 0x48, 0x1f, 0x49, 0x1f, 0x4a, 0x1f, 0x4b, 0x1f, + 0x4c, 0x1f, 0x4d, 0x1f, 0x4e, 0x1f, 0x4f, 0x1f, 0x50, 0x1f, 0x59, 0x1f, 0x52, 0x1f, 0x5b, 0x1f, + 0x54, 0x1f, 0x5d, 0x1f, 0x56, 0x1f, 0x5f, 0x1f, 0x58, 0x1f, 0x59, 0x1f, 0x5a, 0x1f, 0x5b, 0x1f, + 0x5c, 0x1f, 0x5d, 0x1f, 0x5e, 0x1f, 0x5f, 0x1f, 0x68, 0x1f, 0x69, 0x1f, 0x6a, 0x1f, 0x6b, 0x1f, + 0x6c, 0x1f, 0x6d, 0x1f, 0x6e, 0x1f, 0x6f, 0x1f, 0x68, 0x1f, 0x69, 0x1f, 0x6a, 0x1f, 0x6b, 0x1f, + 0x6c, 0x1f, 0x6d, 0x1f, 0x6e, 0x1f, 0x6f, 0x1f, 0xba, 0x1f, 0xbb, 0x1f, 0xc8, 0x1f, 0xc9, 0x1f, + 0xca, 0x1f, 0xcb, 0x1f, 0xda, 0x1f, 0xdb, 0x1f, 0xf8, 0x1f, 0xf9, 0x1f, 0xea, 0x1f, 0xeb, 0x1f, + 0xfa, 0x1f, 0xfb, 0x1f, 0x7e, 0x1f, 0x7f, 0x1f, 0x88, 0x1f, 0x89, 0x1f, 0x8a, 0x1f, 0x8b, 0x1f, + 0x8c, 0x1f, 0x8d, 0x1f, 0x8e, 0x1f, 0x8f, 0x1f, 0x88, 0x1f, 0x89, 0x1f, 0x8a, 0x1f, 0x8b, 0x1f, + 0x8c, 0x1f, 0x8d, 0x1f, 0x8e, 0x1f, 0x8f, 0x1f, 0x98, 0x1f, 0x99, 0x1f, 0x9a, 0x1f, 0x9b, 0x1f, + 0x9c, 0x1f, 0x9d, 0x1f, 0x9e, 0x1f, 0x9f, 0x1f, 0x98, 0x1f, 0x99, 0x1f, 0x9a, 0x1f, 0x9b, 0x1f, + 0x9c, 0x1f, 0x9d, 0x1f, 0x9e, 0x1f, 0x9f, 0x1f, 0xa8, 0x1f, 0xa9, 0x1f, 0xaa, 0x1f, 0xab, 0x1f, + 0xac, 0x1f, 0xad, 0x1f, 0xae, 0x1f, 0xaf, 0x1f, 0xa8, 0x1f, 0xa9, 0x1f, 0xaa, 0x1f, 0xab, 0x1f, + 0xac, 0x1f, 0xad, 0x1f, 0xae, 0x1f, 0xaf, 0x1f, 0xb8, 0x1f, 0xb9, 0x1f, 0xb2, 0x1f, 0xbc, 0x1f, + 0xb4, 0x1f, 0xb5, 0x1f, 0xb6, 0x1f, 0xb7, 0x1f, 0xb8, 0x1f, 0xb9, 0x1f, 0xba, 0x1f, 0xbb, 0x1f, + 0xbc, 0x1f, 0xbd, 0x1f, 0xbe, 0x1f, 0xbf, 0x1f, 0xc0, 0x1f, 0xc1, 0x1f, 0xc2, 0x1f, 0xc3, 0x1f, + 0xc4, 0x1f, 0xc5, 0x1f, 0xc6, 0x1f, 0xc7, 0x1f, 0xc8, 0x1f, 0xc9, 0x1f, 0xca, 0x1f, 0xcb, 0x1f, + 0xc3, 0x1f, 0xcd, 0x1f, 0xce, 0x1f, 0xcf, 0x1f, 0xd8, 0x1f, 0xd9, 0x1f, 0xd2, 0x1f, 0xd3, 0x1f, + 0xd4, 0x1f, 0xd5, 0x1f, 0xd6, 0x1f, 0xd7, 0x1f, 0xd8, 0x1f, 0xd9, 0x1f, 0xda, 0x1f, 0xdb, 0x1f, + 0xdc, 0x1f, 0xdd, 0x1f, 0xde, 0x1f, 0xdf, 0x1f, 0xe8, 0x1f, 0xe9, 0x1f, 0xe2, 0x1f, 0xe3, 0x1f, + 0xe4, 0x1f, 0xec, 0x1f, 0xe6, 0x1f, 0xe7, 0x1f, 0xe8, 0x1f, 0xe9, 0x1f, 0xea, 0x1f, 0xeb, 0x1f, + 0xec, 0x1f, 0xed, 0x1f, 0xee, 0x1f, 0xef, 0x1f, 0xf0, 0x1f, 0xf1, 0x1f, 0xf2, 0x1f, 0xf3, 0x1f, + + /* Sector 9 */ + + 0xf4, 0x1f, 0xf5, 0x1f, 0xf6, 0x1f, 0xf7, 0x1f, 0xf8, 0x1f, 0xf9, 0x1f, 0xfa, 0x1f, 0xfb, 0x1f, + 0xf3, 0x1f, 0xfd, 0x1f, 0xfe, 0x1f, 0xff, 0x1f, 0x00, 0x20, 0x01, 0x20, 0x02, 0x20, 0x03, 0x20, + 0x04, 0x20, 0x05, 0x20, 0x06, 0x20, 0x07, 0x20, 0x08, 0x20, 0x09, 0x20, 0x0a, 0x20, 0x0b, 0x20, + 0x0c, 0x20, 0x0d, 0x20, 0x0e, 0x20, 0x0f, 0x20, 0x10, 0x20, 0x11, 0x20, 0x12, 0x20, 0x13, 0x20, + 0x14, 0x20, 0x15, 0x20, 0x16, 0x20, 0x17, 0x20, 0x18, 0x20, 0x19, 0x20, 0x1a, 0x20, 0x1b, 0x20, + 0x1c, 0x20, 0x1d, 0x20, 0x1e, 0x20, 0x1f, 0x20, 0x20, 0x20, 0x21, 0x20, 0x22, 0x20, 0x23, 0x20, + 0x24, 0x20, 0x25, 0x20, 0x26, 0x20, 0x27, 0x20, 0x28, 0x20, 0x29, 0x20, 0x2a, 0x20, 0x2b, 0x20, + 0x2c, 0x20, 0x2d, 0x20, 0x2e, 0x20, 0x2f, 0x20, 0x30, 0x20, 0x31, 0x20, 0x32, 0x20, 0x33, 0x20, + 0x34, 0x20, 0x35, 0x20, 0x36, 0x20, 0x37, 0x20, 0x38, 0x20, 0x39, 0x20, 0x3a, 0x20, 0x3b, 0x20, + 0x3c, 0x20, 0x3d, 0x20, 0x3e, 0x20, 0x3f, 0x20, 0x40, 0x20, 0x41, 0x20, 0x42, 0x20, 0x43, 0x20, + 0x44, 0x20, 0x45, 0x20, 0x46, 0x20, 0x47, 0x20, 0x48, 0x20, 0x49, 0x20, 0x4a, 0x20, 0x4b, 0x20, + 0x4c, 0x20, 0x4d, 0x20, 0x4e, 0x20, 0x4f, 0x20, 0x50, 0x20, 0x51, 0x20, 0x52, 0x20, 0x53, 0x20, + 0x54, 0x20, 0x55, 0x20, 0x56, 0x20, 0x57, 0x20, 0x58, 0x20, 0x59, 0x20, 0x5a, 0x20, 0x5b, 0x20, + 0x5c, 0x20, 0x5d, 0x20, 0x5e, 0x20, 0x5f, 0x20, 0x60, 0x20, 0x61, 0x20, 0x62, 0x20, 0x63, 0x20, + 0x64, 0x20, 0x65, 0x20, 0x66, 0x20, 0x67, 0x20, 0x68, 0x20, 0x69, 0x20, 0x6a, 0x20, 0x6b, 0x20, + 0x6c, 0x20, 0x6d, 0x20, 0x6e, 0x20, 0x6f, 0x20, 0x70, 0x20, 0x71, 0x20, 0x72, 0x20, 0x73, 0x20, + 0x74, 0x20, 0x75, 0x20, 0x76, 0x20, 0x77, 0x20, 0x78, 0x20, 0x79, 0x20, 0x7a, 0x20, 0x7b, 0x20, + 0x7c, 0x20, 0x7d, 0x20, 0x7e, 0x20, 0x7f, 0x20, 0x80, 0x20, 0x81, 0x20, 0x82, 0x20, 0x83, 0x20, + 0x84, 0x20, 0x85, 0x20, 0x86, 0x20, 0x87, 0x20, 0x88, 0x20, 0x89, 0x20, 0x8a, 0x20, 0x8b, 0x20, + 0x8c, 0x20, 0x8d, 0x20, 0x8e, 0x20, 0x8f, 0x20, 0x90, 0x20, 0x91, 0x20, 0x92, 0x20, 0x93, 0x20, + 0x94, 0x20, 0x95, 0x20, 0x96, 0x20, 0x97, 0x20, 0x98, 0x20, 0x99, 0x20, 0x9a, 0x20, 0x9b, 0x20, + 0x9c, 0x20, 0x9d, 0x20, 0x9e, 0x20, 0x9f, 0x20, 0xa0, 0x20, 0xa1, 0x20, 0xa2, 0x20, 0xa3, 0x20, + 0xa4, 0x20, 0xa5, 0x20, 0xa6, 0x20, 0xa7, 0x20, 0xa8, 0x20, 0xa9, 0x20, 0xaa, 0x20, 0xab, 0x20, + 0xac, 0x20, 0xad, 0x20, 0xae, 0x20, 0xaf, 0x20, 0xb0, 0x20, 0xb1, 0x20, 0xb2, 0x20, 0xb3, 0x20, + 0xb4, 0x20, 0xb5, 0x20, 0xb6, 0x20, 0xb7, 0x20, 0xb8, 0x20, 0xb9, 0x20, 0xba, 0x20, 0xbb, 0x20, + 0xbc, 0x20, 0xbd, 0x20, 0xbe, 0x20, 0xbf, 0x20, 0xc0, 0x20, 0xc1, 0x20, 0xc2, 0x20, 0xc3, 0x20, + 0xc4, 0x20, 0xc5, 0x20, 0xc6, 0x20, 0xc7, 0x20, 0xc8, 0x20, 0xc9, 0x20, 0xca, 0x20, 0xcb, 0x20, + 0xcc, 0x20, 0xcd, 0x20, 0xce, 0x20, 0xcf, 0x20, 0xd0, 0x20, 0xd1, 0x20, 0xd2, 0x20, 0xd3, 0x20, + 0xd4, 0x20, 0xd5, 0x20, 0xd6, 0x20, 0xd7, 0x20, 0xd8, 0x20, 0xd9, 0x20, 0xda, 0x20, 0xdb, 0x20, + 0xdc, 0x20, 0xdd, 0x20, 0xde, 0x20, 0xdf, 0x20, 0xe0, 0x20, 0xe1, 0x20, 0xe2, 0x20, 0xe3, 0x20, + 0xe4, 0x20, 0xe5, 0x20, 0xe6, 0x20, 0xe7, 0x20, 0xe8, 0x20, 0xe9, 0x20, 0xea, 0x20, 0xeb, 0x20, + 0xec, 0x20, 0xed, 0x20, 0xee, 0x20, 0xef, 0x20, 0xf0, 0x20, 0xf1, 0x20, 0xf2, 0x20, 0xf3, 0x20, + + /* Sector 10 */ + + 0xf4, 0x20, 0xf5, 0x20, 0xf6, 0x20, 0xf7, 0x20, 0xf8, 0x20, 0xf9, 0x20, 0xfa, 0x20, 0xfb, 0x20, + 0xfc, 0x20, 0xfd, 0x20, 0xfe, 0x20, 0xff, 0x20, 0x00, 0x21, 0x01, 0x21, 0x02, 0x21, 0x03, 0x21, + 0x04, 0x21, 0x05, 0x21, 0x06, 0x21, 0x07, 0x21, 0x08, 0x21, 0x09, 0x21, 0x0a, 0x21, 0x0b, 0x21, + 0x0c, 0x21, 0x0d, 0x21, 0x0e, 0x21, 0x0f, 0x21, 0x10, 0x21, 0x11, 0x21, 0x12, 0x21, 0x13, 0x21, + 0x14, 0x21, 0x15, 0x21, 0x16, 0x21, 0x17, 0x21, 0x18, 0x21, 0x19, 0x21, 0x1a, 0x21, 0x1b, 0x21, + 0x1c, 0x21, 0x1d, 0x21, 0x1e, 0x21, 0x1f, 0x21, 0x20, 0x21, 0x21, 0x21, 0x22, 0x21, 0x23, 0x21, + 0x24, 0x21, 0x25, 0x21, 0x26, 0x21, 0x27, 0x21, 0x28, 0x21, 0x29, 0x21, 0x2a, 0x21, 0x2b, 0x21, + 0x2c, 0x21, 0x2d, 0x21, 0x2e, 0x21, 0x2f, 0x21, 0x30, 0x21, 0x31, 0x21, 0x32, 0x21, 0x33, 0x21, + 0x34, 0x21, 0x35, 0x21, 0x36, 0x21, 0x37, 0x21, 0x38, 0x21, 0x39, 0x21, 0x3a, 0x21, 0x3b, 0x21, + 0x3c, 0x21, 0x3d, 0x21, 0x3e, 0x21, 0x3f, 0x21, 0x40, 0x21, 0x41, 0x21, 0x42, 0x21, 0x43, 0x21, + 0x44, 0x21, 0x45, 0x21, 0x46, 0x21, 0x47, 0x21, 0x48, 0x21, 0x49, 0x21, 0x4a, 0x21, 0x4b, 0x21, + 0x4c, 0x21, 0x4d, 0x21, 0x32, 0x21, 0x4f, 0x21, 0x50, 0x21, 0x51, 0x21, 0x52, 0x21, 0x53, 0x21, + 0x54, 0x21, 0x55, 0x21, 0x56, 0x21, 0x57, 0x21, 0x58, 0x21, 0x59, 0x21, 0x5a, 0x21, 0x5b, 0x21, + 0x5c, 0x21, 0x5d, 0x21, 0x5e, 0x21, 0x5f, 0x21, 0x60, 0x21, 0x61, 0x21, 0x62, 0x21, 0x63, 0x21, + 0x64, 0x21, 0x65, 0x21, 0x66, 0x21, 0x67, 0x21, 0x68, 0x21, 0x69, 0x21, 0x6a, 0x21, 0x6b, 0x21, + 0x6c, 0x21, 0x6d, 0x21, 0x6e, 0x21, 0x6f, 0x21, 0x60, 0x21, 0x61, 0x21, 0x62, 0x21, 0x63, 0x21, + 0x64, 0x21, 0x65, 0x21, 0x66, 0x21, 0x67, 0x21, 0x68, 0x21, 0x69, 0x21, 0x6a, 0x21, 0x6b, 0x21, + 0x6c, 0x21, 0x6d, 0x21, 0x6e, 0x21, 0x6f, 0x21, 0x80, 0x21, 0x81, 0x21, 0x82, 0x21, 0x83, 0x21, + 0x83, 0x21, 0xff, 0xff, 0x4b, 0x03, 0xb6, 0x24, 0xb7, 0x24, 0xb8, 0x24, 0xb9, 0x24, 0xba, 0x24, + 0xbb, 0x24, 0xbc, 0x24, 0xbd, 0x24, 0xbe, 0x24, 0xbf, 0x24, 0xc0, 0x24, 0xc1, 0x24, 0xc2, 0x24, + 0xc3, 0x24, 0xc4, 0x24, 0xc5, 0x24, 0xc6, 0x24, 0xc7, 0x24, 0xc8, 0x24, 0xc9, 0x24, 0xca, 0x24, + 0xcb, 0x24, 0xcc, 0x24, 0xcd, 0x24, 0xce, 0x24, 0xcf, 0x24, 0xff, 0xff, 0x46, 0x07, 0x00, 0x2c, + 0x01, 0x2c, 0x02, 0x2c, 0x03, 0x2c, 0x04, 0x2c, 0x05, 0x2c, 0x06, 0x2c, 0x07, 0x2c, 0x08, 0x2c, + 0x09, 0x2c, 0x0a, 0x2c, 0x0b, 0x2c, 0x0c, 0x2c, 0x0d, 0x2c, 0x0e, 0x2c, 0x0f, 0x2c, 0x10, 0x2c, + 0x11, 0x2c, 0x12, 0x2c, 0x13, 0x2c, 0x14, 0x2c, 0x15, 0x2c, 0x16, 0x2c, 0x17, 0x2c, 0x18, 0x2c, + 0x19, 0x2c, 0x1a, 0x2c, 0x1b, 0x2c, 0x1c, 0x2c, 0x1d, 0x2c, 0x1e, 0x2c, 0x1f, 0x2c, 0x20, 0x2c, + 0x21, 0x2c, 0x22, 0x2c, 0x23, 0x2c, 0x24, 0x2c, 0x25, 0x2c, 0x26, 0x2c, 0x27, 0x2c, 0x28, 0x2c, + 0x29, 0x2c, 0x2a, 0x2c, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2c, 0x2e, 0x2c, 0x5f, 0x2c, 0x60, 0x2c, + 0x60, 0x2c, 0x62, 0x2c, 0x63, 0x2c, 0x64, 0x2c, 0x65, 0x2c, 0x66, 0x2c, 0x67, 0x2c, 0x67, 0x2c, + 0x69, 0x2c, 0x69, 0x2c, 0x6b, 0x2c, 0x6b, 0x2c, 0x6d, 0x2c, 0x6e, 0x2c, 0x6f, 0x2c, 0x70, 0x2c, + 0x71, 0x2c, 0x72, 0x2c, 0x73, 0x2c, 0x74, 0x2c, 0x75, 0x2c, 0x75, 0x2c, 0x77, 0x2c, 0x78, 0x2c, + 0x79, 0x2c, 0x7a, 0x2c, 0x7b, 0x2c, 0x7c, 0x2c, 0x7d, 0x2c, 0x7e, 0x2c, 0x7f, 0x2c, 0x80, 0x2c, + + /* Sector 11 */ + + 0x80, 0x2c, 0x82, 0x2c, 0x82, 0x2c, 0x84, 0x2c, 0x84, 0x2c, 0x86, 0x2c, 0x86, 0x2c, 0x88, 0x2c, + 0x88, 0x2c, 0x8a, 0x2c, 0x8a, 0x2c, 0x8c, 0x2c, 0x8c, 0x2c, 0x8e, 0x2c, 0x8e, 0x2c, 0x90, 0x2c, + 0x90, 0x2c, 0x92, 0x2c, 0x92, 0x2c, 0x94, 0x2c, 0x94, 0x2c, 0x96, 0x2c, 0x96, 0x2c, 0x98, 0x2c, + 0x98, 0x2c, 0x9a, 0x2c, 0x9a, 0x2c, 0x9c, 0x2c, 0x9c, 0x2c, 0x9e, 0x2c, 0x9e, 0x2c, 0xa0, 0x2c, + 0xa0, 0x2c, 0xa2, 0x2c, 0xa2, 0x2c, 0xa4, 0x2c, 0xa4, 0x2c, 0xa6, 0x2c, 0xa6, 0x2c, 0xa8, 0x2c, + 0xa8, 0x2c, 0xaa, 0x2c, 0xaa, 0x2c, 0xac, 0x2c, 0xac, 0x2c, 0xae, 0x2c, 0xae, 0x2c, 0xb0, 0x2c, + 0xb0, 0x2c, 0xb2, 0x2c, 0xb2, 0x2c, 0xb4, 0x2c, 0xb4, 0x2c, 0xb6, 0x2c, 0xb6, 0x2c, 0xb8, 0x2c, + 0xb8, 0x2c, 0xba, 0x2c, 0xba, 0x2c, 0xbc, 0x2c, 0xbc, 0x2c, 0xbe, 0x2c, 0xbe, 0x2c, 0xc0, 0x2c, + 0xc0, 0x2c, 0xc2, 0x2c, 0xc2, 0x2c, 0xc4, 0x2c, 0xc4, 0x2c, 0xc6, 0x2c, 0xc6, 0x2c, 0xc8, 0x2c, + 0xc8, 0x2c, 0xca, 0x2c, 0xca, 0x2c, 0xcc, 0x2c, 0xcc, 0x2c, 0xce, 0x2c, 0xce, 0x2c, 0xd0, 0x2c, + 0xd0, 0x2c, 0xd2, 0x2c, 0xd2, 0x2c, 0xd4, 0x2c, 0xd4, 0x2c, 0xd6, 0x2c, 0xd6, 0x2c, 0xd8, 0x2c, + 0xd8, 0x2c, 0xda, 0x2c, 0xda, 0x2c, 0xdc, 0x2c, 0xdc, 0x2c, 0xde, 0x2c, 0xde, 0x2c, 0xe0, 0x2c, + 0xe0, 0x2c, 0xe2, 0x2c, 0xe2, 0x2c, 0xe4, 0x2c, 0xe5, 0x2c, 0xe6, 0x2c, 0xe7, 0x2c, 0xe8, 0x2c, + 0xe9, 0x2c, 0xea, 0x2c, 0xeb, 0x2c, 0xec, 0x2c, 0xed, 0x2c, 0xee, 0x2c, 0xef, 0x2c, 0xf0, 0x2c, + 0xf1, 0x2c, 0xf2, 0x2c, 0xf3, 0x2c, 0xf4, 0x2c, 0xf5, 0x2c, 0xf6, 0x2c, 0xf7, 0x2c, 0xf8, 0x2c, + 0xf9, 0x2c, 0xfa, 0x2c, 0xfb, 0x2c, 0xfc, 0x2c, 0xfd, 0x2c, 0xfe, 0x2c, 0xff, 0x2c, 0xa0, 0x10, + 0xa1, 0x10, 0xa2, 0x10, 0xa3, 0x10, 0xa4, 0x10, 0xa5, 0x10, 0xa6, 0x10, 0xa7, 0x10, 0xa8, 0x10, + 0xa9, 0x10, 0xaa, 0x10, 0xab, 0x10, 0xac, 0x10, 0xad, 0x10, 0xae, 0x10, 0xaf, 0x10, 0xb0, 0x10, + 0xb1, 0x10, 0xb2, 0x10, 0xb3, 0x10, 0xb4, 0x10, 0xb5, 0x10, 0xb6, 0x10, 0xb7, 0x10, 0xb8, 0x10, + 0xb9, 0x10, 0xba, 0x10, 0xbb, 0x10, 0xbc, 0x10, 0xbd, 0x10, 0xbe, 0x10, 0xbf, 0x10, 0xc0, 0x10, + 0xc1, 0x10, 0xc2, 0x10, 0xc3, 0x10, 0xc4, 0x10, 0xc5, 0x10, 0xff, 0xff, 0x1b, 0xd2, 0x21, 0xff, + 0x22, 0xff, 0x23, 0xff, 0x24, 0xff, 0x25, 0xff, 0x26, 0xff, 0x27, 0xff, 0x28, 0xff, 0x29, 0xff, + 0x2a, 0xff, 0x2b, 0xff, 0x2c, 0xff, 0x2d, 0xff, 0x2e, 0xff, 0x2f, 0xff, 0x30, 0xff, 0x31, 0xff, + 0x32, 0xff, 0x33, 0xff, 0x34, 0xff, 0x35, 0xff, 0x36, 0xff, 0x37, 0xff, 0x38, 0xff, 0x39, 0xff, + 0x3a, 0xff, 0x5b, 0xff, 0x5c, 0xff, 0x5d, 0xff, 0x5e, 0xff, 0x5f, 0xff, 0x60, 0xff, 0x61, 0xff, + 0x62, 0xff, 0x63, 0xff, 0x64, 0xff, 0x65, 0xff, 0x66, 0xff, 0x67, 0xff, 0x68, 0xff, 0x69, 0xff, + 0x6a, 0xff, 0x6b, 0xff, 0x6c, 0xff, 0x6d, 0xff, 0x6e, 0xff, 0x6f, 0xff, 0x70, 0xff, 0x71, 0xff, + 0x72, 0xff, 0x73, 0xff, 0x74, 0xff, 0x75, 0xff, 0x76, 0xff, 0x77, 0xff, 0x78, 0xff, 0x79, 0xff, + 0x7a, 0xff, 0x7b, 0xff, 0x7c, 0xff, 0x7d, 0xff, 0x7e, 0xff, 0x7f, 0xff, 0x80, 0xff, 0x81, 0xff, + 0x82, 0xff, 0x83, 0xff, 0x84, 0xff, 0x85, 0xff, 0x86, 0xff, 0x87, 0xff, 0x88, 0xff, 0x89, 0xff, + 0x8a, 0xff, 0x8b, 0xff, 0x8c, 0xff, 0x8d, 0xff, 0x8e, 0xff, 0x8f, 0xff, 0x90, 0xff, 0x91, 0xff, + 0x92, 0xff, 0x93, 0xff, 0x94, 0xff, 0x95, 0xff, 0x96, 0xff, 0x97, 0xff, 0x98, 0xff, 0x99, 0xff, + + /* Sector 12 */ + + 0x9a, 0xff, 0x9b, 0xff, 0x9c, 0xff, 0x9d, 0xff, 0x9e, 0xff, 0x9f, 0xff, 0xa0, 0xff, 0xa1, 0xff, + 0xa2, 0xff, 0xa3, 0xff, 0xa4, 0xff, 0xa5, 0xff, 0xa6, 0xff, 0xa7, 0xff, 0xa8, 0xff, 0xa9, 0xff, + 0xaa, 0xff, 0xab, 0xff, 0xac, 0xff, 0xad, 0xff, 0xae, 0xff, 0xaf, 0xff, 0xb0, 0xff, 0xb1, 0xff, + 0xb2, 0xff, 0xb3, 0xff, 0xb4, 0xff, 0xb5, 0xff, 0xb6, 0xff, 0xb7, 0xff, 0xb8, 0xff, 0xb9, 0xff, + 0xba, 0xff, 0xbb, 0xff, 0xbc, 0xff, 0xbd, 0xff, 0xbe, 0xff, 0xbf, 0xff, 0xc0, 0xff, 0xc1, 0xff, + 0xc2, 0xff, 0xc3, 0xff, 0xc4, 0xff, 0xc5, 0xff, 0xc6, 0xff, 0xc7, 0xff, 0xc8, 0xff, 0xc9, 0xff, + 0xca, 0xff, 0xcb, 0xff, 0xcc, 0xff, 0xcd, 0xff, 0xce, 0xff, 0xcf, 0xff, 0xd0, 0xff, 0xd1, 0xff, + 0xd2, 0xff, 0xd3, 0xff, 0xd4, 0xff, 0xd5, 0xff, 0xd6, 0xff, 0xd7, 0xff, 0xd8, 0xff, 0xd9, 0xff, + 0xda, 0xff, 0xdb, 0xff, 0xdc, 0xff, 0xdd, 0xff, 0xde, 0xff, 0xdf, 0xff, 0xe0, 0xff, 0xe1, 0xff, + 0xe2, 0xff, 0xe3, 0xff, 0xe4, 0xff, 0xe5, 0xff, 0xe6, 0xff, 0xe7, 0xff, 0xe8, 0xff, 0xe9, 0xff, + 0xea, 0xff, 0xeb, 0xff, 0xec, 0xff, 0xed, 0xff, 0xee, 0xff, 0xef, 0xff, 0xf0, 0xff, 0xf1, 0xff, + 0xf2, 0xff, 0xf3, 0xff, 0xf4, 0xff, 0xf5, 0xff, 0xf6, 0xff, 0xf7, 0xff, 0xf8, 0xff, 0xf9, 0xff, + 0xfa, 0xff, 0xfb, 0xff, 0xfc, 0xff, 0xfd, 0xff, 0xfe, 0xff, 0xff, 0xff +}; + + +const ULONG UpCaseTableCheckSum = 0xE619D30D; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_exFAT_format PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function formats the media with exFAT file system with raw */ +/* calls to the I/O driver. It can and must be called before the */ +/* fx_media_open and is designed to utilize the same underlying */ +/* FileX driver. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media control block*/ +/* (does not need to be opened)*/ +/* driver Pointer to FileX driver (must */ +/* be able to field requests */ +/* prior to opening) */ +/* driver_info_ptr Optional information pointer */ +/* memory_ptr Pointer to memory used by the */ +/* FileX for this media. */ +/* memory_size Size of media memory - must */ +/* at least 512 bytes and */ +/* one sector size. */ +/* volume_name Name of the volume */ +/* number_of_fats Number of FAT tables */ +/* hidden_sectors Number of hidden sectors */ +/* total_sectors Total number of sectors */ +/* bytes_per_sector Number of bytes per sector */ +/* sectors_per_cluster Number of sectors per cluster */ +/* volume_serial_number Volume Serial Number */ +/* boundary_unit Data area alignment in sectors*/ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* Media driver */ +/* _fx_utility_exFAT_size_calculate Calculate FAT size */ +/* _fx_utility_exFAT_system_sector_write Write a format sector */ +/* _fx_utility_exFAT_system_area_format Format the exFAT system area */ +/* _fx_utility_exFAT_system_area_checksum_write */ +/* Write the checksum */ +/* _fx_utility_memory_set Set memory */ +/* _fx_utility_memory_copy Copy memory */ +/* _fx_utility_16_unsigned_write Write 16-bit unsigned */ +/* _fx_utility_32_unsigned_write Write 32-bit unsigned */ +/* _fx_utility_64_unsigned_write Write 64-bit unsigned */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), removed */ +/* fixed sector size in exFAT, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_media_exFAT_format(FX_MEDIA *media_ptr, + VOID (*driver)(FX_MEDIA *media), + VOID *driver_info_ptr, + UCHAR *memory_ptr, + UINT memory_size, + CHAR *volume_name, + UINT number_of_fats, + ULONG64 hidden_sectors, + ULONG64 total_sectors, + UINT bytes_per_sector, + UINT sectors_per_cluster, + UINT volume_serial_number, + UINT boundary_unit) +{ + +UCHAR *byte_ptr; +UCHAR jump_boot[] = {0xEB, 0x76, 0x90}; +UCHAR file_system_name[] = {'E', 'X', 'F', 'A', 'T', 0x20, 0x20, 0x20}; +UCHAR fat_init_mask[] = {0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}; +ULONG i; +ULONG sector_offset; +ULONG fat_offset; +ULONG sectors_per_fat; +ULONG cluster_heap_offset; +ULONG cluster_count; +ULONG root_dir_entry_first_sector; +ULONG root_dir_entry_first_cluster; +CHAR bytes_per_sector_shift; +CHAR sector_per_cluster_shift; +ULONG bitmap_size_in_bytes; +ULONG bitmap_size_in_clusters; +ULONG upcase_table_size_in_bytes; +ULONG upcase_table_size_in_clusters; +ULONG upcase_table_checksum = 0; +ULONG system_area_checksum = 0; +ULONG offset; +UINT status; + + + /* This parameter has not been supported yet. */ + FX_PARAMETER_NOT_USED(number_of_fats); + + /* Validate bytes per sector value: no more than 4096. */ + if(bytes_per_sector > 4096) + return(FX_SECTOR_INVALID); + + /* Validate bytes per cluster value: no more than 32MB */ + if((bytes_per_sector * sectors_per_cluster) > (1 << 25)) + return(FX_SECTOR_INVALID); + + /* Validate bytes per sector value: no more than bitmap cache size */ + if (bytes_per_sector > sizeof(media_ptr -> fx_media_exfat_bitmap_cache)) + { + return(FX_NOT_ENOUGH_MEMORY); + } + + /* Create & write bootrecord from drive geometry information. */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_FORMAT, media_ptr, hidden_sectors, total_sectors, sectors_per_cluster, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Setup driver pointer and memory information. */ + media_ptr -> fx_media_driver_entry = driver; + media_ptr -> fx_media_memory_buffer = (UCHAR *)memory_ptr; + media_ptr -> fx_media_memory_size = memory_size; + + /* Store geometry information in media record - driver needs this. */ + media_ptr -> fx_media_bytes_per_sector = bytes_per_sector; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_hidden_sectors = hidden_sectors; +#else + media_ptr -> fx_media_hidden_sectors = (ULONG)hidden_sectors; +#endif + /* Initialize the supplied media I/O driver. First, build the + initialize driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_INIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_info = driver_info_ptr; + media_ptr -> fx_media_driver_write_protect = FX_FALSE; + media_ptr -> fx_media_driver_free_sector_update = FX_FALSE; + media_ptr -> fx_media_driver_data_sector_read = FX_FALSE; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_INIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the initialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the I/O driver initialized successfully. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Return the driver error status. */ + return(FX_IO_ERROR); + } + + /* Setup driver buffer memory. */ + media_ptr -> fx_media_driver_buffer = memory_ptr; + + /* Move the buffer pointer into a local copy. */ + byte_ptr = media_ptr -> fx_media_driver_buffer; + + /* If the boundary unit is zero, set it to default value. */ + if (boundary_unit == 0) + { + + /* Set the boundary unit to default value. */ + boundary_unit = EXFAT_DEFAULT_BOUNDARY_UNIT; + } + + /* Recalculate FAT size/cluster heap offset according Incoming values. */ + _fx_utility_exFAT_size_calculate(bytes_per_sector, + boundary_unit, + total_sectors, + sectors_per_cluster, + §ors_per_fat, + &fat_offset, + &cluster_heap_offset); + + /* Fill Boot Sector fields. */ + + /* Clear work buffer. */ + _fx_utility_memory_set(byte_ptr, 0x00, media_ptr -> fx_media_bytes_per_sector); + + _fx_utility_memory_copy((UCHAR *)jump_boot, /* Use case of memcpy is verified. */ + &byte_ptr[FX_JUMP_INSTR], + sizeof(jump_boot)); + + _fx_utility_memory_copy((UCHAR *)file_system_name, /* Use case of memcpy is verified. */ + &byte_ptr[FX_OEM_NAME], + sizeof(file_system_name)); + + _fx_utility_64_unsigned_write(&byte_ptr[FX_EF_PARTITION_OFFSET], + hidden_sectors); + + _fx_utility_64_unsigned_write(&byte_ptr[FX_EF_VOLUME_LENGTH], + total_sectors); + + _fx_utility_32_unsigned_write(&byte_ptr[FX_EF_FAT_OFFSET], + fat_offset); + + _fx_utility_32_unsigned_write(&byte_ptr[FX_EF_FAT_LENGTH], + sectors_per_fat); + + _fx_utility_32_unsigned_write(&byte_ptr[FX_EF_CLUSTER_HEAP_OFFSET], + cluster_heap_offset); + + /* Calculate total number of Clusters. */ + cluster_count = (ULONG)((total_sectors - cluster_heap_offset) / + sectors_per_cluster); + + _fx_utility_32_unsigned_write(&byte_ptr[FX_EF_CLUSTER_COUNT], + cluster_count); + + _fx_utility_32_unsigned_write(&byte_ptr[FX_EF_VOLUME_SERIAL_NUMBER], + volume_serial_number); + + _fx_utility_16_unsigned_write(&byte_ptr[FX_EF_FILE_SYSTEM_REVISION], + (USHORT)EXFAT_FAT_FILE_SYS_REVISION); + + _fx_utility_16_unsigned_write(&byte_ptr[FX_EF_VOLUME_FLAGS], + (USHORT)EXFAT_FAT_VOLUME_FLAG); + + /* Calculate Bytes Per Sector Shift value. */ + i = bytes_per_sector; + bytes_per_sector_shift = 0; + + /* Loop to count the shift value. If the LSB is set, we got the shift value. */ + while (0 == (i & 0x01)) + { + + /* Add the shift value. */ + bytes_per_sector_shift++; + + /* Right shift by 1 position. */ + i >>= 1; + } + + byte_ptr[FX_EF_BYTE_PER_SECTOR_SHIFT] = (UCHAR)bytes_per_sector_shift; + + /* Calculate Sector Per Cluster Shift value. */ + i = sectors_per_cluster; + sector_per_cluster_shift = 0; + + /* Loop to count the shift value. If the LSB is set, we got the shift value. */ + while (0 == (i & 0x01)) + { + + /* Add the shift value. */ + sector_per_cluster_shift++; + + /* Right shift by 1 position. */ + i >>= 1; + } + + /* Write SectorsPerClusterShift, NumberOfFats, DriveSelect and PercentInUse fields. */ + byte_ptr[FX_EF_SECTOR_PER_CLUSTER_SHIFT] = (UCHAR)sector_per_cluster_shift; + byte_ptr[FX_EF_NUMBER_OF_FATS] = EXFAT_FAT_NUM_OF_FATS; + byte_ptr[FX_EF_DRIVE_SELECT] = EXFAT_FAT_DRIVE_SELECT; + byte_ptr[FX_EF_PERCENT_IN_USE] = 0; + + /* Write Boot Sector Signature. */ + byte_ptr[FX_SIG_OFFSET + 0] = FX_SIG_BYTE_1; + byte_ptr[FX_SIG_OFFSET + 1] = FX_SIG_BYTE_2; + + /* Calculate exFAT Bit Map and UpCase tables geometry + and first Cluster of Root Dir Entry. */ + bitmap_size_in_bytes = DIVIDE_TO_CEILING(cluster_count, BITS_PER_BYTE); + + /* Calculate Bit Map Size in sectors. */ + bitmap_size_in_clusters = DIVIDE_TO_CEILING(bitmap_size_in_bytes, media_ptr -> fx_media_bytes_per_sector); + + /* Calculate Bit Map size in clusters. */ + bitmap_size_in_clusters = DIVIDE_TO_CEILING(bitmap_size_in_clusters, sectors_per_cluster); + + /* Calculate UpCase Table Size in bytes. */ + upcase_table_size_in_bytes = sizeof(_fx_utility_exFAT_upcase_table_compressed); + + /* Calculate UpCase Table size sectors. */ + upcase_table_size_in_clusters = DIVIDE_TO_CEILING(upcase_table_size_in_bytes, media_ptr -> fx_media_bytes_per_sector); + + /* Calculate UpCase size in clusters. */ + upcase_table_size_in_clusters = DIVIDE_TO_CEILING(upcase_table_size_in_clusters, sectors_per_cluster); + + /* Determine first Root Dir Entry cluster. */ + root_dir_entry_first_cluster = (UINT)(bitmap_size_in_clusters + + upcase_table_size_in_clusters + + FX_FAT_ENTRY_START); + + /* Determine the first sector for the root directory entry. */ + root_dir_entry_first_sector = cluster_heap_offset + + ((root_dir_entry_first_cluster - FX_FAT_ENTRY_START) << + sector_per_cluster_shift); + + /* Fill FirstClusterOfRootDirectory field. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_EF_FIRST_CLUSTER_OF_ROOT_DIR], + root_dir_entry_first_cluster); + + /* Calculate Boot Sector checksum. */ + for (i = 0; i < media_ptr -> fx_media_bytes_per_sector; i++) + { + + /* Skip VolumeFlags and PercentInUse fields. */ + if ((FX_EF_VOLUME_FLAGS == i) || + (FX_EF_VOLUME_FLAGS + 1 == i) || + (FX_EF_PERCENT_IN_USE == i)) + { + + /* Skip the current byte. */ + continue; + } + + /* Calculate the checksum using the algorithm specified in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + system_area_checksum = ((system_area_checksum >> 1) | (system_area_checksum << 31)) + (ULONG)byte_ptr[i]; + } + + /* Write Main Partition Boot sector. */ + _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, 0, 1, FX_BOOT_SECTOR); + + /* Determine if the write was successful. */ + if (FX_SUCCESS != media_ptr -> fx_media_driver_status) + { + + /* Not successful. Return the error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Write BackUp Partition Boot sector. */ + _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE, 1, FX_BOOT_SECTOR); + + /* Determine if the write was successful. */ + if (FX_SUCCESS != media_ptr -> fx_media_driver_status) + { + + /* Not successful. Return the error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Format exFAT System Area. */ + status = _fx_utility_exFAT_system_area_format(media_ptr, + boundary_unit, + &system_area_checksum, + memory_ptr, + memory_size); + /* Check status. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Write System Area CheckSum. */ + status = _fx_utility_exFAT_system_area_checksum_write(media_ptr, byte_ptr, &system_area_checksum); + + /* Determine if the operation was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Format FAT table */ + _fx_utility_memory_set(byte_ptr, 0x00, media_ptr -> fx_media_bytes_per_sector); + + /* Get the offset for the next available FAT entry after the initialized FAT entries. */ + offset = sizeof(fat_init_mask); + + /* Copy the initial values for FAT table. */ + _fx_utility_memory_copy((UCHAR *)fat_init_mask, /* Use case of memcpy is verified. */ + byte_ptr, + sizeof(fat_init_mask)); + + /* Set free cluster number. */ + i = FX_FAT_ENTRY_START; + + /* Reset the sector offset used for sector writing. */ + sector_offset = 0; + + /* Allocate clusters for BitMap Table. */ + for (cluster_count = 1; cluster_count < bitmap_size_in_clusters; cluster_count++) + { + + /* Increase the next cluster number. */ + i++; + + /* Fill the FAT entry. */ + _fx_utility_32_unsigned_write(&byte_ptr[offset], i); + + /* Move to next FAT entry. */ + offset += sizeof(ULONG); + + /* Check if we reach the sector end. */ + if (offset == bytes_per_sector) + { + + /* Write the sector out. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + fat_offset + sector_offset, + 1, FX_FAT_SECTOR); + + /* Determine if the operation was successful. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Go back to the sector buffer head. */ + offset = 0; + + /* Move to next sector. */ + sector_offset++; + } + } + + /* Mark as last cluster. */ + _fx_utility_32_unsigned_write(&byte_ptr[offset], + EXFAT_LAST_CLUSTER_MASK); + + /* Move to next cluster. */ + i++; + offset += sizeof(ULONG); + + /* Check if we reach the sector end. */ + if (offset == bytes_per_sector) + { + + /* Write the sector out. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + fat_offset + sector_offset, + 1, FX_FAT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Go back to the sector buffer head. */ + offset = 0; + sector_offset++; + } + + /* Allocate clusters for UpCase Table. */ + for (cluster_count = 1; cluster_count < upcase_table_size_in_clusters; cluster_count++) + { + + /* Increase the next cluster number. */ + i++; + + /* Fill the FAT entry. */ + _fx_utility_32_unsigned_write(&byte_ptr[offset], i); + + /* Move to next FAT entry. */ + offset += sizeof(ULONG); + + /* Check if we reach the sector end. */ + if (offset == bytes_per_sector) + { + + /* Write the sector out. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + fat_offset + sector_offset, + 1, FX_FAT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Go back to the sector buffer head. */ + offset = 0; + sector_offset++; + } + } + + /* Mark as last cluster. */ + _fx_utility_32_unsigned_write(&byte_ptr[offset], + EXFAT_LAST_CLUSTER_MASK); + + /* Move to next FAT entry. */ + offset += sizeof(ULONG); + + /* Check if we reach the sector end. */ + if (offset == bytes_per_sector) + { + + /* Write the sector out. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + fat_offset + sector_offset, + 1, FX_FAT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Go back to the sector buffer head. */ + offset = 0; + sector_offset++; + } + + /* Allocate cluster for RootDir Entry. */ + _fx_utility_32_unsigned_write(&byte_ptr[offset], + EXFAT_LAST_CLUSTER_MASK); + + /* Write the sector out. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + fat_offset + sector_offset, + 1, FX_FAT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Format Bit Map Table. */ + sector_offset = 0; + offset = 0; + + /* Check if the bitmap has sectors with all set bits. */ + if ((root_dir_entry_first_cluster - 1) / 8 >= bytes_per_sector) + { + + /* Fill the buffer with one. */ + _fx_utility_memory_set(byte_ptr, 0xFF, media_ptr -> fx_media_bytes_per_sector); + + /* Loop to write all the secotrs with all set bits. */ + for (i = ((root_dir_entry_first_cluster - 1) / 8) % bytes_per_sector; i; i--) + { + + /* Write out the bitmap sector. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + cluster_heap_offset + sector_offset, + 1, FX_FAT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Move to next sector. */ + sector_offset++; + } + } + + /* Loop to mark already occupied clusters in 8 clusters size. */ + for (i = ((root_dir_entry_first_cluster - 1) / 8) % bytes_per_sector; i; i--) + { + + /* Write the byte with all set bits. */ + byte_ptr[offset++] = 0xFF; + } + + /* Clear all the remaining bytes. */ + _fx_utility_memory_set(byte_ptr + offset, 0x00, media_ptr -> fx_media_bytes_per_sector - offset); + + /* Loop to set the remaining bits. */ + for (i = (root_dir_entry_first_cluster - 1) % 8; i; i--) + { + + byte_ptr[offset] = (UCHAR)((byte_ptr[offset] << 1) | 0x1); + } + + /* Write out the bitmap sector. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + cluster_heap_offset + sector_offset, + 1, FX_FAT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Move to next sector. */ + sector_offset++; + + /* Fill the remaining bitmap with zeros. */ + if ((bitmap_size_in_clusters << sector_per_cluster_shift) > sector_offset) + { + + /* Fill the sector buffer with zero. */ + _fx_utility_memory_set(byte_ptr, 0x00, media_ptr -> fx_media_bytes_per_sector); + + /* Loop to write all the remaining bitmap sectors. */ + for (i = (bitmap_size_in_clusters << sector_per_cluster_shift) - sector_offset; i; i--) + { + + /* Write out the bitmap sector. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + cluster_heap_offset + sector_offset, + 1, FX_FAT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + sector_offset++; + } + } + + /* Write the upcase table that fits in sector size. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, (UCHAR *)_fx_utility_exFAT_upcase_table_compressed, + cluster_heap_offset + (bitmap_size_in_clusters << sector_per_cluster_shift), + sizeof(_fx_utility_exFAT_upcase_table_compressed) / media_ptr -> fx_media_bytes_per_sector, + FX_DATA_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Write the remaining upcase table bytes. */ + i = sizeof(_fx_utility_exFAT_upcase_table_compressed) % media_ptr -> fx_media_bytes_per_sector; + if (i != 0) + { + + /* Clear the sector buffer. */ + _fx_utility_memory_set(byte_ptr, 0x00, media_ptr -> fx_media_bytes_per_sector); + + /* Copy the remaining bytes. */ + _fx_utility_memory_copy((UCHAR *)_fx_utility_exFAT_upcase_table_compressed + sizeof(_fx_utility_exFAT_upcase_table_compressed) - i, byte_ptr, i); /* Use case of memcpy is verified. */ + + /* Write out the sector. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + cluster_heap_offset + (bitmap_size_in_clusters << sector_per_cluster_shift) + sizeof(_fx_utility_exFAT_upcase_table_compressed) / media_ptr -> fx_media_bytes_per_sector, + 1, FX_DATA_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + } + + /* Format Dir Entry. */ + + /* Clear work buffer. */ + _fx_utility_memory_set(byte_ptr, 0x00, media_ptr -> fx_media_bytes_per_sector); + + /* Create Volume Label Dir Entry. This is a first entry. */ + byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 0 + FX_EXFAT_ENTRY_TYPE] = FX_EXFAT_DIR_ENTRY_TYPE_VOLUME_LABEL; + + /* Copy volume label. */ + for (i = 0; i < EXFAT_FAT_VOLUME_NAME_FIELD_SIZE; i++) + { + + /* Check for end of Label Name. */ + if (0 == volume_name[i]) + { + break; + } + + /* Store one character. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 0 + FX_EXFAT_VOLUME_LABEL + i * 2], (UINT)volume_name[i]); + } + + byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 0 + FX_EXFAT_CHAR_COUNT] = (UCHAR)i; + + /* Create Allocated BitMap Dir Entry. */ + byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 1 + FX_EXFAT_ENTRY_TYPE] = FX_EXFAT_DIR_ENTRY_TYPE_ALLOCATION_BITMAP; + byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 1 + FX_EXFAT_BIT_MAP_FLAGS] = EXFAT_BIT_MAP_FIRST_TABLE; + + _fx_utility_32_unsigned_write(&byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 1 + FX_EXFAT_FIRST_CLUSTER], + FX_FAT_ENTRY_START); + + _fx_utility_32_unsigned_write(&byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 1 + FX_EXFAT_DATA_LENGTH], + bitmap_size_in_bytes); + + /* Create UpCase Table Dir Entry. */ + byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 2 + FX_EXFAT_ENTRY_TYPE] = FX_EXFAT_DIR_ENTRY_TYPE_UP_CASE_TABLE; + + /* Loop to calculate Compressed UpCase table Check Sum. */ + for (i = 0; i < sizeof(_fx_utility_exFAT_upcase_table_compressed); i++) + { + + /* Calculate the checksum using the algorithm specified in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + upcase_table_checksum = ((upcase_table_checksum >> 1) | (upcase_table_checksum << 31)) + + (ULONG)_fx_utility_exFAT_upcase_table_compressed[i]; + } + + /* Fill the checksum field. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 2 + FX_EXFAT_UP_CASE_TABLE_CHECK_SUM], + upcase_table_checksum); + + /* Fill the first cluster field. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 2 + FX_EXFAT_FIRST_CLUSTER], + FX_FAT_ENTRY_START + bitmap_size_in_clusters); + + /* Fill the data length field. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_EXFAT_DIR_ENTRY_SIZE * 2 + FX_EXFAT_DATA_LENGTH], + upcase_table_size_in_bytes); + + /* Write the directory entry. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + root_dir_entry_first_sector, + 1, FX_BOOT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + + /* Clear the secotr buffer. */ + _fx_utility_memory_set(byte_ptr, 0x00, media_ptr -> fx_media_bytes_per_sector); + + /* Loop to clear the remaining root directory sectors. */ + for (i = 1; i < sectors_per_cluster; i++) + { + + /* Write the directory entry sector. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, byte_ptr, + root_dir_entry_first_sector + i, + 1, FX_BOOT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* Not successful. Return the error status. */ + return(status); + } + } + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + return(media_ptr -> fx_media_driver_status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_extended_space_available.c b/src/Middlewares/ST/filex/common/src/fx_media_extended_space_available.c new file mode 100644 index 00000000..54a8da0e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_extended_space_available.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_extended_space_available PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the number of bytes available in the */ +/* specified media. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* available_bytes_ptr Pointer to available bytes */ +/* destination */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_extended_space_available(FX_MEDIA *media_ptr, ULONG64 *available_bytes_ptr) +{ + +ULONG64 available_bytes; +ULONG bytes_per_cluster; +ULONG available_clusters; + + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_SPACE_AVAILABLE, media_ptr, available_bytes_ptr, media_ptr -> fx_media_available_clusters, 0, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Pickup the number of free clusters. */ + available_clusters = media_ptr -> fx_media_available_clusters; + + /* Derive the bytes per cluster. */ + bytes_per_cluster = media_ptr -> fx_media_bytes_per_sector * media_ptr -> fx_media_sectors_per_cluster; + + /* Calculate the free space. */ + available_bytes = ((ULONG64)available_clusters) * ((ULONG64)bytes_per_cluster); + + /* Return the value. */ + *available_bytes_ptr = available_bytes; + + /* Release media protection. */ + FX_UNPROTECT + + /* Return a successful status to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_flush.c b/src/Middlewares/ST/filex/common/src/fx_media_flush.c new file mode 100644 index 00000000..77579af6 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_flush.c @@ -0,0 +1,373 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" +#include "fx_file.h" +#include "fx_directory.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_flush PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function examines the list of open files for this media and */ +/* "flushes" each written open file to the underlying media. After */ +/* the open files have been flushed, the internal logical sector is */ +/* flushed. Finally, the attached driver is sent a flush command so */ +/* that it can flush its sector cache (if any) to the media. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_write Write the directory entry */ +/* _fx_utility_FAT_flush Flush cached FAT entries */ +/* _fx_utility_FAT_map_flush Flush primary FAT changes to */ +/* secondary FAT(s) */ +/* _fx_utility_logical_sector_flush Flush logical sector cache */ +/* _fx_utility_32_unsigned_read Read 32-bit unsigned */ +/* _fx_utility_32_unsigned_write Write 32-bit unsigned */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable cache, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_flush(FX_MEDIA *media_ptr) +{ + +UINT status; +ULONG open_count; +FX_FILE *file_ptr; +FX_INT_SAVE_AREA + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_flushes++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_FLUSH, media_ptr, 0, 0, 0, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Loop through the media's open files. */ + open_count = media_ptr -> fx_media_opened_file_count; + file_ptr = media_ptr -> fx_media_opened_file_list; + while (open_count) + { + + /* Look at each opened file to see if the same file is opened + for writing and has been written to. */ + if ((file_ptr -> fx_file_open_mode == FX_OPEN_FOR_WRITE) && + (file_ptr -> fx_file_modified)) + { + + /* Protect against update. */ + FX_DISABLE_INTS + + /* Set the new time and date. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_time = _fx_system_time; + file_ptr -> fx_file_dir_entry.fx_dir_entry_date = _fx_system_date; + + /* Restore interrupts. */ + FX_RESTORE_INTS + + /* Copy the new file size into the directory entry. */ + file_ptr -> fx_file_dir_entry.fx_dir_entry_file_size = + file_ptr -> fx_file_current_file_size; + + /* Write the directory entry to the media. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_directory_exFAT_entry_write( + media_ptr, &(file_ptr -> fx_file_dir_entry), UPDATE_STREAM); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + status = _fx_directory_entry_write(media_ptr, &(file_ptr -> fx_file_dir_entry)); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Error writing the directory. */ + return(status); + } + + /* Clear the file modified flag. */ + file_ptr -> fx_file_modified = FX_FALSE; + } + + /* Adjust the pointer and decrement the opened count. */ + file_ptr = file_ptr -> fx_file_opened_next; + open_count--; + } + + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); + + /* Flush changed sector(s) in the primary FAT to secondary FATs. */ + _fx_utility_FAT_map_flush(media_ptr); + +#ifdef FX_ENABLE_EXFAT + if ((media_ptr -> fx_media_FAT_type == FX_exFAT) && + (FX_TRUE == media_ptr -> fx_media_exfat_bitmap_cache_dirty)) + { + + /* Flush bitmap. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + + /* Flush the internal logical sector cache. */ + status = _fx_utility_logical_sector_flush(media_ptr, ((ULONG64) 1), (ULONG64) (media_ptr -> fx_media_total_sectors), FX_FALSE); + + /* Check for a good status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Error writing the directory. */ + return(status); + } + + /* Determine if the media needs to have the additional information sector updated. This will + only be the case for 32-bit FATs. The logic here only needs to be done if the last reported + available cluster count is different that the currently available clusters. */ + if ((media_ptr -> fx_media_FAT32_additional_info_sector) && + (media_ptr -> fx_media_FAT32_additional_info_last_available != media_ptr -> fx_media_available_clusters)) + { + + UCHAR *buffer_ptr; + ULONG signature; + +#ifndef FX_DISABLE_CACHE + + /* Setup a pointer to the first cached entry's buffer. */ + buffer_ptr = (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector_memory_buffer; + + /* Invalidate this cache entry. */ + (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector = (~(ULONG64)0); + (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector_valid = FX_FALSE; +#else + buffer_ptr = media_ptr -> fx_media_memory_buffer; +#endif /* FX_DISABLE_CACHE */ + + /* Read the FAT32 additional information sector from the device. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = buffer_ptr; + media_ptr -> fx_media_driver_logical_sector = media_ptr -> fx_media_FAT32_additional_info_sector; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver read sector(s) requests. */ + media_ptr -> fx_media_driver_read_requests++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_READ, media_ptr, media_ptr -> fx_media_FAT32_additional_info_sector, 1, buffer_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the FAT32 additional information sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the FAT32 sector was read correctly. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(FX_IO_ERROR); + } + + /* Setup a pointer into the FAT32 additional information sector. */ + buffer_ptr = media_ptr -> fx_media_driver_buffer; + + /* Pickup the first signature long word. */ + signature = _fx_utility_32_unsigned_read(&buffer_ptr[0]); + + /* Determine if the signature is correct. */ + if (signature == 0x41615252) + { + + /* Yes, the first signature is correct, now pickup the next signature. */ + signature = _fx_utility_32_unsigned_read(&buffer_ptr[484]); + + /* Determine if this signature is correct. */ + if (signature == 0x61417272) + { + + /* Yes, we have a good FAT32 additional information sector. */ + + /* Set the free cluster count to the available clusters in the media control block. */ + _fx_utility_32_unsigned_write(&buffer_ptr[488], media_ptr -> fx_media_available_clusters); + + /* Set the next free cluster number hint to starting search cluster in the media control block. */ + _fx_utility_32_unsigned_write(&buffer_ptr[492], media_ptr -> fx_media_cluster_search_start); + + /* Now write the sector back out to the media. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = buffer_ptr; + media_ptr -> fx_media_driver_logical_sector = media_ptr -> fx_media_FAT32_additional_info_sector; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + + /* Set the system write flag since we are writing a directory sector. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, media_ptr -> fx_media_FAT32_additional_info_sector, 1, buffer_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the FAT32 additional information sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if the FAT32 sector was written correctly. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the sector IO error status. */ + return(FX_IO_ERROR); + } + + /* Successful update of the FAT32 additional information sector. Update the + last written available cluster count. */ + media_ptr -> fx_media_FAT32_additional_info_last_available = media_ptr -> fx_media_available_clusters; + } + } + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver flush requests. */ + media_ptr -> fx_media_driver_flush_requests++; +#endif + + /* Build the "flush" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_FLUSH; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_FLUSH, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the flush request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the I/O driver flushed successfully. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the driver error status. */ + return(FX_IO_ERROR); + } + + /* Release media protection. */ + FX_UNPROTECT + + /* If we get here, return successful status to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_format.c b/src/Middlewares/ST/filex/common/src/fx_media_format.c new file mode 100644 index 00000000..de4bee97 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_format.c @@ -0,0 +1,691 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" +#include "fx_utility.h" + + +/* Define global variables necessary for formatting. */ + +/* Define OEM Name. This name must be 8 characters long and be blank padded. + The default may be changed by modifying this file or calling the + fx_media_format_oem_name_set utility prior to calling fx_media_format. */ + +UCHAR _fx_media_format_oem_name[8] = "EL FILEX"; + + +/* Define the default media type. This default may be changed by modifying + this file or calling the fx_media_format_type_set utility prior to calling + fx_media_format. */ + +UCHAR _fx_media_format_media_type = 0xF8; + + +/* Define the default volume ID. This default may be changed by modifying + this file or calling the fx_media_format_volume_id_set utility prior to calling + fx_media_format. */ + +ULONG _fx_media_format_volume_id = 1; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_format PORTABLE C */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a FAT12/16/32 format with raw calls to the */ +/* I/O driver. It can and must be called before the fx_media_open */ +/* and is designed to utilize the same underlying FileX driver. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media control block*/ +/* (does not need to be opened)*/ +/* driver Pointer to FileX driver (must */ +/* be able to field requests */ +/* prior to opening) */ +/* driver_info_ptr Optional information pointer */ +/* memory_ptr Pointer to memory used by the */ +/* FileX for this media. */ +/* memory_size Size of media memory - must */ +/* at least 512 bytes and */ +/* one sector size. */ +/* volume_name Name of the volume */ +/* number_of_fats Number of FAT tables */ +/* directory_entries Number of directory entries */ +/* hidden_sectors Number of hidden sectors */ +/* total_sectors Total number of sectors */ +/* bytes_per_sector Number of bytes per sector */ +/* sectors_per_cluster Number of sectors per cluster */ +/* heads Number of heads */ +/* sectors_per_track Number of sectors per track */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* Media driver */ +/* _fx_utility_16_unsigned_write Write 16-bit unsigned */ +/* _fx_utility_32_unsigned_write Write 32-bit unsigned */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable force memset, */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* 08-02-2021 Bhupendra Naphade Modified comment(s), and */ +/* updated boot write logic, */ +/* resulting in version 6.1.8 */ +/* */ +/**************************************************************************/ +UINT _fx_media_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, UCHAR *memory_ptr, UINT memory_size, + CHAR *volume_name, UINT number_of_fats, UINT directory_entries, UINT hidden_sectors, + ULONG total_sectors, UINT bytes_per_sector, UINT sectors_per_cluster, + UINT heads, UINT sectors_per_track) +{ + +UCHAR *byte_ptr; +UINT reserved_sectors, i, j, root_sectors, total_clusters, bytes_needed; +UINT sectors_per_fat, f, s; + + + /* Create & write bootrecord from drive geometry information. */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_FORMAT, media_ptr, directory_entries, total_sectors, sectors_per_cluster, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Validate bytes per sector value: greater than zero and no more than 4096. */ + if((bytes_per_sector == 0) || (bytes_per_sector > 4096)) + return(FX_SECTOR_INVALID); + + /* Validate sectors per cluster value: greater than zero and no more than 128. */ + if((sectors_per_cluster == 0) || (sectors_per_cluster > 128)) + return(FX_SECTOR_INVALID); + + /* Setup driver pointer and memory information. */ + media_ptr -> fx_media_driver_entry = driver; + media_ptr -> fx_media_memory_buffer = (UCHAR *)memory_ptr; + media_ptr -> fx_media_memory_size = memory_size; + + /* Store geometry information in media record - driver needs this. */ + media_ptr -> fx_media_bytes_per_sector = bytes_per_sector; + media_ptr -> fx_media_sectors_per_track = sectors_per_track; + media_ptr -> fx_media_heads = heads; + media_ptr -> fx_media_hidden_sectors = hidden_sectors; + + /* Initialize the supplied media I/O driver. First, build the + initialize driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_INIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_info = driver_info_ptr; + media_ptr -> fx_media_driver_write_protect = FX_FALSE; + media_ptr -> fx_media_driver_free_sector_update = FX_FALSE; + media_ptr -> fx_media_driver_data_sector_read = FX_FALSE; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_INIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the initialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the I/O driver initialized successfully. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Return the driver error status. */ + return(FX_IO_ERROR); + } + + /* Setup driver buffer memory. */ + media_ptr -> fx_media_driver_buffer = memory_ptr; + + /* Move the buffer pointer into a local copy. */ + byte_ptr = media_ptr -> fx_media_driver_buffer; + +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + /* Clear the buffer record out, assuming it is large enough for one sector. */ + for (i = 0; i < bytes_per_sector; i++) + { + + /* Clear each byte of the boot record. */ + byte_ptr[i] = (UCHAR)0; + } +#else + _fx_utility_memory_set(byte_ptr, 0, bytes_per_sector); +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + + /* Set jump instruction at the beginning of the sector. */ + byte_ptr[0] = (UCHAR)0xEB; + byte_ptr[1] = (UCHAR)0x34; + byte_ptr[2] = (UCHAR)0x90; + + /* Set the OEM name in the boot record. */ + for (i = 0; i < 8; i++) + { + + /* Copy a character from the OEM name. */ + byte_ptr[i + 3] = _fx_media_format_oem_name[i]; + } + + /* Set the media type in the boot record. */ + byte_ptr[FX_MEDIA_TYPE] = _fx_media_format_media_type; + + /* Set the number of bytes per sector. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_BYTES_SECTOR], bytes_per_sector); + + /* Set the number of sectors per track. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_SECTORS_PER_TRK], sectors_per_track); + + /* Set the number of heads. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_HEADS], heads); + +#ifdef FX_FORCE_512_BYTE_BOOT_SECTOR + + /* Calculate the number of reserved sectors. If sector size is smaller than 512 bytes, there will be + reserved sectors, otherwise assumed that only the sector containing bootrecord is reserved. */ + if (bytes_per_sector < 512) + { + reserved_sectors = 512 / bytes_per_sector; + } + else + { + reserved_sectors = 1; + } +#else + + /* The boot sector is the only reserved sector. */ + reserved_sectors = 1; +#endif + + + /* Calculate the maximum clusters.... This is actually greater than the actual since the FAT + sectors have yet to be accounted for. */ + total_clusters = (total_sectors - reserved_sectors - ((directory_entries * FX_DIR_ENTRY_SIZE) + (bytes_per_sector - 1)) / bytes_per_sector) / sectors_per_cluster; + + /* Calculate the maximum number of FAT sectors necessary for FAT12. */ + if (total_clusters % 2) + { + bytes_needed = (total_clusters + total_clusters / 2) + 1; + } + else + { + bytes_needed = (total_clusters + total_clusters / 2); + } + sectors_per_fat = bytes_needed / bytes_per_sector; + if (bytes_needed % bytes_per_sector) + { + sectors_per_fat++; + } + + /* Now adjust the total clusters by the number of sectors per FAT. */ + total_clusters = total_clusters - ((sectors_per_fat * number_of_fats) + (sectors_per_cluster - 1)) / sectors_per_cluster; + + /* Is the total cluster count greater than the FAT12 maximum? */ + if (total_clusters >= FX_12_BIT_FAT_SIZE) + { + + /* Yes, too big for FAT12, we need to evaluate for FAT16. */ + + /* Reset the maximum clusters.... This is actually greater than the actual since the FAT + sectors have yet to be accounted for. */ + total_clusters = (total_sectors - reserved_sectors - ((directory_entries * FX_DIR_ENTRY_SIZE) + (bytes_per_sector - 1)) / bytes_per_sector) / sectors_per_cluster; + + /* Calculate 16-bit FAT is present. Each cluster requires a 2 byte entry in the FAT table. */ + sectors_per_fat = (total_clusters * 2) / bytes_per_sector; + if ((total_clusters * 2) % bytes_per_sector) + { + sectors_per_fat++; + } + + /* Now adjust the total clusters by the number of sectors per FAT. */ + total_clusters = total_clusters - ((sectors_per_fat * number_of_fats) + (sectors_per_cluster - 1)) / sectors_per_cluster; + + /* Is the total cluster count greater than the FAT16 maximum? */ + if (total_clusters >= FX_16_BIT_FAT_SIZE) + { + + /* Yes, FAT32 is present. */ + + /* Allocate room for the FAT32 additional information sector. This contains useful information + such as the number of available clusters between successive mounting of the media. */ + if (bytes_per_sector == 512) + { + + /* Write sector number 1 to the additional information sector. */ + _fx_utility_16_unsigned_write(&byte_ptr[48], 1); + + /* Increment the reserved sectors count, since this will count as a reserved sector. */ + reserved_sectors++; + } + else + { + + /* Write value to indicate there is no additional information sector. */ + _fx_utility_16_unsigned_write(&byte_ptr[48], 0xFFFF); + } + + /* Allocate the first cluster to the root directory. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_ROOT_CLUSTER_32], FX_FAT_ENTRY_START); + + /* Determine if the number of root directory entries should be modified. */ + directory_entries = (sectors_per_cluster * bytes_per_sector) / FX_DIR_ENTRY_SIZE; + + /* Reset the total_clusters for the FAT32 calculation. */ + total_clusters = (total_sectors - reserved_sectors) / sectors_per_cluster; + + /* 32-bit FAT is present. Each cluster requires a 4 byte entry in the FAT table. */ + sectors_per_fat = (total_clusters * 4) / bytes_per_sector; + if ((total_clusters * 4) % bytes_per_sector) + { + sectors_per_fat++; + } + + /* Now adjust the total clusters by the number of sectors per FAT. */ + total_clusters = total_clusters - ((sectors_per_fat * number_of_fats) + (sectors_per_cluster - 1)) / sectors_per_cluster; + } + } + + /* Set sectors per FAT type. */ + if (total_clusters < FX_16_BIT_FAT_SIZE) + { + + /* Set the number of sectors per FAT12/16. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_SECTORS_PER_FAT], sectors_per_fat); + + /* Set the signature. */ + byte_ptr[FX_BOOT_SIG] = 0x29; + + /* Setup the volume ID. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_VOLUME_ID], _fx_media_format_volume_id); + } + else + { + + /* Set the number of sectors per FAT32. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_SECTORS_PER_FAT_32], sectors_per_fat); + + /* Set the signature. */ + byte_ptr[FX_BOOT_SIG_32] = 0x29; + + /* Setup the volume ID. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_VOLUME_ID_32], _fx_media_format_volume_id); + } + + /* Set the total number of sectors. */ + if (total_sectors < (ULONG)0xFFFF) + { + + /* Write the 16-bit total sector field. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_SECTORS], (UINT)(total_sectors)); + + /* Set the number of huge sectors. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_HUGE_SECTORS], 0); + } + else + { + + /* Write the 16-bit total sector field as 0. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_SECTORS], (UINT)0); + + /* Set the number of huge sectors. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_HUGE_SECTORS], total_sectors); + } + + /* Set the number of reserved sectors. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_RESERVED_SECTORS], reserved_sectors); + + /* Set the number of sectors per cluster */ + byte_ptr[FX_SECTORS_CLUSTER] = (UCHAR)sectors_per_cluster; + + /* Set the number of FATs. */ + byte_ptr[FX_NUMBER_OF_FATS] = (UCHAR)number_of_fats; + + /* Set the number of hidden sectors. */ + _fx_utility_32_unsigned_write(&byte_ptr[FX_HIDDEN_SECTORS], hidden_sectors); + + /* Determine if a FAT12 or FAT16 is present. If FAT32 is present, these fields are left alone! */ + if (total_clusters < FX_16_BIT_FAT_SIZE) + { + + /* Yes, set the number of root directory entries. */ + _fx_utility_16_unsigned_write(&byte_ptr[FX_ROOT_DIR_ENTRIES], directory_entries); + } + + /* Now setup the volume label. */ + if (total_clusters < FX_16_BIT_FAT_SIZE) + { + + /* FAT12/16 volume label offset. */ + j = FX_VOLUME_LABEL; + } + else + { + + /* FAT32 volume label offset. */ + j = FX_VOLUME_LABEL_32; + } + + i = 0; + while (i < 11) + { + + /* Determine if it is NULL. */ + if (volume_name[i] == 0) + { + + /* Yes, the copying is finished. */ + break; + } + + /* Otherwise, copy byte of volume name into boot record. */ + byte_ptr[j + i] = (UCHAR)volume_name[i]; + + /* Increment byte position. */ + i++; + } + + /* Now blank-pad the remainder of the volume name. */ +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + while (i < 11) + { + + byte_ptr[j + i] = (UCHAR)' '; + i++; + } +#else + _fx_utility_memory_set(&byte_ptr[j + i], ' ', (11 - i)); +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + + +#ifdef FX_FORCE_512_BYTE_BOOT_SECTOR + + /* Set bootrecord signature. */ + byte_ptr[510] = 0x55; + byte_ptr[511] = 0xAA; +#else + + /* Set bootrecord signature. */ + byte_ptr[bytes_per_sector - 2] = 0x55; + byte_ptr[bytes_per_sector - 1] = 0xAA; +#endif + + /* Select the boot record write command. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_BOOT_WRITE; + media_ptr -> fx_media_driver_system_write = FX_TRUE; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_BOOT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_BOOT_WRITE, media_ptr, memory_ptr, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Write out the bootrecord */ + (driver)(media_ptr); + + /* Clear the write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if it was successful. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + return(FX_IO_ERROR); + } + + /* Calculate the number of root sectors. */ + root_sectors = ((directory_entries * FX_DIR_ENTRY_SIZE) + bytes_per_sector - 1) / bytes_per_sector; + + /* Determine if FAT32 is present AND if the bytes per sector is large enough to have + a FSINFO sector. */ + if ((total_clusters >= FX_16_BIT_FAT_SIZE) && (bytes_per_sector == 512)) + { + +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + /* Clear sector buffer. */ + for (i = 0; i < bytes_per_sector; i++) + { + byte_ptr[i] = (CHAR)0; + } +#else + _fx_utility_memory_set(byte_ptr, 0, bytes_per_sector); +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + + /* Build the FSINFO fields. */ + + /* Build first signature word, used to help verify this is a FSINFO sector. */ + byte_ptr[0] = 0x52; + byte_ptr[1] = 0x52; + byte_ptr[2] = 0x61; + byte_ptr[3] = 0x41; + + /* Build the next signature word, this too is used to help verify that this is a FSINFO sector. */ + byte_ptr[484] = 0x72; + byte_ptr[485] = 0x72; + byte_ptr[486] = 0x41; + byte_ptr[487] = 0x61; + + /* Build the final signature word, this too is used to help verify that this is a FSINFO sector. */ + byte_ptr[508] = 0x55; + byte_ptr[509] = 0xAA; + + /* Setup the total available clusters on the media. We need to subtract 1 for the FAT32 root directory. */ + _fx_utility_32_unsigned_write(&byte_ptr[488], (total_clusters - 1)); + + /* Setup the starting free cluster to 3, since cluster 2 is reserved for the FAT32 root directory. */ + _fx_utility_32_unsigned_write(&byte_ptr[492], 3); + + /* Now write the FSINFO sector to the media. */ + media_ptr -> fx_media_driver_logical_sector = 1; + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_system_write = FX_TRUE; + media_ptr -> fx_media_driver_sector_type = FX_BOOT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, 1, 1, memory_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Write out the sector. */ + (driver)(media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if it was successful. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + return(FX_IO_ERROR); + } + } + + /* At this point we need set up first to FAT entries and clear the remaining FAT sectors area. */ + + /* Loop through number of FATs. The first is the only one used. */ + for (f = 0; f < number_of_fats; f++) + { + + /* Loop through all the sectors in this FAT. */ + for (s = 0; s < sectors_per_fat; s++) + { + + if (s == 0) + { + + /* Reserve the first two FAT table entries. */ + if (total_clusters < FX_12_BIT_FAT_SIZE) + { + + /* Reserve the first two FAT-12 entries. */ + byte_ptr[0] = (UCHAR)0x0F; + byte_ptr[1] = (UCHAR)0x0F; + byte_ptr[2] = (UCHAR)0xFF; + + /* Start clearing at FAT entry 3. */ + i = 3; + } + else if (total_clusters < FX_16_BIT_FAT_SIZE) + { + + /* Reserve the first two FAT-16 entries. */ + byte_ptr[0] = (UCHAR)0xF0; + byte_ptr[1] = (UCHAR)0x00; + byte_ptr[2] = (UCHAR)0xFF; + byte_ptr[3] = (UCHAR)0xFF; + + /* Start clearing at FAT entry 3. */ + i = 4; + } + else + { + + /* Reserve the first two FAT-32 entries. */ + byte_ptr[0] = (UCHAR)0xF0; + byte_ptr[1] = (UCHAR)0x00; + byte_ptr[2] = (UCHAR)0x00; + byte_ptr[3] = (UCHAR)0x00; + byte_ptr[4] = (UCHAR)0xFF; + byte_ptr[5] = (UCHAR)0xFF; + byte_ptr[6] = (UCHAR)0xFF; + byte_ptr[7] = (UCHAR)0xFF; + + /* Preallocate the first cluster for the root directory. */ + byte_ptr[8] = (UCHAR)0xFF; + byte_ptr[9] = (UCHAR)0xFF; + byte_ptr[10] = (UCHAR)0xFF; + byte_ptr[11] = (UCHAR)0x0F; + + /* Start clearing at FAT entry 3. */ + i = 12; + } + } + else + { + i = 0; + } + +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + /* Clear remainder of sector buffer. */ + for (; i < bytes_per_sector; i++) + { + byte_ptr[i] = (CHAR)0; + } +#else + _fx_utility_memory_set(&byte_ptr[i], 0, (bytes_per_sector - i)); +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + + /* Build sector write command. */ + media_ptr -> fx_media_driver_logical_sector = reserved_sectors + (f * sectors_per_fat) + s; + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_system_write = FX_TRUE; + media_ptr -> fx_media_driver_sector_type = FX_FAT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, media_ptr -> fx_media_driver_logical_sector, 1, memory_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Write out the sector. */ + (driver)(media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if it was successful. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + return(FX_IO_ERROR); + } + } + } + +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + /* Clear sector buffer. */ + for (i = 0; i < bytes_per_sector; i++) + { + byte_ptr[i] = (CHAR)0; + } +#else + _fx_utility_memory_set(byte_ptr, 0, bytes_per_sector); +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + + /* Now clear the root directory sectors. */ + for (s = 0; s < root_sectors; s++) + { + + /* Build sector write command. */ + media_ptr -> fx_media_driver_logical_sector = reserved_sectors + (number_of_fats * sectors_per_fat) + s; + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_system_write = FX_TRUE; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, media_ptr -> fx_media_driver_logical_sector, 1, memory_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Write out the sector. */ + (driver)(media_ptr); + + /* Clear the write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if it was successful. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + return(FX_IO_ERROR); + } + } + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Return success! */ + return(media_ptr -> fx_media_driver_status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c b/src/Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c new file mode 100644 index 00000000..42780886 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_format_oem_name_set.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +/* Define external reference to OEM name string. */ + +extern UCHAR _fx_media_format_oem_name[8]; +UINT fx_media_format_oem_name_set(UCHAR new_oem_name[8]); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_format_oem_name_set PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function modifies the default OEM name for all formatting. The */ +/* new OEM name must be 8 characters long - blank padded if necessary. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* new_oem_name Pointer to new OEM name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT fx_media_format_oem_name_set(UCHAR new_oem_name[8]) +{ + +UINT i; + + + /* Simply copy the new OEM name into the default location. */ + for (i = 0; i < 8; i++) + { + + /* Copy one character of the new OEM name. */ + _fx_media_format_oem_name[i] = new_oem_name[i]; + } + + /* Return success. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_format_type_set.c b/src/Middlewares/ST/filex/common/src/fx_media_format_type_set.c new file mode 100644 index 00000000..3bd80cda --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_format_type_set.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +/* Define external reference to media type. */ + +extern UCHAR _fx_media_format_media_type; +UINT fx_media_format_type_set(UCHAR new_media_type); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_format_type_set PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function modifies the default media type for all formatting. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* new_media_type New media type value */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT fx_media_format_type_set(UCHAR new_media_type) +{ + + /* Simply copy the new media type into the default location. */ + _fx_media_format_media_type = new_media_type; + + /* Return success. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c b/src/Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c new file mode 100644 index 00000000..7fe94fbb --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_format_volume_id_set.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +/* Define external reference to media volume ID. */ + +extern ULONG _fx_media_format_volume_id; +UINT fx_media_format_volume_id_set(ULONG new_volume_id); + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_format_media_volume_id_set PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function modifies the default media volume ID for all */ +/* formatting. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* new_volume_id New media volume Id value */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT fx_media_format_volume_id_set(ULONG new_volume_id) +{ + + /* Simply copy the new media volume ID into the default location. */ + _fx_media_format_volume_id = new_volume_id; + + /* Return success. */ + return(FX_SUCCESS); +} diff --git a/src/Middlewares/ST/filex/common/src/fx_media_open.c b/src/Middlewares/ST/filex/common/src/fx_media_open.c new file mode 100644 index 00000000..2e495a96 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_open.c @@ -0,0 +1,1059 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_open PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function opens the specified media with the supplied device */ +/* driver. The specified media must conform to the FAT compatible */ +/* file format, which is verified during the media open process. In */ +/* addition, the supplied FileX device driver must also conform to */ +/* the FileX device driver specification. */ +/* */ +/* The FAT boot sector (512 bytes) that is verified by this */ +/* function must look like the following: */ +/* */ +/* Byte Offset Meaning Size */ +/* */ +/* 0x000 Jump Instructions 3 */ +/* 0x003 OEM Name 8 */ +/* 0x00B *Bytes per Sector 2 */ +/* 0x00D *Sectors per Cluster 1 */ +/* 0x00E *Reserved Sectors 2 */ +/* 0x010 *Number of FATs 1 */ +/* 0x011 *Max Root Dir Entries 2 */ +/* 0x013 *Number of Sectors 2 */ +/* 0x015 Media Type 1 */ +/* 0x016 *Sectors per FAT 2 */ +/* 0x018 *Sectors per Track 2 */ +/* 0x01A *Number of Heads 2 */ +/* 0x01C *Hidden Sectors 4 */ +/* 0x020 *Huge Sectors 4 */ +/* 0x024 Drive Number 1 */ +/* 0x025 Reserved 1 */ +/* 0x026 Boot Signature 1 */ +/* 0x027 Volume ID 4 */ +/* 0x02B Volume Label 11 */ +/* 0x036 File System Type 8 */ +/* ... ... ... */ +/* 0x1FE **Signature (0x55aa) 2 */ +/* */ +/* * Denotes which elements of the boot record */ +/* FileX uses. */ +/* */ +/* **Denotes the element is checked by the I/O */ +/* driver. This eliminates the need for a minimum */ +/* 512-byte buffer for FileX. */ +/* */ +/* Note: All values above are in little endian format, i.e. the LSB is */ +/* in the lowest address. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* media_name Pointer to media name string */ +/* media_driver Media driver entry function */ +/* driver_info_ptr Optional information pointer */ +/* supplied to media driver */ +/* memory_ptr Pointer to memory used by the */ +/* FileX for this media. */ +/* memory_size Size of media memory - must */ +/* at least 512 bytes and */ +/* one sector size. */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* I/O Driver */ +/* _fx_utility_exFAT_bitmap_initialize Initialize exFAT bitmap */ +/* _fx_utility_16_unsigned_read Read 16-bit unsigned value */ +/* _fx_utility_32_unsigned_read Read 32-bit unsigned value */ +/* _fx_utility_logical_sector_flush Invalidate log sector cache */ +/* _fx_media_boot_info_extract Extract media information */ +/* _fx_utility_FAT_entry_read Pickup FAT entry contents */ +/* tx_mutex_create Create protection mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable force memset, */ +/* build options and cache, */ +/* resulting in version 6.1 */ +/* 01-31-2022 William E. Lamie Modified comment(s), fixed */ +/* errors without cache, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_media_open(FX_MEDIA *media_ptr, CHAR *media_name, + VOID (*media_driver)(FX_MEDIA *), VOID *driver_info_ptr, + VOID *memory_ptr, ULONG memory_size) +{ + +FX_MEDIA_PTR tail_ptr; +ULONG cluster_number; +ULONG FAT_entry, FAT_sector, FAT_read_sectors; +ULONG i, j; +#ifndef FX_DISABLE_CACHE +FX_CACHED_SECTOR *cache_entry_ptr; +#endif /* FX_DISABLE_CACHE */ +UINT status; +UINT additional_info_sector; +UCHAR *original_memory_ptr; +ULONG bytes_in_buffer; +FX_INT_SAVE_AREA + + +#ifndef FX_DISABLE_BUILD_OPTIONS + /* Reference the version ID and option words to ensure they are linked in. */ + if ((_fx_system_build_options_1 | _fx_system_build_options_2 | _fx_system_build_options_3) == 0 || + _fx_version_id[0] == 0) + { + + /* We should never get here! */ + return(FX_NOT_IMPLEMENTED); + } +#endif /* FX_DISABLE_BUILD_OPTIONS */ + +#ifdef FX_DISABLE_FORCE_MEMORY_OPERATION + _fx_utility_memory_set((UCHAR *)media_ptr, 0, sizeof(FX_MEDIA)); +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ +#ifdef FX_DISABLE_CACHE + media_ptr -> fx_media_memory_buffer_sector = (ULONG64)-1; +#endif /* FX_DISABLE_CACHE */ + + /* Save the basic information in the media control block. */ + media_ptr -> fx_media_name = media_name; + media_ptr -> fx_media_driver_entry = media_driver; + media_ptr -> fx_media_memory_buffer = (UCHAR *)memory_ptr; + media_ptr -> fx_media_memory_size = memory_size; +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + media_ptr -> fx_media_disable_burst_cache = FX_FALSE; + media_ptr -> fx_media_FAT_type = 0; +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + + /* Save the original memory pointer. */ + original_memory_ptr = (UCHAR *)memory_ptr; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Clear the optional media statistics. */ + media_ptr -> fx_media_directory_attributes_reads = 0; + media_ptr -> fx_media_directory_attributes_sets = 0; + media_ptr -> fx_media_directory_creates = 0; + media_ptr -> fx_media_directory_default_gets = 0; + media_ptr -> fx_media_directory_default_sets = 0; + media_ptr -> fx_media_directory_deletes = 0; + media_ptr -> fx_media_directory_first_entry_finds = 0; + media_ptr -> fx_media_directory_first_full_entry_finds = 0; + media_ptr -> fx_media_directory_information_gets = 0; + media_ptr -> fx_media_directory_local_path_clears = 0; + media_ptr -> fx_media_directory_local_path_gets = 0; + media_ptr -> fx_media_directory_local_path_restores = 0; + media_ptr -> fx_media_directory_local_path_sets = 0; + media_ptr -> fx_media_directory_name_tests = 0; + media_ptr -> fx_media_directory_next_entry_finds = 0; + media_ptr -> fx_media_directory_next_full_entry_finds = 0; + media_ptr -> fx_media_directory_renames = 0; + media_ptr -> fx_media_file_allocates = 0; + media_ptr -> fx_media_file_attributes_reads = 0; + media_ptr -> fx_media_file_attributes_sets = 0; + media_ptr -> fx_media_file_best_effort_allocates = 0; + media_ptr -> fx_media_file_closes = 0; + media_ptr -> fx_media_file_creates = 0; + media_ptr -> fx_media_file_deletes = 0; + media_ptr -> fx_media_file_opens = 0; + media_ptr -> fx_media_file_reads = 0; + media_ptr -> fx_media_file_relative_seeks = 0; + media_ptr -> fx_media_file_renames = 0; + media_ptr -> fx_media_file_seeks = 0; + media_ptr -> fx_media_file_truncates = 0; + media_ptr -> fx_media_file_truncate_releases = 0; + media_ptr -> fx_media_file_writes = 0; + media_ptr -> fx_media_aborts = 0; + media_ptr -> fx_media_flushes = 0; + media_ptr -> fx_media_reads = 0; + media_ptr -> fx_media_writes = 0; + media_ptr -> fx_media_directory_entry_reads = 0; + media_ptr -> fx_media_directory_entry_writes = 0; + media_ptr -> fx_media_directory_searches = 0; +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + media_ptr -> fx_media_directory_search_cache_hits = 0; +#endif + media_ptr -> fx_media_directory_free_searches = 0; + media_ptr -> fx_media_fat_entry_reads = 0; + media_ptr -> fx_media_fat_entry_writes = 0; + media_ptr -> fx_media_fat_entry_cache_read_hits = 0; + media_ptr -> fx_media_fat_entry_cache_read_misses = 0; + media_ptr -> fx_media_fat_entry_cache_write_hits = 0; + media_ptr -> fx_media_fat_entry_cache_write_misses = 0; + media_ptr -> fx_media_fat_cache_flushes = 0; + media_ptr -> fx_media_fat_sector_reads = 0; + media_ptr -> fx_media_fat_sector_writes = 0; + media_ptr -> fx_media_logical_sector_reads = 0; + media_ptr -> fx_media_logical_sector_writes = 0; + media_ptr -> fx_media_logical_sector_cache_read_hits = 0; + media_ptr -> fx_media_logical_sector_cache_read_misses = 0; + media_ptr -> fx_media_driver_read_requests = 0; + media_ptr -> fx_media_driver_write_requests = 0; + media_ptr -> fx_media_driver_boot_read_requests = 0; + media_ptr -> fx_media_driver_boot_write_requests = 0; + media_ptr -> fx_media_driver_release_sectors_requests = 0; + media_ptr -> fx_media_driver_flush_requests = 0; +#endif +#ifdef FX_ENABLE_FAULT_TOLERANT + media_ptr -> fx_media_fault_tolerant_enabled = FX_FALSE; + media_ptr -> fx_media_fault_tolerant_state = 0; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_OPEN, media_ptr, media_driver, memory_ptr, memory_size, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Initialize the supplied media I/O driver. First, build the + initialize driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_INIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_info = driver_info_ptr; + media_ptr -> fx_media_driver_write_protect = FX_FALSE; + media_ptr -> fx_media_driver_free_sector_update = FX_FALSE; + media_ptr -> fx_media_driver_data_sector_read = FX_FALSE; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_INIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the initialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the I/O driver initialized successfully. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Return the driver error status. */ + return(FX_IO_ERROR); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver boot read requests. */ + media_ptr -> fx_media_driver_boot_read_requests++; +#endif + + /* Read the boot sector from the device. Build the read boot sector + command. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_BOOT_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = memory_ptr; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_BOOT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_BOOT_READ, media_ptr, memory_ptr, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the boot sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the boot sector was read correctly. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Return the boot sector error status. */ + return(FX_BOOT_ERROR); + } + + /* Extract and validate the media parameters from the boot sector. */ + if (_fx_media_boot_info_extract(media_ptr) != FX_SUCCESS) + { + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Return the invalid media error status. */ + return(FX_MEDIA_INVALID); + } + + /* Pickup the additional info sector number. This will only be used in FAT32 situations. */ + additional_info_sector = _fx_utility_16_unsigned_read(&media_ptr -> fx_media_driver_buffer[48]); + +#ifndef FX_DISABLE_CACHE + /* Determine how many logical sectors can be cached with user's supplied + buffer area - there must be at least enough for one sector! */ + media_ptr -> fx_media_sector_cache_size = memory_size / media_ptr -> fx_media_bytes_per_sector; + + /* Is there at least one? */ + if (media_ptr -> fx_media_sector_cache_size == 0) + { + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Error in the buffer size supplied by user. */ + return(FX_BUFFER_ERROR); + } + + /* If trace is enabled, register this object. */ + FX_TRACE_OBJECT_REGISTER(FX_TRACE_OBJECT_TYPE_MEDIA, media_ptr, media_name, FX_MAX_FAT_CACHE, media_ptr -> fx_media_sector_cache_size) + + /* Adjust the internal cache to fit the fixed number of sector cache control blocks + built into the media control block. */ + if (media_ptr -> fx_media_sector_cache_size > FX_MAX_SECTOR_CACHE) + { + + /* Adjust the number of cache sectors downward. If this is insufficient, + the FX_MAX_SECTOR_CACHE constant in FX_API.H must be changed and the FileX + library must be rebuilt. */ + media_ptr -> fx_media_sector_cache_size = FX_MAX_SECTOR_CACHE; + } + + /* Otherwise, everything is okay. Initialize the data structures for managing the + logical sector cache. */ + i = (UINT)media_ptr -> fx_media_sector_cache_size; + cache_entry_ptr = media_ptr -> fx_media_sector_cache; + while (i--) + { + + /* Initialize each of the cache entries. */ + cache_entry_ptr -> fx_cached_sector_memory_buffer = (UCHAR *)memory_ptr; + cache_entry_ptr -> fx_cached_sector = (~(ULONG64)0); + cache_entry_ptr -> fx_cached_sector_buffer_dirty = FX_FALSE; + cache_entry_ptr -> fx_cached_sector_valid = FX_FALSE; + cache_entry_ptr -> fx_cached_sector_next_used = cache_entry_ptr + 1; + + /* Move to the next cache sector entry. */ + cache_entry_ptr++; + + /* Update the memory pointer to the next buffer slot. */ + memory_ptr = (VOID *)(((UCHAR *)memory_ptr) + media_ptr -> fx_media_bytes_per_sector); + } + + /* Backup to the last cache entry to set its next pointer to NULL. */ + cache_entry_ptr--; + cache_entry_ptr -> fx_cached_sector_next_used = FX_NULL; + + /* Remember the last memory address used by the caching logic. */ + media_ptr -> fx_media_sector_cache_end = ((UCHAR *)memory_ptr) - 1; + + /* Setup the head pointer of the list. */ + media_ptr -> fx_media_sector_cache_list_ptr = media_ptr -> fx_media_sector_cache; + + /* Setup the bit map that keeps track of the valid hashed cache logical sectors. */ + media_ptr -> fx_media_sector_cache_hashed_sector_valid = 0; + + /* Clear the counter of the number of outstanding dirty sectors. */ + media_ptr -> fx_media_sector_cache_dirty_count = 0; + + /* Determine if the logical sector cache should be managed by the hash function + instead of the linear search. The cache must be a power of 2 that is between the + minimum and maximum cache size. */ + if ((media_ptr -> fx_media_sector_cache_size >= FX_SECTOR_CACHE_HASH_ENABLE) && + ((media_ptr -> fx_media_sector_cache_size ^ (media_ptr -> fx_media_sector_cache_size - 1)) == + (media_ptr -> fx_media_sector_cache_size | (media_ptr -> fx_media_sector_cache_size - 1)))) + { + + + /* Set the logical sector cache hash flag. When this flag is set, the logical + sector cache is accessed with a hash function instead of a linear search. */ + media_ptr -> fx_media_sector_cache_hashed = FX_TRUE; + media_ptr -> fx_media_sector_cache_hash_mask = + ((media_ptr -> fx_media_sector_cache_size / FX_SECTOR_CACHE_DEPTH) - 1); + } + else + { + + /* Clear the logical sector cache flag. */ + media_ptr -> fx_media_sector_cache_hashed = FX_FALSE; + } +#else + media_ptr -> fx_media_memory_buffer = memory_ptr; +#endif /* FX_DISABLE_CACHE */ + +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + /* Initialize the FAT cache entry array. */ + for (i = 0; i < FX_MAX_FAT_CACHE; i++) + { + + /* Clear entry in the FAT cache. */ + media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_cluster = 0; + media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_value = 0; + media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_dirty = 0; + } + + /* Initialize the secondary FAT update map. */ + for (i = 0; i < FX_FAT_MAP_SIZE; i++) + { + + /* Clear bit map entry for secondary FAT update. */ + media_ptr -> fx_media_fat_secondary_update_map[i] = 0; + } +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type != FX_exFAT) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Root_sector_start has been computed */ + media_ptr -> fx_media_root_sector_start = media_ptr -> fx_media_reserved_sectors + + (media_ptr -> fx_media_number_of_FATs * + media_ptr -> fx_media_sectors_per_FAT); + + /* Calculate the number of directory sectors. */ + media_ptr -> fx_media_root_sectors = + ((media_ptr -> fx_media_root_directory_entries * FX_DIR_ENTRY_SIZE) + + media_ptr -> fx_media_bytes_per_sector - 1) / + media_ptr -> fx_media_bytes_per_sector; + + /* Calculate the starting data sector. */ + media_ptr -> fx_media_data_sector_start = media_ptr -> fx_media_root_sector_start + + media_ptr -> fx_media_root_sectors; + + /* Calculate the total number of clusters. */ + media_ptr -> fx_media_total_clusters = (ULONG)((media_ptr -> fx_media_total_sectors - media_ptr -> fx_media_data_sector_start) / + media_ptr -> fx_media_sectors_per_cluster); + + /* Determine if a 12-bit FAT is in use. */ + if (media_ptr -> fx_media_total_clusters < FX_12_BIT_FAT_SIZE) + { + + /* Yes, 12-bit FAT is present. Set flag accordingly. */ + media_ptr -> fx_media_12_bit_FAT = FX_TRUE; + media_ptr -> fx_media_32_bit_FAT = FX_FALSE; +#ifdef FX_ENABLE_EXFAT + media_ptr -> fx_media_FAT_type = FX_FAT12; +#endif /* FX_ENABLE_EXFAT */ + + /* No additional information sector in FAT12. */ + media_ptr -> fx_media_FAT32_additional_info_sector = 0; + + /* Set FAT last and FAT reserved. */ + media_ptr -> fx_media_fat_reserved = FX_RESERVED_1; + media_ptr -> fx_media_fat_last = FX_LAST_CLUSTER_2; + } + else if (media_ptr -> fx_media_total_clusters < FX_16_BIT_FAT_SIZE) + { + + /* A 16-bit FAT is present. Set flag accordingly. */ + media_ptr -> fx_media_12_bit_FAT = FX_FALSE; + media_ptr -> fx_media_32_bit_FAT = FX_FALSE; +#ifdef FX_ENABLE_EXFAT + media_ptr -> fx_media_FAT_type = FX_FAT16; +#endif /* FX_ENABLE_EXFAT */ + + /* No additional information sector in FAT16. */ + media_ptr -> fx_media_FAT32_additional_info_sector = 0; + + /* Set FAT last and FAT reserved. */ + media_ptr -> fx_media_fat_reserved = FX_RESERVED_1; + media_ptr -> fx_media_fat_last = FX_LAST_CLUSTER_2; + } + else + { + + /* Yes, a 32-bit FAT is present. */ + media_ptr -> fx_media_12_bit_FAT = FX_FALSE; + media_ptr -> fx_media_32_bit_FAT = FX_TRUE; +#ifdef FX_ENABLE_EXFAT + media_ptr -> fx_media_FAT_type = FX_FAT32; +#endif /* FX_ENABLE_EXFAT */ + + /* Save the additional information sector FAT32. This was read from the boot + sector earlier in this routine. */ + media_ptr -> fx_media_FAT32_additional_info_sector = additional_info_sector; + + /* Set FAT last and FAT reserved. */ + media_ptr -> fx_media_fat_reserved = FX_RESERVED_1_32; + media_ptr -> fx_media_fat_last = FX_LAST_CLUSTER_2_32; + } +#ifdef FX_ENABLE_EXFAT + } + else + { + + /* Set FAT last and FAT reserved. */ + media_ptr -> fx_media_fat_reserved = FX_RESERVED_1_exFAT; + media_ptr -> fx_media_fat_last = FX_LAST_CLUSTER_exFAT; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Determine if a 32-bit FAT is present. If so, calculate the size of the root directory (since + it is variable in FAT32. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_32_bit_FAT == FX_TRUE || + (media_ptr -> fx_media_FAT_type == FX_exFAT)) +#else + if (media_ptr -> fx_media_32_bit_FAT == FX_TRUE) +#endif /* FX_ENABLE_EXFAT */ + { +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_32_bit_FAT == FX_TRUE) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Root First cluster starts from at least cluster 2, or higher. */ + if (media_ptr -> fx_media_root_cluster_32 < FX_FAT_ENTRY_START) + { + return(FX_MEDIA_INVALID); + } + + /* Calculate logical number of root dir sector. */ + media_ptr -> fx_media_root_sector_start = media_ptr -> fx_media_data_sector_start + + (media_ptr -> fx_media_root_cluster_32 - FX_FAT_ENTRY_START) * + media_ptr -> fx_media_sectors_per_cluster; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Calculate maximum possible value for fx_media_root_directory_entries */ + i = 0; + for (cluster_number = media_ptr -> fx_media_root_cluster_32;;) + { + + status = _fx_utility_FAT_entry_read(media_ptr, cluster_number, &FAT_entry); + i++; + /* Determine if the read was successful. */ + if (status != FX_SUCCESS) + { + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + return(FX_FAT_READ_ERROR); + } + + if ((cluster_number == FAT_entry) || (i > media_ptr -> fx_media_total_clusters)) + { + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + return(FX_FAT_READ_ERROR); + } + if (FAT_entry >= FX_RESERVED_1_32) + { + break; + } + cluster_number = FAT_entry; + } + + /* Calculate the number of directory entries. */ + media_ptr -> fx_media_root_directory_entries = (i * media_ptr -> fx_media_sectors_per_cluster * + media_ptr -> fx_media_bytes_per_sector) / FX_DIR_ENTRY_SIZE; + } + +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + /* Calculate the number of available clusters. */ + media_ptr -> fx_media_available_clusters = 0; + + /* Set the cluster search start to an invalid value. */ + media_ptr -> fx_media_cluster_search_start = 0; +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + + /* Determine if there is 32-bit FAT additional information sector. */ + if (media_ptr -> fx_media_FAT32_additional_info_sector) + { + + UCHAR *buffer_ptr; + ULONG signature; + + + /* Yes, read the FAT32 additional information sector to get the available cluster count and + the hint for the first available cluster. */ + +#ifndef FX_DISABLE_CACHE + /* Setup a pointer to the first cached entry's buffer. */ + buffer_ptr = (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector_memory_buffer; + + /* Invalidate this cache entry. */ + (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector = (~((ULONG64) 0)); + (media_ptr -> fx_media_sector_cache_list_ptr) -> fx_cached_sector_valid = FX_FALSE; +#else + buffer_ptr = media_ptr -> fx_media_memory_buffer; +#endif /* FX_DISABLE_CACHE */ + + /* Read the FAT32 additional information sector from the device. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = buffer_ptr; + media_ptr -> fx_media_driver_logical_sector = media_ptr -> fx_media_FAT32_additional_info_sector; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_DIRECTORY_SECTOR; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver read sector(s) requests. */ + media_ptr -> fx_media_driver_read_requests++; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_READ, media_ptr, media_ptr -> fx_media_FAT32_additional_info_sector, 1, buffer_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the FAT32 additional information sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the FAT32 sector was read correctly. */ + if (media_ptr -> fx_media_driver_status == FX_SUCCESS) + { + + /* Yes, setup a pointer into the FAT32 additional information sector. */ + buffer_ptr = media_ptr -> fx_media_driver_buffer; + + /* Pickup the first signature long word. */ + signature = _fx_utility_32_unsigned_read(&buffer_ptr[0]); + + /* Determine if the signature is correct. */ + if (signature == 0x41615252) + { + + /* Yes, the first signature is correct, now pickup the next signature. */ + signature = _fx_utility_32_unsigned_read(&buffer_ptr[484]); + + /* Determine if this signature is correct. */ + if (signature == 0x61417272) + { + + /* Yes, we have a good FAT32 additional information sector. */ + + /* Pickup the current available cluster count on the media. */ + media_ptr -> fx_media_available_clusters = _fx_utility_32_unsigned_read(&buffer_ptr[488]); + + /* Initialize the last reported available cluster count to the same value. */ + media_ptr -> fx_media_FAT32_additional_info_last_available = media_ptr -> fx_media_available_clusters; + + /* Pickup the hint for the starting free cluster search. */ + media_ptr -> fx_media_cluster_search_start = _fx_utility_32_unsigned_read(&buffer_ptr[492]); + + /* Perform a quick sanity check on the available cluster count and the starting free + cluster search. */ + if ((media_ptr -> fx_media_available_clusters > media_ptr -> fx_media_total_clusters) || + (media_ptr -> fx_media_cluster_search_start > media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) || + (media_ptr -> fx_media_cluster_search_start < FX_FAT_ENTRY_START)) + { + + /* Something is wrong, clear the available cluster count and search so the regular processing + is used. */ + media_ptr -> fx_media_available_clusters = 0; + media_ptr -> fx_media_cluster_search_start = 0; + + /* We don't invalidate the additional info sector here because only the data is bad. */ + } + } + else + { + + /* Signature is bad, invalidate the additional info sector. */ + media_ptr -> fx_media_FAT32_additional_info_sector = 0; + } + } + else + { + + /* Signature is bad, invalidate the additional info sector. */ + media_ptr -> fx_media_FAT32_additional_info_sector = 0; + } + } + else + { + + /* IO error trying to read additional information sector, invalidate the additional info sector. */ + media_ptr -> fx_media_FAT32_additional_info_sector = 0; + } + } + + /* Search the media to find the first available cluster as well as the total + available clusters. */ + + /* Determine what type of FAT is present. */ + if (media_ptr -> fx_media_12_bit_FAT) + { + + /* A 12-bit FAT is present. Utilize the FAT entry read utility to pickup + each FAT entry's contents. */ + + /* Loop to read each cluster entry in the first FAT. */ + for (cluster_number = FX_FAT_ENTRY_START; + cluster_number < (media_ptr -> fx_media_total_clusters) + FX_FAT_ENTRY_START; + cluster_number++) + { + + /* Read a FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster_number, &FAT_entry); + + /* Determine if the read was successful. */ + if (status != FX_SUCCESS) + { + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + return(FX_FAT_READ_ERROR); + } + + /* Now determine if the FAT entry is available. */ + if (FAT_entry == FX_FREE_CLUSTER) + { + + /* Increment the number of available clusters. */ + media_ptr -> fx_media_available_clusters++; + + /* Determine if the starting free cluster has been found yet. */ + if (media_ptr -> fx_media_cluster_search_start == 0) + { + + /* Remember the first free cluster to start further searches from. */ + media_ptr -> fx_media_cluster_search_start = cluster_number; + } + } + } + } +#ifdef FX_ENABLE_EXFAT + else if ((media_ptr -> fx_media_available_clusters == 0) + && (media_ptr -> fx_media_FAT_type != FX_exFAT)) +#else + else if (media_ptr -> fx_media_available_clusters == 0) +#endif /* FX_ENABLE_EXFAT */ + { + + /* A 16 or 32-bit FAT is present. Read directly into the logical sector + cache memory to optimize I/O on larger devices. Since we are looking for + values of zero, endian issues are not important. */ + + /* Invalidate the current logical sector cache. */ + _fx_utility_logical_sector_flush(media_ptr, ((ULONG64) 1), (ULONG64) (media_ptr -> fx_media_total_sectors), FX_TRUE); + + /* Reset the memory pointer. */ + media_ptr -> fx_media_memory_buffer = original_memory_ptr; + + /* Loop through all FAT sectors in the primary FAT. The first two entries are + examined in this loop, but they are always unavailable. */ + cluster_number = 0; +#ifndef FX_DISABLE_CACHE + for (i = 0; i < media_ptr -> fx_media_sectors_per_FAT; i = i + media_ptr -> fx_media_sector_cache_size) + { + + /* Calculate the starting next FAT sector. */ + FAT_sector = media_ptr -> fx_media_reserved_sectors + i; + + /* Calculate how many sectors to read. */ + FAT_read_sectors = media_ptr -> fx_media_sectors_per_FAT - i; + + /* Determine if there is not enough memory to read the remaining FAT sectors. */ + if (FAT_read_sectors > media_ptr -> fx_media_sector_cache_size) + { + FAT_read_sectors = media_ptr -> fx_media_sector_cache_size; + } +#else + for (i = 0; i < media_ptr -> fx_media_sectors_per_FAT; i++) + { + + /* Calculate the starting next FAT sector. */ + FAT_sector = media_ptr -> fx_media_reserved_sectors + i; + + /* Calculate how many sectors to read. */ + FAT_read_sectors = 1; +#endif /* FX_DISABLE_CACHE */ + + /* Read the FAT sectors directly from the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; + media_ptr -> fx_media_driver_logical_sector = FAT_sector; + media_ptr -> fx_media_driver_sectors = FAT_read_sectors; + media_ptr -> fx_media_driver_sector_type = FX_FAT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_READ, media_ptr, FAT_sector, FAT_read_sectors, media_ptr -> fx_media_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the FAT sectors. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the read was successful. */ + if (media_ptr -> fx_media_driver_status != FX_SUCCESS) + { + + /* Build the "uninitialize" I/O driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_UNINIT; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_UNINIT, media_ptr, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the specified I/O driver with the uninitialize request. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + return(FX_FAT_READ_ERROR); + } + + /* Calculate the number of bytes in the buffer. */ + bytes_in_buffer = (media_ptr -> fx_media_bytes_per_sector * FAT_read_sectors); + + /* Walk through the sector cache memory to search for available clusters and the first + available if not already found. */ + for (j = 0; j < bytes_in_buffer;) + { + + /* Check for a 32-bit FAT. */ + if (media_ptr -> fx_media_32_bit_FAT) + { + + /* Pickup 32-bit FAT entry. */ + FAT_entry = *((ULONG *)&(media_ptr -> fx_media_memory_buffer[j])); + + /* Advance to next FAT entry. */ + j = j + 4; + } + else + { + + /* Process a 16-bit FAT entry. */ + FAT_entry = (((ULONG)(media_ptr -> fx_media_memory_buffer[j])) & 0xFF) | + ((((ULONG)(media_ptr -> fx_media_memory_buffer[j + 1])) & 0xFF) << 8); + + /* Advance to next FAT entry. */ + j = j + 2; + } + + /* Determine if the FAT entry is free. */ + if (FAT_entry == FX_FREE_CLUSTER) + { + + /* Entry is free, increment available clusters. */ + media_ptr -> fx_media_available_clusters++; + + /* Determine if the starting free cluster has been found yet. */ + if (media_ptr -> fx_media_cluster_search_start == 0) + { + + /* Remember the first free cluster to start further searches from. */ + media_ptr -> fx_media_cluster_search_start = cluster_number; + } + } + + /* Increment the cluster number. */ + cluster_number++; + + /* Determine if we have reviewed all FAT entries. */ + if (cluster_number >= (media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START)) + { + + /* Yes, we have looked at all the FAT entries. */ + + /* Ensure that the outer loop terminates as well. */ + i = media_ptr -> fx_media_sectors_per_FAT; + break; + } + } + } + } +#ifdef FX_ENABLE_EXFAT + else if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + status = _fx_utility_exFAT_bitmap_initialize(media_ptr); + + if ((FX_SUCCESS != status) && + (FX_NO_MORE_SPACE != status)) + { + return(status); + } + } +#endif /* FX_ENABLE_EXFAT */ + + /* If there were no free clusters, just set the search pointer to the + first cluster number. */ + if (media_ptr -> fx_media_cluster_search_start == 0) + { + media_ptr -> fx_media_cluster_search_start = FX_FAT_ENTRY_START; + } + + /* Setup the current working directory fields to default to the root + directory. */ + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name = + media_ptr -> fx_media_default_path.fx_path_name_buffer; + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_short_name[0] = 0; + media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name[0] = 0; + media_ptr -> fx_media_default_path.fx_path_string[0] = (CHAR)0; + media_ptr -> fx_media_default_path.fx_path_string[FX_MAXIMUM_PATH - 1] = (CHAR)0; + media_ptr -> fx_media_default_path.fx_path_current_entry = 0; + +#ifndef FX_MEDIA_DISABLE_SEARCH_CACHE + + /* Invalidate the previously found directory entry. */ + media_ptr -> fx_media_last_found_name[0] = 0; +#endif + +#ifndef FX_DISABLE_FORCE_MEMORY_OPERATION + /* Initialize the opened file linked list and associated counter. */ + media_ptr -> fx_media_opened_file_list = FX_NULL; + media_ptr -> fx_media_opened_file_count = 0; +#endif /* FX_DISABLE_FORCE_MEMORY_OPERATION */ + + /* Create the media protection structure if FX_SINGLE_THREAD is not + defined. */ +#ifndef FX_SINGLE_THREAD + +#ifndef FX_DONT_CREATE_MUTEX + + /* Create ThreadX mutex for protection. */ + tx_mutex_create(&(media_ptr -> fx_media_protect), "FileX Media Mutex", TX_NO_INHERIT); +#endif + +#endif + +#ifdef FX_DONT_CREATE_MUTEX + + /* Load the media ID field in the media control block. This allows the FX_PROTECT + call to succeed. */ + media_ptr -> fx_media_id = (ULONG)FX_MEDIA_ID; + + /* Protect against other threads accessing the media. */ + FX_PROTECT +#endif + + /* Lockout interrupts. */ + FX_DISABLE_INTS + + /* At this point, the media has been opened successfully. Place the + media on the linked list of currently opened media. */ + + /* Load the media ID field in the media control block. */ + media_ptr -> fx_media_id = (ULONG)FX_MEDIA_ID; + + /* Place the thread on the list of opened media. First, + check for an empty list. */ + if (_fx_system_media_opened_ptr) + { + + /* Pickup tail pointer. */ + tail_ptr = _fx_system_media_opened_ptr -> fx_media_opened_previous; + + /* Place the new media in the list. */ + _fx_system_media_opened_ptr -> fx_media_opened_previous = media_ptr; + tail_ptr -> fx_media_opened_next = media_ptr; + + /* Setup this media's opened links. */ + media_ptr -> fx_media_opened_previous = tail_ptr; + media_ptr -> fx_media_opened_next = _fx_system_media_opened_ptr; + } + else + { + + /* The opened media list is empty. Add the media to empty list. */ + _fx_system_media_opened_ptr = media_ptr; + media_ptr -> fx_media_opened_next = media_ptr; + media_ptr -> fx_media_opened_previous = media_ptr; + } + + /* Increment the opened media counter. */ + _fx_system_media_opened_count++; + + /* Invoke media open callback. */ + if (media_ptr -> fx_media_open_notify) + { + media_ptr -> fx_media_open_notify(media_ptr); + } + + /* Restore interrupts. */ + FX_RESTORE_INTS + +#ifdef FX_DONT_CREATE_MUTEX + + /* Release media protection. */ + FX_UNPROTECT +#endif + + /* Return a successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_open_notify_set.c b/src/Middlewares/ST/filex/common/src/fx_media_open_notify_set.c new file mode 100644 index 00000000..eaa98960 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_open_notify_set.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_open_notify_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the notify function called when media is open. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* media_open_notify Notify function called when */ +/* media is open */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_open_notify_set(FX_MEDIA *media_ptr, VOID (*media_open_notify)(FX_MEDIA *media)) +{ + + /* Set the notify function. */ + media_ptr -> fx_media_open_notify = media_open_notify; + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_read.c b/src/Middlewares/ST/filex/common/src/fx_media_read.c new file mode 100644 index 00000000..3a8f1287 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_read.c @@ -0,0 +1,127 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the specified raw logical sector from the */ +/* specified media. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Logical sector to read */ +/* buffer_ptr Pointer to caller's buffer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_read Logical sector read utility */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_read(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr) +{ + +UINT status; + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_reads++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_READ, media_ptr, logical_sector, buffer_ptr, 0, FX_TRACE_MEDIA_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Read the logical sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, buffer_ptr, ((ULONG) 1), FX_DATA_SECTOR); + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check for successful status. */ + if (status == FX_SUCCESS) + { + + /* Update the trace event with the bytes read. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_MEDIA_READ, 0, 0, 0, media_ptr -> fx_media_bytes_per_sector) + } +#endif + + /* Release media protection. */ + FX_UNPROTECT + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_space_available.c b/src/Middlewares/ST/filex/common/src/fx_media_space_available.c new file mode 100644 index 00000000..6ef89463 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_space_available.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_space_available PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the number of bytes available in the */ +/* specified media. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* available_bytes_ptr Pointer to available bytes */ +/* destination */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* _fx_media_extended_space_available Actual space available service*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_space_available(FX_MEDIA *media_ptr, ULONG *available_bytes_ptr) +{ + +UINT status; +ULONG64 available_bytes; + + /* Call actual media space available service. */ + status = _fx_media_extended_space_available(media_ptr, &available_bytes); + + /* Check status. */ + if (status == FX_SUCCESS) + { + + /* Determine if more than 4GB available. */ + if (available_bytes > 0x00000000FFFFFFFF) + { + + /* Yes, we must have more than 4GB available... report the maximum we can fit + in 32bits, which is 4GB. */ + *available_bytes_ptr = 0xFFFFFFFF; + } + else + { + *available_bytes_ptr = (ULONG)(available_bytes); + } + } + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_volume_get.c b/src/Middlewares/ST/filex/common/src/fx_media_volume_get.c new file mode 100644 index 00000000..d28da076 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_volume_get.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_media.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_volume_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the volume name stored in the media's boot */ +/* record or root directory. */ +/* */ +/* Note, this API is deprecated as fx_media_volume_get_extended should */ +/* be used. The maximum written size to volume_name could be 12. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* volume_name Pointer to destination for */ +/* the volume name (maximum */ +/* 11 characters + NULL) */ +/* volume_source Source of volume */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_volume_get_extended Actual media volume get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_volume_get(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_source) +{ + + /* Call the extended version with 12 bytes volume name length. */ + return(_fx_media_volume_get_extended(media_ptr, volume_name, 12, volume_source)); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c b/src/Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c new file mode 100644 index 00000000..8aa1c6d5 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_volume_get_extended.c @@ -0,0 +1,375 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_media.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_volume_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the volume name stored in the media's boot */ +/* record or root directory. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* volume_name Pointer to destination for */ +/* the volume name (maximum */ +/* 11 characters + NULL) */ +/* volume_name_buffer_length Buffer length for volume_name */ +/* volume_source Source of volume */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_read Read directory sector */ +/* _fx_directory_entry_read Directory entry read */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_volume_get_extended(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_name_buffer_length, UINT volume_source) +{ + +UINT status, offset; +ULONG i; +INT j; + +#ifdef FX_ENABLE_EXFAT +ULONG character_count; +#endif /* FX_ENABLE_EXFAT */ +FX_DIR_ENTRY dir_entry; + + + /* Clear the volume name. */ + volume_name[0] = FX_NULL; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_VOLUME_GET, media_ptr, volume_name, volume_source, 0, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + volume_source = FX_DIRECTORY_SECTOR; + } +#endif /* FX_ENABLE_EXFAT */ + + /* Ensure the volume name is NULL initially. */ + volume_name[0] = FX_NULL; + + if (volume_source == FX_DIRECTORY_SECTOR) + { + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Attempt to find the volume name in the root directory. */ + i = 0; + do + { + + /* Read an entry from the root directory. */ + status = _fx_directory_entry_read(media_ptr, FX_NULL, &i, &dir_entry); + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return to caller. */ + return(status); + } + + /* Check for a volume name. */ +#ifdef FX_ENABLE_EXFAT + if (dir_entry.fx_dir_entry_attributes & FX_VOLUME || dir_entry.fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_VOLUME_LABEL) +#else + if (dir_entry.fx_dir_entry_attributes & FX_VOLUME) +#endif /* FX_ENABLE_EXFAT */ + { + + /* Yes, we have found a previously set volume name. */ + break; + } + + /* Move to next directory entry. */ + i++; + } while (i < media_ptr -> fx_media_root_directory_entries); + + /* Determine if a volume entry has been found. */ + if (i < media_ptr -> fx_media_root_directory_entries) + { + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) dir_entry.fx_dir_entry_log_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error code. */ + return(status); + } + + /* Offset to volume label entry. */ + offset = dir_entry.fx_dir_entry_byte_offset; + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Read character count of volume label. */ + character_count = media_ptr -> fx_media_memory_buffer[offset + FX_EXFAT_CHAR_COUNT]; + + /* Check if the buffer is too short for the name. */ + if (character_count >= volume_name_buffer_length) + { + + /* Buffer too short, return error. */ + status = FX_BUFFER_ERROR; + + /* Set character count to fit for the buffer. */ + character_count = volume_name_buffer_length - 1; + } + + /* Move to volume label field. */ + offset += FX_EXFAT_VOLUME_LABEL; + + for (i = 0; i < character_count; i++) + { + + /* Read one character of volume label. */ + volume_name[i] = (CHAR)_fx_utility_16_unsigned_read(&media_ptr -> fx_media_memory_buffer[offset]); + + /* Move to next character. */ + offset += 2; + } + + /* NULL terminate the volume name. */ + volume_name[i] = FX_NULL; + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* Skip trailing space characters of volume name. */ + for (j = 10; j >= 0; j--) + { + + /* Check for space character. */ + if (media_ptr -> fx_media_memory_buffer[offset + (UINT)j] != (UCHAR)' ') + { + + /* Last character found. */ + break; + } + } + + /* Check if the buffer is too short for the name. */ + if (j >= (INT)volume_name_buffer_length - 1) + { + + /* Buffer too short, return error. */ + status = FX_BUFFER_ERROR; + + /* Set character count to fit for the buffer. */ + j = (INT)volume_name_buffer_length - 2; + } + + /* NULL terminate the volume name. */ + volume_name[j + 1] = FX_NULL; + + /* Pickup the remaining characters of the volume name from the boot sector. */ + for (; j >= 0; j--) + { + + /* Pickup byte of volume name. */ + volume_name[j] = (CHAR)media_ptr -> fx_media_memory_buffer[offset + (UINT)j]; + } +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the completion status. */ + return(status); + } + } + + /* Read volume name from boot record. */ + /* Read the logical directory sector 0 - we just do this to get a memory_buffer pointer */ + status = _fx_utility_logical_sector_read(media_ptr, ((ULONG64) 0), + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver read boot sector requests. */ + media_ptr -> fx_media_driver_boot_read_requests++; +#endif + + /* Build the driver request to read the boot record. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_BOOT_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_BOOT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_BOOT_READ, media_ptr, media_ptr -> fx_media_memory_buffer, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the boot sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the request is successful. */ + if (media_ptr -> fx_media_driver_status) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* An error occurred in the driver. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Calculate the offset to the volume name based on the type of FAT. */ + if (media_ptr -> fx_media_32_bit_FAT) + { + + /* FAT32 offset to volume name. */ + offset = FX_VOLUME_LABEL_32; + } + else + { + + /* FAT12/16 offset to volume name. */ + offset = FX_VOLUME_LABEL; + } + + /* Skip trailing space characters of volume name. */ + for (j = 10; j >= 0; j--) + { + + /* Check for space character. */ + if (media_ptr -> fx_media_memory_buffer[offset + (UINT)j] != (UCHAR)' ') + { + + /* Last character found. */ + break; + } + } + + /* Check if the buffer is too short for the name. */ + if (j >= (INT)volume_name_buffer_length - 1) + { + + /* Buffer too short, return error. */ + status = FX_BUFFER_ERROR; + + /* Set character count to fit for the buffer. */ + j = (INT)volume_name_buffer_length - 2; + } + + /* NULL terminate the volume name. */ + volume_name[j + 1] = FX_NULL; + + /* Pickup the remaining characters of the volume name from the boot sector. */ + for (; j >= 0; j--) + { + + /* Pickup byte of volume name. */ + volume_name[j] = (CHAR)media_ptr -> fx_media_memory_buffer[offset + (UINT)j]; + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_volume_set.c b/src/Middlewares/ST/filex/common/src/fx_media_volume_set.c new file mode 100644 index 00000000..28bc1449 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_volume_set.c @@ -0,0 +1,564 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_media.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#endif /* FX_ENABLE_EXFAT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_volume_set PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the volume name to the name supplied by the */ +/* caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* volume_name New volume name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_entry_read Read a directory entry */ +/* _fx_utility_logical_sector_read Read directory sector */ +/* _fx_utility_logical_sector_write Write directory sector */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 06-02-2021 Bhupendra Naphade Modified comment(s),updated */ +/* the initialization of */ +/* dir_entry for exFAT format, */ +/* resulting in version 6.1.7 */ +/* */ +/**************************************************************************/ +UINT _fx_media_volume_set(FX_MEDIA *media_ptr, CHAR *volume_name) +{ + +ULONG i, j; +FX_DIR_ENTRY dir_entry, dir_entry1; +UINT status, offset; +UCHAR *work_ptr; +CHAR alpha; + + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + dir_entry.fx_dir_entry_log_sector = 0; + dir_entry.fx_dir_entry_byte_offset = 0; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_VOLUME_SET, media_ptr, volume_name, 0, 0, FX_TRACE_MEDIA_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Attempt to find the volume name in the root directory. */ + i = 0; + do + { + + /* Read an entry from the root directory. */ + status = _fx_directory_entry_read(media_ptr, FX_NULL, &i, &dir_entry); + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return to caller. */ + return(status); + } + + /* Check for a volume name. */ + if (dir_entry.fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_VOLUME_LABEL) + { + + /* Yes, we have found a previously set volume name. */ + break; + } + + /* Move to next directory entry. */ + i++; + } while (i < media_ptr -> fx_media_root_directory_entries); + + /* Determine if a volume entry has been found. */ + if (i == media_ptr -> fx_media_root_directory_entries) + { + + /* Volume entry not found, attempt to find a free entry in the root directory. */ + i = 0; + do + { + + /* Read an entry from the root directory. */ + status = _fx_directory_entry_read(media_ptr, FX_NULL, &i, &dir_entry); + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return to caller. */ + return(status); + } + + /* Check for a volume name. */ + if (dir_entry.fx_dir_entry_type == FX_EXFAT_DIR_ENTRY_TYPE_FREE) + { + + /* Yes, we have found a free directory entry. */ + break; + } + + /* Move to next directory entry. */ + i++; + } while (i < media_ptr -> fx_media_root_directory_entries); + + /* Determine if a free entry has been found. */ + if (i == media_ptr -> fx_media_root_directory_entries) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* No existing volume name was found, return an error. */ + return(FX_NOT_FOUND); + } + } + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) dir_entry.fx_dir_entry_log_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error code. */ + return(status); + } + + /* Offset to volume label field. */ + offset = dir_entry.fx_dir_entry_byte_offset + FX_EXFAT_VOLUME_LABEL; + + /* Loop to store the volume name. */ + for (i = 0; volume_name[i]; i++) + { + + /* Have we reached the end? */ + if (i == 11) + { + + break; + } + + /* Pickup volume name byte. */ + alpha = volume_name[i]; + + /* Store a byte of the volume name. */ + _fx_utility_16_unsigned_write(&media_ptr -> fx_media_memory_buffer[offset], (UINT)alpha); + + /* Move to next character. */ + offset += 2; + } + + /* Offset to character count field. */ + offset = dir_entry.fx_dir_entry_byte_offset; + + /* Store volume label entry type. */ + media_ptr -> fx_media_memory_buffer[offset] = FX_EXFAT_DIR_ENTRY_TYPE_VOLUME_LABEL; + + /* Store the character count. */ + media_ptr -> fx_media_memory_buffer[offset + FX_EXFAT_CHAR_COUNT] = (UCHAR)i; + + /* Write the directory sector to the media. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) dir_entry.fx_dir_entry_log_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + } + else + { +#endif /* FX_ENABLE_EXFAT */ + + /* First, check for an invalid volume name. */ + if (volume_name[0] == 0) + { + + /* Yes, volume name is invalid. Return an error. */ + return(FX_INVALID_NAME); + } + + /* Read the logical directory sector 0 - we just do this to get a memory_buffer pointer */ + status = _fx_utility_logical_sector_read(media_ptr, ((ULONG64) 0), + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DATA_SECTOR); + + /* Check the read status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver read boot sector requests. */ + media_ptr -> fx_media_driver_boot_read_requests++; +#endif + + /* Build a driver request to read the boot record. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_BOOT_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_BOOT_SECTOR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_BOOT_READ, media_ptr, media_ptr -> fx_media_memory_buffer, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the boot sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Determine if the request is successful. */ + if (media_ptr -> fx_media_driver_status) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* An error occurred in the driver. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Calculate the offset based on the FAT present. */ + if (media_ptr -> fx_media_32_bit_FAT) + { + + /* FAT32 is present. */ + offset = FX_VOLUME_LABEL_32; + } + else + { + + /* FAT12/16 is present. */ + offset = FX_VOLUME_LABEL; + } + + /* Loop to store the volume name. */ + for (i = 0; volume_name[i]; i++) + { + + /* Have we reached the end? */ + if (i == 11) + { + + break; + } + + /* Pickup volume name byte. */ + alpha = volume_name[i]; + + /* Determine if alpha needs to be converted to upper case. */ + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Convert alpha to upper case. */ + alpha = (CHAR)((INT)alpha - 0x20); + } + + /* Store a byte of the volume name. */ + media_ptr -> fx_media_memory_buffer[offset + i] = (UCHAR)alpha; + } + + /* Now pad with spaces. */ + for (; i < 11; i++) + { + + /* Append space character to volume name. */ + media_ptr -> fx_media_memory_buffer[offset + i] = 0x20; + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write boot sector requests. */ + media_ptr -> fx_media_driver_boot_write_requests++; +#endif + + /* Write the boot sector with the new volume name. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_BOOT_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = media_ptr -> fx_media_memory_buffer; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = FX_BOOT_SECTOR; + + /* Set the system write flag since we are writing the boot sector. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_BOOT_WRITE, media_ptr, media_ptr -> fx_media_memory_buffer, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the boot sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Determine if the request is successful. */ + if (media_ptr -> fx_media_driver_status) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* An error occurred in the driver. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Setup pointer to media name buffer. */ + dir_entry1.fx_dir_entry_name = media_ptr -> fx_media_name_buffer; + + /* Clear the short name string. */ + dir_entry1.fx_dir_entry_short_name[0] = 0; + + /* Now we need to find the copy of the volume name in the root directory. */ + i = 0; + j = media_ptr -> fx_media_root_directory_entries + 1; + do + { + + /* Read an entry from the root directory. */ + status = _fx_directory_entry_read(media_ptr, FX_NULL, &i, &dir_entry1); + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return to caller. */ + return(status); + } + + /* Determine if this is an empty entry. */ + if ((dir_entry1.fx_dir_entry_name[0] == (CHAR)FX_DIR_ENTRY_FREE) && (dir_entry1.fx_dir_entry_short_name[0] == 0)) + { + + /* Yes, this is free entry. Is it the first? */ + if (i < j) + { + + /* Yes, first free entry - remember it. */ + dir_entry = dir_entry1; + j = i; + } + } + /* Determine if the directory entries are exhausted. */ + else if (dir_entry1.fx_dir_entry_name[0] == FX_DIR_ENTRY_DONE) + { + + /* Yes, this we are at the end of the directory. Have there + been any other free entries? */ + if (i < j) + { + + /* No, we need to remember this as the free entry. */ + dir_entry = dir_entry1; + j = i; + } + break; + } + /* Check for a volume name. */ + else if (dir_entry1.fx_dir_entry_attributes & FX_VOLUME) + { + + /* Yes, we have found a previously set volume name - use this entry. */ + dir_entry = dir_entry1; + j = i; + break; + } + + /* Move to next directory entry. */ + i++; + } while (i < media_ptr -> fx_media_root_directory_entries); + + /* Determine if a volume entry was not found and there are no more empty slots. */ + if (i == media_ptr -> fx_media_root_directory_entries) + { + + /* Determine if there was a free or previous volume name. */ + if (j == (media_ptr -> fx_media_root_directory_entries + 1)) + { + + /* No, nothing was available in the root directory. */ + + /* Release media protection. */ + FX_UNPROTECT + + /* No, existing volume name or space in the root directly was found, return an error. */ + return(FX_MEDIA_INVALID); + } + } + + /* Now set the volume name and attribute. */ + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) dir_entry.fx_dir_entry_log_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_BOOT_SECTOR); + + /* Check the status of reading the directory entry. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* Calculate pointer into directory buffer. */ + work_ptr = media_ptr -> fx_media_memory_buffer + + (UINT)dir_entry.fx_dir_entry_byte_offset; + + /* Copy the volume name into the directory entry. */ + for (i = 0; volume_name[i]; i++) + { + + /* Have we reached the end? */ + if (i == 11) + { + + break; + } + + /* Pickup volume name byte. */ + alpha = volume_name[i]; + + /* Determine if alpha needs to be converted to upper case. */ + if ((alpha >= 'a') && (alpha <= 'z')) + { + + /* Convert alpha to upper case. */ + alpha = (CHAR)((INT)alpha - 0x20); + } + + /* Store volume name. */ + work_ptr[i] = (UCHAR)alpha; + } + + /* Pad with space characters. */ + for (; i < 11; i++) + { + work_ptr[i] = 0x20; + } + + /* Set the appropriate attributes. */ + work_ptr[11] = FX_VOLUME | FX_ARCHIVE; + + /* Set the other parts of the volume entry. */ + + /* Clear the hi word of cluster. */ + work_ptr[20] = 0; + work_ptr[21] = 0; + + /* Clear the low word of cluster. */ + work_ptr[26] = 0; + work_ptr[27] = 0; + + /* Clear the file size. */ + work_ptr[28] = 0; + work_ptr[29] = 0; + work_ptr[30] = 0; + work_ptr[31] = 0; + + /* Write the directory sector to the media. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) dir_entry.fx_dir_entry_log_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_media_write.c b/src/Middlewares/ST/filex/common/src/fx_media_write.c new file mode 100644 index 00000000..8a96ba6a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_media_write.c @@ -0,0 +1,138 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_media_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes the specified raw logical sector to the */ +/* specified media. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Logical sector to read */ +/* buffer_ptr Pointer to caller's buffer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_write Write logical sector utility */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_media_write(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr) +{ + +UINT status; + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of times this service has been called. */ + media_ptr -> fx_media_writes++; +#endif + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_MEDIA_WRITE, media_ptr, logical_sector, buffer_ptr, 0, FX_TRACE_MEDIA_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Write the logical sector. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) logical_sector, buffer_ptr, ((ULONG) 1), FX_DATA_SECTOR); + +#ifdef TX_ENABLE_EVENT_TRACE + + /* Check for successful status. */ + if (status == FX_SUCCESS) + { + + /* Update the trace event with the bytes written. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_MEDIA_WRITE, 0, 0, 0, media_ptr -> fx_media_bytes_per_sector) + } +#endif + + /* Release media protection. */ + FX_UNPROTECT + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c b/src/Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c new file mode 100644 index 00000000..04c7a20a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_partition_offset_calculate.c @@ -0,0 +1,345 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Application Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_utility.h" + + +/* Define internal data structures. */ + +typedef struct FX_MEDIA_PARTITION_STRUCT +{ + ULONG fx_media_part_start; + ULONG fx_media_part_size; +} FX_MEDIA_PARTITION; + + +/* Define function prototypes for the partition table parsing application + utility. */ + +UINT _fx_partition_offset_calculate(void *partition_sector, UINT partition, + ULONG *partition_start, ULONG *partition_size); +UINT _fx_utility_partition_get(FX_MEDIA_PARTITION *partition_table, + UINT *count, ULONG sector, UCHAR *sector_buffer); + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_partition_offset_calculate PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates the sector offset to the specified */ +/* partition. The buffer containing the partition table is also */ +/* supplied to this function. If the buffer supplied is a boot */ +/* record (which could be the case in non-partition systems), this */ +/* function returns an offset of zero, the total sectors, and a */ +/* successful status indicating that the buffer supplied is the boot */ +/* record. Otherwise, if a partition is found, this function returns */ +/* the sector offset to its boot record along with a successful */ +/* status. If the specified partition is not found or the buffer is */ +/* not a partition table or boot record, this function returns an */ +/* error. */ +/* */ +/* Note: Empty partitions have a FX_SUCCESS return code, however their */ +/* starting sector is FX_NULL and the size returned is 0. */ +/* */ +/* INPUT */ +/* */ +/* partition_sector Pointer to buffer containing */ +/* either the partition table */ +/* or the boot sector */ +/* partition Desired partition */ +/* partition_start Return partition start */ +/* partition_size Return partition size */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_partition_get Actual partition parsing */ +/* routine */ +/* */ +/* CALLED BY */ +/* */ +/* Application Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 04-02-2021 William E. Lamie Modified comment(s), */ +/* ignored signature check for */ +/* no partition situation, */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _fx_partition_offset_calculate(void *partition_sector, UINT partition, + ULONG *partition_start, ULONG *partition_size) +{ + +FX_MEDIA_PARTITION partition_table[4]; +UINT count; +ULONG64 total_sectors; +UCHAR *partition_sector_ptr; + + + /* Setup working pointer and initialize count. */ + partition_sector_ptr = partition_sector; + count = 0; + + /* Check for a real boot sector instead of a partition table. */ + if ((partition_sector_ptr[0] == 0xe9) || ((partition_sector_ptr[0] == 0xeb) && (partition_sector_ptr[2] == 0x90))) + { + + /* Yes, a real boot sector could be present. */ + + /* See if there are good values for sectors per FAT. */ + if (partition_sector_ptr[0x16] || partition_sector_ptr[0x17] || partition_sector_ptr[0x24] || partition_sector_ptr[0x25] || partition_sector_ptr[0x26] || partition_sector_ptr[0x27]) + { + + /* There are values for sectors per FAT. */ + + /* Determine if there is a total sector count. */ + total_sectors = 0; + + if (partition_sector_ptr[0x13] || partition_sector_ptr[0x14]) + { + + /* Calculate the total sectors, FAT12/16. */ + total_sectors = (((ULONG) partition_sector_ptr[0x14]) << 8) | ((ULONG) partition_sector_ptr[0x13]); + } + else if (partition_sector_ptr[0x20] || partition_sector_ptr[0x21] || partition_sector_ptr[0x22] || partition_sector_ptr[0x23]) + { + + /* Calculate the total sectors, FAT32. */ + total_sectors = (((ULONG) partition_sector_ptr[0x23]) << 24) | + (((ULONG) partition_sector_ptr[0x22]) << 16) | + (((ULONG) partition_sector_ptr[0x21]) << 8) | + ((ULONG) partition_sector_ptr[0x20]); + } + + /* Determine if there is a total sector count. */ + if (total_sectors) + { + + if (partition_start != FX_NULL) + { + /* Return an offset of 0, size of boot record, and a successful status. */ + *partition_start = 0; + } + + /* Determine if the total sectors is required. */ + if (partition_size != FX_NULL) + { + + /* Return the total sectors. */ + *partition_size = (ULONG)(total_sectors & 0xFFFFFFFF); + } + + /* Return success! */ + return(FX_SUCCESS); + } + } +#ifdef FX_ENABLE_EXFAT + /* See if there are good values for sectors per exFAT. */ + else if (partition_sector_ptr[0x0b] == 0 && partition_sector_ptr[0x0c] == 0) + { + /* There are values for sectors per exFAT. */ + + /* Calculate the total sectors. */ + total_sectors = _fx_utility_64_unsigned_read(&partition_sector_ptr[FX_EF_VOLUME_LENGTH]); + + /* Determine if there is a total sector count. */ + if (total_sectors) + { + + if (partition_start != FX_NULL) + { + /* Return an offset of 0, size of boot record, and a successful status. */ + *partition_start = 0; + } + + /* Determine if the total sectors is required. */ + if (partition_size != FX_NULL) + { + + if (total_sectors > 0xFFFFFFFF) + { + + /* Overflow. Just return not found. */ + return(FX_NOT_FOUND); + } + + /* Return the total sectors. */ + *partition_size = (ULONG)(total_sectors & 0xFFFFFFFF); + } + + /* Return success! */ + return(FX_SUCCESS); + } + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Check signature to make sure the buffer is valid. */ + if ((partition_sector_ptr[510] != 0x55) || (partition_sector_ptr[511] != 0xAA)) + { + + /* Invalid, return an error. */ + return(FX_NOT_FOUND); + } + + /* Not bootable, look for specific partition. */ + _fx_utility_partition_get(partition_table, &count, 0, partition_sector_ptr); + + /* Determine if return value is valid. */ + if (partition >= count) + { + + /* No, return an error. */ + return(FX_NOT_FOUND); + } + + /* Return the partition starting sector, if non-NULL. */ + if (partition_start != FX_NULL) + { + *partition_start = partition_table[partition].fx_media_part_start; + } + + /* Return the partition size, if non-NULL. */ + if (partition_size != FX_NULL) + { + *partition_size = partition_table[partition].fx_media_part_size; + } + + /* Return successful completion. */ + return(FX_SUCCESS); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_partition_get PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function parses the partition sector and completes the */ +/* supplied partition entry structure. */ +/* */ +/* INPUT */ +/* */ +/* partition_table Pointer to partition table */ +/* count Number of partitions found */ +/* sector Base sector */ +/* sector_buffer Buffer containing partition */ +/* table */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_partition_offset_calculate Calculate partition offset */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 04-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_partition_get(FX_MEDIA_PARTITION *partition_table, + UINT *count, ULONG sector, UCHAR *sector_buffer) +{ + +UINT i; +ULONG base_sector, value; + + /* This parameter has not been supported yet. */ + FX_PARAMETER_NOT_USED(sector); + + /* Initialize base sector. */ + base_sector = 0; + + for(i = 446; i <= 494; i+=16) + { + if (sector_buffer[i + 4] == 0) /* no partition entry here */ + { + + partition_table[*count].fx_media_part_start = 0; + partition_table[*count].fx_media_part_size = 0; + } + else + { + + value = (ULONG) sector_buffer[i + 8]; /* little endian start value */ + value = (((ULONG) sector_buffer[i + 9]) << 8) | value; + value = (((ULONG) sector_buffer[i + 10]) << 16) | value; + value = (((ULONG) sector_buffer[i + 11]) << 24) | value; + partition_table[*count].fx_media_part_start = value + base_sector; + + value = (ULONG) sector_buffer[i + 12]; /* little endian size value */ + value = (((ULONG) sector_buffer[i + 13]) << 8) | value; + value = (((ULONG) sector_buffer[i + 14]) << 16) | value; + value = (((ULONG) sector_buffer[i + 15]) << 24) | value; + partition_table[*count].fx_media_part_size = value; + } + + (*count)++; + } + + /* Return success. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_system_date_get.c b/src/Middlewares/ST/filex/common/src/fx_system_date_get.c new file mode 100644 index 00000000..314f2c76 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_system_date_get.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_system_date_get PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the current contents of the system date in */ +/* the fields specified by the caller. */ +/* */ +/* INPUT */ +/* */ +/* year Pointer to year */ +/* month Pointer to month */ +/* day Pointer to day */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 06-02-2021 William E. Lamie Modified comment(s), */ +/* checked null pointer, */ +/* resulting in version 6.1.7 */ +/* */ +/**************************************************************************/ +UINT _fx_system_date_get(UINT *year, UINT *month, UINT *day) +{ + +UINT date; + + + /* Get a copy of the current date. */ + date = _fx_system_date; + + /* Check to see if the year is required. */ + if (year) + { + + /* Pickup the year. */ + *year = ((date >> FX_YEAR_SHIFT) & FX_YEAR_MASK) + FX_BASE_YEAR; + } + + /* Check to see if the month is required. */ + if (month) + { + + /* Pickup the month. */ + *month = (date >> FX_MONTH_SHIFT) & FX_MONTH_MASK; + } + + /* Check to see if the day is required. */ + if (day) + { + + /* Pickup the day. */ + *day = date & FX_DAY_MASK; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + if (year && month && day) + { + FX_TRACE_IN_LINE_INSERT(FX_TRACE_SYSTEM_DATE_GET, *year, *month, *day, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + } + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_system_date_set.c b/src/Middlewares/ST/filex/common/src/fx_system_date_set.c new file mode 100644 index 00000000..e1bd9bbe --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_system_date_set.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_system_date_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the system date to the date specified by the */ +/* caller. */ +/* */ +/* INPUT */ +/* */ +/* year Year (1980-2107) */ +/* month Month (1-12) */ +/* day Day (1-28/29/30/31) */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_system_date_set(UINT year, UINT month, UINT day) +{ + + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_SYSTEM_DATE_SET, year, month, day, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Set the system date. */ + _fx_system_date = ((year - FX_BASE_YEAR) << FX_YEAR_SHIFT) | + (month << FX_MONTH_SHIFT) | day; + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_system_initialize.c b/src/Middlewares/ST/filex/common/src/fx_system_initialize.c new file mode 100644 index 00000000..3c1682d2 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_system_initialize.c @@ -0,0 +1,207 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Locate FileX control component data in this file. */ + +#define FX_SYSTEM_INIT + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_system_initialize PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the FileX System component. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* tx_timer_create Create system timer */ +/* */ +/* CALLED BY */ +/* */ +/* Application Initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable build options, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _fx_system_initialize(VOID) +{ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_SYSTEM_INITIALIZE, 0, 0, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Initialize the head pointer of the opened media list and the + number of opened media. */ + _fx_system_media_opened_ptr = FX_NULL; + _fx_system_media_opened_count = 0; + + /* Initialize the time and date fields with their default values. */ + _fx_system_date = FX_INITIAL_DATE; + _fx_system_time = FX_INITIAL_TIME; + + /* Initialize the sector and FAT cache sizes. */ + _fx_system_media_max_sector_cache = FX_MAX_SECTOR_CACHE; + _fx_system_media_max_fat_cache = FX_MAX_FAT_CACHE; + + /* Create the FileX system timer. This is responsible for updating + the specified date and time at the rate specified by + FX_UPDATE_RATE_IN_TICKS. Note that the timer is not necessary for + regular FileX operation - it is only needed for accurate system + date and time stamps on files. */ + +#ifndef FX_NO_TIMER + tx_timer_create(&_fx_system_timer, "FileX System Timer", _fx_system_timer_entry, FX_TIMER_ID, + FX_UPDATE_RATE_IN_TICKS, FX_UPDATE_RATE_IN_TICKS, TX_AUTO_ACTIVATE); +#endif + +#ifndef FX_DISABLE_BUILD_OPTIONS + /* Setup the build options variables. */ + + /* Setup the first build options variable. */ + if (FX_MAX_LONG_NAME_LEN > 0xFF) + { + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)0xFF) << 24); + } + else + { + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)(FX_MAX_LONG_NAME_LEN & 0xFF)) << 24); + } + if (FX_MAX_LAST_NAME_LEN > 0xFF) + { + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)0xFF) << 16); + } + else + { + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)(FX_MAX_LAST_NAME_LEN & 0xFF)) << 24); + } + +#ifdef FX_NO_TIMER + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 10); +#endif +#ifdef FX_SINGLE_THREAD + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 9); +#endif +#ifdef FX_DONT_UPDATE_OPEN_FILES + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 8); +#endif +#ifdef FX_MEDIA_DISABLE_SEARCH_CACHE + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 7); +#endif +#ifdef FX_MEDIA_STATISTICS_DISABLE + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 6); +#endif + +#ifdef FX_SINGLE_OPEN_LEGACY + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 4); +#endif +#ifdef FX_RENAME_PATH_INHERIT + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 3); +#endif +#ifdef FX_NO_LOCAL_PATH + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 2); +#endif +#ifdef FX_FAULT_TOLERANT_DATA + _fx_system_build_options_1 = _fx_system_build_options_1 | (((ULONG)1) << 1); +#endif +#ifdef FX_FAULT_TOLERANT + _fx_system_build_options_1 = _fx_system_build_options_1 | ((ULONG)1); +#endif + + /* Setup the second build options variable. */ + if (FX_MAX_SECTOR_CACHE > ((ULONG)0xFFFF)) + { + _fx_system_build_options_2 = _fx_system_build_options_2 | (((ULONG)0xFFFF) << 16); + } + else + { + _fx_system_build_options_2 = _fx_system_build_options_2 | (((ULONG)FX_MAX_SECTOR_CACHE) << 16); + } + if (FX_FAT_MAP_SIZE > 0xFF) + { + _fx_system_build_options_2 = _fx_system_build_options_2 | (((ULONG)0xFF) << 8); + } + else + { + _fx_system_build_options_2 = _fx_system_build_options_2 | (((ULONG)FX_FAT_MAP_SIZE) << 8); + } + if (FX_MAX_FAT_CACHE > 0xFF) + { + _fx_system_build_options_2 = _fx_system_build_options_2 | ((ULONG)0xFF); + } + else + { + _fx_system_build_options_2 = _fx_system_build_options_2 | ((ULONG)FX_MAX_FAT_CACHE); + } + + /* Setup the third build options variable. */ + if (FX_UPDATE_RATE_IN_SECONDS > 0xFF) + { + _fx_system_build_options_3 = _fx_system_build_options_3 | (((ULONG)0xFF) << 16); + } + else + { + _fx_system_build_options_3 = _fx_system_build_options_3 | (((ULONG)FX_UPDATE_RATE_IN_SECONDS) << 16); + } + if (FX_UPDATE_RATE_IN_TICKS > ((ULONG)0xFFFF)) + { + _fx_system_build_options_3 = _fx_system_build_options_3 | ((ULONG)0xFFFF); + } + else + { + _fx_system_build_options_3 = _fx_system_build_options_3 | ((ULONG)FX_UPDATE_RATE_IN_TICKS); + } +#endif /* FX_DISABLE_BUILD_OPTIONS */ +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_system_time_get.c b/src/Middlewares/ST/filex/common/src/fx_system_time_get.c new file mode 100644 index 00000000..b387f8bf --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_system_time_get.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_system_time_get PORTABLE C */ +/* 6.1.7 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the current contents of the system time in */ +/* the fields specified by the caller. */ +/* */ +/* INPUT */ +/* */ +/* hour Pointer to hour */ +/* minute Pointer to minute */ +/* second Pointer to second */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 06-02-2021 William E. Lamie Modified comment(s), */ +/* checked null pointer, */ +/* resulting in version 6.1.7 */ +/* */ +/**************************************************************************/ +UINT _fx_system_time_get(UINT *hour, UINT *minute, UINT *second) +{ + +UINT time; + + + /* Get a copy of the current system time. */ + time = _fx_system_time; + + /* Check to see if the hour is required. */ + if (hour) + { + + /* Pickup the hour. */ + *hour = (time >> FX_HOUR_SHIFT) & FX_HOUR_MASK; + } + + /* Check to see if the minute is required. */ + if (minute) + { + + /* Pickup the minute. */ + *minute = (time >> FX_MINUTE_SHIFT) & FX_MINUTE_MASK; + } + + /* Check to see if the second is required. */ + if (second) + { + + /* Pickup the second. */ + *second = (time & FX_SECOND_MASK) * 2; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + if (hour && minute && second) + { + FX_TRACE_IN_LINE_INSERT(FX_TRACE_SYSTEM_TIME_GET, *hour, *minute, *second, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + } + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_system_time_set.c b/src/Middlewares/ST/filex/common/src/fx_system_time_set.c new file mode 100644 index 00000000..4b31842d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_system_time_set.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_system_time_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function set the system time to the value specified by the */ +/* caller. */ +/* */ +/* INPUT */ +/* */ +/* hour Hour (0-23) */ +/* minute Minute (0-59) */ +/* second Second (0-59) */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_system_time_set(UINT hour, UINT minute, UINT second) +{ + + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_SYSTEM_TIME_SET, hour, minute, second, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Set the new system time. */ + _fx_system_time = (hour << FX_HOUR_SHIFT) | + (minute << FX_MINUTE_SHIFT) | (second / 2); + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_system_timer_entry.c b/src/Middlewares/ST/filex/common/src/fx_system_timer_entry.c new file mode 100644 index 00000000..a35cb64d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_system_timer_entry.c @@ -0,0 +1,343 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_system_timer_entry PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is FileX system timer function. It is called at the */ +/* rate specified by FX_UPDATE_RATE_IN_SECONDS and is responsible for */ +/* maintaining both the system date and time. */ +/* */ +/* INPUT */ +/* */ +/* id Not used */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Initialization */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _fx_system_timer_entry(ULONG id) +{ + +UINT second; +UINT minute; +UINT hour; +UINT day; +UINT month; +UINT year; + + + /* Determine if the ID is valid. */ + if (id == FX_TIMER_ID) + { + + /* Break the current date time into separate fields for easier work! */ + second = (_fx_system_time & FX_SECOND_MASK) * 2; + minute = (_fx_system_time >> FX_MINUTE_SHIFT) & FX_MINUTE_MASK; + hour = (_fx_system_time >> FX_HOUR_SHIFT) & FX_HOUR_MASK; + day = _fx_system_date & FX_DAY_MASK; + month = (_fx_system_date >> FX_MONTH_SHIFT) & FX_MONTH_MASK; + year = ((_fx_system_date >> FX_YEAR_SHIFT) & FX_YEAR_MASK) + FX_BASE_YEAR; + + /* Now apply the "second" update. */ + second = second + FX_UPDATE_RATE_IN_SECONDS; + + /* Determine if we need to adjust the minute field. */ + if (second > FX_MAXIMUM_SECOND) + { + + /* Yes, we need to adjust the minute field. */ + minute = minute + second / 60; + second = second % 60; + + /* Determine if we need to adjust the hour field. */ + if (minute > FX_MAXIMUM_MINUTE) + { + + /* Yes, we need to adjust the hour field. */ + hour = hour + minute / 60; + minute = minute % 60; + + /* Determine if we need to adjust the day field. */ + if (hour > FX_MAXIMUM_HOUR) + { + + /* Yes, we need to adjust the day field. */ + hour = 0; + day++; + + /* Determine if we need to adjust the month field. */ + switch (month) + { + + case 1: /* January */ + { + + /* Check for end of the month. */ + if (day > 31) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 2: /* February */ + { + + /* Check for leap year. We don't need to check for leap + century her (century years divisible by 400) since 2000 + is and this FAT format only supports years to 2107. */ + if ((year % 4) == 0) + { + + /* Leap year in February... check for 29 days + instead of 28. */ + if (day > 29) + { + + /* Adjust the month. */ + day = 1; + month++; + } + } + else + { + + if (day > 28) + { + + /* Adjust the month. */ + day = 1; + month++; + } + } + break; + } + + case 3: /* March */ + { + + /* Check for end of the month. */ + if (day > 31) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 4: /* April */ + { + + /* Check for end of the month. */ + if (day > 30) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 5: /* May */ + { + + /* Check for end of the month. */ + if (day > 31) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 6: /* June */ + { + + /* Check for end of the month. */ + if (day > 30) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 7: /* July */ + { + + /* Check for end of the month. */ + if (day > 31) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 8: /* August */ + { + + /* Check for end of the month. */ + if (day > 31) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 9: /* September */ + { + + /* Check for end of the month. */ + if (day > 30) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 10: /* October */ + { + + /* Check for end of the month. */ + if (day > 31) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 11: /* November */ + { + + /* Check for end of the month. */ + if (day > 30) + { + + /* Move to next month. */ + day = 1; + month++; + } + break; + } + + case 12: /* December */ + { + + /* Check for end of the month. */ + if (day > 31) + { + + /* Move to next month. */ + day = 1; + month = 1; + + /* Also move to next year. */ + year++; + + /* Check for a year that exceeds the representation + in this format. */ + if (year > FX_MAXIMUM_YEAR) + { + return; + } + } + break; + } + + default: /* Invalid month! */ + + return; /* Skip updating date/time! */ + } + } + } + } + + /* Now apply the new setting to the internal representation. */ + + /* Set the system date. */ + _fx_system_date = ((year - FX_BASE_YEAR) << FX_YEAR_SHIFT) | + (month << FX_MONTH_SHIFT) | day; + + /* Set the new system time. */ + _fx_system_time = (hour << FX_HOUR_SHIFT) | + (minute << FX_MINUTE_SHIFT) | (second / 2); + } +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_directory_create.c b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_create.c new file mode 100644 index 00000000..1c0dac03 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_create.c @@ -0,0 +1,291 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_directory_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates the specified unicode directory. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_unicode_name Pointer to source unicode name*/ +/* source_unicode_length Unicode name length */ +/* short_name Designated short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search directory */ +/* _fx_unicode_directory_entry_change Change unicode file name */ +/* _fx_unicode_directory_search Search for unicode name */ +/* _fx_directory_create Create a directory */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_directory_create(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, CHAR *short_name) +{ + +FX_DIR_ENTRY dir_entry; +UINT i, status; +ULONG temp_length; +UCHAR destination_shortname[13]; + + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = FX_NULL; + + /* Set destination shortname to null. */ + destination_shortname[0] = FX_NULL; + + /* Clear the return short name. */ + short_name[0] = FX_NULL; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_ENABLE_EXFAT + /* Check if media format is exFAT. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Return the not implemented error. */ + return(FX_NOT_IMPLEMENTED); + } +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_UNICODE_DIRECTORY_CREATE, media_ptr, source_unicode_name, source_unicode_length, short_name, FX_TRACE_DIRECTORY_EVENTS, 0, 0) + + /* Protect media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Setup temporary length. */ + temp_length = source_unicode_length; + + /* Determine if the destination directory is already present. */ + status = _fx_unicode_directory_search(media_ptr, &dir_entry, destination_shortname, sizeof(destination_shortname), source_unicode_name, &temp_length, 0); + + /* Determine if the search was successful. */ + if (status == FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(FX_ALREADY_CREATED); + } + + /* Okay, at this point we need to create a new long directory name that has enough space for the + eventual unicode directory name. */ + + /* Copy the characters from the unicode directory name and make sure they are + within the ASCII range. */ + _fx_unicode_temp_long_file_name[0] = 'z'; + for (i = 1; i < source_unicode_length; i++) + { + + /* Build temporary long file name. */ + _fx_unicode_temp_long_file_name[i] = (UCHAR)((INT)'0' + (i % 9)); + } + _fx_unicode_temp_long_file_name[i] = FX_NULL; + + /* Loop to try different temp long file names... if necessary. */ + do + { + + /* Create a new directory with the temp long file name. */ + status = _fx_directory_create(media_ptr, (CHAR *)_fx_unicode_temp_long_file_name); + + /* Determine if there was an error. */ + if (status == FX_ALREADY_CREATED) + { + + /* Adjust the name slightly and try again! */ + _fx_unicode_temp_long_file_name[0]--; + + /* Determine if it is outside the lower case boundary. */ + if (_fx_unicode_temp_long_file_name[0] < 0x61) + { + break; + } + } + } while (status == FX_ALREADY_CREATED); + + /* Determine if there was an error. */ + if (status) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error. */ + return(status); + } + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, (CHAR *)_fx_unicode_temp_long_file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* We can now change the temporary long file name with the destination unicode name. */ + status = _fx_unicode_directory_entry_change(media_ptr, &dir_entry, source_unicode_name, source_unicode_length); + + /* Was this successful? */ + if (status == FX_SUCCESS) + { + + /* Yes, copy the short file name to the destination. */ + /* The new short name only have 8 characters, since we didn't include a dot in temp_long_file_name. */ + for (i = 0; i < FX_DIR_NAME_SIZE; i++) + { + + /* Copy a character. */ + short_name[i] = dir_entry.fx_dir_entry_short_name[i]; + + /* Are we done? */ + if (short_name[i] == FX_NULL) + { + break; + } + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release the protection. */ + FX_UNPROTECT + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c new file mode 100644 index 00000000..925791e4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_entry_change.c @@ -0,0 +1,390 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_directory_entry_change PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function changes the unicode name of a directory entry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* entry_ptr Directory entry */ +/* unicode_name Destination unicode name */ +/* unicode_name_length Unicode name size */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_logical_sector_read Read a logical sector */ +/* _fx_utility_logical_sector_write Write a logical sector */ +/* _fx_fault_tolerant_add_dir_log Add directory redo log */ +/* */ +/* CALLED BY */ +/* */ +/* Unicode Utilities */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_directory_entry_change(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr, UCHAR *unicode_name, ULONG unicode_name_length) +{ + +UCHAR *work_ptr, *sector_base_ptr; +UINT status; +UINT i, j, k, u, card, lfn_entries; +UCHAR eof_marker; +ULONG logical_sector, relative_sector; +ULONG byte_offset; +ULONG cluster, next_cluster; + +#ifdef FX_ENABLE_FAULT_TOLERANT +UCHAR *changed_ptr; +UINT changed_size; +ULONG changed_offset; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of directory entry write requests. */ + media_ptr -> fx_media_directory_entry_writes++; +#endif + + /* Pickup the byte offset of the entry. */ + byte_offset = entry_ptr -> fx_dir_entry_byte_offset; + + /* Pickup the logical sector of the entry. */ + logical_sector = (ULONG)entry_ptr -> fx_dir_entry_log_sector; + + /* Figure out where what cluster we are in. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_data_sector_start)) + { + + /* Calculate the cluster that this logical sector is in. */ + cluster = (logical_sector - media_ptr -> fx_media_data_sector_start) / (media_ptr -> fx_media_sectors_per_cluster) + FX_FAT_ENTRY_START; + + /* Calculate the relative cluster. */ + relative_sector = logical_sector - (((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster))); + } + else + { + + /* Clear the cluster and the relative sector. */ + cluster = 0; + relative_sector = 0; + } + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) entry_ptr -> fx_dir_entry_log_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Setup a pointer into the buffer. */ + sector_base_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer; + work_ptr = sector_base_ptr + (UINT)entry_ptr -> fx_dir_entry_byte_offset; + + /* Initialize the unicode index. */ + u = 0; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize data for fault tolerant. */ + changed_ptr = work_ptr; + changed_size = 0; + changed_offset = entry_ptr -> fx_dir_entry_byte_offset; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for a valid long name. */ + if ((0x40 & (*work_ptr))) + { + + /* Get the lower 5 bit containing the cardinality. */ + card = (*work_ptr & (UCHAR)0x1f); + lfn_entries = card; + + /* Loop through the file name. */ + for (j = 0; j < lfn_entries; j++) + { + + /* Clear the eof marker. */ + eof_marker = 0; + + /* Loop through file name fields. */ + for (i = 1, k = (26 * (card - 1)) & 0xFFFFFFFF; i < FX_DIR_ENTRY_SIZE; i += 2) + { + + /* Process relative to specific fields. */ + if ((i == 11) || (i == 26)) + { + continue; + } + + if (i == 13) + { + i = 12; + continue; + } + + /* Determine if the EOF marker is present. */ + if (eof_marker) + { + + work_ptr[i] = eof_marker; + work_ptr[i + 1] = eof_marker; + } + else if (k < (unicode_name_length * 2)) + { + + work_ptr[i] = unicode_name[k]; + work_ptr[i + 1] = unicode_name[k + 1]; + u = u + 2; + } + else if (k == (unicode_name_length * 2)) + { + + work_ptr[i] = 0; + work_ptr[i + 1] = 0; + + /* end of name, pad with 0xff. */ + eof_marker = (UCHAR)0xff; + } + + k = k + 2; + } + + /* Decrement the card. */ + card--; + + /* Setup pointers for the name write. */ + work_ptr += FX_DIR_ENTRY_SIZE; + byte_offset += FX_DIR_ENTRY_SIZE; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Update changed_size. */ + changed_size += FX_DIR_ENTRY_SIZE; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if the write is within the current sector. */ + if (byte_offset >= media_ptr -> fx_media_bytes_per_sector) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_dir_log(media_ptr, (ULONG64) logical_sector, changed_offset, changed_ptr, changed_size); + } + else + { + + /* Write the current sector out. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); + } + + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } +#else /* FX_ENABLE_FAULT_TOLERANT */ + + /* Write the current sector out. */ + /* Note: Since the sector is in the cache after a sector read, therefore _fx_utility_logical_sector_write + always returns success when FX_ENABLE_FAULT_TOLERANT is not defined. In other words, the checking + on the return value is needed only when FX_ENABLE_FAULT_TOLERANT is defined. */ + _fx_utility_logical_sector_write(media_ptr, (ULONG64) logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Determine if we are in the root directory. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_data_sector_start)) + { + + /* Determine the next sector of the directory entry. */ + if (relative_sector < (media_ptr -> fx_media_sectors_per_cluster - 1)) + { + + /* More sectors in this cluster. */ + + /* Simply increment the logical sector. */ + logical_sector++; + + /* Increment the relative sector. */ + relative_sector++; + } + else + { + + /* We need to move to the next cluster. */ + + /* Pickup the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Copy next cluster to the current cluster. */ + cluster = next_cluster; + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster > media_ptr -> fx_media_fat_reserved)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Setup the relative sector (this is zero for subsequent cluster. */ + relative_sector = 0; + + /* Calculate the next logical sector. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + } + } + else + { + + /* Increment the logical sector. */ + logical_sector++; + + /* Determine if the logical sector is valid. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_data_sector_start)) + { + + /* We have exceeded the root directory. */ + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + } + + /* Read the next logical sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Move to the next sector buffer. */ + sector_base_ptr = media_ptr -> fx_media_memory_buffer; + + /* Setup new buffer pointers. */ + byte_offset = 0; + work_ptr = sector_base_ptr; + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Initialize data for fault tolerant. */ + changed_ptr = work_ptr; + changed_size = 0; + changed_offset = 0; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + } + } + + /* Check for an error! */ + if (u != (unicode_name_length * 2)) + { + + /* Return an error! */ + return(FX_FILE_CORRUPT); + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_add_dir_log(media_ptr, (ULONG64) logical_sector, changed_offset, changed_ptr, changed_size); + } + else + { +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Write the directory sector to the media. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) logical_sector, + sector_base_ptr, ((ULONG) 1), FX_DIRECTORY_SECTOR); +#ifdef FX_ENABLE_FAULT_TOLERANT + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c new file mode 100644 index 00000000..7f476b43 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_entry_read.c @@ -0,0 +1,748 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_directory_entry_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads a unicode directory entry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_dir Pointer to source directory */ +/* entry_ptr Entry index in the directory */ +/* destination_ptr Destination directory */ +/* unicode_name Destination unicode name */ +/* unicode_size Destination unicode name size */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* _fx_utility_logical_sector_read Read a logical sector */ +/* _fx_utility_16_unsigned_read Read a 2-byte value */ +/* _fx_utility_32_unsigned_read Read a 4-byte value */ +/* */ +/* CALLED BY */ +/* */ +/* Unicode Utilities */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_directory_entry_read(FX_MEDIA *media_ptr, FX_DIR_ENTRY *source_dir, + ULONG *entry_ptr, FX_DIR_ENTRY *destination_ptr, + UCHAR *unicode_name, ULONG *unicode_size) +{ + +UINT i, j, k, card, dotflag, get_short_name; +UINT number_of_lfns; +UINT status; +ULONG cluster, next_cluster = 0; +UINT relative_cluster; +UINT relative_sector; +ULONG logical_sector; +ULONG byte_offset; +ULONG bytes_per_cluster; +UCHAR *read_ptr; +CHAR *short_name_ptr; +ULONG entry = *entry_ptr; +UINT u; + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of directory entry read requests. */ + media_ptr -> fx_media_directory_entry_reads++; +#endif + + /* Calculate the byte offset of this directory entry. */ + byte_offset = entry * FX_DIR_ENTRY_SIZE; + + /* Determine if a sub-directory or FAT32 root directory is specified. */ + if ((source_dir) || (media_ptr -> fx_media_32_bit_FAT)) + { + + /* Yes, a sub-directory is present. */ + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check for invalid value. */ + if (bytes_per_cluster == 0) + { + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Now determine the relative cluster in the sub-directory file. */ + relative_cluster = (UINT)(byte_offset / bytes_per_cluster); + + /* Calculate the byte offset within the cluster. */ + byte_offset = byte_offset % bytes_per_cluster; + + /* Now figure out the relative sector within the cluster. */ + relative_sector = (UINT)(byte_offset / ((ULONG)media_ptr -> fx_media_bytes_per_sector)); + + /* Read the directory sector into the internal memory buffer. */ + + /* Determine if there is a sub-directory. */ + if (source_dir) + { + + /* Determine if this source directory has valid information from the previous call. */ + if ((source_dir -> fx_dir_entry_last_search_cluster) && + (source_dir -> fx_dir_entry_last_search_relative_cluster <= relative_cluster) && + (source_dir -> fx_dir_entry_last_search_log_sector == source_dir -> fx_dir_entry_log_sector) && + (source_dir -> fx_dir_entry_last_search_byte_offset == source_dir -> fx_dir_entry_byte_offset)) + { + + /* Use the previous information to start the search. */ + cluster = source_dir -> fx_dir_entry_last_search_cluster; + + /* Setup the relative cluster index to the saved relative cluster. */ + i = source_dir -> fx_dir_entry_last_search_relative_cluster; + + /* Clear the search cluster. It will be updated prior to successful return. */ + source_dir -> fx_dir_entry_last_search_cluster = 0; + } + else + { + + /* Nothing from the previous directory read, just setup the starting cluster to the + beginning of the sub-directory. */ + cluster = source_dir -> fx_dir_entry_cluster; + + /* Setup the relative cluster index to zero. */ + i = 0; + } + } + else + { + + /* No, setup the starting cluster to the FAT32 root cluster. */ + cluster = media_ptr -> fx_media_root_cluster_32; + + /* Setup the relative cluster index to zero. */ + i = 0; + } + + /* Loop to position to the appropriate cluster. */ + while (i < relative_cluster) + { + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster > media_ptr -> fx_media_fat_reserved)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Read the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* There is a potential for loop, but hardly anything can be done */ + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Setup the actual cluster. */ + cluster = next_cluster; + + /* Increment the relative cluster number. */ + i++; + } + + /* At this point, the directory data sector needs to be read. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)) + + relative_sector; + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Calculate the byte offset within this sector. */ + byte_offset = byte_offset % media_ptr -> fx_media_bytes_per_sector; + } + else + { + + /* Read the entry from the root directory. */ + + /* Determine which sector the requested root directory entry is in. */ + logical_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_root_sector_start; + + /* Read the logical directory sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Set the cluster and relative variables (not used in this case) to avoid any compiler + warnings. */ + relative_cluster = relative_sector = cluster = 0; + + /* Now calculate the byte offset into this sector. */ + byte_offset = byte_offset - + ((logical_sector - (ULONG)media_ptr -> fx_media_root_sector_start) * + media_ptr -> fx_media_bytes_per_sector); + } + + /* Setup a pointer into the buffer. */ + read_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Save the logical sector and byte offset in the returned directory entry. */ + destination_ptr -> fx_dir_entry_log_sector = logical_sector; + destination_ptr -> fx_dir_entry_byte_offset = byte_offset; + + /* Clear the short file name information. */ + destination_ptr -> fx_dir_entry_long_name_shorted = 0; + destination_ptr -> fx_dir_entry_short_name[0] = 0; + + /* Setup short name pointer. */ + short_name_ptr = destination_ptr -> fx_dir_entry_name; + + /* Initialize the unicode index. */ + u = 0; + + /* Check if long file name exists. */ + get_short_name = 0; + if ((*(read_ptr + 11) == (UCHAR)FX_LONG_NAME) && (*read_ptr != (UCHAR)FX_DIR_ENTRY_FREE)) + { + + /* Collate the long name. */ + + + /* Save the number of LFN entries. */ + number_of_lfns = (UINT)(*read_ptr & (UCHAR)0x1f); + + if(number_of_lfns == 0) + { + /* Number of LFN cannot is 1-based. Therefore it cannot be zero. */ + return(FX_FILE_CORRUPT); + } + else + { + /* Pickup the file name length. */ + i = (number_of_lfns - 1) * FX_LONG_NAME_ENTRY_LEN; + } + + /* Check the file name size. */ + if (i >= (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Name is too big, shorten it. */ + get_short_name = 1; + destination_ptr -> fx_dir_entry_long_name_shorted = (UINT)(*read_ptr & (UCHAR)0x1f); + } + else + { + + /* Size of name is fine, save pointer to short file name. */ + short_name_ptr = destination_ptr -> fx_dir_entry_short_name; + + /* Loop to make sure the long file name is NULL terminated. */ + j = i + FX_LONG_NAME_ENTRY_LEN + 1; + do + { + /* Place a NULL in the long name. */ + destination_ptr -> fx_dir_entry_name[i] = 0; + + /* Position to the next entry. */ + i++; + } while ((i < j) && (i < FX_MAX_LONG_NAME_LEN)); + } + + /* Loop to pickup the rest of the name. */ + do + { + + /* Get the lower 5 bit containing the cardinality. */ + card = (*read_ptr) & 0x1f; + + if(card == 0) + { + + /* Number of LFN starts from one. Therefore it cannot be zero. */ + return(FX_FILE_CORRUPT); + } + else + { + card = card - 1; + } + /* For simplicity no checksum or cardinality checking is done */ + if ((get_short_name == 0) || (u)) + { + + /* Loop to pickup name. */ + for (i = 1, j = 0, k = 0; i < FX_DIR_ENTRY_SIZE; i += 2) + { + + if ((i == 11) || (i == 26)) + { + continue; + } + + /* i = 12, 27 is not generated due to +=2 */ + if (i == 13) + { + i = 12; + continue; /* this time next unicode is byte offset 14*/ + } + + /* Determine if there is an actual unicode character present. */ + if (read_ptr[i + 1]) + { + + /* Extended byte is non-zero, make sure both bytes of the unicode entry are not + all ones, since this is a normal case. */ + if ((read_ptr[i + 1] != (UCHAR)0xFF) || (read_ptr[i] != (UCHAR)0xFF)) + { + + /* Name is an actual unicode name, shorten it. */ + get_short_name = 1; + + /* Save the number of directory entries the LFN has. This will be + used later when updating the 8.3 portion of the LFN. */ + destination_ptr -> fx_dir_entry_long_name_shorted = number_of_lfns; + + /* Setup short name pointer. */ + short_name_ptr = destination_ptr -> fx_dir_entry_name; + } + } + + /* Determine if the character is NULL. */ + if (((read_ptr[i] == FX_NULL) && (read_ptr[i + 1] == FX_NULL)) || + ((read_ptr[i] == (UCHAR)0xFF) && (read_ptr[i + 1] == (UCHAR)0xFF))) + { + continue; + } + + /* Determine if the name is too big. */ + if ((card * 13 + j) >= (FX_MAX_LONG_NAME_LEN - 1)) + { + + /* Name is actually too big, shorten it. */ + get_short_name = 1; + + /* Save the number of directory entries the LFN has. This will be + used later when updating the 8.3 portion of the LFN. */ + destination_ptr -> fx_dir_entry_long_name_shorted = number_of_lfns; + + /* Also reposition the short name pointer. */ + short_name_ptr = destination_ptr -> fx_dir_entry_name; + + break; + } + + /* Each entry contains 13 unicode and first byte ASCII, second byte is extended. */ + if (get_short_name == 0) + { + destination_ptr -> fx_dir_entry_name[13 * card + j] = (CHAR)read_ptr[i]; + } + + /* Save the potential unicode characters. */ + unicode_name[k + 26 * card + j] = read_ptr[i]; + unicode_name[k + 26 * card + j + 1] = read_ptr[i + 1]; + k++; + u++; + + j++; + } + } + + /* Determine if a new sector needs to be read. */ + if (byte_offset + FX_DIR_ENTRY_SIZE >= media_ptr -> fx_media_bytes_per_sector) + { + + /* Determine if a sub-directory or FAT32 root directory is specified. */ + if ((source_dir) || (media_ptr -> fx_media_32_bit_FAT)) + { + + /* Determine the next sector of the directory entry. */ + if (relative_sector < (media_ptr -> fx_media_sectors_per_cluster - 1)) + { + + /* More sectors in this cluster. */ + + /* Simply increment the logical sector. */ + logical_sector++; + + /* Increment the relative sector. */ + relative_sector++; + } + else + { + + /* We need to move to the next cluster. */ + + /* Pickup the next cluster. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check for I/O error. */ + if (status != FX_SUCCESS) + { + + /* Return error code. */ + return(status); + } + + /* Copy next cluster to the current cluster. */ + cluster = next_cluster; + + /* Check the value of the new cluster - it must be a valid cluster number + or something is really wrong! */ + if ((cluster < FX_FAT_ENTRY_START) || (cluster > media_ptr -> fx_media_fat_reserved)) + { + + /* Send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + + /* Now increment the relative cluster. */ + relative_cluster++; + + /* Setup the relative sector (this is zero for subsequent cluster. */ + relative_sector = 0; + + /* Calculate the next logical sector. */ + logical_sector = ((ULONG)media_ptr -> fx_media_data_sector_start) + + (((ULONG)cluster - FX_FAT_ENTRY_START) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster)); + } + } + else + { + + /* Non-FAT 32 root directory. */ + + /* Advance to the next sector. */ + logical_sector++; + + /* Determine if the logical sector is valid. */ + if (logical_sector >= (ULONG)(media_ptr -> fx_media_root_sector_start + media_ptr -> fx_media_root_sectors)) + { + + /* Trying to read past root directory - send error message back to caller. */ + return(FX_FILE_CORRUPT); + } + } + + /* Read the new sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) logical_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_DIRECTORY_SECTOR); + + /* Check I/O status. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Set the byte offset to 0 for new sector. */ + byte_offset = 0; + } + else + { + + /* Calculate the new byte offset. */ + byte_offset += FX_DIR_ENTRY_SIZE; + } + + /* Calculate the next read pointer. */ + read_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Move to the next entry. */ + entry++; + } while (card > 0); + + /* Set flag indicating long file name is present. */ + destination_ptr -> fx_dir_entry_long_name_present = 1; + } + else + { + /* No long file name is present. */ + get_short_name = 1; + } + + /* Determine if we need to clear the long name flag. */ + if (get_short_name == 1) + { + + /* Clear the long name flag. */ + destination_ptr -> fx_dir_entry_long_name_present = 0; + } + + /* Store the unicode name size. */ + *unicode_size = u; + + /* Pickup the short file name. */ + short_name_ptr[0] = 0; + dotflag = 0; + for (i = 0, j = 0; i < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); i++) + { + + /* Check for a NULL. */ + if ((CHAR)read_ptr[i] == 0) + { + break; + } + + /* Check for a dot. This happens for the first two directory entries, no + extra dot is needed. */ + if ((CHAR)read_ptr[i] == '.') + { + dotflag = 2; + } + + /* Check for a space. */ + if ((CHAR)read_ptr[i] == ' ') + { + /* Put a dot if a character comes after space. */ + if (dotflag == 0) + { + dotflag = 1; + } + continue; + } + + /* Check for the main short file name size. */ + if (i == FX_DIR_NAME_SIZE) + { + /* Check to see if we need to insert a dot. */ + if (dotflag == 0) + { + dotflag = 1; + } + } + + /* Check to see if we need to add a dot. */ + if (dotflag == 1) + { + /* Add dot to short file name. */ + short_name_ptr[j++] = '.'; + dotflag = 2; /* no more dot for spaces */ + } + + /* Copy a character. */ + short_name_ptr[j] = (CHAR)read_ptr[i]; + + /* Increment size. */ + j++; + } + + /* Determine if a long file name is present and its associated short file + name is actually free. */ + if ((destination_ptr -> fx_dir_entry_long_name_present) && (((UCHAR)short_name_ptr[0]) == (UCHAR)FX_DIR_ENTRY_FREE)) + { + + /* Yes, the short file name is really free even though long file name entries directly precede it. + In this case, simply place the free directory marker at the front of the long file name. */ + destination_ptr -> fx_dir_entry_name[0] = (CHAR)FX_DIR_ENTRY_FREE; + short_name_ptr[0] = (CHAR)0; + } + + /* Determine if the short name pointer is NULL while the read pointer is + non-NULL. */ + if ((short_name_ptr[0] == 0) && (read_ptr[0] == ' ')) + { + + /* This condition can occur with an all blank volume name. Simply + copy the volume name to the short name in this case. */ + for (j = 0; j < (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); j++) + { + + /* Copy a byte of the volume name. */ + short_name_ptr[j] = (CHAR)read_ptr[j]; + } + } + + /* Set end of string to null. */ + short_name_ptr[j] = 0; + + /* Load up the destination directory entry. */ + read_ptr += (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE); + + /* Copy the attribute into the destination. */ + destination_ptr -> fx_dir_entry_attributes = *read_ptr++; + + /* Pickup the reserved byte. */ + destination_ptr -> fx_dir_entry_reserved = *read_ptr++; + + /* Check for an undocumented NT file name feature for optimizing the storage + of all lower case file names that otherwise are valid 8.3 file names. The + following reserved bit definitions are present: + + BIT3 - set if 8.3 is all in lower case and no extended filename. + BIT4 - set for file, clear for directory entry if no extended filename. + + This is true for all NT systems. Prior to NT follows MSDOS FAT documentation and + is set to 0x00, all bits cleared. Therefore if BIT3 is set force lowercase. */ + if ((get_short_name) && (destination_ptr -> fx_dir_entry_reserved & 0x08)) + { + + /* Microsoft undocumented NT file name feature... convert short name to lower + case. */ + for (j = 0; j <= (FX_DIR_NAME_SIZE + FX_DIR_EXT_SIZE) && (short_name_ptr[j] != 0x00); j++) + { + + /* Determine if an upper case character is present. */ + if ((short_name_ptr[j] >= 'A') && (short_name_ptr[j] <= 'Z')) + { + + /* Yes, an upper case character is present. Force it to lower case. */ + short_name_ptr[j] = (CHAR)((INT)short_name_ptr[j] + 32); + } + } + } + + /* Pickup the created time in milliseconds. */ + destination_ptr -> fx_dir_entry_created_time_ms = *read_ptr++; + + /* Pickup the created time. */ + destination_ptr -> fx_dir_entry_created_time = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Pickup the created date. */ + destination_ptr -> fx_dir_entry_created_date = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Pickup the last accessed date. */ + destination_ptr -> fx_dir_entry_last_accessed_date = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* read the upper 2 bytes of starting cluster - required only for 32 bit FAT */ + if (media_ptr -> fx_media_32_bit_FAT) + { + + /* FAT32 only. */ + destination_ptr -> fx_dir_entry_cluster = _fx_utility_16_unsigned_read(read_ptr); + destination_ptr -> fx_dir_entry_cluster <<= 16; + } + else + { + /* Not required for non FAT32. */ + destination_ptr -> fx_dir_entry_cluster = 0; + } + + /* Advance the read pointer. */ + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Copy the time into the destination. */ + destination_ptr -> fx_dir_entry_time = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Copy the date into the destination. */ + destination_ptr -> fx_dir_entry_date = _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Copy the starting cluster into the destination. */ + destination_ptr -> fx_dir_entry_cluster += _fx_utility_16_unsigned_read(read_ptr); + read_ptr = read_ptr + 2; /* Always 2 bytes */ + + /* Copy the file size into the destination. */ + destination_ptr -> fx_dir_entry_file_size = _fx_utility_32_unsigned_read(read_ptr); + + /* Clear the destination search specific fields. */ + destination_ptr -> fx_dir_entry_last_search_cluster = 0; + destination_ptr -> fx_dir_entry_last_search_relative_cluster = 0; + destination_ptr -> fx_dir_entry_last_search_log_sector = 0; + destination_ptr -> fx_dir_entry_last_search_byte_offset = 0; + + /* Remember the entry number. */ + destination_ptr -> fx_dir_entry_number = entry; + + /* Return entry number. */ + *entry_ptr = entry; + + /* Determine if we should remember the last cluster and relative cluster. */ + if (source_dir) + { + + /* Yes, remember the last cluster and relative cluster for a subsequent call + to read a directory entry. */ + source_dir -> fx_dir_entry_last_search_cluster = cluster; + source_dir -> fx_dir_entry_last_search_relative_cluster = relative_cluster; + + /* Also remember several other items that are unique to the directory... just to verify that the + search information can be used. */ + source_dir -> fx_dir_entry_last_search_log_sector = source_dir -> fx_dir_entry_log_sector; + source_dir -> fx_dir_entry_last_search_byte_offset = source_dir -> fx_dir_entry_byte_offset; + } + + /* Return success to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c new file mode 100644 index 00000000..81159381 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_rename.c @@ -0,0 +1,353 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_directory_rename PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates the specified unicode directory. */ +/* This function first attempts to find the specified directory. */ +/* If found, the unicode rename request is valid and the directory */ +/* will be changed to the new unicode name. Otherwise, if the directory*/ +/* is not found, the appropriate error code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* old_unicode_name Pointer to old unicode name */ +/* old_unicode_length Old unicode name length */ +/* new_unicode_name Pointer to new unicode name */ +/* new_unicode_length Old unicode name length */ +/* new_short_name Pointer to new short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_short_name_get Get the directory short name */ +/* _fx_unicode_directory_search Search for unicode name */ +/* _fx_unicode_directory_entry_change Change unicode file name */ +/* _fx_directory_rename Rename the directory */ +/* _fx_directory_search Search directory */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_directory_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name) +{ + +FX_DIR_ENTRY dir_entry; +UINT i, status; +ULONG temp_length; +CHAR old_dir_short_name[13]; +CHAR new_dir_short_name[13]; +UCHAR alpha, beta; + + + /* Clear the return short name. */ + new_short_name[0] = FX_NULL; + + /* Set shortname to null. */ + old_dir_short_name[0] = FX_NULL; + new_dir_short_name[0] = FX_NULL; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_ENABLE_EXFAT + /* Check if media format is exFAT. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Return the not implemented error. */ + return(FX_NOT_IMPLEMENTED); + } +#endif + + /* Get the old short name. */ + status = _fx_unicode_short_name_get(media_ptr, old_unicode_name, old_unicode_length, &old_dir_short_name[0]); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Return the error code. */ + return(status); + } + + /* Protect media. */ + FX_PROTECT + + /* Setup temporary length. */ + temp_length = new_unicode_length; + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = FX_NULL; + + /* Determine if the new directory name is already present. */ + status = _fx_unicode_directory_search(media_ptr, &dir_entry, (UCHAR *)new_dir_short_name, sizeof(new_dir_short_name), new_unicode_name, &temp_length, 0); + + /* Determine if the search was successful. */ + if (status == FX_SUCCESS) + { + + /* Determine if the name length are equal. */ + if (old_unicode_length == new_unicode_length) + { + + /* Determine if the new name simply has a UNICODE case change. If so, simply let the processing + continue. */ + i = 0; + do + { + + /* Pickup an old name and new name character and convert to upper case if necessary. */ + alpha = old_unicode_name[i * 2]; + if ((alpha >= 'a') && (alpha <= 'z') && (old_unicode_name[i * 2 + 1] == 0)) + { + + /* Lower case, convert to upper case! */ + alpha = (UCHAR)((INT)alpha - 0x20); + } + beta = new_unicode_name[i * 2]; + if ((beta >= 'a') && (beta <= 'z') && (new_unicode_name[i * 2 + 1] == 0)) + { + + /* Lower case, convert to upper case! */ + beta = (UCHAR)((INT)beta - 0x20); + } + + /* Now compare the characters. */ + if (alpha != beta) + { + + /* Get out of this loop! */ + break; + } + + /* Pickup the high bytes. */ + alpha = old_unicode_name[i * 2 + 1]; + beta = new_unicode_name[i * 2 + 1]; + + /* Now compare the byte. */ + if ((alpha != beta)) + { + + /* Get out of this loop! */ + break; + } + + /* Move to next character. */ + i++; + } while (i < old_unicode_length); + } + else + { + alpha = 0; + beta = 1; + } + + /* Now determine if the names match. */ + if (alpha != beta) + { + + /* Yes, the directory name already exists in the target location. */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(FX_ALREADY_CREATED); + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Okay, at this point we need to create a new long directory name that has enough space for the + eventual unicode directory name. */ + + /* Copy the characters from the unicode directory name and make sure they are + within the ASCII range. */ + _fx_unicode_temp_long_file_name[0] = 'z'; + for (i = 1; i < new_unicode_length; i++) + { + + /* Build temporary long file name. */ + _fx_unicode_temp_long_file_name[i] = (UCHAR)((UINT)'0' + (i % 9)); + } + _fx_unicode_temp_long_file_name[i] = FX_NULL; + + /* Loop to try different temp long file names... if necessary. */ + do + { + + /* Rename the directory name. */ + status = _fx_directory_rename(media_ptr, old_dir_short_name, (CHAR *)_fx_unicode_temp_long_file_name); + + /* Determine if there was an error. */ + if (status == FX_ALREADY_CREATED) + { + + /* Adjust the name slightly and try again! */ + _fx_unicode_temp_long_file_name[0]--; + + /* Determine if it is outside the lower case boundary. */ + if (_fx_unicode_temp_long_file_name[0] < 0x61) + { + break; + } + } + } while (status == FX_ALREADY_CREATED); + + /* Determine if there was an error. */ + if (status) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error. */ + return(status); + } + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = FX_NULL; + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, (CHAR *)_fx_unicode_temp_long_file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* We can now change the temporary long file name with the destination unicode name. */ + status = _fx_unicode_directory_entry_change(media_ptr, &dir_entry, new_unicode_name, new_unicode_length); + + /* Determine if the rename was successful. */ + if (status == FX_SUCCESS) + { + + /* Yes, copy the short file name to the destination. */ + /* The new short name only have 8 characters, since we didn't include a dot in temp_long_file_name. */ + for (i = 0; i < FX_DIR_NAME_SIZE; i++) + { + + /* Copy a character. */ + new_short_name[i] = dir_entry.fx_dir_entry_short_name[i]; + + /* Are we done? */ + if (new_short_name[i] == FX_NULL) + { + break; + } + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release the protection. */ + FX_UNPROTECT + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_directory_search.c b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_search.c new file mode 100644 index 00000000..6063e511 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_directory_search.c @@ -0,0 +1,501 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" +#include "fx_utility.h" + +#ifndef FX_NO_LOCAL_PATH +FX_LOCAL_PATH_SETUP +#endif + + +/* Define several Unicode working arrays... This keeps the data structures + off the local stack. */ + +UCHAR _fx_unicode_temp_long_file_name[FX_MAX_LONG_NAME_LEN]; +UCHAR _fx_unicode_search_name[FX_MAX_LONG_NAME_LEN * 2]; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_directory_search PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function searches for the specified unicode or short name. */ +/* */ +/* Note: The buffer of short_name and unicode_name must be valid to */ +/* fill search result. When short_name is a zero length string, search */ +/* is based on unicode string (terminated with NULL). If it's found */ +/* the short name is written back to buffer of short_name. In this case*/ +/* unicode_name_buffer_length is ignored and short_name_buffer_length */ +/* must not be zero to specify the buffer length. If buffer is too */ +/* smallfor the result, overflow characters and NULL-terminator are cut*/ +/* off. When short_name is a valid string, search is based on */ +/* short_name (terminated with NULL). If it's found the unicode name is*/ +/* written back to buffer of unicode_name. In this case */ +/* short_name_buffer_length is ignored and unicode_name_buffer_length */ +/* must not be zero to specify the unicode buffer length. If buffer is */ +/* too small for the result, overflow characters are cut off but */ +/* NULL-terminator is kept. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* short_name Pointer to short name */ +/* short_name_buffer_length Buffer length for short name */ +/* unicode_name Pointer to Unicode name */ +/* unicode_name_length Unicode name length */ +/* unicode_name_buffer_length Buffer length for Unicode name*/ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_directory_entry_read Read a full unicode directory */ +/* entry */ +/* _fx_utility_FAT_entry_read Read a FAT entry */ +/* */ +/* CALLED BY */ +/* */ +/* Unicode Utilities */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_directory_search(FX_MEDIA *media_ptr, FX_DIR_ENTRY *entry_ptr, + UCHAR *short_name, ULONG short_name_buffer_length, + UCHAR *unicode_name, ULONG *unicode_name_length, ULONG unicode_name_buffer_length) +{ + +ULONG i, j; +UINT status, found; +ULONG cluster, next_cluster = 0; +ULONG directory_size; +FX_DIR_ENTRY search_dir; +FX_DIR_ENTRY *search_dir_ptr; +ULONG unicode_search_length; +ULONG local_unicode_name_length; +CHAR unicode_to_short_name[13]; +CHAR *short_name_ptr; + + + /* Setup temp unicode name length. */ + local_unicode_name_length = *unicode_name_length; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of directory search requests. */ + media_ptr -> fx_media_directory_searches++; +#endif + + /* Set the initial search directory to the current working + directory - if there is one. */ + + /* First check for a local path pointer stored in the thread control block. This + is only available in ThreadX Version 4 and above. */ +#ifndef FX_NO_LOCAL_PATH + if (_tx_thread_current_ptr -> tx_thread_filex_ptr) + { + + /* Determine if the local directory is not the root directory. */ + if (((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_directory.fx_dir_entry_name[0]) + { + + /* Start at the current working directory of the media. */ + search_dir = ((FX_PATH *)_tx_thread_current_ptr -> tx_thread_filex_ptr) -> fx_path_directory; + + /* Set the internal pointer to the search directory as well. */ + search_dir_ptr = &search_dir; + } + else + { + + /* We are searching in the root directory. */ + search_dir_ptr = FX_NULL; + } + } + else +#endif + if (media_ptr -> fx_media_default_path.fx_path_directory.fx_dir_entry_name[0]) + { + + /* Start at the current working directory of the media. */ + search_dir = media_ptr -> fx_media_default_path.fx_path_directory; + + /* Set the internal pointer to the search directory as well. */ + search_dir_ptr = &search_dir; + } + else + { + + /* The current default directory is the root so just set the + search directory pointer to NULL. */ + search_dir_ptr = FX_NULL; + } + + /* Calculate the directory size. */ + if (search_dir_ptr) + { + + /* Ensure that the search directory's last search cluster is cleared. */ + search_dir_ptr -> fx_dir_entry_last_search_cluster = 0; + + /* Calculate the directory size by counting the allocated + clusters for it. */ + i = 0; + cluster = search_dir_ptr -> fx_dir_entry_cluster; + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < media_ptr -> fx_media_fat_reserved)) + { + + /* Increment the cluster count. */ + i++; + + /* Read the next FAT entry. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &next_cluster); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + + /* Check for error situation. */ + if ((cluster == next_cluster) || (i > media_ptr -> fx_media_total_clusters)) + { + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + cluster = next_cluster; + } + + /* Now we can calculate the directory size. */ + directory_size = (((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster) * i) / + (ULONG)FX_DIR_ENTRY_SIZE; + + /* Also save this in the directory entry so we don't have to + calculate it later. */ + search_dir_ptr -> fx_dir_entry_file_size = directory_size; + } + else + { + + /* Directory size is the number of entries in the root directory. */ + directory_size = (ULONG)media_ptr -> fx_media_root_directory_entries; + } + + /* Determine if we are searching for a short file name or a unicode file name. */ + if (short_name[0] == 0) + { + + /* If the unicode name fit into short name length, covert the Unicode to ASCII if possible. */ + if (local_unicode_name_length <= 13) + { + for (j = 0; j < local_unicode_name_length; j++) + { + if ((unicode_name[j * 2] <= 0x7F) && (unicode_name[j * 2 + 1] == 0)) + { + + unicode_to_short_name[j] = (CHAR)unicode_name[j * 2]; + if ((unicode_to_short_name[j] >= 'a') && (unicode_to_short_name[j] <= 'z')) + { + + /* Lower case, convert to upper case! */ + unicode_to_short_name[j] = (CHAR)((INT)unicode_to_short_name[j] - 0x20); + } + } + else + { + unicode_to_short_name[0] = 0; + break; + } + } + } + else + { + unicode_to_short_name[0] = 0; + } + } + else + { + unicode_to_short_name[0] = 0; + } + + /* Loop through entries in the directory. Yes, this is a + linear search! */ + i = 0; + do + { + + /* Read an entry from the directory. */ + status = _fx_unicode_directory_entry_read(media_ptr, search_dir_ptr, &i, entry_ptr, &_fx_unicode_search_name[0], &unicode_search_length); + i++; + + /* Check for error status. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Determine if this is an empty entry. */ + if (((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_FREE) && (entry_ptr -> fx_dir_entry_short_name[0] == 0)) + { + continue; + } + + /* Determine if this is the last directory entry. */ + if ((UCHAR)entry_ptr -> fx_dir_entry_name[0] == (UCHAR)FX_DIR_ENTRY_DONE) + { + break; + } + + /* Determine if there is a short name to match. */ + if (unicode_to_short_name[0]) + { + + /* Get the short name pointer. */ + if (entry_ptr -> fx_dir_entry_short_name[0]) + { + short_name_ptr = entry_ptr -> fx_dir_entry_short_name; + } + else + { + short_name_ptr = entry_ptr -> fx_dir_entry_name; + } + + for (j = 0; j < local_unicode_name_length; j++) + { + + /* Compare characters. */ + if (short_name_ptr[j] != unicode_to_short_name[j]) + { + break; + } + } + if (j == local_unicode_name_length) + { + + /* Only the 1st 13 bytes or the buffer length is copied, whichever is smaller. */ + if (short_name_buffer_length > 13) + { + short_name_buffer_length = 13; + } + + /* The names match, copy the short name into the destination. */ + for (j = 0; j < short_name_buffer_length; j++) + { + short_name[j] = (UCHAR)short_name_ptr[j]; + } + + /* Return success to caller. */ + return(FX_SUCCESS); + } + } + + /* Determine if this is not a unicode name. */ + if (unicode_search_length == 0) + { + continue; + } + + /* Determine if we are searching for a short file name or a unicode file name. */ + if (short_name[0]) + { + + /* We have a short name and need a unicode name. Compare the short name against the short name in + the directory entry for a match. */ + found = FX_TRUE; + for (j = 0; j < 12; j++) + { + + /* Compare characters... */ + if (entry_ptr -> fx_dir_entry_short_name[0]) + { + + /* Yes, the return name is in the short name field... compare against it! */ + if (short_name[j] != (UCHAR)entry_ptr -> fx_dir_entry_short_name[j]) + { + + found = FX_FALSE; + break; + } + } + else + { + + /* No, the return name is in the name field... compare against it! */ + if (short_name[j] != (UCHAR)entry_ptr -> fx_dir_entry_name[j]) + { + + found = FX_FALSE; + break; + } + } + + /* Are we done? */ + if (short_name[j] == (UCHAR)FX_NULL) + { + break; + } + } + + /* One final compare to see if we have a match. */ + if ((found == FX_FALSE) || ((j == 12) && (short_name[12] != 0))) + { + continue; + } + + /* A match was found so copy the unicode name and length and return. */ + /* Copy the length. */ + *unicode_name_length = unicode_search_length; + + /* Check if the name fit in the buffer. */ + if (unicode_name_buffer_length < (unicode_search_length + 1) * 2) + { + unicode_search_length = (unicode_name_buffer_length - 2) / 2; + } + + /* Copy the unicode name. */ + for (j = 0; j < unicode_search_length * 2; j++) + { + + /* Copy one unicode character to the destination... */ + unicode_name[j] = _fx_unicode_search_name[j]; + } + + /* Make sure there is a NULL in the destination. */ + unicode_name[j] = (UCHAR)0; + unicode_name[j + 1] = (UCHAR)0; + + + + /* Return successful completion. */ + return(FX_SUCCESS); + } + else + { + + /* Determine if this is the correct unicode name. */ + if (unicode_search_length != local_unicode_name_length) + { + continue; + } + + /* Compare the unicode search name with the requested unicode name. */ + for (j = 0; j < (local_unicode_name_length * 2); j = j + 2) + { + + /* Compare bytes of each unicode name. */ + if (unicode_name[j] != _fx_unicode_search_name[j]) + { + + /* Not match, Check if the character is in ASCII range. */ + if ((_fx_unicode_search_name[j + 1] == 0) && (unicode_name[j + 1] == 0)) + { + + /* Check if it is case mismatch. */ + if ((unicode_name[j]) >= 'a' && (unicode_name[j] <= 'z')) + { + if ((unicode_name[j] - 0x20) == _fx_unicode_search_name[j]) + { + continue; + } + } + if ((_fx_unicode_search_name[j]) >= 'a' && (_fx_unicode_search_name[j] <= 'z')) + { + if ((_fx_unicode_search_name[j] - 0x20) == unicode_name[j]) + { + continue; + } + } + } + + break; + } + + /* Compare the next byte. */ + if (unicode_name[j + 1] != _fx_unicode_search_name[j + 1]) + { + break; + } + } + + /* Determine if the names do not match. */ + if (j != (local_unicode_name_length * 2)) + { + continue; + } + + /* Otherwise, the names match, copy the short name into the destination. */ + /* Only the 1st 13 bytes or the buffer length is copied, whichever is smaller. */ + if (short_name_buffer_length > 13) + { + short_name_buffer_length = 13; + } + for (j = 0; j < short_name_buffer_length; j++) + { + + /* Copy a character. */ + if (entry_ptr -> fx_dir_entry_short_name[0]) + { + short_name[j] = (UCHAR)entry_ptr -> fx_dir_entry_short_name[j]; + } + else + { + short_name[j] = (UCHAR)entry_ptr -> fx_dir_entry_name[j]; + } + } + + /* Return success to caller. */ + return(FX_SUCCESS); + } + } while (i < directory_size); + + /* Return not found. */ + return(FX_NOT_FOUND); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_file_create.c b/src/Middlewares/ST/filex/common/src/fx_unicode_file_create.c new file mode 100644 index 00000000..4c3bc864 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_file_create.c @@ -0,0 +1,292 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_file_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates the specified unicode name. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_unicode_name Pointer to source unicode name*/ +/* source_unicode_length Unicode name length */ +/* short_name Designated short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_search Search directory */ +/* _fx_unicode_directory_entry_change Change unicode file name */ +/* _fx_unicode_directory_search Search for unicode name */ +/* _fx_file_create Create a file */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* _fx_fault_tolerant_recover Recover FAT chain */ +/* _fx_fault_tolerant_reset_log_file Reset the log file */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_file_create(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, CHAR *short_name) +{ + +FX_DIR_ENTRY dir_entry; +UINT i, status; +ULONG temp_length; +UCHAR destination_shortname[13]; + + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = FX_NULL; + + /* Set destination shortname to null. */ + destination_shortname[0] = FX_NULL; + + /* Clear the return short name. */ + short_name[0] = FX_NULL; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_ENABLE_EXFAT + /* Check if media format is exFAT. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Return the not implemented error. */ + return(FX_NOT_IMPLEMENTED); + } +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_UNICODE_FILE_CREATE, media_ptr, source_unicode_name, source_unicode_length, short_name, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect media. */ + FX_PROTECT + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return write protect error. */ + return(FX_WRITE_PROTECT); + } + + /* Setup temporary length. */ + temp_length = source_unicode_length; + + /* Determine if the destination file is already present. */ + status = _fx_unicode_directory_search(media_ptr, &dir_entry, destination_shortname, sizeof(destination_shortname), source_unicode_name, &temp_length, 0); + + /* Determine if the search was successful. */ + if (status == FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(FX_ALREADY_CREATED); + } + + /* Okay, at this point we need to create a new long file name that has enough space for the + eventual unicode file name. */ + + /* Copy the characters from the unicode file name and make sure they are + within the ASCII range. */ + _fx_unicode_temp_long_file_name[0] = 'z'; + for (i = 1; i < source_unicode_length; i++) + { + + /* Build temporary long file name. */ + _fx_unicode_temp_long_file_name[i] = (UCHAR)((UINT)'0' + (i % 9)); + } + _fx_unicode_temp_long_file_name[i] = FX_NULL; + + /* Loop to try different temp long file names... if necessary. */ + do + { + + /* Create a new file with the temp long file name. */ + status = _fx_file_create(media_ptr, (CHAR *)_fx_unicode_temp_long_file_name); + + /* Determine if there was an error. */ + if (status == FX_ALREADY_CREATED) + { + + /* Adjust the name slightly and try again! */ + _fx_unicode_temp_long_file_name[0]--; + + /* Determine if it is outside the lower case boundary. */ + if (_fx_unicode_temp_long_file_name[0] < 0x61) + { + break; + } + } + } while (status == FX_ALREADY_CREATED); + + /* Determine if there was an error. */ + if (status) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error. */ + return(status); + } + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, (CHAR *)_fx_unicode_temp_long_file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* We can now change the temporary long file name with the destination unicode name. */ + status = _fx_unicode_directory_entry_change(media_ptr, &dir_entry, source_unicode_name, source_unicode_length); + + /* Was this successful? */ + if (status == FX_SUCCESS) + { + + /* Yes, copy the short file name to the destination. */ + /* The new short name only have 8 characters, since we didn't include a dot in temp_long_file_name. */ + for (i = 0; i < FX_DIR_NAME_SIZE; i++) + { + + /* Copy a character. */ + short_name[i] = dir_entry.fx_dir_entry_short_name[i]; + + /* Are we done? */ + if (short_name[i] == FX_NULL) + { + break; + } + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release the protection. */ + FX_UNPROTECT + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_file_rename.c b/src/Middlewares/ST/filex/common/src/fx_unicode_file_rename.c new file mode 100644 index 00000000..995015e4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_file_rename.c @@ -0,0 +1,353 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" +#include "fx_directory.h" +#include "fx_file.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_file_rename PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function first attempts to find the specified file. If found, */ +/* the rename request is valid and the directory entry will be changed */ +/* to the new file name. Otherwise, if the file is not found, the */ +/* appropriate error code is returned to the caller. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* old_unicode_name Pointer to old unicode name */ +/* old_unicode_length Old unicode name length */ +/* new_unicode_name Pointer to new unicode name */ +/* new_unicode_length New unicode name length */ +/* new_short_name Designated new short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_short_name_get Get short name of unicode name*/ +/* _fx_directory_search Search directory */ +/* _fx_unicode_directory_entry_change Change unicode file name */ +/* _fx_unicode_directory_search Search for unicode name */ +/* _fx_file_rename Rename for ASCII file name */ +/* _fx_fault_tolerant_transaction_start Start fault tolerant */ +/* transaction */ +/* _fx_fault_tolerant_transaction_end End fault tolerant transaction*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_file_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name) +{ +ULONG i; +UINT status; +CHAR alpha, beta; +CHAR old_shortname[13]; +CHAR new_shortname[13]; +FX_DIR_ENTRY dir_entry; + + + /* Clear the return short name. */ + new_short_name[0] = FX_NULL; + + /* Set shortname to null. */ + old_shortname[0] = FX_NULL; + new_shortname[0] = FX_NULL; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_ENABLE_EXFAT + /* Check if media format is exFAT. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Return the not implemented error. */ + return(FX_NOT_IMPLEMENTED); + } +#endif + + /* Get shortname of old unicode name. */ + status = _fx_unicode_short_name_get(media_ptr, old_unicode_name, old_unicode_length, old_shortname); + + /* Determine if the result was successful. */ + if (status != FX_SUCCESS) + { + + /* Return the error code. */ + return(status); + } + + /* Protect media. */ + FX_PROTECT + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = FX_NULL; + + /* Search the target directory for the same file name. */ + status = _fx_unicode_directory_search(media_ptr, &dir_entry, (UCHAR *)new_shortname, sizeof(new_shortname), + new_unicode_name, &new_unicode_length, 0); + + /* Determine if the name already exists. */ + if (status == FX_SUCCESS) + { + + if (old_unicode_length == new_unicode_length) + { + + /* Determine if the new name simply has an ASCII case change. If so, simply let the processing + continue. */ + i = 0; + do + { + + /* Pickup an old name and new name character and convert to upper case if necessary. */ + alpha = (CHAR)old_unicode_name[i << 1]; + if ((alpha >= 'a') && (alpha <= 'z') && (old_unicode_name[(i << 1) + 1] == 0)) + { + + /* Lower case, convert to upper case! */ + alpha = (CHAR)((INT)alpha - 0x20); + } + beta = (CHAR)new_unicode_name[i << 1]; + if ((beta >= 'a') && (beta <= 'z') && (new_unicode_name[(i << 1) + 1] == 0)) + { + + /* Lower case, convert to upper case! */ + beta = (CHAR)((INT)beta - 0x20); + } + + /* Now compare the characters. */ + if ((alpha != beta)) + { + + /* Get out of this loop! */ + break; + } + + /* Pickup the high bytes. */ + alpha = (CHAR)old_unicode_name[(i << 1) + 1]; + beta = (CHAR)new_unicode_name[(i << 1) + 1]; + + /* Now compare the byte. */ + if ((alpha != beta)) + { + + /* Get out of this loop! */ + break; + } + + /* Move to next character. */ + i++; + } while (i < old_unicode_length); + } + else + { + + /* Names not match. */ + alpha = 0; + beta = 1; + } + + /* Now determine if the names match. */ + if (alpha != beta) + { + + /* No, the names do not match so simply return an error + to the caller. */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the not a file error code. */ + return(FX_ALREADY_CREATED); + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Start transaction. */ + _fx_fault_tolerant_transaction_start(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Okay, at this point we need to rename to a new long file name that has enough space for the + eventual unicode file name. */ + + /* Copy the characters from the unicode file name and make sure they are + within the ASCII range. */ + _fx_unicode_temp_long_file_name[0] = 'z'; + for (i = 1; i < new_unicode_length; i++) + { + + /* Build temporary long file name. */ + _fx_unicode_temp_long_file_name[i] = (UCHAR)((UINT)'0' + (i % 9)); + } + _fx_unicode_temp_long_file_name[i] = FX_NULL; + + /* Loop to try different temp long file names... if necessary. */ + do + { + + /* Create a new file with the temp long file name. */ + status = _fx_file_rename(media_ptr, old_shortname, (CHAR *)_fx_unicode_temp_long_file_name); + + /* Determine if there was an error. */ + if (status == FX_ALREADY_CREATED) + { + + /* Adjust the name slightly and try again! */ + _fx_unicode_temp_long_file_name[0]--; + + /* Determine if it is outside the lower case boundary. */ + if (_fx_unicode_temp_long_file_name[0] < 0x61) + { + break; + } + } + } while (status == FX_ALREADY_CREATED); + + /* Determine if there was an error. */ + if (status) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return error. */ + return(status); + } + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Search the system for the supplied file name. */ + status = _fx_directory_search(media_ptr, (CHAR *)_fx_unicode_temp_long_file_name, &dir_entry, FX_NULL, FX_NULL); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { +#ifdef FX_ENABLE_FAULT_TOLERANT + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error status. */ + return(status); + } + + /* We can now change the temporary long file name with the destination unicode name. */ + status = _fx_unicode_directory_entry_change(media_ptr, &dir_entry, new_unicode_name, new_unicode_length); + + /* Was this successful? */ + if (status == FX_SUCCESS) + { + + /* Yes, copy the short file name to the destination. */ + /* The new short name only have 8 characters, since we didn't include a dot in temp_long_file_name. */ + for (i = 0; i < FX_DIR_NAME_SIZE; i++) + { + + /* Copy a character. */ + new_short_name[i] = dir_entry.fx_dir_entry_short_name[i]; + + /* Are we done? */ + if (new_short_name[i] == FX_NULL) + { + break; + } + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + /* Check for a bad status. */ + if (status != FX_SUCCESS) + { + + FX_FAULT_TOLERANT_TRANSACTION_FAIL(media_ptr); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the bad status. */ + return(status); + } + + /* End transaction. */ + status = _fx_fault_tolerant_transaction_end(media_ptr); +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Release the protection. */ + FX_UNPROTECT + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_length_get.c b/src/Middlewares/ST/filex/common/src/fx_unicode_length_get.c new file mode 100644 index 00000000..0ac52bca --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_length_get.c @@ -0,0 +1,81 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_length_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the length of the supplied unicode name. */ +/* */ +/* Note, this API is deprecated as _fx_unicode_length_get_extended */ +/* should be used. The maximum buffer size of unicode_name is 256. */ +/* */ +/* INPUT */ +/* */ +/* unicode_name Pointer to unicode name */ +/* */ +/* OUTPUT */ +/* */ +/* length */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_length_get_extended Actual unicode length get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _fx_unicode_length_get(UCHAR *unicode_name) +{ + + /* Call the extended version with 256 bytes maximum buffer length. */ + return(_fx_unicode_length_get_extended(unicode_name, 256)); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c b/src/Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c new file mode 100644 index 00000000..c667c9fd --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_length_get_extended.c @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_length_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the length of the supplied unicode name. */ +/* */ +/* INPUT */ +/* */ +/* unicode_name Pointer to unicode name */ +/* buffer_length Buffer length for unicode name*/ +/* */ +/* OUTPUT */ +/* */ +/* length */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _fx_unicode_length_get_extended(UCHAR *unicode_name, UINT buffer_length) +{ + +ULONG i; +ULONG length; + + + i = 0; + length = 0; + while (i < buffer_length) + { + + /* See if we are at the end of the unicode string... This assumes that there is a NULL at the end of the string. */ + if ((unicode_name[i] == 0) && (unicode_name[i + 1] == 0)) + { + break; + } + + /* Increment index. */ + i = i + 2; + + /* Increment the length. */ + length++; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_UNICODE_LENGTH_GET, unicode_name, length, 0, 0, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Return length. */ + return(length); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_name_get.c b/src/Middlewares/ST/filex/common/src/fx_unicode_name_get.c new file mode 100644 index 00000000..79af309c --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_name_get.c @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_name_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function finds the unicode name associated with the supplied */ +/* short 8.3 name. */ +/* */ +/* Note, this API is deprecated as fx_unicode_name_get_extended should */ +/* be used. The maximum written size to destination_unicode_name could */ +/* be FX_MAX_LONG_NAME_LEN * 2. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_short_name Pointer to short file name */ +/* destination_unicode_name Pointer to destination name */ +/* destination_unicode_length Destination for name length */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_name_get_extended Actual unicode name get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_name_get(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length) +{ + + /* Call the extended version with 13 bytes short name length. */ + return(_fx_unicode_name_get_extended(media_ptr, source_short_name, destination_unicode_name, destination_unicode_length, FX_MAX_LONG_NAME_LEN * 2)); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c b/src/Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c new file mode 100644 index 00000000..d53a6f73 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_name_get_extended.c @@ -0,0 +1,145 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_name_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function finds the unicode name associated with the supplied */ +/* short 8.3 name. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_short_name Pointer to short file name */ +/* destination_unicode_name Pointer to destination name */ +/* destination_unicode_length Destination for name length */ +/* unicode_name_buffer_length Buffer length of unicode name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_directory_search Search for unicode name */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_name_get_extended(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length, ULONG unicode_name_buffer_length) +{ + +UINT status; +FX_DIR_ENTRY dir_entry; + +#ifdef TX_ENABLE_EVENT_TRACE +TX_TRACE_BUFFER_ENTRY *trace_event; +ULONG trace_timestamp; +#endif + + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_ENABLE_EXFAT + /* Check if media format is exFAT. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Return the not implemented error. */ + return(FX_NOT_IMPLEMENTED); + } +#endif + + /* Set the destination unicode length to zero to indicate there is nothing in terms of a match. */ + *destination_unicode_length = 0; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_UNICODE_NAME_GET, media_ptr, source_short_name, destination_unicode_name, 0, FX_TRACE_FILE_EVENTS, &trace_event, &trace_timestamp) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied short file name and return the unicode name if there is a match. */ + status = _fx_unicode_directory_search(media_ptr, &dir_entry, (UCHAR *)source_short_name, 0, destination_unicode_name, destination_unicode_length, unicode_name_buffer_length); + + /* Determine if the search was successful. */ + if (status != FX_SUCCESS) + { + + /* Release media protection. */ + FX_UNPROTECT + + /* Return the error code. */ + return(status); + } + + /* Release media protection. */ + FX_UNPROTECT + + /* Update the trace event with the unicode length. */ + FX_TRACE_EVENT_UPDATE(trace_event, trace_timestamp, FX_TRACE_UNICODE_NAME_GET, 0, 0, 0, *destination_unicode_length) + + /* Return successful completion status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c b/src/Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c new file mode 100644 index 00000000..8d4d0915 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_short_name_get.c @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_short_name_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function finds the short name associated with the supplied */ +/* unicode name. */ +/* */ +/* Note, this API is deprecated as fx_unicode_short_name_get_extended */ +/* should be used. The maximum written size to destination_short_name */ +/* could be 13. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_unicode_name Pointer to unicode name */ +/* source_unicode_length Length of unicode name */ +/* destination_short_name Pointer to destination name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_short_name_get_extended Actual unicode short name get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_short_name_get(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name) +{ + + /* Call the extended version with 13 bytes short name length. */ + return(_fx_unicode_short_name_get_extended(media_ptr, source_unicode_name, source_unicode_length, destination_short_name, 13)); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c b/src/Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c new file mode 100644 index 00000000..bf8fb4bd --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_unicode_short_name_get_extended.c @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_unicode_short_name_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function finds the short name associated with the supplied */ +/* unicode name. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_unicode_name Pointer to unicode name */ +/* source_unicode_length Length of unicode name */ +/* destination_short_name Pointer to destination name */ +/* short_name_buffer_length Buffer length of short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_directory_search Search for unicode name */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_unicode_short_name_get_extended(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name, ULONG short_name_buffer_length) +{ + +UINT status; +ULONG temp_unicode_length; +FX_DIR_ENTRY dir_entry; + + + /* Setup pointer to media name buffer. */ + dir_entry.fx_dir_entry_name = media_ptr -> fx_media_name_buffer + FX_MAX_LONG_NAME_LEN; + + /* Clear the short name string. */ + dir_entry.fx_dir_entry_short_name[0] = 0; + + /* Check the media to make sure it is open. */ + if (media_ptr -> fx_media_id != FX_MEDIA_ID) + { + + /* Return the media not opened error. */ + return(FX_MEDIA_NOT_OPEN); + } + +#ifdef FX_ENABLE_EXFAT + /* Check if media format is exFAT. */ + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Return the not implemented error. */ + return(FX_NOT_IMPLEMENTED); + } +#endif + + /* Null terminate the short return name. */ + destination_short_name[0] = (UCHAR)0; + + /* Setup temporary unicode name length for search call. */ + temp_unicode_length = source_unicode_length; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_UNICODE_SHORT_NAME_GET, media_ptr, source_unicode_name, source_unicode_length, destination_short_name, FX_TRACE_FILE_EVENTS, 0, 0) + + /* Protect against other threads accessing the media. */ + FX_PROTECT + + /* Search the system for the supplied short name and return the unicode name if there is a match. */ + status = _fx_unicode_directory_search(media_ptr, &dir_entry, (UCHAR *)destination_short_name, short_name_buffer_length, source_unicode_name, &temp_unicode_length, 0); + + /* Release media protection. */ + FX_UNPROTECT + + /* Return successful completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c b/src/Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c new file mode 100644 index 00000000..addb4993 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_16_unsigned_read.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_16_unsigned_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads (with endian awareness) 16-bit unsigned data */ +/* from the specified source and returns the value to the caller. */ +/* */ +/* INPUT */ +/* */ +/* source_ptr Source memory pointer */ +/* */ +/* OUTPUT */ +/* */ +/* UINT value */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_16_unsigned_read(UCHAR *source_ptr) +{ + +UINT value; + + /* Pickup the UINT from the destination with endian-awareness. */ + value = ((((UINT)*(source_ptr + 1)) & 0xFF) << 8) | + ((UINT)*(source_ptr) & 0xFF); + + /* Return value to caller. */ + return(value); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c b/src/Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c new file mode 100644 index 00000000..f0dd68f9 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_16_unsigned_write.c @@ -0,0 +1,81 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_16_unsigned_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes (with endian awareness) 16-bit unsigned data */ +/* to the specified destination. */ +/* */ +/* INPUT */ +/* */ +/* dest_ptr Destination memory pointer */ +/* value Value to write to memory */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _fx_utility_16_unsigned_write(UCHAR *dest_ptr, UINT value) +{ + + /* Store the UINT into the destination with endian-awareness. */ + *(dest_ptr) = (UCHAR)(value & 0xFF); + *(dest_ptr + 1) = (UCHAR)((value >> 8) & 0xFF); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c b/src/Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c new file mode 100644 index 00000000..f9f5e52e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_32_unsigned_read.c @@ -0,0 +1,87 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_32_unsigned_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads (with endian awareness) a 32-bit unsigned data */ +/* from the specified source and returns the value to the caller. */ +/* */ +/* INPUT */ +/* */ +/* source_ptr Source memory pointer */ +/* */ +/* OUTPUT */ +/* */ +/* ULONG value */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _fx_utility_32_unsigned_read(UCHAR *source_ptr) +{ + +ULONG value; + + /* Pickup the UINT from the destination with endian-awareness. */ + value = ((((ULONG) *(source_ptr+3)) & 0xFF) << 24) | + ((((ULONG) *(source_ptr+2)) & 0xFF) << 16) | + ((((ULONG) *(source_ptr+1)) & 0xFF) << 8) | + (((ULONG) *(source_ptr)) & 0xFF); + + /* Return value to caller. */ + return(value); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c b/src/Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c new file mode 100644 index 00000000..3edf5dc9 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_32_unsigned_write.c @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_32_unsigned_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes (with endian awareness) a 32-bit unsigned data */ +/* type to the specified destination. */ +/* */ +/* INPUT */ +/* */ +/* dest_ptr Destination memory pointer */ +/* value Value to write to memory */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _fx_utility_32_unsigned_write(UCHAR *dest_ptr, ULONG value) +{ + + /* Store the UINT into the destination with endian-awareness. */ + *(dest_ptr) = (UCHAR)(value & 0xFF); + *(dest_ptr + 1) = (UCHAR)((value >> 8) & 0xFF); + *(dest_ptr + 2) = (UCHAR)((value >> 16) & 0xFF); + *(dest_ptr + 3) = (UCHAR)((value >> 24) & 0xFF); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c b/src/Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c new file mode 100644 index 00000000..baa3772b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_64_unsigned_read.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_64_unsigned_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads (with endian awareness) a 64-bit unsigned data */ +/* from the specified source and returns the value to the caller. */ +/* */ +/* INPUT */ +/* */ +/* source_ptr Source memory pointer */ +/* */ +/* OUTPUT */ +/* */ +/* ULONG64 value */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG64 _fx_utility_64_unsigned_read(UCHAR *source_ptr) +{ + +ULONG64 value; +ULONG upper_portion; +ULONG lower_portion; + + + lower_portion = _fx_utility_32_unsigned_read(source_ptr); + upper_portion = _fx_utility_32_unsigned_read(source_ptr + sizeof(ULONG)); + + value = ((ULONG64)upper_portion) << 32; + value |= (ULONG64)lower_portion; + + /* Return 64-bit value to caller. */ + return(value); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c b/src/Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c new file mode 100644 index 00000000..6de3d91a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_64_unsigned_write.c @@ -0,0 +1,81 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_64_unsigned_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes (with endian awareness) a 64-bit unsigned data */ +/* type to the specified destination. */ +/* */ +/* INPUT */ +/* */ +/* dest_ptr Destination memory pointer */ +/* value Value to write to memory */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _fx_utility_64_unsigned_write(UCHAR *dest_ptr, ULONG64 value) +{ + + /* Store the ULONG64 into the destination with endian-awareness. */ + _fx_utility_32_unsigned_write(dest_ptr, (ULONG)value); + _fx_utility_32_unsigned_write(dest_ptr + sizeof(ULONG), (ULONG)(value >> 32)); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c new file mode 100644 index 00000000..fd5a0beb --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_entry_read.c @@ -0,0 +1,445 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_FAT_entry_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the supplied FAT entry from the first FAT of */ +/* the media. 12-bit, 16-bit, and 32-bit FAT reading is supported. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster entry number */ +/* entry_ptr Pointer to destination for */ +/* the FAT entry */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_read Read a UINT from FAT buffer */ +/* _fx_utility_32_unsigned_read Read a ULONG form FAT buffer */ +/* _fx_utility_FAT_flush Flush FAT entry cache */ +/* _fx_utility_logical_sector_read Read FAT sector into memory */ +/* _fx_fault_tolerant_read_FAT Read FAT entry from log file */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable fat entry refresh, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_FAT_entry_read(FX_MEDIA *media_ptr, ULONG cluster, ULONG *entry_ptr) +{ + +ULONG FAT_sector; +ULONG byte_offset, entry32; +UCHAR *FAT_ptr; +UINT entry, index; +UINT status; +FX_FAT_CACHE_ENTRY *cache_entry_ptr; +FX_FAT_CACHE_ENTRY temp_cache_entry; + + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED)) + { + + /* Redirect this request to log file. */ + status = _fx_fault_tolerant_read_FAT(media_ptr, cluster, entry_ptr, FX_FAULT_TOLERANT_FAT_LOG_TYPE); + + /* Return on success. */ + if (status != FX_READ_CONTINUE) + { + return(status); + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Increment the number of FAT entry reads and cache hits. */ + media_ptr -> fx_media_fat_entry_reads++; + media_ptr -> fx_media_fat_entry_cache_read_hits++; +#endif + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_UTILITY_FAT_ENTRY_READ_EXTENSION + + /* Calculate the area of the cache for this FAT entry. */ + index = (cluster & FX_FAT_CACHE_HASH_MASK) * FX_FAT_CACHE_DEPTH; + + /* Build a pointer to the cache entry. */ + cache_entry_ptr = &media_ptr -> fx_media_fat_cache[index]; + +#ifndef FX_DISABLE_FAT_ENTRY_REFRESH + /* Determine if the FAT entry is in the cache - assuming the depth of the FAT cache is + 4 entries. */ + if ((cache_entry_ptr -> fx_fat_cache_entry_cluster) == cluster) + { + + /* Yes, return the cached value. */ + *entry_ptr = cache_entry_ptr -> fx_fat_cache_entry_value; + + /* Don't move anything since we found the entry. */ + + /* Return a successful status. */ + return(FX_SUCCESS); + } + else if (((cache_entry_ptr + 1) -> fx_fat_cache_entry_cluster) == cluster) + { + + /* Yes, return the cached value. */ + *entry_ptr = (cache_entry_ptr + 1) -> fx_fat_cache_entry_value; + + /* Just swap the first and second entry. */ + temp_cache_entry = *(cache_entry_ptr); + *(cache_entry_ptr) = *(cache_entry_ptr + 1); + *(cache_entry_ptr + 1) = temp_cache_entry; + + /* Return a successful status. */ + return(FX_SUCCESS); + } + else if (((cache_entry_ptr + 2) -> fx_fat_cache_entry_cluster) == cluster) + { + + /* Yes, return the cached value. */ + *entry_ptr = (cache_entry_ptr + 2) -> fx_fat_cache_entry_value; + + /* Move the third entry to the top and the first two entries down. */ + temp_cache_entry = *(cache_entry_ptr); + *(cache_entry_ptr) = *(cache_entry_ptr + 2); + *(cache_entry_ptr + 2) = *(cache_entry_ptr + 1); + *(cache_entry_ptr + 1) = temp_cache_entry; + + /* Return a successful status. */ + return(FX_SUCCESS); + } + else if (((cache_entry_ptr + 3) -> fx_fat_cache_entry_cluster) == cluster) + { + + /* Yes, return the cached value. */ + *entry_ptr = (cache_entry_ptr + 3) -> fx_fat_cache_entry_value; + + /* Move the last entry to the top and the first three entries down. */ + temp_cache_entry = *(cache_entry_ptr); + *(cache_entry_ptr) = *(cache_entry_ptr + 3); + *(cache_entry_ptr + 3) = *(cache_entry_ptr + 2); + *(cache_entry_ptr + 2) = *(cache_entry_ptr + 1); + *(cache_entry_ptr + 1) = temp_cache_entry; + + /* Return a successful status. */ + return(FX_SUCCESS); + } +#else + for (UINT i = 0; i < 4; i++) + { + if (((cache_entry_ptr + i) -> fx_fat_cache_entry_cluster) == cluster) + { + *entry_ptr = (cache_entry_ptr + i) -> fx_fat_cache_entry_value; + + /* Return a successful status. */ + return(FX_SUCCESS); + } + } +#endif /* FX_DISABLE_FAT_ENTRY_REFRESH */ + + /* Determine if the oldest entry was modified, i.e. whether or not it is + dirty. */ + if (media_ptr -> fx_media_fat_cache[index + 3].fx_fat_cache_entry_dirty) + { + + /* Yes, the entry is dirty and needs to be flushed out. */ + status = _fx_utility_FAT_flush(media_ptr); + + /* Check for completion status. */ + if (status != FX_SUCCESS) + { + + /* Return error status. */ + return(status); + } + } + + /* If we get here, the entry was not found in the FAT entry cache. We need to + actually read the FAT entry. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Decrement the number of cache hits. */ + media_ptr -> fx_media_fat_entry_cache_read_hits--; + + /* Increment the number of cache misses. */ + media_ptr -> fx_media_fat_entry_cache_read_misses++; +#endif + + /* Determine which type of FAT is present. */ + if (media_ptr -> fx_media_12_bit_FAT) + { + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster << 1) + cluster) >> 1; + + /* Calculate the FAT sector the requested FAT entry resides in. */ + FAT_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Read the sector in. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + /* Return the error status. */ + return(status); + } + + /* Now calculate the byte offset into this FAT sector. */ + byte_offset = byte_offset - + ((FAT_sector - (ULONG)media_ptr -> fx_media_reserved_sectors) * + media_ptr -> fx_media_bytes_per_sector); + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Determine if the cluster entry is odd or even. */ + if (cluster & 1) + { + + /* Odd cluster number. */ + + /* Pickup the lower nibble of the FAT entry. */ + entry = (((UINT)*FAT_ptr) & 0xF0) >> 4; + + /* Move to the next byte of the FAT entry. */ + FAT_ptr++; + + /* Determine if we are now past the end of the FAT buffer in memory. */ + if (byte_offset == (ULONG)(media_ptr -> fx_media_bytes_per_sector - 1)) + { + + /* Yes, we need to read the next sector. */ + FAT_sector++; + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer; + } + + /* Pickup the upper 8 bits of the FAT entry. */ + entry = entry | (((UINT)*FAT_ptr) << 4); + } + else + { + + /* Even cluster number. */ + + /* Pickup the lower byte of the FAT entry. */ + entry = (UINT)(((UINT)*FAT_ptr) & 0xFF); + + /* Move to the next nibble of the FAT entry. */ + FAT_ptr++; + + /* Determine if we are now past the end of the FAT buffer in memory. */ + if (byte_offset == (ULONG)(media_ptr -> fx_media_bytes_per_sector - 1)) + { + + /* Yes, we need to read the next sector. */ + FAT_sector++; + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer; + } + + /* Pickup the upper 4 bits of the FAT entry. */ + entry = entry | ((((UINT)*FAT_ptr) & 0x0F) << 8); + } + + /* Determine if we need to do sign extension on the 12-bit eof value. */ + if (entry >= FX_MAX_12BIT_CLUST) + { + + /* Yes, we need to sign extend. */ + entry = entry | FX_SIGN_EXTEND; + } + + *entry_ptr = entry; + } + + /* Check for a 16-bit FAT. */ +#ifdef FX_ENABLE_EXFAT + else if (FX_FAT16 == media_ptr -> fx_media_FAT_type) +#else + else if (!media_ptr -> fx_media_32_bit_FAT) +#endif /* FX_ENABLE_EXFAT */ + { + + /* 16-bit FAT is present. */ + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster) * 2); + + /* Calculate the FAT sector the requested FAT entry resides in. */ + FAT_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Read the FAT sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error code. */ + return(status); + } + + /* Now calculate the byte offset into this FAT sector. */ + byte_offset = byte_offset - + ((FAT_sector - (ULONG)media_ptr -> fx_media_reserved_sectors) * + media_ptr -> fx_media_bytes_per_sector); + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Pickup the FAT entry. */ + entry = _fx_utility_16_unsigned_read(FAT_ptr); + + *entry_ptr = entry; + } +#ifdef FX_ENABLE_EXFAT + else if ((media_ptr -> fx_media_FAT_type == FX_FAT32) || + (media_ptr -> fx_media_FAT_type == FX_exFAT)) +#else + else +#endif /* FX_ENABLE_EXFAT */ + { + + /* Otherwise, a 32 bit FAT present. */ + byte_offset = (((ULONG)cluster) * 4); + + /* Calculate the FAT sector the requested FAT entry resides in. */ + FAT_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Calculate the byte offset to the FAT entry. */ + byte_offset = (byte_offset % media_ptr -> fx_media_bytes_per_sector); + + /* Read the appropriate FAT sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error code. */ + return(status); + } + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (ULONG)byte_offset; + + /* Pickup the FAT entry. */ + entry32 = _fx_utility_32_unsigned_read(FAT_ptr); + +#ifdef FX_ENABLE_EXFAT + /* FAT32 uses 28 bit cluster addressing but exFAT uses 32 bit. */ + if (media_ptr -> fx_media_FAT_type == FX_FAT32) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Clear upper nibble. */ + entry32 = entry32 & 0x0FFFFFFF; +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + + *entry_ptr = entry32; + } + + /* Move all the cache entries down so the oldest is at the bottom. */ + *(cache_entry_ptr + 3) = *(cache_entry_ptr + 2); + *(cache_entry_ptr + 2) = *(cache_entry_ptr + 1); + *(cache_entry_ptr + 1) = *(cache_entry_ptr); + + /* Setup the new FAT entry in the cache. */ + cache_entry_ptr -> fx_fat_cache_entry_cluster = cluster; + cache_entry_ptr -> fx_fat_cache_entry_value = *entry_ptr; + + /* Return success to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c new file mode 100644 index 00000000..1d117109 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_entry_write.c @@ -0,0 +1,265 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_FAT_entry_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes to the supplied FAT entry to all FATs in */ +/* the media. 12-bit, 16-bit, and 32-bit FAT writing is supported. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster entry number */ +/* next_cluster Next cluster integer pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_FAT_flush FLUSH dirty entries in the */ +/* FAT cache */ +/* _fx_fault_tolerant_add_fat_log Add FAT redo log */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_FAT_entry_write(FX_MEDIA *media_ptr, ULONG cluster, ULONG next_cluster) +{ + +UINT status, index, i; +FX_FAT_CACHE_ENTRY *cache_entry_ptr; +#ifdef FX_ENABLE_FAULT_TOLERANT +ULONG FAT_sector; + + /* While fault_tolerant is enabled, only FAT entries in the same sector are allowed to be cached. */ + /* We must flush FAT sectors in the order of FAT chains. */ + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED)) + { + + if (!(media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN)) + { + + /* Redirect this request to log file. */ + return(_fx_fault_tolerant_add_FAT_log(media_ptr, cluster, next_cluster)); + } + + /* Get sector number of the incoming FAT entry. */ + FAT_sector = _fx_utility_FAT_sector_get(media_ptr, cluster); + + /* Is FAT sector changed? */ + if (FAT_sector != media_ptr -> fx_media_fault_tolerant_cached_FAT_sector) + { + + /* Are there any cached FAT entries? */ + if (media_ptr -> fx_media_fault_tolerant_cached_FAT_sector) + { + + /* Current FAT entry is located in different sector. Force flush. */ + /* Flush the cached individual FAT entries */ + _fx_utility_FAT_flush(media_ptr); + +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_exFAT) + { + + /* Flush exFAT bitmap. */ + _fx_utility_exFAT_bitmap_flush(media_ptr); + } +#endif /* FX_ENABLE_EXFAT */ + } + + /* Record sector number of current FAT entry. */ + media_ptr -> fx_media_fault_tolerant_cached_FAT_sector = FAT_sector; + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Increment the number of FAT entry writes and cache hits. */ + media_ptr -> fx_media_fat_entry_writes++; + media_ptr -> fx_media_fat_entry_cache_write_hits++; +#endif + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_UTILITY_FAT_ENTRY_WRITE_EXTENSION + + /* Calculate the area of the cache for this FAT entry. */ + index = (cluster & FX_FAT_CACHE_HASH_MASK) * FX_FAT_CACHE_DEPTH; + + /* Build a pointer to the cache entry. */ + cache_entry_ptr = &media_ptr -> fx_media_fat_cache[index]; + + /* First search for the entry in the FAT entry cache. */ + for (i = 0; i < FX_FAT_CACHE_DEPTH; i++) + { + + /* See if the entry matches the write request. */ + if (((cache_entry_ptr + i) -> fx_fat_cache_entry_cluster) == cluster) + { + + /* Yes, we have a matching entry. Save the new information in the FAT + cache and mark this entry as dirty. */ + (cache_entry_ptr + i) -> fx_fat_cache_entry_value = next_cluster; + (cache_entry_ptr + i) -> fx_fat_cache_entry_dirty = 1; + + /* Determine if the driver has requested notification when data sectors in the media + become free. This can be useful to FLASH manager software. */ + if ((media_ptr -> fx_media_driver_free_sector_update) && (next_cluster == FX_FREE_CLUSTER)) + { + + /* Yes, the driver does wish to know that these specific sector(s) are + not in use. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver release sectors requests. */ + media_ptr -> fx_media_driver_release_sectors_requests++; +#endif + + /* This cluster is being released so inform the driver that the + corresponding sectors are now available. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_RELEASE_SECTORS; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_logical_sector = (media_ptr -> fx_media_data_sector_start + + ((cluster - FX_FAT_ENTRY_START) * media_ptr -> fx_media_sectors_per_cluster)); + media_ptr -> fx_media_driver_sectors = media_ptr -> fx_media_sectors_per_cluster; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_RELEASE_SECTORS, media_ptr, media_ptr -> fx_media_driver_logical_sector, media_ptr -> fx_media_driver_sectors, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the driver. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + } + + /* Done, return successful status. */ + return(FX_SUCCESS); + } + } + + /* If we reach this point, we know that the FAT write request is not in + the cache. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Decrement the number of cache hits. */ + media_ptr -> fx_media_fat_entry_cache_write_hits--; + + /* Increment the number of cache misses. */ + media_ptr -> fx_media_fat_entry_cache_write_misses++; +#endif + + /* Determine if the oldest entry is dirty and needs to be flushed. */ + if (media_ptr -> fx_media_fat_cache[index + 3].fx_fat_cache_entry_dirty == 1) + { + + /* Flush the dirty entry so it can be used to hold the current + FAT entry write request. */ + status = _fx_utility_FAT_flush(media_ptr); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + + /* No, return error status to caller. */ + return(status); + } + + } + + /* Move all the cache entries down so the oldest is at the bottom. */ + *(cache_entry_ptr + 3) = *(cache_entry_ptr + 2); + *(cache_entry_ptr + 2) = *(cache_entry_ptr + 1); + *(cache_entry_ptr + 1) = *(cache_entry_ptr); + + /* Save the current FAT entry write request and mark as dirty. */ + cache_entry_ptr -> fx_fat_cache_entry_dirty = 1; + cache_entry_ptr -> fx_fat_cache_entry_cluster = cluster; + cache_entry_ptr -> fx_fat_cache_entry_value = next_cluster; + + /* Determine if the driver has requested notification when data sectors in the media + become free. This can be useful to FLASH manager software. */ + if ((media_ptr -> fx_media_driver_free_sector_update) && (next_cluster == FX_FREE_CLUSTER)) + { + + /* Yes, the driver does wish to know that these specific sector(s) are + not in use. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver release sectors requests. */ + media_ptr -> fx_media_driver_release_sectors_requests++; +#endif + + /* This cluster is being released so inform the driver that the + corresponding sectors are now available. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_RELEASE_SECTORS; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_logical_sector = (media_ptr -> fx_media_data_sector_start + + ((cluster - FX_FAT_ENTRY_START) * media_ptr -> fx_media_sectors_per_cluster)); + media_ptr -> fx_media_driver_sectors = media_ptr -> fx_media_sectors_per_cluster; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_RELEASE_SECTORS, media_ptr, media_ptr -> fx_media_driver_logical_sector, media_ptr -> fx_media_driver_sectors, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Call the driver. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + } + + /* Return success to caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c new file mode 100644 index 00000000..c771646f --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_flush.c @@ -0,0 +1,564 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_FAT_flush PORTABLE C */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function flushes the contents of the FAT cache to the media. */ +/* 12-bit, 16-bit and 32-bit FAT writing is supported. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_16_unsigned_write Write a UINT into buffer */ +/* _fx_utility_32_unsigned_read Read a ULONG from buffer */ +/* _fx_utility_32_unsigned_write Write a ULONG into buffer */ +/* _fx_utility_logical_sector_read Read FAT sector into memory */ +/* _fx_utility_logical_sector_write Write FAT sector back to disk */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 11-09-2020 William E. Lamie Modified comment(s), */ +/* updated logic for */ +/* FAT secondary update map, */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_FAT_flush(FX_MEDIA *media_ptr) +{ + +ULONG FAT_sector; +ULONG byte_offset; +UCHAR *FAT_ptr; +UINT temp, i; +UINT status, index, ind; +ULONG cluster, next_cluster; +UCHAR sectors_per_bit; +INT multi_sector_entry; +ULONG sector; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + /* Increment the number of cache flush requests. */ + media_ptr -> fx_media_fat_cache_flushes++; +#endif + + /* Loop through the media's FAT cache and flush out dirty entries. */ + for (index = 0; index < FX_MAX_FAT_CACHE; index++) + { + + /* Determine if the entry is dirty. */ + if ((media_ptr -> fx_media_fat_cache[index].fx_fat_cache_entry_dirty) == 0) + { + + /* No, just advance to the next entry. */ + continue; + } + + /* Otherwise, the entry is indeed dirty and must be flushed out. Process + relative to the type of FAT that is being used. */ + + /* Pickup the contents of the FAT cache entry. */ + cluster = media_ptr -> fx_media_fat_cache[index].fx_fat_cache_entry_cluster; + + /* Determine which type of FAT is present. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_FAT12) +#else + if (media_ptr -> fx_media_12_bit_FAT) +#endif /* FX_ENABLE_EXFAT */ + { + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster << 1) + cluster) >> 1; + + /* Calculate the FAT sector the requested FAT entry resides in. */ + FAT_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Initialize as not written. */ + multi_sector_entry = -1; + + for (;;) + { + + /* Pickup the FAT sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Determine if a mulit-sector FAT update is present. */ + if (multi_sector_entry != -1) + { + + /* Yes, store the remaining portion of the new FAT entry in the + next FAT sector. */ + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer; + + /* Pickup the cluster and next cluster. */ + cluster = (media_ptr -> fx_media_fat_cache[multi_sector_entry].fx_fat_cache_entry_cluster); + next_cluster = media_ptr -> fx_media_fat_cache[multi_sector_entry].fx_fat_cache_entry_value; + + /* Determine if the cluster entry is odd or even. */ + if (cluster & 1) + { + + /* Store the upper 8 bits of the FAT entry. */ + *FAT_ptr = (UCHAR)((next_cluster >> 4) & 0xFF); + } + else + { + + /* Store the upper 4 bits of the FAT entry. */ + temp = ((UINT)*FAT_ptr) & 0xF0; + *FAT_ptr = (UCHAR)(temp | ((next_cluster >> 8) & 0xF)); + } + + /* Clear the multi-sector flag. */ + multi_sector_entry = -1; + } + + /* Loop through the remainder of the cache to check for multiple entries + within the same FAT sector being written out. */ + for (i = index; i < FX_MAX_FAT_CACHE; i++) + { + + /* Is the cache entry dirty? */ + if ((media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_dirty) == 0) + { + + /* Not dirty, does not need to be flushed. */ + continue; + } + + /* Isolate the cluster. */ + cluster = (media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_cluster); + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster << 1) + cluster) >> 1; + + /* Pickup the sector. */ + sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Is it the current FAT sector? */ + if (sector != FAT_sector) + { + + /* Different FAT sector - not in this pass of the loop. */ + continue; + } + + /* Pickup new value for this FAT entry. */ + next_cluster = media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_value; + + /* Now calculate the byte offset into this FAT sector. */ + byte_offset = byte_offset - + ((FAT_sector - (ULONG)media_ptr -> fx_media_reserved_sectors) * + media_ptr -> fx_media_bytes_per_sector); + + /* Determine if we are now past the end of the FAT buffer in memory. */ + if (byte_offset == (ULONG)(media_ptr -> fx_media_bytes_per_sector - 1)) + { + + /* Yes, we need to read the next sector */ + multi_sector_entry = (INT)i; + } + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Clear the dirty flag. */ + media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_dirty = 0; + + /* Determine if the cluster entry is odd or even. */ + if (cluster & 1) + { + + /* Odd cluster number. */ + + /* Pickup the upper nibble of the FAT entry. */ + + /* First, set the lower nibble of the FAT entry. */ + temp = (((UINT)*FAT_ptr) & 0x0F); + *FAT_ptr = (UCHAR)(temp | ((next_cluster << 4) & 0xF0)); + + /* Determine if this is a mulit-sector entry. */ + if ((multi_sector_entry) == (INT)i) + { + + /* Yes, requires multiple sector - will write rest of the part later. */ + continue; + } + + /* Move to the next byte of the FAT entry. */ + FAT_ptr++; + + /* Store the upper 8 bits of the FAT entry. */ + *FAT_ptr = (UCHAR)((next_cluster >> 4) & 0xFF); + } + else + { + + /* Even cluster number. */ + + /* Store the lower byte of the FAT entry. */ + *FAT_ptr = (UCHAR)(next_cluster & 0xFF); + + /* Determine if this is a mulit-sector entry. */ + if ((multi_sector_entry) == (INT)i) + { + + /* Yes, requires multiple sector - will write rest of the part later. */ + continue; + } + + /* Move to the next nibble of the FAT entry. */ + FAT_ptr++; + + /* Store the upper 4 bits of the FAT entry. */ + temp = ((UINT)*FAT_ptr) & 0xF0; + *FAT_ptr = (UCHAR)(temp | ((next_cluster >> 8) & 0xF)); + } + } + + /* First, write out the current sector. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Mark the FAT sector update bit map to indicate this sector has been written. */ + if (media_ptr -> fx_media_sectors_per_FAT % (FX_FAT_MAP_SIZE << 3) == 0) + { + sectors_per_bit = (UCHAR)((UINT)media_ptr -> fx_media_sectors_per_FAT / (FX_FAT_MAP_SIZE << 3)); + } + else + { + sectors_per_bit = (UCHAR)((UINT)media_ptr -> fx_media_sectors_per_FAT / (FX_FAT_MAP_SIZE << 3) + 1); + } + + /* Check for invalid value. */ + if (sectors_per_bit == 0) + { + + /* Invalid media, return error. */ + return(FX_MEDIA_INVALID); + } + + ind = ((FAT_sector - media_ptr -> fx_media_reserved_sectors) / sectors_per_bit) >> 3; + media_ptr -> fx_media_fat_secondary_update_map[ind] = + (UCHAR)((INT)media_ptr -> fx_media_fat_secondary_update_map[ind] + | (1 <<(((FAT_sector - media_ptr -> fx_media_reserved_sectors) / sectors_per_bit) & 7))); + + /* Determine if the multi-sector flag is set. */ + if (multi_sector_entry != -1) + { + + /* Yes, position to the next sector and read it in. */ + FAT_sector++; + } + else + { + + /* No, we are finished with this loop. */ + break; + } + } + } +#ifdef FX_ENABLE_EXFAT + else if (media_ptr -> fx_media_FAT_type == FX_FAT16) +#else + else if (!media_ptr -> fx_media_32_bit_FAT) +#endif /* FX_ENABLE_EXFAT */ + { + + /* 16-bit FAT is present. */ + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster) << 1); + + /* Calculate the FAT sector the requested FAT entry resides in. */ + FAT_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Read the FAT sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Loop through the remainder of the cache to check for multiple entries + within the same FAT sector being written out. */ + for (i = index; i < FX_MAX_FAT_CACHE; i++) + { + + /* Determine if the entry is dirty. */ + if (media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_dirty == 0) + { + + /* Not dirty, does not need to be flushed. */ + continue; + } + + /* Isolate the cluster. */ + cluster = (media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_cluster); + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster) * 2); + + /* Pickup the sector. */ + sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Is it the current FAT sector? */ + if (sector != FAT_sector) + { + + /* Different FAT sector - not in this pass of the loop. */ + continue; + } + + /* Now calculate the byte offset into this FAT sector. */ + byte_offset = byte_offset - + ((FAT_sector - (ULONG)media_ptr -> fx_media_reserved_sectors) * + media_ptr -> fx_media_bytes_per_sector); + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Pickup new value for this FAT entry. */ + next_cluster = media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_value; + + /* Store the FAT entry. */ + _fx_utility_16_unsigned_write(FAT_ptr, (UINT)next_cluster); + + /* Clear the dirty flag. */ + media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_dirty = 0; + } + + /* Write the last written FAT sector out. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + /* Return the error status. */ + return(status); + } + + /* Mark the FAT sector update bit map to indicate this sector has been + written. */ + if (media_ptr -> fx_media_sectors_per_FAT % (FX_FAT_MAP_SIZE << 3) == 0) + { + sectors_per_bit = (UCHAR)(media_ptr -> fx_media_sectors_per_FAT / (FX_FAT_MAP_SIZE << 3)); + } + else + { + sectors_per_bit = (UCHAR)((media_ptr -> fx_media_sectors_per_FAT / (FX_FAT_MAP_SIZE << 3)) + 1); + } + ind = ((FAT_sector - media_ptr -> fx_media_reserved_sectors) / sectors_per_bit) >> 3; + media_ptr -> fx_media_fat_secondary_update_map[ind] = + (UCHAR)((INT)media_ptr -> fx_media_fat_secondary_update_map[ind] + | (1 <<(((FAT_sector - media_ptr -> fx_media_reserved_sectors) / sectors_per_bit) & 7))); + } + else + { + + /* 32-bit FAT or exFAT are present. */ + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster) * 4); + + /* Calculate the FAT sector the requested FAT entry resides in. */ + FAT_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Read the FAT sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Loop through the remainder of the cache to check for multiple entries + within the same FAT sector being written out. */ + for (i = index; i < FX_MAX_FAT_CACHE; i++) + { + + /* Determine if the entry is dirty. */ + if (media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_dirty == 0) + { + + /* Not dirty, does not need to be flushed. */ + continue; + } + + /* Isolate the cluster. */ + cluster = (media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_cluster); + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster) * 4); + + /* Pickup the sector. */ + sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Is it the current FAT sector? */ + if (sector != FAT_sector) + { + + /* Different FAT sector - not in this pass of the loop. */ + continue; + } + + /* Now calculate the byte offset into this FAT sector. */ + byte_offset = byte_offset - + ((FAT_sector - (ULONG)media_ptr -> fx_media_reserved_sectors) * + media_ptr -> fx_media_bytes_per_sector); + + /* Setup a pointer into the buffer. */ + FAT_ptr = (UCHAR *)media_ptr -> fx_media_memory_buffer + (UINT)byte_offset; + + /* Pickup new value for this FAT entry. */ + next_cluster = media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_value; + + /* Store the FAT entry. */ + _fx_utility_32_unsigned_write(FAT_ptr, next_cluster); + + /* Clear the dirty flag. */ + media_ptr -> fx_media_fat_cache[i].fx_fat_cache_entry_dirty = 0; + } + + /* Write the last written FAT sector out. */ + status = _fx_utility_logical_sector_write(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + +#ifdef FX_ENABLE_EXFAT + /* We are not using fx_media_fat_secondary_update_map for exFAT. */ + if (media_ptr -> fx_media_FAT_type == FX_FAT32) + { +#endif /* FX_ENABLE_EXFAT */ + + /* Mark the FAT sector update bit map to indicate this sector has been + written. */ + if (media_ptr -> fx_media_sectors_per_FAT % (FX_FAT_MAP_SIZE << 3) == 0) + { + sectors_per_bit = (UCHAR)(media_ptr -> fx_media_sectors_per_FAT / (FX_FAT_MAP_SIZE << 3)); + } + else + { + sectors_per_bit = (UCHAR)((media_ptr -> fx_media_sectors_per_FAT / (FX_FAT_MAP_SIZE << 3)) + 1); + } + ind = ((FAT_sector - media_ptr -> fx_media_reserved_sectors) / sectors_per_bit) >> 3; + media_ptr -> fx_media_fat_secondary_update_map[ind] = + (UCHAR)((INT)media_ptr -> fx_media_fat_secondary_update_map[ind] + | (1 <<(((FAT_sector - media_ptr -> fx_media_reserved_sectors) / sectors_per_bit) & 7))); +#ifdef FX_ENABLE_EXFAT + } +#endif /* FX_ENABLE_EXFAT */ + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + + /* While fault_tolerant is enabled, this function will be called before the return of all APIs. */ + if (media_ptr -> fx_media_fault_tolerant_enabled) + { + + /* Delete the record of FAT sector since all FAT entries are flushed. */ + media_ptr -> fx_media_fault_tolerant_cached_FAT_sector = 0; + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Return successful status. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c new file mode 100644 index 00000000..0e63680e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_map_flush.c @@ -0,0 +1,172 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_FAT_map_flush PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function updates mirrors changes in the primary FAT to each of */ +/* secondary FATs in the media. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_read Read FAT sector into memory */ +/* _fx_utility_logical_sector_write Write FAT sector back to disk */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_FAT_map_flush(FX_MEDIA *media_ptr) +{ + +ULONG FAT_sector, last_sector; +UINT i, status, FATs; +UCHAR sectors_per_bit; + + + /* Determine how many FAT sectors each bit in the bit map represents. Depending on + the number of sectors in the primary FAT, each bit in this map may represent one + or more primary FAT sectors. Because of this, it is possible some FAT sectors that + were not changed may get flushed out to the secondary FAT. However, this method + provides very nice performance benefits during normal operation and is much more + reasonable than performing a total copy of the primary FAT to each secondary FAT + on media flush and media close. */ + if (media_ptr -> fx_media_sectors_per_FAT % (FX_FAT_MAP_SIZE << 3) == 0) + { + sectors_per_bit = (UCHAR)(media_ptr -> fx_media_sectors_per_FAT / (FX_FAT_MAP_SIZE << 3)); + } + else + { + sectors_per_bit = (UCHAR)(media_ptr -> fx_media_sectors_per_FAT / (FX_FAT_MAP_SIZE << 3) + 1); + } + + /* Loop through the FAT update map to mirror primary FAT sectors to secondary FAT(s). */ + for (i = 0; i < FX_FAT_MAP_SIZE << 3; i++) + { + + /* Determine if there are FAT changes specified by this entry. */ + if ((media_ptr -> fx_media_fat_secondary_update_map[i >> 3] & (1 << (i & 7))) == 0) + { + + /* No, look at the next bit map entry. */ + continue; + } + + /* Setup the parameters for performing the update. */ + FAT_sector = i * sectors_per_bit + media_ptr -> fx_media_reserved_sectors; + last_sector = FAT_sector + sectors_per_bit; + + /* Make sure the last update sector is within range. */ + if (last_sector > (media_ptr -> fx_media_sectors_per_FAT + media_ptr -> fx_media_reserved_sectors)) + { + last_sector = media_ptr -> fx_media_sectors_per_FAT + media_ptr -> fx_media_reserved_sectors; + } + + /* Loop to mirror primary FAT sectors to secondary FAT(s). */ + for (; FAT_sector < last_sector; FAT_sector++) + { + + /* Read the FAT sector. */ + status = _fx_utility_logical_sector_read(media_ptr, (ULONG64) FAT_sector, + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + /* Return the error status. */ + return(status); + } + + /* Pickup how many secondary FATs there are. */ + FATs = media_ptr -> fx_media_number_of_FATs - 1; + + /* Loop to update additional FAT entries. */ + while (FATs) + { + + /* Mirror main FAT sector write into the additional FATs. */ + status = _fx_utility_logical_sector_write(media_ptr, + ((ULONG64) FAT_sector) + ((ULONG64)FATs * (ULONG64)(media_ptr -> fx_media_sectors_per_FAT)), + media_ptr -> fx_media_memory_buffer, ((ULONG) 1), FX_FAT_SECTOR); + + /* Determine if an error occurred. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Decrement the number of FATs. */ + FATs--; + } + } + } + + /* Clear the bit map that indicates primary FAT updates. */ + for (i = 0; i < FX_FAT_MAP_SIZE; i++) + { + + /* Clear each entry in the bit map. */ + media_ptr -> fx_media_fat_secondary_update_map[i] = 0; + } + + /* Return a successful completion. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c new file mode 100644 index 00000000..b8909777 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_FAT_sector_get.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_FAT_sector_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the sector of supplied FAT entry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster entry number */ +/* */ +/* OUTPUT */ +/* */ +/* return sector of FAT entry */ +/* */ +/* CALLS */ +/* */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _fx_utility_FAT_sector_get(FX_MEDIA *media_ptr, ULONG cluster) +{ + +ULONG FAT_sector; +ULONG byte_offset; + + /* Determine which type of FAT is present. */ +#ifdef FX_ENABLE_EXFAT + if (media_ptr -> fx_media_FAT_type == FX_FAT12) +#else + if (media_ptr -> fx_media_12_bit_FAT) +#endif /* FX_ENABLE_EXFAT */ + { + + /* 12-bit FAT is present. */ + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster << 1) + cluster) >> 1; + + } +#ifdef FX_ENABLE_EXFAT + else if (media_ptr -> fx_media_FAT_type == FX_FAT16) +#else + else if (!media_ptr -> fx_media_32_bit_FAT) +#endif /* FX_ENABLE_EXFAT */ + { + + /* 16-bit FAT is present. */ + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster) << 1); + } + else + { + + /* 32-bit FAT or exFAT are present. */ + + /* Calculate the byte offset to the cluster entry. */ + byte_offset = (((ULONG)cluster) * 4); + } + + /* Calculate the FAT sector the requested FAT entry resides in. */ + FAT_sector = (byte_offset / media_ptr -> fx_media_bytes_per_sector) + + (ULONG)media_ptr -> fx_media_reserved_sectors; + + /* Return successful status. */ + return(FAT_sector); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c b/src/Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c new file mode 100644 index 00000000..e10ad28e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_absolute_path_get.c @@ -0,0 +1,254 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_utility.h" + + +#ifdef FX_ENABLE_EXFAT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_absolute_path_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts concatenating of base and new path to */ +/* absolute path. */ +/* */ +/* INPUT */ +/* */ +/* base_path Base (current) path */ +/* new_path New path */ +/* absolute_path Absolute Path */ +/* */ +/* OUTPUT */ +/* */ +/* absolute_path Resulting absolute path */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_token_length_get Get the next token length */ +/* _fx_utility_string_length_get Get string length */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_default_set */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_absolute_path_get(CHAR *base_path, CHAR *new_path, CHAR *absolute_path) +{ + +UINT length; +UINT absolute_position; +UINT i; + + + /* Check if we got null pointers. */ + if (!base_path || !new_path || !absolute_path) + { + + /* Return error. */ + return(FX_INVALID_PATH); + } + + /* Is the new path starts from root? */ + if ((new_path[0] == '\\') || (new_path[0] == '/')) + { + + /* Yes, set the absolute path to root. */ + absolute_path[0] = '\\'; + absolute_path[1] = 0; + new_path++; + } + else + { + + /* Initialize the absolute path with the base path. */ + i = 0; + while ((base_path[i]) && (i < FX_MAXIMUM_PATH)) + { + + /* Copy a character. */ + absolute_path[i] = base_path[i]; + + /* Move to next character. */ + i++; + } + + /* Is the absolute path still NULL? */ + if ((absolute_path[0] == 0) || (i == 0)) + { + + /* Yes, set the absolute path to root. */ + absolute_path[0] = '\\'; + absolute_path[1] = 0; + } + } + + /* Loop to add new path to the absolute path. */ + while ((length = _fx_utility_token_length_get(new_path)) > 0) + { + + /* Check if the path is too long. */ + if ((new_path[length] != 0) && (new_path[length] != '\\') && (new_path[length] != '/')) + { + /* The path is too long, return error. */ + return(FX_INVALID_PATH); + } + + /* Check if we have a current directory mark. */ + if ((length == 1) && (new_path[0] == '.')) + { + + /* The same directory, just skip it. */ + } + /* Do we have a parent directory mark? */ + else if ((length == 2) && (new_path[0] == '.') && (new_path[1] == '.')) + { + + /* Yes, we need to move the absolute path to the parent directory. */ + /* Check absolute path length. */ + absolute_position = _fx_utility_string_length_get(absolute_path, FX_MAXIMUM_PATH); + if ((absolute_position < 2) || (absolute_path[absolute_position] != 0)) + { + + /* No parent directory left in the absolute path, or invalid path length, return error. */ + return(FX_INVALID_PATH); + } + + /* Move to the last character of the absolute path. */ + absolute_position--; + + /* Check if we have a directory separator. */ + if ((absolute_path[absolute_position] == '\\') || (absolute_path[absolute_position] == '/')) + { + + /* Remove the separator. */ + absolute_path[absolute_position] = 0; + absolute_position--; + } + + /* Loop to clear the character backward until a seprator or string exhaust. */ + while ((absolute_path[absolute_position] != '\\') && (absolute_path[absolute_position] != '/') && (absolute_position > 0)) + { + + /* Remove one character. */ + absolute_path[absolute_position] = 0; + absolute_position--; + } + + /* Do we have somthing left in the path? */ + if (absolute_position > 1) + { + + /* Yes, remove the last separator. */ + absolute_path[absolute_position] = 0; + } + } + else + { + + /* Normal directory, add it. */ + absolute_position = _fx_utility_string_length_get(absolute_path, FX_MAXIMUM_PATH); + + /* Check if the path is too long. */ + if (absolute_path[absolute_position] != 0) + { + + /* The path is too long, return error. */ + return(FX_INVALID_PATH); + } + + /* Check if we have something in the path. */ + if (absolute_position) + { + + /* Do we have a separator in the last character? */ + if ((absolute_path[absolute_position - 1] != '\\') && (absolute_path[absolute_position - 1] != '/')) + { + + /* No, add a directory separator to the path string. */ + absolute_path[absolute_position] = '\\'; + absolute_position++; + } + } + + /* Loop to copy the new path to the absolute path. */ + i = 0; + while ((absolute_position < FX_MAXIMUM_PATH) && (i < length)) + { + + /* Copy one character. */ + absolute_path[absolute_position++] = new_path[i++]; + } + + /* Check if we have not exceed the maximum length. */ + if (absolute_position < FX_MAXIMUM_PATH) + { + + /* Terminate the string. */ + absolute_path[absolute_position] = 0; + } + else + { + + /* The path is too long, return error. */ + return(FX_INVALID_PATH); + } + } + + /* Move to the next component. */ + new_path += length; + + /* Is the next component starts with a separator? */ + if ((new_path[0] == '\\') || (new_path[0] == '/')) + { + + /* Yes, skip it. */ + new_path++; + } + } + + return(FX_SUCCESS); +} +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c new file mode 100644 index 00000000..d46e2a26 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_allocate_new_cluster.c @@ -0,0 +1,232 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_directory.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_allocate_new_cluster PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates new cluster media for a free */ +/* directory entry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_ptr Pointer to directory to */ +/* search in */ +/* last_cluster Last cluster of entry */ +/* cluster Allocated cluster */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_exFAT_entry_read Read exFAT entries */ +/* _fx_utility_exFAT_bitmap_flush Flush exFAT allocation bitmap */ +/* _fx_utility_exFAT_bitmap_free_cluster_find */ +/* Find free cluster */ +/* _fx_utility_exFAT_cluster_state_get Get cluster state */ +/* _fx_utility_FAT_entry_read Read FAT entry */ +/* _fx_utility_FAT_entry_write Write FAT entry */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_exFAT_free_search */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_allocate_new_cluster(FX_MEDIA *media_ptr, FX_DIR_ENTRY *directory_ptr, + ULONG *last_cluster, ULONG *cluster) +{ + +UINT status = FX_SUCCESS; +ULONG cluster_count; +ULONG bytes_per_cluster; +ULONG i; +ULONG FAT_value = 0; +UCHAR cluster_state = FX_EXFAT_BITMAP_CLUSTER_OCCUPIED; + + + /* Clear the last cluster number. */ + *last_cluster = 0; + + /* Check if we have any already allocated clusters. */ + if (!directory_ptr || (directory_ptr -> fx_dir_entry_available_file_size > 0)) + { + + /* Calculate bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Check if FAT table is not used. */ + if (directory_ptr && (directory_ptr -> fx_dir_entry_dont_use_fat & 1)) + { + + /* Calculate the cluster count associated with the directory. */ + cluster_count = (ULONG)((directory_ptr -> fx_dir_entry_available_file_size + bytes_per_cluster - 1) / + bytes_per_cluster); + + /* Calculate the next cluster and the last cluster. */ + *cluster = directory_ptr -> fx_dir_entry_cluster + cluster_count; + *last_cluster = *cluster - 1; + + /* Make sure the next cluster number don't exceed the total cluster number. */ + if (*cluster < media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) + { + + /* Get cluster state. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, *cluster, &cluster_state); + + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + } + + /* Is the next cluster free? */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_FREE) + { + + /* Yes, so we still don't need to use FAT. */ + return(FX_SUCCESS); + } + + /* Now we should use FAT. Clear the bit 0. */ + directory_ptr -> fx_dir_entry_dont_use_fat &= (CHAR)0xfe; + + /* Loop to build FAT chain. */ + for (i = directory_ptr -> fx_dir_entry_cluster; i < *last_cluster; ++i) + { + + /* Write the FAT entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, i, i + 1); + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + } + + /* Write last cluster entry. */ + status = _fx_utility_FAT_entry_write(media_ptr, *last_cluster, FX_LAST_CLUSTER_exFAT); + + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + } + else + { + + /* Find last cluster by walk through the FAT chain. */ + /* See if we are in sub directory or the root directory. And set the start cluster. */ + if (directory_ptr) + { + *cluster = directory_ptr -> fx_dir_entry_cluster; + } + else + { + *cluster = media_ptr -> fx_media_root_cluster_32; + } + + /* Initialize loop variables. */ + *last_cluster = 0; + i = 0; + + /* Follow the link of FAT entries. */ + while ((*cluster >= FX_FAT_ENTRY_START) && (*cluster < FX_RESERVED_1_exFAT)) + { + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, *cluster, &FAT_value); + i++; + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + + /* Determine if the FAT read was invalid. */ + if ((*cluster == FAT_value) || (i > media_ptr -> fx_media_total_clusters)) + { + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + /* Save the last valid cluster. */ + *last_cluster = *cluster; + + /* Setup for the next cluster. */ + *cluster = FAT_value; + } + } + } + + /* Find free cluster from exFAT media. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, + media_ptr -> fx_media_cluster_search_start, + cluster); + + return(status); +} + + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c new file mode 100644 index 00000000..4369273c --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_prepare.c @@ -0,0 +1,120 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_bitmap_cache_prepare PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if the bitmap for specified cluster is in */ +/* cache. If not, it will read the bitmap portion to cache. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster number */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_bitmap_flush Flush bitmap cache */ +/* _fx_utility_exFAT_bitmap_cache_update Read bitmap to cache */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_bitmap_cache_prepare(FX_MEDIA *media_ptr, ULONG cluster) +{ + +UINT status; + + + /* Default the status to no more space. */ + status = FX_NO_MORE_SPACE; + + /* Make sure the cluster does not exceed the total count. */ + if (cluster < media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) + { + + /* Check if the request cluster is already cached. */ + if ((cluster >= media_ptr -> fx_media_exfat_bitmap_cache_start_cluster) && + (cluster <= media_ptr -> fx_media_exfat_bitmap_cache_end_cluster)) + { + + /* Cluster already cached. */ + status = FX_SUCCESS; + } + else + { + + /* Need to Cache update. */ + + /* Flush previous cached data if required. */ + if (FX_SUCCESS == (status = _fx_utility_exFAT_bitmap_flush(media_ptr))) + { + + /* Call utility function to update cache. */ + status = _fx_utility_exFAT_bitmap_cache_update(media_ptr, cluster); + } + } + } + + /* Return status. */ + return(status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c new file mode 100644 index 00000000..b546a79e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_cache_update.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_bitmap_cache_update PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads parts of exFAT bitmap to cache. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster number */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* Media driver */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_bitmap_cache_update(FX_MEDIA *media_ptr, ULONG cluster) +{ + + /* Read exFAT bitmap to cache. */ + cluster -= FX_FAT_ENTRY_START; + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_buffer = (UCHAR *)media_ptr -> fx_media_exfat_bitmap_cache; + media_ptr -> fx_media_driver_logical_sector = media_ptr -> fx_media_exfat_bitmap_start_sector + + (cluster >> media_ptr -> fx_media_exfat_bitmap_clusters_per_sector_shift); + media_ptr -> fx_media_driver_sectors = media_ptr -> fx_media_exfat_bitmap_cache_size_in_sectors; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* Invoke the driver to read the FAT sectors. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Calculate new cached clusters. */ + media_ptr -> fx_media_exfat_bitmap_cache_start_cluster = + (ULONG)((media_ptr -> fx_media_driver_logical_sector - media_ptr -> fx_media_exfat_bitmap_start_sector) << + media_ptr -> fx_media_exfat_bitmap_clusters_per_sector_shift) + + FX_FAT_ENTRY_START; + + media_ptr -> fx_media_exfat_bitmap_cache_end_cluster = media_ptr -> fx_media_exfat_bitmap_cache_start_cluster + + ((media_ptr -> fx_media_exfat_bitmap_cache_size_in_sectors << media_ptr -> fx_media_exfat_bytes_per_sector_shift) << + BITS_PER_BYTE_SHIFT) - 1; + + /* Return driver status. */ + return(media_ptr -> fx_media_driver_status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c new file mode 100644 index 00000000..6f92ba9c --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_flush.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + +/* Include necessary system files. */ + + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_bitmap_flush PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes cached exFAT bitmap back to media. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* Media driver */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_bitmap_flush(FX_MEDIA *media_ptr) +{ + + /* Check if the bitmap cache is dirty. */ + if (FX_TRUE == media_ptr -> fx_media_exfat_bitmap_cache_dirty) + { + + /* Write cached exFAT bitmap. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = (UCHAR *)media_ptr -> fx_media_exfat_bitmap_cache; + media_ptr -> fx_media_driver_sectors = media_ptr -> fx_media_exfat_bitmap_cache_size_in_sectors; + + media_ptr -> fx_media_driver_logical_sector = media_ptr -> fx_media_exfat_bitmap_start_sector + + ((media_ptr -> fx_media_exfat_bitmap_cache_start_cluster - FX_FAT_ENTRY_START) >> + media_ptr -> fx_media_exfat_bitmap_clusters_per_sector_shift); + + /* Invoke the driver to write the bitmap sectors. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Determine if the write was successful. */ + if (media_ptr -> fx_media_driver_status == FX_SUCCESS) + { + + /* Set bitmap cache dirty flag to false. */ + media_ptr -> fx_media_exfat_bitmap_cache_dirty = FX_FALSE; + } + } + else + { + + /* Initialize return status to success. */ + media_ptr -> fx_media_driver_status = FX_SUCCESS; + } + + return(media_ptr -> fx_media_driver_status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c new file mode 100644 index 00000000..08d85b96 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_free_cluster_find.c @@ -0,0 +1,161 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + +/* Include necessary system files. */ + + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_bitmap_free_cluster_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function searches for a free cluster. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* search_start_cluster Cluster number to begin search*/ +/* free_cluster ULONG pointer to store cluster*/ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_cluster_state_get Get cluster state */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_bitmap_free_cluster_find(FX_MEDIA *media_ptr, ULONG search_start_cluster, ULONG *free_cluster) +{ + +UINT status; +UCHAR cluster_state; +ULONG cluster = search_start_cluster; + + + /* Search for a free cluster. */ + while (cluster < media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) + { + + /* Get the cluster state. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, cluster, &cluster_state); + + /* Check the status of the state get. */ + if (status != FX_SUCCESS) + { + + /* Media error or out of total clusters number - stop searching. */ + return(status); + } + + /* Is this cluster free? */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_FREE) + { + + /* Yes, finished the search. */ + + /* Return the cluster. */ + *free_cluster = cluster; + + /* Return success. */ + return(FX_SUCCESS); + } + + /* Move to next cluster. */ + cluster++; + } + + /* See if there is anything to search in the beginning. */ + if (search_start_cluster > FX_FAT_ENTRY_START) + { + + /* Start at the beginning. */ + cluster = FX_FAT_ENTRY_START; + + /* Loop to search clusters. */ + while (cluster < search_start_cluster) + { + + /* Get the cluster state. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, cluster, &cluster_state); + if (status != FX_SUCCESS) + { + + /* Media error or out of total clusters number - stop searching. */ + return(status); + } + + /* Is this cluster free? */ + if (cluster_state == FX_EXFAT_BITMAP_CLUSTER_FREE) + { + + /* Yes, finished the search. */ + + /* Return the cluster. */ + *free_cluster = cluster; + + /* Return success. */ + return(FX_SUCCESS); + } + + /* Move to the next cluster. */ + cluster++; + } + } + + /* No more free clusters, return error. */ + return(FX_NO_MORE_SPACE); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c new file mode 100644 index 00000000..91c6cce7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_initialize.c @@ -0,0 +1,186 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_bitmap_initialize PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes bitmap for exFAT volume. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* Media driver */ +/* _fx_utility_exFAT_bitmap_free_cluster_find */ +/* Find free cluster */ +/* _fx_utility_exFAT_bitmap_cache_update Read bitmap cache */ +/* _fx_utility_exFAT_bitmap_start_sector_get */ +/* Get the bitmap starting sector*/ +/* _fx_utility_exFAT_cluster_state_get Get cluster state */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_bitmap_initialize(FX_MEDIA *media_ptr) +{ + +UINT status; +ULONG cluster; +UCHAR cluster_state; +ULONG bitmap_cache_size; +ULONG bitmap_size_in_bytes; +ULONG bitmap_size_in_sectors; +ULONG bitmap_total_size_in_bytes; + + + /* Calculate exFAT bitmap size. */ + bitmap_size_in_bytes = DIVIDE_TO_CEILING(media_ptr -> fx_media_total_clusters, BITS_PER_BYTE); + bitmap_size_in_sectors = DIVIDE_TO_CEILING(bitmap_size_in_bytes, media_ptr -> fx_media_bytes_per_sector); + + /* Align bitmap size by sectors size. */ + bitmap_total_size_in_bytes = bitmap_size_in_sectors << media_ptr -> fx_media_exfat_bytes_per_sector_shift; + + /* Set default bitMap cache size. */ + bitmap_cache_size = media_ptr -> fx_media_bytes_per_sector * FX_EXFAT_BIT_MAP_NUM_OF_CACHED_SECTORS; + + /* Do not use the memory if it not required. */ + if (bitmap_cache_size > bitmap_total_size_in_bytes) + { + + /* Adjust the cache size. */ + bitmap_cache_size = bitmap_total_size_in_bytes; + } + + /* Try to find BitMap start sector. */ + status = _fx_utility_exFAT_bitmap_start_sector_get(media_ptr, &media_ptr -> fx_media_exfat_bitmap_start_sector); + + /* Did we get the starting sector? */ + if (status == FX_SUCCESS) + { + + /* Yes, setup the media cache parameters. */ + media_ptr -> fx_media_exfat_bitmap_cache_size_in_sectors = + bitmap_cache_size >> media_ptr -> fx_media_exfat_bytes_per_sector_shift; + + media_ptr -> fx_media_exfat_bitmap_cache_dirty = FX_FALSE; + media_ptr -> fx_media_exfat_bitmap_cache_start_cluster = FX_FAT_ENTRY_START; + + /* Calculate how many clusters mapped in the one sector. */ + media_ptr -> fx_media_exfat_bitmap_clusters_per_sector_shift = + media_ptr -> fx_media_exfat_bytes_per_sector_shift + + BITS_PER_BYTE_SHIFT; + + /* Start at initial cluster. */ + cluster = FX_FAT_ENTRY_START; + + /* Read first portion of BitMap. */ + status = _fx_utility_exFAT_bitmap_cache_update(media_ptr, cluster); + + /* Was the BitMap read successful? */ + if (status == FX_SUCCESS) + { + + /* Find first free cluster. */ + status = _fx_utility_exFAT_bitmap_free_cluster_find(media_ptr, cluster, &cluster); + + /* Did we find a free cluster? */ + if (status == FX_SUCCESS) + { + + /* Save first free cluster number. */ + media_ptr -> fx_media_cluster_search_start = cluster; + + /* Calculate number of free clusters from first free cluster. */ + while (cluster < media_ptr -> fx_media_total_clusters + FX_FAT_ENTRY_START) + { + + /* Get the state of the cluster. */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, cluster, &cluster_state); + + /* Was the state get successful? */ + if (status != FX_SUCCESS) + { + + /* No, get out of the loop. */ + break; + } + + /* Is the cluster free? */ + if (FX_EXFAT_BITMAP_CLUSTER_FREE == cluster_state) + { + + /* Yes, increment the available clusters. */ + media_ptr -> fx_media_available_clusters++; + } + + /* Move to next cluster. */ + cluster++; + } + } + } + } + + /* Return status. */ + return(status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c new file mode 100644 index 00000000..5aeda912 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_bitmap_start_sector_get.c @@ -0,0 +1,153 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_bitmap_start_sector_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the start sector of exFAT bitmap. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* bitmap_started_sector Pointer to ULONG */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_read Read logical sector */ +/* _fx_utility_64_unsigned_read Read a ULONG64 from memory */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_bitmap_start_sector_get(FX_MEDIA *media_ptr, ULONG *bitmap_started_sector) +{ + +ULONG sectors_count; +UCHAR *dir_entry_ptr; + + + /* Initialize the sector count. */ + sectors_count = 0; + + /* Go through the first cluster of exFAT root directory. This cluster should + contain BitMap allocation DirEntry */ + while (sectors_count < media_ptr -> fx_media_sectors_per_cluster) + { + + /* Will use read sector function with cache functionality since first cluster + will be used by other services. */ + if (FX_SUCCESS != _fx_utility_logical_sector_read(media_ptr, + (ULONG64) (media_ptr -> fx_media_root_sector_start + sectors_count), + media_ptr -> fx_media_memory_buffer, + ((ULONG) 1), FX_DATA_SECTOR)) + { + + /* Error reading the sector, get out of the loop. */ + break; + } + + /* Increment the sectors count. */ + sectors_count++; + + /* Setup pointer to directory entry. */ + dir_entry_ptr = media_ptr -> fx_media_memory_buffer; + + /* Go through the read buffer and try to find BitMap table directory entry. */ + while (dir_entry_ptr < (media_ptr -> fx_media_memory_buffer + + media_ptr -> fx_media_bytes_per_sector)) + { + + /* Determine if this entry is the bitmap allocation type. */ + if (FX_EXFAT_DIR_ENTRY_TYPE_ALLOCATION_BITMAP == dir_entry_ptr[FX_EXFAT_ENTRY_TYPE]) + { + + /* Yes, calculate BitMap table start sector. */ + *bitmap_started_sector = media_ptr -> fx_media_data_sector_start + + (UINT)((dir_entry_ptr[FX_EXFAT_FIRST_CLUSTER] - FX_FAT_ENTRY_START) << + media_ptr -> fx_media_exfat_sector_per_clusters_shift); + + /* Check FirstCluster and DataLength fields for error. */ + if ((0 == *bitmap_started_sector) || + (media_ptr -> fx_media_total_clusters > + ((ULONG)_fx_utility_64_unsigned_read(&dir_entry_ptr[FX_EXFAT_DATA_LENGTH]) << + BITS_PER_BYTE_SHIFT))) + { + + /* Media invalid - return error! */ + return(FX_MEDIA_INVALID); + } + + /* Return success! */ + return(FX_SUCCESS); + } + else + { + + /* Move to next directory entry. */ + dir_entry_ptr += FX_EXFAT_DIR_ENTRY_SIZE; + } + } + } + + /* Return media invalid error. */ + return(FX_MEDIA_INVALID); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c new file mode 100644 index 00000000..bc30e6be --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_free.c @@ -0,0 +1,215 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_cluster_free PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deallocates clusters deleted unknown type */ +/* directory entry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* work_ptr Pointer to directory to */ +/* unknown directory entry */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_32_unsigned_read Read 32-bit value */ +/* _fx_utility_64_unsigned_read Read 64-bit value */ +/* _fx_utility_FAT_entry_read Read FAT entry */ +/* _fx_utility_FAT_entry_write Write FAT entry */ +/* _fx_utility_exFAT_cluster_state_set Set cluster state */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_exFAT_unicode_entry_write */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_cluster_free(FX_MEDIA *media_ptr, UCHAR *work_ptr) +{ + +ULONG cluster; +ULONG64 data_length; +ULONG clusters_released; +ULONG clusters_count; +ULONG bytes_per_cluster; +ULONG contents = 0; +UCHAR dont_use_fat; +UINT status; + + + /* Pickup the cluster to release. */ + cluster = _fx_utility_32_unsigned_read(&(work_ptr[FX_EXFAT_FIRST_CLUSTER])); + + /* Pickup the data length. */ + data_length = _fx_utility_64_unsigned_read(&(work_ptr[FX_EXFAT_DATA_LENGTH])); + + /* Pickup the flag that determines if the FAT should be used. */ + dont_use_fat = (work_ptr[FX_EXFAT_SECOND_FLAG] >> 1) & 1; + + /* Default status to success. */ + status = FX_SUCCESS; + + /* Is the allocation possible flag cleared? Is there any allocated cluster for this entry? */ + if (((work_ptr[FX_EXFAT_SECOND_FLAG] & FX_EXFAT_SECOND_FLAG_ALLOCATION_POSSIBLE_MASK) == 0) || + (cluster == 0) || + (data_length == 0)) + { + + /* No cluster allocated to this entry, nothing to deallocate. */ + return(FX_SUCCESS); + } + + /* Calculate the number of bytes per cluster. */ + bytes_per_cluster = ((ULONG)media_ptr -> fx_media_bytes_per_sector) * + ((ULONG)media_ptr -> fx_media_sectors_per_cluster); + + /* Determine how many clusters. */ + clusters_count = (ULONG)((data_length + bytes_per_cluster - 1) / bytes_per_cluster - 1); + + /* Initialize released cluster count to 0. */ + clusters_released = 0; + + /* Follow the link of FAT entries. */ + while ((cluster >= FX_FAT_ENTRY_START) && (cluster < FX_RESERVED_1_exFAT)) + { + + /* Increment the number of clusters released. */ + clusters_released++; + + /* Determine if the FAT chain is to be used. */ + if (dont_use_fat) + { + + /* Yes, don't use the FAT chain. */ + + /* Check for file size range. */ + if (clusters_released - 1 >= clusters_count) + { + + /* Set the next cluster to LAST to indicate it is the last cluster. */ + contents = FX_LAST_CLUSTER_exFAT; + } + else + { + + /* The next cluster is just after the current cluster. */ + contents = cluster + 1; + } + } + else + { + + /* Read the current cluster entry from the FAT. */ + status = _fx_utility_FAT_entry_read(media_ptr, cluster, &contents); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + } + + /* Check for data corruption. */ + if ((cluster == contents) || (clusters_released > media_ptr -> fx_media_total_clusters)) + { + + /* Return the bad status. */ + return(FX_FAT_READ_ERROR); + } + + /* Make the current cluster available. */ + if (!dont_use_fat) + { + + /* Write the FAT to free the cluster. */ + status = _fx_utility_FAT_entry_write(media_ptr, cluster, FX_FREE_CLUSTER); + + /* Check the return value. */ + if (status != FX_SUCCESS) + { + + /* Return the error status. */ + return(status); + } + } + + /* Set cluster state in the bitmap. */ + status = _fx_utility_exFAT_cluster_state_set(media_ptr, cluster, FX_EXFAT_BITMAP_CLUSTER_FREE); + + /* Check the return status. */ + if (status != FX_SUCCESS) + { + + /* Return the bad status. */ + return(status); + } + + /* Setup for the next cluster. */ + cluster = contents; + } + + /* Update the free clusters in the media control block. */ + media_ptr -> fx_media_available_clusters = media_ptr -> fx_media_available_clusters + clusters_released; + + /* Return success. */ + return(FX_SUCCESS); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c new file mode 100644 index 00000000..95664adf --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_get.c @@ -0,0 +1,157 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_cluster_state_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the cluster state of exFAT volume. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster number */ +/* cluster_state UCHAR pointer to store state */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_bitmap_cache_prepare */ +/* Read bitmap to cache */ +/* _fx_fault_tolerant_read_FAT Read FAT entry from log file */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_cluster_state_get(FX_MEDIA *media_ptr, ULONG cluster, UCHAR *cluster_state) +{ + +UINT status; +UINT bitmap_offset; +UCHAR cluster_shift; +UCHAR eight_clusters_block; +#ifdef FX_ENABLE_FAULT_TOLERANT +ULONG value; + + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED)) + { + + + /* Redirect this request to the log file. + During file or directory operations with Fault Tolerant + protection, intermediate operations are written to the fault + tolerant log file. Therefore, FAT-entry read should search for + fault tolerant log before the request can be passed to normal FAT + entry read routine. + */ + status = _fx_fault_tolerant_read_FAT(media_ptr, cluster, &value, FX_FAULT_TOLERANT_BITMAP_LOG_TYPE); + + /* Return on success. */ + if (status != FX_READ_CONTINUE) + { + *cluster_state = (UCHAR)value; + return(status); + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Prepare bitmap cache. */ + status = _fx_utility_exFAT_bitmap_cache_prepare(media_ptr, cluster); + + /* Was it successful? */ + if (status == FX_SUCCESS) + { + + /* Calculate the bitmap offset. */ + bitmap_offset = (UINT)(cluster - media_ptr -> fx_media_exfat_bitmap_cache_start_cluster) >> BITS_PER_BYTE_SHIFT; + + /* Pickup the 8 cluster block. */ + eight_clusters_block = *(media_ptr -> fx_media_exfat_bitmap_cache + bitmap_offset); + + /* Check all 8 bits for 0x00 (all clusters in the block are free). */ + if (eight_clusters_block == 0x00) + { + + /* Cluster is free, return state. */ + *cluster_state = FX_EXFAT_BITMAP_CLUSTER_FREE; + } + /* Check all 8 bits for 0xFF (all 8 clusters are occupied). */ + else if (0xFF == eight_clusters_block) + { + + /* Cluster is not free, return state. */ + *cluster_state = FX_EXFAT_BITMAP_CLUSTER_OCCUPIED; + } + else + { + + /* Check bit respondent for cluster state. */ + cluster_shift = (UCHAR)((cluster - FX_FAT_ENTRY_START) % BITS_PER_BYTE); + + *cluster_state = (eight_clusters_block >> cluster_shift) & 0x1; + } + } + + /* Return status. */ + return(status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c new file mode 100644 index 00000000..09c842e7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_cluster_state_set.c @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_cluster_state_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the cluster state of exFAT volume. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* cluster Cluster number */ +/* new_cluster_state Cluster state to set */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_cluster_state_get Get cluster state */ +/* _fx_fault_tolerant_add_bitmap_log Add bitmap redo log */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_cluster_state_set(FX_MEDIA *media_ptr, ULONG cluster, UCHAR new_cluster_state) +{ + +UINT status; +UCHAR cluster_state; +UINT bitmap_offset; +UCHAR cluster_shift; + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED) && + !(media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_SET_FAT_CHAIN)) + { + + /* Redirect this request to log file. + Under fault tolerant protection, the changes to FAT is recorded in the fault tolerant + log, in case the operation fails, the changes can be reverted. */ + return(_fx_fault_tolerant_add_bitmap_log(media_ptr, cluster, new_cluster_state)); + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + /* Get the state of the cluster? */ + status = _fx_utility_exFAT_cluster_state_get(media_ptr, cluster, &cluster_state); + + /* Was the state get successful? */ + if (status == FX_SUCCESS) + { + + /* Is it the same state? */ + if (new_cluster_state != cluster_state) + { + + /* No, we need to set the state. */ + + /* Calculate the bitmap offset. */ + bitmap_offset = (UINT)(cluster - media_ptr -> fx_media_exfat_bitmap_cache_start_cluster) >> BITS_PER_BYTE_SHIFT; + + /* Calculate where the cluster is located. */ + cluster_shift = (UCHAR)((cluster - FX_FAT_ENTRY_START) % BITS_PER_BYTE); + + /* Is occupied the new state? */ + if (FX_EXFAT_BITMAP_CLUSTER_OCCUPIED == new_cluster_state) + { + + /* Yes, mark this cluster as occupied. */ + *(media_ptr -> fx_media_exfat_bitmap_cache + bitmap_offset) = (UCHAR)(*(media_ptr -> fx_media_exfat_bitmap_cache + bitmap_offset) | (1 << cluster_shift)); + } + else + { + + /* No, mark this cluster as not occupied. */ + *(media_ptr -> fx_media_exfat_bitmap_cache + bitmap_offset) &= (UCHAR)~(1 << cluster_shift); + } + + /* Mark the cache as dirty. */ + media_ptr -> fx_media_exfat_bitmap_cache_dirty = FX_TRUE; + } + } + + /* Return status. */ + return(status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c new file mode 100644 index 00000000..585ec648 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_geometry_check.c @@ -0,0 +1,320 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_geometry_check PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks exFAT geometry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* sector_buffer Pointer to sector buffer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_exFAT_system_area_checksum_verify Verify SystemArea checksum */ +/* _fx_utility_64_unsigned_read Read ULONG64 from memory */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), replaced */ +/* sector size constant, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_geometry_check(FX_MEDIA *media_ptr, UCHAR *sector_buffer) +{ + +ULONG temp; +ULONG counter; +ULONG calculated_checksum = 0; +ULONG main_system_area_checksum = 0; +ULONG backup_system_area_checksum = 0; +ULONG bitmap_start_sector = 0; +ULONG bitmap_size_in_bytes = 0; +ULONG upcase_table_start_sector = 0; +ULONG upcase_table_size_in_bytes = 0; +ULONG upcase_table_checksum = 0; +UCHAR *dir_entry_ptr = NULL; +ULONG dir_entries_found = 0; +UINT status; + + + /* Check FAT Size. */ + temp = (media_ptr -> fx_media_sectors_per_FAT << + media_ptr -> fx_media_exfat_bytes_per_sector_shift) >> + FX_EXFAT_SIZE_OF_FAT_ELEMENT_SHIFT; + + /* Is the FAT capable of holding the total number of clusters? */ + if (temp < media_ptr -> fx_media_total_clusters) + { + + /* No, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Check Cluster Heap Offset. */ + temp = media_ptr -> fx_media_reserved_sectors + + media_ptr -> fx_media_sectors_per_FAT; + + /* Is the cluster heap placed after the FAT table? */ + if (temp > media_ptr -> fx_media_data_sector_start) + { + + /* No, the media is invalid. */ + return(FX_MEDIA_INVALID); + } + + /* Check System Area checksum. */ + status = _fx_utility_exFAT_system_area_checksum_verify(media_ptr, + sector_buffer, + FX_EXFAT_FAT_MAIN_BOOT_SECTOR_OFFSET, + &main_system_area_checksum); + + /* Is the checksum correct? */ + if (FX_SUCCESS != status) + { + + /* No, return error. */ + return(status); + } + + /* Check System Area checksum in backup region. */ + status = _fx_utility_exFAT_system_area_checksum_verify(media_ptr, + sector_buffer, + FX_EXFAT_FAT_BACKUP_BOOT_SECTOR_OFFSET, + &backup_system_area_checksum); + + /* Is the checksum correct? */ + if (FX_SUCCESS != status) + { + + /* No, return error. */ + return(status); + } + + /* Is the main system area checksum equals to the backup system area checksum? */ + if (main_system_area_checksum != backup_system_area_checksum) + { + + /* No, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Get Bit Map and Up Case table parameters. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_buffer = sector_buffer; + media_ptr -> fx_media_driver_sectors = 1; + + counter = 0; + + /* Go through the first cluster of exFAT root directory. + This cluster should contain BitMap allocation Dir Entry + and Up Case table Dir Entry. */ + while ((counter < media_ptr -> fx_media_sectors_per_cluster) && + (EXFAT_NUM_OF_DIR_ENTRIES != dir_entries_found)) + { + + /* Build the read sector command. */ + media_ptr -> fx_media_driver_logical_sector = media_ptr -> fx_media_root_sector_start + counter; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* Invoke the driver to read the directory entry sector. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Determine if the read was successful. */ + if (FX_SUCCESS != media_ptr -> fx_media_driver_status) + { + + /* Return the error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Move to next sector. */ + counter++; + + /* Setup directory entry pointer to the sector buffer. */ + dir_entry_ptr = sector_buffer; + + /* Go through the read buffer and try to find BitMap table and UpCase table dir entries. */ + while (dir_entry_ptr < (media_ptr -> fx_media_memory_buffer + + media_ptr -> fx_media_bytes_per_sector) && + (EXFAT_NUM_OF_DIR_ENTRIES != dir_entries_found)) + { + + /* Check if we found the bitmap table. */ + if (FX_EXFAT_DIR_ENTRY_TYPE_ALLOCATION_BITMAP == dir_entry_ptr[FX_EXFAT_ENTRY_TYPE]) + { + + /* Calculate BitMap table start sector. */ + bitmap_start_sector = media_ptr -> fx_media_data_sector_start + + ((_fx_utility_32_unsigned_read(&dir_entry_ptr[FX_EXFAT_FIRST_CLUSTER]) - + FX_FAT_ENTRY_START) << media_ptr -> fx_media_exfat_sector_per_clusters_shift); + + bitmap_size_in_bytes = (ULONG)_fx_utility_64_unsigned_read(&dir_entry_ptr[FX_EXFAT_DATA_LENGTH]); + + dir_entries_found++; + } + /* Check if we found the upcase table. */ + else if (FX_EXFAT_DIR_ENTRY_TYPE_UP_CASE_TABLE == dir_entry_ptr[FX_EXFAT_ENTRY_TYPE]) + { + + /* Calculate UpCase table start sector. */ + upcase_table_start_sector = media_ptr -> fx_media_data_sector_start + + ((_fx_utility_32_unsigned_read(&dir_entry_ptr[FX_EXFAT_FIRST_CLUSTER]) - + FX_FAT_ENTRY_START) << media_ptr -> fx_media_exfat_sector_per_clusters_shift); + + upcase_table_checksum = _fx_utility_32_unsigned_read(&dir_entry_ptr[FX_EXFAT_UP_CASE_TABLE_CHECK_SUM]); + upcase_table_size_in_bytes = (ULONG)_fx_utility_64_unsigned_read(&dir_entry_ptr[FX_EXFAT_DATA_LENGTH]); + + dir_entries_found++; + } + + /* Move to next directory entry. */ + dir_entry_ptr += FX_EXFAT_DIR_ENTRY_SIZE; + } + } + + /* Validate the directory entries. */ + if ((0 == bitmap_start_sector) || + (0 == bitmap_size_in_bytes) || + (0 == upcase_table_start_sector) || + (0 == upcase_table_checksum) || + (0 == upcase_table_size_in_bytes)) + { + + /* Directory entries have invalid value, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Check Bit Map size. */ + if (media_ptr -> fx_media_total_clusters > + /* 1 Byte = > map to 8 clusters. */ + (bitmap_size_in_bytes << BITS_PER_BYTE_SHIFT)) + { + + /* Bitmap size is not correct, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Check Up Case Table checksum. */ + calculated_checksum = 0; + + /* Build driver request to read the upcase table. */ + media_ptr -> fx_media_driver_logical_sector = upcase_table_start_sector; + + /* Loop to calculate upcase table checksum. */ + while (upcase_table_size_in_bytes > 0) + { + + /* Build driver request. */ + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* Invoke the driver to read one sector. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Determine if the read was successful. */ + if (FX_SUCCESS != media_ptr -> fx_media_driver_status) + { + + /* Return the error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Determine the processing size. */ + if (upcase_table_size_in_bytes >= media_ptr -> fx_media_bytes_per_sector) + { + + /* Process one sector at a time. */ + temp = media_ptr -> fx_media_bytes_per_sector; + upcase_table_size_in_bytes -= media_ptr -> fx_media_bytes_per_sector; + media_ptr -> fx_media_driver_logical_sector++; + } + else + { + + /* Remaining data is less than one sector, process all the remaining bytes. */ + temp = upcase_table_size_in_bytes; + upcase_table_size_in_bytes = 0; + } + + /* Calculate checksum. */ + for (counter = 0; counter < temp; counter++) + { + + /* Calculate the checksum using the algorithm specified in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + calculated_checksum = ((calculated_checksum >> 1) | (calculated_checksum << 31)) + (ULONG)sector_buffer[counter]; + } + } + + /* Verify the checksum. */ + if (calculated_checksum != upcase_table_checksum) + { + + /* Checksum not correct, return error. */ + return(FX_MEDIA_INVALID); + } + + /* Return success. */ + return(FX_SUCCESS); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c new file mode 100644 index 00000000..1e3cc6ae --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_name_hash_get.c @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_name_hash_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns hash of ASCII file name. */ +/* */ +/* INPUT */ +/* */ +/* name ASCII file name */ +/* */ +/* OUTPUT */ +/* */ +/* return name hash */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_exFAT_entry_write */ +/* _fx_directory_rename */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +USHORT _fx_utility_exFAT_name_hash_get(CHAR *name) +{ + +USHORT hash; + + + /* Initialize hash to 0. */ + hash = 0; + + /* Is there a name? */ + if (!name) + { + + /* No, just return 0. */ + return(0); + } + + /* Create hash for name. */ + while (*name) + { + + /* Compute hash. */ + hash = (USHORT)(((hash >> 1) | (hash << 15)) + _fx_utility_exFAT_upcase_get((USHORT)*name)); + hash = (USHORT)((hash >> 1) | (hash << 15)); + + /* Move to next character of name. */ + name++; + } + + /* Return the hash. */ + return(hash); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c new file mode 100644 index 00000000..5407d5fc --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_size_calculate.c @@ -0,0 +1,157 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_size_calculate PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function calculates FAT size according to given parameters. */ +/* */ +/* INPUT */ +/* */ +/* boundary_unit Data area alignment in sectors*/ +/* size_in_sectors Partition size in sectors */ +/* sectors_per_cluster Number of sectors per cluster */ +/* sectors_per_fat_ptr Pointer to sector per FAT */ +/* fat_offset_ptr Pointer to offset of FAT */ +/* cluster_heap_offset_ptr Pointer to offset of cluster */ +/* heap */ +/* */ +/* OUTPUT */ +/* */ +/* NONE */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_media_exFAT_format */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), fixed */ +/* FAT size calculation issue, */ +/* resulting in version 6.1.5 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), and */ +/* replaced sector size */ +/* constant, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _fx_utility_exFAT_size_calculate(UINT bytes_per_sector, ULONG boundary_unit, ULONG64 size_in_sectors, ULONG sectors_per_cluster, + ULONG *sectors_per_fat_ptr, ULONG *fat_offset_ptr, ULONG *cluster_heap_offset_ptr) +{ + +ULONG system_area_sectors = 0; /* Number of sectors for exFTA system area (from partition begining) */ +ULONG64 total_cluster_heap_sectors; + + + /* Align the boundary unit. If zero supplied, then set to default value. */ + boundary_unit = ALIGN_UP(boundary_unit, 128); + + /* Align System Area according Boundary Unit. */ + while (system_area_sectors < (EXFAT_BOOT_REGION_SIZE + EXFAT_MIN_NUM_OF_RESERVED_SECTORS)) + { + + system_area_sectors += boundary_unit; + } + + /* Save preliminary FAT offset. */ + *fat_offset_ptr = system_area_sectors; + + /* Save preliminary Clusters Heap offset. */ + *cluster_heap_offset_ptr = *fat_offset_ptr; + + /* Calculate number of available sectors without system sectors. */ + total_cluster_heap_sectors = size_in_sectors - system_area_sectors; + + /* Calculate required number of FAT sectors. */ + *sectors_per_fat_ptr = (ULONG)DIVIDE_TO_CEILING(((total_cluster_heap_sectors / sectors_per_cluster) * EXFAT_FAT_BITS), + (bytes_per_sector * BITS_PER_BYTE)); + + *sectors_per_fat_ptr = ALIGN_UP(*sectors_per_fat_ptr, boundary_unit >> 1); + + /* Check is it possible to allocate FAT inside calculated System Area sectors or not. */ + if (system_area_sectors > + (EXFAT_BOOT_REGION_SIZE + + EXFAT_MIN_NUM_OF_RESERVED_SECTORS + *sectors_per_fat_ptr)) + { + + /* We able allocate FAT inside calculated logical_system_area_sectors. */ + *fat_offset_ptr -= *sectors_per_fat_ptr; + } + else /* Recalculate FAT size since System Area will be increased on FAT size. */ + { + do + { + + /* Increase System Area size on number of FAT sectors aligned according BU. */ + system_area_sectors = *fat_offset_ptr + *sectors_per_fat_ptr; + + /* Decrease sectors available for clusters heap. */ + total_cluster_heap_sectors = size_in_sectors - system_area_sectors; + + /* Re-calculate number of sectors per FAT. */ + *sectors_per_fat_ptr = (ULONG)DIVIDE_TO_CEILING(((total_cluster_heap_sectors / sectors_per_cluster) * EXFAT_FAT_BITS), + (bytes_per_sector * BITS_PER_BYTE)); + + *sectors_per_fat_ptr = ALIGN_UP(*sectors_per_fat_ptr, boundary_unit >> 1); + + /* Increase Cluster Heap offset according new FAT size. */ + *cluster_heap_offset_ptr = *fat_offset_ptr + *sectors_per_fat_ptr; + + /* Loop until we find a FAT size that can hold all the clusters. */ + }while (*sectors_per_fat_ptr * bytes_per_sector * BITS_PER_BYTE / EXFAT_FAT_BITS < ((size_in_sectors - *cluster_heap_offset_ptr) / sectors_per_cluster)); + } +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c new file mode 100644 index 00000000..dc044acc --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_verify.c @@ -0,0 +1,216 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_system_area_checksum_verify PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks exFAT geometry. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* sector_buffer Pointer to sector buffer */ +/* boot_sector_offset Offset of boot sector */ +/* calculated_checksum Pointer to checksum value */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* Media driver */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), replaced */ +/* sector size constant, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_system_area_checksum_verify(FX_MEDIA *media_ptr, UCHAR *sector_buffer, + ULONG boot_sector_offset, ULONG *calculated_checksum) +{ + +ULONG temp; +ULONG counter; + + + /* Clear the checksum for checksum calculation. */ + *calculated_checksum = 0; + + /* Prepare driver request. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_buffer = sector_buffer; + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_logical_sector = boot_sector_offset; + + /* Call driver. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Check driver status. */ + if (FX_SUCCESS != media_ptr -> fx_media_driver_status) + { + + /* Error, return error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Loop to calculate Boot Sector checksum. */ + for (temp = 0; temp < media_ptr -> fx_media_bytes_per_sector; temp++) + { + + /* Check if it is VolumeFlags or PercentInUse. */ + if ((FX_EF_VOLUME_FLAGS == temp) || + (FX_EF_VOLUME_FLAGS + 1 == temp) || + (FX_EF_PERCENT_IN_USE == temp)) + { + + /* Skip these fields in checksum calculation. */ + continue; + } + + /* Calculate the checksum using the algorithm specified in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + *calculated_checksum = ((*calculated_checksum >> 1) | (*calculated_checksum << 31)) + (ULONG)sector_buffer[temp]; + } + + /* Map to Extended boot Sector. */ + media_ptr -> fx_media_driver_logical_sector++; + + /* Read System Area from Extended Boot Sector + and calculate checksum. */ + for (temp = FX_EXFAT_FAT_EXT_BOOT_SECTOR_OFFSET; FX_EXFAT_FAT_CHECK_SUM_OFFSET > temp; temp++) + { + + /* Build driver request. */ + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* Read next sector. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Check status. */ + if (FX_SUCCESS != media_ptr -> fx_media_driver_status) + { + + /* Clear checksum. */ + *calculated_checksum = 0; + + /* Error, return error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Move to next logical sector. */ + media_ptr -> fx_media_driver_logical_sector++; + + /* Check Sector Signature. */ + if (((sector_buffer[media_ptr -> fx_media_bytes_per_sector - 2] != FX_SIG_BYTE_1) || + (sector_buffer[media_ptr -> fx_media_bytes_per_sector - 1] != FX_SIG_BYTE_2)) && + (FX_EXFAT_FAT_OEM_PARAM_OFFSET > temp)) + { + + /* Clear checksum. */ + *calculated_checksum = 0; + + /* Error, return error status. */ + return(FX_MEDIA_INVALID); + } + + /* Loop to calculate the checksum. */ + for (counter = 0; counter < media_ptr -> fx_media_bytes_per_sector; counter++) + { + + /* Calculate the checksum using the algorithm specified in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + *calculated_checksum = ((*calculated_checksum >> 1) | (*calculated_checksum << 31)) + (ULONG)sector_buffer[counter]; + } + } + + /* Build driver request. */ + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* Read stored checksum. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Determine if the read was successful. */ + if (FX_SUCCESS != media_ptr -> fx_media_driver_status) + { + + /* Not successful, return error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Loop to check sector content. */ + for (counter = 0; counter < media_ptr -> fx_media_bytes_per_sector; counter += sizeof(ULONG)) + { + + /* Read a 32 bit value from sector buffer. */ + temp = _fx_utility_32_unsigned_read(§or_buffer[counter]); + + /* Compare the read value with the caclulated checksum. */ + if (temp != *calculated_checksum) + { + + /* Not equal, checksum verify failed. */ + return(FX_MEDIA_INVALID); + } + } + + /* Return success. */ + return(FX_SUCCESS); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c new file mode 100644 index 00000000..52b1f237 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_checksum_write.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_system.h" +#include "fx_media.h" +#include "fx_utility.h" +#include "fx_directory_exFAT.h" + + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_system_area_checksum_write PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes system area checksum. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* sector_buffer Pointer to sector buffer */ +/* system_area_checksum_ptr Pointer to checksum value */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_exFAT_system_sector_write Write a format sector */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), replaced */ +/* sector size constant, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_system_area_checksum_write(FX_MEDIA *media_ptr, UCHAR *sector_buffer, ULONG *system_area_checksum_ptr) +{ + +UINT index; + + /* Fill buffer by check sum. */ + for (index = 0; index < media_ptr -> fx_media_bytes_per_sector;) + { + _fx_utility_32_unsigned_write(§or_buffer[index], + *system_area_checksum_ptr); + + index += sizeof(*system_area_checksum_ptr); + } + + /* Write Check Sum for Main System area. */ + _fx_utility_exFAT_system_sector_write(media_ptr, sector_buffer, + FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE - 1, + 1, FX_BOOT_SECTOR); + + if (FX_SUCCESS != media_ptr -> fx_media_driver_status) + { + return(media_ptr -> fx_media_driver_status); + } + + /* Write Check Sum for BackUp System area. */ + _fx_utility_exFAT_system_sector_write(media_ptr, sector_buffer, + FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE - 1 + FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE, + 1, FX_BOOT_SECTOR); + + return(media_ptr -> fx_media_driver_status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c new file mode 100644 index 00000000..32b2082b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_area_format.c @@ -0,0 +1,237 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_system_area_format PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function formats system area for exFAT. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media control block*/ +/* boundary_unit Data area alignment in sectors*/ +/* system_area_checksum_ptr Pointer system area checksum */ +/* memory_ptr Pointer to work buffer */ +/* memory_size Size of the work buffer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_memory_set Set memory */ +/* _fx_utility_exFAT_system_sector_write Write exFAT format sector */ +/* _fx_utility_32_unsigned_write Write 32-bit word */ +/* _fx_utility_16_unsigned_write Write 16-bit word */ +/* */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_media_exFAT_format */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Bhupendra Naphade Modified comment(s), replaced */ +/* sector size constant, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_system_area_format(FX_MEDIA *media_ptr, ULONG boundary_unit, + ULONG *system_area_checksum_ptr, + UCHAR *memory_ptr, UINT memory_size) +{ + +UINT counter; +UINT i; +UINT sector_offset = 0; +UINT status; +UCHAR *system_area_buffer = NULL; + + + /* Is the memory size large enough? */ + if (memory_size < media_ptr -> fx_media_bytes_per_sector) + { + + /* No, return an error. */ + return(FX_PTR_ERROR); + } + + /* Setup pointer to system area buffer. */ + system_area_buffer = memory_ptr; + + /* Align the boundary unit. */ + boundary_unit = ALIGN_UP(boundary_unit, 128); + + /* Clear work buffer. */ + _fx_utility_memory_set(system_area_buffer, 0x00, media_ptr -> fx_media_bytes_per_sector); + + /* Add signature to System area sectors without boot, OEM, reserved and checksum sector. */ + system_area_buffer[media_ptr -> fx_media_bytes_per_sector - 2] = FX_SIG_BYTE_1; + system_area_buffer[media_ptr -> fx_media_bytes_per_sector - 1] = FX_SIG_BYTE_2; + + /* Loop to write all the extended boot sectors. */ + for (counter = 0; counter < (FX_EXFAT_FAT_OEM_PARAM_OFFSET - FX_EXFAT_FAT_EXT_BOOT_SECTOR_OFFSET); counter++) + { + + /* Loop to calculate the checksum for System Area */ + for (i = 0; i < media_ptr -> fx_media_bytes_per_sector; i++) + { + + /* Calculate the checksum using the algorithm specified in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + *system_area_checksum_ptr = ((*system_area_checksum_ptr >> 1) | (*system_area_checksum_ptr << 31)) + + (ULONG)system_area_buffer[i]; + } + + /* Write out the extended boot sector. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, system_area_buffer, + (ULONG64) (FX_EXFAT_FAT_EXT_BOOT_SECTOR_OFFSET + counter), + ((ULONG) 1), FX_BOOT_SECTOR); + + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Write out the extended boot sector in the backup region. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, system_area_buffer, + (ULONG64) (FX_EXFAT_FAT_EXT_BOOT_SECTOR_OFFSET + counter + FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE), + ((ULONG) 1), FX_BOOT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + return(status); + } + } + + /* Add OEM - Flash parameters. */ + system_area_buffer[media_ptr -> fx_media_bytes_per_sector - 2] = 0; + system_area_buffer[media_ptr -> fx_media_bytes_per_sector - 1] = 0; + + /* GUID 0A0C7E46-3399-4021-90C8-FA6D389C4BA2 */ + _fx_utility_32_unsigned_write(&(system_area_buffer[sector_offset]), 0x0A0C7E46); + _fx_utility_16_unsigned_write(&(system_area_buffer[sector_offset + 4]), 0x3399); + _fx_utility_16_unsigned_write(&(system_area_buffer[sector_offset + 6]), 0x4021); + system_area_buffer[sector_offset + 8] = 0x90; system_area_buffer[sector_offset + 9] = 0xC8; + system_area_buffer[sector_offset + 10] = 0xFA; system_area_buffer[sector_offset + 11] = 0x6D; + system_area_buffer[sector_offset + 12] = 0x38; system_area_buffer[sector_offset + 13] = 0x9C; + system_area_buffer[sector_offset + 14] = 0x4B; system_area_buffer[sector_offset + 15] = 0xA2; + + /* Add EraseBlockSize. */ + _fx_utility_32_unsigned_write(&(system_area_buffer[sector_offset + 16]), boundary_unit / 2); + + /* Write out the OEM parameters sector. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, system_area_buffer, + FX_EXFAT_FAT_OEM_PARAM_OFFSET, + 1, FX_BOOT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Write out the OEM parameters sector in the backup region. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, system_area_buffer, + FX_EXFAT_FAT_OEM_PARAM_OFFSET + FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE, + 1, FX_BOOT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Loop to calculate checksum for System Area. */ + for (counter = 0; counter < media_ptr -> fx_media_bytes_per_sector; counter++) + { + + /* Calculate the checksum using the algorithm specified in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + *system_area_checksum_ptr = ((*system_area_checksum_ptr >> 1) | (*system_area_checksum_ptr << 31)) + + (ULONG)system_area_buffer[counter]; + } + + /* Clear work buffer. */ + _fx_utility_memory_set(system_area_buffer, 0x00, media_ptr -> fx_media_bytes_per_sector); + + /* Loop to calculate checksum for System Area. */ + for (counter = 0; counter < media_ptr -> fx_media_bytes_per_sector; counter++) + { + + /* Calculate the checksum using the algorithm specified in the specification. */ + /* Right rotate the checksum by one bit position and add the data. */ + *system_area_checksum_ptr = ((*system_area_checksum_ptr >> 1) | (*system_area_checksum_ptr << 31)) + + (ULONG)system_area_buffer[counter]; + } + + /* Write out the boot checksum sector. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, system_area_buffer, + FX_EXFAT_FAT_OEM_PARAM_OFFSET + 1, + 1, FX_BOOT_SECTOR); + + /* Determine if the write was successful. */ + if (status != FX_SUCCESS) + { + return(status); + } + + /* Write out the boot checksum sector in the backup region. */ + status = _fx_utility_exFAT_system_sector_write(media_ptr, system_area_buffer, + FX_EXFAT_FAT_OEM_PARAM_OFFSET + 1 + FX_EXFAT_FAT_MAIN_SYSTEM_AREA_SIZE, + 1, FX_BOOT_SECTOR); + + /* Return completion status. */ + return(status); +} + +#endif + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c new file mode 100644 index 00000000..99846118 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_system_sector_write.c @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + +#include "fx_api.h" +#include "fx_utility.h" + + +#ifdef FX_ENABLE_EXFAT +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_system_sector_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes a sector for exFAT format. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media control block*/ +/* data_buffer Pointer to sector data buffer */ +/* logical_sector Sector number to write */ +/* sector_count Number of sectors to write */ +/* sector_type Sector type of the sector to */ +/* be written */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* Media driver */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_media_exFAT_format */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_exFAT_system_sector_write(FX_MEDIA *media_ptr, UCHAR *data_buffer, + ULONG64 logical_sector, ULONG sector_count, + ULONG sector_type) +{ + + + /* Build sector write command. */ +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = logical_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector; +#endif + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_sectors = sector_count; + media_ptr -> fx_media_driver_system_write = FX_TRUE; + media_ptr -> fx_media_driver_sector_type = sector_type; + media_ptr -> fx_media_driver_buffer = data_buffer; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, media_ptr -> fx_media_driver_logical_sector, 1, sector_type, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Write out the sector. */ + (media_ptr -> fx_media_driver_entry)(media_ptr); + + /* Return status. */ + return(media_ptr -> fx_media_driver_status); +} + +#endif + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c new file mode 100644 index 00000000..9b6aef97 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_unicode_name_hash_get.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_unicode_name_hash_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns hash of Unicode file name. */ +/* */ +/* INPUT */ +/* */ +/* unicode_name Unicode file name */ +/* unicode_length Unicode name length */ +/* */ +/* OUTPUT */ +/* */ +/* return name hash */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_exFAT_entry_write */ +/* _fx_directory_rename */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +USHORT _fx_utility_exFAT_unicode_name_hash_get(CHAR *unicode_name, ULONG unicode_length) +{ + +USHORT hash; +USHORT upcased_char; + + /* Initialize hash to 0. */ + hash = 0; + + /* Is there a name? */ + if (!unicode_name) + { + + /* No, just return 0. */ + return(0); + } + + /* Create hash for name. */ + while (unicode_length) + { + + /* Get up-cased character. */ + upcased_char = (USHORT)(_fx_utility_exFAT_upcase_get((USHORT)(*unicode_name | (*(unicode_name + 1) << 8)))); + + /* Compute hash. */ + hash = (USHORT)(((hash >> 1) | (hash << 15)) + (upcased_char & 0xFF)); + hash = (USHORT)(((hash >> 1) | (hash << 15)) + (upcased_char >> 8)); + + /* Move to next character of the Unicode name. */ + unicode_name = unicode_name + 2; + + /* Decrement length. */ + unicode_length--; + } + + /* Return the hash. */ + return(hash); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c new file mode 100644 index 00000000..6e71e33c --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_exFAT_upcase_table.c @@ -0,0 +1,261 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_utility.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_directory_exFAT.h" + + +/* Define upcase table used by exFAT. */ +static const USHORT _fx_utility_exFAT_upcase_table_differential[] = +{ + + /* 0x0060 - 0x007f, offset 0 */ + 0x0060, 0x0041, 0x0042, 0x0043, 0x0044, 0x0045, 0x0046, 0x0047, 0x0048, 0x0049, 0x004a, 0x004b, 0x004c, 0x004d, 0x004e, 0x004f, + 0x0050, 0x0051, 0x0052, 0x0053, 0x0054, 0x0055, 0x0056, 0x0057, 0x0058, 0x0059, 0x005a, 0x007b, 0x007c, 0x007d, 0x007e, 0x007f, + + /* 0x00e0 - 0x029f, offset 32 */ + 0x00c0, 0x00c1, 0x00c2, 0x00c3, 0x00c4, 0x00c5, 0x00c6, 0x00c7, 0x00c8, 0x00c9, 0x00ca, 0x00cb, 0x00cc, 0x00cd, 0x00ce, 0x00cf, + 0x00d0, 0x00d1, 0x00d2, 0x00d3, 0x00d4, 0x00d5, 0x00d6, 0x00f7, 0x00d8, 0x00d9, 0x00da, 0x00db, 0x00dc, 0x00dd, 0x00de, 0x0178, + 0x0100, 0x0100, 0x0102, 0x0102, 0x0104, 0x0104, 0x0106, 0x0106, 0x0108, 0x0108, 0x010a, 0x010a, 0x010c, 0x010c, 0x010e, 0x010e, + 0x0110, 0x0110, 0x0112, 0x0112, 0x0114, 0x0114, 0x0116, 0x0116, 0x0118, 0x0118, 0x011a, 0x011a, 0x011c, 0x011c, 0x011e, 0x011e, + 0x0120, 0x0120, 0x0122, 0x0122, 0x0124, 0x0124, 0x0126, 0x0126, 0x0128, 0x0128, 0x012a, 0x012a, 0x012c, 0x012c, 0x012e, 0x012e, + 0x0130, 0x0131, 0x0132, 0x0132, 0x0134, 0x0134, 0x0136, 0x0136, 0x0138, 0x0139, 0x0139, 0x013b, 0x013b, 0x013d, 0x013d, 0x013f, + 0x013f, 0x0141, 0x0141, 0x0143, 0x0143, 0x0145, 0x0145, 0x0147, 0x0147, 0x0149, 0x014a, 0x014a, 0x014c, 0x014c, 0x014e, 0x014e, + 0x0150, 0x0150, 0x0152, 0x0152, 0x0154, 0x0154, 0x0156, 0x0156, 0x0158, 0x0158, 0x015a, 0x015a, 0x015c, 0x015c, 0x015e, 0x015e, + 0x0160, 0x0160, 0x0162, 0x0162, 0x0164, 0x0164, 0x0166, 0x0166, 0x0168, 0x0168, 0x016a, 0x016a, 0x016c, 0x016c, 0x016e, 0x016e, + 0x0170, 0x0170, 0x0172, 0x0172, 0x0174, 0x0174, 0x0176, 0x0176, 0x0178, 0x0179, 0x0179, 0x017b, 0x017b, 0x017d, 0x017d, 0x017f, + 0x0243, 0x0181, 0x0182, 0x0182, 0x0184, 0x0184, 0x0186, 0x0187, 0x0187, 0x0189, 0x018a, 0x018b, 0x018b, 0x018d, 0x018e, 0x018f, + 0x0190, 0x0191, 0x0191, 0x0193, 0x0194, 0x01f6, 0x0196, 0x0197, 0x0198, 0x0198, 0x023d, 0x019b, 0x019c, 0x019d, 0x0220, 0x019f, + 0x01a0, 0x01a0, 0x01a2, 0x01a2, 0x01a4, 0x01a4, 0x01a6, 0x01a7, 0x01a7, 0x01a9, 0x01aa, 0x01ab, 0x01ac, 0x01ac, 0x01ae, 0x01af, + 0x01af, 0x01b1, 0x01b2, 0x01b3, 0x01b3, 0x01b5, 0x01b5, 0x01b7, 0x01b8, 0x01b8, 0x01ba, 0x01bb, 0x01bc, 0x01bc, 0x01be, 0x01f7, + 0x01c0, 0x01c1, 0x01c2, 0x01c3, 0x01c4, 0x01c5, 0x01c4, 0x01c7, 0x01c8, 0x01c7, 0x01ca, 0x01cb, 0x01ca, 0x01cd, 0x01cd, 0x01cf, + 0x01cf, 0x01d1, 0x01d1, 0x01d3, 0x01d3, 0x01d5, 0x01d5, 0x01d7, 0x01d7, 0x01d9, 0x01d9, 0x01db, 0x01db, 0x018e, 0x01de, 0x01de, + 0x01e0, 0x01e0, 0x01e2, 0x01e2, 0x01e4, 0x01e4, 0x01e6, 0x01e6, 0x01e8, 0x01e8, 0x01ea, 0x01ea, 0x01ec, 0x01ec, 0x01ee, 0x01ee, + 0x01f0, 0x01f1, 0x01f2, 0x01f1, 0x01f4, 0x01f4, 0x01f6, 0x01f7, 0x01f8, 0x01f8, 0x01fa, 0x01fa, 0x01fc, 0x01fc, 0x01fe, 0x01fe, + 0x0200, 0x0200, 0x0202, 0x0202, 0x0204, 0x0204, 0x0206, 0x0206, 0x0208, 0x0208, 0x020a, 0x020a, 0x020c, 0x020c, 0x020e, 0x020e, + 0x0210, 0x0210, 0x0212, 0x0212, 0x0214, 0x0214, 0x0216, 0x0216, 0x0218, 0x0218, 0x021a, 0x021a, 0x021c, 0x021c, 0x021e, 0x021e, + 0x0220, 0x0221, 0x0222, 0x0222, 0x0224, 0x0224, 0x0226, 0x0226, 0x0228, 0x0228, 0x022a, 0x022a, 0x022c, 0x022c, 0x022e, 0x022e, + 0x0230, 0x0230, 0x0232, 0x0232, 0x0234, 0x0235, 0x0236, 0x0237, 0x0238, 0x0239, 0x2c65, 0x023b, 0x023b, 0x023d, 0x2c66, 0x023f, + 0x0240, 0x0241, 0x0241, 0x0243, 0x0244, 0x0245, 0x0246, 0x0246, 0x0248, 0x0248, 0x024a, 0x024a, 0x024c, 0x024c, 0x024e, 0x024e, + 0x0250, 0x0251, 0x0252, 0x0181, 0x0186, 0x0255, 0x0189, 0x018a, 0x0258, 0x018f, 0x025a, 0x0190, 0x025c, 0x025d, 0x025e, 0x025f, + 0x0193, 0x0261, 0x0262, 0x0194, 0x0264, 0x0265, 0x0266, 0x0267, 0x0197, 0x0196, 0x026a, 0x2c62, 0x026c, 0x026d, 0x026e, 0x019c, + 0x0270, 0x0271, 0x019d, 0x0273, 0x0274, 0x019f, 0x0276, 0x0277, 0x0278, 0x0279, 0x027a, 0x027b, 0x027c, 0x2c64, 0x027e, 0x027f, + 0x01a6, 0x0281, 0x0282, 0x01a9, 0x0284, 0x0285, 0x0286, 0x0287, 0x01ae, 0x0244, 0x01b1, 0x01b2, 0x0245, 0x028d, 0x028e, 0x028f, + 0x0290, 0x0291, 0x01b7, 0x0293, 0x0294, 0x0295, 0x0296, 0x0297, 0x0298, 0x0299, 0x029a, 0x029b, 0x029c, 0x029d, 0x029e, 0x029f, + + /* 0x0370 - 0x037f, offset 480 */ + 0x0370, 0x0371, 0x0372, 0x0373, 0x0374, 0x0375, 0x0376, 0x0377, 0x0378, 0x0379, 0x037a, 0x03fd, 0x03fe, 0x03ff, 0x037e, 0x037f, + + /* 0x03a0 - 0x03ff, offset 496 */ + 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a6, 0x03a7, 0x03a8, 0x03a9, 0x03aa, 0x03ab, 0x0386, 0x0388, 0x0389, 0x038a, + 0x03b0, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 0x039e, 0x039f, + 0x03a0, 0x03a1, 0x03a3, 0x03a3, 0x03a4, 0x03a5, 0x03a6, 0x03a7, 0x03a8, 0x03a9, 0x03aa, 0x03ab, 0x038c, 0x038e, 0x038f, 0x03cf, + 0x03d0, 0x03d1, 0x03d2, 0x03d3, 0x03d4, 0x03d5, 0x03d6, 0x03d7, 0x03d8, 0x03d8, 0x03da, 0x03da, 0x03dc, 0x03dc, 0x03de, 0x03de, + 0x03e0, 0x03e0, 0x03e2, 0x03e2, 0x03e4, 0x03e4, 0x03e6, 0x03e6, 0x03e8, 0x03e8, 0x03ea, 0x03ea, 0x03ec, 0x03ec, 0x03ee, 0x03ee, + 0x03f0, 0x03f1, 0x03f9, 0x03f3, 0x03f4, 0x03f5, 0x03f6, 0x03f7, 0x03f7, 0x03f9, 0x03fa, 0x03fa, 0x03fc, 0x03fd, 0x03fe, 0x03ff, + + /* 0x0430 - 0x051f, offset 592 */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, 0x0418, 0x0419, 0x041a, 0x041b, 0x041c, 0x041d, 0x041e, 0x041f, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, 0x0428, 0x0429, 0x042a, 0x042b, 0x042c, 0x042d, 0x042e, 0x042f, + 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0406, 0x0407, 0x0408, 0x0409, 0x040a, 0x040b, 0x040c, 0x040d, 0x040e, 0x040f, + 0x0460, 0x0460, 0x0462, 0x0462, 0x0464, 0x0464, 0x0466, 0x0466, 0x0468, 0x0468, 0x046a, 0x046a, 0x046c, 0x046c, 0x046e, 0x046e, + 0x0470, 0x0470, 0x0472, 0x0472, 0x0474, 0x0474, 0x0476, 0x0476, 0x0478, 0x0478, 0x047a, 0x047a, 0x047c, 0x047c, 0x047e, 0x047e, + 0x0480, 0x0480, 0x0482, 0x0483, 0x0484, 0x0485, 0x0486, 0x0487, 0x0488, 0x0489, 0x048a, 0x048a, 0x048c, 0x048c, 0x048e, 0x048e, + 0x0490, 0x0490, 0x0492, 0x0492, 0x0494, 0x0494, 0x0496, 0x0496, 0x0498, 0x0498, 0x049a, 0x049a, 0x049c, 0x049c, 0x049e, 0x049e, + 0x04a0, 0x04a0, 0x04a2, 0x04a2, 0x04a4, 0x04a4, 0x04a6, 0x04a6, 0x04a8, 0x04a8, 0x04aa, 0x04aa, 0x04ac, 0x04ac, 0x04ae, 0x04ae, + 0x04b0, 0x04b0, 0x04b2, 0x04b2, 0x04b4, 0x04b4, 0x04b6, 0x04b6, 0x04b8, 0x04b8, 0x04ba, 0x04ba, 0x04bc, 0x04bc, 0x04be, 0x04be, + 0x04c0, 0x04c1, 0x04c1, 0x04c3, 0x04c3, 0x04c5, 0x04c5, 0x04c7, 0x04c7, 0x04c9, 0x04c9, 0x04cb, 0x04cb, 0x04cd, 0x04cd, 0x04c0, + 0x04d0, 0x04d0, 0x04d2, 0x04d2, 0x04d4, 0x04d4, 0x04d6, 0x04d6, 0x04d8, 0x04d8, 0x04da, 0x04da, 0x04dc, 0x04dc, 0x04de, 0x04de, + 0x04e0, 0x04e0, 0x04e2, 0x04e2, 0x04e4, 0x04e4, 0x04e6, 0x04e6, 0x04e8, 0x04e8, 0x04ea, 0x04ea, 0x04ec, 0x04ec, 0x04ee, 0x04ee, + 0x04f0, 0x04f0, 0x04f2, 0x04f2, 0x04f4, 0x04f4, 0x04f6, 0x04f6, 0x04f8, 0x04f8, 0x04fa, 0x04fa, 0x04fc, 0x04fc, 0x04fe, 0x04fe, + 0x0500, 0x0500, 0x0502, 0x0502, 0x0504, 0x0504, 0x0506, 0x0506, 0x0508, 0x0508, 0x050a, 0x050a, 0x050c, 0x050c, 0x050e, 0x050e, + 0x0510, 0x0510, 0x0512, 0x0512, 0x0514, 0x0515, 0x0516, 0x0517, 0x0518, 0x0519, 0x051a, 0x051b, 0x051c, 0x051d, 0x051e, 0x051f, + + + /* 0x0560 - 0x058f, offset 832 */ + 0x0560, 0x0531, 0x0532, 0x0533, 0x0534, 0x0535, 0x0536, 0x0537, 0x0538, 0x0539, 0x053a, 0x053b, 0x053c, 0x053d, 0x053e, 0x053f, + 0x0540, 0x0541, 0x0542, 0x0543, 0x0544, 0x0545, 0x0546, 0x0547, 0x0548, 0x0549, 0x054a, 0x054b, 0x054c, 0x054d, 0x054e, 0x054f, + 0x0550, 0x0551, 0x0552, 0x0553, 0x0554, 0x0555, 0x0556, 0x0587, 0x0588, 0x0589, 0x058a, 0x058b, 0x058c, 0x058d, 0x058e, 0x058f, + + /* 0x1d70 - 0x1d7f, offset 880 */ + 0x1d70, 0x1d71, 0x1d72, 0x1d73, 0x1d74, 0x1d75, 0x1d76, 0x1d77, 0x1d78, 0x1d79, 0x1d7a, 0x1d7b, 0x1d7c, 0x2c63, 0x1d7e, 0x1d7f, + + /* 0x1e00 - 0x1fff, offset 896 */ + 0x1e00, 0x1e00, 0x1e02, 0x1e02, 0x1e04, 0x1e04, 0x1e06, 0x1e06, 0x1e08, 0x1e08, 0x1e0a, 0x1e0a, 0x1e0c, 0x1e0c, 0x1e0e, 0x1e0e, + 0x1e10, 0x1e10, 0x1e12, 0x1e12, 0x1e14, 0x1e14, 0x1e16, 0x1e16, 0x1e18, 0x1e18, 0x1e1a, 0x1e1a, 0x1e1c, 0x1e1c, 0x1e1e, 0x1e1e, + 0x1e20, 0x1e20, 0x1e22, 0x1e22, 0x1e24, 0x1e24, 0x1e26, 0x1e26, 0x1e28, 0x1e28, 0x1e2a, 0x1e2a, 0x1e2c, 0x1e2c, 0x1e2e, 0x1e2e, + 0x1e30, 0x1e30, 0x1e32, 0x1e32, 0x1e34, 0x1e34, 0x1e36, 0x1e36, 0x1e38, 0x1e38, 0x1e3a, 0x1e3a, 0x1e3c, 0x1e3c, 0x1e3e, 0x1e3e, + 0x1e40, 0x1e40, 0x1e42, 0x1e42, 0x1e44, 0x1e44, 0x1e46, 0x1e46, 0x1e48, 0x1e48, 0x1e4a, 0x1e4a, 0x1e4c, 0x1e4c, 0x1e4e, 0x1e4e, + 0x1e50, 0x1e50, 0x1e52, 0x1e52, 0x1e54, 0x1e54, 0x1e56, 0x1e56, 0x1e58, 0x1e58, 0x1e5a, 0x1e5a, 0x1e5c, 0x1e5c, 0x1e5e, 0x1e5e, + 0x1e60, 0x1e60, 0x1e62, 0x1e62, 0x1e64, 0x1e64, 0x1e66, 0x1e66, 0x1e68, 0x1e68, 0x1e6a, 0x1e6a, 0x1e6c, 0x1e6c, 0x1e6e, 0x1e6e, + 0x1e70, 0x1e70, 0x1e72, 0x1e72, 0x1e74, 0x1e74, 0x1e76, 0x1e76, 0x1e78, 0x1e78, 0x1e7a, 0x1e7a, 0x1e7c, 0x1e7c, 0x1e7e, 0x1e7e, + 0x1e80, 0x1e80, 0x1e82, 0x1e82, 0x1e84, 0x1e84, 0x1e86, 0x1e86, 0x1e88, 0x1e88, 0x1e8a, 0x1e8a, 0x1e8c, 0x1e8c, 0x1e8e, 0x1e8e, + 0x1e90, 0x1e90, 0x1e92, 0x1e92, 0x1e94, 0x1e94, 0x1e96, 0x1e97, 0x1e98, 0x1e99, 0x1e9a, 0x1e9b, 0x1e9c, 0x1e9d, 0x1e9e, 0x1e9f, + 0x1ea0, 0x1ea0, 0x1ea2, 0x1ea2, 0x1ea4, 0x1ea4, 0x1ea6, 0x1ea6, 0x1ea8, 0x1ea8, 0x1eaa, 0x1eaa, 0x1eac, 0x1eac, 0x1eae, 0x1eae, + 0x1eb0, 0x1eb0, 0x1eb2, 0x1eb2, 0x1eb4, 0x1eb4, 0x1eb6, 0x1eb6, 0x1eb8, 0x1eb8, 0x1eba, 0x1eba, 0x1ebc, 0x1ebc, 0x1ebe, 0x1ebe, + 0x1ec0, 0x1ec0, 0x1ec2, 0x1ec2, 0x1ec4, 0x1ec4, 0x1ec6, 0x1ec6, 0x1ec8, 0x1ec8, 0x1eca, 0x1eca, 0x1ecc, 0x1ecc, 0x1ece, 0x1ece, + 0x1ed0, 0x1ed0, 0x1ed2, 0x1ed2, 0x1ed4, 0x1ed4, 0x1ed6, 0x1ed6, 0x1ed8, 0x1ed8, 0x1eda, 0x1eda, 0x1edc, 0x1edc, 0x1ede, 0x1ede, + 0x1ee0, 0x1ee0, 0x1ee2, 0x1ee2, 0x1ee4, 0x1ee4, 0x1ee6, 0x1ee6, 0x1ee8, 0x1ee8, 0x1eea, 0x1eea, 0x1eec, 0x1eec, 0x1eee, 0x1eee, + 0x1ef0, 0x1ef0, 0x1ef2, 0x1ef2, 0x1ef4, 0x1ef4, 0x1ef6, 0x1ef6, 0x1ef8, 0x1ef8, 0x1efa, 0x1efb, 0x1efc, 0x1efd, 0x1efe, 0x1eff, + 0x1f08, 0x1f09, 0x1f0a, 0x1f0b, 0x1f0c, 0x1f0d, 0x1f0e, 0x1f0f, 0x1f08, 0x1f09, 0x1f0a, 0x1f0b, 0x1f0c, 0x1f0d, 0x1f0e, 0x1f0f, + 0x1f18, 0x1f19, 0x1f1a, 0x1f1b, 0x1f1c, 0x1f1d, 0x1f16, 0x1f17, 0x1f18, 0x1f19, 0x1f1a, 0x1f1b, 0x1f1c, 0x1f1d, 0x1f1e, 0x1f1f, + 0x1f28, 0x1f29, 0x1f2a, 0x1f2b, 0x1f2c, 0x1f2d, 0x1f2e, 0x1f2f, 0x1f28, 0x1f29, 0x1f2a, 0x1f2b, 0x1f2c, 0x1f2d, 0x1f2e, 0x1f2f, + 0x1f38, 0x1f39, 0x1f3a, 0x1f3b, 0x1f3c, 0x1f3d, 0x1f3e, 0x1f3f, 0x1f38, 0x1f39, 0x1f3a, 0x1f3b, 0x1f3c, 0x1f3d, 0x1f3e, 0x1f3f, + 0x1f48, 0x1f49, 0x1f4a, 0x1f4b, 0x1f4c, 0x1f4d, 0x1f46, 0x1f47, 0x1f48, 0x1f49, 0x1f4a, 0x1f4b, 0x1f4c, 0x1f4d, 0x1f4e, 0x1f4f, + 0x1f50, 0x1f59, 0x1f52, 0x1f5b, 0x1f54, 0x1f5d, 0x1f56, 0x1f5f, 0x1f58, 0x1f59, 0x1f5a, 0x1f5b, 0x1f5c, 0x1f5d, 0x1f5e, 0x1f5f, + 0x1f68, 0x1f69, 0x1f6a, 0x1f6b, 0x1f6c, 0x1f6d, 0x1f6e, 0x1f6f, 0x1f68, 0x1f69, 0x1f6a, 0x1f6b, 0x1f6c, 0x1f6d, 0x1f6e, 0x1f6f, + 0x1fba, 0x1fbb, 0x1fc8, 0x1fc9, 0x1fca, 0x1fcb, 0x1fda, 0x1fdb, 0x1ff8, 0x1ff9, 0x1fea, 0x1feb, 0x1ffa, 0x1ffb, 0x1f7e, 0x1f7f, + 0x1f88, 0x1f89, 0x1f8a, 0x1f8b, 0x1f8c, 0x1f8d, 0x1f8e, 0x1f8f, 0x1f88, 0x1f89, 0x1f8a, 0x1f8b, 0x1f8c, 0x1f8d, 0x1f8e, 0x1f8f, + 0x1f98, 0x1f99, 0x1f9a, 0x1f9b, 0x1f9c, 0x1f9d, 0x1f9e, 0x1f9f, 0x1f98, 0x1f99, 0x1f9a, 0x1f9b, 0x1f9c, 0x1f9d, 0x1f9e, 0x1f9f, + 0x1fa8, 0x1fa9, 0x1faa, 0x1fab, 0x1fac, 0x1fad, 0x1fae, 0x1faf, 0x1fa8, 0x1fa9, 0x1faa, 0x1fab, 0x1fac, 0x1fad, 0x1fae, 0x1faf, + 0x1fb8, 0x1fb9, 0x1fb2, 0x1fbc, 0x1fb4, 0x1fb5, 0x1fb6, 0x1fb7, 0x1fb8, 0x1fb9, 0x1fba, 0x1fbb, 0x1fbc, 0x1fbd, 0x1fbe, 0x1fbf, + 0x1fc0, 0x1fc1, 0x1fc2, 0x1fc3, 0x1fc4, 0x1fc5, 0x1fc6, 0x1fc7, 0x1fc8, 0x1fc9, 0x1fca, 0x1fcb, 0x1fc3, 0x1fcd, 0x1fce, 0x1fcf, + 0x1fd8, 0x1fd9, 0x1fd2, 0x1fd3, 0x1fd4, 0x1fd5, 0x1fd6, 0x1fd7, 0x1fd8, 0x1fd9, 0x1fda, 0x1fdb, 0x1fdc, 0x1fdd, 0x1fde, 0x1fdf, + 0x1fe8, 0x1fe9, 0x1fe2, 0x1fe3, 0x1fe4, 0x1fec, 0x1fe6, 0x1fe7, 0x1fe8, 0x1fe9, 0x1fea, 0x1feb, 0x1fec, 0x1fed, 0x1fee, 0x1fef, + 0x1ff0, 0x1ff1, 0x1ff2, 0x1ff3, 0x1ff4, 0x1ff5, 0x1ff6, 0x1ff7, 0x1ff8, 0x1ff9, 0x1ffa, 0x1ffb, 0x1ff3, 0x1ffd, 0x1ffe, 0x1fff, + + /* 0x2140 - 0x214f, offset 1408 */ + 0x2140, 0x2141, 0x2142, 0x2143, 0x2144, 0x2145, 0x2146, 0x2147, 0x2148, 0x2149, 0x214a, 0x214b, 0x214c, 0x214d, 0x2132, 0x214f, + + /* 0x2170 - 0x218f, offset 1424 */ + 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216a, 0x216b, 0x216c, 0x216d, 0x216e, 0x216f, + 0x2180, 0x2181, 0x2182, 0x2183, 0x2183, 0x2185, 0x2186, 0x2187, 0x2188, 0x2189, 0x218a, 0x218b, 0x218c, 0x218d, 0x218e, 0x218f, + + /* 0x24d0 - 0x24ef, offset 1456 */ + 0x24b6, 0x24b7, 0x24b8, 0x24b9, 0x24ba, 0x24bb, 0x24bc, 0x24bd, 0x24be, 0x24bf, 0x24c0, 0x24c1, 0x24c2, 0x24c3, 0x24c4, 0x24c5, + 0x24c6, 0x24c7, 0x24c8, 0x24c9, 0x24ca, 0x24cb, 0x24cc, 0x24cd, 0x24ce, 0x24cf, 0x24ea, 0x24eb, 0x24ec, 0x24ed, 0x24ee, 0x24ef, + + /* 0x2c30 - 0x2d2f, offset 1488 */ + 0x2c00, 0x2c01, 0x2c02, 0x2c03, 0x2c04, 0x2c05, 0x2c06, 0x2c07, 0x2c08, 0x2c09, 0x2c0a, 0x2c0b, 0x2c0c, 0x2c0d, 0x2c0e, 0x2c0f, + 0x2c10, 0x2c11, 0x2c12, 0x2c13, 0x2c14, 0x2c15, 0x2c16, 0x2c17, 0x2c18, 0x2c19, 0x2c1a, 0x2c1b, 0x2c1c, 0x2c1d, 0x2c1e, 0x2c1f, + 0x2c20, 0x2c21, 0x2c22, 0x2c23, 0x2c24, 0x2c25, 0x2c26, 0x2c27, 0x2c28, 0x2c29, 0x2c2a, 0x2c2b, 0x2c2c, 0x2c2d, 0x2c2e, 0x2c5f, + 0x2c60, 0x2c60, 0x2c62, 0x2c63, 0x2c64, 0x2c65, 0x2c66, 0x2c67, 0x2c67, 0x2c69, 0x2c69, 0x2c6b, 0x2c6b, 0x2c6d, 0x2c6e, 0x2c6f, + 0x2c70, 0x2c71, 0x2c72, 0x2c73, 0x2c74, 0x2c75, 0x2c75, 0x2c77, 0x2c78, 0x2c79, 0x2c7a, 0x2c7b, 0x2c7c, 0x2c7d, 0x2c7e, 0x2c7f, + 0x2c80, 0x2c80, 0x2c82, 0x2c82, 0x2c84, 0x2c84, 0x2c86, 0x2c86, 0x2c88, 0x2c88, 0x2c8a, 0x2c8a, 0x2c8c, 0x2c8c, 0x2c8e, 0x2c8e, + 0x2c90, 0x2c90, 0x2c92, 0x2c92, 0x2c94, 0x2c94, 0x2c96, 0x2c96, 0x2c98, 0x2c98, 0x2c9a, 0x2c9a, 0x2c9c, 0x2c9c, 0x2c9e, 0x2c9e, + 0x2ca0, 0x2ca0, 0x2ca2, 0x2ca2, 0x2ca4, 0x2ca4, 0x2ca6, 0x2ca6, 0x2ca8, 0x2ca8, 0x2caa, 0x2caa, 0x2cac, 0x2cac, 0x2cae, 0x2cae, + 0x2cb0, 0x2cb0, 0x2cb2, 0x2cb2, 0x2cb4, 0x2cb4, 0x2cb6, 0x2cb6, 0x2cb8, 0x2cb8, 0x2cba, 0x2cba, 0x2cbc, 0x2cbc, 0x2cbe, 0x2cbe, + 0x2cc0, 0x2cc0, 0x2cc2, 0x2cc2, 0x2cc4, 0x2cc4, 0x2cc6, 0x2cc6, 0x2cc8, 0x2cc8, 0x2cca, 0x2cca, 0x2ccc, 0x2ccc, 0x2cce, 0x2cce, + 0x2cd0, 0x2cd0, 0x2cd2, 0x2cd2, 0x2cd4, 0x2cd4, 0x2cd6, 0x2cd6, 0x2cd8, 0x2cd8, 0x2cda, 0x2cda, 0x2cdc, 0x2cdc, 0x2cde, 0x2cde, + 0x2ce0, 0x2ce0, 0x2ce2, 0x2ce2, 0x2ce4, 0x2ce5, 0x2ce6, 0x2ce7, 0x2ce8, 0x2ce9, 0x2cea, 0x2ceb, 0x2cec, 0x2ced, 0x2cee, 0x2cef, + 0x2cf0, 0x2cf1, 0x2cf2, 0x2cf3, 0x2cf4, 0x2cf5, 0x2cf6, 0x2cf7, 0x2cf8, 0x2cf9, 0x2cfa, 0x2cfb, 0x2cfc, 0x2cfd, 0x2cfe, 0x2cff, + 0x10a0, 0x10a1, 0x10a2, 0x10a3, 0x10a4, 0x10a5, 0x10a6, 0x10a7, 0x10a8, 0x10a9, 0x10aa, 0x10ab, 0x10ac, 0x10ad, 0x10ae, 0x10af, + 0x10b0, 0x10b1, 0x10b2, 0x10b3, 0x10b4, 0x10b5, 0x10b6, 0x10b7, 0x10b8, 0x10b9, 0x10ba, 0x10bb, 0x10bc, 0x10bd, 0x10be, 0x10bf, + 0x10c0, 0x10c1, 0x10c2, 0x10c3, 0x10c4, 0x10c5, 0x2d26, 0x2d27, 0x2d28, 0x2d29, 0x2d2a, 0x2d2b, 0x2d2c, 0x2d2d, 0x2d2e, 0x2d2f, + + /* 0xff40 - 0xff5f, offset 1744 */ + 0xff40, 0xff21, 0xff22, 0xff23, 0xff24, 0xff25, 0xff26, 0xff27, 0xff28, 0xff29, 0xff2a, 0xff2b, 0xff2c, 0xff2d, 0xff2e, 0xff2f, + 0xff30, 0xff31, 0xff32, 0xff33, 0xff34, 0xff35, 0xff36, 0xff37, 0xff38, 0xff39, 0xff3a, 0xff5b, 0xff5c, 0xff5d, 0xff5e, 0xff5f +}; + + +static const USHORT diff_table_range_low[] = +{ + 0x0060, 0x00e0, 0x0370, 0x03a0, 0x0430, 0x0560, 0x1d70, 0x1e00, 0x2140, 0x2170, 0x24d0, 0x2c30, 0xff40 +}; + +static const USHORT diff_table_range_high[] = +{ + 0x007f, 0x029f, 0x037f, 0x03ff, 0x051f, 0x058f, 0x1d7f, 0x1fff, 0x214f, 0x218f, 0x24ef, 0x2d2f, 0xff5f +}; + +static const USHORT diff_table_offset[] = +{ + 0, 32, 480, 496, 592, 832, 880, 896, 1408, 1424, 1456, 1488, 1744 +}; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_exFAT_upcase_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function return the upper case character of the input */ +/* character. */ +/* */ +/* INPUT */ +/* */ +/* character Input character */ +/* */ +/* OUTPUT */ +/* */ +/* return upper case character */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_utility_exFAT_name_hash_get */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +USHORT _fx_utility_exFAT_upcase_get(USHORT character) +{ + +UINT i; + + + /* Loop to find if the character is in the range of the differential table. */ + for (i = 0; i < sizeof(diff_table_range_low) / sizeof(USHORT); i++) + { + + /* Check the range. */ + if (character >= diff_table_range_low[i] && character <= diff_table_range_high[i]) + { + + /* Return the character from table. */ + return(_fx_utility_exFAT_upcase_table_differential[diff_table_offset[i] + character - diff_table_range_low[i]]); + } + } + + /* Lower case and upper case are the same, return directly. */ + return(character); +} + + + + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c b/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c new file mode 100644 index 00000000..172cd32e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_cache_entry_read.c @@ -0,0 +1,359 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_logical_sector_cache_entry_read PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles logical sector cache read requests for the */ +/* logical sector read function. If the function finds the requested */ +/* sector in the cache, it setup the appropriate pointers and */ +/* returns a FX_NULL. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Logical sector number */ +/* previous_cache_entry Pointer to previous entry in */ +/* non-hashed cache */ +/* */ +/* OUTPUT */ +/* */ +/* FX_CACHED_SECTOR * Cache entry to setup */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_utility_logical_sector_read Logical sector read function */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable cache, */ +/* resulting in version 6.1 */ +/* 01-31-2022 William E. Lamie Modified comment(s), fixed */ +/* errors without cache, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +FX_CACHED_SECTOR *_fx_utility_logical_sector_cache_entry_read(FX_MEDIA *media_ptr, ULONG64 logical_sector, + FX_CACHED_SECTOR **previous_cache_entry) +{ + +#ifndef FX_DISABLE_CACHE +FX_CACHED_SECTOR *cache_entry; +FX_CACHED_SECTOR temp_storage; +ULONG cache_size; +ULONG index; + + + /* Determine if the logical sector cache access should use the hash function. */ + if (media_ptr -> fx_media_sector_cache_hashed) + { + + /* Calculate the area of the cache for this logical sector. */ + + /* First compute the hashed value of this index by simply using the lower bits of + the sector number. */ + index = (ULONG)(logical_sector & media_ptr -> fx_media_sector_cache_hash_mask); + + /* Set the bit indicating there is one or more valid sectors at this cache index. */ + media_ptr -> fx_media_sector_cache_hashed_sector_valid |= ((ULONG)1) << (index % 32); + + /* Compute the actual array index by multiplying by the cache depth. */ + index = index * FX_SECTOR_CACHE_DEPTH; + + /* Build a pointer to the cache entry. */ + cache_entry = &(media_ptr -> fx_media_sector_cache[index]); + + /* Determine if the logical sector is in the cache - assuming the depth of the + sector cache is 4 entries. */ + if ((cache_entry -> fx_cached_sector_valid) && (cache_entry -> fx_cached_sector == logical_sector)) + { + + /* Yes, we found a match. Simply setup the pointer to this + buffer and return. */ + media_ptr -> fx_media_memory_buffer = cache_entry -> fx_cached_sector_memory_buffer; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of logical sectors cache read hits. */ + media_ptr -> fx_media_logical_sector_cache_read_hits++; +#endif + /* Success, return to caller immediately! */ + return(FX_NULL); + } + else if (((cache_entry + 1) -> fx_cached_sector_valid) && ((cache_entry + 1) -> fx_cached_sector == logical_sector)) + { + + /* Yes, we found a match. Simply setup the pointer to this + buffer and return. */ + media_ptr -> fx_media_memory_buffer = (cache_entry + 1) -> fx_cached_sector_memory_buffer; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of logical sectors cache read hits. */ + media_ptr -> fx_media_logical_sector_cache_read_hits++; +#endif + + /* Swap the first and second cache entries to keep the most recently used + at the top. */ + temp_storage.fx_cached_sector_memory_buffer = (cache_entry) -> fx_cached_sector_memory_buffer; + temp_storage.fx_cached_sector = (cache_entry) -> fx_cached_sector; + temp_storage.fx_cached_sector_buffer_dirty = (cache_entry) -> fx_cached_sector_buffer_dirty; + temp_storage.fx_cached_sector_valid = (cache_entry) -> fx_cached_sector_valid; + temp_storage.fx_cached_sector_type = (cache_entry) -> fx_cached_sector_type; + + (cache_entry) -> fx_cached_sector_memory_buffer = (cache_entry + 1) -> fx_cached_sector_memory_buffer; + (cache_entry) -> fx_cached_sector = (cache_entry + 1) -> fx_cached_sector; + (cache_entry) -> fx_cached_sector_buffer_dirty = (cache_entry + 1) -> fx_cached_sector_buffer_dirty; + (cache_entry) -> fx_cached_sector_valid = (cache_entry + 1) -> fx_cached_sector_valid; + (cache_entry) -> fx_cached_sector_type = (cache_entry + 1) -> fx_cached_sector_type; + + (cache_entry + 1) -> fx_cached_sector_memory_buffer = temp_storage.fx_cached_sector_memory_buffer; + (cache_entry + 1) -> fx_cached_sector = temp_storage.fx_cached_sector; + (cache_entry + 1) -> fx_cached_sector_buffer_dirty = temp_storage.fx_cached_sector_buffer_dirty; + (cache_entry + 1) -> fx_cached_sector_valid = temp_storage.fx_cached_sector_valid; + (cache_entry + 1) -> fx_cached_sector_type = temp_storage.fx_cached_sector_type; + + /* Success, return to caller immediately! */ + return(FX_NULL); + } + else if (((cache_entry + 2) -> fx_cached_sector_valid) && ((cache_entry + 2) -> fx_cached_sector == logical_sector)) + { + + /* Yes, we found a match. Simply setup the pointer to this + buffer and return. */ + media_ptr -> fx_media_memory_buffer = (cache_entry + 2) -> fx_cached_sector_memory_buffer; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of logical sectors cache read hits. */ + media_ptr -> fx_media_logical_sector_cache_read_hits++; +#endif + + /* Move the third entry to the top and the first two entries down. */ + temp_storage.fx_cached_sector_memory_buffer = (cache_entry) -> fx_cached_sector_memory_buffer; + temp_storage.fx_cached_sector = (cache_entry) -> fx_cached_sector; + temp_storage.fx_cached_sector_buffer_dirty = (cache_entry) -> fx_cached_sector_buffer_dirty; + temp_storage.fx_cached_sector_valid = (cache_entry) -> fx_cached_sector_valid; + temp_storage.fx_cached_sector_type = (cache_entry) -> fx_cached_sector_type; + + (cache_entry) -> fx_cached_sector_memory_buffer = (cache_entry + 2) -> fx_cached_sector_memory_buffer; + (cache_entry) -> fx_cached_sector = (cache_entry + 2) -> fx_cached_sector; + (cache_entry) -> fx_cached_sector_buffer_dirty = (cache_entry + 2) -> fx_cached_sector_buffer_dirty; + (cache_entry) -> fx_cached_sector_valid = (cache_entry + 2) -> fx_cached_sector_valid; + (cache_entry) -> fx_cached_sector_type = (cache_entry + 2) -> fx_cached_sector_type; + + (cache_entry + 2) -> fx_cached_sector_memory_buffer = (cache_entry + 1) -> fx_cached_sector_memory_buffer; + (cache_entry + 2) -> fx_cached_sector = (cache_entry + 1) -> fx_cached_sector; + (cache_entry + 2) -> fx_cached_sector_buffer_dirty = (cache_entry + 1) -> fx_cached_sector_buffer_dirty; + (cache_entry + 2) -> fx_cached_sector_valid = (cache_entry + 1) -> fx_cached_sector_valid; + (cache_entry + 2) -> fx_cached_sector_type = (cache_entry + 1) -> fx_cached_sector_type; + + (cache_entry + 1) -> fx_cached_sector_memory_buffer = temp_storage.fx_cached_sector_memory_buffer; + (cache_entry + 1) -> fx_cached_sector = temp_storage.fx_cached_sector; + (cache_entry + 1) -> fx_cached_sector_buffer_dirty = temp_storage.fx_cached_sector_buffer_dirty; + (cache_entry + 1) -> fx_cached_sector_valid = temp_storage.fx_cached_sector_valid; + (cache_entry + 1) -> fx_cached_sector_type = temp_storage.fx_cached_sector_type; + + /* Success, return to caller immediately! */ + return(FX_NULL); + } + else if (((cache_entry + 3) -> fx_cached_sector_valid) && ((cache_entry + 3) -> fx_cached_sector == logical_sector)) + { + + /* Yes, we found a match. Simply setup the pointer to this + buffer and return. */ + media_ptr -> fx_media_memory_buffer = (cache_entry + 3) -> fx_cached_sector_memory_buffer; + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of logical sectors cache read hits. */ + media_ptr -> fx_media_logical_sector_cache_read_hits++; +#endif + + /* Move the last entry to the top and the first three entries down. */ + temp_storage.fx_cached_sector_memory_buffer = (cache_entry) -> fx_cached_sector_memory_buffer; + temp_storage.fx_cached_sector = (cache_entry) -> fx_cached_sector; + temp_storage.fx_cached_sector_buffer_dirty = (cache_entry) -> fx_cached_sector_buffer_dirty; + temp_storage.fx_cached_sector_valid = (cache_entry) -> fx_cached_sector_valid; + temp_storage.fx_cached_sector_type = (cache_entry) -> fx_cached_sector_type; + + (cache_entry) -> fx_cached_sector_memory_buffer = (cache_entry + 3) -> fx_cached_sector_memory_buffer; + (cache_entry) -> fx_cached_sector = (cache_entry + 3) -> fx_cached_sector; + (cache_entry) -> fx_cached_sector_buffer_dirty = (cache_entry + 3) -> fx_cached_sector_buffer_dirty; + (cache_entry) -> fx_cached_sector_valid = (cache_entry + 3) -> fx_cached_sector_valid; + (cache_entry) -> fx_cached_sector_type = (cache_entry + 3) -> fx_cached_sector_type; + + (cache_entry + 3) -> fx_cached_sector_memory_buffer = (cache_entry + 2) -> fx_cached_sector_memory_buffer; + (cache_entry + 3) -> fx_cached_sector = (cache_entry + 2) -> fx_cached_sector; + (cache_entry + 3) -> fx_cached_sector_buffer_dirty = (cache_entry + 2) -> fx_cached_sector_buffer_dirty; + (cache_entry + 3) -> fx_cached_sector_valid = (cache_entry + 2) -> fx_cached_sector_valid; + (cache_entry + 3) -> fx_cached_sector_type = (cache_entry + 2) -> fx_cached_sector_type; + + (cache_entry + 2) -> fx_cached_sector_memory_buffer = (cache_entry + 1) -> fx_cached_sector_memory_buffer; + (cache_entry + 2) -> fx_cached_sector = (cache_entry + 1) -> fx_cached_sector; + (cache_entry + 2) -> fx_cached_sector_buffer_dirty = (cache_entry + 1) -> fx_cached_sector_buffer_dirty; + (cache_entry + 2) -> fx_cached_sector_valid = (cache_entry + 1) -> fx_cached_sector_valid; + (cache_entry + 2) -> fx_cached_sector_type = (cache_entry + 1) -> fx_cached_sector_type; + + (cache_entry + 1) -> fx_cached_sector_memory_buffer = temp_storage.fx_cached_sector_memory_buffer; + (cache_entry + 1) -> fx_cached_sector = temp_storage.fx_cached_sector; + (cache_entry + 1) -> fx_cached_sector_buffer_dirty = temp_storage.fx_cached_sector_buffer_dirty; + (cache_entry + 1) -> fx_cached_sector_valid = temp_storage.fx_cached_sector_valid; + (cache_entry + 1) -> fx_cached_sector_type = temp_storage.fx_cached_sector_type; + + /* Success, return to caller immediately! */ + return(FX_NULL); + } + + /* At this point we have a cache miss. We need to move all of the sectors down one slot, swapping + the 4th entry with the first. */ + temp_storage.fx_cached_sector_memory_buffer = (cache_entry + 3) -> fx_cached_sector_memory_buffer; + temp_storage.fx_cached_sector = (cache_entry + 3) -> fx_cached_sector; + temp_storage.fx_cached_sector_buffer_dirty = (cache_entry + 3) -> fx_cached_sector_buffer_dirty; + temp_storage.fx_cached_sector_valid = (cache_entry + 3) -> fx_cached_sector_valid; + temp_storage.fx_cached_sector_type = (cache_entry + 3) -> fx_cached_sector_type; + + (cache_entry + 3) -> fx_cached_sector_memory_buffer = (cache_entry + 2) -> fx_cached_sector_memory_buffer; + (cache_entry + 3) -> fx_cached_sector = (cache_entry + 2) -> fx_cached_sector; + (cache_entry + 3) -> fx_cached_sector_buffer_dirty = (cache_entry + 2) -> fx_cached_sector_buffer_dirty; + (cache_entry + 3) -> fx_cached_sector_valid = (cache_entry + 2) -> fx_cached_sector_valid; + (cache_entry + 3) -> fx_cached_sector_type = (cache_entry + 2) -> fx_cached_sector_type; + + (cache_entry + 2) -> fx_cached_sector_memory_buffer = (cache_entry + 1) -> fx_cached_sector_memory_buffer; + (cache_entry + 2) -> fx_cached_sector = (cache_entry + 1) -> fx_cached_sector; + (cache_entry + 2) -> fx_cached_sector_buffer_dirty = (cache_entry + 1) -> fx_cached_sector_buffer_dirty; + (cache_entry + 2) -> fx_cached_sector_valid = (cache_entry + 1) -> fx_cached_sector_valid; + (cache_entry + 2) -> fx_cached_sector_type = (cache_entry + 1) -> fx_cached_sector_type; + + (cache_entry + 1) -> fx_cached_sector_memory_buffer = (cache_entry) -> fx_cached_sector_memory_buffer; + (cache_entry + 1) -> fx_cached_sector = (cache_entry) -> fx_cached_sector; + (cache_entry + 1) -> fx_cached_sector_buffer_dirty = (cache_entry) -> fx_cached_sector_buffer_dirty; + (cache_entry + 1) -> fx_cached_sector_valid = (cache_entry) -> fx_cached_sector_valid; + (cache_entry + 1) -> fx_cached_sector_type = (cache_entry) -> fx_cached_sector_type; + + (cache_entry) -> fx_cached_sector_memory_buffer = temp_storage.fx_cached_sector_memory_buffer; + (cache_entry) -> fx_cached_sector = temp_storage.fx_cached_sector; + (cache_entry) -> fx_cached_sector_buffer_dirty = temp_storage.fx_cached_sector_buffer_dirty; + (cache_entry) -> fx_cached_sector_valid = temp_storage.fx_cached_sector_valid; + (cache_entry) -> fx_cached_sector_type = temp_storage.fx_cached_sector_type; + + /* Set the previous pointer to NULL to avoid the linked list update below. */ + *previous_cache_entry = FX_NULL; + } + else + { + + /* Search for an entry in the cache that matches this request. */ + cache_size = media_ptr -> fx_media_sector_cache_size; + cache_entry = media_ptr -> fx_media_sector_cache_list_ptr; + *previous_cache_entry = FX_NULL; + + /* Look at the cache entries until a match is found or the end of + the cache is reached. */ + while (cache_size--) + { + + /* Determine if the requested sector has been found. */ + if ((cache_entry -> fx_cached_sector_valid) && (cache_entry -> fx_cached_sector == logical_sector)) + { + + /* Yes, we found a match. Simply setup the pointer to this + buffer and return. */ + media_ptr -> fx_media_memory_buffer = cache_entry -> fx_cached_sector_memory_buffer; + + /* Determine if we need to update the last used list. */ + if (*previous_cache_entry) + { + + /* Yes, the current entry is not at the front of the list + so we need to change the order. */ + + /* Link the previous entry to this entry's next pointer. */ + (*previous_cache_entry) -> fx_cached_sector_next_used = + cache_entry -> fx_cached_sector_next_used; + + /* Place this entry at the head of the list. */ + cache_entry -> fx_cached_sector_next_used = + media_ptr -> fx_media_sector_cache_list_ptr; + media_ptr -> fx_media_sector_cache_list_ptr = cache_entry; + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of logical sectors cache read hits. */ + media_ptr -> fx_media_logical_sector_cache_read_hits++; +#endif + + /* Success, return to caller immediately! */ + return(FX_NULL); + } + + /* Otherwise, we have not found the cached entry yet. */ + + /* If there are more entries, move to the next one. */ + if (cache_entry -> fx_cached_sector_next_used) + { + + *previous_cache_entry = cache_entry; + cache_entry = cache_entry -> fx_cached_sector_next_used; + } + } + } + + /* The requested sector is not in cache, return the last cache entry. */ + return(cache_entry); +#else + FX_PARAMETER_NOT_USED(media_ptr); + FX_PARAMETER_NOT_USED(logical_sector); + FX_PARAMETER_NOT_USED(previous_cache_entry); + return(FX_NULL); +#endif /* FX_DISABLE_CACHE */ +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c b/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c new file mode 100644 index 00000000..fd79aa70 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_flush.c @@ -0,0 +1,522 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_logical_sector_flush PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles logical sector flush requests for all FileX */ +/* components. It will process all dirty logical sectors in the */ +/* logical sector cache within the range specified. This function */ +/* optionally invalidates sectors. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* starting_sector Starting sector number */ +/* sectors Number of sectors */ +/* invalidate Invalidate flag */ +/* (FX_TRUE -> invalidate) */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* I/O Driver */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable cache, */ +/* resulting in version 6.1 */ +/* 01-31-2022 William E. Lamie Modified comment(s), fixed */ +/* errors without cache, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_logical_sector_flush(FX_MEDIA *media_ptr, ULONG64 starting_sector, ULONG64 sectors, UINT invalidate) +{ + +#ifndef FX_DISABLE_CACHE +FX_CACHED_SECTOR *cache_entry; +UINT cache_size; +UINT i, bit_set, use_starting_sector; +ULONG index; +ULONG remaining_valid; +ULONG remaining_dirty; +ULONG64 ending_sector; +ULONG valid_bit_map; + + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_UTILITY_LOGICAL_SECTOR_FLUSH_EXTENSION + + /* Calculate the ending sector. */ + ending_sector = starting_sector + sectors - 1; + + /* Pickup the number of dirty sectors currently in the cache. */ + remaining_dirty = media_ptr -> fx_media_sector_cache_dirty_count; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_MEDIA_FLUSH, media_ptr, media_ptr -> fx_media_sector_cache_dirty_count, 0, 0, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Determine what type of cache configuration we have. */ + if (media_ptr -> fx_media_sector_cache_hashed == FX_FALSE) + { + + /* Linear cache present, simply walk through the search list until + an unused cache entry is present. */ + + /* Flush and invalidate the internal logical sector cache. */ + cache_size = media_ptr -> fx_media_sector_cache_size; + cache_entry = media_ptr -> fx_media_sector_cache_list_ptr; + + /* Look at the cache entries that have been written to. */ + while ((cache_size--) && (cache_entry -> fx_cached_sector)) + { + + /* Determine if invalidation is not required and there are no + more dirty sectors. */ + if ((remaining_dirty == 0) && (invalidate == FX_FALSE)) + { + + /* Yes, nothing left to do. */ + break; + } + + /* Determine if there are any more sectors to process. */ + if (sectors == 0) + { + + /* No more sectors required to process. */ + break; + } + + /* Determine if this cached sector is within the specified range and is valid. */ + if ((cache_entry -> fx_cached_sector_valid) && + (cache_entry -> fx_cached_sector >= starting_sector) && + (cache_entry -> fx_cached_sector <= ending_sector)) + { + + /* Yes, the cache entry is valid and within the specified range. Determine if + the requested sector has been written to. */ + if (cache_entry -> fx_cached_sector_buffer_dirty) + { + + /* Yes, write the cached sector out to the media. */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect == FX_FALSE) + { + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = cache_entry -> fx_cached_sector_memory_buffer; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = cache_entry -> fx_cached_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)cache_entry -> fx_cached_sector; +#endif + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = cache_entry -> fx_cached_sector_type; + + /* Sectors other than FX_DATA_SECTOR will never be dirty when FX_FAULT_TOLERANT is defined. */ +#ifndef FX_FAULT_TOLERANT + /* Determine if the system write flag needs to be set. */ + if (cache_entry -> fx_cached_sector_type != FX_DATA_SECTOR) + { + + /* Yes, a system sector write is present so set the flag. The driver + can use this flag to make extra safeguards in writing the sector + out, yielding more fault tolerance. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + } +#endif /* FX_FAULT_TOLERANT */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, cache_entry -> fx_cached_sector, 1, cache_entry -> fx_cached_sector_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Check for successful completion. */ + if (media_ptr -> fx_media_driver_status) + { + + /* Error writing a cached sector out. Return the + error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Clear the buffer dirty flag since it has been flushed + out. */ + cache_entry -> fx_cached_sector_buffer_dirty = FX_FALSE; + + /* Decrement the number of dirty sectors currently in the cache. */ + media_ptr -> fx_media_sector_cache_dirty_count--; + remaining_dirty--; + } + } + + /* Determine if the invalidate option is specified. */ + if (invalidate) + { + + /* Invalidate the cache entry. */ + cache_entry -> fx_cached_sector_valid = FX_FALSE; + + /* Place all ones in the sector number. */ + cache_entry -> fx_cached_sector = (~(ULONG64)0); + + /* Determine if this sector is still dirty, this could be the case if + write protection was turned on. */ + if (cache_entry -> fx_cached_sector_buffer_dirty) + { + + /* Yes, clear the dirty flag. */ + cache_entry -> fx_cached_sector_buffer_dirty = FX_FALSE; + + /* Decrement the number of dirty sectors currently in the cache. */ + media_ptr -> fx_media_sector_cache_dirty_count--; + remaining_dirty--; + } + } + + /* Decrement the number of sectors in the range that have been processed. */ + sectors--; + } + + /* Move to the next entry in the sector cache. */ + cache_entry = cache_entry -> fx_cached_sector_next_used; + } + } + else + { + + /* Hashed cache is present. Pickup the cache size. */ + cache_size = media_ptr -> fx_media_sector_cache_size; + + /* Initialize the loop control parameters. */ + bit_set = 0; + valid_bit_map = media_ptr -> fx_media_sector_cache_hashed_sector_valid; + + /* Determine how to process the hashed cache based on the number of sectors + to process. If the sequential sector range is less than the bit map size, + simply use the starting sector to derive the index into the cache. */ + if (sectors < 32) + { + use_starting_sector = FX_TRUE; + } + else + { + use_starting_sector = FX_FALSE; + } + + /* Determine if there is anything valid in the cache. */ + while (valid_bit_map) + { + + /* Determine if invalidation is not required and there are no + more dirty sectors. */ + if ((remaining_dirty == 0) && (invalidate == FX_FALSE)) + { + + /* Yes, nothing left to do. */ + break; + } + + /* Determine if there are any more sectors to process. */ + if ((sectors == 0) || (starting_sector > ending_sector)) + { + + /* No more sectors required to process. */ + break; + } + + /* Determine how to compute the hash index. */ + if (use_starting_sector) + { + + /* Calculate the hash value of this sector using the lower bits. */ + index = (ULONG)(starting_sector & media_ptr -> fx_media_sector_cache_hash_mask); + + /* Calculate the bit set indicating there is one or more valid sectors at this cache index. */ + bit_set = (index % 32); + + /* Compute the actual array index by multiplying by the cache depth. */ + index = (bit_set * FX_SECTOR_CACHE_DEPTH); + } + else + { + + /* Walk the bit map to find the next valid entry. */ + + /* Find the next set bit. */ + while ((valid_bit_map & 1) == 0) + { + + /* Otherwise, shift down the bit in the bit map. */ + valid_bit_map = valid_bit_map >> 1; + + /* Increment the set bit marker. */ + bit_set++; + } + + /* Compute the first actual index into the hashed cache. */ + index = (bit_set * FX_SECTOR_CACHE_DEPTH); + } + + /* At this point, bit_set represents the next group of hashed sectors that could + have valid cache entries and index represents the index into the sector cache + of that sector group. */ + + /* Clear the remaining valid sectors for this entry in the bit map. */ + remaining_valid = 0; + + /* Loop to check the corresponding hash entries. */ + do + { + + /* Setup pointer to the cache entry. */ + cache_entry = &(media_ptr -> fx_media_sector_cache[index]); + + /* Loop to examine the full depth of the hashed cache. */ + for (i = 0; i < 4; i++) + { + + /* Determine if this cached sector is within the specified range and is valid. */ + if ((cache_entry -> fx_cached_sector_valid) && + (cache_entry -> fx_cached_sector >= starting_sector) && + (cache_entry -> fx_cached_sector <= ending_sector)) + { + + /* Determine if the requested sector has been written to. */ + if (cache_entry -> fx_cached_sector_buffer_dirty) + { + + + /* Yes, write the cached sector out to the media. */ + + /* Check for write protect at the media level (set by driver). */ + if (media_ptr -> fx_media_driver_write_protect == FX_FALSE) + { + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build Write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = cache_entry -> fx_cached_sector_memory_buffer; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = cache_entry -> fx_cached_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)cache_entry -> fx_cached_sector; +#endif + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = cache_entry -> fx_cached_sector_type; + + /* Sectors other than FX_DATA_SECTOR will never be dirty when FX_FAULT_TOLERANT is defined. */ +#ifndef FX_FAULT_TOLERANT + /* Determine if the system write flag needs to be set. */ + if (cache_entry -> fx_cached_sector_type != FX_DATA_SECTOR) + { + + /* Yes, a system sector write is present so set the flag. The driver + can use this flag to make extra safeguards in writing the sector + out, yielding more fault tolerance. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + } +#endif /* FX_FAULT_TOLERANT */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, cache_entry -> fx_cached_sector, 1, cache_entry -> fx_cached_sector_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Check for successful completion. */ + if (media_ptr -> fx_media_driver_status) + { + + /* Error writing a cached sector out. Return the + error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Clear the buffer dirty flag since it has been flushed + out. */ + cache_entry -> fx_cached_sector_buffer_dirty = FX_FALSE; + + /* Decrement the number of dirty sectors currently in the cache. */ + media_ptr -> fx_media_sector_cache_dirty_count--; + remaining_dirty--; + } + } + + /* Determine if the invalidate option is specified. */ + if (invalidate) + { + + /* Invalidate the cache entry. */ + cache_entry -> fx_cached_sector_valid = FX_FALSE; + + /* Place all ones in the sector number. */ + cache_entry -> fx_cached_sector = (~(ULONG64)0); + + /* Determine if this sector is still dirty, this could be the case if + write protection was turned on. */ + if (cache_entry -> fx_cached_sector_buffer_dirty) + { + + /* Yes, clear the dirty flag. */ + cache_entry -> fx_cached_sector_buffer_dirty = FX_FALSE; + + /* Decrement the number of dirty sectors currently in the cache. */ + media_ptr -> fx_media_sector_cache_dirty_count--; + remaining_dirty--; + } + } + + /* Decrement the number of sectors in the range that have been processed. */ + sectors--; + } + else + { + + /* Determine if the sector is valid. */ + if (cache_entry -> fx_cached_sector_valid) + { + + /* Increment the number of still remaining but out of range sectors. */ + remaining_valid++; + } + } + + /* Determine if invalidation is not required and there are no + more dirty sectors. */ + if ((remaining_dirty == 0) && (invalidate == FX_FALSE)) + { + + /* Yes, nothing left to do. */ + break; + } + + /* Determine if there are any more sectors to process. */ + if ((sectors == 0) && (invalidate == FX_FALSE)) + { + + /* No more sectors required to process. */ + break; + } + + /* Move to the next cache entry. */ + cache_entry++; + } + + /* Move the index to the next position since the bit map can only represent 32 + cache entries. */ + index = index + (32 * FX_SECTOR_CACHE_DEPTH); + } while (index < cache_size); + + /* Determine if invalidation was required and there are no more valid sectors + associated with this bit position. */ + if ((invalidate) && (remaining_valid == 0)) + { + + /* Clear this bit position. */ + media_ptr -> fx_media_sector_cache_hashed_sector_valid &= ~(((ULONG)1) << bit_set); + } + + /* Determine if the starting sector is being used for examination of the hash. */ + if (use_starting_sector) + { + + /* Move to the next sector. */ + starting_sector++; + } + else + { + + /* Move to next bit in the map. */ + valid_bit_map = valid_bit_map >> 1; + + /* Increment the set bit marker. */ + bit_set++; + } + } + } +#else + FX_PARAMETER_NOT_USED(media_ptr); + FX_PARAMETER_NOT_USED(starting_sector); + FX_PARAMETER_NOT_USED(sectors); + FX_PARAMETER_NOT_USED(invalidate); +#endif /* FX_DISABLE_CACHE */ + + /* If we get here, return successful status to the caller. */ + return(FX_SUCCESS); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c b/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c new file mode 100644 index 00000000..38f7f309 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_read.c @@ -0,0 +1,607 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_logical_sector_read PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles logical sector read requests for all FileX */ +/* components. If the logical sector is currently in the logical */ +/* sector cache, the function simply sets the appropriate pointer and */ +/* returns a successful status to the caller. Otherwise, physical I/O */ +/* is requested through the corresponding I/O driver. */ +/* */ +/* Note: Conversion of the logical sector is done inside the driver. */ +/* This results in a performance boost for FLASH or RAM media */ +/* devices. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Logical sector number */ +/* buffer_ptr Pointer of receiving buffer */ +/* sectors Number of sectors to read */ +/* sector_type Type of sector(s) to read */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_cache_entry_read */ +/* Read logical sector cache */ +/* _fx_utility_logical_sector_flush Flush and invalidate sectors */ +/* that overlap with non-cache */ +/* sector I/O. */ +/* _fx_utility_memory_copy Copy cache sector */ +/* _fx_fault_tolerant_read_directory_sector */ +/* Read directory sector */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* verified memcpy usage, and */ +/* added conditional to */ +/* disable cache, */ +/* resulting in version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s), */ +/* updated check for logical */ +/* sector value, */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_logical_sector_read(FX_MEDIA *media_ptr, ULONG64 logical_sector, + VOID *buffer_ptr, ULONG sectors, UCHAR sector_type) +{ +#ifndef FX_DISABLE_CACHE +FX_CACHED_SECTOR *cache_entry; +FX_CACHED_SECTOR *previous_cache_entry; +ULONG64 end_sector; +#endif /* FX_DISABLE_CACHE */ + +#ifdef FX_ENABLE_FAULT_TOLERANT +UINT status; +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Determine if the request is for FAT sector. */ + if (sector_type == FX_FAT_SECTOR) + { + + /* Increment the number of FAT sector reads. */ + media_ptr -> fx_media_fat_sector_reads++; + } + + /* Increment the number of logical sectors read. */ + media_ptr -> fx_media_logical_sector_reads++; +#endif + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_UTILITY_LOGICAL_SECTOR_READ_EXTENSION + +#ifndef FX_DISABLE_CACHE + /* Determine if the request is for the internal media buffer area. */ + if ((((UCHAR *)buffer_ptr) >= media_ptr -> fx_media_memory_buffer) && + (((UCHAR *)buffer_ptr) <= media_ptr -> fx_media_sector_cache_end)) + { + + /* Internal cache buffer is requested. */ + + /* Examine the logical sector cache. */ + cache_entry = _fx_utility_logical_sector_cache_entry_read(media_ptr, logical_sector, &previous_cache_entry); + + /* Was the sector found? */ + if (cache_entry == FX_NULL) + { + + /* Yes, the sector was found. Return success! */ + return(FX_SUCCESS); + } + + /* At this point, we need to read in a sector from the media. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of logical sectors cache read misses. */ + media_ptr -> fx_media_logical_sector_cache_read_misses++; +#endif + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_LOG_SECTOR_CACHE_MISS, media_ptr, logical_sector, media_ptr -> fx_media_logical_sector_cache_read_misses, media_ptr -> fx_media_sector_cache_size, FX_TRACE_INTERNAL_EVENTS, 0, 0) +#else + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_LOG_SECTOR_CACHE_MISS, media_ptr, logical_sector, 0, media_ptr -> fx_media_sector_cache_size, FX_TRACE_INTERNAL_EVENTS, 0, 0) +#endif + + /* First, check and see if the last used entry has been + modified. */ + if ((cache_entry -> fx_cached_sector_valid) && + (cache_entry -> fx_cached_sector_buffer_dirty)) + { + + /* Yes, we need to flush this buffer out to the physical media + before we read in the new buffer. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = cache_entry -> fx_cached_sector_memory_buffer; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = cache_entry -> fx_cached_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)cache_entry -> fx_cached_sector; +#endif + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = cache_entry -> fx_cached_sector_type; + + /* Determine if the sector is a data sector or a system sector. */ + if (cache_entry -> fx_cached_sector_type != FX_DATA_SECTOR) + { + + /* System sector is present. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, cache_entry -> fx_cached_sector, 1, cache_entry -> fx_cached_sector_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Check for successful completion. */ + if (media_ptr -> fx_media_driver_status) + { + + /* Error writing a cached sector out. Return the + error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Clear the buffer dirty flag since it has been flushed + out. */ + cache_entry -> fx_cached_sector_buffer_dirty = FX_FALSE; + + /* Decrement the number of outstanding dirty cache entries. */ + media_ptr -> fx_media_sector_cache_dirty_count--; + } + + /* At this point, we can go out and setup this cached sector + entry. */ + + /* Compare against logical sector to make sure it is valid. */ + if (logical_sector >= media_ptr -> fx_media_total_sectors) + { + return(FX_SECTOR_INVALID); + } + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver read sector(s) requests. */ + media_ptr -> fx_media_driver_read_requests++; +#endif + + /* Build Read request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = cache_entry -> fx_cached_sector_memory_buffer; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = logical_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector; +#endif + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = sector_type; + + /* Determine if the sector is a data sector or a system sector. */ + if (sector_type == FX_DATA_SECTOR) + { + + /* Data sector is present. */ + media_ptr -> fx_media_driver_data_sector_read = FX_TRUE; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_READ, media_ptr, logical_sector, 1, cache_entry -> fx_cached_sector_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear data sector is present flag. */ + media_ptr -> fx_media_driver_data_sector_read = FX_FALSE; + + /* Determine if the read was successful. */ + if (media_ptr -> fx_media_driver_status == FX_SUCCESS) + { + + /* Remember the sector number. */ + cache_entry -> fx_cached_sector = logical_sector; + + /* Make the cache entry valid. */ + cache_entry -> fx_cached_sector_valid = FX_TRUE; + + /* Remember the sector type. */ + cache_entry -> fx_cached_sector_type = sector_type; + + /* Place this entry that the head of the cached sector + list. */ + + /* Determine if we need to update the last used list. */ + if (previous_cache_entry) + { + + /* Yes, the current entry is not at the front of the list + so we need to change the order. */ + + /* Link the previous entry to this entry's next pointer. */ + previous_cache_entry -> fx_cached_sector_next_used = + cache_entry -> fx_cached_sector_next_used; + + /* Place this entry at the head of the list. */ + cache_entry -> fx_cached_sector_next_used = + media_ptr -> fx_media_sector_cache_list_ptr; + media_ptr -> fx_media_sector_cache_list_ptr = cache_entry; + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED) && + (sector_type == FX_DIRECTORY_SECTOR)) + { + + /* Read sector from log file. */ + status = _fx_fault_tolerant_read_directory_sector(media_ptr, logical_sector, cache_entry -> fx_cached_sector_memory_buffer, 1); + + /* Check for successful completion. */ + if (status) + { + + /* Return the error status. */ + return(status); + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + } + else + { + + /* Invalidate the cache entry on read errors. */ + cache_entry -> fx_cached_sector_valid = FX_FALSE; + + /* Put all ones in the sector value. */ + cache_entry -> fx_cached_sector = (~(ULONG64)0); + } + + /* Simply setup the pointer to this buffer and return. */ + media_ptr -> fx_media_memory_buffer = cache_entry -> fx_cached_sector_memory_buffer; + + /* Return the driver status. */ + return(media_ptr -> fx_media_driver_status); + } +#else + if ((logical_sector == media_ptr -> fx_media_memory_buffer_sector) && (sectors == 1) && (buffer_ptr == media_ptr -> fx_media_memory_buffer)) + { + return(FX_SUCCESS); + } +#endif + else + { + + /* Direct I/O to application buffer area. */ + + /* Compare against logical sector to make sure it is valid. */ + if ((logical_sector + sectors - 1) > (ULONG)media_ptr -> fx_media_total_sectors) + { + return(FX_SECTOR_INVALID); + } + +#ifndef FX_DISABLE_CACHE + /* Attempt to fill the beginning of the buffer from cached sectors. */ + while (sectors) + { + + /* Determine if the sector is in the cache. */ + if (_fx_utility_logical_sector_cache_entry_read(media_ptr, logical_sector, &previous_cache_entry)) + { + + /* Not in the cache - get out of the loop! */ + break; + } + + /* Yes, sector is in the cache. Copy the data from the cache to the destination buffer. */ + _fx_utility_memory_copy(media_ptr -> fx_media_memory_buffer, buffer_ptr, media_ptr -> fx_media_bytes_per_sector); /* Use case of memcpy is verified. */ + + /* Advance the destination buffer. */ + buffer_ptr = ((UCHAR *)buffer_ptr) + media_ptr -> fx_media_bytes_per_sector; + + /* Advance the sector and decrement the number of sectors left. */ + logical_sector++; + sectors--; + } + + /* Calculate the end sector. */ + end_sector = logical_sector + sectors - 1; + + /* Attempt to fill the end of the buffer from the opposite direction. */ + while (sectors) + { + + /* Determine if the sector is in the cache. */ + if (_fx_utility_logical_sector_cache_entry_read(media_ptr, end_sector, &previous_cache_entry)) + { + + /* Not in the cache - get out of the loop! */ + break; + } + + /* Yes, sector is in the cache. Copy the data from the cache to the destination buffer. */ + _fx_utility_memory_copy(media_ptr -> fx_media_memory_buffer, /* Use case of memcpy is verified. */ + ((UCHAR *)buffer_ptr) + ((sectors - 1) * media_ptr -> fx_media_bytes_per_sector), + media_ptr -> fx_media_bytes_per_sector); + + /* Move sector to previous sector and decrement the number of sectors left. */ + end_sector--; + sectors--; + } + + /* Determine if there are still sectors left to read. */ + if (sectors == 0) + { + + /* No more sectors to read - return success! */ + return(FX_SUCCESS); + } + + /* Flush and invalidate any entries in the cache that are in this direct I/O read request range. */ + _fx_utility_logical_sector_flush(media_ptr, logical_sector, (ULONG64) sectors, FX_TRUE); +#endif /* FX_DISABLE_CACHE */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver read sector(s) requests. */ + media_ptr -> fx_media_driver_read_requests++; +#endif + + /* Build read request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_READ; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = buffer_ptr; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = logical_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector; +#endif + media_ptr -> fx_media_driver_sectors = sectors; + media_ptr -> fx_media_driver_sector_type = sector_type; + + /* Determine if the sector is a data sector or a system sector. */ + if (sector_type == FX_DATA_SECTOR) + { + + /* Data sector is present. */ + media_ptr -> fx_media_driver_data_sector_read = FX_TRUE; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_READ, media_ptr, logical_sector, sectors, buffer_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to read the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear data sector is present flag. */ + media_ptr -> fx_media_driver_data_sector_read = FX_FALSE; + +#ifdef FX_DISABLE_CACHE + if ((media_ptr -> fx_media_driver_status == FX_SUCCESS) && (sectors == 1) && (buffer_ptr == media_ptr -> fx_media_memory_buffer)) + { + media_ptr -> fx_media_memory_buffer_sector = logical_sector; + return(FX_SUCCESS); + } +#endif /* FX_DISABLE_CACHE */ + +#ifndef FX_DISABLE_DIRECT_DATA_READ_CACHE_FILL + + /* Determine if the read was successful and if number of sectors just read will + reasonably fit into the cache. */ + if ((media_ptr -> fx_media_driver_status == FX_SUCCESS) && (sectors < (media_ptr -> fx_media_sector_cache_size / 4))) + { + + /* Yes, read of direct sectors was successful. */ + + /* Copy the sectors directly read into the cache so they are available on + subsequent read requests. */ + while (sectors) + { + + /* Attempt to read the cache entry. */ + cache_entry = _fx_utility_logical_sector_cache_entry_read(media_ptr, logical_sector, &previous_cache_entry); + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_UTILITY_LOGICAL_SECTOR_READ_EXTENSION_1 + + /* At this point, a cache entry should always be present since we invalidated + the cache over this sector range previously. In any case, check for the error + condition. */ + if (cache_entry == FX_NULL) + { + + /* This case should never happen, however, if it does simply give up on updating the + cache with the sectors from the direct read. */ + return(FX_SUCCESS); + } + + /* Determine if the cache entry is dirty and needs to be written out before it is used. */ + if ((cache_entry -> fx_cached_sector_valid) && + (cache_entry -> fx_cached_sector_buffer_dirty)) + { + + /* Yes, we need to flush this buffer out to the physical media + before we read in the new buffer. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = cache_entry -> fx_cached_sector_memory_buffer; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = cache_entry -> fx_cached_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)cache_entry -> fx_cached_sector; +#endif + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = cache_entry -> fx_cached_sector_type; + + /* Only data sectors may be dirty when FX_FAULT_TOLERANT is defined */ +#ifndef FX_FAULT_TOLERANT + /* Determine if the sector is a data sector or a system sector. */ + if (cache_entry -> fx_cached_sector_type != FX_DATA_SECTOR) + { + + /* System sector is present. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + } +#endif /* FX_FAULT_TOLERANT */ + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, cache_entry -> fx_cached_sector, 1, cache_entry -> fx_cached_sector_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector. */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Check for successful completion. */ + if (media_ptr -> fx_media_driver_status) + { + + /* Error writing a cached sector out. Return the + error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* Clear the buffer dirty flag since it has been flushed + out. */ + cache_entry -> fx_cached_sector_buffer_dirty = FX_FALSE; + + /* Decrement the number of outstanding dirty cache entries. */ + media_ptr -> fx_media_sector_cache_dirty_count--; + } + + /* Now setup the cache entry with information from the new sector. */ + + /* Remember the sector number. */ + cache_entry -> fx_cached_sector = logical_sector; + + /* Make the cache entry valid. */ + cache_entry -> fx_cached_sector_valid = FX_TRUE; + + /* Remember the sector type. */ + cache_entry -> fx_cached_sector_type = sector_type; + + /* Place this entry that the head of the cached sector + list. */ + + /* Determine if we need to update the last used list. */ + if (previous_cache_entry) + { + + /* Yes, the current entry is not at the front of the list + so we need to change the order. */ + + /* Link the previous entry to this entry's next pointer. */ + previous_cache_entry -> fx_cached_sector_next_used = + cache_entry -> fx_cached_sector_next_used; + + /* Place this entry at the head of the list. */ + cache_entry -> fx_cached_sector_next_used = + media_ptr -> fx_media_sector_cache_list_ptr; + media_ptr -> fx_media_sector_cache_list_ptr = cache_entry; + } + + /* Copy the data from the destination buffer to the cache entry. */ + _fx_utility_memory_copy(buffer_ptr, /* Use case of memcpy is verified. */ + cache_entry -> fx_cached_sector_memory_buffer, + media_ptr -> fx_media_bytes_per_sector); + + /* Advance the destination buffer. */ + buffer_ptr = ((UCHAR *)buffer_ptr) + media_ptr -> fx_media_bytes_per_sector; + + /* Advance the source sector and decrement the sector count. */ + logical_sector++; + sectors--; + } + } +#endif + + /* Return the driver status. */ + return(media_ptr -> fx_media_driver_status); + } +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c b/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c new file mode 100644 index 00000000..62b7fa06 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_logical_sector_write.c @@ -0,0 +1,444 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_logical_sector_write PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles logical sector write requests for all FileX */ +/* components. If the logical sector is currently in the media's */ +/* buffer supplied by the caller, the function simply marks the buffer */ +/* as written to. Otherwise, physical I/O is requested through the */ +/* corresponding I/O driver. */ +/* */ +/* Note: Conversion of the logical sector is done inside the driver. */ +/* This results in a performance boost for FLASH or RAM media */ +/* devices. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Logical sector number */ +/* buffer_ptr Pointer of sector buffer */ +/* sectors Number of sectors to write */ +/* sector_type Type of sector(s) to write */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_utility_logical_sector_flush Flush and invalidate sectors */ +/* that overlap with non-cache */ +/* sector I/O. */ +/* I/O Driver */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), and */ +/* added conditional to */ +/* disable cache, */ +/* resulting in version 6.1 */ +/* 04-02-2021 Bhupendra Naphade Modified comment(s), */ +/* updated check for logical */ +/* sector value, */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_logical_sector_write(FX_MEDIA *media_ptr, ULONG64 logical_sector, + VOID *buffer_ptr, ULONG sectors, UCHAR sector_type) +{ + +#ifndef FX_DISABLE_CACHE +FX_CACHED_SECTOR *cache_entry; +UINT cache_size; +UINT index; +UINT i; +UCHAR cache_found = FX_FALSE; +#endif /* FX_DISABLE_CACHE */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Determine if the request is for FAT sector. */ + if (sector_type == FX_FAT_SECTOR) + { + + /* Increment the number of FAT sector writes. */ + media_ptr -> fx_media_fat_sector_writes++; + } + + /* Increment the number of logical sectors written. */ + media_ptr -> fx_media_logical_sector_writes++; +#endif + + /* Extended port-specific processing macro, which is by default defined to white space. */ + FX_UTILITY_LOGICAL_SECTOR_WRITE_EXTENSION + +#ifndef FX_DISABLE_CACHE + /* Determine if the request is from the internal media buffer area. */ + if ((((UCHAR *)buffer_ptr) >= media_ptr -> fx_media_memory_buffer) && + (((UCHAR *)buffer_ptr) <= media_ptr -> fx_media_sector_cache_end)) + { + + /* Internal cache buffer is requested. */ + + /* Determine if the logical sector cache access should use the hash function. */ + if (media_ptr -> fx_media_sector_cache_hashed) + { + + /* Calculate the area of the cache for this logical sector. */ + index = (ULONG)(logical_sector & media_ptr -> fx_media_sector_cache_hash_mask) * FX_SECTOR_CACHE_DEPTH; + + /* Build a pointer to the cache entry. */ + cache_entry = &(media_ptr -> fx_media_sector_cache[index]); + + for (i = 0; i < FX_SECTOR_CACHE_DEPTH; i++, cache_entry++) + { + + + /* Determine if the logical sector is in the cache - assuming the depth of the + sector cache is 4 entries. */ + if ((cache_entry -> fx_cached_sector_valid) && (cache_entry -> fx_cached_sector == logical_sector)) + { + cache_found = FX_TRUE; + break; + } + } + } + else + { + + /* Search for an entry in the cache that matches this request. */ + cache_size = media_ptr -> fx_media_sector_cache_size; + cache_entry = media_ptr -> fx_media_sector_cache_list_ptr; + + /* Look at the cache entries until a match is found or the end of + the cache is reached. */ + while (cache_size--) + { + + /* Determine if the requested sector has been found. */ + if ((cache_entry -> fx_cached_sector_valid) && (cache_entry -> fx_cached_sector == logical_sector)) + { + cache_found = FX_TRUE; + break; + } + + /* Otherwise, we have not found the cached entry yet. */ + + /* If there are more entries, move to the next one. */ + if (cache_entry -> fx_cached_sector_next_used) + { + + /* Move to the next cache entry. */ + cache_entry = cache_entry -> fx_cached_sector_next_used; + } + } + } + +#ifdef FX_ENABLE_FAULT_TOLERANT + if (media_ptr -> fx_media_fault_tolerant_enabled && + (media_ptr -> fx_media_fault_tolerant_state & FX_FAULT_TOLERANT_STATE_STARTED) && + (sector_type == FX_DATA_SECTOR) && + !(cache_found && (cache_entry -> fx_cached_sector_memory_buffer == buffer_ptr))) + { + + /* Special use case for file write when fault tolerant is enabled. */ + /* Data are read from one sector but write to another sector. */ + /* Need to invalidate both of original and new caches. */ + if (cache_found) + { + + /* Invalidate the new cache. */ + cache_entry -> fx_cached_sector_valid = FX_FALSE; + cache_found = FX_FALSE; + } + + /* Search for original cache. */ + cache_size = media_ptr -> fx_media_sector_cache_size; + cache_entry = media_ptr -> fx_media_sector_cache_list_ptr; + + /* Look at the cache entries until a match is found or the end of + the cache is reached. */ + while (cache_size--) + { + + /* Determine if the original sector has been found. */ + if ((cache_entry -> fx_cached_sector_valid) && + (cache_entry -> fx_cached_sector_memory_buffer == buffer_ptr)) + { + + /* Invalidate the original cache. */ + cache_entry -> fx_cached_sector_valid = FX_FALSE; + break; + } + + /* Otherwise, we have not found the cached entry yet. */ + + /* If there are more entries, move to the next one. */ + if (cache_entry -> fx_cached_sector_next_used) + { + + /* Move to the next cache entry. */ + cache_entry = cache_entry -> fx_cached_sector_next_used; + } + } + } +#endif /* FX_ENABLE_FAULT_TOLERANT */ + + if (cache_found) + { + + /* Yes, we found a match. */ + +#ifdef FX_FAULT_TOLERANT + + /* Check for a system sector. Data sector fault tolerance is selected with + the FX_FAULT_TOLERANT_DATA option. */ + if (sector_type != FX_DATA_SECTOR) + { + + /* With the fault tolerant option enabled, system sectors are written immediately to + the media. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = cache_entry -> fx_cached_sector_memory_buffer; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = logical_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector; +#endif + media_ptr -> fx_media_driver_sectors = 1; + media_ptr -> fx_media_driver_sector_type = sector_type; + + /* Yes, a system sector write is present so set the flag. The driver + can use this flag to make extra safeguards in writing the sector + out, yielding more fault tolerance. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, logical_sector, 1, cache_entry -> fx_cached_sector_memory_buffer, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector(s). */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Return success. */ + return(media_ptr -> fx_media_driver_status); + } +#endif + + /* Determine if this is the first write of this logical sector. */ + if (cache_entry -> fx_cached_sector_buffer_dirty == FX_FALSE) + { + + /* Yes, increment the number of outstanding dirty sectors. */ + media_ptr -> fx_media_sector_cache_dirty_count++; + + /* Simply mark this entry as dirty. */ + cache_entry -> fx_cached_sector_buffer_dirty = FX_TRUE; + } + + /* Don't bother updating the cache linked list since writes are + preceded by reads anyway. */ + + /* Success, return to caller immediately! */ + return(FX_SUCCESS); + } + + + /* Okay, so if we are here the request must be for the additional FAT writes, since this is the + only time a write request is made without a preceding read request. */ + + /* Is the logical sector valid? */ + if ((logical_sector == 0) || (logical_sector == ((ULONG)0xFFFFFFFF))) + { + return(FX_SECTOR_INVALID); + } + + /* Compare logical sector against total sectors to make sure it is valid. */ + if ((logical_sector + sectors - 1) >= media_ptr -> fx_media_total_sectors) + { + return(FX_SECTOR_INVALID); + } + + /* Just write the buffer to the media. */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build write request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = buffer_ptr; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = logical_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector; +#endif + media_ptr -> fx_media_driver_sectors = sectors; + media_ptr -> fx_media_driver_sector_type = sector_type; + + /* Determine if the system write flag needs to be set. */ + if (sector_type != FX_DATA_SECTOR) + { + + /* Yes, a system sector write is present so set the flag. The driver + can use this flag to make extra safeguards in writing the sector + out, yielding more fault tolerance. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, logical_sector, sectors, buffer_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector(s). */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Check for successful completion. */ + if (media_ptr -> fx_media_driver_status) + { + + /* Error writing a internal sector out. Return the + error status. */ + return(media_ptr -> fx_media_driver_status); + } + + /* At this point, we have a successful write. */ + return(FX_SUCCESS); + } + else +#endif /* FX_DISABLE_CACHE */ + { + + /* Otherwise, the write request is being made directly from an application + buffer. Determine if the logical sector is valid. */ + + /* Is the logical sector valid? */ + if ((logical_sector == 0) || (logical_sector == ((ULONG)0xFFFFFFFF))) + { + return(FX_SECTOR_INVALID); + } + + /* Compare logical sector against total sectors to make sure it is valid. */ + if ((logical_sector + sectors - 1) >= media_ptr -> fx_media_total_sectors) + { + return(FX_SECTOR_INVALID); + } + + /* Flush and invalidate for any entries in the cache that are in this direct I/O read request range. */ + _fx_utility_logical_sector_flush(media_ptr, logical_sector, (ULONG64) sectors, FX_TRUE); + +#ifdef FX_DISABLE_CACHE + if ((logical_sector <= media_ptr -> fx_media_memory_buffer_sector) && (logical_sector + sectors >= media_ptr -> fx_media_memory_buffer_sector)) + { + media_ptr -> fx_media_memory_buffer_sector = (ULONG64)-1; + } +#endif /* FX_DISABLE_CACHE */ + +#ifndef FX_MEDIA_STATISTICS_DISABLE + + /* Increment the number of driver write sector(s) requests. */ + media_ptr -> fx_media_driver_write_requests++; +#endif + + /* Build request to the driver. */ + media_ptr -> fx_media_driver_request = FX_DRIVER_WRITE; + media_ptr -> fx_media_driver_status = FX_IO_ERROR; + media_ptr -> fx_media_driver_buffer = buffer_ptr; +#ifdef FX_DRIVER_USE_64BIT_LBA + media_ptr -> fx_media_driver_logical_sector = logical_sector; +#else + media_ptr -> fx_media_driver_logical_sector = (ULONG)logical_sector; +#endif + media_ptr -> fx_media_driver_sectors = sectors; + media_ptr -> fx_media_driver_sector_type = sector_type; + + /* Determine if the system write flag needs to be set. */ + if (sector_type != FX_DATA_SECTOR) + { + + /* Yes, a system sector write is present so set the flag. The driver + can use this flag to make extra safeguards in writing the sector + out, yielding more fault tolerance. */ + media_ptr -> fx_media_driver_system_write = FX_TRUE; + } + + /* If trace is enabled, insert this event into the trace buffer. */ + FX_TRACE_IN_LINE_INSERT(FX_TRACE_INTERNAL_IO_DRIVER_WRITE, media_ptr, logical_sector, sectors, buffer_ptr, FX_TRACE_INTERNAL_EVENTS, 0, 0) + + /* Invoke the driver to write the sector(s). */ + (media_ptr -> fx_media_driver_entry) (media_ptr); + + /* Clear the system write flag. */ + media_ptr -> fx_media_driver_system_write = FX_FALSE; + + /* Return driver status. */ + return(media_ptr -> fx_media_driver_status); + } +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_memory_copy.c b/src/Middlewares/ST/filex/common/src/fx_utility_memory_copy.c new file mode 100644 index 00000000..5fef3c00 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_memory_copy.c @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" +#include "string.h" + + +/* Remove any previous remapping for memory copy when compiling this + module. */ + +#undef _fx_utility_memory_copy + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_memory_copy PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function copies the specified number of bytes from the source */ +/* to the destination. */ +/* */ +/* INPUT */ +/* */ +/* source_ptr Source memory pointer */ +/* dest_ptr Destination memory pointer */ +/* size number of bytes to copy */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), verified */ +/* memcpy usage, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _fx_utility_memory_copy(UCHAR *source_ptr, UCHAR *dest_ptr, ULONG size) +{ + + /* Copy the memory. */ + memcpy(dest_ptr, source_ptr, size); /* Use case of memcpy is verified. */ +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_memory_set.c b/src/Middlewares/ST/filex/common/src/fx_utility_memory_set.c new file mode 100644 index 00000000..1967925d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_memory_set.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_utility.h" +#include "string.h" + + +/* Remove any previous remapping for memory copy when compiling this + module. */ + +#undef _fx_utility_memory_set + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_memory_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function copies the specified number of bytes from the source */ +/* to the destination. */ +/* */ +/* INPUT */ +/* */ +/* dest_ptr Destination memory pointer */ +/* value Value to fill */ +/* size Number of bytes to set */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* FileX System Functions */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _fx_utility_memory_set(UCHAR *dest_ptr, UCHAR value, ULONG size) +{ + + /* Loop to set memory. */ + while (size--) + { + + /* Set byte. */ + *dest_ptr++ = value; + } +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_string_length_get.c b/src/Middlewares/ST/filex/common/src/fx_utility_string_length_get.c new file mode 100644 index 00000000..9ca24e09 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_string_length_get.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_string_length_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns length of string up to the maximum length. */ +/* */ +/* INPUT */ +/* */ +/* string Pointer to string */ +/* max_length Maximum length which can be */ +/* returned by function */ +/* */ +/* OUTPUT */ +/* */ +/* return length of string */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_directory_exFAT_unicode_entry_write */ +/* _fx_directory_exFAT_free_search */ +/* _fx_utility_absolute_path_get Get absolute path */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_string_length_get(CHAR *string, UINT max_length) +{ + +UINT length; + + /* Initialize length to 0. */ + length = 0; + + /* Loop to calculate the length. */ + while (string[length] && (length < max_length)) + { + + /* Increment the length (index). */ + length++; + } + + /* Return length. */ + return(length); +} + diff --git a/src/Middlewares/ST/filex/common/src/fx_utility_token_length_get.c b/src/Middlewares/ST/filex/common/src/fx_utility_token_length_get.c new file mode 100644 index 00000000..67f25eff --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fx_utility_token_length_get.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#ifdef FX_ENABLE_EXFAT +#include "fx_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fx_utility_token_length_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the length of the next part of the file */ +/* name. */ +/* */ +/* INPUT */ +/* */ +/* path Base (current) path */ +/* */ +/* OUTPUT */ +/* */ +/* length Length of the string */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* _fx_utility_absolute_path_get Get absolute path */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fx_utility_token_length_get(CHAR *path) +{ + +UINT length; + + + /* Initialize the length to 0. */ + length = 0; + + /* Walk to the next sub-directory break. */ + while (path[length] && (path[length] != '\\') && (path[length] != '/') && (length < FX_MAXIMUM_PATH)) + { + + /* Increment length (index). */ + length++; + } + + /* Return length. */ + return(length); +} + +#endif + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c b/src/Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c new file mode 100644 index 00000000..b5f191e5 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_attributes_read.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_attributes_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory attributes read */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name pointer */ +/* attributes_ptr Return attributes pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_attributes_read Actual read directory */ +/* attributes service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_attributes_read(FX_MEDIA *media_ptr, CHAR *directory_name, UINT *attributes_ptr) +{ + +UINT status; + + /* Check for a null media or attributes pointer. */ + if ((media_ptr == FX_NULL) || (attributes_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual read file attributes service. */ + status = _fx_directory_attributes_read(media_ptr, directory_name, attributes_ptr); + + /* File attribute read is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c b/src/Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c new file mode 100644 index 00000000..c8872de0 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_attributes_set.c @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_attributes_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory attribute set */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name pointer */ +/* attributes New file attributes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_attributes_set Actual directory attributes */ +/* set service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_attributes_set(FX_MEDIA *media_ptr, CHAR *directory_name, UINT attributes) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for invalid attributes. */ + if ((INT)attributes & ~(FX_DIRECTORY | FX_READ_ONLY | FX_HIDDEN | FX_SYSTEM | FX_ARCHIVE)) + { + return(FX_INVALID_ATTR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual set attributes service. */ + status = _fx_directory_attributes_set(media_ptr, directory_name, attributes); + + /* File attribute set is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_create.c b/src/Middlewares/ST/filex/common/src/fxe_directory_create.c new file mode 100644 index 00000000..c6146834 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_create.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory create call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_create Actual directory create call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_create(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual directory create service. */ + status = _fx_directory_create(media_ptr, directory_name); + + /* Directory create is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_default_get.c b/src/Middlewares/ST/filex/common/src/fxe_directory_default_get.c new file mode 100644 index 00000000..e05a9da8 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_default_get.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_default_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory default get call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* return_path_name Destination string pointer */ +/* address */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_default_get Actual default directory get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_default_get(FX_MEDIA *media_ptr, CHAR **return_path_name) +{ + +UINT status; + + + /* Check for a null media pointer or null destination for the default path. */ + if ((media_ptr == FX_NULL) || (return_path_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual default directory get service. */ + status = _fx_directory_default_get(media_ptr, return_path_name); + + /* Return default directory get status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c b/src/Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c new file mode 100644 index 00000000..35016201 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_default_get_copy.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_default_get_copy PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory default get copy */ +/* call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* return_path_name_buffer Destination buffer for name */ +/* return_path_name_buffer_size Size of buffer pointed to by */ +/* return_path_name_buffer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_default_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size) +{ + +UINT status; + + + /* Check for a null media pointer or name buffer pointer. */ + if ((media_ptr == FX_NULL) || (return_path_name_buffer == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual default directory get copy service. */ + status = _fx_directory_default_get_copy(media_ptr, return_path_name_buffer, return_path_name_buffer_size); + + /* Return successful status. */ + return(status); +} diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_default_set.c b/src/Middlewares/ST/filex/common/src/fxe_directory_default_set.c new file mode 100644 index 00000000..212dc960 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_default_set.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_default_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the default directory set call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* new_path_name New path to set current */ +/* working directory to */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_default_set Actual default directory set */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_default_set(FX_MEDIA *media_ptr, CHAR *new_path_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual default directory set service. */ + status = _fx_directory_default_set(media_ptr, new_path_name); + + /* Default directory set is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_delete.c b/src/Middlewares/ST/filex/common/src/fxe_directory_delete.c new file mode 100644 index 00000000..3b65e00b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_delete.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory delete call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name to delete */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_delete Actual directory delete call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_delete(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual directory delete service. */ + status = _fx_directory_delete(media_ptr, directory_name); + + /* Directory delete is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c b/src/Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c new file mode 100644 index 00000000..5815015d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_first_entry_find.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_first_entry_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory find first call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Destination for directory */ +/* name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_first_entry_find Actual first find service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_first_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual directory find first service. */ + status = _fx_directory_first_entry_find(media_ptr, directory_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c b/src/Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c new file mode 100644 index 00000000..14c1994b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_first_full_entry_find.c @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_first_full_entry_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory find first full */ +/* entry call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Destination for directory */ +/* name */ +/* attributes Destination for attributes */ +/* size Destination for size */ +/* year Destination for year */ +/* month Destination for month */ +/* day Destination for day */ +/* hour Destination for hour */ +/* minute Destination for minute */ +/* second Destination for second */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_first_full_entry_find Actual first find service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_first_full_entry_find(FX_MEDIA *media_ptr, + CHAR *directory_name, UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual directory find first full entry service. */ + status = _fx_directory_first_full_entry_find(media_ptr, directory_name, + attributes, size, year, month, day, hour, minute, second); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_information_get.c b/src/Middlewares/ST/filex/common/src/fxe_directory_information_get.c new file mode 100644 index 00000000..eed4c2e3 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_information_get.c @@ -0,0 +1,111 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_information_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory information */ +/* get call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name pointer */ +/* attributes Pointer to attributes */ +/* size Pointer to size */ +/* year Pointer to year */ +/* month Pointer to month */ +/* day Pointer to day */ +/* hour Pointer to hour */ +/* minute Pointer to minute */ +/* second Pointer to second */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_information_get Actual directory information */ +/* get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_information_get(FX_MEDIA *media_ptr, CHAR *directory_name, + UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, + UINT *hour, UINT *minute, UINT *second) +{ + +UINT status; + + + /* Check for a null media pointer or all null return parameter pointers. */ + if ((media_ptr == FX_NULL) || + ((attributes == FX_NULL) && (size == FX_NULL) && (year == FX_NULL) && (month == FX_NULL) && + (day == FX_NULL) && (hour == FX_NULL) && (minute == FX_NULL) && (second == FX_NULL))) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual directory information get service. */ + status = _fx_directory_information_get(media_ptr, directory_name, attributes, size, + year, month, day, hour, minute, second); + + /* Directory information get is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c new file mode 100644 index 00000000..b61b225e --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_clear.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_local_path_clear PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the local path clear call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_local_path_set Actual core service call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_local_path_clear(FX_MEDIA *media_ptr) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Call actual local path clear service. */ + status = _fx_directory_local_path_clear(media_ptr); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c new file mode 100644 index 00000000..683f5a47 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_get.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_local_path_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the local path get call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* return_path_name Return local path name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_local_path_get Actual core service call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_local_path_get(FX_MEDIA *media_ptr, CHAR **return_path_name) +{ + +UINT status; + + + /* Check for a null media pointer or null destination for the default path. */ + if ((media_ptr == FX_NULL) || (return_path_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Call actual local path get service. */ + status = _fx_directory_local_path_get(media_ptr, return_path_name); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c new file mode 100644 index 00000000..0e0229f9 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_get_copy.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_local_path_get_copy PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the local path get copy call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* return_path_name_buffer Destination buffer for name */ +/* return_path_name_buffer_size Size of buffer pointed to by */ +/* return_path_name_buffer */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_local_path_get_copy(FX_MEDIA *media_ptr, CHAR *return_path_name_buffer, UINT return_path_name_buffer_size) +{ + +UINT status; + + + /* Check for a null media pointer or name buffer pointer. */ + if ((media_ptr == FX_NULL) || (return_path_name_buffer == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual default directory get copy service. */ + status = _fx_directory_local_path_get_copy(media_ptr, return_path_name_buffer, return_path_name_buffer_size); + + /* Return successful status. */ + return(status); +} diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c new file mode 100644 index 00000000..e9361b8b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_restore.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_local_path_restore PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the local path restore call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* local_path_ptr Local path control block ptr */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fxe_directory_local_path_restore Actual core service call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_local_path_restore(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr) +{ + +UINT status; + + + /* Check for a null media pointer or a null local path. */ + if ((media_ptr == FX_NULL) || (local_path_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Call actual local path restore service. */ + status = _fx_directory_local_path_restore(media_ptr, local_path_ptr); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c new file mode 100644 index 00000000..c0105013 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_local_path_set.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" +#include "fx_file.h" +#include "fx_utility.h" +#include "fx_directory.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_local_path_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the local path set call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* local_path_ptr Local path control block ptr */ +/* new_path_name New path to set current local */ +/* working directory to */ +/* local_path_control_block_size Size of the FX_LOCAL_PATH */ +/* structure */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_local_path_set Actual core service call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_local_path_set(FX_MEDIA *media_ptr, FX_LOCAL_PATH *local_path_ptr, CHAR *new_path_name, UINT local_path_control_block_size) +{ + +UINT status; + + + /* Check for a null media pointer or null local path. */ + if ((media_ptr == FX_NULL) || (local_path_ptr == FX_NULL) || (local_path_control_block_size != sizeof(FX_LOCAL_PATH))) + { + return(FX_PTR_ERROR); + } + + /* Call actual local path set service. */ + status = _fx_directory_local_path_set(media_ptr, local_path_ptr, new_path_name); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c b/src/Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c new file mode 100644 index 00000000..b9ccee43 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_long_name_get.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_long_name_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the long name get service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* short_file_name Pointer to short (8.3) name */ +/* long_file_name Pointer to long (max 255) name*/ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_long_name_get Actual long name get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_long_name_get(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name) +{ + +UINT status; + + + /* Check for a NULL media or file name pointer. */ + if ((media_ptr == FX_NULL) || (short_file_name == FX_NULL) || (long_file_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual long name get service. */ + status = _fx_directory_long_name_get(media_ptr, short_file_name, long_file_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c b/src/Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c new file mode 100644 index 00000000..533ca139 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_long_name_get_extended.c @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_long_name_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the long name get service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* short_file_name Pointer to short (8.3) name */ +/* long_file_name Pointer to long (max 255) name*/ +/* long_file_name_buffer_length Buffer length for long name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_long_name_get_extended Actual long name get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_long_name_get_extended(FX_MEDIA *media_ptr, CHAR *short_file_name, CHAR *long_file_name, UINT long_file_name_buffer_length) +{ + +UINT status; + + + /* Check for a NULL media or file name pointer. */ + if ((media_ptr == FX_NULL) || (short_file_name == FX_NULL) || (long_file_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for zero length buffer. */ + if (long_file_name_buffer_length == 0) + { + return(FX_BUFFER_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual long name get service. */ + status = _fx_directory_long_name_get_extended(media_ptr, short_file_name, long_file_name, long_file_name_buffer_length); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_name_test.c b/src/Middlewares/ST/filex/common/src/fxe_directory_name_test.c new file mode 100644 index 00000000..8fe633eb --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_name_test.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_name_test PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory name test call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Directory name pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_name_test Actual directory name test */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_name_test(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual directory name test service. */ + status = _fx_directory_name_test(media_ptr, directory_name); + + /* Directory name test is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c b/src/Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c new file mode 100644 index 00000000..7e68a761 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_next_entry_find.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_next_entry_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks the next directory entry find call for errors. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Destination for directory */ +/* name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_next_entry_find Actual entry find service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_next_entry_find(FX_MEDIA *media_ptr, CHAR *directory_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual next directory entry find service. */ + status = _fx_directory_next_entry_find(media_ptr, directory_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c b/src/Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c new file mode 100644 index 00000000..a9abd187 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_next_full_entry_find.c @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_next_full_entry_find PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks the next directory full entry find call for */ +/* errors. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* directory_name Destination for directory */ +/* name */ +/* attributes Destination for attributes */ +/* size Destination for size */ +/* year Destination for year */ +/* month Destination for month */ +/* day Destination for day */ +/* hour Destination for hour */ +/* minute Destination for minute */ +/* second Destination for second */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_next_full_entry_find Actual full entry find service*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_next_full_entry_find(FX_MEDIA *media_ptr, + CHAR *directory_name, UINT *attributes, ULONG *size, + UINT *year, UINT *month, UINT *day, UINT *hour, UINT *minute, UINT *second) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual next directory full entry find service. */ + status = _fx_directory_next_full_entry_find(media_ptr, directory_name, + attributes, size, year, month, day, hour, minute, second); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_rename.c b/src/Middlewares/ST/filex/common/src/fxe_directory_rename.c new file mode 100644 index 00000000..704e9337 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_rename.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_rename PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the directory rename call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* old_directory_name Old file directory pointer */ +/* new_directory_name New file directory pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_rename Actual directory rename call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_rename(FX_MEDIA *media_ptr, CHAR *old_directory_name, CHAR *new_directory_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual directory rename service. */ + status = _fx_directory_rename(media_ptr, old_directory_name, new_directory_name); + + /* Directory rename is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c b/src/Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c new file mode 100644 index 00000000..68bc999d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_short_name_get.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_short_name_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the short name get service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* long_file_name Pointer to long (max 255) name*/ +/* short_file_name Pointer to short (8.3) name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_short_name_get Actual short name get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_short_name_get(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name) +{ + +UINT status; + + + /* Check for a NULL media or file name pointer. */ + if ((media_ptr == FX_NULL) || (short_file_name == FX_NULL) || (long_file_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual short name get service. */ + status = _fx_directory_short_name_get(media_ptr, long_file_name, short_file_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c b/src/Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c new file mode 100644 index 00000000..a1708d21 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_directory_short_name_get_extended.c @@ -0,0 +1,104 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Directory */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_directory.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_directory_short_name_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the short name get service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* long_file_name Pointer to long (max 255) name*/ +/* short_file_name Pointer to short (8.3) name */ +/* short_file_name_length Buffer length for short name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_short_name_get_extended Actual short name get service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_directory_short_name_get_extended(FX_MEDIA *media_ptr, CHAR *long_file_name, CHAR *short_file_name, UINT short_file_name_length) +{ + +UINT status; + + + /* Check for a NULL media or file name pointer. */ + if ((media_ptr == FX_NULL) || (short_file_name == FX_NULL) || (long_file_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for zero length buffer. */ + if (short_file_name_length == 0) + { + return(FX_BUFFER_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual short name get service. */ + status = _fx_directory_short_name_get_extended(media_ptr, long_file_name, short_file_name, short_file_name_length); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c b/src/Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c new file mode 100644 index 00000000..10113842 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_fault_tolerant_enable.c @@ -0,0 +1,99 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Fault Tolerant */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#ifdef FX_ENABLE_FAULT_TOLERANT +#include "fx_fault_tolerant.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_fault_tolerant_enable PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the fault tolerant enable call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* memory_buffer Pointer to memory buffer. */ +/* memory_size Size of memory buffer. It must*/ +/* be one sector. */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_fault_tolerant_enable Actual enable service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_fault_tolerant_enable(FX_MEDIA *media_ptr, VOID *memory_buffer, UINT memory_size) +{ + +UINT status; + + + /* Check for a null media pointer or buffer pointer. */ + if ((media_ptr == FX_NULL) || (memory_buffer == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual fault tolerant enable service. */ + status = _fx_fault_tolerant_enable(media_ptr, memory_buffer, memory_size); + + /* Return status to the caller. */ + return(status); +} +#endif /* FX_ENABLE_FAULT_TOLERANT */ + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_allocate.c b/src/Middlewares/ST/filex/common/src/fxe_file_allocate.c new file mode 100644 index 00000000..34a69d99 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_allocate.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_allocate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file allocate service. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size Number of bytes to allocate */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_allocate Actual file allocate service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_allocate(FX_FILE *file_ptr, ULONG size) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file allocate service. */ + status = _fx_file_allocate(file_ptr, size); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_attributes_read.c b/src/Middlewares/ST/filex/common/src/fxe_file_attributes_read.c new file mode 100644 index 00000000..09ee1dd1 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_attributes_read.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_attributes_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file attributes read call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name pointer */ +/* attributes_ptr Return attributes pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_attributes_read Actual read file attributes */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_attributes_read(FX_MEDIA *media_ptr, CHAR *file_name, UINT *attributes_ptr) +{ + +UINT status; + + /* Check for a null media or attributes pointer. */ + if ((media_ptr == FX_NULL) || (attributes_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual read file attributes service. */ + status = _fx_file_attributes_read(media_ptr, file_name, attributes_ptr); + + /* File attribute read is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_attributes_set.c b/src/Middlewares/ST/filex/common/src/fxe_file_attributes_set.c new file mode 100644 index 00000000..6756330b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_attributes_set.c @@ -0,0 +1,103 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_attributes_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file attribute set call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name pointer */ +/* attributes New file attributes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_attributes_set Actual file attributes set */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_attributes_set(FX_MEDIA *media_ptr, CHAR *file_name, UINT attributes) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for invalid attributes. */ + if ((INT)attributes & ~(FX_READ_ONLY | FX_HIDDEN | FX_SYSTEM | FX_ARCHIVE)) + { + return(FX_INVALID_ATTR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual set attributes service. */ + status = _fx_file_attributes_set(media_ptr, file_name, attributes); + + /* File attribute set is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c b/src/Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c new file mode 100644 index 00000000..49f17bd1 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_best_effort_allocate.c @@ -0,0 +1,98 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_best_effort_allocate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file best effort allocate */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size Number of bytes to allocate */ +/* actual_size_allocated Number of bytes allocated */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_best_effort_allocate Actual best effort file */ +/* allocate service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_best_effort_allocate(FX_FILE *file_ptr, ULONG size, ULONG *actual_size_allocated) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if ((file_ptr == FX_NULL) || (actual_size_allocated == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual best effort file allocate service. */ + status = _fx_file_best_effort_allocate(file_ptr, size, actual_size_allocated); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_close.c b/src/Middlewares/ST/filex/common/src/fxe_file_close.c new file mode 100644 index 00000000..56485b26 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_close.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_close PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the close file call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_close Actual file close service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_close(FX_FILE *file_ptr) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file close service. */ + status = _fx_file_close(file_ptr); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_create.c b/src/Middlewares/ST/filex/common/src/fxe_file_create.c new file mode 100644 index 00000000..0c7211cc --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_create.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file create call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_create Actual file create call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_create(FX_MEDIA *media_ptr, CHAR *file_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file create service. */ + status = _fx_file_create(media_ptr, file_name); + + /* File create is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_date_time_set.c b/src/Middlewares/ST/filex/common/src/fxe_file_date_time_set.c new file mode 100644 index 00000000..f6c4a425 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_date_time_set.c @@ -0,0 +1,293 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_date_time_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file date/time set service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name pointer */ +/* year Year */ +/* month Month */ +/* day Day */ +/* hour Hour */ +/* minute Minute */ +/* second Second */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_date_time_set Actual file date/time set */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_date_time_set(FX_MEDIA *media_ptr, CHAR *file_name, + UINT year, UINT month, UINT day, UINT hour, UINT minute, UINT second) +{ + +UINT status; + + + /* Check for a NULL media or file name pointer. */ + if ((media_ptr == FX_NULL) || (file_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for invalid year. */ + if ((year < FX_BASE_YEAR) || (year > FX_MAXIMUM_YEAR)) + { + return(FX_INVALID_YEAR); + } + + /* Check for invalid day. */ + if (day < 1) + { + return(FX_INVALID_DAY); + } + + /* Check for invalid day. */ + switch (month) + { + + case 1: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 2: + { + + /* Check for leap year. */ + if ((year % 4) == 0) + { + + /* Leap year, February has 29 days. */ + if (day > 29) + { + return(FX_INVALID_DAY); + } + } + else + { + + /* Otherwise, non-leap year. February has + 28 days. */ + if (day > 28) + { + return(FX_INVALID_DAY); + } + } + break; + } + + case 3: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 4: + { + + /* Check for 30 days. */ + if (day > 30) + { + return(FX_INVALID_DAY); + } + break; + } + + case 5: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 6: + { + + /* Check for 30 days. */ + if (day > 30) + { + return(FX_INVALID_DAY); + } + break; + } + + case 7: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 8: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 9: + { + + /* Check for 30 days. */ + if (day > 30) + { + return(FX_INVALID_DAY); + } + break; + } + + case 10: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 11: + { + + /* Check for 30 days. */ + if (day > 30) + { + return(FX_INVALID_DAY); + } + break; + } + + case 12: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + default: + + /* Invalid month. */ + return(FX_INVALID_MONTH); + } + + /* Check for invalid hour. */ + if (hour > FX_MAXIMUM_HOUR) + { + return(FX_INVALID_HOUR); + } + + /* Check for invalid minute. */ + if (minute > FX_MAXIMUM_MINUTE) + { + return(FX_INVALID_MINUTE); + } + + /* Check for invalid second. */ + if (second > FX_MAXIMUM_SECOND) + { + return(FX_INVALID_SECOND); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file date/time set service. */ + status = _fx_file_date_time_set(media_ptr, file_name, + year, month, day, + hour, minute, second); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_delete.c b/src/Middlewares/ST/filex/common/src/fxe_file_delete.c new file mode 100644 index 00000000..b6d6b97b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_delete.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file delete call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_name File name pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_delete Actual file delete service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_delete(FX_MEDIA *media_ptr, CHAR *file_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file delete service. */ + status = _fx_file_delete(media_ptr, file_name); + + /* File delete is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c b/src/Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c new file mode 100644 index 00000000..440b9b0f --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_extended_allocate.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_extended_allocate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file allocate service. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size Number of bytes to allocate */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_allocate Actual file allocate service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_extended_allocate(FX_FILE *file_ptr, ULONG64 size) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file allocate service. */ + status = _fx_file_extended_allocate(file_ptr, size); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c b/src/Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c new file mode 100644 index 00000000..cdb5dcf5 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_extended_best_effort_allocate.c @@ -0,0 +1,98 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_extended_best_effort_allocate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file best effort allocate */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size Number of bytes to allocate */ +/* actual_size_allocated Number of bytes allocated */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_best_effort_allocate Actual best effort file */ +/* allocate service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_extended_best_effort_allocate(FX_FILE *file_ptr, ULONG64 size, ULONG64 *actual_size_allocated) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if ((file_ptr == FX_NULL) || (actual_size_allocated == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual best effort file allocate service. */ + status = _fx_file_extended_best_effort_allocate(file_ptr, size, actual_size_allocated); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c b/src/Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c new file mode 100644 index 00000000..1b34f7e6 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_extended_relative_seek.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_extended_relative_seek PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file relative seek call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* byte_offset Byte offset of the seek */ +/* seek_from Direction for relative seek, */ +/* legal values are: */ +/* */ +/* FX_SEEK_BEGIN */ +/* FX_SEEK_END */ +/* FX_SEEK_FORWARD */ +/* FX_SEEK_BACK */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_relative_seek Actual relative file seek */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_extended_relative_seek(FX_FILE *file_ptr, ULONG64 byte_offset, UINT seek_from) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for valid seek from option. */ + if ((seek_from != FX_SEEK_BEGIN) && (seek_from != FX_SEEK_END) && + (seek_from != FX_SEEK_FORWARD) && (seek_from != FX_SEEK_BACK)) + { + return(FX_INVALID_OPTION); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file relative seek service. */ + status = _fx_file_extended_relative_seek(file_ptr, byte_offset, seek_from); + + /* Seek is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_extended_seek.c b/src/Middlewares/ST/filex/common/src/fxe_file_extended_seek.c new file mode 100644 index 00000000..126d4c02 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_extended_seek.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_extended_seek PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file seek call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* byte_offset Byte offset into the file */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_seek Actual file seek service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_extended_seek(FX_FILE *file_ptr, ULONG64 byte_offset) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file seek service. */ + status = _fx_file_extended_seek(file_ptr, byte_offset); + + /* Seek is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c b/src/Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c new file mode 100644 index 00000000..479f9017 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_extended_truncate.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_extended_truncate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file truncate call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size New size of the file in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_truncate Actual file truncate service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_extended_truncate(FX_FILE *file_ptr, ULONG64 size) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file truncate service. */ + status = _fx_file_extended_truncate(file_ptr, size); + + /* Truncate is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c b/src/Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c new file mode 100644 index 00000000..04337757 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_extended_truncate_release.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_extended_truncate_release PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file truncate release call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size New size of the file in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_extended_truncate_release Actual file truncate release */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_extended_truncate_release(FX_FILE *file_ptr, ULONG64 size) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file truncate release service. */ + status = _fx_file_extended_truncate_release(file_ptr, size); + + /* Truncate is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_open.c b/src/Middlewares/ST/filex/common/src/fxe_file_open.c new file mode 100644 index 00000000..b4a5a393 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_open.c @@ -0,0 +1,137 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_open PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file open call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* file_ptr File control block pointer */ +/* file_name Name pointer */ +/* open_type Type of open requested */ +/* file_control_block_size Size of FX_FILE structure */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_open Actual open file service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_open(FX_MEDIA *media_ptr, FX_FILE *file_ptr, CHAR *file_name, UINT open_type, UINT file_control_block_size) +{ + +UINT status; +FX_FILE *current_file; +ULONG open_count; + + + /* Check for a null media or file pointer. */ + if ((media_ptr == FX_NULL) || (media_ptr -> fx_media_id != FX_MEDIA_ID) || (file_ptr == FX_NULL) || (file_control_block_size != sizeof(FX_FILE))) + { + return(FX_PTR_ERROR); + } + + /* Check for an invalid open type. */ + if ((open_type != FX_OPEN_FOR_READ) && (open_type != FX_OPEN_FOR_READ_FAST) && (open_type != FX_OPEN_FOR_WRITE)) + { + return(FX_ACCESS_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Get protection. */ + FX_PROTECT + + /* Check for a duplicate file open. */ + + /* Loop to search the list for the same file handle. */ + current_file = media_ptr -> fx_media_opened_file_list; + open_count = media_ptr -> fx_media_opened_file_count; + + while (open_count--) + { + + /* See if a match exists. */ + if (file_ptr == current_file) + { + + /* Release protection. */ + FX_UNPROTECT + + /* Return error. */ + return(FX_PTR_ERROR); + } + + /* Move to the next opened file. */ + current_file = current_file -> fx_file_opened_next; + } + + /* Release protection. */ + FX_UNPROTECT + + /* Call actual file open service. */ + status = _fx_file_open(media_ptr, file_ptr, file_name, open_type); + + /* Open is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_read.c b/src/Middlewares/ST/filex/common/src/fxe_file_read.c new file mode 100644 index 00000000..b28a8557 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_read.c @@ -0,0 +1,98 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the read file call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* buffer_ptr Buffer pointer */ +/* request_size Number of bytes requested */ +/* actual_size Pointer to variable for the */ +/* number of bytes read */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_read Actual file read service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_read(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG request_size, ULONG *actual_size) +{ + +UINT status; + + + /* Check for a null file or buffer pointer. */ + if ((file_ptr == FX_NULL) || (buffer_ptr == FX_NULL) || (actual_size == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file read service. */ + status = _fx_file_read(file_ptr, buffer_ptr, request_size, actual_size); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_relative_seek.c b/src/Middlewares/ST/filex/common/src/fxe_file_relative_seek.c new file mode 100644 index 00000000..d01edca7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_relative_seek.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_relative_seek PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file relative seek call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* byte_offset Byte offset of the seek */ +/* seek_from Direction for relative seek, */ +/* legal values are: */ +/* */ +/* FX_SEEK_BEGIN */ +/* FX_SEEK_END */ +/* FX_SEEK_FORWARD */ +/* FX_SEEK_BACK */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_relative_seek Actual relative file seek */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_relative_seek(FX_FILE *file_ptr, ULONG byte_offset, UINT seek_from) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for valid seek from option. */ + if ((seek_from != FX_SEEK_BEGIN) && (seek_from != FX_SEEK_END) && + (seek_from != FX_SEEK_FORWARD) && (seek_from != FX_SEEK_BACK)) + { + return(FX_INVALID_OPTION); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file relative seek service. */ + status = _fx_file_relative_seek(file_ptr, byte_offset, seek_from); + + /* Seek is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_rename.c b/src/Middlewares/ST/filex/common/src/fxe_file_rename.c new file mode 100644 index 00000000..60a9716a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_rename.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_rename PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file rename call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* old_file_name Old file name pointer */ +/* new_file_name New file name pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_rename Actual file rename service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_rename(FX_MEDIA *media_ptr, CHAR *old_file_name, CHAR *new_file_name) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file rename service. */ + status = _fx_file_rename(media_ptr, old_file_name, new_file_name); + + /* File rename is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_seek.c b/src/Middlewares/ST/filex/common/src/fxe_file_seek.c new file mode 100644 index 00000000..4b8c7908 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_seek.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_seek PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file seek call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* byte_offset Byte offset into the file */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_seek Actual file seek service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_seek(FX_FILE *file_ptr, ULONG byte_offset) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file seek service. */ + status = _fx_file_seek(file_ptr, byte_offset); + + /* Seek is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_truncate.c b/src/Middlewares/ST/filex/common/src/fxe_file_truncate.c new file mode 100644 index 00000000..3dbf1a81 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_truncate.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_truncate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file truncate call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size New size of the file in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_truncate Actual file truncate service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_truncate(FX_FILE *file_ptr, ULONG size) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file truncate service. */ + status = _fx_file_truncate(file_ptr, size); + + /* Truncate is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_truncate_release.c b/src/Middlewares/ST/filex/common/src/fxe_file_truncate_release.c new file mode 100644 index 00000000..b7e46af9 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_truncate_release.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_truncate_release PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file truncate release call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* size New size of the file in bytes */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_truncate_release Actual file truncate release */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_truncate_release(FX_FILE *file_ptr, ULONG size) +{ + +UINT status; + + + /* Check for a null file pointer. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file truncate release service. */ + status = _fx_file_truncate_release(file_ptr, size); + + /* Truncate is complete, return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_write.c b/src/Middlewares/ST/filex/common/src/fxe_file_write.c new file mode 100644 index 00000000..7bb0aead --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_write.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file write call. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* buffer_ptr Buffer pointer */ +/* size Number of bytes to write */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_write Actual file write service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_write(FX_FILE *file_ptr, VOID *buffer_ptr, ULONG size) +{ + +UINT status; + + + /* Check for a null file or buffer pointer. */ + if ((file_ptr == FX_NULL) || (buffer_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file write service. */ + status = _fx_file_write(file_ptr, buffer_ptr, size); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c b/src/Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c new file mode 100644 index 00000000..61e0d227 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_file_write_notify_set.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** File */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_file.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_file_write_notify_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the file write notify set. */ +/* */ +/* INPUT */ +/* */ +/* file_ptr File control block pointer */ +/* file_write_notify Notify function called when */ +/* file is written to */ +/* */ +/* OUTPUT */ +/* */ +/* FX_PTR_ERROR media_ptr is NULL */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _fx_file_write_notify Actual file write notify set */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_file_write_notify_set(FX_FILE *file_ptr, VOID (*file_write_notify)(FX_FILE *file)) +{ +UINT status; + + /* Check for invalid input pointers. */ + if (file_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual file write notify set service. */ + status = _fx_file_write_notify_set(file_ptr, file_write_notify); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_abort.c b/src/Middlewares/ST/filex/common/src/fxe_media_abort.c new file mode 100644 index 00000000..31f1bc3d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_abort.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_abort PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media abort call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_abort Actual media abort service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_abort(FX_MEDIA *media_ptr) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media abort service. */ + status = _fx_media_abort(media_ptr); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c b/src/Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c new file mode 100644 index 00000000..2221a7b2 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_cache_invalidate.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_cache_invalidate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media invalidate service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_cache_invalidate Actual media invalidate */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_cache_invalidate(FX_MEDIA *media_ptr) +{ + +UINT status; + + + /* Check for a NULL media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media invalidate service. */ + status = _fx_media_cache_invalidate(media_ptr); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_check.c b/src/Middlewares/ST/filex/common/src/fxe_media_check.c new file mode 100644 index 00000000..b11688b9 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_check.c @@ -0,0 +1,136 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_check PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media check call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to a previously */ +/* opened media */ +/* scratch_memory_ptr Pointer to memory area for */ +/* check disk to use (as */ +/* mentioned above) */ +/* scratch_memory_size Size of the scratch memory */ +/* error_correction_option Specifies which - if any - */ +/* errors are corrected by */ +/* the check disk function. */ +/* Setting the following bit */ +/* causes that error to be */ +/* corrected: */ +/* */ +/* 0x01 -> Fix FAT Chain Errors*/ +/* 0x02 -> Fix Directory Entry */ +/* Errors */ +/* 0x04 -> Fix Lost Clusters */ +/* */ +/* errors_detected Specifies the destination */ +/* ULONG to place the error */ +/* report from check disk. */ +/* This has a similar bit map */ +/* as before: */ +/* */ +/* 0x01 -> FAT Chain Error(s) */ +/* 0x02 -> Directory Entry */ +/* Error(s) */ +/* 0x04 -> Lost Cluster(s) */ +/* */ +/* OUTPUT */ +/* */ +/* FX_SUCCESS Check disk performed its */ +/* operation successfully. */ +/* This does not mean that */ +/* there were no errors. The */ +/* errors_detected variable */ +/* needs to be examined. */ +/* FX_MEDIA_NOT_OPEN The media was not open. */ +/* FX_NOT_ENOUGH_MEMORY The scratch memory was not */ +/* large enough or the nesting */ +/* depth was greater than the */ +/* maximum specified. */ +/* FX_IO_ERROR I/O Error reading/writing to */ +/* the media. */ +/* FX_ERROR_NOT_FIXED Fundamental problem with */ +/* media that couldn't be fixed*/ +/* */ +/* CALLS */ +/* */ +/* _fx_media_check Actual media check service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_check(FX_MEDIA *media_ptr, UCHAR *scratch_memory_ptr, ULONG scratch_memory_size, ULONG error_correction_option, ULONG *errors_detected) +{ + +UINT status; + + + /* Check for a NULL media or scratch pointer. */ + if ((media_ptr == FX_NULL) || (scratch_memory_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media check service. */ + status = _fx_media_check(media_ptr, scratch_memory_ptr, scratch_memory_size, error_correction_option, errors_detected); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_close.c b/src/Middlewares/ST/filex/common/src/fxe_media_close.c new file mode 100644 index 00000000..fb70ab5b --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_close.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_close PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media close call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_close Actual media close service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_close(FX_MEDIA *media_ptr) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media close service. */ + status = _fx_media_close(media_ptr); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c b/src/Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c new file mode 100644 index 00000000..e66482d2 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_close_notify_set.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_close_notify_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media close notify set. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* media_close_notify Notify function called when */ +/* media is closed */ +/* */ +/* OUTPUT */ +/* */ +/* FX_PTR_ERROR media_ptr is NULL */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_close_notify Actual media close notify set */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_close_notify_set(FX_MEDIA *media_ptr, VOID (*media_close_notify)(FX_MEDIA *media)) +{ +UINT status; + + /* Check for invalid input pointers. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media close notify set service. */ + status = _fx_media_close_notify_set(media_ptr, media_close_notify); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c b/src/Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c new file mode 100644 index 00000000..5017687d --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_exFAT_format.c @@ -0,0 +1,123 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" + + +#ifdef FX_ENABLE_EXFAT +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_exFAT_format PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the exFAT media format call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media control block*/ +/* (does not need to be opened)*/ +/* driver Pointer to FileX driver (must */ +/* be able to field requests */ +/* prior to opening) */ +/* driver_info_ptr Optional information pointer */ +/* memory_ptr Pointer to memory used by the */ +/* FileX for this media. */ +/* memory_size Size of media memory - must */ +/* at least 512 bytes and */ +/* one sector size. */ +/* volume_name Name of the volume */ +/* number_of_fats Number of FAT tables */ +/* hidden_sectors Number of hidden sectors */ +/* total_sectors Total number of sectors */ +/* bytes_per_sector Number of bytes per sector */ +/* sectors_per_cluster Number of sectors per cluster */ +/* volume_serial_number Volume Serial Number */ +/* boundary_unit Data area alignment in sectors*/ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_exFAT_format Actual media format service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_exFAT_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, + UCHAR *memory_ptr, UINT memory_size, CHAR *volume_name, UINT number_of_fats, + ULONG64 hidden_sectors, ULONG64 total_sectors, UINT bytes_per_sector, + UINT sectors_per_cluster, UINT volume_serial_number, UINT boundary_unit) +{ + +UINT status; + + + /* Check for invalid input pointers. */ + if ((media_ptr == FX_NULL) || (driver == FX_NULL) || (memory_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media format service. */ + status = _fx_media_exFAT_format(media_ptr, driver, driver_info_ptr, memory_ptr, memory_size, + volume_name, number_of_fats, hidden_sectors, total_sectors, bytes_per_sector, sectors_per_cluster, volume_serial_number, boundary_unit); + + /* Return completion status. */ + return(status); +} + +#endif /* FX_ENABLE_EXFAT */ + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c b/src/Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c new file mode 100644 index 00000000..212900c3 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_extended_space_available.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_extended_space_available PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media space available call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* available_bytes_ptr Pointer to available bytes */ +/* destination */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_extended_space_available Actual space available service*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_extended_space_available(FX_MEDIA *media_ptr, ULONG64 *available_bytes_ptr) +{ + +UINT status; + + + /* Check for a null media pointer or destination pointer. */ + if ((media_ptr == FX_NULL) || (available_bytes_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media space available service. */ + status = _fx_media_extended_space_available(media_ptr, available_bytes_ptr); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_flush.c b/src/Middlewares/ST/filex/common/src/fxe_media_flush.c new file mode 100644 index 00000000..ce71d122 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_flush.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_flush PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the flush media call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* FX_PTR_ERROR Supplied pointer is invalid */ +/* FX_CALLER_ERROR Caller is not a thread */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_flush Actual media flush service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_flush(FX_MEDIA *media_ptr) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media flush service. */ + status = _fx_media_flush(media_ptr); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_format.c b/src/Middlewares/ST/filex/common/src/fxe_media_format.c new file mode 100644 index 00000000..9da865a4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_format.c @@ -0,0 +1,122 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_format PORTABLE C */ +/* 6.1.5 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media format call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media control block*/ +/* (does not need to be opened)*/ +/* driver Pointer to FileX driver (must */ +/* be able to field requests */ +/* prior to opening) */ +/* driver_info_ptr Optional information pointer */ +/* memory_ptr Pointer to memory used by the */ +/* FileX for this media. */ +/* memory_size Size of media memory - must */ +/* at least 512 bytes and */ +/* one sector size. */ +/* volume_name Name of the volume */ +/* number_of_fats Number of FAT tables */ +/* directory_entries Number of directory entries */ +/* hidden_sectors Number of hidden sectors */ +/* total_sectors Total number of sectors */ +/* bytes_per_sector Number of bytes per sector */ +/* sectors_per_cluster Number of sectors per cluster */ +/* heads Number of heads */ +/* sectors_per_track Number of sectors per track */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_format Actual media format service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* 03-02-2021 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_format(FX_MEDIA *media_ptr, VOID (*driver)(FX_MEDIA *media), VOID *driver_info_ptr, UCHAR *memory_ptr, UINT memory_size, + CHAR *volume_name, UINT number_of_fats, UINT directory_entries, UINT hidden_sectors, + ULONG total_sectors, UINT bytes_per_sector, UINT sectors_per_cluster, + UINT heads, UINT sectors_per_track) +{ + +UINT status; + + + /* Check for invalid input pointers. */ + if ((media_ptr == FX_NULL) || (driver == FX_NULL) || (memory_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media format service. */ + status = _fx_media_format(media_ptr, driver, driver_info_ptr, memory_ptr, memory_size, + volume_name, number_of_fats, directory_entries, hidden_sectors, + total_sectors, bytes_per_sector, sectors_per_cluster, + heads, sectors_per_track); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_open.c b/src/Middlewares/ST/filex/common/src/fxe_media_open.c new file mode 100644 index 00000000..2b144482 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_open.c @@ -0,0 +1,189 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" +#include "fx_system.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_open PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media open call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* media_name Pointer to media name string */ +/* media_driver Media driver entry function */ +/* driver_info_ptr Optional information pointer */ +/* supplied to media driver */ +/* memory_ptr Pointer to memory used by the */ +/* FileX for this media. */ +/* memory_size Size of media memory - must */ +/* at least 512 bytes and */ +/* one sector size. */ +/* media_control_block_size Size of FX_MEDIA structure */ +/* */ +/* OUTPUT */ +/* */ +/* FX_PTR_ERROR One or more input parameters */ +/* are NULL */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_identify Get current thread */ +/* tx_thread_preemption_change Disable/restore preemption */ +/* _fx_media_open Actual media open service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_open(FX_MEDIA *media_ptr, CHAR *media_name, + VOID (*media_driver)(FX_MEDIA *), VOID *driver_info_ptr, + VOID *memory_ptr, ULONG memory_size, UINT media_control_block_size) +{ + +UINT status; +ULONG temp; +FX_MEDIA *current_media; +ULONG open_count; + +#ifndef FX_SINGLE_THREAD +TX_THREAD *current_thread; +UINT old_threshold; +#endif + + + /* Check for invalid input pointers. */ + if ((media_ptr == FX_NULL) || (media_driver == FX_NULL) || (memory_ptr == FX_NULL) || (media_control_block_size != sizeof(FX_MEDIA))) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Check for proper size of the logical sector cache. */ + temp = _fx_system_media_max_sector_cache; + + /* Isolate the lowest set bit. */ + temp = (temp & ((~temp) + ((ULONG) 1))); + + /* If FX_MAX_SECTOR_CACHE is a power of 2, the value of temp should be unchanged. */ + if ((temp == 1) || (temp != _fx_system_media_max_sector_cache)) + { + + /* Not a power of 2, return an error. */ + return(FX_MEDIA_INVALID); + } + + /* Check for proper size of the FAT cache. */ + temp = _fx_system_media_max_fat_cache; + + /* Isolate the lowest set bit. */ + temp = (temp & ((~temp) + ((ULONG) 1))); + + /* If FX_MAX_FAT_CACHE is a power of 2, the value of temp should be unchanged. */ + if ((temp == 1) || (temp != _fx_system_media_max_fat_cache)) + { + + /* Not a power of 2, return an error. */ + return(FX_MEDIA_INVALID); + } + +#ifndef FX_SINGLE_THREAD + + /* Pickup current thread pointer. At this point we know the current thread pointer is non-null since + it was checked by code in FX_CALLER_CHECKING_CODE macro. */ + current_thread = tx_thread_identify(); + + /* Disable preemption temporarily. */ + tx_thread_preemption_change(current_thread, 0, &old_threshold); +#endif + + /* Loop to check for the media already opened. */ + current_media = _fx_system_media_opened_ptr; + open_count = _fx_system_media_opened_count; + while (open_count--) + { + + /* Is the new media pointer already open? */ + if (media_ptr == current_media) + { + +#ifndef FX_SINGLE_THREAD + + /* Restore preemption. */ + tx_thread_preemption_change(current_thread, old_threshold, &old_threshold); +#endif + + /* Duplicate media open, return an error! */ + return(FX_PTR_ERROR); + } + + /* Move to next entry. */ + current_media = current_media -> fx_media_opened_next; + } + +#ifndef FX_SINGLE_THREAD + + /* Restore preemption. */ + tx_thread_preemption_change(current_thread, old_threshold, &old_threshold); +#endif + + /* Call actual media open service. */ + status = _fx_media_open(media_ptr, media_name, media_driver, driver_info_ptr, + memory_ptr, memory_size); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c b/src/Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c new file mode 100644 index 00000000..8c656608 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_open_notify_set.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_open_notify_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media open notify set. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* media_open_notify Notify function called when */ +/* media is open */ +/* */ +/* OUTPUT */ +/* */ +/* FX_PTR_ERROR media_ptr is NULL */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_open_notify Actual media open notify set */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_open_notify_set(FX_MEDIA *media_ptr, VOID (*media_open_notify)(FX_MEDIA *media)) +{ +UINT status; + + /* Check for invalid input pointers. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media open notify set service. */ + status = _fx_media_open_notify_set(media_ptr, media_open_notify); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_read.c b/src/Middlewares/ST/filex/common/src/fxe_media_read.c new file mode 100644 index 00000000..0c8d2069 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_read.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media read call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Logical sector to read */ +/* buffer_ptr Pointer to caller's buffer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_read Actual media read service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_read(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr) +{ + +UINT status; + + + /* Check for a null media pointer or buffer pointer. */ + if ((media_ptr == FX_NULL) || (buffer_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media read service. */ + status = _fx_media_read(media_ptr, logical_sector, buffer_ptr); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_space_available.c b/src/Middlewares/ST/filex/common/src/fxe_media_space_available.c new file mode 100644 index 00000000..3552226f --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_space_available.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_space_available PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media space available call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* available_bytes_ptr Pointer to available bytes */ +/* destination */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_space_available Actual space available service*/ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_space_available(FX_MEDIA *media_ptr, ULONG *available_bytes_ptr) +{ + +UINT status; + + + /* Check for a null media pointer or destination pointer. */ + if ((media_ptr == FX_NULL) || (available_bytes_ptr == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media space available service. */ + status = _fx_media_space_available(media_ptr, available_bytes_ptr); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_volume_get.c b/src/Middlewares/ST/filex/common/src/fxe_media_volume_get.c new file mode 100644 index 00000000..6136d3b8 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_volume_get.c @@ -0,0 +1,100 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_volume_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media volume get service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* volume_name Pointer to destination for */ +/* the volume name (maximum */ +/* 11 characters + NULL) */ +/* volume_source Source of volume */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_volume_get Actual media volume get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_volume_get(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_source) +{ + +UINT status; + + + /* Check for a NULL media or volume name pointer. */ + if ((media_ptr == FX_NULL) || (volume_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media volume get service. */ + status = _fx_media_volume_get(media_ptr, volume_name, volume_source); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c b/src/Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c new file mode 100644 index 00000000..d2645cc8 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_volume_get_extended.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_volume_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media volume get service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* volume_name Pointer to destination for */ +/* the volume name (maximum */ +/* 11 characters + NULL) */ +/* volume_name_buffer_length Buffer length for volume_name */ +/* volume_source Source of volume */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_volume_get_extended Actual media volume get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_volume_get_extended(FX_MEDIA *media_ptr, CHAR *volume_name, UINT volume_name_buffer_length, UINT volume_source) +{ + +UINT status; + + + /* Check for a NULL media or volume name pointer. */ + if ((media_ptr == FX_NULL) || (volume_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for zero length buffer. */ + if (volume_name_buffer_length == 0) + { + return(FX_BUFFER_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media volume get service. */ + status = _fx_media_volume_get_extended(media_ptr, volume_name, volume_name_buffer_length, volume_source); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_volume_set.c b/src/Middlewares/ST/filex/common/src/fxe_media_volume_set.c new file mode 100644 index 00000000..f4efd5ce --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_volume_set.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_volume_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media volume set service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* volume_name New volume name */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_volume_set Actual media volume name set */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_volume_set(FX_MEDIA *media_ptr, CHAR *volume_name) +{ + +UINT status; + + + /* Check for a NULL media or volume name pointer. */ + if ((media_ptr == FX_NULL) || (volume_name == FX_NULL) || (volume_name[0] == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media volume set service. */ + status = _fx_media_volume_set(media_ptr, volume_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_media_write.c b/src/Middlewares/ST/filex/common/src/fxe_media_write.c new file mode 100644 index 00000000..21865fe4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_media_write.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Media */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_media.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_media_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the media write call. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Media control block pointer */ +/* logical_sector Logical sector to read */ +/* buffer_ptr Pointer to caller's buffer */ +/* */ +/* OUTPUT */ +/* */ +/* return status */ +/* */ +/* CALLS */ +/* */ +/* _fx_media_write Actual media write service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_media_write(FX_MEDIA *media_ptr, ULONG logical_sector, VOID *buffer_ptr) +{ + +UINT status; + + + /* Check for a null media pointer. */ + if (media_ptr == FX_NULL) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual media write service. */ + status = _fx_media_write(media_ptr, logical_sector, buffer_ptr); + + /* Return a successful status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_system_date_get.c b/src/Middlewares/ST/filex/common/src/fxe_system_date_get.c new file mode 100644 index 00000000..1216ed65 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_system_date_get.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_system_date_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the get system date call. */ +/* */ +/* INPUT */ +/* */ +/* year Pointer to year */ +/* month Pointer to month */ +/* day Pointer to day */ +/* */ +/* OUTPUT */ +/* */ +/* FX_PTR_ERROR Invalid destination pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _fx_system_date_get Actual get system date call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_system_date_get(UINT *year, UINT *month, UINT *day) +{ + +UINT status; + + + /* Check for an invalid pointer. */ + if ((year == FX_NULL) || (month == FX_NULL) || (day == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Call actual service to get the system date. */ + status = _fx_system_date_get(year, month, day); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_system_date_set.c b/src/Middlewares/ST/filex/common/src/fxe_system_date_set.c new file mode 100644 index 00000000..3628d22a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_system_date_set.c @@ -0,0 +1,257 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_system_date_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the set system date call. */ +/* */ +/* INPUT */ +/* */ +/* year Year (1980-2107) */ +/* month Month (1-12) */ +/* day Day (1-28/29/30/31) */ +/* */ +/* OUTPUT */ +/* */ +/* FX_INVALID_YEAR Supplied year is invalid */ +/* FX_INVALID_MONTH Supplied month is invalid */ +/* FX_INVALID_DAY Supplied day is invalid */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _fx_system_date_set Actual system date set call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_system_date_set(UINT year, UINT month, UINT day) +{ + +UINT status; + + + /* Check for invalid year. */ + if ((year < FX_BASE_YEAR) || (year > FX_MAXIMUM_YEAR)) + { + return(FX_INVALID_YEAR); + } + + /* Check for invalid day. */ + if (day < 1) + { + return(FX_INVALID_DAY); + } + + /* Check for invalid day. */ + switch (month) + { + + case 1: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 2: + { + + /* Check for leap year. */ + if ((year % 4) == 0) + { + + /* Leap year, February has 29 days. */ + if (day > 29) + { + return(FX_INVALID_DAY); + } + } + else + { + + /* Otherwise, non-leap year. February has + 28 days. */ + if (day > 28) + { + return(FX_INVALID_DAY); + } + } + break; + } + + case 3: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 4: + { + + /* Check for 30 days. */ + if (day > 30) + { + return(FX_INVALID_DAY); + } + break; + } + + case 5: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 6: + { + + /* Check for 30 days. */ + if (day > 30) + { + return(FX_INVALID_DAY); + } + break; + } + + case 7: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 8: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 9: + { + + /* Check for 30 days. */ + if (day > 30) + { + return(FX_INVALID_DAY); + } + break; + } + + case 10: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + case 11: + { + + /* Check for 30 days. */ + if (day > 30) + { + return(FX_INVALID_DAY); + } + break; + } + + case 12: + { + + /* Check for 31 days. */ + if (day > 31) + { + return(FX_INVALID_DAY); + } + break; + } + + default: + + /* Invalid month. */ + return(FX_INVALID_MONTH); + } + + /* Call actual system date set service. */ + status = _fx_system_date_set(year, month, day); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_system_time_get.c b/src/Middlewares/ST/filex/common/src/fxe_system_time_get.c new file mode 100644 index 00000000..109aa33a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_system_time_get.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_system_time_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks of errors in the get system time call. */ +/* */ +/* INPUT */ +/* */ +/* hour Pointer to hour */ +/* minute Pointer to minute */ +/* second Pointer to second */ +/* */ +/* OUTPUT */ +/* */ +/* FX_PTR_ERROR Invalid destination pointer */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _fx_system_time_get Actual get time service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_system_time_get(UINT *hour, UINT *minute, UINT *second) +{ + +UINT status; + + + /* Check for an invalid destination pointer. */ + if ((hour == FX_NULL) || (minute == FX_NULL) || (second == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Call actual get time service. */ + status = _fx_system_time_get(hour, minute, second); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_system_time_set.c b/src/Middlewares/ST/filex/common/src/fxe_system_time_set.c new file mode 100644 index 00000000..07d946ab --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_system_time_set.c @@ -0,0 +1,106 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_system.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_system_time_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the set the system time call. */ +/* */ +/* INPUT */ +/* */ +/* hour Hour (0-23) */ +/* minute Minute (0-59) */ +/* second Second (0-59) */ +/* */ +/* OUTPUT */ +/* */ +/* FX_INVALID_HOUR Supplied hour is invalid */ +/* FX_INVALID_MINUTE Supplied minute is invalid */ +/* FX_INVALID_SECOND Supplied second is invalid */ +/* status Actual completion status */ +/* */ +/* CALLS */ +/* */ +/* _fx_system_time_set Actual system time set call */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_system_time_set(UINT hour, UINT minute, UINT second) +{ + +UINT status; + + + /* Check for invalid hour. */ + if (hour > FX_MAXIMUM_HOUR) + { + return(FX_INVALID_HOUR); + } + + /* Check for invalid minute. */ + if (minute > FX_MAXIMUM_MINUTE) + { + return(FX_INVALID_MINUTE); + } + + /* Check for invalid second. */ + if (second > FX_MAXIMUM_SECOND) + { + return(FX_INVALID_SECOND); + } + + /* Call the actual set system time service. */ + status = _fx_system_time_set(hour, minute, second); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c b/src/Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c new file mode 100644 index 00000000..22c334e1 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_unicode_directory_create.c @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_unicode_directory_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the Unicode directory create */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_unicode_name Pointer to source unicode name*/ +/* source_unicode_length Unicode name length */ +/* short_name Designated short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_directory_create Actual Unicode directory */ +/* create service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_unicode_directory_create(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, CHAR *short_name) +{ + +UINT status, i; + + /* Check for a NULL media or name pointers. */ + if ((media_ptr == FX_NULL) || (source_unicode_name == FX_NULL) || (source_unicode_length == 0) || (short_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Check unicode zero in source_unicode_name */ + for (i = 0; i < (source_unicode_length << 1); i += 2) + { + if ((source_unicode_name[i] == 0) && (source_unicode_name[i + 1] == 0)) + { + return(FX_INVALID_NAME); + } + } + + /* Call actual Unicode directory create service. */ + status = _fx_unicode_directory_create(media_ptr, source_unicode_name, source_unicode_length, short_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c b/src/Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c new file mode 100644 index 00000000..55975806 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_unicode_directory_rename.c @@ -0,0 +1,122 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_unicode_directory_rename PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the Unicode directory rename */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* old_unicode_name Pointer to old unicode name */ +/* old_unicode_length Old unicode name length */ +/* new_unicode_name Pointer to new unicode name */ +/* new_unicode_length Old unicode name length */ +/* new_short_name Pointer to new short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_directory_rename Actual Unicode directory */ +/* rename service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_unicode_directory_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name) +{ + +UINT status, i; + + + /* Check for a NULL media or name pointers. */ + if ((media_ptr == FX_NULL) || (old_unicode_name == FX_NULL) || (old_unicode_length == 0) || + (new_unicode_name == FX_NULL) || (new_unicode_length == 0) || (new_short_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Check unicode zero in old_unicode_name */ + for (i = 0; i < (old_unicode_length << 1); i += 2) + { + if ((old_unicode_name[i] == 0) && (old_unicode_name[i + 1] == 0)) + { + return(FX_INVALID_NAME); + } + } + + /* Check unicode zero in new_unicode_name */ + for (i = 0; i < (new_unicode_length << 1); i += 2) + { + if ((new_unicode_name[i] == 0) && (new_unicode_name[i + 1] == 0)) + { + return(FX_INVALID_NAME); + } + } + + /* Call actual Unicode directory rename service. */ + status = _fx_unicode_directory_rename(media_ptr, old_unicode_name, old_unicode_length, new_unicode_name, new_unicode_length, new_short_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_unicode_file_create.c b/src/Middlewares/ST/filex/common/src/fxe_unicode_file_create.c new file mode 100644 index 00000000..6ff937df --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_unicode_file_create.c @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_unicode_file_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the Unicode file create service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_unicode_name Pointer to source unicode name*/ +/* source_unicode_length Unicode name length */ +/* short_name Designated short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_file_create Actual Unicode file create */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_unicode_file_create(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, CHAR *short_name) +{ + +UINT status, i; + + + /* Check for a NULL media or name pointers. */ + if ((media_ptr == FX_NULL) || (source_unicode_name == FX_NULL) || (source_unicode_length == 0) || (short_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Check unicode zero in source_unicode_name */ + for (i = 0; i < (source_unicode_length << 1); i += 2) + { + if ((source_unicode_name[i] == 0) && (source_unicode_name[i + 1] == 0)) + { + return(FX_INVALID_NAME); + } + } + + /* Call actual Unicode file create service. */ + status = _fx_unicode_file_create(media_ptr, source_unicode_name, source_unicode_length, short_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c b/src/Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c new file mode 100644 index 00000000..3ab05db7 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_unicode_file_rename.c @@ -0,0 +1,122 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_unicode_file_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the Unicode file rename service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* old_unicode_name Pointer to old unicode name */ +/* old_unicode_length Old unicode name length */ +/* new_unicode_name Pointer to new unicode name */ +/* new_unicode_length New unicode name length */ +/* new_short_name Designated new short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_file_rename Actual Unicode file rename */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_unicode_file_rename(FX_MEDIA *media_ptr, UCHAR *old_unicode_name, ULONG old_unicode_length, + UCHAR *new_unicode_name, ULONG new_unicode_length, CHAR *new_short_name) +{ + +UINT status, i; + + + /* Check for a NULL media or name pointers. */ + if ((media_ptr == FX_NULL) || (old_unicode_name == FX_NULL) || (old_unicode_length == 0) || + (new_unicode_name == FX_NULL) || (new_unicode_length == 0) || (new_short_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Check unicode zero in old_unicode_name */ + for (i = 0; i < (old_unicode_length << 1); i += 2) + { + if ((old_unicode_name[i] == 0) && (old_unicode_name[i + 1] == 0)) + { + return(FX_INVALID_NAME); + } + } + + /* Check unicode zero in new_unicode_name */ + for (i = 0; i < (new_unicode_length << 1); i += 2) + { + if ((new_unicode_name[i] == 0) && (new_unicode_name[i + 1] == 0)) + { + return(FX_INVALID_NAME); + } + } + + /* Call actual Unicode file rename service. */ + status = _fx_unicode_file_rename(media_ptr, old_unicode_name, old_unicode_length, + new_unicode_name, new_unicode_length, new_short_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_unicode_name_get.c b/src/Middlewares/ST/filex/common/src/fxe_unicode_name_get.c new file mode 100644 index 00000000..aba8c0b4 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_unicode_name_get.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_unicode_name_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the Unicode name get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_short_name Pointer to short file name */ +/* destination_unicode_name Pointer to destination name */ +/* destination_unicode_length Destination for name length */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_directory_unicode_search Search for unicode name */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_unicode_name_get(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length) +{ + +UINT status; + + + /* Check for a NULL media or name pointers. */ + if ((media_ptr == FX_NULL) || (source_short_name == FX_NULL) || (destination_unicode_name == FX_NULL) || (destination_unicode_length == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual Unicode name get service. */ + status = _fx_unicode_name_get(media_ptr, source_short_name, + destination_unicode_name, destination_unicode_length); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c b/src/Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c new file mode 100644 index 00000000..e3789d20 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_unicode_name_get_extended.c @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +FX_CALLER_CHECKING_EXTERNS + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_unicode_name_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the Unicode name get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_short_name Pointer to short file name */ +/* destination_unicode_name Pointer to destination name */ +/* destination_unicode_length Destination for name length */ +/* unicode_name_buffer_length Buffer length of unicode name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_name_get_extended Actual unicode name get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_unicode_name_get_extended(FX_MEDIA *media_ptr, CHAR *source_short_name, + UCHAR *destination_unicode_name, ULONG *destination_unicode_length, ULONG unicode_name_buffer_length) +{ + +UINT status; + + + /* Check for a NULL media or name pointers. */ + if ((media_ptr == FX_NULL) || (source_short_name == FX_NULL) || (destination_unicode_name == FX_NULL) || (destination_unicode_length == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for zero length buffer. */ + if (unicode_name_buffer_length == 0) + { + return(FX_BUFFER_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Call actual Unicode name get service. */ + status = _fx_unicode_name_get_extended(media_ptr, source_short_name, + destination_unicode_name, destination_unicode_length, unicode_name_buffer_length); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c b/src/Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c new file mode 100644 index 00000000..368223c6 --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_unicode_short_name_get.c @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +FX_CALLER_CHECKING_EXTERNS + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_unicode_short_name_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the Unicode short name get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_unicode_name Pointer to unicode name */ +/* source_unicode_length Length of unicode name */ +/* destination_short_name Pointer to destination name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_short_name_get Actual unicode short name get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_unicode_short_name_get(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name) +{ + +UINT status, i; + + + /* Check for a NULL media or name pointers. */ + if ((media_ptr == FX_NULL) || (source_unicode_name == FX_NULL) || (source_unicode_length == 0) || (destination_short_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Check unicode zero in source_unicode_name */ + for (i = 0; i < (source_unicode_length << 1); i += 2) + { + if ((source_unicode_name[i] == 0) && (source_unicode_name[i + 1] == 0)) + { + return(FX_INVALID_NAME); + } + } + + /* Call actual Unicode short name get service. */ + status = _fx_unicode_short_name_get(media_ptr, source_unicode_name, source_unicode_length, destination_short_name); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c b/src/Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c new file mode 100644 index 00000000..9032c20a --- /dev/null +++ b/src/Middlewares/ST/filex/common/src/fxe_unicode_short_name_get_extended.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Unicode */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define FX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "fx_api.h" +#include "fx_unicode.h" + + +FX_CALLER_CHECKING_EXTERNS + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _fxe_unicode_short_name_get_extended PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for errors in the Unicode short name get */ +/* service. */ +/* */ +/* INPUT */ +/* */ +/* media_ptr Pointer to media */ +/* source_unicode_name Pointer to unicode name */ +/* source_unicode_length Length of unicode name */ +/* destination_short_name Pointer to destination name */ +/* short_name_buffer_length Buffer length of short name */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _fx_unicode_short_name_get_extended Actual unicode short name get */ +/* service */ +/* */ +/* CALLED BY */ +/* */ +/* Application Code */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 William E. Lamie Initial Version 6.0 */ +/* 09-30-2020 William E. Lamie Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _fxe_unicode_short_name_get_extended(FX_MEDIA *media_ptr, UCHAR *source_unicode_name, ULONG source_unicode_length, + CHAR *destination_short_name, ULONG short_name_buffer_length) +{ + +UINT status, i; + + + /* Check for a NULL media or name pointers. */ + if ((media_ptr == FX_NULL) || (source_unicode_name == FX_NULL) || (source_unicode_length == 0) || (destination_short_name == FX_NULL)) + { + return(FX_PTR_ERROR); + } + + /* Check for zero length buffer. */ + if (short_name_buffer_length == 0) + { + return(FX_BUFFER_ERROR); + } + + /* Check for a valid caller. */ + FX_CALLER_CHECKING_CODE + + /* Check unicode zero in source_unicode_name */ + for (i = 0; i < (source_unicode_length << 1); i += 2) + { + if ((source_unicode_name[i] == 0) && (source_unicode_name[i + 1] == 0)) + { + return(FX_INVALID_NAME); + } + } + + /* Call actual Unicode short name get service. */ + status = _fx_unicode_short_name_get_extended(media_ptr, source_unicode_name, source_unicode_length, destination_short_name, short_name_buffer_length); + + /* Return status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/filex/ports/generic/inc/fx_port.h b/src/Middlewares/ST/filex/ports/generic/inc/fx_port.h new file mode 100644 index 00000000..332b7f43 --- /dev/null +++ b/src/Middlewares/ST/filex/ports/generic/inc/fx_port.h @@ -0,0 +1,222 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** FileX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* fx_port.h Generic */ +/* 6.1.5 */ +/* */ +/* AUTHOR */ +/* */ +/* William E. Lamie, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make the FileX FAT */ +/* compatible file system function identically on a variety of */ +/* different processor architectures. For example, the byte offset of */ +/* various entries in the boot record, and directory entries are */ +/* defined in this file. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 11-09-2020 William E. Lamie Initial Version 6.1.2 */ +/* 03-02-2021 William E. Lamie Modified comment(s), and */ +/* added standalone support, */ +/* resulting in version 6.1.5 */ +/* */ +/**************************************************************************/ + +#ifndef FX_PORT_H +#define FX_PORT_H + + +/* Determine if the optional FileX user define file should be used. */ + +#ifdef FX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in fx_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "fx_user.h" +#endif + + +/* Include the ThreadX api file. */ + +#ifndef FX_STANDALONE_ENABLE +#include "tx_api.h" + + +/* Define ULONG64 typedef, if not already defined. */ + +#ifndef ULONG64_DEFINED +#define ULONG64_DEFINED +typedef unsigned long long ULONG64; +#endif + +#else + +/* Define compiler library include files. */ + +#include +#include + +#define VOID void +typedef char CHAR; +typedef char BOOL; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; + +#ifndef ULONG64_DEFINED +#define ULONG64_DEFINED +typedef unsigned long long ULONG64; +#endif + +/* Define basic alignment type used in block and byte pool operations. This data type must + be at least 32-bits in size and also be large enough to hold a pointer type. */ + +#ifndef ALIGN_TYPE_DEFINED +#define ALIGN_TYPE_DEFINED +#define ALIGN_TYPE ULONG +#endif + +#endif + +/* Define FileX internal protection macros. If FX_SINGLE_THREAD is defined, + these protection macros are effectively disabled. However, for multi-thread + uses, the macros are setup to utilize a ThreadX mutex for multiple thread + access control into an open media. */ + +#if defined(FX_SINGLE_THREAD) || defined(FX_STANDALONE_ENABLE) +#define FX_PROTECT +#define FX_UNPROTECT +#else +#define FX_PROTECT if (media_ptr -> fx_media_id != FX_MEDIA_ID) return(FX_MEDIA_NOT_OPEN); \ + else if (tx_mutex_get(&(media_ptr -> fx_media_protect), TX_WAIT_FOREVER) != TX_SUCCESS) return(FX_MEDIA_NOT_OPEN); +#define FX_UNPROTECT tx_mutex_put(&(media_ptr -> fx_media_protect)); +#endif + + +/* Define interrupt lockout constructs to protect the system date/time from being updated + while they are being read. */ +#ifndef FX_STANDALONE_ENABLE +#ifndef FX_INT_SAVE_AREA +#define FX_INT_SAVE_AREA unsigned int old_interrupt_posture; +#endif + +#ifndef FX_DISABLE_INTS +#define FX_DISABLE_INTS old_interrupt_posture = tx_interrupt_control(TX_INT_DISABLE); +#endif + +#ifndef FX_RESTORE_INTS +#define FX_RESTORE_INTS tx_interrupt_control(old_interrupt_posture); +#endif +#else +/* Disable use of ThreadX protection in standalone mode for FileX */ +#ifndef FX_LEGACY_INTERRUPT_PROTECTION +#define FX_LEGACY_INTERRUPT_PROTECTION +#endif +#define FX_INT_SAVE_AREA +#define FX_DISABLE_INTS +#define FX_RESTORE_INTS +#endif + +/* Define the error checking logic to determine if there is a caller error in the FileX API. + The default definitions assume ThreadX is being used. This code can be completely turned + off by just defining these macros to white space. */ + +#ifndef FX_STANDALONE_ENABLE +#ifndef TX_TIMER_PROCESS_IN_ISR + +#define FX_CALLER_CHECKING_EXTERNS extern TX_THREAD *_tx_thread_current_ptr; \ + extern TX_THREAD _tx_timer_thread; \ + extern volatile ULONG _tx_thread_system_state; + +#define FX_CALLER_CHECKING_CODE if ((TX_THREAD_GET_SYSTEM_STATE()) || \ + (_tx_thread_current_ptr == TX_NULL) || \ + (_tx_thread_current_ptr == &_tx_timer_thread)) \ + return(FX_CALLER_ERROR); + +#else +#define FX_CALLER_CHECKING_EXTERNS extern TX_THREAD *_tx_thread_current_ptr; \ + extern volatile ULONG _tx_thread_system_state; + +#define FX_CALLER_CHECKING_CODE if ((TX_THREAD_GET_SYSTEM_STATE()) || \ + (_tx_thread_current_ptr == TX_NULL)) \ + return(FX_CALLER_ERROR); +#endif +#else +#define FX_CALLER_CHECKING_EXTERNS +#define FX_CALLER_CHECKING_CODE +#endif + + +/* Define the update rate of the system timer. These values may also be defined at the command + line when compiling the fx_system_initialize.c module in the FileX library build. Alternatively, they can + be modified in this file or fx_user.h. Note: the update rate must be an even number of seconds greater + than or equal to 2, which is the minimal update rate for FAT time. */ + +/* Define the number of seconds the timer parameters are updated in FileX. The default + value is 10 seconds. This value can be overwritten externally. */ + +#ifndef FX_UPDATE_RATE_IN_SECONDS +#define FX_UPDATE_RATE_IN_SECONDS 10 +#endif + + +/* Defines the number of ThreadX timer ticks required to achieve the update rate specified by + FX_UPDATE_RATE_IN_SECONDS defined previously. By default, the ThreadX timer tick is 10ms, + so the default value for this constant is 1000. If TX_TIMER_TICKS_PER_SECOND is defined, + this value is derived from TX_TIMER_TICKS_PER_SECOND. */ + +#ifndef FX_UPDATE_RATE_IN_TICKS +#if (defined(TX_TIMER_TICKS_PER_SECOND) && (!defined(FX_STANDALONE_ENABLE))) +#define FX_UPDATE_RATE_IN_TICKS (TX_TIMER_TICKS_PER_SECOND * FX_UPDATE_RATE_IN_SECONDS) +#else +#define FX_UPDATE_RATE_IN_TICKS 1000 +#endif +#endif + + +/* Define the version ID of FileX. This may be utilized by the application. */ + +#ifdef FX_SYSTEM_INIT +CHAR _fx_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * FileX Generic Version 6.1.10 *"; +#else +extern CHAR _fx_version_id[]; +#endif + +#endif + diff --git a/src/Middlewares/ST/threadx/common/src/tx_misra.c b/src/Middlewares/ST/threadx/common/src/tx_misra.c deleted file mode 100644 index bc71c58f..00000000 --- a/src/Middlewares/ST/threadx/common/src/tx_misra.c +++ /dev/null @@ -1,836 +0,0 @@ -/**************************************************************************/ -/* */ -/* Copyright (c) Microsoft Corporation. All rights reserved. */ -/* */ -/* This software is licensed under the Microsoft Software License */ -/* Terms for Microsoft Azure RTOS. Full text of the license can be */ -/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ -/* and in the root directory of this software. */ -/* */ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ThreadX Component */ -/** */ -/** ThreadX MISRA Compliance */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** _tx_version_id */ -/** */ -/**************************************************************************/ -/**************************************************************************/ - -#ifndef TX_MISRA_ENABLE -#include "tx_api.h" -#else -#define TX_THREAD_INIT -//CHAR _tx_version_id[100] = "Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX 6.1 MISRA C Compliant *"; - -#include "tx_api.h" -#include "tx_thread.h" -#include "tx_trace.h" - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -VOID _tx_misra_memset(VOID *ptr, UINT value, UINT size) -{ - memset(ptr, (INT)value, size); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -UCHAR *_tx_misra_uchar_pointer_add(UCHAR *ptr, ULONG amount) -{ - ptr = ptr + amount; - return(ptr); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -UCHAR *_tx_misra_uchar_pointer_sub(UCHAR *ptr, ULONG amount) -{ - ptr = ptr - amount; - return(ptr); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -ULONG _tx_misra_uchar_pointer_dif(UCHAR *ptr1, UCHAR *ptr2) -{ - -ULONG value; - - value = (ULONG)(ptr1 - ptr2); - return(value); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -ULONG _tx_misra_pointer_to_ulong_convert(VOID *ptr) -{ - return((ULONG) ptr); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -ULONG *_tx_misra_ulong_pointer_add(ULONG *ptr, ULONG amount) -{ - ptr = ptr + amount; - return(ptr); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -ULONG *_tx_misra_ulong_pointer_sub(ULONG *ptr, ULONG amount) -{ - - ptr = ptr - amount; - return(ptr); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -ULONG _tx_misra_ulong_pointer_dif(ULONG *ptr1, ULONG *ptr2) -{ -ULONG value; - - value = (ULONG)(ptr1 - ptr2); - return(value); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_ulong_to_pointer_convert(ULONG input); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -VOID *_tx_misra_ulong_to_pointer_convert(ULONG input) -{ - - return((VOID *) input); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, */ -/** UINT size); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -VOID _tx_misra_message_copy(ULONG **source, ULONG **destination, UINT size) -{ - -ULONG *s, *d; -UINT z; - - s = *source; - d = *destination; - z = size; - - *(d) = *(s); - (d)++; - (s)++; - if ((z) > ((UINT) 1)) - { - (z)--; - while ((z)) - { - *(d) = *(s); - (d)++; - (s)++; - (z)--; - } - } - - *source = s; - *destination = d; -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, */ -/** TX_TIMER_INTERNAL **ptr2); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -ULONG _tx_misra_timer_pointer_dif(TX_TIMER_INTERNAL **ptr1, TX_TIMER_INTERNAL **ptr2) -{ - -ULONG value; - - value = (ULONG)(ptr1 - ptr2); - return(value); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL */ -/** **ptr1, ULONG size); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -TX_TIMER_INTERNAL **_tx_misra_timer_pointer_add(TX_TIMER_INTERNAL **ptr1, ULONG amount) -{ - ptr1 = ptr1 + amount; - return(ptr1); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL */ -/** *internal_timer, TX_TIMER **user_timer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -VOID _tx_misra_user_timer_pointer_get(TX_TIMER_INTERNAL *internal_timer, TX_TIMER **user_timer) -{ - -UCHAR *working_ptr; -TX_TIMER *temp_timer; - - - working_ptr = (UCHAR *) internal_timer; - - temp_timer = (TX_TIMER *) working_ptr; - working_ptr = working_ptr - (((UCHAR *) &temp_timer -> tx_timer_internal) - ((UCHAR *) &temp_timer -> tx_timer_id)); - *user_timer = (TX_TIMER *) working_ptr; -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, */ -/** VOID **highest_stack); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -VOID _tx_misra_thread_stack_check(TX_THREAD *thread_ptr, VOID **highest_stack) -{ - -TX_INTERRUPT_SAVE_AREA - - TX_DISABLE - if (((thread_ptr)) && ((thread_ptr) -> tx_thread_id == TX_THREAD_ID)) - { - if (((ULONG *) (thread_ptr) -> tx_thread_stack_ptr) < ((ULONG *) *highest_stack)) - { - *highest_stack = (thread_ptr) -> tx_thread_stack_ptr; - } - if ((*((ULONG *) (thread_ptr) -> tx_thread_stack_start) != TX_STACK_FILL) || - (*((ULONG *) (((UCHAR *) (thread_ptr) -> tx_thread_stack_end) + 1)) != TX_STACK_FILL) || - (((ULONG *) *highest_stack) < ((ULONG *) (thread_ptr) -> tx_thread_stack_start))) - { - TX_RESTORE - _tx_thread_stack_error_handler((thread_ptr)); - TX_DISABLE - } - if (*(((ULONG *) *highest_stack) - 1) != TX_STACK_FILL) - { - TX_RESTORE - _tx_thread_stack_analyze((thread_ptr)); - TX_DISABLE - } - } - TX_RESTORE -} - - -#ifdef TX_ENABLE_EVENT_TRACE - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID _tx_misra_trace_event_insert(ULONG event_id, */ -/** VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, */ -/** ULONG info_field_4, ULONG filter, ULONG time_stamp); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -VOID _tx_misra_trace_event_insert(ULONG event_id, VOID *info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, ULONG time_stamp) -{ - -TX_TRACE_BUFFER_ENTRY *trace_event_ptr; -ULONG trace_system_state; -ULONG trace_priority; -TX_THREAD *trace_thread_ptr; - - - trace_event_ptr = _tx_trace_buffer_current_ptr; - if ((trace_event_ptr) && (_tx_trace_event_enable_bits & ((ULONG) (filter)))) - { - TX_TRACE_PORT_EXTENSION - trace_system_state = (ULONG) _tx_thread_system_state; - trace_thread_ptr = _tx_thread_current_ptr; - - if (trace_system_state == 0) - { - trace_priority = trace_thread_ptr -> tx_thread_priority; - trace_priority = trace_priority | 0x80000000UL | (trace_thread_ptr -> tx_thread_preempt_threshold << 16); - } - else if (trace_system_state < 0xF0F0F0F0UL) - { - trace_priority = (ULONG) trace_thread_ptr; - trace_thread_ptr = (TX_THREAD *) 0xFFFFFFFFUL; - } - else - { - trace_thread_ptr = (TX_THREAD *) 0xF0F0F0F0UL; - trace_priority = 0; - } - trace_event_ptr -> tx_trace_buffer_entry_thread_pointer = (ULONG) trace_thread_ptr; - trace_event_ptr -> tx_trace_buffer_entry_thread_priority = (ULONG) trace_priority; - trace_event_ptr -> tx_trace_buffer_entry_event_id = (ULONG) (event_id); - trace_event_ptr -> tx_trace_buffer_entry_time_stamp = (ULONG) (time_stamp); -#ifdef TX_MISRA_ENABLE - trace_event_ptr -> tx_trace_buffer_entry_info_1 = (ULONG) (info_field_1); - trace_event_ptr -> tx_trace_buffer_entry_info_2 = (ULONG) (info_field_2); - trace_event_ptr -> tx_trace_buffer_entry_info_3 = (ULONG) (info_field_3); - trace_event_ptr -> tx_trace_buffer_entry_info_4 = (ULONG) (info_field_4); -#else - trace_event_ptr -> tx_trace_buffer_entry_information_field_1 = (ULONG) (info_field_1); - trace_event_ptr -> tx_trace_buffer_entry_information_field_2 = (ULONG) (info_field_2); - trace_event_ptr -> tx_trace_buffer_entry_information_field_3 = (ULONG) (info_field_3); - trace_event_ptr -> tx_trace_buffer_entry_information_field_4 = (ULONG) (info_field_4); -#endif - trace_event_ptr++; - if (trace_event_ptr >= _tx_trace_buffer_end_ptr) - { - trace_event_ptr = _tx_trace_buffer_start_ptr; - _tx_trace_buffer_current_ptr = trace_event_ptr; - _tx_trace_header_ptr -> tx_trace_header_buffer_current_pointer = (ULONG) trace_event_ptr; - if (_tx_trace_full_notify_function) - (_tx_trace_full_notify_function)((VOID *) _tx_trace_header_ptr); - } - else - { - _tx_trace_buffer_current_ptr = trace_event_ptr; - _tx_trace_header_ptr -> tx_trace_header_buffer_current_pointer = (ULONG) trace_event_ptr; - } - } -} - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** ULONG _tx_misra_time_stamp_get(VOID); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -ULONG _tx_misra_time_stamp_get(VOID) -{ - - /* Return time stamp. */ - return(0); -} - -#endif - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** UINT _tx_misra_always_true(void); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -UINT _tx_misra_always_true(void) -{ - return(TX_TRUE); -} - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ -UCHAR **_tx_misra_indirect_void_to_uchar_pointer_convert(VOID **return_ptr) -{ - - /* Return an indirect UCHAR pointer. */ - return((UCHAR **) ((VOID *) return_ptr)); -} - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ -UCHAR **_tx_misra_uchar_to_indirect_uchar_pointer_convert(UCHAR *pointer) -{ - - /* Return an indirect UCHAR pointer. */ - return((UCHAR **) ((VOID *) pointer)); -} - - -/***********************************************************************************/ -/***********************************************************************************/ -/** */ -/** UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool); */ -/** */ -/***********************************************************************************/ -/***********************************************************************************/ -UCHAR *_tx_misra_block_pool_to_uchar_pointer_convert(TX_BLOCK_POOL *pool) -{ - - /* Return a UCHAR pointer. */ - return((UCHAR *) ((VOID *) pool)); -} - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ -TX_BLOCK_POOL *_tx_misra_void_to_block_pool_pointer_convert(VOID *pointer) -{ - - /* Return a block pool pointer. */ - return((TX_BLOCK_POOL *) ((VOID *) pointer)); -} - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ -UCHAR *_tx_misra_void_to_uchar_pointer_convert(VOID *pointer) -{ - - /* Return a UCHAR pointer. */ - return((UCHAR *) ((VOID *) pointer)); -} - - -/************************************************************************************/ -/************************************************************************************/ -/** */ -/** TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************/ -/************************************************************************************/ -TX_BLOCK_POOL *_tx_misra_uchar_to_block_pool_pointer_convert(UCHAR *pointer) -{ - - /* Return a UCHAR pointer. */ - return((TX_BLOCK_POOL *) ((VOID *) pointer)); -} - - -/**************************************************************************************/ -/**************************************************************************************/ -/** */ -/** UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************/ -/**************************************************************************************/ -UCHAR **_tx_misra_void_to_indirect_uchar_pointer_convert(VOID *pointer) -{ - - /* Return a UCHAR pointer. */ - return((UCHAR **) ((VOID *) pointer)); -} - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ -TX_BYTE_POOL *_tx_misra_void_to_byte_pool_pointer_convert(VOID *pointer) -{ - - /* Return a byte pool pointer. */ - return((TX_BYTE_POOL *) ((VOID *) pointer)); -} - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ -UCHAR *_tx_misra_byte_pool_to_uchar_pointer_convert(TX_BYTE_POOL *pool) -{ - - /* Return a UCHAR pointer. */ - return((UCHAR *) ((VOID *) pool)); -} - - -/*****************************************************************************************/ -/*****************************************************************************************/ -/** */ -/** ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer); */ -/** */ -/*****************************************************************************************/ -/*****************************************************************************************/ -ALIGN_TYPE *_tx_misra_uchar_to_align_type_pointer_convert(UCHAR *pointer) -{ - - /* Return an align time pointer. */ - return((ALIGN_TYPE *) ((VOID *) pointer)); -} - - -/****************************************************************************************************/ -/****************************************************************************************************/ -/** */ -/** TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer); */ -/** */ -/****************************************************************************************************/ -/****************************************************************************************************/ -TX_BYTE_POOL **_tx_misra_uchar_to_indirect_byte_pool_pointer_convert(UCHAR *pointer) -{ - - /* Return a byte pool pointer. */ - return((TX_BYTE_POOL **) ((VOID *) pointer)); -} - - -/**************************************************************************************************/ -/**************************************************************************************************/ -/** */ -/** TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer); */ -/** */ -/**************************************************************************************************/ -/**************************************************************************************************/ -TX_EVENT_FLAGS_GROUP *_tx_misra_void_to_event_flags_pointer_convert(VOID *pointer) -{ - - /* Return event flags pointer. */ - return((TX_EVENT_FLAGS_GROUP *) ((VOID *) pointer)); -} - - -/*****************************************************************************/ -/*****************************************************************************/ -/** */ -/** ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer); */ -/** */ -/*****************************************************************************/ -/*****************************************************************************/ -ULONG *_tx_misra_void_to_ulong_pointer_convert(VOID *pointer) -{ - - /* Return a ULONG pointer. */ - return((ULONG *) ((VOID *) pointer)); -} - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ -TX_MUTEX *_tx_misra_void_to_mutex_pointer_convert(VOID *pointer) -{ - - /* Return a mutex pointer. */ - return((TX_MUTEX *) ((VOID *) pointer)); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** UINT _tx_misra_status_get(UINT status); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -UINT _tx_misra_status_get(UINT status) -{ - (VOID)status; - - /* Return a successful status. */ - return(TX_SUCCESS); -} - - -/********************************************************************************/ -/********************************************************************************/ -/** */ -/** TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer); */ -/** */ -/********************************************************************************/ -/********************************************************************************/ -TX_QUEUE *_tx_misra_void_to_queue_pointer_convert(VOID *pointer) -{ - - /* Return queue pointer. */ - return((TX_QUEUE *) ((VOID *) pointer)); -} - - -/****************************************************************************************/ -/****************************************************************************************/ -/** */ -/** TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer); */ -/** */ -/****************************************************************************************/ -/****************************************************************************************/ -TX_SEMAPHORE *_tx_misra_void_to_semaphore_pointer_convert(VOID *pointer) -{ - - /* Return semaphore pointer. */ - return((TX_SEMAPHORE *) ((VOID *) pointer)); -} - - -/**************************************************************************/ -/**************************************************************************/ -/** */ -/** VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer); */ -/** */ -/**************************************************************************/ -/**************************************************************************/ -VOID *_tx_misra_uchar_to_void_pointer_convert(UCHAR *pointer) -{ - - /* Return a VOID pointer. */ - return((VOID *) ((VOID *) pointer)); -} - - -/*********************************************************************************/ -/*********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value); */ -/** */ -/*********************************************************************************/ -/*********************************************************************************/ -TX_THREAD *_tx_misra_ulong_to_thread_pointer_convert(ULONG value) -{ - - /* Return a thread pointer. */ - return((TX_THREAD *) ((VOID *) value)); -} - - -/***************************************************************************************************/ -/***************************************************************************************************/ -/** */ -/** VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer); */ -/** */ -/***************************************************************************************************/ -/***************************************************************************************************/ -VOID *_tx_misra_timer_indirect_to_void_pointer_convert(TX_TIMER_INTERNAL **pointer) -{ - - /* Return a void pointer. */ - return((VOID *) ((VOID *) pointer)); -} - - -/***************************************************************************************/ -/***************************************************************************************/ -/** */ -/** CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer); */ -/** */ -/***************************************************************************************/ -/***************************************************************************************/ -CHAR *_tx_misra_const_char_to_char_pointer_convert(const char *pointer) -{ - - /* Return a CHAR pointer. */ - return((CHAR *) ((VOID *) pointer)); -} - - -/**********************************************************************************/ -/**********************************************************************************/ -/** */ -/** TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer); */ -/** */ -/**********************************************************************************/ -/**********************************************************************************/ -TX_THREAD *_tx_misra_void_to_thread_pointer_convert(void *pointer) -{ - - /* Return thread pointer. */ - return((TX_THREAD *) ((VOID *) pointer)); -} - - -#ifdef TX_ENABLE_EVENT_TRACE - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ -UCHAR *_tx_misra_object_to_uchar_pointer_convert(TX_TRACE_OBJECT_ENTRY *pointer) -{ - - /* Return a UCHAR pointer. */ - return((UCHAR *) ((VOID *) pointer)); -} - - -/************************************************************************************************/ -/************************************************************************************************/ -/** */ -/** TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer); */ -/** */ -/************************************************************************************************/ -/************************************************************************************************/ -TX_TRACE_OBJECT_ENTRY *_tx_misra_uchar_to_object_pointer_convert(UCHAR *pointer) -{ - - /* Return an object entry pointer. */ - return((TX_TRACE_OBJECT_ENTRY *) ((VOID *) pointer)); -} - - -/******************************************************************************************/ -/******************************************************************************************/ -/** */ -/** TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer); */ -/** */ -/******************************************************************************************/ -/******************************************************************************************/ -TX_TRACE_HEADER *_tx_misra_uchar_to_header_pointer_convert(UCHAR *pointer) -{ - - /* Return a trace header pointer. */ - return((TX_TRACE_HEADER *) ((VOID *) pointer)); -} - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ -TX_TRACE_BUFFER_ENTRY *_tx_misra_uchar_to_entry_pointer_convert(UCHAR *pointer) -{ - - /* Return a trace buffer entry pointer. */ - return((TX_TRACE_BUFFER_ENTRY *) ((VOID *) pointer)); -} - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ -UCHAR *_tx_misra_entry_to_uchar_pointer_convert(TX_TRACE_BUFFER_ENTRY *pointer) -{ - - /* Return a UCHAR pointer. */ - return((UCHAR *) ((VOID *) pointer)); -} - -#endif - - -/***********************************************************************************************/ -/***********************************************************************************************/ -/** */ -/** UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer); */ -/** */ -/***********************************************************************************************/ -/***********************************************************************************************/ -UCHAR *_tx_misra_char_to_uchar_pointer_convert(CHAR *pointer) -{ - - /* Return a UCHAR pointer. */ - return((UCHAR *) ((VOID *) pointer)); -} - - -#endif - diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.s b/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.s deleted file mode 100644 index 0e0e1f34..00000000 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.s +++ /dev/null @@ -1,14 +0,0 @@ -# 0 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.S" -# 0 "" -# 0 "" -# 1 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.S" -# 27 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.S" - .text - .align 4 - .syntax unified -# 70 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.S" - .global _tx_thread_context_restore - .thumb_func -_tx_thread_context_restore: -# 81 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_restore.S" - BX lr diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.s b/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.s deleted file mode 100644 index 9df162b0..00000000 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.s +++ /dev/null @@ -1,14 +0,0 @@ -# 0 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.S" -# 0 "" -# 0 "" -# 1 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.S" -# 23 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.S" - .text - .align 4 - .syntax unified -# 66 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.S" - .global _tx_thread_context_save - .thumb_func -_tx_thread_context_save: -# 79 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_context_save.S" - BX lr diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.s b/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.s deleted file mode 100644 index 4dd7f4d6..00000000 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.s +++ /dev/null @@ -1,22 +0,0 @@ -# 0 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S" -# 0 "" -# 0 "" -# 1 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S" -# 23 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S" - .text 32 - .align 4 - .syntax unified -# 66 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_control.S" - .global _tx_thread_interrupt_control - .thumb_func -_tx_thread_interrupt_control: - - - - - - MRS r1, PRIMASK - MSR PRIMASK, r0 - MOV r0, r1 - - BX lr diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.s b/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.s deleted file mode 100644 index 6c32084c..00000000 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.s +++ /dev/null @@ -1,167 +0,0 @@ -# 0 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S" -# 0 "" -# 0 "" -# 1 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S" -# 23 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S" - .global _tx_thread_current_ptr - .global _tx_thread_execute_ptr - .global _tx_timer_time_slice - .global _tx_execution_thread_enter - .global _tx_execution_thread_exit - - - - - .text - .align 4 - .syntax unified -# 79 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S" - .global _tx_thread_schedule - .thumb_func -_tx_thread_schedule: - - - - - - - - MOV r0, #0 - LDR r2, =_tx_thread_preempt_disable - STR r0, [r2, #0] -# 102 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S" - CPSIE i - - - - MOV r0, #0x10000000 - MOV r1, #0xE000E000 - STR r0, [r1, #0xD04] - DSB - ISB - - - -__tx_wait_here: - B __tx_wait_here - - - - - .global PendSV_Handler - .global __tx_PendSVHandler - .syntax unified - .thumb_func -PendSV_Handler: - .thumb_func -__tx_PendSVHandler: - - - -__tx_ts_handler: -# 141 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S" - LDR r0, =_tx_thread_current_ptr - LDR r2, =_tx_thread_execute_ptr - MOV r3, #0 - LDR r1, [r0] - - - - CBZ r1, __tx_ts_new - - - - STR r3, [r0] - MRS r12, PSP - STMDB r12!, {r4-r11} - - - - - - - LDR r4, =_tx_timer_time_slice - STMDB r12!, {LR} - - - - LDR r5, [r4] - STR r12, [r1, #8] - CBZ r5, __tx_ts_new - - - - STR r5, [r1, #24] - - - - STR r3, [r4] - - - -__tx_ts_new: - - - - CPSID i - LDR r1, [r2] - CBZ r1, __tx_ts_wait - - - - STR r1, [r0] - CPSIE i - - - -__tx_ts_restore: - LDR r7, [r1, #4] - LDR r4, =_tx_timer_time_slice - LDR r5, [r1, #24] - ADD r7, r7, #1 - STR r7, [r1, #4] - - - - STR r5, [r4] -# 215 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S" - LDR r12, [r1, #8] - LDMIA r12!, {LR} - - - - - - - LDMIA r12!, {r4-r11} - MSR PSP, r12 - - - - BX lr - - - - - -__tx_ts_wait: - CPSID i - LDR r1, [r2] - STR r1, [r0] - CBNZ r1, __tx_ts_ready -# 258 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_schedule.S" - CPSIE i - B __tx_ts_wait - - - - -__tx_ts_ready: - MOV r7, #0x08000000 - MOV r8, #0xE000E000 - STR r7, [r8, #0xD04] - - - - CPSIE i - B __tx_ts_restore diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.s b/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.s deleted file mode 100644 index c0e5f166..00000000 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.s +++ /dev/null @@ -1,50 +0,0 @@ -# 0 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.S" -# 0 "" -# 0 "" -# 1 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.S" -# 23 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.S" - .text - .align 4 - .syntax unified -# 68 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.S" - .global _tx_thread_stack_build - .thumb_func -_tx_thread_stack_build: -# 96 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_stack_build.S" - LDR r2, [r0, #16] - BIC r2, r2, #0x7 - SUB r2, r2, #68 - LDR r3, =0xFFFFFFFD - STR r3, [r2, #0] - - - - MOV r3, #0 - STR r3, [r2, #4] - STR r3, [r2, #8] - STR r3, [r2, #12] - STR r3, [r2, #16] - STR r3, [r2, #20] - STR r3, [r2, #24] - STR r3, [r2, #28] - STR r3, [r2, #32] - - - - STR r3, [r2, #36] - STR r3, [r2, #40] - STR r3, [r2, #44] - STR r3, [r2, #48] - STR r3, [r2, #52] - MOV r3, #0xFFFFFFFF - STR r3, [r2, #56] - STR r1, [r2, #60] - MOV r3, #0x01000000 - STR r3, [r2, #64] - - - - - STR r2, [r0, #8] - - BX lr diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.s b/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.s deleted file mode 100644 index f4275e23..00000000 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.s +++ /dev/null @@ -1,34 +0,0 @@ -# 0 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.S" -# 0 "" -# 0 "" -# 1 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.S" -# 23 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.S" - .text 32 - .align 4 - .syntax unified -# 68 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_system_return.S" - .thumb_func - .global _tx_thread_system_return -_tx_thread_system_return: - - - - - MOV r0, #0x10000000 - MOV r1, #0xE000E000 - STR r0, [r1, #0xD04] - MRS r0, IPSR - CMP r0, #0 - BNE _isr_context - - - - - - - MRS r1, PRIMASK - CPSIE i - MSR PRIMASK, r1 - -_isr_context: - BX lr diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.s b/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.s deleted file mode 100644 index 6f43f1b7..00000000 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.s +++ /dev/null @@ -1,190 +0,0 @@ -# 0 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.S" -# 0 "" -# 0 "" -# 1 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.S" -# 23 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.S" - .global _tx_timer_time_slice - .global _tx_timer_system_clock - .global _tx_timer_current_ptr - .global _tx_timer_list_start - .global _tx_timer_list_end - .global _tx_timer_expired_time_slice - .global _tx_timer_expired - .global _tx_thread_time_slice - .global _tx_timer_expiration_process - - .text - .align 4 - .syntax unified -# 83 "src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_timer_interrupt.S" - .global _tx_timer_interrupt - .thumb_func -_tx_timer_interrupt: - - - - - - - - LDR r1, =_tx_timer_system_clock - LDR r0, [r1, #0] - ADD r0, r0, #1 - STR r0, [r1, #0] - - - - - - LDR r3, =_tx_timer_time_slice - LDR r2, [r3, #0] - CBZ r2, __tx_timer_no_time_slice - - - - - - SUB r2, r2, #1 - STR r2, [r3, #0] - - - - - CBNZ r2, __tx_timer_no_time_slice - - - - - - LDR r3, =_tx_timer_expired_time_slice - MOV r0, #1 - STR r0, [r3, #0] - - - -__tx_timer_no_time_slice: - - - - - - LDR r1, =_tx_timer_current_ptr - LDR r0, [r1, #0] - LDR r2, [r0, #0] - CBZ r2, __tx_timer_no_timer - - - - - - LDR r3, =_tx_timer_expired - MOV r2, #1 - STR r2, [r3, #0] - B __tx_timer_done - - - - -__tx_timer_no_timer: - - - - - ADD r0, r0, #4 - - - - - LDR r3, =_tx_timer_list_end - LDR r2, [r3, #0] - CMP r0, r2 - BNE __tx_timer_skip_wrap - - - - - LDR r3, =_tx_timer_list_start - LDR r0, [r3, #0] - -__tx_timer_skip_wrap: - - STR r0, [r1, #0] - - -__tx_timer_done: - - - - - - LDR r3, =_tx_timer_expired_time_slice - LDR r2, [r3, #0] - CBNZ r2, __tx_something_expired - - LDR r1, =_tx_timer_expired - LDR r0, [r1, #0] - CBZ r0, __tx_timer_nothing_expired - - -__tx_something_expired: - - STMDB sp!, {r0, lr} - - - - - - - LDR r1, =_tx_timer_expired - LDR r0, [r1, #0] - CBZ r0, __tx_timer_dont_activate - - - - - - BL _tx_timer_expiration_process - - -__tx_timer_dont_activate: - - - - - - LDR r3, =_tx_timer_expired_time_slice - LDR r2, [r3, #0] - CBZ r2, __tx_timer_not_ts_expiration - - - - - - BL _tx_thread_time_slice - LDR r0, =_tx_thread_preempt_disable - LDR r1, [r0] - CBNZ r1, __tx_timer_skip_time_slice - LDR r0, =_tx_thread_current_ptr - LDR r1, [r0] - LDR r2, =_tx_thread_execute_ptr - LDR r3, [r2] - LDR r0, =0xE000ED04 - LDR r2, =0x10000000 - CMP r1, r3 - BEQ __tx_timer_skip_time_slice - STR r2, [r0] -__tx_timer_skip_time_slice: - - - -__tx_timer_not_ts_expiration: - - LDMIA sp!, {r0, lr} - - - - -__tx_timer_nothing_expired: - - DSB - BX lr diff --git a/src/Middlewares/ST/threadx/utility/low_power/low_power.md b/src/Middlewares/ST/threadx/utility/low_power/low_power.md deleted file mode 100644 index 8be714a3..00000000 --- a/src/Middlewares/ST/threadx/utility/low_power/low_power.md +++ /dev/null @@ -1,249 +0,0 @@ ---- -title: Low Power Utility -author: sclarson -ms.author: sclarson -description: This article is a summary of the Low Power utility APIs available in ThreadX. -ms.date: 03/02/2021 -ms.topic: article -ms.service: rtos ---- - -# Low Power APIs - -## Summary of Low Power APIs - -There are additional API functions available for low power, as follows: - -- ***tx_low_power_enter*** - *Enter low power mode* -- ***tx_low_power_exit*** - *Exit low power mode* -- ***tx_time_increment*** - *Increment ThreadX timers by specific amount* -- ***tx_timer_get_next*** - *Get next ThreadX timer expiration* - ---- -## User-defined Macros - -- **TX_LOW_POWER_TIMER_SETUP** - an optional macro to a user routine that sets up a low power clock. To set up a low power timer or operate ticklessly in low power mode, this must be defined. This is called in **tx_low_power_enter**. -- **TX_LOW_POWER_TICKLESS** - an optional define to operate ticklessly in low power mode. Symbol **TX_LOW_POWER_TIMER_SETUP** must also be defined. With this defined, there is no need to set up a low power timer to keep track of time. ThreadX will not maintain/update the internal tick count during or after exiting low power mode. -- **TX_LOW_POWER_USER_ENTER** - an optional macro to a user routine that configures the processor for entering low power mode (e.g. turn off peripherals and select a sleep mode). This is called in **tx_low_power_enter**. -- **TX_LOW_POWER_USER_EXIT** - an optional macro to a user routine that configures the processor for exiting low power mode (e.g. turn on peripherals). This is called in **tx_low_power_exit**. -- **TX_LOW_POWER_USER_TIMER_ADJUST** - an optional user macro to determine how much time has elapsed while in low power mode (in units of ThreadX ticks). This is called in **tx_low_power_exit** to get the number of ticks needed to adjust the ThreadX timers. - -## tx_low_power_enter - -Enter low power mode. - -### Prototype - -```c -VOID tx_low_power_enter(VOID); -``` - -### Description - -This service enters low power mode. -For keeping track of time while in low power mode, there are two possibilities: - -1. A ThreadX timer is active. Function **tx_timer_get_next** returns **TX_TRUE**. Note that in this situation, a low power clock must be used in order to wake up the CPU for the next ThreadX timer expiration. Therefore an alternative clock must be programmed. Program the hardware timer source such that the next timer interrupt is equal to: *tx_low_power_next_expiration \* tick_frequency*. The *tick_frequency* is application-specific and typically set up in **tx_low_level_initialize**. - -2. There are no ThreadX timers active. Function **tx_timer_get_next** returns **TX_FALSE**. - 1. The application may choose not to keep the ThreadX internal - tick count updated (define **TX_LOW_POWER_TICKLESS**), therefore there is no need - to set up a low power clock. - - 2. The application still needs to keep the ThreadX tick up-to-date. In this case - a low power clock needs to be set up. - -### Input parameters - -- **none** - -### Return values - -- **none** - -### Allowed from - -Internal ThreadX code, application - -### Example - -ARM assembly -```c -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_enter // Enter low power mode - POP {r0-r3} -#endif - -#ifdef TX_ENABLE_WFI - DSB // Ensure no outstanding memory transactions - WFI // Wait for interrupt - ISB // Ensure pipeline is flushed -#endif - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_exit // Exit low power mode - POP {r0-r3} -#endif -``` -### See also - -- tx_low_power_exit - ---- - -## tx_low_power_exit - -Exit low power mode. - -### Prototype - -```c -VOID tx_low_power_exit(VOID); - -``` - -### Description - -This service exits low power mode. - -### Input parameters - -- **none** - -### Return values - -- **none** - -### Allowed from - -Internal ThreadX code, application - -### Example - -```c -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_enter // Enter low power mode - POP {r0-r3} -#endif - -#ifdef TX_ENABLE_WFI - DSB // Ensure no outstanding memory transactions - WFI // Wait for interrupt - ISB // Ensure pipeline is flushed -#endif - -#ifdef TX_LOW_POWER - PUSH {r0-r3} - BL tx_low_power_exit // Exit low power mode - POP {r0-r3} -#endif -``` - -### See also - -- tx_low_power_enter - ---- - -## tx_time_increment - -This function increments the current time by a specified value. The value was derived by the application by calling the **tx_timer_get_next** function prior to this call, which was right before the processor was put in low power mode. - -### Prototype - -```c -VOID tx_time_increment(ULONG time_increment); -``` - -### Description - -This function increments the current time by a specified value. The value was derived by the application by calling the **tx_timer_get_next** function prior to this call, which was right before the processor was put in low power mode. - -### Input parameters - -- **time_increment** Number of ThreadX ticks to increment time and timers. - -### Return values - -- **none** - -### Allowed from - -Internal ThreadX code, application - -### Example - -From **tx_low_power_exit**: - -```c - /* Call the low-power timer driver code to obtain the amount of time (in ticks) - the system has been in low power mode. */ -#ifdef TX_LOW_POWER_TIMER_ADJUST - tx_low_power_adjust_ticks = TX_LOW_POWER_USER_TIMER_ADJUST; -#else - tx_low_power_adjust_ticks = (ULONG) 0; -#endif - - /* Determine if the ThreadX timer needs incrementing. */ - if (tx_low_power_adjust_ticks) - { - /* Yes, the ThreadX time must be incremented. */ - tx_time_increment(tx_low_power_adjust_ticks); - } -``` - -### See also - -- tx_timer_get_next - ---- - -## tx_timer_get_next - -Get next ThreadX timer expiration - -### Prototype - -```c -ULONG tx_timer_get_next(ULONG *next_timer_tick_ptr); -``` - -### Description - -This service gets the next ThreadX timer expiration, in ticks. - -### Input parameters - -- **next_timer_tick_ptr** pointer to hold number of ticks - -### Return values - -- **TX_TRUE** (1) At least one timer is active. -- **TX_FALSE** (0) No timers are currently active. - -### Allowed from - -Internal ThreadX code, application - -### Example - -From **tx_low_power_enter**: - -```c -ULONG tx_low_power_next_expiration; /* The next timer expiration (units of ThreadX timer ticks). */ -ULONG timers_active; - - /* At this point, we want to enter low power mode, since nothing - meaningful is going on in the system. However, in order to keep - the ThreadX timer services accurate, we must first determine the - next ThreadX timer expiration in terms of ticks. This is - accomplished via the tx_timer_get_next API. */ - timers_active = tx_timer_get_next(&tx_low_power_next_expiration); -``` - -### See also - -- tx_time_increment diff --git a/src/Middlewares/ST/usbx/LICENSE.txt b/src/Middlewares/ST/usbx/LICENSE.txt new file mode 100644 index 00000000..7fe33120 --- /dev/null +++ b/src/Middlewares/ST/usbx/LICENSE.txt @@ -0,0 +1,246 @@ +MICROSOFT SOFTWARE LICENSE TERMS + +MICROSOFT AZURE RTOS + +Shape + +These license terms are an agreement between you and Microsoft Corporation (or +one of its affiliates). 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Vous +pourriez avoir d’autres droits prévus par les lois de votre pays. Le présent +contrat ne modifie pas les droits que vous confèrent les lois de votre pays si +celles-ci ne le permettent pas. \ No newline at end of file diff --git a/src/Middlewares/ST/usbx/LICENSED-HARDWARE.txt b/src/Middlewares/ST/usbx/LICENSED-HARDWARE.txt new file mode 100644 index 00000000..5573bcb0 --- /dev/null +++ b/src/Middlewares/ST/usbx/LICENSED-HARDWARE.txt @@ -0,0 +1,37 @@ +LICENSED HARDWARE LIST + +Last Updated January 28, 2022 + +Microsoft has entered into OEM Agreements with manufacturers of the following microprocessors and +microcontrollers (the “hardware”) to enable those manufacturers to include and distribute Azure RTOS +in certain hardware. By purchasing and using hardware on this list you inherit the “Distribution and +Production Use” rights in Section 2 of the Microsoft Software License Terms for Microsoft Azure RTOS. If +hardware is not listed below, you do not have those rights. + +Manufacturer: + + STMicroelectronics + +Licensed Microcontrollers and Microprocessors: + + STM32H7 Series + + STM32U5 Series + + STM32F4 Series + + STM32L4/STM32L4+ series + + STM32G4 Series + + STM32F7 Series + + STM32L5 Series + + STM32G0 Series + + STM32WL Series + + STM32WB Series + + STM32C0 Series diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_api.h b/src/Middlewares/ST/usbx/common/core/inc/ux_api.h new file mode 100644 index 00000000..c919011e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_api.h @@ -0,0 +1,2752 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Application Interface (API) */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* APPLICATION INTERFACE DEFINITION RELEASE */ +/* */ +/* ux_api.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the basic Application Interface (API) to the */ +/* high-performance USBX real-time USB stack. All service prototypes */ +/* and data structure definitions are defined in this file. */ +/* Please note that basic data type definitions and other architecture-*/ +/* specific information is contained in the file ux_port.h. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* added query usage of device */ +/* ClassSubclassProtocol, */ +/* added option to disable FX */ +/* media integration, prefixed */ +/* UX to MS_TO_TICK, added */ +/* APIs and macros related to */ +/* uninitialize, optimized */ +/* based on compile */ +/* definitions, updated */ +/* product constants, used */ +/* host class extension */ +/* pointer for class specific */ +/* structured data, used UX */ +/* prefix to refer to TX */ +/* symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 11-09-2020 Chaoqiong Xiao Modified comment(s), */ +/* used unsigned defines, */ +/* added HCD uninit command, */ +/* modified HCD status code, */ +/* fixed compile warnings, */ +/* resulting in version 6.1.2 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* added BOS support, */ +/* resulting in version 6.1.3 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added configuration activate*/ +/* and deactivate support, */ +/* added host printer get */ +/* device ID support, */ +/* added host device string */ +/* descriptor get support, */ +/* added events for device */ +/* connection/disconnection, */ +/* resulting in version 6.1.4 */ +/* 03-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1.5 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added macros for Word/DWord */ +/* to bytes extraction, */ +/* resulting in version 6.1.6 */ +/* 06-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added trace dependency test,*/ +/* changed transfer timeout */ +/* value, */ +/* resulting in version 6.1.7 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed spelling error, */ +/* fixed trace ID order error, */ +/* resulting in version 6.1.8 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* improved assert macros, */ +/* added transfer size field, */ +/* improved traceX support, */ +/* resulting in version 6.1.9 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added too many ports error, */ +/* moved tx_api.h include and */ +/* typedefs to ux_port.h, */ +/* added standalone support, */ +/* added device HID trace IDs, */ +/* added some general errors, */ +/* added printer trace IDs, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_API_H +#define UX_API_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + +/* Include USBX port specific file. */ + +#include "ux_port.h" + +/* Process compile options: + * + * - UX_HOST_SIDE_ONLY/UX_HOST_STANDALONE: + * Must not be defined at the same time, + * When defined, only host/device side APIs are available. + * + * - UX_STANDALONE: + * Defined, whole RTOS dependencies are removed from USBX. + * + * - UX_DEVICE_STANDALONE/UX_HOST_STANDALONE + * Internal definitions for different parts, + * _DEVICE_STANDALONE removes RTOS dependencies of DCD, device stack and classes, + * _HOST_STANDALONE removes RTOS dependencies of HCD, host stack and classes, + * if UX_STANDALONE is not defined, RTOS is always enabled in system and utilities. + */ +#if defined(UX_STANDALONE) +#if !defined(UX_DEVICE_STANDALONE) +#define UX_DEVICE_STANDALONE +#endif +#if !defined(UX_HOST_STANDALONE) +#define UX_HOST_STANDALONE +#endif +#if !defined(UX_OTG_STANDALONE) +#define UX_OTG_STANDALONE +#endif +#else +#if defined(UX_DEVICE_STANDALONE) && defined(UX_HOST_STANDALONE) && defined(UX_OTG_STANDALONE) ||\ + defined(UX_DEVICE_STANDALONE) && defined(UX_DEVICE_SIDE_ONLY) ||\ + defined(UX_HOST_STANDALONE) && defined(UX_HOST_SIDE_ONLY) +#define UX_STANDALONE +#endif +#endif + + +/* Define the maximum length for class names (exclude string null-terminator). */ +#define UX_MAX_CLASS_NAME_LENGTH 63 + +/* Define the maximum length for HCD names (exclude string null-terminator). */ +#define UX_MAX_HCD_NAME_LENGTH 63 + +/* Disable warning of parameter not used. */ +#ifndef UX_PARAMETER_NOT_USED +#define UX_PARAMETER_NOT_USED(p) ((VOID)(p)) +#endif + +/* Define additional generic USBX types. */ + +#ifndef SCHAR +typedef signed char SCHAR; +#endif + +/* If the port file did not define the memory barrier instruction, define it + to nothing since this is platform-specific. */ +#ifndef UX_DATA_MEMORY_BARRIER +#define UX_DATA_MEMORY_BARRIER +#endif + + +/* This defines the ASSERT and process on ASSERT fail. */ +#ifdef UX_ENABLE_ASSERT +#ifndef UX_ASSERT_FAIL +#ifdef TX_API_H +#define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } +#else +#define UX_ASSERT_FAIL for (;;) {} +#endif +#endif +#define UX_ASSERT(s) if (!(s)) {UX_ASSERT_FAIL} +#else +#define UX_ASSERT(s) +#endif /* UX_ENABLE_ASSERT */ + + +/* Convert from millisecond to ThreadX Tick value. */ +#define UX_MS_TO_TICK(ms) ((ms) * (UX_PERIODIC_RATE) / 1000) +#define UX_MS_TO_TICK_NON_ZERO(ms) UX_MAX(1, UX_MS_TO_TICK(ms)) + +/* Deprecated, left to be compatible with apps already using MS_TO_TICK. */ +#define MS_TO_TICK(ms) UX_MS_TO_TICK(ms) + + +/* If UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE is defined, + it define USBX device max number of endpoints (1~n). + else max number of endpoints are from scan result. + It must be equal to or larger than max number of endpoints + can be activated at the same time. */ +#ifndef UX_MAX_DEVICE_ENDPOINTS +#define UX_MAX_DEVICE_ENDPOINTS 6 +#endif + +/* If UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE is defined, + it define USBX device max number of interfacess (1~n). + else max number of interfacess are from scan result. + It must be equal to or larger than max number of interfaces + in a activated configuration. */ +#ifndef UX_MAX_DEVICE_INTERFACES +#define UX_MAX_DEVICE_INTERFACES 6 +#endif + + +/* Define USBX device max bInterfaceNumber of interfaces (0 ~ n), + it must be larger than max bInterfaceNumber in USB + framework descriptors. */ +#ifndef UX_MAX_SLAVE_INTERFACES +#define UX_MAX_SLAVE_INTERFACES 16 +#endif + + +/* Define USBX max number of devices (1 ~ n). */ +#ifndef UX_MAX_DEVICES +#define UX_MAX_DEVICES 4 +#endif + +/* Define USBX max number of HCDs (1 ~ n). */ +#ifndef UX_MAX_HCD +#define UX_MAX_HCD 2 +#endif + +/* Define USBX max root hub port (1 ~ n). */ +#ifndef UX_MAX_ROOTHUB_PORT +#define UX_MAX_ROOTHUB_PORT 4 +#endif + +/* Define USBX max TT. */ +#ifndef UX_MAX_TT +#define UX_MAX_TT 8 +#endif + +/* Define USBX Host Enum Thread Stack Size. */ +#ifndef UX_HOST_ENUM_THREAD_STACK_SIZE +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +#endif + +/* Define USBX Host Thread Stack Size. */ +#ifndef UX_HOST_HCD_THREAD_STACK_SIZE +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +#endif + +/* Define USBX Host HNP Polling Thread Stack Size */ +#ifndef UX_HOST_HNP_POLLING_THREAD_STACK +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +#endif + +/* Define basic constants for the USBX Stack. */ +#define AZURE_RTOS_USBX +#define USBX_MAJOR_VERSION 6 +#define USBX_MINOR_VERSION 1 +#define USBX_PATCH_VERSION 10 + +/* Macros for concatenating tokens, where UX_CONCATn concatenates n tokens. */ + +#define UX_CONCAT_BASE(x,y) x ## y +#define UX_CONCAT2(s0,s1) UX_CONCAT_BASE(s0,s1) + +/* Static assert that can report an error at compile time. */ +#define UX_COMPILE_TIME_ASSERT(exp, meaningful_name_as_variable) \ + typedef char UX_CONCAT2(meaningful_name_as_variable, __LINE__)[!(exp) ? -1 : 1]; + +/* Arithmetic. */ + +#define UX_MIN(a, b) ((a) < (b) ? (a) : (b)) +#define UX_MAX(a, b) ((a) > (b) ? (a) : (b)) + +#define UX_W0(word) ( (word) & 0xFF) +#define UX_W1(word) (((word) >> 8) & 0xFF) + +#define UX_DW0(dword) ( (dword) & 0xFF) +#define UX_DW1(dword) (((dword) >> 8) & 0xFF) +#define UX_DW2(dword) (((dword) >> 16) & 0xFF) +#define UX_DW3(dword) (((dword) >> 24) & 0xFF) + +/* Safe arithmetic check macros. */ + +#ifndef UX_DISABLE_ARITHMETIC_CHECK + +/* Calculate and check if result overflow/underflow. */ + +#define UX_OVERFLOW_CHECK_ADD_ULONG(a, b) ((a) > 0xFFFFFFFFul - (b)) +#define UX_OVERFLOW_CHECK_ADD_USHORT(a, b) ((a) > 0xFFFFul - (b)) +#define UX_OVERFLOW_CHECK_ADD_UCHAR(a, b) ((a) > 0xFFul - (b)) + +#define UX_UNDERFLOW_CHECK_MINUS(a, b) ((a) < (b)) + +/* Overflow check optimized in case multiplying a 2nd factor of const. */ +#define UX_OVERFLOW_CHECK_MULC_ULONG(v, c) (((c) != 0) && ((v) > 0xFFFFFFFFul / (c))) +#define UX_OVERFLOW_CHECK_MULC_USHORT(v, c) (((c) != 0) && ((v) > 0xFFFFul / (c))) +#define UX_OVERFLOW_CHECK_MULC_UCHAR(v, c) (((c) != 0) && ((v) > 0xFFul / (c))) + +/* Overflow check optimized in case multiplying factors of variables and division instruction unavailable. */ +#define UX_OVERFLOW_CHECK_MULV_ULONG(v, v1) ((v) * (v1) < UX_MIN(v, v1)) +#define UX_OVERFLOW_CHECK_MULV_USHORT(v, v1) ((USHORT)((v) * (v1)) < UX_MIN(v, v1)) +#define UX_OVERFLOW_CHECK_MULV_UCHAR(v, v1) ((UCHAR)((v) * (v1)) < UX_MIN(v, v1)) + +#else + +/* There is no overflow/underflow, always 0 (false). */ + +#define UX_OVERFLOW_CHECK_ADD_ULONG(a, b) (0) +#define UX_OVERFLOW_CHECK_ADD_USHORT(a, b) (0) +#define UX_OVERFLOW_CHECK_ADD_UCHAR(a, b) (0) + +#define UX_OVERFLOW_CHECK_MULC_ULONG(v, c) (0) +#define UX_OVERFLOW_CHECK_MULC_USHORT(v, c) (0) +#define UX_OVERFLOW_CHECK_MULC_UCHAR(v, c) (0) + +#define UX_OVERFLOW_CHECK_MULV_ULONG(v, v1) (0) +#define UX_OVERFLOW_CHECK_MULV_USHORT(v, v1) (0) +#define UX_OVERFLOW_CHECK_MULV_UCHAR(v, v1) (0) +#endif + +/* Define the default extension to hold the control block for 64-bit mode. */ + +#ifndef UX_THREAD_EXTENSION_PTR_SET +#define UX_THREAD_EXTENSION_PTR_SET(a, b) +#endif + +#ifndef UX_THREAD_EXTENSION_PTR_GET +#define UX_THREAD_EXTENSION_PTR_GET(a, b, c) (a) = (b *)(c); +#endif + +#ifndef UX_TIMER_EXTENSION_PTR_SET +#define UX_TIMER_EXTENSION_PTR_SET(a, b) +#endif + +#ifndef UX_TIMER_EXTENSION_PTR_GET +#define UX_TIMER_EXTENSION_PTR_GET(a, b, c) (a) = (b *)(c); +#endif + +/* Determine if error log is enabled. */ + +#ifdef UX_ENABLE_DEBUG_LOG + +#ifndef UX_DEBUG_LOG_SIZE +#define UX_DEBUG_LOG_SIZE (1024 * 32) +#endif + +/* Map the error log macros to internal USBX function. */ + +#define UX_DEBUG_LOG(debug_location, debug_message, debug_code, debug_parameter_1, debug_parameter_2) _ux_utility_debug_log((UCHAR *) debug_location, (UCHAR *) debug_message, (ULONG) debug_code, (ULONG) debug_parameter_1, (ULONG) debug_parameter_2); + +VOID _ux_utility_debug_log(UCHAR *debug_location, UCHAR *debug_message, ULONG debug_code, ULONG debug_parameter_1, ULONG debug_parameter_2); + +/* DEBUG LOG MESSAGES SHOULD BE WRITTEN LIKE THIS IN THE CODE : */ +/* If error log is enabled, insert this error message into the log buffer. */ +/* UX_DEBUG_LOG("_ux_host_stack_rh_device_insertion", "Device insertion", port_index, port_index, 0) */ + + +#else + +/* If Log is not defined, map it to nothing so that debug messages can stay in the code. */ +#define UX_DEBUG_LOG(debug_location, debug_message, debug_code, debug_parameter_1, debug_parameter_2) +#endif + +/* Determine if tracing is enabled. */ + +#if defined(TX_ENABLE_EVENT_TRACE) && !defined(UX_STANDALONE) +#define UX_ENABLE_EVENT_TRACE +#endif + +#ifdef UX_ENABLE_EVENT_TRACE + +/* Trace is enabled. Remap calls so that interrupts can be disabled around the actual event logging. */ + +#include "tx_trace.h" + + +/* Map the trace macros to internal USBX versions so we can get interrupt protection. */ + +#define UX_TRACE_OBJECT_REGISTER(t,p,n,a,b) _ux_trace_object_register(t, (VOID *) p, (CHAR *) n, (ULONG) a, (ULONG) b); +#define UX_TRACE_OBJECT_UNREGISTER(o) _ux_trace_object_unregister((VOID *) o); +#define UX_TRACE_IN_LINE_INSERT(i,a,b,c,d,f,g,h) _ux_trace_event_insert((ULONG) i, (ULONG) a, (ULONG) b, (ULONG) c, (ULONG) d, (ULONG) f, g, h); +#define UX_TRACE_EVENT_UPDATE(e,t,i,a,b,c,d) _ux_trace_event_update((TX_TRACE_BUFFER_ENTRY *) e, (ULONG) t, (ULONG) i, (ULONG) a, (ULONG) b, (ULONG) c, (ULONG) d); + + +/* Define USBX trace prototypes. */ + +VOID _ux_trace_object_register(UCHAR object_type, VOID *object_ptr, CHAR *object_name, ULONG parameter_1, ULONG parameter_2); +VOID _ux_trace_object_unregister(VOID *object_ptr); +VOID _ux_trace_event_insert(ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4, ULONG filter, TX_TRACE_BUFFER_ENTRY **current_event, ULONG *current_timestamp); +VOID _ux_trace_event_update(TX_TRACE_BUFFER_ENTRY *event, ULONG timestamp, ULONG event_id, ULONG info_field_1, ULONG info_field_2, ULONG info_field_3, ULONG info_field_4); + + +/* Define USBX event trace constants. */ + +#define UX_TRACE_OBJECT_TYPE_BASE 20 +#define UX_TRACE_HOST_OBJECT_TYPE_DEVICE (UX_TRACE_OBJECT_TYPE_BASE + 1) +#define UX_TRACE_HOST_OBJECT_TYPE_INTERFACE (UX_TRACE_OBJECT_TYPE_BASE + 2) +#define UX_TRACE_HOST_OBJECT_TYPE_ENDPOINT (UX_TRACE_OBJECT_TYPE_BASE + 3) +#define UX_TRACE_HOST_OBJECT_TYPE_CLASS_INSTANCE (UX_TRACE_OBJECT_TYPE_BASE + 4) + +#define UX_TRACE_DEVICE_OBJECT_TYPE_DEVICE (UX_TRACE_OBJECT_TYPE_BASE + 5) +#define UX_TRACE_DEVICE_OBJECT_TYPE_INTERFACE (UX_TRACE_OBJECT_TYPE_BASE + 6) +#define UX_TRACE_DEVICE_OBJECT_TYPE_ENDPOINT (UX_TRACE_OBJECT_TYPE_BASE + 7) +#define UX_TRACE_DEVICE_OBJECT_TYPE_CLASS_INSTANCE (UX_TRACE_OBJECT_TYPE_BASE + 8) + +/* Define event filters that can be used to selectively disable certain events or groups of events. */ + +#define UX_TRACE_ALL_EVENTS 0x7F000000 /* All USBX events */ +#define UX_TRACE_ERRORS 0x01000000 /* USBX Errors events */ +#define UX_TRACE_HOST_STACK_EVENTS 0x02000000 /* USBX Host Class Events */ +#define UX_TRACE_DEVICE_STACK_EVENTS 0x04000000 /* USBX Device Class Events */ +#define UX_TRACE_HOST_CONTROLLER_EVENTS 0x08000000 /* USBX Host Controller Events */ +#define UX_TRACE_DEVICE_CONTROLLER_EVENTS 0x10000000 /* USBX Device Controllers Events */ +#define UX_TRACE_HOST_CLASS_EVENTS 0x20000000 /* USBX Host Class Events */ +#define UX_TRACE_DEVICE_CLASS_EVENTS 0x40000000 /* USBX Device Class Events */ + + +/* Define the trace events in USBX, if not defined. */ + +/* Define the USBX host stack events. */ + +#define UX_TRACE_HOST_STACK_EVENTS_BASE 600 +#define UX_TRACE_HOST_STACK_CLASS_INSTANCE_CREATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 1) /* I1 = class , I2 = class instance */ +#define UX_TRACE_HOST_STACK_CLASS_INSTANCE_DESTROY (UX_TRACE_HOST_STACK_EVENTS_BASE + 2) /* I1 = class , I2 = class instance */ +#define UX_TRACE_HOST_STACK_CONFIGURATION_DELETE (UX_TRACE_HOST_STACK_EVENTS_BASE + 3) /* I1 = configuration */ +#define UX_TRACE_HOST_STACK_CONFIGURATION_ENUMERATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 4) /* I1 = device */ +#define UX_TRACE_HOST_STACK_CONFIGURATION_INSTANCE_CREATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 5) /* I1 = configuration */ +#define UX_TRACE_HOST_STACK_CONFIGURATION_INSTANCE_DELETE (UX_TRACE_HOST_STACK_EVENTS_BASE + 6) /* I1 = configuration */ +#define UX_TRACE_HOST_STACK_CONFIGURATION_SET (UX_TRACE_HOST_STACK_EVENTS_BASE + 7) /* I1 = configuration */ +#define UX_TRACE_HOST_STACK_DEVICE_ADDRESS_SET (UX_TRACE_HOST_STACK_EVENTS_BASE + 8) /* I1 = device , I2 = device address */ +#define UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_GET (UX_TRACE_HOST_STACK_EVENTS_BASE + 9) /* I1 = device , I2 = configuration */ +#define UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_SELECT (UX_TRACE_HOST_STACK_EVENTS_BASE + 10) /* I1 = device , I2 = configuration */ +#define UX_TRACE_HOST_STACK_DEVICE_DESCRIPTOR_READ (UX_TRACE_HOST_STACK_EVENTS_BASE + 11) /* I1 = device */ +#define UX_TRACE_HOST_STACK_DEVICE_GET (UX_TRACE_HOST_STACK_EVENTS_BASE + 12) /* I1 = device index */ +#define UX_TRACE_HOST_STACK_DEVICE_REMOVE (UX_TRACE_HOST_STACK_EVENTS_BASE + 13) /* I1 = hcd , I2 = parent , I3 = port index , I4 = device */ +#define UX_TRACE_HOST_STACK_DEVICE_RESOURCE_FREE (UX_TRACE_HOST_STACK_EVENTS_BASE + 14) /* I1 = device */ +#define UX_TRACE_HOST_STACK_ENDPOINT_INSTANCE_CREATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 15) /* I1 = device , I2 = endpoint */ +#define UX_TRACE_HOST_STACK_ENDPOINT_INSTANCE_DELETE (UX_TRACE_HOST_STACK_EVENTS_BASE + 16) /* I1 = device , I2 = endpoint */ +#define UX_TRACE_HOST_STACK_ENDPOINT_RESET (UX_TRACE_HOST_STACK_EVENTS_BASE + 17) /* I1 = device , I2 = endpoint */ +#define UX_TRACE_HOST_STACK_ENDPOINT_TRANSFER_ABORT (UX_TRACE_HOST_STACK_EVENTS_BASE + 18) /* I1 = endpoint */ +#define UX_TRACE_HOST_STACK_HCD_REGISTER (UX_TRACE_HOST_STACK_EVENTS_BASE + 19) /* I1 = hcd name , I2 = parameter 1 , I3 = parameter 2 */ +#define UX_TRACE_HOST_STACK_INITIALIZE (UX_TRACE_HOST_STACK_EVENTS_BASE + 20) /* */ +#define UX_TRACE_HOST_STACK_INTERFACE_ENDPOINT_GET (UX_TRACE_HOST_STACK_EVENTS_BASE + 21) /* I1 = interface , I2 = endpoint index */ +#define UX_TRACE_HOST_STACK_INTERFACE_INSTANCE_CREATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 22) /* I1 = interface */ +#define UX_TRACE_HOST_STACK_INTERFACE_INSTANCE_DELETE (UX_TRACE_HOST_STACK_EVENTS_BASE + 23) /* I1 = interface */ +#define UX_TRACE_HOST_STACK_INTERFACE_SET (UX_TRACE_HOST_STACK_EVENTS_BASE + 24) /* I1 = interface */ +#define UX_TRACE_HOST_STACK_INTERFACE_SETTING_SELECT (UX_TRACE_HOST_STACK_EVENTS_BASE + 25) /* I1 = interface */ +#define UX_TRACE_HOST_STACK_NEW_CONFIGURATION_CREATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 26) /* I1 = device , I2 = configuration */ +#define UX_TRACE_HOST_STACK_NEW_DEVICE_CREATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 27) /* I1 = hcd , I2 = device owner , I3 = port index , I4 = device */ +#define UX_TRACE_HOST_STACK_NEW_ENDPOINT_CREATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 28) /* I1 = interface , I2 = endpoint */ +#define UX_TRACE_HOST_STACK_RH_CHANGE_PROCESS (UX_TRACE_HOST_STACK_EVENTS_BASE + 29) /* I1 = port index */ +#define UX_TRACE_HOST_STACK_RH_DEVICE_EXTRACTION (UX_TRACE_HOST_STACK_EVENTS_BASE + 30) /* I1 = hcd , I2 = port index */ +#define UX_TRACE_HOST_STACK_RH_DEVICE_INSERTION (UX_TRACE_HOST_STACK_EVENTS_BASE + 31) /* I1 = hcd , I2 = port index */ +#define UX_TRACE_HOST_STACK_TRANSFER_REQUEST (UX_TRACE_HOST_STACK_EVENTS_BASE + 32) /* I1 = device , I2 = endpoint , I3 = transfer request */ +#define UX_TRACE_HOST_STACK_TRANSFER_REQUEST_ABORT (UX_TRACE_HOST_STACK_EVENTS_BASE + 33) /* I1 = device , I2 = endpoint , I3 = transfer request */ +#define UX_TRACE_HOST_STACK_UNINITIALIZE (UX_TRACE_HOST_STACK_EVENTS_BASE + 34) /* */ +#define UX_TRACE_HOST_STACK_HCD_UNREGISTER (UX_TRACE_HOST_STACK_EVENTS_BASE + 35) /* I1 = hcd name , I2 = parameter 1 , I3 = parameter 2 */ +#define UX_TRACE_HOST_STACK_CLASS_REGISTER (UX_TRACE_HOST_STACK_EVENTS_BASE + 36) /* I1 = class name , I2 = entry function */ +#define UX_TRACE_HOST_STACK_CLASS_UNREGISTER (UX_TRACE_HOST_STACK_EVENTS_BASE + 37) /* I1 = class entry */ +#define UX_TRACE_HOST_STACK_DEVICE_STRING_GET (UX_TRACE_HOST_STACK_EVENTS_BASE + 38) /* I1 = device , I2 = buffer , I3 = length , I4 = (langID<<16) | index */ +#define UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_ACTIVATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 39) /* I1 = device , I2 = configuration */ +#define UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_DEACTIVATE (UX_TRACE_HOST_STACK_EVENTS_BASE + 40) /* I1 = device , I2 = configuration */ + +/* Define the USBX host class events. */ + +#define UX_TRACE_HOST_CLASS_EVENTS_BASE 650 +#define UX_TRACE_HOST_CLASS_ASIX_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 1) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_ASIX_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 2) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_ASIX_INTERRUPT_NOTIFICATION (UX_TRACE_HOST_CLASS_EVENTS_BASE + 3) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_ASIX_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 4) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_ASIX_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 5) /* I1 = class instance , I2 = data pointer , I3 = requested length */ + +#define UX_TRACE_HOST_CLASS_AUDIO_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 10) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_AUDIO_CONTROL_VALUE_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 11) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_AUDIO_CONTROL_VALUE_SET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 12) /* I1 = class instance , I2 = audio control */ +#define UX_TRACE_HOST_CLASS_AUDIO_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 13) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_AUDIO_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 14) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_AUDIO_STREAMING_SAMPLING_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 15) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_AUDIO_STREAMING_SAMPLING_SET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 16) /* I1 = class instance , I2 = audio sampling */ +#define UX_TRACE_HOST_CLASS_AUDIO_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 17) /* I1 = class instance , I2 = data pointer , I3 = requested length */ + +#define UX_TRACE_HOST_CLASS_CDC_ACM_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 20) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 21) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_IOCTL_SET_LINE_CODING (UX_TRACE_HOST_CLASS_EVENTS_BASE + 22) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_IOCTL_GET_LINE_CODING (UX_TRACE_HOST_CLASS_EVENTS_BASE + 23) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_IOCTL_SET_LINE_STATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 24) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_IOCTL_SEND_BREAK (UX_TRACE_HOST_CLASS_EVENTS_BASE + 25) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_IOCTL_ABORT_IN_PIPE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 26) /* I1 = class instance , I2 = endpoint */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_IOCTL_ABORT_OUT_PIPE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 27) /* I1 = class instance , I2 = endpointr */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_IOCTL_NOTIFICATION_CALLBACK (UX_TRACE_HOST_CLASS_EVENTS_BASE + 28) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_IOCTL_GET_DEVICE_STATUS (UX_TRACE_HOST_CLASS_EVENTS_BASE + 29) /* I1 = class instance , I2 = device status */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 30) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_RECEPTION_START (UX_TRACE_HOST_CLASS_EVENTS_BASE + 31) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_RECEPTION_STOP (UX_TRACE_HOST_CLASS_EVENTS_BASE + 32) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_CDC_ACM_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 33) /* I1 = class instance , I2 = data pointer , I3 = requested length */ + +#define UX_TRACE_HOST_CLASS_CDC_ECM_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 35) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_CDC_ECM_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 36) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_CDC_ECM_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 37) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_CDC_ECM_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 38) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_CDC_ECM_INTERRUPT_NOTIFICATION (UX_TRACE_HOST_CLASS_EVENTS_BASE + 39) /* I1 = class instance */ + +#define UX_TRACE_HOST_CLASS_HID_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 40) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_HID_CLIENT_REGISTER (UX_TRACE_HOST_CLASS_EVENTS_BASE + 41) /* I1 = hid client name */ +#define UX_TRACE_HOST_CLASS_HID_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 42) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_HID_IDLE_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 43) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_HID_IDLE_SET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 44) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_HID_KEYBOARD_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 45) /* I1 = class instance , I2 = hid client instance */ +#define UX_TRACE_HOST_CLASS_HID_KEYBOARD_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 46) /* I1 = class instance , I2 = hid client instance */ +#define UX_TRACE_HOST_CLASS_HID_MOUSE_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 47) /* I1 = class instance , I2 = hid client instance */ +#define UX_TRACE_HOST_CLASS_HID_MOUSE_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 48) /* I1 = class instance , I2 = hid client instance */ +#define UX_TRACE_HOST_CLASS_HID_REMOTE_CONTROL_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 49) /* I1 = class instance , I2 = hid client instance */ +#define UX_TRACE_HOST_CLASS_HID_REMOTE_CONTROL_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 50) /* I1 = class instance , I2 = hid client instance */ +#define UX_TRACE_HOST_CLASS_HID_REPORT_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 51) /* I1 = class instance , I2 = client report */ +#define UX_TRACE_HOST_CLASS_HID_REPORT_SET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 52) /* I1 = class instance , I2 = client report */ +#define UX_TRACE_HOST_CLASS_HID_REMOTE_CONTROL_CALLBACK (UX_TRACE_HOST_CLASS_EVENTS_BASE + 53) /* I1 = client instance , I2 = remote control instance */ + +#define UX_TRACE_HOST_CLASS_HUB_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 60) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_HUB_CHANGE_DETECT (UX_TRACE_HOST_CLASS_EVENTS_BASE + 62) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_HUB_PORT_CHANGE_CONNECTION_PROCESS (UX_TRACE_HOST_CLASS_EVENTS_BASE + 63) /* I1 = class instance , I2 = port , I3 = port status */ +#define UX_TRACE_HOST_CLASS_HUB_PORT_CHANGE_ENABLE_PROCESS (UX_TRACE_HOST_CLASS_EVENTS_BASE + 64) /* I1 = class instance , I2 = port , I3 = port status */ +#define UX_TRACE_HOST_CLASS_HUB_PORT_CHANGE_OVER_CURRENT_PROCESS (UX_TRACE_HOST_CLASS_EVENTS_BASE + 65) /* I1 = class instance , I2 = port , I3 = port status */ +#define UX_TRACE_HOST_CLASS_HUB_PORT_CHANGE_RESET_PROCESS (UX_TRACE_HOST_CLASS_EVENTS_BASE + 66) /* I1 = class instance , I2 = port , I3 = port status */ +#define UX_TRACE_HOST_CLASS_HUB_PORT_CHANGE_SUSPEND_PROCESS (UX_TRACE_HOST_CLASS_EVENTS_BASE + 67) /* I1 = class instance , I2 = port , I3 = port status */ +#define UX_TRACE_HOST_CLASS_HUB_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 68) /* I1 = class instance */ + +#define UX_TRACE_HOST_CLASS_PIMA_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 70) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PIMA_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 71) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PIMA_DEVICE_INFO_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 72) /* I1 = class instance , I2 = pima device */ +#define UX_TRACE_HOST_CLASS_PIMA_DEVICE_RESET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 73) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PIMA_NOTIFICATION (UX_TRACE_HOST_CLASS_EVENTS_BASE + 74) /* I1 = class instance , I2 = event code , I3 = transaction ID , I4 = parameter1 */ +#define UX_TRACE_HOST_CLASS_PIMA_NUM_OBJECTS_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 75) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_CLOSE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 76) /* I1 = class instance , I2 = object */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_COPY (UX_TRACE_HOST_CLASS_EVENTS_BASE + 77) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_DELETE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 78) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 79) /* I1 = class instance , I2 = object handle , I3 = object */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_INFO_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 80) /* I1 = class instance , I2 = object handle , I3 = object */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_INFO_SEND (UX_TRACE_HOST_CLASS_EVENTS_BASE + 81) /* I1 = class instance , I2 = object */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_MOVE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 82) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_SEND (UX_TRACE_HOST_CLASS_EVENTS_BASE + 83) /* I1 = class instance , I2 = object , I3 = object_buffer , I4 = object length */ +#define UX_TRACE_HOST_CLASS_PIMA_OBJECT_TRANSFER_ABORT (UX_TRACE_HOST_CLASS_EVENTS_BASE + 84) /* I1 = class instance , I2 = object handle , I3 = object */ +#define UX_TRACE_HOST_CLASS_PIMA_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 85) /* I1 = class instance , I2 = data pointer , I3 = data length */ +#define UX_TRACE_HOST_CLASS_PIMA_REQUEST_CANCEL (UX_TRACE_HOST_CLASS_EVENTS_BASE + 86) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PIMA_SESSION_CLOSE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 87) /* I1 = class instance , I2 = pima session */ +#define UX_TRACE_HOST_CLASS_PIMA_SESSION_OPEN (UX_TRACE_HOST_CLASS_EVENTS_BASE + 88) /* I1 = class instance , I2 = pima session */ +#define UX_TRACE_HOST_CLASS_PIMA_STORAGE_IDS_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 89) /* I1 = class instance , I2 = storage ID array, I3 = storage ID length */ +#define UX_TRACE_HOST_CLASS_PIMA_STORAGE_INFO_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 90) /* I1 = class instance , I2 = storage ID , I3 = storage */ +#define UX_TRACE_HOST_CLASS_PIMA_THUMB_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 91) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_HOST_CLASS_PIMA_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 92) /* I1 = class instance , I2 = data pointer , I3 = data length */ + +#define UX_TRACE_HOST_CLASS_PRINTER_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 100) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PRINTER_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 101) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PRINTER_NAME_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 102) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PRINTER_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 103) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_PRINTER_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 104) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_PRINTER_SOFT_RESET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 105) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PRINTER_STATUS_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 106) /* I1 = class instance , I2 = printer status */ +#define UX_TRACE_HOST_CLASS_PRINTER_DEVICE_ID_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 107) /* I1 = class instance , I2 = printer , I3 = data pointer , I4 = buffer length */ + +#define UX_TRACE_HOST_CLASS_PROLIFIC_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 110) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 111) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_SET_LINE_CODING (UX_TRACE_HOST_CLASS_EVENTS_BASE + 112) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_GET_LINE_CODING (UX_TRACE_HOST_CLASS_EVENTS_BASE + 113) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_SET_LINE_STATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 114) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_PURGE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 115) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_SEND_BREAK (UX_TRACE_HOST_CLASS_EVENTS_BASE + 116) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_ABORT_IN_PIPE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 117) /* I1 = class instance , I2 = endpoint */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_ABORT_OUT_PIPE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 118) /* I1 = class instance , I2 = endpointr */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_REPORT_DEVICE_STATUS_CHANGE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 119) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_IOCTL_GET_DEVICE_STATUS (UX_TRACE_HOST_CLASS_EVENTS_BASE + 120) /* I1 = class instance , I2 = device status */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 121) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_RECEPTION_START (UX_TRACE_HOST_CLASS_EVENTS_BASE + 122) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_RECEPTION_STOP (UX_TRACE_HOST_CLASS_EVENTS_BASE + 123) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_PROLIFIC_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 124) /* I1 = class instance , I2 = data pointer , I3 = requested length */ + +#define UX_TRACE_HOST_CLASS_STORAGE_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 130) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_STORAGE_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 131) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_STORAGE_MEDIA_CAPACITY_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 132) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_STORAGE_MEDIA_FORMAT_CAPACITY_GET (UX_TRACE_HOST_CLASS_EVENTS_BASE + 133) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_STORAGE_MEDIA_MOUNT (UX_TRACE_HOST_CLASS_EVENTS_BASE + 134) /* I1 = class instance , I2 = sector */ +#define UX_TRACE_HOST_CLASS_STORAGE_MEDIA_OPEN (UX_TRACE_HOST_CLASS_EVENTS_BASE + 135) /* I1 = class instance , I2 = media */ +#define UX_TRACE_HOST_CLASS_STORAGE_MEDIA_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 136) /* I1 = class instance , I2 = sector start , I3 = sector count , I4 = data pointer */ +#define UX_TRACE_HOST_CLASS_STORAGE_MEDIA_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 137) /* I1 = class instance , I2 = sector start , I3 = sector count , I4 = data pointer */ +#define UX_TRACE_HOST_CLASS_STORAGE_REQUEST_SENSE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 138) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_STORAGE_START_STOP (UX_TRACE_HOST_CLASS_EVENTS_BASE + 139) /* I1 = class instance , I2 = start stop signal */ +#define UX_TRACE_HOST_CLASS_STORAGE_UNIT_READY_TEST (UX_TRACE_HOST_CLASS_EVENTS_BASE + 140) /* I1 = class instance */ + +#define UX_TRACE_HOST_CLASS_DPUMP_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 150) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_DPUMP_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 151) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_DPUMP_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 152) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_DPUMP_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 153) /* I1 = class instance , I2 = data pointer , I3 = requested length */ + +#define UX_TRACE_HOST_CLASS_SWAR_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 160) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_SWAR_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 161) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_SWAR_IOCTL_ABORT_IN_PIPE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 162) /* I1 = class instance , I2 = endpoint */ +#define UX_TRACE_HOST_CLASS_SWAR_IOCTL_ABORT_OUT_PIPE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 163) /* I1 = class instance , I2 = endpointr */ +#define UX_TRACE_HOST_CLASS_SWAR_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 164) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_SWAR_RECEPTION_START (UX_TRACE_HOST_CLASS_EVENTS_BASE + 165) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_SWAR_RECEPTION_STOP (UX_TRACE_HOST_CLASS_EVENTS_BASE + 166) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_SWAR_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 167) /* I1 = class instance , I2 = data pointer , I3 = requested length */ + +#define UX_TRACE_HOST_CLASS_GSER_ACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 170) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_GSER_DEACTIVATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 171) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_SET_LINE_CODING (UX_TRACE_HOST_CLASS_EVENTS_BASE + 172) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_GET_LINE_CODING (UX_TRACE_HOST_CLASS_EVENTS_BASE + 173) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_SET_LINE_STATE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 174) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_PURGE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 175) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_SEND_BREAK (UX_TRACE_HOST_CLASS_EVENTS_BASE + 176) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_ABORT_IN_PIPE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 177) /* I1 = class instance , I2 = endpoint */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_ABORT_OUT_PIPE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 178) /* I1 = class instance , I2 = endpointr */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_REPORT_DEVICE_STATUS_CHANGE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 179) /* I1 = class instance , I2 = parameter */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_GET_DEVICE_STATUS (UX_TRACE_HOST_CLASS_EVENTS_BASE + 180) /* I1 = class instance , I2 = device status */ +#define UX_TRACE_HOST_CLASS_GSER_IOCTL_NOTIFICATION_CALLBACK (UX_TRACE_HOST_CLASS_EVENTS_BASE + 181) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_GSER_READ (UX_TRACE_HOST_CLASS_EVENTS_BASE + 182) /* I1 = class instance , I2 = data pointer , I3 = requested length */ +#define UX_TRACE_HOST_CLASS_GSER_RECEPTION_START (UX_TRACE_HOST_CLASS_EVENTS_BASE + 183) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_GSER_RECEPTION_STOP (UX_TRACE_HOST_CLASS_EVENTS_BASE + 184) /* I1 = class instance */ +#define UX_TRACE_HOST_CLASS_GSER_WRITE (UX_TRACE_HOST_CLASS_EVENTS_BASE + 185) /* I1 = class instance , I2 = data pointer , I3 = requested length */ + +/* Define the USBX device stack events. */ + +#define UX_TRACE_DEVICE_STACK_EVENTS_BASE 850 +#define UX_TRACE_DEVICE_STACK_ALTERNATE_SETTING_GET (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 1) /* I1 = interface value */ +#define UX_TRACE_DEVICE_STACK_ALTERNATE_SETTING_SET (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 2) /* I1 = interface value , I2 = alternate setting value */ +#define UX_TRACE_DEVICE_STACK_CLASS_REGISTER (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 3) /* I1 = class name , I2 = interface number, I3 = parameter */ +#define UX_TRACE_DEVICE_STACK_CLEAR_FEATURE (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 4) /* I1 = request type , I2 = request value , I3 = request index */ +#define UX_TRACE_DEVICE_STACK_CONFIGURATION_GET (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 5) /* I1 = configuration value */ +#define UX_TRACE_DEVICE_STACK_CONFIGURATION_SET (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 6) /* I1 = configuration value */ +#define UX_TRACE_DEVICE_STACK_CONNECT (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 7) /* */ +#define UX_TRACE_DEVICE_STACK_DESCRIPTOR_SEND (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 8) /* I1 = descriptor type , I2 = request index */ +#define UX_TRACE_DEVICE_STACK_DISCONNECT (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 9) /* I1 = device */ +#define UX_TRACE_DEVICE_STACK_ENDPOINT_STALL (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 10) /* I1 = endpoint */ +#define UX_TRACE_DEVICE_STACK_GET_STATUS (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 11) /* I1 = request type , I2 = request value , I3 = request index */ +#define UX_TRACE_DEVICE_STACK_HOST_WAKEUP (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 12) /* */ +#define UX_TRACE_DEVICE_STACK_INITIALIZE (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 13) /* */ +#define UX_TRACE_DEVICE_STACK_INTERFACE_DELETE (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 14) /* I1 = interface */ +#define UX_TRACE_DEVICE_STACK_INTERFACE_GET (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 15) /* I1 = interface value */ +#define UX_TRACE_DEVICE_STACK_INTERFACE_SET (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 16) /* I1 = alternate setting value */ +#define UX_TRACE_DEVICE_STACK_SET_FEATURE (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 17) /* I1 = request value , I2 = request index */ +#define UX_TRACE_DEVICE_STACK_TRANSFER_ABORT (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 18) /* I1 = transfer request, I2 = completion code */ +#define UX_TRACE_DEVICE_STACK_TRANSFER_ALL_REQUEST_ABORT (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 19) /* I1 = endpoint , I2 = completion code */ +#define UX_TRACE_DEVICE_STACK_TRANSFER_REQUEST (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 20) /* I1 = transfer request */ +#define UX_TRACE_DEVICE_STACK_MICROSOFT_EXTENSION_REGISTER (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 21) /* I1 = transfer request */ +#define UX_TRACE_DEVICE_STACK_CLASS_UNREGISTER (UX_TRACE_DEVICE_STACK_EVENTS_BASE + 22) /* I1 = class name */ + +/* Define the USBX device stack events first. */ + +#define UX_TRACE_DEVICE_CLASS_EVENTS_BASE 900 +#define UX_TRACE_DEVICE_CLASS_DPUMP_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 1) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_DPUMP_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 2) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_DPUMP_READ (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 3) /* I1 = class instance , I2 = buffer , I3 = requested_length */ +#define UX_TRACE_DEVICE_CLASS_DPUMP_WRITE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 4) /* I1 = class instance , I2 = buffer , I3 = requested_length */ +#define UX_TRACE_DEVICE_CLASS_DPUMP_CHANGE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 5) /* I1 = class instance , I2 = buffer , I3 = requested_length */ + +#define UX_TRACE_DEVICE_CLASS_CDC_ACM_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 10) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_CDC_ACM_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 11) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_CDC_ACM_READ (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 12) /* I1 = class instance , I2 = buffer , I3 = requested_length */ +#define UX_TRACE_DEVICE_CLASS_CDC_ACM_WRITE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 13) /* I1 = class instance , I2 = buffer , I3 = requested_length */ + +#define UX_TRACE_DEVICE_CLASS_HID_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 20) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_HID_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 21) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_HID_EVENT_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 22) /* I1 = class instance , I2 = hid event */ +#define UX_TRACE_DEVICE_CLASS_HID_EVENT_SET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 23) /* I1 = class instance , I2 = hid event */ +#define UX_TRACE_DEVICE_CLASS_HID_REPORT_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 24) /* I1 = class instance , I2 = descriptor type , I3 = request index */ +#define UX_TRACE_DEVICE_CLASS_HID_REPORT_SET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 25) /* I1 = class instance , I2 = descriptor type , I3 = request index */ +#define UX_TRACE_DEVICE_CLASS_HID_DESCRIPTOR_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 26) /* I1 = class instance , I2 = descriptor type , I3 = request index */ +#define UX_TRACE_DEVICE_CLASS_HID_READ (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 27) /* I1 = class instance , I2 = buffer , I3 = requested_length */ +#define UX_TRACE_DEVICE_CLASS_HID_RECEIVER_EVENT_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 28) /* I1 = class instance , I2 = receiver event , I3 = wait_option */ +#define UX_TRACE_DEVICE_CLASS_HID_RECEIVER_EVENT_FREE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 29) /* I1 = class instance , I2 = receiver event */ + +#define UX_TRACE_DEVICE_CLASS_PIMA_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 30) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 31) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_DEVICE_INFO_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 32) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_EVENT_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 33) /* I1 = class instance , I2 = pima event */ +#define UX_TRACE_DEVICE_CLASS_PIMA_EVENT_SET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 34) /* I1 = class instance , I2 = pima event */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECT_ADD (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 35) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECT_DATA_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 36) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECT_DATA_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 37) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECT_DELETE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 38) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECT_HANDLES_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 39) /* I1 = class instance , I2 = storage id , I3 = object format code, I4 = object association */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECT_INFO_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 40) /* I1 = class instance , I2 = object handle */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECT_INFO_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 41) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECTS_NUMBER_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 42) /* I1 = class instance , I2 = storage id , I3 = object format code, I4 = object association */ +#define UX_TRACE_DEVICE_CLASS_PIMA_PARTIAL_OBJECT_DATA_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 43) /* I1 = class instance , I2 = object handle , I3 = offset requested , I4 = length requested */ +#define UX_TRACE_DEVICE_CLASS_PIMA_RESPONSE_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 44) /* I1 = class instance , I2 = response code , I3 = number parameter , I4 = pima parameter 1 */ +#define UX_TRACE_DEVICE_CLASS_PIMA_STORAGE_ID_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 45) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_STORAGE_INFO_SEND (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 46) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_GET_DEVICE_PROP_DESC_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 47) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_GET_DEVICE_PROP_VALUE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 48) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_GET_DEVICE_PROP_VALUE_SET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 49) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_GET_OBJECT_PROP_DESC (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 50) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_GET_OBJECT_PROP_VALUE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 51) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECTS_PROPS_SUPPORTED_GET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 52) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_GET_OBJECT_REFERENCES (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 53) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_OBJECTS_PROPS_SUPPORTED_SET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 54) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_SET_OBJECT_REFERENCES (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 55) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_STORAGE_FORMAT (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 56) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_DEVICE_RESET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 57) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PIMA_SET_OBJECT_PROP_VALUE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 58) /* I1 = class instance */ + +#define UX_TRACE_DEVICE_CLASS_RNDIS_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 60) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_RNDIS_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 61) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_RNDIS_PACKET_RECEIVE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 62) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_RNDIS_PACKET_TRANSMIT (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 63) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_RNDIS_MSG_QUERY (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 64) /* I1 = class instance , I2 = rndis OID */ +#define UX_TRACE_DEVICE_CLASS_RNDIS_MSG_KEEP_ALIVE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 65) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_RNDIS_MSG_RESET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 66) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_RNDIS_MSG_SET (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 67) /* I1 = class instance , I2 = rndis OID */ + +#define UX_TRACE_DEVICE_CLASS_STORAGE_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 70) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 71) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_FORMAT (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 72) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_INQUIRY (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 73) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_MODE_SELECT (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 74) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_MODE_SENSE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 75) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_PREVENT_ALLOW_MEDIA_REMOVAL (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 76) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_READ (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 77) /* I1 = class instance , I2 = lun , I3 = sector , I4 = number sectors */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_READ_CAPACITY (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 78) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_READ_FORMAT_CAPACITY (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 79) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_READ_TOC (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 80) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_REQUEST_SENSE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 81) /* I1 = class instance , I2 = lun , I3 = sense key , I4 = code */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_TEST_READY (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 82) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_START_STOP (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 83) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_VERIFY (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 84) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_WRITE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 85) /* I1 = class instance , I2 = lun , I3 = sector , I4 = number sectors */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_GET_CONFIGURATION (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 86) /* I1 = class instance , I2 = lun */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_SYNCHRONIZE_CACHE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 87) /* I1 = class instance , I2 = lun , I3 = sector , I4 = number sectors */ +#define UX_TRACE_DEVICE_CLASS_STORAGE_OTHER (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 88) /* I1 = class instance , I2 = lun */ + +#define UX_TRACE_DEVICE_CLASS_CDC_ECM_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 90) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_CDC_ECM_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 91) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_CDC_ECM_CHANGE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 92) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_CDC_ECM_READ (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 93) /* I1 = class instance , I2 = buffer , I3 = requested_length */ +#define UX_TRACE_DEVICE_CLASS_CDC_ECM_WRITE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 94) /* I1 = class instance , I2 = buffer , I3 = requested_length */ +#define UX_TRACE_DEVICE_CLASS_CDC_ECM_PACKET_TRANSMIT (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 95) /* I1 = class instance , I2 = buffer , I3 = requested_length */ +#define UX_TRACE_DEVICE_CLASS_CDC_ECM_PACKET_RECEIVE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 96) /* I1 = class instance , I2 = buffer , I3 = requested_length */ + +#define UX_TRACE_DEVICE_CLASS_DFU_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 97) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_DFU_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 98) /* I1 = class instance */ + +#define UX_TRACE_DEVICE_CLASS_PRINTER_ACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 100) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PRINTER_DEACTIVATE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 101) /* I1 = class instance */ +#define UX_TRACE_DEVICE_CLASS_PRINTER_READ (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 102) /* I1 = class instance , I2 = buffer , I3 = requested_length */ +#define UX_TRACE_DEVICE_CLASS_PRINTER_WRITE (UX_TRACE_DEVICE_CLASS_EVENTS_BASE + 103) /* I1 = class instance , I2 = buffer , I3 = requested_length */ + +/* Define the USBX Error Event. */ + +#define UX_TRACE_ERROR 999 + + +#else +#define UX_TRACE_OBJECT_REGISTER(t,p,n,a,b) +#define UX_TRACE_OBJECT_UNREGISTER(o) +#define UX_TRACE_IN_LINE_INSERT(i,a,b,c,d,f,g,h) +#define UX_TRACE_EVENT_UPDATE(e,t,i,a,b,c,d) +#endif + + +/* Define the system level for error trapping. */ +#define UX_SYSTEM_LEVEL_INTERRUPT 1 +#define UX_SYSTEM_LEVEL_THREAD 2 + +/* Define the system context for error trapping. */ +#define UX_SYSTEM_CONTEXT_HCD 1 +#define UX_SYSTEM_CONTEXT_DCD 2 +#define UX_SYSTEM_CONTEXT_INIT 3 +#define UX_SYSTEM_CONTEXT_ENUMERATOR 4 +#define UX_SYSTEM_CONTEXT_ROOT_HUB 5 +#define UX_SYSTEM_CONTEXT_HUB 6 +#define UX_SYSTEM_CONTEXT_CLASS 7 +#define UX_SYSTEM_CONTEXT_UTILITY 8 +#define UX_SYSTEM_CONTEXT_DEVICE_STACK 9 +#define UX_SYSTEM_CONTEXT_HOST_STACK 10 + + +/* Defines the number of ThreadX timer ticks per seconds. By default, the ThreadX timer tick is 10ms, + so the default value for this constant is 100. If TX_TIMER_TICKS_PER_SECOND is defined, + this value is derived from TX_TIMER_TICKS_PER_SECOND. */ + +#ifndef UX_PERIODIC_RATE +#ifdef TX_TIMER_TICKS_PER_SECOND +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) +#else +#define UX_PERIODIC_RATE 100 +#endif +#endif + + +/* Define interrupts lockout constructs to protect the memory allocation/release which could happen + under ISR in the device stack. */ + +#ifndef UX_INTERRUPT_SAVE_AREA +#ifdef TX_INTERRUPT_SAVE_AREA +#define UX_INTERRUPT_SAVE_AREA TX_INTERRUPT_SAVE_AREA +#else +#define UX_INTERRUPT_SAVE_AREA ALIGN_TYPE saved_flags; +#endif +#endif + +#ifndef UX_DISABLE +#ifdef TX_DISABLE +#define UX_DISABLE TX_DISABLE +#else +#define UX_DISABLE saved_flags = _ux_utility_interrupt_disable(); +#endif +#endif + +#ifndef UX_RESTORE +#ifdef TX_RESTORE +#define UX_RESTORE TX_RESTORE +#else +#define UX_RESTORE _ux_utility_interrupt_restore(saved_flags); +#endif +#endif + +#ifndef UX_INT_SAVE_AREA /* Backword compatible. */ +#define UX_INT_SAVE_AREA UX_INTERRUPT_SAVE_AREA +#endif +#ifndef UX_DISABLE_INTS /* Backword compatible. */ +#define UX_DISABLE_INTS UX_DISABLE +#endif +#ifndef UX_RESTORE_INTS /* Backword compatible. */ +#define UX_RESTORE_INTS UX_RESTORE +#endif + + +/* Define thread/timer related things. */ + +#ifndef UX_EMPTY +#ifdef TX_EMPTY +#define UX_EMPTY TX_EMPTY +#else +#define UX_EMPTY (0) +#endif +#endif + +#ifndef UX_TIMER +#ifdef TX_API_H +#define UX_TIMER TX_TIMER +#endif +#endif + +#ifndef UX_THREAD +#ifdef TX_API_H +#define UX_THREAD TX_THREAD +#endif +#endif + +#ifndef UX_AUTO_START +#ifdef TX_AUTO_START +#define UX_AUTO_START TX_AUTO_START +#else +#define UX_AUTO_START (1ul) +#endif +#endif + +#ifndef UX_DONT_START +#ifdef TX_DONT_START +#define UX_DONT_START TX_DONT_START +#else +#define UX_DONT_START (0ul) +#endif +#endif + +#ifndef UX_AUTO_ACTIVATE +#ifdef TX_AUTO_ACTIVATE +#define UX_AUTO_ACTIVATE TX_AUTO_ACTIVATE +#else +#define UX_AUTO_ACTIVATE (1ul) +#endif +#endif + +#ifndef UX_NO_ACTIVATE +#ifdef TX_NO_ACTIVATE +#define UX_NO_ACTIVATE TX_NO_ACTIVATE +#else +#define UX_NO_ACTIVATE (0ul) +#endif +#endif + +#ifndef UX_THREAD_GET_SYSTEM_STATE +#define UX_THREAD_GET_SYSTEM_STATE TX_THREAD_GET_SYSTEM_STATE +#endif + +#ifndef UX_WAIT_FOREVER +#ifdef TX_WAIT_FOREVER +#define UX_WAIT_FOREVER TX_WAIT_FOREVER +#else +#define UX_WAIT_FOREVER (0xFFFFFFFFul) +#endif +#endif + +#ifndef UX_NO_WAIT +#ifdef TX_NO_WAIT +#define UX_NO_WAIT TX_NO_WAIT +#else +#define UX_NO_WAIT (0ul) +#endif +#endif + +#ifndef UX_NO_TIME_SLICE +#ifdef TX_NO_TIME_SLICE +#define UX_NO_TIME_SLICE TX_NO_TIME_SLICE +#else +#define UX_NO_TIME_SLICE (0ul) +#endif +#endif + + +/* Define semaphore related things. */ + +#ifndef UX_SEMAPHORE +#ifdef TX_API_H +#define UX_SEMAPHORE TX_SEMAPHORE +#endif +#endif + + +/* Define mutex related things. */ + +#ifndef UX_MUTEX +#ifdef TX_API_H +#define UX_MUTEX TX_MUTEX +#endif +#endif + + +/* Define event flags group related things. */ + +#ifndef UX_EVENT_FLAGS_GROUP +#ifdef TX_API_H +#define UX_EVENT_FLAGS_GROUP TX_EVENT_FLAGS_GROUP +#endif +#endif + +#ifndef UX_OR_CLEAR +#ifdef TX_OR_CLEAR +#define UX_OR_CLEAR TX_OR_CLEAR +#else +#define UX_OR_CLEAR (1u) +#endif +#endif + +#ifndef UX_OR +#ifdef TX_OR +#define UX_OR TX_OR +#else +#define UX_OR (0u) +#endif +#endif + +#ifndef UX_AND_CLEAR +#ifdef TX_AND_CLEAR +#define UX_AND_CLEAR TX_AND_CLEAR +#else +#define UX_AND_CLEAR (3u) +#endif +#endif + +#ifndef UX_AND +#ifdef TX_AND +#define UX_AND TX_AND +#else +#define UX_AND (2u) +#endif +#endif + +#ifndef UX_NO_EVENTS +#ifdef TX_NO_EVENTS +#define UX_NO_EVENTS TX_NO_EVENTS +#else +#define UX_NO_EVENTS (7u) +#endif +#endif + + +/* Define basic USBX constants. */ + +#define UX_NULL ((void*)0) +#define UX_INVALID_PTR ((void*)(~((ALIGN_TYPE)0))) +#define UX_TRUE 1u +#define UX_FALSE 0u +#define UX_TT_MASK 0x1FFu +#define UX_TT_BANDWIDTH 6000u +#define UX_SLAVE_ENDPOINT_DEFAULT_BUFFER_SIZE 256u + +#define UX_MAX_BYTES_PER_FRAME_FS 1157u +#define UX_MAX_BYTES_PER_MICROFRAME_HS 5785u + +/* Define USBX command request constants. */ + +#define UX_SETUP_REQUEST_TYPE 0u +#define UX_SETUP_REQUEST 1u +#define UX_SETUP_VALUE 2u +#define UX_SETUP_INDEX 4u +#define UX_SETUP_LENGTH 6u +#define UX_SETUP_SIZE 8u + + +/* Define USBX standard commands. */ + +#define UX_GET_STATUS 0u +#define UX_CLEAR_FEATURE 1u +#define UX_SET_FEATURE 3u +#define UX_SET_ADDRESS 5u +#define UX_GET_DESCRIPTOR 6u +#define UX_SET_DESCRIPTOR 7u +#define UX_GET_CONFIGURATION 8u +#define UX_SET_CONFIGURATION 9u +#define UX_GET_INTERFACE 10u +#define UX_SET_INTERFACE 11u +#define UX_SYNCH_FRAME 12u + + +/* Define USBX command sub constants. */ + +#define UX_ENDPOINT_HALT 0u + +/* Define USBX feature selector constants. */ +#define UX_REQUEST_FEATURE_ENDPOINT_HALT 0u +#define UX_REQUEST_FEATURE_DEVICE_REMOTE_WAKEUP 1u +#define UX_REQUEST_FEATURE_TEST_MODE 2u + +/* Define Generic USBX constants. */ + +#define UX_UNUSED 0 +#define UX_USED 1 + +#define UX_MEMORY_UNUSED 0x00000000u +#define UX_MEMORY_USED 0x80000000u +#define UX_REGULAR_MEMORY 0 +#define UX_CACHE_SAFE_MEMORY 1 + +#define UX_NO_ALIGN 0u +#define UX_ALIGN_16 0x0fu +#define UX_ALIGN_MIN 0x0fu +#define UX_ALIGN_32 0x1fu +#define UX_ALIGN_64 0x3fu +#define UX_ALIGN_128 0x7fu +#define UX_ALIGN_256 0xffu +#define UX_ALIGN_512 0x1ffu +#define UX_ALIGN_1024 0x3ffu +#define UX_ALIGN_2048 0x7ffu +#define UX_ALIGN_4096 0xfffu +#define UX_SAFE_ALIGN 0xffffffffu +#define UX_MAX_SCATTER_GATHER_ALIGNMENT 4096 + +#define UX_MAX_USB_DEVICES 127 + +#define UX_ENDPOINT_DIRECTION 0x80u +#define UX_ENDPOINT_IN 0x80u +#define UX_ENDPOINT_OUT 0x00u + +#define UX_MASK_ENDPOINT_TYPE 3u +#define UX_CONTROL_ENDPOINT 0u +#define UX_ISOCHRONOUS_ENDPOINT 1u +#define UX_BULK_ENDPOINT 2u +#define UX_INTERRUPT_ENDPOINT 3u + +#define UX_ISOCHRONOUS_ENDPOINT_IN 0x81u +#define UX_ISOCHRONOUS_ENDPOINT_OUT 0x01u +#define UX_BULK_ENDPOINT_IN 0x82u +#define UX_BULK_ENDPOINT_OUT 0x02u +#define UX_INTERRUPT_ENDPOINT_IN 0x83u +#define UX_INTERRUPT_ENDPOINT_OUT 0x03u + +#define UX_MAX_PACKET_SIZE_MASK 0x7ffu +#define UX_MAX_NUMBER_OF_TRANSACTIONS_MASK 0x1800u +#define UX_MAX_NUMBER_OF_TRANSACTIONS_SHIFT 11 + +#define UX_REQUEST_DIRECTION 0x80u +#define UX_REQUEST_IN 0x80u +#define UX_REQUEST_OUT 0x00u + +#define UX_REQUEST_TYPE 0x60u +#define UX_REQUEST_TYPE_STANDARD 0x00u +#define UX_REQUEST_TYPE_CLASS 0x20u +#define UX_REQUEST_TYPE_VENDOR 0x40u + +#define UX_REQUEST_TARGET 0x03u +#define UX_REQUEST_TARGET_DEVICE 0x00u +#define UX_REQUEST_TARGET_INTERFACE 0x01u +#define UX_REQUEST_TARGET_ENDPOINT 0x02u +#define UX_REQUEST_TARGET_OTHER 0x03u + +#define UX_DEVICE_RESET 0 +#define UX_DEVICE_ATTACHED 1 +#define UX_DEVICE_ADDRESSED 2 +#define UX_DEVICE_CONFIGURED 3 +#define UX_DEVICE_SUSPENDED 4 +#define UX_DEVICE_RESUMED 5 +#define UX_DEVICE_SELF_POWERED_STATE 6 +#define UX_DEVICE_BUS_POWERED_STATE 7 +#define UX_DEVICE_REMOTE_WAKEUP 8 +#define UX_DEVICE_BUS_RESET_COMPLETED 9 +#define UX_DEVICE_REMOVED 10 +#define UX_DEVICE_FORCE_DISCONNECT 11 + +#define UX_ENDPOINT_RESET 0 +#define UX_ENDPOINT_RUNNING 1 +#define UX_ENDPOINT_HALTED 2 + +#define UX_DEVICE_DESCRIPTOR_ITEM 1u +#define UX_CONFIGURATION_DESCRIPTOR_ITEM 2u +#define UX_STRING_DESCRIPTOR_ITEM 3u +#define UX_INTERFACE_DESCRIPTOR_ITEM 4u +#define UX_ENDPOINT_DESCRIPTOR_ITEM 5u +#define UX_DEVICE_QUALIFIER_DESCRIPTOR_ITEM 6u +#define UX_OTHER_SPEED_DESCRIPTOR_ITEM 7u +#define UX_OTG_DESCRIPTOR_ITEM 9u +#define UX_INTERFACE_ASSOCIATION_DESCRIPTOR_ITEM 11u +#define UX_BOS_DESCRIPTOR_ITEM 15u +#define UX_DEVICE_CAPABILITY_DESCRIPTOR_ITEM 16u +#define UX_DFU_FUNCTIONAL_DESCRIPTOR_ITEM 0x21u +#define UX_HUB_DESCRIPTOR_ITEM 0x29u + +#define UX_CAPABILITY_WIRELESS_USB 0x01u +#define UX_CAPABILITY_USB_2_0_EXTENSION 0x02u +#define UX_CAPABILITY_SUPERSPEED_USB 0x03u +#define UX_CAPABILITY_CONTAINER_ID 0x04u +#define UX_CAPABILITY_PLATFORM 0x05u +#define UX_CAPABILITY_POWER_DELIVERY 0x06u +#define UX_CAPABILITY_BATTERY_INFO 0x07u +#define UX_CAPABILITY_PD_CONSUMER_PORT 0x08u +#define UX_CAPABILITY_PD_PROVIDER_PORT 0x09u +#define UX_CAPABILITY_SUPERSPEED_PLUS 0x0Au +#define UX_CAPABILITY_PRECISION_TIME_MEASUREMENT 0x0Bu +#define UX_CAPABILITY_WIRELESS_USB_EXT 0x0Cu +#define UX_CAPABILITY_BILLBOARD 0x0Du +#define UX_CAPABILITY_AUTHENTICATION 0x0Eu +#define UX_CAPABILITY_BILLBOARD_EX 0x0Fu +#define UX_CAPABILITY_CONFIGURATION_SUMMARY 0x10u + + +#ifndef UX_CONTROL_TRANSFER_TIMEOUT +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +#endif + +#ifndef UX_NON_CONTROL_TRANSFER_TIMEOUT +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +#endif +#define UX_PORT_ENABLE_WAIT 50 +#define UX_DEVICE_ADDRESS_SET_WAIT 50 +#define UX_HIGH_SPEED_DETECTION_HANDSHAKE_SUSPEND_WAIT 200 +#define UX_ENUMERATION_THREAD_WAIT 200 + + +/* USB Billboard constants. */ + +#define UX_CLASS_BILLBOARD_CLASS 0x11 +#define UX_CLASS_BILLBOARD_SUBCLASS 0x00 +#define UX_CLASS_BILLBOARD_PROTOCOL 0x00 +#define UX_CLASS_BILLBOARD_DESCRIPTOR_BILLBOARD 0x0D +#define UX_CLASS_BILLBOARD_DESCRIPTOR_ALTERNATE_MODE 0x0F +#define UX_CLASS_BILLBOARD_MAX_NUM_ALT_MODE 0x34 + +/* USBX 5.8 BACKWARD COMPATIBILITY DEFINITIONS. THESE DEFINITIONS ARE NOW OBSOLETE + BUT DEFINED HERE FOR COMPATIBILITY REASONS. */ + +#ifndef UX_CONTROL_TRANSFER_TIMEOUT_IN_MS +#define UX_CONTROL_TRANSFER_TIMEOUT_IN_MS 10000 +#endif + +#ifndef UX_NON_CONTROL_TRANSFER_TIMEOUT_IN_MS +#define UX_NON_CONTROL_TRANSFER_TIMEOUT_IN_MS 50000 +#endif + +#ifndef UX_PORT_ENABLE_WAIT_IN_MS +#define UX_PORT_ENABLE_WAIT_IN_MS 500 +#endif + +#ifndef UX_DEVICE_ADDRESS_SET_WAIT_IN_MS +#define UX_DEVICE_ADDRESS_SET_WAIT_IN_MS 500 +#endif + +#ifndef UX_HIGH_SPEED_DETECTION_HANDSHAKE_SUSPEND_WAIT_IN_MS +#define UX_HIGH_SPEED_DETECTION_HANDSHAKE_SUSPEND_WAIT_IN_MS 2000 +#endif + +/* END OF 5.8 BACKWARD COMPATIBILITY DEFINITIONS. */ + +#define UX_TRANSFER_PHASE_SETUP 1 +#define UX_TRANSFER_PHASE_DATA_IN 2 +#define UX_TRANSFER_PHASE_DATA_OUT 3 +#define UX_TRANSFER_PHASE_STATUS_IN 4 +#define UX_TRANSFER_PHASE_STATUS_OUT 5 + + +/* Host change callback events : _callback(event, *class, *instance) */ + +#define UX_DEVICE_INSERTION 0x01u +#define UX_DEVICE_REMOVAL 0x02u +#define UX_HID_CLIENT_INSERTION 0x03u +#define UX_HID_CLIENT_REMOVAL 0x04u +#define UX_STORAGE_MEDIA_INSERTION 0x05u +#define UX_STORAGE_MEDIA_REMOVAL 0x06u + +/* Host change callback events : _callback(event, NULL, *device_instance) */ + +#define UX_DEVICE_CONNECTION 0x81u +#define UX_DEVICE_DISCONNECTION 0x82u + +/* Host change callback events : _callback(event, NULL, NULL) */ + +#define UX_STANDALONE_WAIT_BACKGROUND_TASK 0x00u + + +/* Define USBX transfer request status constants. */ + +#define UX_TRANSFER_STATUS_NOT_PENDING 0 +#define UX_TRANSFER_STATUS_PENDING 1 +#define UX_TRANSFER_STATUS_COMPLETED 2 +#define UX_TRANSFER_STATUS_ABORT 4 + +/* Define USBX device power constants. */ + +#define UX_DEVICE_BUS_POWERED 1u +#define UX_DEVICE_SELF_POWERED 2u +#define UX_MAX_SELF_POWER (500u/2) +#define UX_MAX_BUS_POWER (100u/2) +#define UX_CONFIGURATION_DEVICE_BUS_POWERED 0x80u +#define UX_CONFIGURATION_DEVICE_SELF_POWERED 0x40u +#define UX_STATUS_DEVICE_SELF_POWERED 1u + +/* Define USBX OTG constants. */ + +#define UX_OTG_BM_ATTRIBUTES 2u +#define UX_OTG_SRP_SUPPORT 1u +#define UX_OTG_HNP_SUPPORT 2u +#define UX_HCD_OTG_CAPABLE 1u +#define UX_DCD_OTG_CAPABLE 1u + +#define UX_OTG_FEATURE_B_HNP_ENABLE 3u +#define UX_OTG_FEATURE_A_HNP_SUPPORT 4u +#define UX_OTG_FEATURE_A_ALT_HNP_SUPPORT 5u +#define UX_OTG_STATUS_SELECTOR 0xF000u +#define UX_OTG_HOST_REQUEST_FLAG 0x01u + +#define UX_OTG_IDLE 0u +#define UX_OTG_IDLE_TO_HOST 1u +#define UX_OTG_IDLE_TO_SLAVE 2u +#define UX_OTG_HOST_TO_IDLE 3u +#define UX_OTG_HOST_TO_SLAVE 4u +#define UX_OTG_SLAVE_TO_IDLE 5u +#define UX_OTG_SLAVE_TO_HOST 6u +#define UX_OTG_SLAVE_SRP 7u + +#define UX_OTG_MODE_IDLE 0u +#define UX_OTG_MODE_SLAVE 1u +#define UX_OTG_MODE_HOST 2u + +#define UX_OTG_DEVICE_IDLE 0u +#define UX_OTG_DEVICE_A 1u +#define UX_OTG_DEVICE_B 2u + +#define UX_OTG_VBUS_IDLE 0u +#define UX_OTG_VBUS_ON 1u +#define UX_OTG_VBUS_OFF 2u + + +#define UX_OTG_HNP_THREAD_SLEEP_TIME (2 * UX_PERIODIC_RATE) + +/* Define USBX device speed constants. */ + +#define UX_DEFAULT_HS_MPS 64 +#define UX_DEFAULT_MPS 8 + +#define UX_LOW_SPEED_DEVICE 0 +#define UX_FULL_SPEED_DEVICE 1 +#define UX_HIGH_SPEED_DEVICE 2 + + +/* Define USBX generic port status constants. */ + +#define UX_PS_CCS 0x01u +#define UX_PS_CPE 0x01u +#define UX_PS_PES 0x02u +#define UX_PS_PSS 0x04u +#define UX_PS_POCI 0x08u +#define UX_PS_PRS 0x10u +#define UX_PS_PPS 0x20u +#define UX_PS_DS_LS 0x00u +#define UX_PS_DS_FS 0x40u +#define UX_PS_DS_HS 0x80u + +#define UX_PS_DS 6u + + +/* Define USBX generic state machine constants. */ + +#define UX_STATE_RESET 0u +#define UX_STATE_EXIT 1u +#define UX_STATE_IDLE 2u +#define UX_STATE_ERROR 3u +#define UX_STATE_NEXT 4u +#define UX_STATE_WAIT 5u +#define UX_STATE_LOCK 6u +#define UX_STATE_BUSY 6u +#define UX_STATE_STEP 0x20u +#define UX_STATE_STACK_STEP 0x20u +#define UX_STATE_DRIVER_STEP 0x40u +#define UX_STATE_CLASS_STEP 0x60u +#define UX_STATE_APP_STEP 0x80u + +#define UX_STATE_IS_RESET(s) (!(s)) /* Reset state */ +#define UX_STATE_IS_FATAL(s) ((s) && (s) < UX_STATE_ERROR) /* Fatal, break all pending loops. */ +#define UX_STATE_IS_ERROR(s) ((s) == UX_STATE_ERROR) /* General error */ +#define UX_STATE_IS_BUSY(s) ((s) >= UX_STATE_WAIT) /* Locked or pending */ +#define UX_STATE_IS_LOCKED(s) ((s) >= UX_STATE_LOCK) /* Locked but not pendint */ + + +/* Define USBX Error Code constants. The following format describes + their meaning: + + 0x00 : Success + 0x0x : State machine return codes + 0x1x : Configuration errors + 0x2x : USB transport errors + 0x3x : USB controller errors + 0x4x : USB topology errors + 0x5x : USB API errors + 0x6x : USB Generic Class errors + 0x7x : USB HID Class errors + 0x8x : USB Audio Class errors + 0x9x : USB CDC-ECM Class errors + ... + 0xfx : General errors +*/ + +#define UX_SUCCESS 0 + +#define UX_ERROR 0xff +#define UX_BUSY 0xfe +#define UX_TIMEOUT 0xfd +#define UX_REENTRY 0xfc +#define UX_INVALID_STATE 0xfb +#define UX_INVALID_PARAMETER 0xfa +#define UX_ABORTED 0xf9 + +#define UX_TOO_MANY_DEVICES 0x11 +#define UX_MEMORY_INSUFFICIENT 0x12 +#define UX_NO_TD_AVAILABLE 0x13 +#define UX_NO_ED_AVAILABLE 0x14 +#define UX_SEMAPHORE_ERROR 0x15 +#define UX_THREAD_ERROR 0x16 +#define UX_MUTEX_ERROR 0x17 +#define UX_EVENT_ERROR 0x18 +#define UX_MEMORY_CORRUPTED 0x19 +#define UX_MEMORY_ARRAY_FULL 0x1a +#define UX_FATAL_ERROR 0x1b +#define UX_ALREADY_ACTIVATED 0x1c + +#define UX_TRANSFER_STALLED 0x21 +#define UX_TRANSFER_NO_ANSWER 0x22 +#define UX_TRANSFER_ERROR 0x23 +#define UX_TRANSFER_MISSED_FRAME 0x24 +#define UX_TRANSFER_NOT_READY 0x25 +#define UX_TRANSFER_BUS_RESET 0x26 +#define UX_TRANSFER_BUFFER_OVERFLOW 0x27 +#define UX_TRANSFER_APPLICATION_RESET 0x28 +#define UX_TRANSFER_DATA_LESS_THAN_EXPECTED 0x29 + +#define UX_PORT_RESET_FAILED 0x31 +#define UX_CONTROLLER_INIT_FAILED 0x32 +#define UX_CONTROLLER_DEAD 0x33 + +#define UX_NO_BANDWIDTH_AVAILABLE 0x41 +#define UX_DESCRIPTOR_CORRUPTED 0x42 +#define UX_OVER_CURRENT_CONDITION 0x43 +#define UX_DEVICE_ENUMERATION_FAILURE 0x44 +#define UX_TOO_MANY_HUB_PORTS 0x45 + +#define UX_DEVICE_HANDLE_UNKNOWN 0x50 +#define UX_CONFIGURATION_HANDLE_UNKNOWN 0x51 +#define UX_INTERFACE_HANDLE_UNKNOWN 0x52 +#define UX_ENDPOINT_HANDLE_UNKNOWN 0x53 +#define UX_FUNCTION_NOT_SUPPORTED 0x54 +#define UX_CONTROLLER_UNKNOWN 0x55 +#define UX_PORT_INDEX_UNKNOWN 0x56 +#define UX_NO_CLASS_MATCH 0x57 +#define UX_HOST_CLASS_ALREADY_INSTALLED 0x58 +#define UX_HOST_CLASS_UNKNOWN 0x59 +#define UX_CONNECTION_INCOMPATIBLE 0x5a +#define UX_HOST_CLASS_INSTANCE_UNKNOWN 0x5b +#define UX_TRANSFER_TIMEOUT 0x5c +#define UX_BUFFER_OVERFLOW 0x5d +#define UX_NO_ALTERNATE_SETTING 0x5e +#define UX_NO_DEVICE_CONNECTED 0x5f + +#define UX_HOST_CLASS_PROTOCOL_ERROR 0x60 +#define UX_HOST_CLASS_MEMORY_ERROR 0x61 +#define UX_HOST_CLASS_MEDIA_NOT_SUPPORTED 0x62 +#define UX_CLASS_MALFORMED_PACKET_RECEIVED_ERROR 0x63 + +#define UX_HOST_CLASS_HID_REPORT_OVERFLOW 0x70 +#define UX_HOST_CLASS_HID_USAGE_OVERFLOW 0x71 +#define UX_HOST_CLASS_HID_TAG_UNSUPPORTED 0x72 +#define UX_HOST_CLASS_HID_PUSH_OVERFLOW 0x73 +#define UX_HOST_CLASS_HID_POP_UNDERFLOW 0x74 +#define UX_HOST_CLASS_HID_COLLECTION_OVERFLOW 0x75 +#define UX_HOST_CLASS_HID_COLLECTION_UNDERFLOW 0x76 +#define UX_HOST_CLASS_HID_MIN_MAX_ERROR 0x77 +#define UX_HOST_CLASS_HID_DELIMITER_ERROR 0x78 +#define UX_HOST_CLASS_HID_REPORT_ERROR 0x79 +#define UX_HOST_CLASS_HID_PERIODIC_REPORT_ERROR 0x7A +#define UX_HOST_CLASS_HID_UNKNOWN 0x7B + +#define UX_HOST_CLASS_AUDIO_WRONG_TYPE 0x80 +#define UX_HOST_CLASS_AUDIO_WRONG_INTERFACE 0x81 + +#define UX_CLASS_CDC_ECM_LINK_STATE_DOWN_ERROR 0x90 + + +/* Define USBX HCD API function constants. */ + +#define UX_HCD_DISABLE_CONTROLLER 1 +#define UX_HCD_GET_PORT_STATUS 2 +#define UX_HCD_ENABLE_PORT 3 +#define UX_HCD_DISABLE_PORT 4 +#define UX_HCD_POWER_ON_PORT 5 +#define UX_HCD_POWER_DOWN_PORT 6 +#define UX_HCD_SUSPEND_PORT 7 +#define UX_HCD_RESUME_PORT 8 +#define UX_HCD_RESET_PORT 9 +#define UX_HCD_GET_FRAME_NUMBER 10 +#define UX_HCD_SET_FRAME_NUMBER 11 +#define UX_HCD_TRANSFER_REQUEST 12 +#define UX_HCD_TRANSFER_RUN 12 +#define UX_HCD_TRANSFER_ABORT 13 +#define UX_HCD_CREATE_ENDPOINT 14 +#define UX_HCD_DESTROY_ENDPOINT 15 +#define UX_HCD_RESET_ENDPOINT 16 +#define UX_HCD_PROCESS_DONE_QUEUE 17 +#define UX_HCD_TASKS_RUN 17 +#define UX_HCD_UNINITIALIZE 18 + +/* Define USBX DCD API function constants. */ + +#define UX_DCD_DISABLE_CONTROLLER 1 +#define UX_DCD_GET_PORT_STATUS 2 +#define UX_DCD_ENABLE_PORT 3 +#define UX_DCD_DISABLE_PORT 4 +#define UX_DCD_POWER_ON_PORT 5 +#define UX_DCD_POWER_DOWN_PORT 6 +#define UX_DCD_SUSPEND_PORT 7 +#define UX_DCD_RESUME_PORT 8 +#define UX_DCD_RESET_PORT 9 +#define UX_DCD_GET_FRAME_NUMBER 10 +#define UX_DCD_SET_FRAME_NUMBER 11 +#define UX_DCD_TRANSFER_REQUEST 12 +#define UX_DCD_TRANSFER_RUN 12 +#define UX_DCD_TRANSFER_ABORT 13 +#define UX_DCD_CREATE_ENDPOINT 14 +#define UX_DCD_DESTROY_ENDPOINT 15 +#define UX_DCD_RESET_ENDPOINT 16 +#define UX_DCD_SET_DEVICE_ADDRESS 17 +#define UX_DCD_ISR_PENDING 18 +#define UX_DCD_TASKS_RUN 18 +#define UX_DCD_CHANGE_STATE 19 +#define UX_DCD_STALL_ENDPOINT 20 +#define UX_DCD_ENDPOINT_STATUS 21 + + +/* Define USBX generic host controller constants. */ + +#define UX_HCD_STATUS_UNUSED 0 +#define UX_HCD_STATUS_HALTED 1 +#define UX_HCD_STATUS_OPERATIONAL 2 +#define UX_HCD_STATUS_DEAD 3 + +/* Define USBX generic SLAVE controller constants. */ + +#define UX_DCD_STATUS_HALTED 0 +#define UX_DCD_STATUS_OPERATIONAL 1 +#define UX_DCD_STATUS_DEAD 2 + +/* Define USBX SLAVE controller VBUS constants. */ + +#define UX_DCD_VBUS_RESET 0 +#define UX_DCD_VBUS_SET 1 + +/* Define USBX class interface constants. */ + +#define UX_HOST_CLASS_COMMAND_QUERY 1 +#define UX_HOST_CLASS_COMMAND_ACTIVATE 2 +#define UX_HOST_CLASS_COMMAND_DEACTIVATE 3 +#define UX_HOST_CLASS_COMMAND_DESTROY 4 +#define UX_HOST_CLASS_COMMAND_ACTIVATE_START UX_HOST_CLASS_COMMAND_ACTIVATE +#define UX_HOST_CLASS_COMMAND_ACTIVATE_WAIT 5 + +#define UX_SLAVE_CLASS_COMMAND_QUERY 1 +#define UX_SLAVE_CLASS_COMMAND_ACTIVATE 2 +#define UX_SLAVE_CLASS_COMMAND_DEACTIVATE 3 +#define UX_SLAVE_CLASS_COMMAND_REQUEST 4 +#define UX_SLAVE_CLASS_COMMAND_INITIALIZE 5 +#define UX_SLAVE_CLASS_COMMAND_CHANGE 6 +#define UX_SLAVE_CLASS_COMMAND_UNINITIALIZE 7 + +#define UX_HOST_CLASS_COMMAND_USAGE_PIDVID 1 +#define UX_HOST_CLASS_COMMAND_USAGE_CSP 2 +#define UX_HOST_CLASS_COMMAND_USAGE_DCSP 3 + +#define UX_HOST_CLASS_INSTANCE_FREE 0 +#define UX_HOST_CLASS_INSTANCE_LIVE 1 +#define UX_HOST_CLASS_INSTANCE_SHUTDOWN 2 +#define UX_HOST_CLASS_INSTANCE_MOUNTING 3 + + +/* Define USBX root HUB constants. */ + +#define UX_RH_ENUMERATION_RETRY 3 +#define UX_RH_ENUMERATION_RETRY_DELAY 100 + + +/* Define USBX PCI driver constants. */ + +#define UX_PCI_NB_FUNCTIONS 7 +#define UX_PCI_NB_DEVICE 32 +#define UX_PCI_NB_BUS 0xff + +#define UX_PCI_CMD_IO_ENABLE 0x0001u +#define UX_PCI_CMD_MEM_ENABLE 0x0002u +#define UX_PCI_CMD_MASTER_ENABLE 0x0004u +#define UX_PCI_CMD_MONITOR_ENABLE 0x0008u +#define UX_PCI_CMD_MEM_WRITE_INV_ENABLE 0x0010u +#define UX_PCI_CMD_SNOOP_PALETTE_ENABLE 0x0020u +#define UX_PCI_CMD_PARITY_ERROR_ENABLE 0x0040u +#define UX_PCI_CMD_WAIT_CYCLE_CTRL_ENABLE 0x0080u +#define UX_PCI_CMD_SERR_ENABLE 0x0100u +#define UX_PCI_CMD_FBB_ENABLE 0x0200u + +#define UX_PCI_CFG_CTRL_ADDRESS 0x0cf8u +#define UX_PCI_CFG_DATA_ADDRESS 0x0cfcu + +#define UX_PCI_CFG_VENDOR_ID 0x00 +#define UX_PCI_CFG_DEVICE_ID 0x02 +#define UX_PCI_CFG_COMMAND 0x04 +#define UX_PCI_CFG_STATUS 0x06 +#define UX_PCI_CFG_REVISION 0x08 +#define UX_PCI_CFG_PROGRAMMING_IF 0x09 +#define UX_PCI_CFG_SUBCLASS 0x0a +#define UX_PCI_CFG_CLASS 0x0b +#define UX_PCI_CFG_CACHE_LINE_SIZE 0x0c +#define UX_PCI_CFG_LATENCY_TIMER 0x0d +#define UX_PCI_CFG_HEADER_TYPE 0x0e +#define UX_PCI_CFG_BIST 0x0f +#define UX_PCI_CFG_BASE_ADDRESS_0 0x10 +#define UX_PCI_CFG_BASE_ADDRESS_1 0x14 +#define UX_PCI_CFG_BASE_ADDRESS_2 0x18 +#define UX_PCI_CFG_BASE_ADDRESS_3 0x1c +#define UX_PCI_CFG_BASE_ADDRESS_4 0x20 +#define UX_PCI_CFG_BASE_ADDRESS_5 0x24 +#define UX_PCI_CFG_CARDBUS_CIS 0x28 +#define UX_PCI_CFG_SUB_VENDOR_ID 0x2c +#define UX_PCI_CFG_SUB_SYSTEM_ID 0x2e +#define UX_PCI_CFG_EXPANSION_ROM_ADDRESS 0x30 +#define UX_PCI_CFG_RESERVED_0 0x34 +#define UX_PCI_CFG_RESERVED_1 0x38 +#define UX_PCI_CFG_INT_LINE 0x3c +#define UX_PCI_CFG_INT_PIN 0x3d +#define UX_PCI_CFG_MIN_GNT 0x3e +#define UX_PCI_CFG_MAX_LATENCY 0x3f + +#define UX_PCI_CFG_SBRN 0x60 +#define UX_PCI_CFG_FLADJ 0x61 + +/* Define DFU constants. */ +#define UX_SYSTEM_DFU_STATE_APP_IDLE 0 +#define UX_SYSTEM_DFU_STATE_APP_DETACH 1 +#define UX_SYSTEM_DFU_STATE_DFU_IDLE 2 +#define UX_SYSTEM_DFU_STATE_DFU_DNLOAD_SYNC 3 +#define UX_SYSTEM_DFU_STATE_DFU_DNBUSY 4 +#define UX_SYSTEM_DFU_STATE_DFU_DNLOAD_IDLE 5 +#define UX_SYSTEM_DFU_STATE_DFU_MANIFEST_SYNC 6 +#define UX_SYSTEM_DFU_STATE_DFU_MANIFEST 7 +#define UX_SYSTEM_DFU_STATE_DFU_MANIFEST_WAIT_RESET 8 +#define UX_SYSTEM_DFU_STATE_DFU_UPLOAD_IDLE 9 +#define UX_SYSTEM_DFU_STATE_DFU_ERROR 10 + +/* Define basic class constants. */ + +#define UX_HOST_CLASS_PRINTER_NAME_LENGTH 64 + + +/* Define USBX 2.0 TT Instance structure. */ + +typedef struct UX_HUB_TT_STRUCT +{ + + ULONG ux_hub_tt_port_mapping; + ULONG ux_hub_tt_max_bandwidth; +} UX_HUB_TT; + + +/* Define USBX Class calling command structure. */ + +typedef struct UX_HOST_CLASS_COMMAND_STRUCT +{ + + UINT ux_host_class_command_request; + VOID *ux_host_class_command_container; + VOID *ux_host_class_command_instance; + UINT ux_host_class_command_usage; + UINT ux_host_class_command_pid; + UINT ux_host_class_command_vid; + UINT ux_host_class_command_class; + UINT ux_host_class_command_subclass; + UINT ux_host_class_command_protocol; + UINT ux_host_class_command_iad_class; + UINT ux_host_class_command_iad_subclass; + UINT ux_host_class_command_iad_protocol; + + struct UX_HOST_CLASS_STRUCT + *ux_host_class_command_class_ptr; +} UX_HOST_CLASS_COMMAND; + + +/* Define USBX Class container structure. */ + +typedef struct UX_HOST_CLASS_STRUCT +{ + +#if defined(UX_NAME_REFERENCED_BY_POINTER) + const UCHAR *ux_host_class_name; +#else + UCHAR ux_host_class_name[UX_MAX_CLASS_NAME_LENGTH + 1]; /* "+1" for string null-terminator */ +#endif + +#if defined(UX_HOST_STANDALONE) + UINT (*ux_host_class_task_function)(struct UX_HOST_CLASS_STRUCT *); +#endif + + UINT ux_host_class_status; + UINT (*ux_host_class_entry_function) (struct UX_HOST_CLASS_COMMAND_STRUCT *); + VOID *ux_host_class_first_instance; + VOID *ux_host_class_client; + VOID *ux_host_class_media; + VOID *ux_host_class_ext; + +} UX_HOST_CLASS; + + +/* Define USBX transfer request structure. */ + +typedef struct UX_TRANSFER_STRUCT +{ + + ULONG ux_transfer_request_status; + struct UX_ENDPOINT_STRUCT + *ux_transfer_request_endpoint; + UCHAR * ux_transfer_request_data_pointer; + ULONG ux_transfer_request_requested_length; + ULONG ux_transfer_request_actual_length; + UINT ux_transfer_request_type; + UINT ux_transfer_request_function; + UINT ux_transfer_request_value; + UINT ux_transfer_request_index; + VOID (*ux_transfer_request_completion_function) (struct UX_TRANSFER_STRUCT *); + VOID *ux_transfer_request_class_instance; + ULONG ux_transfer_request_maximum_length; + ULONG ux_transfer_request_timeout_value; + UINT ux_transfer_request_completion_code; + ULONG ux_transfer_request_packet_length; + struct UX_TRANSFER_STRUCT + *ux_transfer_request_next_transfer_request; + VOID *ux_transfer_request_user_specific; +#if !defined(UX_HOST_STANDALONE) + UX_SEMAPHORE ux_transfer_request_semaphore; + UX_THREAD *ux_transfer_request_thread_pending; +#else + UINT ux_transfer_request_state; + ULONG ux_transfer_request_time_start; + ULONG ux_transfer_request_flags; + struct UX_TRANSFER_STRUCT + *ux_transfer_request_next_pending; +#endif +} UX_TRANSFER; + +#if defined(UX_HOST_STANDALONE) +#define UX_TRANSFER_STATE_RESET(tr) ((tr)->ux_transfer_request_state = UX_STATE_RESET) +#define UX_TRANSFER_STATE_IDLE(tr) ((tr)->ux_transfer_request_state = UX_STATE_IDLE) +#define UX_TRANSFER_STATE_IS_BUSY(tr) UX_STATE_IS_BUSY((tr)->ux_transfer_request_state) +#define UX_TRANSFER_STATE_IS_IDLE(tr) ((tr)->ux_transfer_request_state == UX_STATE_IDLE) + +#define UX_TRANSFER_FLAGS_RESET(tr) ((tr)->ux_transfer_request_flags = 0) +#define UX_TRANSFER_FLAG_LOCK (0x1u << 0) +#define UX_TRANSFER_FLAG_AUTO_WAIT (0x1u << 1) /* Wait until transfer done. */ +#define UX_TRANSFER_FLAG_AUTO_DEVICE_UNLOCK (0x1u << 2) /* In wait case, unlock device after transfer done. */ +#endif + + +/* Define USBX Endpoint Descriptor structure. */ + +typedef struct UX_ENDPOINT_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bEndpointAddress; + ULONG bmAttributes; + ULONG wMaxPacketSize; + ULONG bInterval; +} UX_ENDPOINT_DESCRIPTOR; + +#define UX_ENDPOINT_DESCRIPTOR_ENTRIES 6 +#define UX_ENDPOINT_DESCRIPTOR_LENGTH 7 + + +/* Define USBX Endpoint Container structure. */ + +typedef struct UX_ENDPOINT_STRUCT +{ + + ULONG ux_endpoint; + ULONG ux_endpoint_state; + void *ux_endpoint_ed; + struct UX_ENDPOINT_DESCRIPTOR_STRUCT + ux_endpoint_descriptor; + struct UX_ENDPOINT_STRUCT + *ux_endpoint_next_endpoint; + struct UX_INTERFACE_STRUCT + *ux_endpoint_interface; + struct UX_DEVICE_STRUCT + *ux_endpoint_device; + struct UX_TRANSFER_STRUCT + ux_endpoint_transfer_request; +} UX_ENDPOINT; + + +/* Define USBX Device Descriptor structure. */ + +typedef struct UX_DEVICE_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bcdUSB; + ULONG bDeviceClass; + ULONG bDeviceSubClass; + ULONG bDeviceProtocol; + ULONG bMaxPacketSize0; + ULONG idVendor; + ULONG idProduct; + ULONG bcdDevice; + ULONG iManufacturer; + ULONG iProduct; + ULONG iSerialNumber; + ULONG bNumConfigurations; +} UX_DEVICE_DESCRIPTOR; + +#define UX_DEVICE_DESCRIPTOR_ENTRIES 14 +#define UX_DEVICE_DESCRIPTOR_LENGTH 18 + +/* Define USBX Device Qualifier Descriptor structure. */ + +typedef struct UX_DEVICE_QUALIFIER_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bcdUSB; + ULONG bDeviceClass; + ULONG bDeviceSubClass; + ULONG bDeviceProtocol; + ULONG bMaxPacketSize0; + ULONG bNumConfigurations; + ULONG bReserved; +} UX_DEVICE_QUALIFIER_DESCRIPTOR; + +#define UX_DEVICE_QUALIFIER_DESCRIPTOR_ENTRIES 9 +#define UX_DEVICE_QUALIFIER_DESCRIPTOR_LENGTH 10 + + +/* Define USBX Other Speed Descriptor structure. */ + +typedef struct UX_OTHER_SPEED_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG wTotalLength; + ULONG bNumInterfaces; + ULONG bConfigurationValue; + ULONG iConfiguration; + ULONG bmAttributes; + ULONG MaxPower; +} UX_OTHER_SPEED_DESCRIPTOR; + +#define UX_OTHER_SPEED_DESCRIPTOR_ENTRIES 8 +#define UX_OTHER_SPEED_DESCRIPTOR_LENGTH 9 + +/* Define USBX OTG Descriptor structure. */ + +typedef struct UX_OTG_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bmAttributes; + ULONG bcdOTG; +} UX_OTG_DESCRIPTOR; + +#define UX_OTG_DESCRIPTOR_ENTRIES 4 +#define UX_OTG_DESCRIPTOR_LENGTH 5 + +/* Define USBX Interface Association Descriptor structure. */ + +typedef struct UX_INTERFACE_ASSOCIATION_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bFirstInterface; + ULONG bInterfaceCount; + ULONG bFunctionClass; + ULONG bFunctionSubClass; + ULONG bFunctionProtocol; + ULONG iFunction; + +} UX_INTERFACE_ASSOCIATION_DESCRIPTOR; + +#define UX_INTERFACE_ASSOCIATION_DESCRIPTOR_ENTRIES 8 +#define UX_INTERFACE_ASSOCIATION_DESCRIPTOR_LENGTH 8 + + +/* Define USBX Device Container structure. */ + +typedef struct UX_DEVICE_STRUCT +{ + + ULONG ux_device_handle; + ULONG ux_device_type; + ULONG ux_device_state; + ULONG ux_device_address; + ULONG ux_device_speed; + ULONG ux_device_power_source; + struct UX_CONFIGURATION_STRUCT + *ux_device_current_configuration; +#if !defined(UX_HOST_STANDALONE) + UX_SEMAPHORE ux_device_protection_semaphore; +#endif + struct UX_HOST_CLASS_STRUCT + *ux_device_class; + VOID *ux_device_class_instance; + struct UX_CONFIGURATION_STRUCT + *ux_device_first_configuration; + struct UX_DEVICE_DESCRIPTOR_STRUCT + ux_device_descriptor; + struct UX_ENDPOINT_STRUCT + ux_device_control_endpoint; + ULONG ux_device_port_location; +#if UX_MAX_HCD > 1 + struct UX_HCD_STRUCT + *ux_device_hcd; +#endif +#if UX_MAX_DEVICES > 1 + struct UX_DEVICE_STRUCT + *ux_device_parent; + ULONG ux_device_max_power; + struct UX_HUB_TT_STRUCT + ux_device_hub_tt[UX_MAX_TT]; +#endif + +#if defined(UX_HOST_STANDALONE) + ULONG ux_device_flags; + + struct UX_DEVICE_STRUCT + *ux_device_enum_next; + struct UX_TRANSFER_STRUCT + *ux_device_enum_trans; + union { + struct UX_DEVICE_STRUCT + *device; + struct UX_CONFIGURATION_STRUCT + *configuration; + struct UX_INTERFACE_STRUCT + *interface; + VOID *ptr; + } ux_device_enum_inst; + + ULONG ux_device_enum_wait_start; + ULONG ux_device_enum_wait_ms; + + UCHAR ux_device_enum_state; + UCHAR ux_device_dbg_state; + UCHAR ux_device_enum_next_state; + UCHAR ux_device_enum_retry; + UCHAR ux_device_enum_port_status; + UCHAR ux_device_enum_index; + UCHAR reserved[2]; + ULONG ux_device_dbg_state_count; +#endif + +} UX_DEVICE; + +#if defined(UX_HOST_STANDALONE) +#define UX_DEVICE_FLAG_LOCK 0x01u +#define UX_DEVICE_FLAG_RESET 0x02u +#define UX_DEVICE_FLAG_ENUM 0x04u +#define UX_DEVICE_FLAG_PROTECT 0x08u +#endif + +#if UX_MAX_HCD > 1 +#define UX_DEVICE_HCD_GET(d) ((d)->ux_device_hcd) +#define UX_DEVICE_HCD_SET(d,h) do { (d)->ux_device_hcd = (h); } while(0) +#define UX_DEVICE_HCD_MATCH(d,h) ((d)->ux_device_hcd == (h)) +#else +#define UX_DEVICE_HCD_GET(d) (_ux_system_host->ux_system_host_hcd_array) +#define UX_DEVICE_HCD_SET(d,h) +#define UX_DEVICE_HCD_MATCH(d,h) (_ux_system_host->ux_system_host_hcd_array == (h)) +#endif + + +#if UX_MAX_DEVICES > 1 +#define UX_DEVICE_PARENT_GET(d) ((d)->ux_device_parent) +#define UX_DEVICE_PARENT_SET(d,p) do { (d)->ux_device_parent = (p); } while(0) +#define UX_DEVICE_PARENT_MATCH(d,p) ((d)->ux_device_parent == (p)) +#define UX_DEVICE_PARENT_IS_HUB(d) ((d)->ux_device_parent != UX_NULL) +#define UX_DEVICE_PARENT_IS_ROOTHUB(d) ((d)->ux_device_parent == UX_NULL) +#define UX_DEVICE_MAX_POWER_GET(d) ((d)->ux_device_max_power) +#define UX_DEVICE_MAX_POWER_SET(d,p) do {(d)->ux_device_max_power = (p); } while(0) +#else +#define UX_DEVICE_PARENT_GET(d) (UX_NULL) +#define UX_DEVICE_PARENT_SET(d,p) UX_PARAMETER_NOT_USED(p) +#define UX_DEVICE_PARENT_MATCH(d,p) ((p) == UX_NULL) +#define UX_DEVICE_PARENT_IS_HUB(d) (UX_FALSE) +#define UX_DEVICE_PARENT_IS_ROOTHUB(d) (UX_TRUE) +#define UX_DEVICE_MAX_POWER_GET(d) (UX_MAX_SELF_POWER) +#define UX_DEVICE_MAX_POWER_SET(d,p) UX_PARAMETER_NOT_USED(p) +#endif +#define UX_DEVICE_PORT_LOCATION_GET(d) ((d)->ux_device_port_location) +#define UX_DEVICE_PORT_LOCATION_SET(d,l) do { (d)->ux_device_port_location = (l); } while(0) +#define UX_DEVICE_PORT_LOCATION_MATCH(d,l) ((d)->ux_device_port_location == (l)) + + +/* Define USBX Configuration Descriptor structure. */ + +typedef struct UX_CONFIGURATION_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG wTotalLength; + ULONG bNumInterfaces; + ULONG bConfigurationValue; + ULONG iConfiguration; + ULONG bmAttributes; + ULONG MaxPower; +} UX_CONFIGURATION_DESCRIPTOR; + +#define UX_CONFIGURATION_DESCRIPTOR_ENTRIES 8 +#define UX_CONFIGURATION_DESCRIPTOR_LENGTH 9 + + +/* Define USBX Configuration Container structure. */ + +typedef struct UX_CONFIGURATION_STRUCT +{ + + ULONG ux_configuration_handle; + ULONG ux_configuration_state; + ULONG ux_configuration_otg_capabilities; + struct UX_CONFIGURATION_DESCRIPTOR_STRUCT + ux_configuration_descriptor; + struct UX_INTERFACE_STRUCT + *ux_configuration_first_interface; + struct UX_CONFIGURATION_STRUCT + *ux_configuration_next_configuration; + struct UX_DEVICE_STRUCT + *ux_configuration_device; + ULONG ux_configuration_iad_class; + ULONG ux_configuration_iad_subclass; + ULONG ux_configuration_iad_protocol; +} UX_CONFIGURATION; + + +/* Define USBX Interface Descriptor structure. */ + +typedef struct UX_INTERFACE_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bInterfaceNumber; + ULONG bAlternateSetting; + ULONG bNumEndpoints; + ULONG bInterfaceClass; + ULONG bInterfaceSubClass; + ULONG bInterfaceProtocol; + ULONG iInterface; +} UX_INTERFACE_DESCRIPTOR; + +#define UX_INTERFACE_DESCRIPTOR_ENTRIES 9 +#define UX_INTERFACE_DESCRIPTOR_LENGTH 9 + + +/* Define USBX Interface Container structure. */ + +typedef struct UX_INTERFACE_STRUCT +{ + + ULONG ux_interface_handle; + ULONG ux_interface_state; + UINT ux_interface_current_alternate_setting; + struct UX_INTERFACE_DESCRIPTOR_STRUCT + ux_interface_descriptor; + struct UX_HOST_CLASS_STRUCT + *ux_interface_class; + VOID *ux_interface_class_instance; + struct UX_ENDPOINT_STRUCT + *ux_interface_first_endpoint; + struct UX_INTERFACE_STRUCT + *ux_interface_next_interface; + struct UX_CONFIGURATION_STRUCT + *ux_interface_configuration; + ULONG ux_interface_iad_class; + ULONG ux_interface_iad_subclass; + ULONG ux_interface_iad_protocol; + +} UX_INTERFACE; + + +/* Define USBX String Descriptor structure. */ + +typedef struct UX_STRING_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bString[1]; +} UX_STRING_DESCRIPTOR; + +#define UX_STRING_DESCRIPTOR_ENTRIES 3 +#define UX_STRING_DESCRIPTOR_LENGTH 4 + + +/* Define USBX BOS Descriptor structure. */ + +typedef struct UX_BOS_DESCRIPTOR_STRUCT +{ + ULONG bLength; + ULONG bDescriptorType; + ULONG wTotalLength; + ULONG bNumDeviceCaps; +} UX_BOS_DESCRIPTOR; + +#define UX_BOS_DESCRIPTOR_ENTRIES 4 +#define UX_BOS_DESCRIPTOR_LENGTH 5 + + +/* Define USBX USB 2.0 Descriptor structure. */ + +typedef struct UX_USB_2_0_EXTENSION_DESCRIPTOR_STRUCT +{ + ULONG bLength; + ULONG bDescriptorType; + ULONG bDevCapabilityType; + ULONG bmAttributes; +} UX_USB_2_0_EXTENSION_DESCRIPTOR; + +#define UX_USB_2_0_EXTENSION_DESCRIPTOR_ENTRIES 4 +#define UX_USB_2_0_EXTENSION_DESCRIPTOR_LENGTH 7 + + +/* Define USBX Container ID Descriptor structure. */ + +typedef struct UX_CONTAINER_ID_DESCRIPTOR_STRUCT +{ + ULONG bLength; + ULONG bDescriptorType; + ULONG bDevCapabilityType; + ULONG bReserved; + ULONG ContainerID[4]; +} UX_CONTAINER_ID_DESCRIPTOR; + +#define UX_CONTAINER_ID_DESCRIPTOR_ENTRIES 5 +#define UX_CONTAINER_ID_DESCRIPTOR_LENGTH 20 + + +/* Define USBX DFU functional descriptor. */ + +typedef struct UX_DFU_FUNCTIONAL_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bmAttributes; + ULONG wDetachTimeOut; + ULONG wTransferSize; + ULONG bcdDFUVersion; +} UX_DFU_FUNCTIONAL_DESCRIPTOR; + +#define UX_DFU_FUNCTIONAL_DESCRIPTOR_ENTRIES 6 +#define UX_DFU_FUNCTIONAL_DESCRIPTOR_LENGTH 9 + +/* Define USBX Host Controller structure. */ + +typedef struct UX_HCD_STRUCT +{ + +#if defined(UX_NAME_REFERENCED_BY_POINTER) + const UCHAR *ux_hcd_name; +#else + UCHAR ux_hcd_name[UX_MAX_HCD_NAME_LENGTH + 1]; /* "+1" for string null-terminator */ +#endif + + UINT ux_hcd_status; + UINT ux_hcd_controller_type; + UINT ux_hcd_irq; + UINT ux_hcd_nb_root_hubs; + UINT ux_hcd_root_hub_signal[UX_MAX_ROOTHUB_PORT]; + UINT ux_hcd_nb_devices; + UINT ux_hcd_thread_signal; + ULONG ux_hcd_rh_device_connection; + ULONG ux_hcd_io; + UINT (*ux_hcd_entry_function) (struct UX_HCD_STRUCT *, UINT, VOID *); + void *ux_hcd_controller_hardware; + +#if defined(UX_OTG_SUPPORT) + UINT ux_hcd_otg_capabilities; +#endif + +#if UX_MAX_DEVICES > 1 + UCHAR ux_hcd_address[16]; + UINT ux_hcd_power_switch; + ULONG ux_hcd_available_bandwidth; + ULONG ux_hcd_version; +#endif + +#if defined(UX_HOST_STANDALONE) + ULONG ux_hcd_flags; +#endif +} UX_HCD; + + +/* Define USBX Device Transfer Request structure. */ + +typedef struct UX_SLAVE_TRANSFER_STRUCT +{ + + ULONG ux_slave_transfer_request_status; + ULONG ux_slave_transfer_request_type; + struct UX_SLAVE_ENDPOINT_STRUCT + *ux_slave_transfer_request_endpoint; + UCHAR *ux_slave_transfer_request_data_pointer; + UCHAR *ux_slave_transfer_request_current_data_pointer; + ULONG ux_slave_transfer_request_requested_length; + ULONG ux_slave_transfer_request_actual_length; + ULONG ux_slave_transfer_request_in_transfer_length; + ULONG ux_slave_transfer_request_transfer_length; + ULONG ux_slave_transfer_request_completion_code; + ULONG ux_slave_transfer_request_phase; + VOID (*ux_slave_transfer_request_completion_function) (struct UX_SLAVE_TRANSFER_STRUCT *); +#if defined(UX_DEVICE_STANDALONE) + ULONG ux_slave_transfer_request_state; +#else + UX_SEMAPHORE ux_slave_transfer_request_semaphore; +#endif + ULONG ux_slave_transfer_request_timeout; + ULONG ux_slave_transfer_request_force_zlp; + UCHAR ux_slave_transfer_request_setup[UX_SETUP_SIZE]; + ULONG ux_slave_transfer_request_status_phase_ignore; +} UX_SLAVE_TRANSFER; + +#if defined(UX_DEVICE_STANDALONE) +#define UX_SLAVE_TRANSFER_STATE_RESET(tr) ((tr)->ux_slave_transfer_request_state = UX_STATE_RESET) +#endif + + +/* Define USBX Device Controller Endpoint structure. */ + +typedef struct UX_SLAVE_ENDPOINT_STRUCT +{ + + ULONG ux_slave_endpoint_status; + ULONG ux_slave_endpoint_state; + void *ux_slave_endpoint_ed; + struct UX_ENDPOINT_DESCRIPTOR_STRUCT + ux_slave_endpoint_descriptor; + struct UX_SLAVE_ENDPOINT_STRUCT + *ux_slave_endpoint_next_endpoint; + struct UX_SLAVE_INTERFACE_STRUCT + *ux_slave_endpoint_interface; + struct UX_SLAVE_DEVICE_STRUCT + *ux_slave_endpoint_device; + struct UX_SLAVE_TRANSFER_STRUCT + ux_slave_endpoint_transfer_request; +} UX_SLAVE_ENDPOINT; + + +/* Define USBX Device Controller Interface structure. */ + +typedef struct UX_SLAVE_INTERFACE_STRUCT +{ + ULONG ux_slave_interface_status; + struct UX_SLAVE_CLASS_STRUCT + *ux_slave_interface_class; + VOID *ux_slave_interface_class_instance; + + struct UX_INTERFACE_DESCRIPTOR_STRUCT + ux_slave_interface_descriptor; + struct UX_SLAVE_INTERFACE_STRUCT + *ux_slave_interface_next_interface; + struct UX_SLAVE_ENDPOINT_STRUCT + *ux_slave_interface_first_endpoint; +} UX_SLAVE_INTERFACE; + + +/* Define USBX Device Controller structure. */ + +typedef struct UX_SLAVE_DEVICE_STRUCT +{ + + ULONG ux_slave_device_state; + struct UX_DEVICE_DESCRIPTOR_STRUCT + ux_slave_device_descriptor; + struct UX_SLAVE_ENDPOINT_STRUCT + ux_slave_device_control_endpoint; + ULONG ux_slave_device_configuration_selected; + struct UX_CONFIGURATION_DESCRIPTOR_STRUCT + ux_slave_device_configuration_descriptor; + struct UX_SLAVE_INTERFACE_STRUCT + *ux_slave_device_first_interface; + struct UX_SLAVE_INTERFACE_STRUCT + *ux_slave_device_interfaces_pool; + ULONG ux_slave_device_interfaces_pool_number; + struct UX_SLAVE_ENDPOINT_STRUCT + *ux_slave_device_endpoints_pool; + ULONG ux_slave_device_endpoints_pool_number; + ULONG ux_slave_device_power_state; + +} UX_SLAVE_DEVICE; + + +/* Define USBX Device Controller structure. */ + +typedef struct UX_SLAVE_DCD_STRUCT +{ + + UINT ux_slave_dcd_status; + UINT ux_slave_dcd_controller_type; + UINT ux_slave_dcd_otg_capabilities; + UINT ux_slave_dcd_irq; + ULONG ux_slave_dcd_io; + ULONG ux_slave_dcd_device_address; + UINT (*ux_slave_dcd_function) (struct UX_SLAVE_DCD_STRUCT *,UINT, VOID *); + void *ux_slave_dcd_controller_hardware; + +#if defined(UX_DEVICE_STANDALONE) + UINT (*ux_device_dcd_task_function)(struct UX_SLAVE_DCD_STRUCT *); +#endif + +} UX_SLAVE_DCD; + +/* Define USBX Device Class Command container structure. */ + +typedef struct UX_SLAVE_CLASS_COMMAND_STRUCT +{ + + UINT ux_slave_class_command_request; + VOID *ux_slave_class_command_container; + VOID *ux_slave_class_command_interface; + UINT ux_slave_class_command_pid; + UINT ux_slave_class_command_vid; + UINT ux_slave_class_command_class; + UINT ux_slave_class_command_subclass; + UINT ux_slave_class_command_protocol; + struct UX_SLAVE_CLASS_STRUCT + *ux_slave_class_command_class_ptr; + VOID *ux_slave_class_command_parameter; + VOID *ux_slave_class_command_interface_number; + +} UX_SLAVE_CLASS_COMMAND; + + +/* Define USBX Device Class container structure. */ + +typedef struct UX_SLAVE_CLASS_STRUCT +{ + +#if defined(UX_NAME_REFERENCED_BY_POINTER) + const UCHAR *ux_slave_class_name; +#else + UCHAR ux_slave_class_name[UX_MAX_CLASS_NAME_LENGTH + 1]; /* "+1" for string null-terminator */ +#endif + + UINT ux_slave_class_status; + UINT (*ux_slave_class_entry_function) (struct UX_SLAVE_CLASS_COMMAND_STRUCT *); + VOID *ux_slave_class_instance; + VOID *ux_slave_class_client; +#if !defined(UX_DEVICE_STANDALONE) + UX_THREAD ux_slave_class_thread; + VOID *ux_slave_class_thread_stack; +#else + UINT (*ux_slave_class_task_function)(VOID *class_instance); +#endif + VOID *ux_slave_class_interface_parameter; + ULONG ux_slave_class_interface_number; + ULONG ux_slave_class_configuration_number; + struct UX_SLAVE_INTERFACE_STRUCT + *ux_slave_class_interface; + +} UX_SLAVE_CLASS; + +/* Define USBX Memory Management structure. */ + +typedef struct UX_MEMORY_BLOCK_STRUCT +{ + + ULONG ux_memory_block_size; + ULONG ux_memory_block_status; + struct UX_MEMORY_BLOCK_STRUCT + *ux_memory_block_next; + struct UX_MEMORY_BLOCK_STRUCT + *ux_memory_block_previous; +} UX_MEMORY_BLOCK; + + +typedef struct UX_SYSTEM_STRUCT +{ + + UX_MEMORY_BLOCK *ux_system_regular_memory_pool_start; + ULONG ux_system_regular_memory_pool_size; + ULONG ux_system_regular_memory_pool_free; + UX_MEMORY_BLOCK *ux_system_cache_safe_memory_pool_start; + ULONG ux_system_cache_safe_memory_pool_size; + ULONG ux_system_cache_safe_memory_pool_free; +#ifdef UX_ENABLE_MEMORY_STATISTICS + UCHAR *ux_system_regular_memory_pool_base; + ALIGN_TYPE ux_system_regular_memory_pool_max_start_offset; + ALIGN_TYPE ux_system_regular_memory_pool_min_free; + UCHAR *ux_system_cache_safe_memory_pool_base; + ALIGN_TYPE ux_system_cache_safe_memory_pool_max_start_offset; + ALIGN_TYPE ux_system_cache_safe_memory_pool_min_free; + ULONG ux_system_regular_memory_pool_alloc_count; + ULONG ux_system_regular_memory_pool_alloc_total; + ULONG ux_system_regular_memory_pool_alloc_max_count; + ULONG ux_system_regular_memory_pool_alloc_max_total; + ULONG ux_system_cache_safe_memory_pool_alloc_count; + ULONG ux_system_cache_safe_memory_pool_alloc_total; + ULONG ux_system_cache_safe_memory_pool_alloc_max_count; + ULONG ux_system_cache_safe_memory_pool_alloc_max_total; +#endif + + UINT ux_system_thread_lowest_priority; +#if !defined(UX_STANDALONE) + UX_MUTEX ux_system_mutex; +#endif + +#ifndef UX_DISABLE_ERROR_HANDLER + UINT ux_system_last_error; + UINT ux_system_error_count; + VOID (*ux_system_error_callback_function) (UINT system_level, UINT system_context, UINT error_code); +#endif + +#ifdef UX_ENABLE_DEBUG_LOG + ULONG ux_system_debug_code; + ULONG ux_system_debug_count; + UCHAR *ux_system_debug_log_buffer; + UCHAR *ux_system_debug_log_head; + UCHAR *ux_system_debug_log_tail; + ULONG ux_system_debug_log_size; + VOID (*ux_system_debug_callback_function) (UCHAR *debug_message, ULONG debug_value); +#endif +} UX_SYSTEM; + + +/* Define USBX System Host Data structure. */ + +typedef struct UX_SYSTEM_HOST_STRUCT +{ + +#if UX_MAX_CLASS_DRIVER > 1 + UINT ux_system_host_max_class; +#endif + UX_HOST_CLASS *ux_system_host_class_array; + +#if UX_MAX_HCD > 1 + UINT ux_system_host_max_hcd; +#endif + UINT ux_system_host_registered_hcd; + UX_HCD *ux_system_host_hcd_array; + +#if UX_MAX_DEVICES > 1 + ULONG ux_system_host_max_devices; +#endif + UX_DEVICE *ux_system_host_device_array; + + ULONG ux_system_host_max_ed; + ULONG ux_system_host_max_td; + ULONG ux_system_host_max_iso_td; + +#if !defined(UX_HOST_STANDALONE) + UCHAR *ux_system_host_enum_thread_stack; + UX_THREAD ux_system_host_enum_thread; + UX_SEMAPHORE ux_system_host_enum_semaphore; +#endif + +#if UX_MAX_DEVICES > 1 + VOID (*ux_system_host_enum_hub_function) (VOID); +#endif + +#if !defined(UX_HOST_STANDALONE) + UCHAR *ux_system_host_hcd_thread_stack; + UX_THREAD ux_system_host_hcd_thread; + UX_SEMAPHORE ux_system_host_hcd_semaphore; +#endif + +#if defined(UX_OTG_SUPPORT) && !defined(UX_OTG_STANDALONE) + UCHAR *ux_system_host_hnp_polling_thread_stack; + UX_THREAD ux_system_host_hnp_polling_thread; +#endif + +#if defined(UX_HOST_STANDALONE) + struct UX_DEVICE_STRUCT + *ux_system_host_enum_device; + struct UX_DEVICE_STRUCT + *ux_system_host_enum_lock; + struct UX_TRANSFER_STRUCT + *ux_system_host_pending_transfers; +#if UX_MAX_DEVICES > 1 + struct UX_HOST_CLASS_HUB_STRUCT + *ux_system_host_hub_list; +#endif +#endif + + UINT (*ux_system_host_change_function) (ULONG, UX_HOST_CLASS *, VOID *); +} UX_SYSTEM_HOST; + +#if UX_MAX_CLASS_DRIVER > 1 +#define UX_SYSTEM_HOST_MAX_CLASS_GET() (_ux_system_host->ux_system_host_max_class) +#define UX_SYSTEM_HOST_MAX_CLASS_SET(n) do { _ux_system_host->ux_system_host_max_class = (n); } while(0) +#else +#define UX_SYSTEM_HOST_MAX_CLASS_GET() (1) +#define UX_SYSTEM_HOST_MAX_CLASS_SET(n) UX_PARAMETER_NOT_USED(n) +#endif + +#if UX_MAX_HCD > 1 +#define UX_SYSTEM_HOST_MAX_HCD_GET() (_ux_system_host->ux_system_host_max_hcd) +#define UX_SYSTEM_HOST_MAX_HCD_SET(n) do { _ux_system_host->ux_system_host_max_hcd = (n); } while(0) +#else +#define UX_SYSTEM_HOST_MAX_HCD_GET() (1) +#define UX_SYSTEM_HOST_MAX_HCD_SET(n) UX_PARAMETER_NOT_USED(n) +#endif + +#if UX_MAX_DEVICES > 1 +#define UX_SYSTEM_HOST_MAX_DEVICES_SET(n) do { _ux_system_host->ux_system_host_max_devices = (n); } while(0) +#define UX_SYSTEM_HOST_MAX_DEVICES_GET() (_ux_system_host->ux_system_host_max_devices) +#else +#define UX_SYSTEM_HOST_MAX_DEVICES_SET(n) UX_PARAMETER_NOT_USED(n) +#define UX_SYSTEM_HOST_MAX_DEVICES_GET() (1) +#endif + + +typedef struct UX_SYSTEM_SLAVE_STRUCT +{ + + UX_SLAVE_DCD ux_system_slave_dcd; + UX_SLAVE_DEVICE ux_system_slave_device; + UCHAR *ux_system_slave_device_framework; + ULONG ux_system_slave_device_framework_length; + UCHAR *ux_system_slave_device_framework_full_speed; + ULONG ux_system_slave_device_framework_length_full_speed; + UCHAR *ux_system_slave_device_framework_high_speed; + ULONG ux_system_slave_device_framework_length_high_speed; + UCHAR *ux_system_slave_string_framework; + ULONG ux_system_slave_string_framework_length; + UCHAR *ux_system_slave_language_id_framework; + ULONG ux_system_slave_language_id_framework_length; + UCHAR *ux_system_slave_dfu_framework; + ULONG ux_system_slave_dfu_framework_length; +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + UINT ux_system_slave_max_class; +#endif + UX_SLAVE_CLASS *ux_system_slave_class_array; + UX_SLAVE_CLASS *ux_system_slave_interface_class_array[UX_MAX_SLAVE_INTERFACES]; + ULONG ux_system_slave_speed; + ULONG ux_system_slave_power_state; + ULONG ux_system_slave_remote_wakeup_capability; + ULONG ux_system_slave_remote_wakeup_enabled; + ULONG ux_system_slave_device_dfu_capabilities; + ULONG ux_system_slave_device_dfu_detach_timeout; + ULONG ux_system_slave_device_dfu_transfer_size; + ULONG ux_system_slave_device_dfu_state_machine; + ULONG ux_system_slave_device_dfu_mode; + UINT (*ux_system_slave_change_function) (ULONG); + ULONG ux_system_slave_device_vendor_request; + UINT (*ux_system_slave_device_vendor_request_function) (ULONG, ULONG, ULONG, ULONG, UCHAR *, ULONG *); + +} UX_SYSTEM_SLAVE; + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 +#define UX_SYSTEM_DEVICE_MAX_CLASS_SET(n) do { _ux_system_slave->ux_system_slave_max_class = (n); } while(0) +#define UX_SYSTEM_DEVICE_MAX_CLASS_GET() (_ux_system_slave->ux_system_slave_max_class) +#else +#define UX_SYSTEM_DEVICE_MAX_CLASS_SET(n) do { UX_PARAMETER_NOT_USED(n); } while(0) +#define UX_SYSTEM_DEVICE_MAX_CLASS_GET() (1) +#endif + +typedef struct UX_SYSTEM_OTG_STRUCT +{ + +#if !defined(UX_OTG_STANDALONE) + UX_THREAD ux_system_otg_thread; + UCHAR *ux_system_otg_thread_stack; + UX_SEMAPHORE ux_system_otg_semaphore; +#endif + UINT (*ux_system_otg_function) (ULONG); + ULONG ux_system_otg_mode; + ULONG ux_system_otg_io; + ULONG ux_system_otg_vbus_state; + ULONG ux_system_otg_change_mode_event; + ULONG ux_system_otg_change_vbus_event; + ULONG ux_system_otg_slave_role_swap_flag; + ULONG ux_system_otg_slave_set_feature_flag; + ULONG ux_system_otg_device_type; + VOID (*ux_system_otg_vbus_function) (ULONG); + VOID (*ux_system_otg_change_mode_callback) (ULONG); +} UX_SYSTEM_OTG; + +/* Define Data Pump Class instance structure. */ + + +typedef struct UX_HOST_CLASS_DPUMP_STRUCT +{ + + struct UX_HOST_CLASS_DPUMP_STRUCT + *ux_host_class_dpump_next_instance; + UX_HOST_CLASS *ux_host_class_dpump_class; + UX_DEVICE *ux_host_class_dpump_device; + UX_INTERFACE *ux_host_class_dpump_interface; + UX_ENDPOINT *ux_host_class_dpump_bulk_out_endpoint; + UX_ENDPOINT *ux_host_class_dpump_bulk_in_endpoint; + UX_ENDPOINT *ux_host_class_dpump_interrupt_endpoint; + UINT ux_host_class_dpump_state; +#if !defined(UX_HOST_STANDALONE) + UX_SEMAPHORE ux_host_class_dpump_semaphore; +#else + ULONG ux_host_class_dpump_flags; +#endif +} UX_HOST_CLASS_DPUMP; + + +/* Define the system API mappings based on the error checking + selected by the user. Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef UX_SOURCE_CODE + + +/* Define USBX Services. */ + +#define ux_system_initialize _ux_system_initialize +#define ux_system_uninitialize _ux_system_uninitialize +#define ux_system_tasks_run _ux_system_tasks_run + +#define ux_host_class_hub_entry _ux_host_class_hub_entry + +#define ux_host_class_storage_entry _ux_host_class_storage_entry + +#define ux_host_stack_class_get _ux_host_stack_class_get +#define ux_host_stack_class_instance_create _ux_host_stack_class_instance_create +#define ux_host_stack_class_instance_destroy _ux_host_stack_class_instance_destroy +#define ux_host_stack_class_instance_get _ux_host_stack_class_instance_get +#define ux_host_stack_class_register _ux_host_stack_class_register +#define ux_host_stack_class_unregister _ux_host_stack_class_unregister +#define ux_host_stack_configuration_interface_get _ux_host_stack_configuration_interface_get +#define ux_host_stack_device_configuration_activate _ux_host_stack_device_configuration_activate +#define ux_host_stack_device_configuration_deactivate _ux_host_stack_device_configuration_deactivate +#define ux_host_stack_device_configuration_get _ux_host_stack_device_configuration_get +#define ux_host_stack_device_configuration_select _ux_host_stack_device_configuration_select +#define ux_host_stack_device_get _ux_host_stack_device_get +#define ux_host_stack_device_string_get _ux_host_stack_device_string_get +#define ux_host_stack_endpoint_transfer_abort _ux_host_stack_endpoint_transfer_abort +#define ux_host_stack_hcd_register _ux_host_stack_hcd_register +#define ux_host_stack_hcd_unregister _ux_host_stack_hcd_unregister +#define ux_host_stack_initialize _ux_host_stack_initialize +#define ux_host_stack_uninitialize _ux_host_stack_uninitialize +#define ux_host_stack_interface_endpoint_get _ux_host_stack_interface_endpoint_get +#define ux_host_stack_interface_setting_select _ux_host_stack_interface_setting_select +#define ux_host_stack_transfer_request _ux_host_stack_transfer_request +#define ux_host_stack_transfer_request_abort _ux_host_stack_transfer_request_abort +#define ux_host_stack_hnp_polling_thread_entry _ux_host_stack_hnp_polling_thread_entry +#define ux_host_stack_role_swap _ux_host_stack_role_swap +#define ux_host_stack_device_configuration_reset _ux_host_stack_device_configuration_reset + +#define ux_host_stack_tasks_run _ux_host_stack_tasks_run +#define ux_host_stack_transfer_run _ux_host_stack_transfer_run + +#define ux_utility_pci_class_scan _ux_utility_pci_class_scan +#define ux_utility_pci_read _ux_utility_pci_read +#define ux_utility_pci_write _ux_utility_pci_write + +#define ux_device_stack_alternate_setting_get _ux_device_stack_alternate_setting_get +#define ux_device_stack_alternate_setting_set _ux_device_stack_alternate_setting_set +#define ux_device_stack_class_register _ux_device_stack_class_register +#define ux_device_stack_class_unregister _ux_device_stack_class_unregister +#define ux_device_stack_configuration_get _ux_device_stack_configuration_get +#define ux_device_stack_configuration_set _ux_device_stack_configuration_set +#define ux_device_stack_descriptor_send _ux_device_stack_descriptor_send +#define ux_device_stack_connect _ux_device_stack_connect +#define ux_device_stack_disconnect _ux_device_stack_disconnect +#define ux_device_stack_endpoint_stall _ux_device_stack_endpoint_stall +#define ux_device_stack_host_wakeup _ux_device_stack_host_wakeup +#define ux_device_stack_initialize _ux_device_stack_initialize +#define ux_device_stack_uninitialize _ux_device_stack_uninitialize +#define ux_device_stack_interface_delete _ux_device_stack_interface_delete +#define ux_device_stack_interface_get _ux_device_stack_interface_get +#define ux_device_stack_interface_set _ux_device_stack_interface_set +#define ux_device_stack_interface_start _ux_device_stack_interface_start +#define ux_device_stack_transfer_request _ux_device_stack_transfer_request +#define ux_device_stack_transfer_abort _ux_device_stack_transfer_abort + +#define ux_device_stack_tasks_run _ux_device_stack_tasks_run +#define ux_device_stack_transfer_run _ux_device_stack_transfer_run + +#define ux_hcd_ehci_initialize _ux_hcd_ehci_initialize +#define ux_hcd_isp1161_initialize _ux_hcd_isp1161_initialize +#define ux_hcd_ohci_initialize _ux_hcd_ohci_initialize +#define ux_hcd_sim_host_initialize _ux_hcd_sim_host_initialize +#define ux_dcd_sim_slave_initialize _ux_dcd_sim_slave_initialize + +#define ux_network_driver_init _ux_network_driver_init + +#endif + + +/* Define USBX API prototypes. */ + +UINT ux_system_initialize(VOID *non_cached_memory_pool_start, ULONG non_cached_memory_size, + VOID *cached_memory_pool_start, ULONG cached_memory_size); +UINT ux_system_uninitialize(VOID); +UINT ux_system_tasks_run(VOID); + +/* Define USBX Host API prototypes. */ + +UINT ux_hcd_ehci_initialize(UX_HCD *hcd); +UINT ux_hcd_isp1161_initialize(UX_HCD *hcd); +UINT ux_hcd_ohci_initialize(UX_HCD *hcd); +UINT ux_hcd_sim_host_initialize(UX_HCD *hcd); + +UINT ux_host_stack_class_get(UCHAR *class_name, UX_HOST_CLASS **host_class); +UINT ux_host_stack_class_instance_create(UX_HOST_CLASS *host_class, VOID *class_instance); +UINT ux_host_stack_class_instance_destroy(UX_HOST_CLASS *host_class, VOID *class_instance); +UINT ux_host_stack_class_instance_get(UX_HOST_CLASS *host_class, UINT class_index, VOID **class_instance); +UINT ux_host_stack_class_register(UCHAR *class_name, UINT (*class_entry_function)(struct UX_HOST_CLASS_COMMAND_STRUCT *)); +UINT ux_host_stack_class_unregister(UINT (*class_entry_function)(struct UX_HOST_CLASS_COMMAND_STRUCT *)); +UINT ux_host_stack_configuration_interface_get(UX_CONFIGURATION *configuration, UINT interface_index, + UINT alternate_setting_index, UX_INTERFACE **interface); +UINT ux_host_stack_device_configuration_activate(UX_CONFIGURATION *configuration); +UINT ux_host_stack_device_configuration_deactivate(UX_DEVICE *device); +UINT ux_host_stack_device_configuration_get(UX_DEVICE *device, UINT configuration_index, UX_CONFIGURATION **configuration); +UINT ux_host_stack_device_configuration_select(UX_CONFIGURATION *configuration); +UINT ux_host_stack_device_get(ULONG device_index, UX_DEVICE **device); +UINT ux_host_stack_device_string_get(UX_DEVICE *device, UCHAR *descriptor_buffer, ULONG length, ULONG language_id, ULONG string_index); +UINT ux_host_stack_endpoint_transfer_abort(UX_ENDPOINT *endpoint); +UINT ux_host_stack_hcd_register(UCHAR *hcd_name, UINT (*hcd_initialize_function)(struct UX_HCD_STRUCT *), ULONG hcd_param1, ULONG hcd_param2); +UINT ux_host_stack_hcd_unregister(UCHAR *hcd_name, ULONG hcd_param1, ULONG hcd_param2); +UINT ux_host_stack_initialize(UINT (*ux_system_host_change_function)(ULONG, UX_HOST_CLASS *, VOID *)); +UINT ux_host_stack_uninitialize(VOID); +UINT ux_host_stack_interface_endpoint_get(UX_INTERFACE *interface, UINT endpoint_index, UX_ENDPOINT **endpoint); +UINT ux_host_stack_interface_setting_select(UX_INTERFACE *interface); +UINT ux_host_stack_transfer_request(UX_TRANSFER *transfer_request); +UINT ux_host_stack_transfer_request_abort(UX_TRANSFER *transfer_request); +VOID ux_host_stack_hnp_polling_thread_entry(ULONG id); +UINT ux_host_stack_role_swap(UX_DEVICE *device); +UINT ux_host_stack_device_configuration_reset(UX_DEVICE *device); + +UINT ux_host_stack_tasks_run(VOID); +UINT ux_host_stack_transfer_run(UX_TRANSFER *transfer_request); + +/* Define USBX Device API prototypes. */ + +UINT ux_dcd_at91_initialize(ULONG dcd_io); +UINT ux_dcd_isp1181_initialize(ULONG dcd_io, ULONG dcd_irq, ULONG dcd_vbus_address); +UINT ux_dcd_ml6965_initialize(ULONG dcd_io, ULONG dcd_irq, ULONG dcd_vbus_address); +UINT ux_dcd_sim_slave_initialize(VOID); + +UINT ux_device_class_storage_entry(UX_SLAVE_CLASS_COMMAND *command); +VOID ux_device_class_storage_thread(ULONG); +UINT ux_device_stack_alternate_setting_get(ULONG interface_value); +UINT ux_device_stack_alternate_setting_set(ULONG interface_value, ULONG alternate_setting_value); +UINT ux_device_stack_class_register(UCHAR *class_name, + UINT (*class_entry_function)(struct UX_SLAVE_CLASS_COMMAND_STRUCT *), + ULONG configuration_number, + ULONG interface_number, + VOID *parameter); +UINT ux_device_stack_class_unregister(UCHAR *class_name, + UINT (*class_entry_function)(struct UX_SLAVE_CLASS_COMMAND_STRUCT *)); +UINT ux_device_stack_configuration_get(VOID); +UINT ux_device_stack_configuration_set(ULONG configuration_value); +UINT ux_device_stack_descriptor_send(ULONG descriptor_type, ULONG request_index, ULONG host_length); +UINT ux_device_stack_disconnect(VOID); +UINT ux_device_stack_endpoint_stall(UX_SLAVE_ENDPOINT *endpoint); +UINT ux_device_stack_host_wakeup(VOID); +UINT ux_device_stack_initialize(UCHAR * device_framework_high_speed, ULONG device_framework_length_high_speed, + UCHAR * device_framework_full_speed, ULONG device_framework_length_full_speed, + UCHAR * string_framework, ULONG string_framework_length, + UCHAR * language_id_framework, ULONG language_id_framework_length, + UINT (*ux_system_slave_change_function)(ULONG)); +UINT ux_device_stack_uninitialize(VOID); +UINT ux_device_stack_interface_delete(UX_SLAVE_INTERFACE *interface); +UINT ux_device_stack_interface_get(UINT interface_value); +UINT ux_device_stack_interface_set(UCHAR * device_framework, ULONG device_framework_length, + ULONG alternate_setting_value); +UINT ux_device_stack_interface_start(UX_SLAVE_INTERFACE *interface); +UINT ux_device_stack_transfer_request(UX_SLAVE_TRANSFER *transfer_request, ULONG slave_length, ULONG host_length); +UINT ux_device_stack_transfer_request_abort(UX_SLAVE_TRANSFER *transfer_request, ULONG completion_code); + +UINT ux_device_stack_tasks_run(VOID); +UINT ux_device_stack_transfer_run(UX_SLAVE_TRANSFER *transfer_request, ULONG slave_length, ULONG host_length); + +/* Include USBX utility and system file. */ + +#include "ux_utility.h" +#include "ux_system.h" + + + + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus + } +#endif + + +#endif + + diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_dcd_sim_slave.h b/src/Middlewares/ST/usbx/common/core/inc/ux_dcd_sim_slave.h new file mode 100644 index 00000000..f3e1e46d --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_dcd_sim_slave.h @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Slave Simulator Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_dcd_sim_slave.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX slave simulator. It is designed to work ONLY with the USBX */ +/* host simulator. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added HCD connected to, */ +/* supported bi-dir-endpoints, */ +/* resulting in version 6.1.6 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DCD_SIM_SLAVE_H +#define UX_DCD_SIM_SLAVE_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define USB slave simulator major equivalences. */ + +#define UX_DCD_SIM_SLAVE_SLAVE_CONTROLLER 98 +#define UX_DCD_SIM_SLAVE_MAX_ED 16 + + +/* Define USB slave simulator error code register bits. */ + +#define UX_DCD_SIM_SLAVE_ERROR_TRANSMISSION_OK 0x00000001u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_MASK 0x0000000eu +#define UX_DCD_SIM_SLAVE_ERROR_CODE_SHIFT 0x00000001u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_PID_ERROR 0x00000001u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_PID_UNKNOWN 0x00000002u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_UNEXPECTED_PACKET 0x00000003u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_TOKEN_CRC 0x00000004u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_DATA_CRC 0x00000005u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_TIME_OUT 0x00000006u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_BABBLE 0x00000007u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_UNEXPECTED_EOP 0x00000008u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_NAK 0x00000009u +#define UX_DCD_SIM_SLAVE_ERROR_CODE_STALLED 0x0000000au +#define UX_DCD_SIM_SLAVE_ERROR_CODE_OVERFLOW 0x0000000bu +#define UX_DCD_SIM_SLAVE_ERROR_CODE_EMPTY_PACKET 0x0000000cu +#define UX_DCD_SIM_SLAVE_ERROR_CODE_BIT_STUFFING 0x0000000du +#define UX_DCD_SIM_SLAVE_ERROR_CODE_SYNC_ERROR 0x0000000eu +#define UX_DCD_SIM_SLAVE_ERROR_CODE_DATA_TOGGLE 0x0000000fu + + +/* Define USB slave simulator physical endpoint status definition. */ + +#define UX_DCD_SIM_SLAVE_ED_STATUS_UNUSED 0u +#define UX_DCD_SIM_SLAVE_ED_STATUS_USED 1u +#define UX_DCD_SIM_SLAVE_ED_STATUS_TRANSFER 2u +#define UX_DCD_SIM_SLAVE_ED_STATUS_STALLED 4u +#define UX_DCD_SIM_SLAVE_ED_STATUS_DONE 8u + + +/* Define USB slave simulator physical endpoint structure. */ + +typedef struct UX_DCD_SIM_SLAVE_ED_STRUCT +{ + + ULONG ux_sim_slave_ed_status; + ULONG ux_sim_slave_ed_index; + ULONG ux_sim_slave_ed_payload_length; + ULONG ux_sim_slave_ed_ping_pong; + ULONG ux_sim_slave_ed_status_register; + ULONG ux_sim_slave_ed_configuration_value; + struct UX_SLAVE_ENDPOINT_STRUCT + *ux_sim_slave_ed_endpoint; +} UX_DCD_SIM_SLAVE_ED; + + +/* Define USB slave simulator DCD structure definition. */ + +typedef struct UX_DCD_SIM_SLAVE_STRUCT +{ + + struct UX_SLAVE_DCD_STRUCT + *ux_dcd_sim_slave_dcd_owner; + struct UX_DCD_SIM_SLAVE_ED_STRUCT + ux_dcd_sim_slave_ed[UX_DCD_SIM_SLAVE_MAX_ED]; +#ifdef UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT + struct UX_DCD_SIM_SLAVE_ED_STRUCT + ux_dcd_sim_slave_ed_in[UX_DCD_SIM_SLAVE_MAX_ED]; +#endif + UINT (*ux_dcd_sim_slave_dcd_control_request_process_hub)(UX_SLAVE_TRANSFER *transfer_request); + VOID *ux_dcd_sim_slave_hcd; +} UX_DCD_SIM_SLAVE; + + +/* Define slave simulator function prototypes. */ + +UINT _ux_dcd_sim_slave_address_set(UX_DCD_SIM_SLAVE *dcd_sim_slave, ULONG address); +UINT _ux_dcd_sim_slave_endpoint_create(UX_DCD_SIM_SLAVE *dcd_sim_slave, UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_dcd_sim_slave_endpoint_destroy(UX_DCD_SIM_SLAVE *dcd_sim_slave, UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_dcd_sim_slave_endpoint_reset(UX_DCD_SIM_SLAVE *dcd_sim_slave, UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_dcd_sim_slave_endpoint_stall(UX_DCD_SIM_SLAVE *dcd_sim_slave, UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_dcd_sim_slave_endpoint_status(UX_DCD_SIM_SLAVE *dcd_sim_slave, ULONG endpoint_index); +UINT _ux_dcd_sim_slave_frame_number_get(UX_DCD_SIM_SLAVE *dcd_sim_slave, ULONG *frame_number); +UINT _ux_dcd_sim_slave_function(UX_SLAVE_DCD *dcd, UINT function, VOID *parameter); +UINT _ux_dcd_sim_slave_initialize(VOID); +UINT _ux_dcd_sim_slave_initialize_complete(VOID); +UINT _ux_dcd_sim_slave_state_change(UX_DCD_SIM_SLAVE *dcd_sim_slave, ULONG state); +UINT _ux_dcd_sim_slave_transfer_request(UX_DCD_SIM_SLAVE *dcd_sim_slave, UX_SLAVE_TRANSFER *transfer_request); +UINT _ux_dcd_sim_slave_transfer_run(UX_DCD_SIM_SLAVE *dcd_sim_slave, UX_SLAVE_TRANSFER *transfer_request); +UINT _ux_dcd_sim_slave_transfer_abort(UX_DCD_SIM_SLAVE *dcd_sim_slave, UX_SLAVE_TRANSFER *transfer_request); + +/* Define Device Simulator Class API prototypes. */ + +#define ux_dcd_sim_slave_initialize _ux_dcd_sim_slave_initialize + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_device_class_dpump.h b/src/Middlewares/ST/usbx/common/core/inc/ux_device_class_dpump.h new file mode 100644 index 00000000..6c2ba173 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_device_class_dpump.h @@ -0,0 +1,144 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Data Pump Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_dpump.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX device dpump class. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 08-02-2021 Wen Wang Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_DPUMP_H +#define UX_DEVICE_CLASS_DPUMP_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define Storage Class USB Class constants. */ + +#define UX_SLAVE_CLASS_DPUMP_CLASS 0x99 +#define UX_SLAVE_CLASS_DPUMP_SUBCLASS 0x99 +#define UX_SLAVE_CLASS_DPUMP_PROTOCOL 0x99 + +/* Define Data Pump Class packet equivalences. */ +#define UX_DEVICE_CLASS_DPUMP_PACKET_SIZE 128 + + +/* Define Slave DPUMP Class Calling Parameter structure */ + +typedef struct UX_SLAVE_CLASS_DPUMP_PARAMETER_STRUCT +{ + VOID (*ux_slave_class_dpump_instance_activate)(VOID *); + VOID (*ux_slave_class_dpump_instance_deactivate)(VOID *); + +} UX_SLAVE_CLASS_DPUMP_PARAMETER; + +/* Define Slave Data Pump Class structure. */ + +typedef struct UX_SLAVE_CLASS_DPUMP_STRUCT +{ + UX_SLAVE_INTERFACE *ux_slave_class_dpump_interface; + UX_SLAVE_CLASS_DPUMP_PARAMETER ux_slave_class_dpump_parameter; + UX_SLAVE_ENDPOINT *ux_slave_class_dpump_bulkin_endpoint; + UX_SLAVE_ENDPOINT *ux_slave_class_dpump_bulkout_endpoint; + ULONG ux_slave_class_dpump_alternate_setting; +#if defined(UX_DEVICE_STANDALONE) + UCHAR *ux_device_class_dpump_write_buffer; + ULONG ux_device_class_dpump_write_requested_length; + ULONG ux_device_class_dpump_write_transfer_length; + ULONG ux_device_class_dpump_write_actual_length; + UINT ux_device_class_dpump_write_state; + UINT ux_device_class_dpump_write_status; + UCHAR *ux_device_class_dpump_read_buffer; + ULONG ux_device_class_dpump_read_requested_length; + ULONG ux_device_class_dpump_read_transfer_length; + ULONG ux_device_class_dpump_read_actual_length; + UINT ux_device_class_dpump_read_state; + UINT ux_device_class_dpump_read_status; +#endif +} UX_SLAVE_CLASS_DPUMP; + +/* Define Device Data Pump Class prototypes. */ + +UINT _ux_device_class_dpump_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_dpump_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_dpump_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_dpump_entry(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_dpump_read(UX_SLAVE_CLASS_DPUMP *dpump, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_device_class_dpump_read_run(UX_SLAVE_CLASS_DPUMP *dpump, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_device_class_dpump_write(UX_SLAVE_CLASS_DPUMP *dpump, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_device_class_dpump_write_run(UX_SLAVE_CLASS_DPUMP *dpump, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_device_class_dpump_change(UX_SLAVE_CLASS_COMMAND *command); + +/* Define Device DPUMP Class API prototypes. */ + +#define ux_device_class_dpump_entry _ux_device_class_dpump_entry +#define ux_device_class_dpump_read _ux_device_class_dpump_read +#define ux_device_class_dpump_read_run _ux_device_class_dpump_read_run +#define ux_device_class_dpump_write _ux_device_class_dpump_write +#define ux_device_class_dpump_write_run _ux_device_class_dpump_write_run + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_device_stack.h b/src/Middlewares/ST/usbx/common/core/inc/ux_device_stack.h new file mode 100644 index 00000000..0296bdf3 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_device_stack.h @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_stack.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the equivalences for the USBX Device Stack */ +/* component. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 08-02-2021 Wen Wang Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_STACK_H +#define UX_DEVICE_STACK_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define USB Device Stack prototypes. */ + +UINT _ux_device_stack_alternate_setting_get(ULONG interface_value); +UINT _ux_device_stack_alternate_setting_set(ULONG interface_value, ULONG alternate_setting_value); +UINT _ux_device_stack_class_register(UCHAR *class_name, + UINT (*class_entry_function)(struct UX_SLAVE_CLASS_COMMAND_STRUCT *), + ULONG configuration_number, + ULONG interface_number, + VOID *parameter); +UINT _ux_device_stack_clear_feature(ULONG request_type, ULONG request_value, ULONG request_index); +UINT _ux_device_stack_configuration_get(VOID); +UINT _ux_device_stack_configuration_set(ULONG configuration_value); +UINT _ux_device_stack_control_request_process(UX_SLAVE_TRANSFER *transfer_request); +UINT _ux_device_stack_descriptor_send(ULONG descriptor_type, ULONG request_index, ULONG host_length); +UINT _ux_device_stack_disconnect(VOID); +UINT _ux_device_stack_endpoint_stall(UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_device_stack_get_status(ULONG request_type, ULONG request_index, ULONG request_length); +UINT _ux_device_stack_host_wakeup(VOID); +UINT _ux_device_stack_initialize(UCHAR * device_framework_high_speed, ULONG device_framework_length_high_speed, + UCHAR * device_framework_full_speed, ULONG device_framework_length_full_speed, + UCHAR * string_framework, ULONG string_framework_length, + UCHAR * language_id_framework, ULONG language_id_framework_length, + UINT (*ux_system_slave_change_function)(ULONG)); +UINT _ux_device_stack_interface_delete(UX_SLAVE_INTERFACE *interface); +UINT _ux_device_stack_interface_get(UINT interface_value); +UINT _ux_device_stack_interface_set(UCHAR * device_framework, ULONG device_framework_length, + ULONG alternate_setting_value); +UINT _ux_device_stack_interface_start(UX_SLAVE_INTERFACE *interface); +UINT _ux_device_stack_set_feature(ULONG request_type, ULONG request_value, ULONG request_index); +UINT _ux_device_stack_transfer_all_request_abort(UX_SLAVE_ENDPOINT *endpoint, ULONG completion_code); +UINT _ux_device_stack_transfer_request(UX_SLAVE_TRANSFER *transfer_request, ULONG slave_length, ULONG host_length); +UINT _ux_device_stack_transfer_abort(UX_SLAVE_TRANSFER *transfer_request, ULONG completion_code); +UINT _ux_device_stack_class_unregister(UCHAR *class_name, UINT (*class_entry_function)(struct UX_SLAVE_CLASS_COMMAND_STRUCT *)); +UINT _ux_device_stack_microsoft_extension_register(ULONG vendor_request, UINT (*vendor_request_function)(ULONG, ULONG, ULONG, ULONG, UCHAR *, ULONG *)); +UINT _ux_device_stack_uninitialize(VOID); + +UINT _ux_device_stack_tasks_run(VOID); +UINT _ux_device_stack_transfer_run(UX_SLAVE_TRANSFER *transfer_request, ULONG slave_length, ULONG host_length); + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_hcd_sim_host.h b/src/Middlewares/ST/usbx/common/core/inc/ux_hcd_sim_host.h new file mode 100644 index 00000000..fbeeaef8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_hcd_sim_host.h @@ -0,0 +1,278 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Simulator Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_hcd_sim_host.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX host simulator. It is designed to work ONLY with the USBX */ +/* device (slave) simulator. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* added controller disable, */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 11-09-2020 Chaoqiong Xiao Modified comment(s), */ +/* added HCD uninitialize, */ +/* resulting in version 6.1.2 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added port status variable, */ +/* resulting in version 6.1.6 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_HCD_SIM_HOST_H +#define UX_HCD_SIM_HOST_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define simulator host generic definitions. */ + +#define UX_HCD_SIM_HOST_CONTROLLER 99 +#define UX_HCD_SIM_HOST_MAX_PAYLOAD 4096 +#define UX_HCD_SIM_HOST_FRAME_DELAY 4 +#define UX_HCD_SIM_HOST_PERIODIC_ENTRY_NB 32 +#define UX_HCD_SIM_HOST_PERIODIC_ENTRY_MASK 0x1f +#define UX_HCD_SIM_HOST_AVAILABLE_BANDWIDTH 6000 + + + +/* Define simulator host completion code errors. */ + +#define UX_HCD_SIM_HOST_NO_ERROR 0x00 +#define UX_HCD_SIM_HOST_ERROR_CRC 0x01 +#define UX_HCD_SIM_HOST_ERROR_BIT_STUFFING 0x02 +#define UX_HCD_SIM_HOST_ERROR_DATA_TOGGLE 0x03 +#define UX_HCD_SIM_HOST_ERROR_STALL 0x04 +#define UX_HCD_SIM_HOST_ERROR_DEVICE_NOT_RESPONDING 0x05 +#define UX_HCD_SIM_HOST_ERROR_PID_FAILURE 0x06 +#define UX_HCD_SIM_HOST_ERROR_PID_UNEXPECTED 0x07 +#define UX_HCD_SIM_HOST_ERROR_DATA_OVERRRUN 0x08 +#define UX_HCD_SIM_HOST_ERROR_DATA_UNDERRUN 0x09 +#define UX_HCD_SIM_HOST_ERROR_BUFFER_OVERRRUN 0x0c +#define UX_HCD_SIM_HOST_ERROR_BUFFER_UNDERRUN 0x0d +#define UX_HCD_SIM_HOST_NOT_ACCESSED 0x0e +#define UX_HCD_SIM_HOST_NAK 0x0f + + +/* Define simulator host structure. */ + +typedef struct UX_HCD_SIM_HOST_STRUCT +{ + + struct UX_HCD_STRUCT + *ux_hcd_sim_host_hcd_owner; + ULONG ux_hcd_sim_host_hcor; + UINT ux_hcd_sim_host_nb_root_hubs; + ULONG ux_hcd_sim_host_port_status[1]; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_hcd_sim_host_ed_list; + struct UX_HCD_SIM_HOST_TD_STRUCT + *ux_hcd_sim_host_td_list; + struct UX_HCD_SIM_HOST_ISO_TD_STRUCT + *ux_hcd_sim_host_iso_td_list; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_hcd_sim_host_asynch_head_ed; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_hcd_sim_host_asynch_current_ed; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_hcd_sim_host_iso_head_ed; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_hcd_sim_host_interrupt_ed_list[32]; + UINT ux_hcd_sim_host_queue_empty; + UINT ux_hcd_sim_host_periodic_scheduler_active; + UINT ux_hcd_sim_host_interruptible; + ULONG ux_hcd_sim_host_interrupt_count; +#if !defined(UX_HOST_STANDALONE) + UX_TIMER ux_hcd_sim_host_timer; +#endif +} UX_HCD_SIM_HOST; + + +/* Define simulator host ED structure. */ + +typedef struct UX_HCD_SIM_HOST_ED_STRUCT +{ + + struct UX_HCD_SIM_HOST_TD_STRUCT + *ux_sim_host_ed_tail_td; + struct UX_HCD_SIM_HOST_TD_STRUCT + *ux_sim_host_ed_head_td; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_sim_host_ed_next_ed; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_sim_host_ed_previous_ed; + ULONG ux_sim_host_ed_status; + struct UX_ENDPOINT_STRUCT + *ux_sim_host_ed_endpoint; + ULONG ux_sim_host_ed_toggle; + ULONG ux_sim_host_ed_frame; +} UX_HCD_SIM_HOST_ED; + + +/* Define simulator host ED bitmap. */ + +#define UX_HCD_SIM_HOST_ED_STATIC 0x80000000u +#define UX_HCD_SIM_HOST_ED_SKIP 0x40000000u +#define UX_HCD_SIM_HOST_ED_TRANSFER 0x00100000u + + +/* Define simulator host TD structure. */ + +typedef struct UX_HCD_SIM_HOST_TD_STRUCT +{ + + UCHAR * ux_sim_host_td_buffer; + ULONG ux_sim_host_td_length; + struct UX_HCD_SIM_HOST_TD_STRUCT + *ux_sim_host_td_next_td; + struct UX_TRANSFER_STRUCT + *ux_sim_host_td_transfer_request; + struct UX_HCD_SIM_HOST_TD_STRUCT + *ux_sim_host_td_next_td_transfer_request; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_sim_host_td_ed; + ULONG ux_sim_host_td_actual_length; + ULONG ux_sim_host_td_status; + ULONG ux_sim_host_td_direction; + ULONG ux_sim_host_td_toggle; +} UX_HCD_SIM_HOST_TD; + + +/* Define simulator host TD bitmap. */ + +#define UX_HCD_SIM_HOST_TD_SETUP_PHASE 0x00010000 +#define UX_HCD_SIM_HOST_TD_DATA_PHASE 0x00020000 +#define UX_HCD_SIM_HOST_TD_STATUS_PHASE 0x00040000 +#define UX_HCD_SIM_HOST_TD_OUT 0x00000800 +#define UX_HCD_SIM_HOST_TD_IN 0x00001000 +#define UX_HCD_SIM_HOST_TD_ACK_PENDING 0x00002000 +#define UX_HCD_SIM_HOST_TD_TOGGLE_FROM_ED 0x80000000 + + +/* Define simulator host ISOCHRONOUS TD structure. */ + +typedef struct UX_HCD_SIM_HOST_ISO_TD_STRUCT +{ + + UCHAR * ux_sim_host_iso_td_buffer; + ULONG ux_sim_host_iso_td_length; + struct UX_HCD_SIM_HOST_ISO_TD_STRUCT + *ux_sim_host_iso_td_next_td; + struct UX_TRANSFER_STRUCT + *ux_sim_host_iso_td_transfer_request; + struct UX_HCD_SIM_HOST_ISO_TD_STRUCT + *ux_sim_host_iso_td_next_td_transfer_request; + struct UX_HCD_SIM_HOST_ED_STRUCT + *ux_sim_host_iso_td_ed; + ULONG ux_sim_host_iso_td_actual_length; + ULONG ux_sim_host_iso_td_status; + ULONG ux_sim_host_iso_td_direction; +} UX_HCD_SIM_HOST_ISO_TD; + + +/* Define simulator host function prototypes. */ + +VOID _ux_hcd_sim_host_asynch_queue_process(UX_HCD_SIM_HOST *hcd_sim_host); +VOID _ux_hcd_sim_host_asynch_schedule(UX_HCD_SIM_HOST *hcd_sim_host); +UINT _ux_hcd_sim_host_asynchronous_endpoint_create(UX_HCD_SIM_HOST *hcd_sim_host, UX_ENDPOINT *endpoint); +UINT _ux_hcd_sim_host_asynchronous_endpoint_destroy(UX_HCD_SIM_HOST *hcd_sim_host, UX_ENDPOINT *endpoint); +UX_HCD_SIM_HOST_ED + *_ux_hcd_sim_host_ed_obtain(UX_HCD_SIM_HOST *hcd_sim_host); +VOID _ux_hcd_sim_host_ed_td_clean(UX_HCD_SIM_HOST_ED *ed); +UINT _ux_hcd_sim_host_endpoint_reset(UX_HCD_SIM_HOST *hcd_sim_host, UX_ENDPOINT *endpoint); +UINT _ux_hcd_sim_host_entry(UX_HCD *hcd, UINT function, VOID *parameter); +UINT _ux_hcd_sim_host_frame_number_get(UX_HCD_SIM_HOST *hcd_sim_host, ULONG *frame_number); +VOID _ux_hcd_sim_host_frame_number_set(UX_HCD_SIM_HOST *hcd_sim_host, ULONG frame_number); +UINT _ux_hcd_sim_host_initialize(UX_HCD *hcd); +UINT _ux_hcd_sim_host_uninitialize(UX_HCD_SIM_HOST *hcd); +UINT _ux_hcd_sim_host_controller_disable(UX_HCD_SIM_HOST *hcd); +UINT _ux_hcd_sim_host_interrupt_endpoint_create(UX_HCD_SIM_HOST *hcd_sim_host, UX_ENDPOINT *endpoint); +VOID _ux_hcd_sim_host_iso_queue_process(UX_HCD_SIM_HOST *hcd_sim_host); +VOID _ux_hcd_sim_host_iso_schedule(UX_HCD_SIM_HOST *hcd_sim_host); +UINT _ux_hcd_sim_host_isochronous_endpoint_create(UX_HCD_SIM_HOST *hcd_sim_host, UX_ENDPOINT *endpoint); +UX_HCD_SIM_HOST_ISO_TD + *_ux_hcd_sim_host_isochronous_td_obtain(UX_HCD_SIM_HOST *hcd_sim_host); +UX_HCD_SIM_HOST_ED + *_ux_hcd_sim_host_least_traffic_list_get(UX_HCD_SIM_HOST *hcd_sim_host); +UINT _ux_hcd_sim_host_periodic_endpoint_destroy(UX_HCD_SIM_HOST *hcd_sim_host, UX_ENDPOINT *endpoint); +VOID _ux_hcd_sim_host_periodic_schedule(UX_HCD_SIM_HOST *hcd_sim_host); +UINT _ux_hcd_sim_host_periodic_tree_create(UX_HCD_SIM_HOST *hcd_sim_host); +ULONG _ux_hcd_sim_host_port_status_get(UX_HCD_SIM_HOST *hcd_sim_host, ULONG port_index); +UX_HCD_SIM_HOST_TD + *_ux_hcd_sim_host_regular_td_obtain(UX_HCD_SIM_HOST *hcd_sim_host); +UINT _ux_hcd_sim_host_request_bulk_transfer(UX_HCD_SIM_HOST *hcd_sim_host, UX_TRANSFER *transfer_request); +UINT _ux_hcd_sim_host_request_control_transfer(UX_HCD_SIM_HOST *hcd_sim_host, UX_TRANSFER *transfer_request); +UINT _ux_hcd_sim_host_request_interrupt_transfer(UX_HCD_SIM_HOST *hcd_sim_host, UX_TRANSFER *transfer_request); +UINT _ux_hcd_sim_host_request_isochronous_transfer(UX_HCD_SIM_HOST *hcd_sim_host, UX_TRANSFER *transfer_request); +UINT _ux_hcd_sim_host_request_transfer(UX_HCD_SIM_HOST *hcd_sim_host, UX_TRANSFER *transfer_request); +VOID _ux_hcd_sim_host_timer_function(ULONG hcd_sim_host_addr); +UINT _ux_hcd_sim_host_transaction_schedule(UX_HCD_SIM_HOST *hcd_sim_host, UX_HCD_SIM_HOST_ED *ed); +UINT _ux_hcd_sim_host_transfer_abort(UX_HCD_SIM_HOST *hcd_sim_host, UX_TRANSFER *transfer_request); +UINT _ux_hcd_sim_host_port_reset(UX_HCD_SIM_HOST *hcd_sim_host, ULONG port_index); + +UINT _ux_hcd_sim_host_transfer_run(UX_HCD_SIM_HOST *hcd_sim_host, UX_TRANSFER *transfer_request); + +/* Define Device Simulator Class API prototypes. */ + +#define ux_hcd_sim_host_initialize _ux_hcd_sim_host_initialize +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_host_class_dpump.h b/src/Middlewares/ST/usbx/common/core/inc/ux_host_class_dpump.h new file mode 100644 index 00000000..973a3939 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_host_class_dpump.h @@ -0,0 +1,118 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Data Pump Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_host_class_dpump.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX demo data pump class. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 08-02-2021 Wen Wang Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_HOST_CLASS_DPUMP_H +#define UX_HOST_CLASS_DPUMP_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define Data Pump Class constants. */ + +#define UX_HOST_CLASS_DPUMP_CLASS_TRANSFER_TIMEOUT 300000 +#define UX_HOST_CLASS_DPUMP_CLASS 0x99 +#define UX_HOST_CLASS_DPUMP_SUBCLASS 0x99 +#define UX_HOST_CLASS_DPUMP_PROTOCOL 0x99 + +/* Define Data Pump Class packet equivalences. */ +#define UX_HOST_CLASS_DPUMP_PACKET_SIZE 128 + +/* Define Data Pump Class Ioctl functions. */ +#define UX_HOST_CLASS_DPUMP_SELECT_ALTERNATE_SETTING 1 + +/* Define Data Pump Class string constants. */ + +#define UX_HOST_CLASS_DPUMP_GENERIC_NAME "USB DPUMP" + +/* Define R/W lock bits for standalone mode. */ + +#define UX_HOST_CLASS_DPUMP_READ_LOCK (1u<<0) +#define UX_HOST_CLASS_DPUMP_WRITE_LOCK (1u<<1) + +/* Define Printer Class function prototypes. */ + +UINT _ux_host_class_dpump_activate(UX_HOST_CLASS_COMMAND *command); +UINT _ux_host_class_dpump_configure(UX_HOST_CLASS_DPUMP *dpump); +UINT _ux_host_class_dpump_deactivate(UX_HOST_CLASS_COMMAND *command); +UINT _ux_host_class_dpump_endpoints_get(UX_HOST_CLASS_DPUMP *dpump); +UINT _ux_host_class_dpump_entry(UX_HOST_CLASS_COMMAND *command); +UINT _ux_host_class_dpump_read (UX_HOST_CLASS_DPUMP *dpump, UCHAR *data_pointer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_host_class_dpump_write(UX_HOST_CLASS_DPUMP *dpump, UCHAR * data_pointer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_host_class_dpump_ioctl(UX_HOST_CLASS_DPUMP *dpump, ULONG ioctl_function, + VOID *parameter); + + +#define ux_host_class_dpump_entry _ux_host_class_dpump_entry +#define ux_host_class_dpump_read _ux_host_class_dpump_read +#define ux_host_class_dpump_write _ux_host_class_dpump_write +#define ux_host_class_dpump_ioctl _ux_host_class_dpump_ioctl + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_host_stack.h b/src/Middlewares/ST/usbx/common/core/inc/ux_host_stack.h new file mode 100644 index 00000000..599e2907 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_host_stack.h @@ -0,0 +1,198 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_host_stack.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX Host Stack component. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* added uninitialize APIs, */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added configuration activate*/ +/* and deactivate support, */ +/* added host device string */ +/* descriptor get support, */ +/* updated internal function, */ +/* resulting in version 6.1.4 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_HOST_STACK_H +#define UX_HOST_STACK_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define Host Stack enumeration state machine states. */ + +#define UX_HOST_STACK_ENUM_PORT_ENABLE (UX_STATE_STEP + 0) +#define UX_HOST_STACK_ENUM_PORT_RESET (UX_STATE_STEP + 1) +#define UX_HOST_STACK_ENUM_PORT_RESET_WAIT (UX_STATE_STEP + 2) +#define UX_HOST_STACK_ENUM_DEVICE_ADDR_SET (UX_STATE_STEP + 3) +#define UX_HOST_STACK_ENUM_DEVICE_ADDR_SENT (UX_STATE_STEP + 4) +#define UX_HOST_STACK_ENUM_DEVICE_DESCR_READ (UX_STATE_STEP + 5) +#define UX_HOST_STACK_ENUM_DEVICE_DESCR_PARSE (UX_STATE_STEP + 6) +#define UX_HOST_STACK_ENUM_CONFIG_DESCR_READ (UX_STATE_STEP + 7) +#define UX_HOST_STACK_ENUM_CONFIG_DESCR_PARSE (UX_STATE_STEP + 8) +#define UX_HOST_STACK_ENUM_CONFIG_DESCR_NEXT (UX_STATE_STEP + 9) +#define UX_HOST_STACK_ENUM_CONFIG_SET (UX_STATE_STEP + 10) +#define UX_HOST_STACK_ENUM_CONFIG_ACTIVATE (UX_STATE_STEP + 11) +#define UX_HOST_STACK_ENUM_ACTIVATE (UX_STATE_STEP + 12) +#define UX_HOST_STACK_ENUM_ACTIVATE_WAIT (UX_STATE_STEP + 13) +#define UX_HOST_STACK_ENUM_RETRY (UX_STATE_STEP + 14) +#define UX_HOST_STACK_ENUM_NEXT (UX_STATE_STEP + 15) +#define UX_HOST_STACK_ENUM_TRANS_LOCK_WAIT (UX_STATE_STEP + 16) +#define UX_HOST_STACK_ENUM_TRANS_WAIT (UX_STATE_STEP + 17) +#define UX_HOST_STACK_ENUM_WAIT (UX_STATE_STEP + 18) +#define UX_HOST_STACK_ENUM_FAIL (UX_STATE_STEP + 19) +#define UX_HOST_STACK_ENUM_DONE (UX_STATE_STEP + 20) +#define UX_HOST_STACK_ENUM_IDLE (UX_STATE_STEP + 21) + + +/* Define Host Stack component function prototypes. */ + +#if UX_MAX_DEVICES > 1 +VOID _ux_host_stack_bandwidth_release(UX_HCD *hcd, UX_ENDPOINT *endpoint); +VOID _ux_host_stack_bandwidth_claim(UX_HCD *hcd, UX_ENDPOINT *endpoint); +UINT _ux_host_stack_bandwidth_check(UX_HCD *hcd, UX_ENDPOINT *endpoint); +#else +#define _ux_host_stack_bandwidth_release(a,b) +#define _ux_host_stack_bandwidth_claim(a,b) +#define _ux_host_stack_bandwidth_check(a,b) (UX_SUCCESS) +#endif + +UX_HOST_CLASS * _ux_host_stack_class_call(UX_HOST_CLASS_COMMAND *class_command); +UINT _ux_host_stack_class_device_scan(UX_DEVICE *device); +UINT _ux_host_stack_class_get(UCHAR *class_name, UX_HOST_CLASS **class); +UINT _ux_host_stack_class_instance_destroy(UX_HOST_CLASS *class, VOID *class_instance); +UINT _ux_host_stack_class_instance_create(UX_HOST_CLASS *class, VOID *class_instance); +UINT _ux_host_stack_class_instance_get(UX_HOST_CLASS *class, UINT class_index, VOID **class_instance); +UINT _ux_host_stack_class_instance_verify(UCHAR *class_name, VOID *class_instance); +UINT _ux_host_stack_class_interface_scan(UX_DEVICE *device); +UINT _ux_host_stack_class_register(UCHAR *class_name, + UINT (*class_entry_function)(struct UX_HOST_CLASS_COMMAND_STRUCT *)); +UINT _ux_host_stack_class_unregister(UINT (*class_entry_function)(struct UX_HOST_CLASS_COMMAND_STRUCT *)); +UINT _ux_host_stack_configuration_descriptor_parse(UX_DEVICE *device, UX_CONFIGURATION *configuration, UINT configuration_index); +UINT _ux_host_stack_configuration_enumerate(UX_DEVICE *device); +UINT _ux_host_stack_configuration_instance_create(UX_CONFIGURATION *configuration); +VOID _ux_host_stack_configuration_instance_delete(UX_CONFIGURATION *configuration); +UINT _ux_host_stack_configuration_interface_get(UX_CONFIGURATION *configuration, + UINT interface_index, UINT alternate_setting_index, + UX_INTERFACE **interface); +UINT _ux_host_stack_configuration_interface_scan(UX_CONFIGURATION *configuration); +UINT _ux_host_stack_configuration_set(UX_CONFIGURATION *configuration); +VOID _ux_host_stack_delay_ms(ULONG time); +UINT _ux_host_stack_device_address_set(UX_DEVICE *device); +UINT _ux_host_stack_device_configuration_activate(UX_CONFIGURATION *configuration); +UINT _ux_host_stack_device_configuration_deactivate(UX_DEVICE *device); +UINT _ux_host_stack_device_configuration_get(UX_DEVICE *device, UINT configuration_index, + UX_CONFIGURATION **configuration); +UINT _ux_host_stack_device_configuration_select(UX_CONFIGURATION *configuration); +UINT _ux_host_stack_device_configuration_reset(UX_DEVICE *device); +UINT _ux_host_stack_device_descriptor_read(UX_DEVICE *device); +UINT _ux_host_stack_device_get(ULONG device_index, UX_DEVICE **device); +UINT _ux_host_stack_device_string_get(UX_DEVICE *device, UCHAR *descriptor_buffer, ULONG length, ULONG language_id, ULONG string_index); +UINT _ux_host_stack_device_remove(UX_HCD *hcd, UX_DEVICE *parent, UINT port_index); +UINT _ux_host_stack_device_resources_free(UX_DEVICE *device); +UINT _ux_host_stack_endpoint_instance_create(UX_ENDPOINT *endpoint); +VOID _ux_host_stack_endpoint_instance_delete(UX_ENDPOINT *endpoint); +UINT _ux_host_stack_endpoint_reset(UX_ENDPOINT *endpoint); +UINT _ux_host_stack_endpoint_transfer_abort(UX_ENDPOINT *endpoint); +VOID _ux_host_stack_enum_thread_entry(ULONG input); +UINT _ux_host_stack_hcd_register(UCHAR *hcd_name, + UINT (*hcd_init_function)(struct UX_HCD_STRUCT *), ULONG hcd_param1, ULONG hcd_param2); +UINT _ux_host_stack_hcd_unregister(UCHAR *hcd_name, ULONG hcd_param1, ULONG hcd_param2); +VOID _ux_host_stack_hcd_thread_entry(ULONG input); +UINT _ux_host_stack_hcd_transfer_request(UX_TRANSFER *transfer_request); +UINT _ux_host_stack_initialize(UINT (*ux_system_host_change_function)(ULONG, UX_HOST_CLASS *, VOID *)); +UINT _ux_host_stack_uninitialize(VOID); +UINT _ux_host_stack_interface_endpoint_get(UX_INTERFACE *interface, UINT endpoint_index, UX_ENDPOINT **endpoint); +UINT _ux_host_stack_interface_instance_create(UX_INTERFACE *interface); +VOID _ux_host_stack_interface_instance_delete(UX_INTERFACE *interface); +UINT _ux_host_stack_interface_set(UX_INTERFACE *interface); +UINT _ux_host_stack_interface_setting_select(UX_INTERFACE *interface); +UINT _ux_host_stack_interfaces_scan(UX_CONFIGURATION *configuration, UCHAR * descriptor); +VOID _ux_host_stack_new_configuration_create(UX_DEVICE *device, UX_CONFIGURATION *configuration); +UX_DEVICE *_ux_host_stack_new_device_get(VOID); +UINT _ux_host_stack_new_device_create(UX_HCD *hcd, UX_DEVICE *device_owner, + UINT port_index, UINT device_speed, + UINT port_max_power, + UX_DEVICE **created_device); +UINT _ux_host_stack_new_endpoint_create(UX_INTERFACE *interface, UCHAR * interface_endpoint); +UINT _ux_host_stack_new_interface_create(UX_CONFIGURATION *configuration, UCHAR * descriptor, ULONG length); +VOID _ux_host_stack_rh_change_process(VOID); +UINT _ux_host_stack_rh_device_extraction(UX_HCD *hcd, UINT port_index); +UINT _ux_host_stack_rh_device_insertion(UX_HCD *hcd, UINT port_index); +UINT _ux_host_stack_transfer_request(UX_TRANSFER *transfer_request); +UINT _ux_host_stack_transfer_request_abort(UX_TRANSFER *transfer_request); +UINT _ux_host_stack_role_swap(UX_DEVICE *device); + +#if defined(UX_OTG_SUPPORT) +VOID _ux_host_stack_hnp_polling_thread_entry(ULONG id); +#endif + +UINT _ux_host_stack_tasks_run(VOID); +UINT _ux_host_stack_transfer_run(UX_TRANSFER *transfer_request); + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_system.h b/src/Middlewares/ST/usbx/common/core/inc/ux_system.h new file mode 100644 index 00000000..be9ba8e8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_system.h @@ -0,0 +1,162 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_system.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX main system component. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* added BOS support, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* added device printer name, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_SYSTEM_HOST_H +#define UX_SYSTEM_HOST_H + +/* Define System component function prototypes. Note that since ux_api.h + includes this file, the APIs are only declared if this file is included + by internal code in order to prevent duplicate declarations for + applications. */ + + +#ifdef UX_SOURCE_CODE +UINT _ux_system_initialize(VOID *regular_memory_pool_start, ULONG regular_memory_size, + VOID *cache_safe_memory_pool_start, ULONG cache_safe_memory_size); +UINT _ux_system_uninitialize(VOID); +UINT _ux_system_tasks_run(VOID); +#endif + +/* Define System component external data references. */ + +extern UX_SYSTEM *_ux_system; +extern UX_SYSTEM_HOST *_ux_system_host; +extern UX_SYSTEM_SLAVE *_ux_system_slave; +extern UX_SYSTEM_OTG *_ux_system_otg; +extern UCHAR _ux_system_endpoint_descriptor_structure[]; +extern UCHAR _ux_system_device_descriptor_structure[]; +extern UCHAR _ux_system_configuration_descriptor_structure[]; +extern UCHAR _ux_system_interface_descriptor_structure[]; +extern UCHAR _ux_system_interface_association_descriptor_structure[]; +extern UCHAR _ux_system_string_descriptor_structure[]; +extern UCHAR _ux_system_dfu_functional_descriptor_structure[]; +extern UCHAR _ux_system_hub_descriptor_structure[]; +extern UCHAR _ux_system_hid_descriptor_structure[]; +extern UCHAR _ux_system_class_audio_interface_descriptor_structure[]; +extern UCHAR _ux_system_class_audio_input_terminal_descriptor_structure[]; +extern UCHAR _ux_system_class_audio_output_terminal_descriptor_structure[]; +extern UCHAR _ux_system_class_audio_feature_unit_descriptor_structure[]; +extern UCHAR _ux_system_class_audio_streaming_interface_descriptor_structure[]; +extern UCHAR _ux_system_class_audio_streaming_endpoint_descriptor_structure[]; +extern UCHAR _ux_system_class_pima_storage_structure[]; +extern UCHAR _ux_system_class_pima_object_structure[]; +extern UCHAR _ux_system_ecm_interface_descriptor_structure[]; + +extern UCHAR _ux_system_bos_descriptor_structure[]; +extern UCHAR _ux_system_usb_2_0_extension_descriptor_structure[]; +extern UCHAR _ux_system_container_id_descriptor_structure[]; + +extern UINT _ux_system_host_hcd_periodic_tree_entries[32]; + +extern UCHAR _ux_system_host_class_hub_name[]; +extern UCHAR _ux_system_host_class_printer_name[]; +extern UCHAR _ux_system_host_class_storage_name[]; +extern UCHAR _ux_system_host_class_hid_name[]; +extern UCHAR _ux_system_host_class_audio_name[]; +extern UCHAR _ux_system_host_class_cdc_acm_name[]; +extern UCHAR _ux_system_host_class_cdc_dlc_name[]; +extern UCHAR _ux_system_host_class_cdc_ecm_name[]; +extern UCHAR _ux_system_host_class_prolific_name[]; +extern UCHAR _ux_system_host_class_dpump_name[]; +extern UCHAR _ux_system_host_class_pima_name[]; +extern UCHAR _ux_system_host_class_asix_name[]; +extern UCHAR _ux_system_host_class_swar_name[]; +extern UCHAR _ux_system_host_class_gser_name[]; +extern UCHAR _ux_system_host_class_hid_client_remote_control_name[]; +extern UCHAR _ux_system_host_class_hid_client_mouse_name[]; +extern UCHAR _ux_system_host_class_hid_client_keyboard_name[]; + +extern UCHAR _ux_system_host_hcd_ohci_name[]; +extern UCHAR _ux_system_host_hcd_ehci_name[]; +extern UCHAR _ux_system_host_hcd_isp1161_name[]; +extern UCHAR _ux_system_host_hcd_isp1362_name[]; +extern UCHAR _ux_system_host_hcd_sh2_name[]; +extern UCHAR _ux_system_host_hcd_rx_name[]; +extern UCHAR _ux_system_host_hcd_pic32_name[]; +extern UCHAR _ux_system_host_hcd_stm32_name[]; +extern UCHAR _ux_system_host_hcd_musb_name[]; +extern UCHAR _ux_system_host_hcd_atm7_name[]; +extern UCHAR _ux_system_host_hcd_simulator_name[]; + +extern UCHAR _ux_system_slave_class_storage_name[]; +extern UCHAR _ux_system_slave_class_storage_vendor_id[]; +extern UCHAR _ux_system_slave_class_storage_product_id[]; +extern UCHAR _ux_system_slave_class_storage_product_rev[]; +extern UCHAR _ux_system_slave_class_storage_product_serial[]; +extern UCHAR _ux_system_slave_class_audio_name[]; +extern UCHAR _ux_system_slave_class_cdc_acm_name[]; +extern UCHAR _ux_system_slave_class_dpump_name[]; +extern UCHAR _ux_system_slave_class_pima_name[]; +extern UCHAR _ux_system_slave_class_hid_name[]; +extern UCHAR _ux_system_slave_class_rndis_name[]; +extern UCHAR _ux_system_slave_class_cdc_ecm_name[]; +extern UCHAR _ux_system_slave_class_dfu_name[]; + +extern UCHAR _ux_system_device_class_printer_name[]; + +#if defined(UX_HOST_SIDE_ONLY) +#define _ux_system_host_tasks_run _ux_host_stack_tasks_run +#else +#define _ux_system_host_tasks_run _ux_system_tasks_run +#endif + +#if defined(UX_DEVICE_SIDE_ONLY) +#define _ux_system_device_tasks_run _ux_device_stack_tasks_run +#else +#define _ux_system_device_tasks_run _ux_system_tasks_run +#endif + +#endif + diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_user_sample.h b/src/Middlewares/ST/usbx/common/core/inc/ux_user_sample.h new file mode 100644 index 00000000..c1102124 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_user_sample.h @@ -0,0 +1,488 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* ux_user.h PORTABLE C */ +/* 6.1.10 */ +/* */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring USBX in specific */ +/* ways. This file will have an effect only if the application and */ +/* USBX library are built with UX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building USBX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 02-02-2021 Xiuwen Cai Modified comment(s), added */ +/* compile option for using */ +/* packet pool from NetX, */ +/* resulting in version 6.1.4 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added DFU_UPLOAD option, */ +/* added macro to enable */ +/* device bi-dir-endpoints, */ +/* added macro to disable CDC- */ +/* ACM transmission support, */ +/* resulting in version 6.1.6 */ +/* 06-02-2021 Xiuwen Cai Modified comment(s), added */ +/* transfer timeout value */ +/* options, */ +/* resulting in version 6.1.7 */ +/* 08-02-2021 Wen Wang Modified comment(s), */ +/* fixed spelling error, */ +/* resulting in version 6.1.8 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* added option for assert, */ +/* resulting in version 6.1.9 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* added option for device */ +/* audio feedback endpoint, */ +/* added option for MTP, */ +/* added options for HID */ +/* interrupt OUT support, */ +/* added option to validate */ +/* class code in enumeration, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_USER_H +#define UX_USER_H + + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + though the compiler's equivalent of the -D option. */ +/* #define UX_THREAD_STACK_SIZE (2 * 1024) */ + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Override various options with default values already assigned in ux_api.h or ux_port.h. Please + also refer to ux_port.h for descriptions on each of these options. */ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE 1000 +*/ +#define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND) + +/* Define control transfer timeout value in millisecond. + The default is 10000 milliseconds. */ +/* +#define UX_CONTROL_TRANSFER_TIMEOUT 10000 +*/ + +/* Define non control transfer timeout value in millisecond. + The default is 50000 milliseconds. */ +/* +#define UX_NON_CONTROL_TRANSFER_TIMEOUT 50000 +*/ + + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +/* #define UX_MAX_CLASSES 3 +*/ + + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ + +/* #define UX_MAX_SLAVE_CLASS_DRIVER 1 +*/ + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 +*/ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +/* #define UX_MAX_HCD 1 +*/ + + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 +*/ + + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 +*/ + + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constrained environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +*/ + + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constrained environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH (1024 * 2) + + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. +*/ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constrained environments. */ +#define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE (1024 * 8) + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constrained environments. */ + +#define UX_MAX_ED 80 +#define UX_MAX_TD 128 +#define UX_MAX_ISO_TD 1 + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 4096 + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +#define UX_HOST_CLASS_HID_USAGES 2048 + + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + pool availability checking loop. + The default is 100 milliseconds. +*/ + +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_INSTANCE_WAIT 10 */ + +/* Defined, this enables CDC ECM class to use the packet pool from NetX instance. */ + +/* #define UX_HOST_CLASS_CDC_ECM_USE_PACKET_POOL_FROM_NETX */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_MODE (1) */ + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +/* #define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) */ + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this macro disables CDC ACM non-blocking transmission support. */ + +/* #define UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE */ + +/* defined, this macro enables device audio feedback endpoint support. */ + +/* #define UX_DEVICE_CLASS_AUDIO_FEEDBACK_SUPPORT */ + +/* Defined, device HID interrupt OUT transfer is supported. */ + +/* #define UX_DEVICE_CLASS_HID_INTERRUPT_OUT_SUPPORT */ + +/* Defined, this macro enables device bi-directional-endpoint support. */ + +/* #define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT */ + +/* Defined, this macro enables device/host PIMA MTP support. */ + +/* #define UX_PIMA_WITH_MTP_SUPPORT */ + +/* Defined, this macro enables host device class code validation. + Only following USB-IF allowed device class code is allowed: + 0x00, 0x02 (CDC Control), 0x09 (Hub), 0x11 (Billboard), 0xDC (Diagnostic), 0xEF (MISC), 0xFF (Vendor) + Refer to https://www.usb.org/defined-class-codes for more details. + */ + +/* #define UX_HOST_DEVICE_CLASS_CODE_VALIDATION_ENABLE */ + +/* Defined, host HID interrupt OUT transfer is supported. */ + +/* #define UX_HOST_CLASS_HID_INTERRUPT_OUT_SUPPORT */ + +/* Define HID report transfer timeout value in millisecond. + The default is 10000 milliseconds. */ + +/* #define UX_HOST_CLASS_HID_REPORT_TRANSFER_TIMEOUT 10000 */ + +/* Defined, this value will only enable the host side of usbx. */ +/* #define UX_HOST_SIDE_ONLY */ + +/* Defined, this value will only enable the device side of usbx. */ +/* #define UX_DEVICE_SIDE_ONLY */ + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +/* #define UX_OTG_SUPPORT */ + +#endif +#endif + +/* Defined, this macro will enable the standalone mode of usbx. */ +/* #define UX_STANDALONE */ + +/* Defined, this macro will remove the FileX dependency of host storage. + In this mode, sector access is offered instead of directly FileX FX_MEDIA support. + Use following APIs for media obtain and access: + - ux_host_class_storage_media_get : get instance of UX_HOST_CLASS_STORAGE_MEDIA + - ux_host_class_storage_media_lock : lock specific media for further read/write + - ux_host_class_storage_media_read : read sectors on locked media + - ux_host_class_storage_media_write : write sectors on locked media + - ux_host_class_storage_media_unlock : unlock media + Note it's forced defined/enabled in standalone mode of usbx. +*/ +/* #define UX_HOST_CLASS_STORAGE_NO_FILEX */ + +/* Defined, this value represents the maximum size of single transfers for the SCSI data phase. + By default it's 1024. +*/ + +#define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) + +/* Defined, this value represents the size of the log pool. +*/ +#define UX_DEBUG_LOG_SIZE (1024 * 16) + +/* Defined, this macro represents the non-blocking function to return time tick. + This macro is used only in standalone mode. + The tick rate is defined by UX_PERIODIC_RATE. + If it's not defined, or TX is not included, a external function must be + implement in application: + extern ULONG _ux_utility_time_get(VOID); +*/ +/* #define _ux_utility_time_get() tx_time_get() */ + +/* Defined, this macro represents the non-blocking function to disable interrupts + and return old interrupt setting flags. + If it's not defined, or TX is not included, a external function must be + implement in application: + extern ALIGN_TYPE _ux_utility_interrupt_disable(VOID); +*/ +/* #define _ux_utility_interrupt_disable() _tx_thread_interrupt_disable() */ + +/* Defined, this macro represents the non-blocking function to restore interrupts. + If it's not defined, or TX is not included, a external function must be + implement in application: + extern VOID _ux_utility_interrupt_restore(ALIGN_TYPE); +*/ +/* #define _ux_utility_interrupt_restore(flags) _tx_thread_interrupt_restore(flags) */ + +/* Defined, this enables the assert checks inside usbx. */ +#define UX_ENABLE_ASSERT + +/* Defined, this defines the assert action taken when failure detected. By default + it halts without any output. */ +/* #define UX_ASSERT_FAIL for (;;) {tx_thread_sleep(UX_WAIT_FOREVER); } */ + + +/* DEBUG includes and macros for a specific platform go here. */ +#ifdef UX_INCLUDE_USER_DEFINE_BSP +#include "usb_bsp.h" +#include "usbh_hcs.h" +#include "usbh_stdreq.h" +#include "usbh_core.h" +#endif + +#endif + diff --git a/src/Middlewares/ST/usbx/common/core/inc/ux_utility.h b/src/Middlewares/ST/usbx/common/core/inc/ux_utility.h new file mode 100644 index 00000000..f97fcd52 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/inc/ux_utility.h @@ -0,0 +1,416 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_utility.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX components that utilize utility functions. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* added timer delete, used UX */ +/* prefix to refer to TX */ +/* symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_UTILITY_H +#define UX_UTILITY_H + + +/* Define Utility component function prototypes. */ + +VOID _ux_utility_descriptor_parse(UCHAR * raw_descriptor, UCHAR * descriptor_structure, + UINT descriptor_entries, UCHAR * descriptor); +VOID _ux_utility_descriptor_pack(UCHAR * descriptor, UCHAR * descriptor_structure, + UINT descriptor_entries, UCHAR * raw_descriptor); +ULONG _ux_utility_long_get(UCHAR * address); +VOID _ux_utility_long_put(UCHAR * address, ULONG value); +VOID _ux_utility_long_put_big_endian(UCHAR * address, ULONG value); +ULONG _ux_utility_long_get_big_endian(UCHAR * address); +VOID *_ux_utility_memory_allocate(ULONG memory_alignment,ULONG memory_cache_flag, ULONG memory_size_requested); +UINT _ux_utility_memory_compare(VOID *memory_source, VOID *memory_destination, ULONG length); +VOID _ux_utility_memory_copy(VOID *memory_destination, VOID *memory_source, ULONG length); +VOID _ux_utility_memory_free(VOID *memory); +ULONG _ux_utility_string_length_get(UCHAR *string); +UINT _ux_utility_string_length_check(UCHAR *input_string, UINT *string_length_ptr, UINT max_string_length); +UX_MEMORY_BLOCK *_ux_utility_memory_free_block_best_get(ULONG memory_cache_flag, ULONG memory_size_requested); +VOID _ux_utility_memory_set(VOID *destination, UCHAR value, ULONG length); +ULONG _ux_utility_pci_class_scan(ULONG pci_class, ULONG bus_number, ULONG device_number, + ULONG function_number, ULONG *current_bus_number, + ULONG *current_device_number, ULONG *current_function_number); +ULONG _ux_utility_pci_read(ULONG bus_number, ULONG device_number, ULONG function_number, + ULONG offset, UINT read_size); +VOID _ux_utility_pci_write(ULONG bus_number, ULONG device_number, ULONG function_number, + ULONG offset, ULONG value, UINT write_size); +VOID *_ux_utility_physical_address(VOID *virtual_address); +VOID _ux_utility_set_interrupt_handler(UINT irq, VOID (*interrupt_handler)(VOID)); +ULONG _ux_utility_short_get(UCHAR * address); +ULONG _ux_utility_short_get_big_endian(UCHAR * address); +VOID _ux_utility_short_put(UCHAR * address, USHORT value); +VOID _ux_utility_short_put_big_endian(UCHAR * address, USHORT value); +VOID *_ux_utility_virtual_address(VOID *physical_address); +VOID _ux_utility_unicode_to_string(UCHAR *source, UCHAR *destination); +VOID _ux_utility_string_to_unicode(UCHAR *source, UCHAR *destination); +VOID _ux_utility_debug_callback_register(VOID (*debug_callback)(UCHAR *, ULONG)); +VOID _ux_utility_delay_ms(ULONG ms_wait); + +#if !defined(UX_STANDALONE) +UINT _ux_utility_mutex_create(UX_MUTEX *mutex, CHAR *mutex_name); +UINT _ux_utility_mutex_delete(UX_MUTEX *mutex); +VOID _ux_utility_mutex_off(UX_MUTEX *mutex); +VOID _ux_utility_mutex_on(UX_MUTEX *mutex); +UINT _ux_utility_semaphore_create(UX_SEMAPHORE *semaphore, CHAR *semaphore_name, UINT initial_count); +UINT _ux_utility_semaphore_delete(UX_SEMAPHORE *semaphore); +UINT _ux_utility_semaphore_get(UX_SEMAPHORE *semaphore, ULONG semaphore_signal); +UINT _ux_utility_semaphore_put(UX_SEMAPHORE *semaphore); +UINT _ux_utility_thread_create(UX_THREAD *thread_ptr, CHAR *name, + VOID (*entry_function)(ULONG), ULONG entry_input, + VOID *stack_start, ULONG stack_size, + UINT priority, UINT preempt_threshold, + ULONG time_slice, UINT auto_start); +UINT _ux_utility_thread_delete(UX_THREAD *thread_ptr); +VOID _ux_utility_thread_relinquish(VOID); +UINT _ux_utility_thread_schedule_other(UINT caller_priority); +UINT _ux_utility_thread_resume(UX_THREAD *thread_ptr); +UINT _ux_utility_thread_sleep(ULONG ticks); +UINT _ux_utility_thread_suspend(UX_THREAD *thread_ptr); +UX_THREAD *_ux_utility_thread_identify(VOID); +UINT _ux_utility_timer_create(UX_TIMER *timer, CHAR *timer_name, VOID (*expiration_function) (ULONG), + ULONG expiration_input, ULONG initial_ticks, ULONG reschedule_ticks, + UINT activation_flag); +UINT _ux_utility_timer_delete(UX_TIMER *timer); +UINT _ux_utility_event_flags_create(UX_EVENT_FLAGS_GROUP*group_ptr, CHAR *name); +UINT _ux_utility_event_flags_delete(UX_EVENT_FLAGS_GROUP*group_ptr); +UINT _ux_utility_event_flags_get(UX_EVENT_FLAGS_GROUP*group_ptr, ULONG requested_flags, + UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option); +UINT _ux_utility_event_flags_set(UX_EVENT_FLAGS_GROUP*group_ptr, ULONG flags_to_set, + UINT set_option); +#endif + +#ifndef _ux_utility_interrupt_disable +#ifdef TX_API_H +#define _ux_utility_interrupt_disable() _tx_thread_interrupt_disable() +#else +extern ALIGN_TYPE _ux_utility_interrupt_disable(VOID); +#endif +#else +extern ALIGN_TYPE _ux_utility_interrupt_disable(VOID); +#endif + +#ifndef _ux_utility_interrupt_restore +#ifdef TX_API_H +#define _ux_utility_interrupt_restore(flags) _tx_thread_interrupt_restore(flags) +#else +extern VOID _ux_utility_interrupt_restore(ALIGN_TYPE); +#endif +#else +extern VOID _ux_utility_interrupt_restore(ALIGN_TYPE); +#endif + +#ifndef _ux_utility_time_get +#ifdef TX_API_H +#define _ux_utility_time_get() tx_time_get() +#else +extern ULONG _ux_utility_time_get(VOID); +#endif +#else +extern ULONG _ux_utility_time_get(VOID); +#endif + +#ifndef _ux_utility_time_elapsed +#define _ux_utility_time_elapsed(a,b) (((b)>=(a)) ? ((b)-(a)) : (0xFFFFFFFFul-(b)+(a)+1)) +#else +extern ALIGN_TYPE _ux_utility_time_elapsed(ALIGN_TYPE, ALIGN_TYPE); +#endif + +#if !defined(UX_STANDALONE) +#define _ux_system_semaphore_create _ux_utility_semaphore_create +#define _ux_system_semaphore_create_rc _ux_utility_semaphore_create +#define _ux_system_semaphore_delete _ux_utility_semaphore_delete +#define _ux_system_thread_create_rc _ux_utility_thread_create +#define _ux_system_mutex_create _ux_utility_mutex_create +#define _ux_system_mutex_delete _ux_utility_mutex_delete +#define _ux_system_mutex_off _ux_utility_mutex_off +#define _ux_system_mutex_on _ux_utility_mutex_on +#else +#define _ux_system_semaphore_create(sem,name,cnt) do{}while(0) +#define _ux_system_semaphore_create_rc(sem,name,cnt) (UX_SUCCESS) +#define _ux_system_semaphore_delete _ux_utility_semaphore_delete +#define _ux_system_thread_create_rc(t,name,entry,entry_param,stack,stack_size,priority,preempt_threshold,time_slice,auto_start) (UX_SUCCESS) +#define _ux_system_mutex_create(mutex,name) do{}while(0) +#define _ux_system_mutex_delete(mutex) do{}while(0) +#define _ux_system_mutex_off(mutex) do{}while(0) +#define _ux_system_mutex_on(mutex) do{}while(0) +#endif + +#if !defined(UX_DEVICE_STANDALONE) +#define _ux_device_thread_create _ux_utility_thread_create +#define _ux_device_thread_delete _ux_utility_thread_delete +#define _ux_device_thread_suspend _ux_utility_thread_suspend +#define _ux_device_thread_resume _ux_utility_thread_resume +#define _ux_device_thread_relinquish _ux_utility_thread_relinquish +#define _ux_device_semaphore_create _ux_utility_semaphore_create +#define _ux_device_semaphore_created(sem) ((sem)->tx_semaphore_id != 0) +#define _ux_device_semaphore_waiting(sem) ((sem)->tx_semaphore_count != 0) +#define _ux_device_semaphore_delete _ux_utility_semaphore_delete +#define _ux_device_semaphore_get _ux_utility_semaphore_get +#define _ux_device_semaphore_put _ux_utility_semaphore_put +#define _ux_device_mutex_create _ux_utility_mutex_create +#define _ux_device_mutex_delete _ux_utility_mutex_delete +#define _ux_device_mutex_off _ux_utility_mutex_off +#define _ux_device_mutex_on _ux_utility_mutex_on +#define _ux_device_event_flags_create _ux_utility_event_flags_create +#define _ux_device_event_flags_delete _ux_utility_event_flags_delete +#define _ux_device_event_flags_get _ux_utility_event_flags_get +#define _ux_device_event_flags_set _ux_utility_event_flags_set +#else +#define _ux_device_thread_create(t,name,entry,entry_param,stack,stack_size,priority,preempt_threshold,time_slice,auto_start) (UX_SUCCESS) +#define _ux_device_thread_delete(t) do{}while(0) +#define _ux_device_thread_suspend(t) do{}while(0) +#define _ux_device_thread_resume(t) do{}while(0) +#define _ux_device_thread_relinquish(t) do{}while(0) +#define _ux_device_semaphore_create(sem,name,cnt) (UX_SUCCESS) +#define _ux_device_semaphore_created(sem) (UX_FALSE) +#define _ux_device_semaphore_waiting(sem) (UX_FALSE) +#define _ux_device_semaphore_delete(sem) do{}while(0) +#define _ux_device_semaphore_get(sem,t) (UX_SUCCESS) +#define _ux_device_semaphore_put(sem) do{}while(0) +#define _ux_device_mutex_create(mutex,name) do{}while(0) +#define _ux_device_mutex_delete(mutex) do{}while(0) +#define _ux_device_mutex_off(mutex) do{}while(0) +#define _ux_device_mutex_on(mutex) do{}while(0) +#define _ux_device_event_flags_create(g,name) do{}while(0) +#define _ux_device_event_flags_delete(g) do{}while(0) +#define _ux_device_event_flags_get(g,req,gopt,actual,wopt) do{}while(0) +#define _ux_device_event_flags_set(g,flags,option) do{}while(0) +#endif + + +#if !defined(UX_HOST_STANDALONE) +#define _ux_host_thread_create _ux_utility_thread_create +#define _ux_host_thread_created(thr) ((thr)->tx_thread_id != 0) +#define _ux_host_thread_delete _ux_utility_thread_delete +#define _ux_host_thread_resume _ux_utility_thread_resume +#define _ux_host_thread_sleep _ux_utility_thread_sleep +#define _ux_host_thread_schedule_other _ux_utility_thread_schedule_other +#define _ux_host_semaphore_create _ux_utility_semaphore_create +#define _ux_host_semaphore_created(sem) ((sem)->tx_semaphore_id != 0) +#define _ux_host_semaphore_waiting(sem) ((sem)->tx_semaphore_count != 0) +#define _ux_host_semaphore_delete _ux_utility_semaphore_delete +#define _ux_host_semaphore_get _ux_utility_semaphore_get +#define _ux_host_semaphore_get_norc _ux_utility_semaphore_get +#define _ux_host_semaphore_put _ux_utility_semaphore_put +#define _ux_host_semaphore_put_rc _ux_utility_semaphore_put +#define _ux_host_mutex_create _ux_utility_mutex_create +#define _ux_host_mutex_delete _ux_utility_mutex_delete +#define _ux_host_mutex_off _ux_utility_mutex_off +#define _ux_host_mutex_on _ux_utility_mutex_on +#define _ux_host_event_flags_create _ux_utility_event_flags_create +#define _ux_host_event_flags_delete _ux_utility_event_flags_delete +#define _ux_host_event_flags_get _ux_utility_event_flags_get +#define _ux_host_event_flags_set _ux_utility_event_flags_set +#define _ux_host_timer_create _ux_utility_timer_create +#define _ux_host_timer_delete _ux_utility_timer_delete +#else +#define _ux_host_thread_create(t,name,entry,entry_param,stack,stack_size,priority,preempt_threshold,time_slice,auto_start) (UX_SUCCESS) +#define _ux_host_thread_created(t) (UX_FALSE) +#define _ux_host_thread_delete(t) do{}while(0) +#define _ux_host_thread_resume(t) do{}while(0) +#define _ux_host_thread_sleep(t) do{}while(0) +#define _ux_host_thread_schedule_other(t) do{}while(0) +#define _ux_host_semaphore_create(sem,name,cnt) (UX_SUCCESS) +#define _ux_host_semaphore_created(sem) (UX_FALSE) +#define _ux_host_semaphore_waiting(sem) (UX_FALSE) +#define _ux_host_semaphore_delete(sem) do{}while(0) +#define _ux_host_semaphore_get(sem,t) (UX_SUCCESS) +#define _ux_host_semaphore_get_norc(sem,t) do{}while(0) +#define _ux_host_semaphore_put(sem) do{}while(0) +#define _ux_host_semaphore_put_rc(sem) (UX_SUCCESS) +#define _ux_host_mutex_create(mutex,name) do{}while(0) +#define _ux_host_mutex_delete(mutex) do{}while(0) +#define _ux_host_mutex_off(mutex) do{}while(0) +#define _ux_host_mutex_on(mutex) do{}while(0) +#define _ux_host_event_flags_create(g,name) do{}while(0) +#define _ux_host_event_flags_delete(g) do{}while(0) +#define _ux_host_event_flags_get(g,req,gopt,actual,wopt) do{}while(0) +#define _ux_host_event_flags_set(g,flags,option) do{}while(0) +#define _ux_host_timer_create(t,name,func,arg,tick0,tick1,flag) (UX_SUCCESS) +#define _ux_host_timer_delete(t) do{}while(0) +#endif + + +#ifdef UX_DISABLE_ERROR_HANDLER +#define _ux_system_error_handler(system_level, system_context, error_code) do {} while(0) +#define _ux_utility_error_callback_register(error_callback) do {} while(0) +#else +VOID _ux_system_error_handler(UINT system_level, UINT system_context, UINT error_code); +VOID _ux_utility_error_callback_register(VOID (*error_callback)(UINT system_level, UINT system_context, UINT error_code)); +#endif + +#define UX_UTILITY_ADD_SAFE(add_a, add_b, result, status) do { \ + if (UX_OVERFLOW_CHECK_ADD_ULONG(add_a, add_b)) \ + status = UX_ERROR; \ + else \ + result = (add_a) + (add_b); \ + } while(0) + +#define UX_UTILITY_MULC_SAFE(mul_v, mul_c, result, status) do { \ + if (UX_OVERFLOW_CHECK_MULC_ULONG(mul_v, mul_c)) \ + status = UX_ERROR; \ + else \ + result = (mul_v) * (mul_c); \ + } while(0) + +#define UX_UTILITY_MULV_SAFE(mul_v0, mul_v1, result, status) do { \ + if (UX_OVERFLOW_CHECK_MULC_ULONG(mul_v0, mul_v1)) \ + status = UX_ERROR; \ + else \ + result = (mul_v0) * (mul_v1); \ + } while(0) + +#define UX_UTILITY_MEMORY_ALLOCATE_MULC_SAFE(align,cache,size_mul_v,size_mul_c) \ + (UX_OVERFLOW_CHECK_MULC_ULONG(size_mul_v, size_mul_c) ? UX_NULL : _ux_utility_memory_allocate((align), (cache), (size_mul_v)*(size_mul_c))) +#define UX_UTILITY_MEMORY_ALLOCATE_MULV_SAFE(align,cache,size_mul_v0,size_mul_v1) \ + (UX_OVERFLOW_CHECK_MULV_ULONG(size_mul_v0, size_mul_v1) ? UX_NULL : _ux_utility_memory_allocate((align), (cache), (size_mul_v0)*(size_mul_v1))) +#define UX_UTILITY_MEMORY_ALLOCATE_ADD_SAFE(align,cache,size_add_a,size_add_b) \ + (UX_OVERFLOW_CHECK_ADD_ULONG(size_add_a, size_add_b) ? UX_NULL : _ux_utility_memory_allocate((align), (cache), (size_add_a)+(size_add_b))) + +#ifdef UX_DISABLE_ARITHMETIC_CHECK + +/* No arithmetic check, calculate directly. */ + +#define _ux_utility_memory_allocate_mulc_safe(align,cache,size_mul_v,size_mul_c) _ux_utility_memory_allocate((align), (cache), (size_mul_v)*(size_mul_c)) +#define _ux_utility_memory_allocate_mulv_safe(align,cache,size_mul_v0,size_mul_v1) _ux_utility_memory_allocate((align), (cache), (size_mul_v0)*(size_mul_v1)) +#define _ux_utility_memory_allocate_add_safe(align,cache,size_add_a,size_add_b) _ux_utility_memory_allocate((align), (cache), (size_add_a)+(size_add_b)) + +#else /* UX_DISABLE_ARITHMETIC_CHECK */ + +#ifdef UX_ENABLE_MEMORY_ARITHMETIC_OPTIMIZE + +/* Uses macro to enable code optimization on compiling. */ + +#define _ux_utility_memory_allocate_mulc_safe(align,cache,size_mul_v,size_mul_c) UX_UTILITY_MEMORY_ALLOCATE_MULC_SAFE(align,cache,size_mul_v,size_mul_c) +#define _ux_utility_memory_allocate_mulv_safe(align,cache,size_mul_v0,size_mul_v1) UX_UTILITY_MEMORY_ALLOCATE_MULV_SAFE(align,cache,size_mul_v0,size_mul_v1) +#define _ux_utility_memory_allocate_add_safe(align,cache,size_add_a,size_add_b) UX_UTILITY_MEMORY_ALLOCATE_ADD_SAFE(align,cache,size_add_a,size_add_b) + +#else /* UX_ENABLE_MEMORY_ARITHMETIC_OPTIMIZE */ + +/* Uses functions to be most flexible. */ + +VOID* _ux_utility_memory_allocate_mulc_safe(ULONG align,ULONG cache,ULONG size_mul_v,ULONG size_mul_c); +VOID* _ux_utility_memory_allocate_mulv_safe(ULONG align,ULONG cache,ULONG size_mul_v0,ULONG size_mul_v1); +VOID* _ux_utility_memory_allocate_add_safe(ULONG align,ULONG cache,ULONG size_add_a,ULONG size_add_b); + +#endif /* UX_ENABLE_MEMORY_ARITHMETIC_OPTIMIZE */ + +#endif /* UX_DISABLE_ARITHMETIC_CHECK */ + + +#if defined(UX_NAME_REFERENCED_BY_POINTER) +#define ux_utility_name_match(n0,n1,l) ((n0) == (n1)) +#else +#define ux_utility_name_match(n0,n1,l) (_ux_utility_memory_compare(n0,n1,l) == UX_SUCCESS) +#endif + + +/* Define the system API mappings. + Note: this section is only applicable to + application source code, hence the conditional that turns off this + stuff when the include file is processed by the ThreadX source. */ + +#ifndef UX_SOURCE_CODE + + +#define ux_utility_descriptor_parse _ux_utility_descriptor_parse +#define ux_utility_descriptor_pack _ux_utility_descriptor_pack +#define ux_utility_long_get _ux_utility_long_get +#define ux_utility_long_put _ux_utility_long_put +#define ux_utility_long_put_big_endian _ux_utility_long_put_big_endian +#define ux_utility_long_get_big_endian _ux_utility_long_get_big_endian +#define ux_utility_memory_allocate _ux_utility_memory_allocate +#define ux_utility_memory_compare _ux_utility_memory_compare +#define ux_utility_memory_copy _ux_utility_memory_copy +#define ux_utility_memory_free _ux_utility_memory_free +#define ux_utility_string_length_get _ux_utility_string_length_get +#define ux_utility_string_length_check _ux_utility_string_length_check +#define ux_utility_memory_set _ux_utility_memory_set +#define ux_utility_mutex_create _ux_utility_mutex_create +#define ux_utility_mutex_delete _ux_utility_mutex_delete +#define ux_utility_mutex_off _ux_utility_mutex_off +#define ux_utility_mutex_on _ux_utility_mutex_on +#define ux_utility_pci_class_scan _ux_utility_pci_class_scan +#define ux_utility_pci_read _ux_utility_pci_read +#define ux_utility_pci_write _ux_utility_pci_write +#define ux_utility_physical_address _ux_utility_physical_address +#define ux_utility_semaphore_create _ux_utility_semaphore_create +#define ux_utility_semaphore_delete _ux_utility_semaphore_delete +#define ux_utility_semaphore_get _ux_utility_semaphore_get +#define ux_utility_semaphore_put _ux_utility_semaphore_put +#define ux_utility_set_interrupt_handler _ux_utility_set_interrupt_handler +#define ux_utility_short_get _ux_utility_short_get +#define ux_utility_short_get_big_endian _ux_utility_short_get_big_endian +#define ux_utility_short_put _ux_utility_short_put +#define ux_utility_short_put_big_endian _ux_utility_short_put_big_endian +#define ux_utility_thread_create _ux_utility_thread_create +#define ux_utility_thread_delete _ux_utility_thread_delete +#define ux_utility_thread_relinquish _ux_utility_thread_relinquish +#define ux_utility_thread_resume _ux_utility_thread_resume +#define ux_utility_thread_sleep _ux_utility_thread_sleep +#define ux_utility_thread_suspend _ux_utility_thread_suspend +#define ux_utility_thread_identify _ux_utility_thread_identify +#define ux_utility_timer_create _ux_utility_timer_create +#define ux_utility_event_flags_create _ux_utility_event_flags_create +#define ux_utility_event_flags_delete _ux_utility_event_flags_delete +#define ux_utility_event_flags_get _ux_utility_event_flags_get +#define ux_utility_event_flags_set _ux_utility_event_flags_set +#define ux_utility_unicode_to_string _ux_utility_unicode_to_string +#define ux_utility_string_to_unicode _ux_utility_string_to_unicode +#define ux_utility_delay_ms _ux_utility_delay_ms +#define ux_utility_error_callback_register _ux_utility_error_callback_register +#define ux_system_error_handler _ux_system_error_handler + +#define ux_utility_time_get _ux_utility_time_get +#define ux_utility_time_elapsed _ux_utility_time_elapsed +#endif + +#endif diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_alternate_setting_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_alternate_setting_get.c new file mode 100644 index 00000000..047a0e22 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_alternate_setting_get.c @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_alternate_setting_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the alternate setting for a specific interface. */ +/* */ +/* INPUT */ +/* */ +/* endpoint Pointer to endpoint */ +/* interface_value Interface value */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Process transfer request */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_alternate_setting_get(ULONG interface_value) +{ + +UX_SLAVE_TRANSFER *transfer_request; +UX_SLAVE_INTERFACE *interface; +UX_SLAVE_DEVICE *device; +UX_SLAVE_ENDPOINT *endpoint; +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_ALTERNATE_SETTING_GET, interface_value, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* If the device was in the configured state, there may be interfaces + attached to the configuration. */ + if (device -> ux_slave_device_state == UX_DEVICE_CONFIGURED) + { + + /* Obtain the pointer to the first interface attached. */ + interface = device -> ux_slave_device_first_interface; + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Start parsing each interface. */ + while (interface != UX_NULL) +#else + if (interface != UX_NULL) +#endif + { + + /* Check if this is the interface we have an inquiry for. */ + if (interface -> ux_slave_interface_descriptor.bInterfaceNumber == interface_value) + { + + /* Get the control endpoint of the device. */ + endpoint = &device -> ux_slave_device_control_endpoint; + + /* Get the pointer to the transfer request associated with the endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Set the value of the alternate setting in the buffer. */ + *transfer_request -> ux_slave_transfer_request_data_pointer = + (UCHAR) interface -> ux_slave_interface_descriptor.bAlternateSetting; + + /* Setup the length appropriately. */ + transfer_request -> ux_slave_transfer_request_requested_length = 1; + + /* Set the phase of the transfer to data out. */ + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT; + + /* Send the descriptor with the appropriate length to the host. */ + status = _ux_device_stack_transfer_request(transfer_request, 1, 1); + + /* Return the function status. */ + return(status); + } + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Get the next interface. */ + interface = interface -> ux_slave_interface_next_interface; +#endif + } + } + + /* Return error completion. */ + return(UX_ERROR); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_alternate_setting_set.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_alternate_setting_set.c new file mode 100644 index 00000000..c177074f --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_alternate_setting_set.c @@ -0,0 +1,460 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_alternate_setting_set PORTABLE C */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the alternate setting for a specific interface. */ +/* The previous interface is unmounted and all the endpoints */ +/* associated with the alternate setting are mounted. */ +/* */ +/* INPUT */ +/* */ +/* endpoint Pointer to endpoint */ +/* interface_value Interface value */ +/* alternate_setting_value Alternate setting value */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* _ux_utility_descriptor_parse Parse descriptor */ +/* _ux_device_stack_transfer_all_request_abort */ +/* Abort transfer */ +/* _ux_utility_memory_copy Copy memory */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, verified */ +/* memset and memcpy cases, */ +/* resulting in version 6.1 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* calculated payload size, */ +/* resulting in version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_alternate_setting_set(ULONG interface_value, ULONG alternate_setting_value) +{ + +UX_SLAVE_DEVICE *device; +UX_SLAVE_INTERFACE *interface; +#if !defined(UX_DEVICE_ALTERNATE_SETTING_SUPPORT_DISABLE) +UX_SLAVE_DCD *dcd; +UX_SLAVE_TRANSFER *transfer_request; +UCHAR *device_framework; +ULONG device_framework_length; +ULONG descriptor_length; +UCHAR descriptor_type; +UX_CONFIGURATION_DESCRIPTOR configuration_descriptor; +UX_INTERFACE_DESCRIPTOR interface_descriptor; +UX_SLAVE_ENDPOINT *endpoint; +UX_SLAVE_ENDPOINT *next_endpoint; +UX_SLAVE_ENDPOINT *endpoint_link; +ULONG endpoints_pool_number; +UX_SLAVE_CLASS_COMMAND class_command; +UX_SLAVE_CLASS *class; +UINT status; +ULONG max_transfer_length, n_trans; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_ALTERNATE_SETTING_SET, interface_value, alternate_setting_value, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Protocol error must be reported when it's unconfigured */ + if (device -> ux_slave_device_state != UX_DEVICE_CONFIGURED) + return(UX_FUNCTION_NOT_SUPPORTED); + + /* Find the current interface. */ + interface = device -> ux_slave_device_first_interface; + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Scan all interfaces if any. */ + while (interface != UX_NULL) + { + + if (interface -> ux_slave_interface_descriptor.bInterfaceNumber == interface_value) + break; + else + interface = interface -> ux_slave_interface_next_interface; + } +#else + if (interface -> ux_slave_interface_descriptor.bInterfaceNumber != interface_value) + interface = UX_NULL; +#endif + + /* We must have found the interface pointer for the interface value + requested by the caller. */ + if (interface == UX_NULL) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_CLASS, UX_INTERFACE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_INTERFACE_HANDLE_UNKNOWN, interface, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_INTERFACE_HANDLE_UNKNOWN); + } + + /* If the host is requesting a change of alternate setting to the current one, + we do not need to do any work. */ + if (interface -> ux_slave_interface_descriptor.bAlternateSetting == alternate_setting_value) + return(UX_SUCCESS); + +#if defined(UX_DEVICE_ALTERNATE_SETTING_SUPPORT_DISABLE) + + /* If alternate setting is disabled, do error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_CLASS, UX_FUNCTION_NOT_SUPPORTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_FUNCTION_NOT_SUPPORTED, interface, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_FUNCTION_NOT_SUPPORTED); +#else + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave->ux_system_slave_dcd; + + /* We may have multiple configurations! */ + device_framework = _ux_system_slave -> ux_system_slave_device_framework; + device_framework_length = _ux_system_slave -> ux_system_slave_device_framework_length; + + /* Parse the device framework and locate a configuration descriptor. */ + while (device_framework_length != 0) + { + + /* Get the length of the current descriptor. */ + descriptor_length = (ULONG) *device_framework; + + /* And its length. */ + descriptor_type =* (device_framework + 1); + + /* Check if this is a configuration descriptor. */ + if (descriptor_type == UX_CONFIGURATION_DESCRIPTOR_ITEM) + { + + /* Parse the descriptor in something more readable. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_configuration_descriptor_structure, + UX_CONFIGURATION_DESCRIPTOR_ENTRIES, + (UCHAR *) &configuration_descriptor); + + /* Now we need to check the configuration value. */ + if (configuration_descriptor.bConfigurationValue == device -> ux_slave_device_configuration_selected) + { + + /* Limit the search in current configuration descriptor. */ + device_framework_length = configuration_descriptor.wTotalLength; + + /* We have found the configuration value that was selected by the host + We need to scan all the interface descriptors following this + configuration descriptor and locate the interface for which the alternate + setting must be changed. */ + while (device_framework_length != 0) + { + + /* Get the length of the current descriptor. */ + descriptor_length = (ULONG) *device_framework; + + /* And its type. */ + descriptor_type = *(device_framework + 1); + + /* Check if this is an interface descriptor. */ + if (descriptor_type == UX_INTERFACE_DESCRIPTOR_ITEM) + { + + /* Parse the descriptor in something more readable. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_interface_descriptor_structure, + UX_INTERFACE_DESCRIPTOR_ENTRIES, + (UCHAR *) &interface_descriptor); + + /* Check if this is the interface we are searching. */ + if (interface_descriptor.bInterfaceNumber == interface_value && + interface_descriptor.bAlternateSetting == alternate_setting_value) + { + + /* We have found the right interface and alternate setting. Before + we mount all the endpoints for this interface, we need to + unmount the endpoints associated with the previous alternate setting. */ + endpoint = interface -> ux_slave_interface_first_endpoint; + while (endpoint != UX_NULL) + { + + /* Abort any pending transfer. */ + _ux_device_stack_transfer_all_request_abort(endpoint, UX_TRANSFER_BUS_RESET); + + /* The device controller must be called to destroy the endpoint. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_DESTROY_ENDPOINT, (VOID *) endpoint); + + /* Get the next endpoint. */ + next_endpoint = endpoint -> ux_slave_endpoint_next_endpoint; + + /* Free the endpoint. */ + endpoint -> ux_slave_endpoint_status = UX_UNUSED; + + /* Make sure the endpoint instance is now cleaned up. */ + endpoint -> ux_slave_endpoint_state = 0; + endpoint -> ux_slave_endpoint_next_endpoint = UX_NULL; + endpoint -> ux_slave_endpoint_interface = UX_NULL; + endpoint -> ux_slave_endpoint_device = UX_NULL; + + /* Now we refresh the endpoint pointer. */ + endpoint = next_endpoint; + } + + /* Now clear the interface endpoint entry. */ + interface -> ux_slave_interface_first_endpoint = UX_NULL; + + /* Point beyond the interface descriptor. */ + device_framework_length -= (ULONG) *device_framework; + device_framework += (ULONG) *device_framework; + + /* Parse the device framework and locate endpoint descriptor(s). */ + while (device_framework_length != 0) + { + + /* Get the length of the current descriptor. */ + descriptor_length = (ULONG) *device_framework; + + /* And its type. */ + descriptor_type = *(device_framework + 1); + + /* Check if this is an endpoint descriptor. */ + switch(descriptor_type) + { + + case UX_ENDPOINT_DESCRIPTOR_ITEM: + + /* Find a free endpoint in the pool and hook it to the + existing interface after it's created by DCD. */ + endpoint = device -> ux_slave_device_endpoints_pool; + endpoints_pool_number = device -> ux_slave_device_endpoints_pool_number; + while (endpoints_pool_number != 0) + { + /* Check if this endpoint is free. */ + if (endpoint -> ux_slave_endpoint_status == UX_UNUSED) + { + /* Mark this endpoint as used now. */ + endpoint -> ux_slave_endpoint_status = UX_USED; + break; + } + + /* Try the next endpoint. */ + endpoint++; + + /* Decrement the number of endpoints to scan from the pool. */ + endpoints_pool_number--; + } + + /* Did we find a free endpoint ? */ + if (endpoints_pool_number == 0) + return(UX_MEMORY_INSUFFICIENT); + + /* Parse the descriptor in something more readable. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_endpoint_descriptor_structure, + UX_ENDPOINT_DESCRIPTOR_ENTRIES, + (UCHAR *) &endpoint -> ux_slave_endpoint_descriptor); + + /* Now we create a transfer request to accept transfer on this endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Validate descriptor wMaxPacketSize. */ + UX_ASSERT(endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize != 0); + + /* Calculate endpoint transfer payload max size. */ + max_transfer_length = + endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize & + UX_MAX_PACKET_SIZE_MASK; + if ((_ux_system_slave -> ux_system_slave_speed == UX_HIGH_SPEED_DEVICE) && + (endpoint -> ux_slave_endpoint_descriptor.bmAttributes & 0x1u)) + { + n_trans = endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize & + UX_MAX_NUMBER_OF_TRANSACTIONS_MASK; + if (n_trans) + { + n_trans >>= UX_MAX_NUMBER_OF_TRANSACTIONS_SHIFT; + n_trans ++; + max_transfer_length *= n_trans; + } + } + + /* Validate max transfer size and save it. */ + UX_ASSERT(max_transfer_length <= UX_SLAVE_REQUEST_DATA_MAX_LENGTH); + transfer_request -> ux_slave_transfer_request_transfer_length = max_transfer_length; + + /* We store the endpoint in the transfer request as well. */ + transfer_request -> ux_slave_transfer_request_endpoint = endpoint; + + /* By default the timeout is infinite on request. */ + transfer_request -> ux_slave_transfer_request_timeout = UX_WAIT_FOREVER; + + /* Attach the interface to the endpoint. */ + endpoint -> ux_slave_endpoint_interface = interface; + + /* Attach the device to the endpoint. */ + endpoint -> ux_slave_endpoint_device = device; + + /* Create the endpoint at the DCD level. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_CREATE_ENDPOINT, (VOID *) endpoint); + + /* Do a sanity check on endpoint creation. */ + if (status != UX_SUCCESS) + { + + /* Error was returned, endpoint cannot be created. */ + endpoint -> ux_slave_endpoint_status = UX_UNUSED; + return(status); + } + + /* Attach this endpoint to the end of the endpoint chain. */ + if (interface -> ux_slave_interface_first_endpoint == UX_NULL) + { + + interface -> ux_slave_interface_first_endpoint = endpoint; + } + else + { + /* Multiple endpoints exist, so find the end of the chain. */ + endpoint_link = interface -> ux_slave_interface_first_endpoint; + while (endpoint_link -> ux_slave_endpoint_next_endpoint != UX_NULL) + endpoint_link = endpoint_link -> ux_slave_endpoint_next_endpoint; + endpoint_link -> ux_slave_endpoint_next_endpoint = endpoint; + } + + break; + + case UX_CONFIGURATION_DESCRIPTOR_ITEM: + case UX_INTERFACE_DESCRIPTOR_ITEM: + + /* We have found a new configuration or interface descriptor, this is the end of the current + interface. The search for the endpoints must be terminated as if it was the end of the + entire descriptor. */ + device_framework_length = descriptor_length; + + break; + + + default: + + /* We have found another descriptor embedded in the interface. Ignore it. */ + break; + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + + /* The interface descriptor in the current class must be changed to the new alternate setting. */ + _ux_utility_memory_copy(&interface -> ux_slave_interface_descriptor, &interface_descriptor, sizeof(UX_INTERFACE_DESCRIPTOR)); /* Use case of memcpy is verified. */ + + /* Get the class for the interface. */ + class = _ux_system_slave -> ux_system_slave_interface_class_array[interface -> ux_slave_interface_descriptor.bInterfaceNumber]; + + /* Check if class driver is available. */ + if (class == UX_NULL || class -> ux_slave_class_status == UX_UNUSED) + { + + return (UX_NO_CLASS_MATCH); + } + + /* The interface attached to this configuration must be changed at the class + level. */ + class_command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_CHANGE; + class_command.ux_slave_class_command_interface = (VOID *) interface; + + /* And store it. */ + class_command.ux_slave_class_command_class_ptr = class; + + /* We can now memorize the interface pointer associated with this class. */ + class -> ux_slave_class_interface = interface; + + /* We have found a potential candidate. Call this registered class entry function to change the alternate setting. */ + status = class -> ux_slave_class_entry_function(&class_command); + + /* We are done here. */ + return(status); + } + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + + /* In case alter setting not found, report protocol error. */ + break; + } + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + + /* Return error completion. */ + return(UX_ERROR); +#endif +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_class_register.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_class_register.c new file mode 100644 index 00000000..340577f7 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_class_register.c @@ -0,0 +1,168 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_class_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a slave class to the slave stack. */ +/* */ +/* Note: The C string of class_name must be NULL-terminated and the */ +/* length of it (without the NULL-terminator itself) must be no larger */ +/* than UX_MAX_CLASS_NAME_LENGTH. */ +/* */ +/* INPUT */ +/* */ +/* class_name Name of class */ +/* class_function_entry Class entry function */ +/* configuration_number Configuration # for this class*/ +/* interface_number Interface # for this class */ +/* parameter Parameter specific for class */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check C string and return */ +/* its length if null-terminated */ +/* _ux_utility_memory_copy Memory copy */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, verified */ +/* memset and memcpy cases, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_class_register(UCHAR *class_name, + UINT (*class_entry_function)(struct UX_SLAVE_CLASS_COMMAND_STRUCT *), + ULONG configuration_number, + ULONG interface_number, + VOID *parameter) +{ + +UX_SLAVE_CLASS *class_inst; +UINT status; +UX_SLAVE_CLASS_COMMAND command; +UINT class_name_length = 0; +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 +ULONG class_index; +#endif + + + /* Get the length of the class name (exclude null-terminator). */ + status = _ux_utility_string_length_check(class_name, &class_name_length, UX_MAX_CLASS_NAME_LENGTH); + if (status) + return(status); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_CLASS_REGISTER, class_name, interface_number, parameter, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get first class. */ + class_inst = _ux_system_slave -> ux_system_slave_class_array; + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* We need to parse the class table to find an empty spot. */ + for (class_index = 0; class_index < _ux_system_slave -> ux_system_slave_max_class; class_index++) + { +#endif + + /* Check if this class is already used. */ + if (class_inst -> ux_slave_class_status == UX_UNUSED) + { + +#if defined(UX_NAME_REFERENCED_BY_POINTER) + class_inst -> ux_slave_class_name = (const UCHAR *)class_name; +#else + /* We have found a free container for the class. Copy the name (with null-terminator). */ + _ux_utility_memory_copy(class_inst -> ux_slave_class_name, class_name, class_name_length + 1); /* Use case of memcpy is verified. */ +#endif + + /* Memorize the entry function of this class. */ + class_inst -> ux_slave_class_entry_function = class_entry_function; + + /* Memorize the pointer to the application parameter. */ + class_inst -> ux_slave_class_interface_parameter = parameter; + + /* Memorize the configuration number on which this instance will be called. */ + class_inst -> ux_slave_class_configuration_number = configuration_number; + + /* Memorize the interface number on which this instance will be called. */ + class_inst -> ux_slave_class_interface_number = interface_number; + + /* Build all the fields of the Class Command to initialize the class. */ + command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_INITIALIZE; + command.ux_slave_class_command_parameter = parameter; + command.ux_slave_class_command_class_ptr = class_inst; + + /* Call the class initialization routine. */ + status = class_entry_function(&command); + + /* Check the status. */ + if (status != UX_SUCCESS) + return(status); + + /* Make this class used now. */ + class_inst -> ux_slave_class_status = UX_USED; + + /* Return successful completion. */ + return(UX_SUCCESS); + } + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* Move to the next class. */ + class_inst ++; + } +#endif + + /* No more entries in the class table. */ + return(UX_MEMORY_INSUFFICIENT); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_class_unregister.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_class_unregister.c new file mode 100644 index 00000000..f9d614e2 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_class_unregister.c @@ -0,0 +1,152 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_class_unregister PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unregisters a slave class to the slave stack. */ +/* */ +/* Note: The C string of class_name must be NULL-terminated and the */ +/* length of it (without the NULL-terminator itself) must be no larger */ +/* than UX_MAX_CLASS_NAME_LENGTH. */ +/* */ +/* INPUT */ +/* */ +/* class_name Name of class */ +/* class_function_entry Class entry function */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check C string and return */ +/* its length if null-terminated */ +/* _ux_utility_memory_compare Memory compare */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_class_unregister(UCHAR *class_name, + UINT (*class_entry_function)(struct UX_SLAVE_CLASS_COMMAND_STRUCT *)) +{ + +UX_SLAVE_CLASS *class_inst; +UINT status; +UX_SLAVE_CLASS_COMMAND command; +#if !defined(UX_NAME_REFERENCED_BY_POINTER) +UINT class_name_length = 0; +#endif +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 +ULONG class_index; +#endif + + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_CLASS_UNREGISTER, class_name, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + +#if !defined(UX_NAME_REFERENCED_BY_POINTER) + /* Get the length of the class name (exclude null-terminator). */ + status = _ux_utility_string_length_check(class_name, &class_name_length, UX_MAX_CLASS_NAME_LENGTH); + if (status) + return(status); +#endif + + class_inst = _ux_system_slave -> ux_system_slave_class_array; + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* We need to parse the class table to find the right class. */ + for (class_index = 0; class_index < _ux_system_slave -> ux_system_slave_max_class; class_index++) + { +#endif + + /* Check if this class is the right one. */ + if (class_inst -> ux_slave_class_status == UX_USED) + { + + /* We have found a used container with a class. Compare the name (include null-terminator). */ + if (ux_utility_name_match(class_inst -> ux_slave_class_name, class_name, class_name_length + 1)) + { + + /* Build all the fields of the Class Command to uninitialize the class. */ + command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_UNINITIALIZE; + command.ux_slave_class_command_class_ptr = class_inst; + + /* Call the class uninitialization routine. */ + status = class_entry_function(&command); + + /* Check the status. */ + if (status != UX_SUCCESS) + return(status); + + /* Make this class unused now. */ + class_inst -> ux_slave_class_status = UX_UNUSED; + + /* Erase the instance of the class. */ + class_inst -> ux_slave_class_instance = UX_NULL; + + /* Return successful completion. */ + return(UX_SUCCESS); + } + } + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* Move to the next class. */ + class_inst ++; + } +#endif + + /* No class match. */ + return(UX_NO_CLASS_MATCH); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_clear_feature.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_clear_feature.c new file mode 100644 index 00000000..dfcb3717 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_clear_feature.c @@ -0,0 +1,184 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_clear_feature PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function clears a specific feature (Device, Interface, */ +/* Endpoint ....). */ +/* */ +/* INPUT */ +/* */ +/* request_type Request type */ +/* request_value Request value */ +/* request_index Request index */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* */ +/* CALLED BY */ +/* */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_clear_feature(ULONG request_type, ULONG request_value, ULONG request_index) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_DEVICE *device; +UX_SLAVE_INTERFACE *interface; +UX_SLAVE_ENDPOINT *endpoint; +UX_SLAVE_ENDPOINT *endpoint_target; + + UX_PARAMETER_NOT_USED(request_value); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_CLEAR_FEATURE, request_type, request_value, request_index, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Get the control endpoint for the device. */ + endpoint = &device -> ux_slave_device_control_endpoint; + + /* The request can be for either the device or the endpoint. */ + switch (request_type & UX_REQUEST_TARGET) + { + + case UX_REQUEST_TARGET_DEVICE: + + /* Check if we have a DEVICE_REMOTE_WAKEUP Feature. */ + if (request_value == UX_REQUEST_FEATURE_DEVICE_REMOTE_WAKEUP) + { + + /* Check if we have the capability. */ + if (_ux_system_slave -> ux_system_slave_remote_wakeup_capability) + { + + /* Disable the feature. */ + _ux_system_slave -> ux_system_slave_remote_wakeup_enabled = UX_FALSE; + } + + else + + /* Protocol error. */ + return (UX_FUNCTION_NOT_SUPPORTED); + } + + break; + + case UX_REQUEST_TARGET_ENDPOINT: + + /* The only clear feature for endpoint is ENDPOINT_STALL. This clears + the endpoint of the stall situation and resets its data toggle. + We need to find the endpoint through the interface(s). */ + interface = device -> ux_slave_device_first_interface; + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + while (interface != UX_NULL) + { +#endif + + /* Get the first endpoint for this interface. */ + endpoint_target = interface -> ux_slave_interface_first_endpoint; + + /* Parse all the endpoints. */ + while (endpoint_target != UX_NULL) + { + + /* Check the endpoint index. */ + if (endpoint_target -> ux_slave_endpoint_descriptor.bEndpointAddress == request_index) + { + + /* Reset the endpoint. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_RESET_ENDPOINT, endpoint_target); + + /* Mark its state now. */ + endpoint_target -> ux_slave_endpoint_state = UX_ENDPOINT_RESET; + + /* Return the function status. */ + return(UX_SUCCESS); + } + + /* Next endpoint. */ + endpoint_target = endpoint_target -> ux_slave_endpoint_next_endpoint; + } + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Next interface. */ + interface = interface -> ux_slave_interface_next_interface; + } +#endif + + /* Intentional fallthrough and go into the default case. */ + /* fall through */ + + /* We get here when the endpoint is wrong. Should not happen though. */ + default: + + /* We stall the command. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + + /* No more work to do here. The command failed but the upper layer does not depend on it. */ + return(UX_SUCCESS); + } + + /* Return the function status. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_configuration_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_configuration_get.c new file mode 100644 index 00000000..84820463 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_configuration_get.c @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_configuration_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets the current configuration for the device. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Transfer request */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_configuration_get(VOID) +{ + +UX_SLAVE_TRANSFER *transfer_request; +UX_SLAVE_DEVICE *device; +UX_SLAVE_ENDPOINT *endpoint; +UINT status; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Get the control endpoint for the device. */ + endpoint = &device -> ux_slave_device_control_endpoint; + + /* Get the pointer to the transfer request associated with the endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Set the value of the configuration in the buffer. */ + *transfer_request -> ux_slave_transfer_request_data_pointer = + (UCHAR) device -> ux_slave_device_configuration_selected; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_CONFIGURATION_GET, device -> ux_slave_device_configuration_selected, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Set the phase of the transfer to data out. */ + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT; + + /* Send the descriptor with the appropriate length to the host. */ + status = _ux_device_stack_transfer_request(transfer_request, 1, 1); + + /* Return the function status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_configuration_set.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_configuration_set.c new file mode 100644 index 00000000..84cddc6e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_configuration_set.c @@ -0,0 +1,400 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_configuration_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the configuration from the host and will enable */ +/* the default alternate setting 0 for all the interfaces attached to */ +/* this configuration. */ +/* */ +/* INPUT */ +/* */ +/* endpoint Pointer to endpoint */ +/* configuration_value Configuration selected */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_class_entry_function) Device class entry function */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* _ux_device_stack_interface_delete Delete interface */ +/* _ux_device_stack_interface_set Set interface */ +/* _ux_utility_descriptor_parse Parse descriptor */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_configuration_set(ULONG configuration_value) +{ + +UX_SLAVE_DCD *dcd; +UCHAR * device_framework; +ULONG device_framework_length; +ULONG descriptor_length; +UCHAR descriptor_type; +UX_CONFIGURATION_DESCRIPTOR configuration_descriptor = { 0 }; +UX_INTERFACE_DESCRIPTOR interface_descriptor; +UX_SLAVE_INTERFACE *interface; +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 +UX_SLAVE_INTERFACE *next_interface; +#endif +UX_SLAVE_CLASS *class_inst; +UX_SLAVE_CLASS *current_class = UX_NULL; +UX_SLAVE_CLASS_COMMAND class_command; +UX_SLAVE_DEVICE *device; +ULONG iad_flag; +ULONG iad_first_interface = 0; +ULONG iad_number_interfaces = 0; +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 +ULONG class_index; +#endif + + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_CONFIGURATION_SET, configuration_value, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Reset the IAD flag. */ + iad_flag = UX_FALSE; + + /* If the configuration value is already selected, keep it. */ + if (device -> ux_slave_device_configuration_selected == configuration_value) + return(UX_SUCCESS); + + /* We may have multiple configurations !, the index will tell us what + configuration descriptor we need to return. */ + device_framework = _ux_system_slave -> ux_system_slave_device_framework; + device_framework_length = _ux_system_slave -> ux_system_slave_device_framework_length; + + /* Parse the device framework and locate a configuration descriptor. */ + while (device_framework_length != 0) + { + /* Get the length of the current descriptor. */ + descriptor_length = (ULONG) *device_framework; + + /* And its type. */ + descriptor_type = *(device_framework + 1); + + /* Check if this is a configuration descriptor. */ + if (descriptor_type == UX_CONFIGURATION_DESCRIPTOR_ITEM) + { + /* Parse the descriptor in something more readable. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_configuration_descriptor_structure, + UX_CONFIGURATION_DESCRIPTOR_ENTRIES, + (UCHAR *) &configuration_descriptor); + + /* Now we need to check the configuration value. It has + to be the same as the one specified in the setup function. */ + if (configuration_descriptor.bConfigurationValue == configuration_value) + /* The configuration is found. */ + break; + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + + /* Configuration not found. */ + if (device_framework_length == 0 && configuration_value != 0) + return(UX_ERROR); + + /* We unmount the configuration if there is previous configuration selected. */ + if (device -> ux_slave_device_configuration_selected) + { + + /* Get the pointer to the first interface. */ + interface = device -> ux_slave_device_first_interface; + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Deactivate all the interfaces if any. */ + while (interface != UX_NULL) + { +#endif + /* Build all the fields of the Class Command. */ + class_command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_DEACTIVATE; + class_command.ux_slave_class_command_interface = (VOID *) interface; + + /* Get the pointer to the class container of this interface. */ + class_inst = interface -> ux_slave_interface_class; + + /* Store the class container. */ + class_command.ux_slave_class_command_class_ptr = class_inst; + + /* If there is a class container for this instance, deactivate it. */ + if (class_inst != UX_NULL) + + /* Call the class with the DEACTIVATE signal. */ + class_inst -> ux_slave_class_entry_function(&class_command); + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Get the next interface. */ + next_interface = interface -> ux_slave_interface_next_interface; +#endif + + /* Remove the interface and all endpoints associated with it. */ + _ux_device_stack_interface_delete(interface); + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Now we refresh the interface pointer. */ + interface = next_interface; + } +#endif + + } + + /* No configuration is selected. */ + device -> ux_slave_device_configuration_selected = 0; + + /* Mark the device as attached now. */ + device -> ux_slave_device_state = UX_DEVICE_ATTACHED; + + /* The DCD needs to update the device state too. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_CHANGE_STATE, (VOID *) UX_DEVICE_ATTACHED); + + /* If the host tries to unconfigure, we are done. */ + if (configuration_value == 0) + return(UX_SUCCESS); + + /* Memorize the configuration selected. */ + device -> ux_slave_device_configuration_selected = configuration_value; + + /* We have found the configuration value requested by the host. + Create the configuration descriptor and attach it to the device. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_configuration_descriptor_structure, + UX_CONFIGURATION_DESCRIPTOR_ENTRIES, + (UCHAR *) &device -> ux_slave_device_configuration_descriptor); + + /* Configuration character D6 is for Self-powered */ + _ux_system_slave -> ux_system_slave_power_state = (configuration_descriptor.bmAttributes & 0x40) ? UX_DEVICE_SELF_POWERED : UX_DEVICE_BUS_POWERED; + + /* Configuration character D5 is for Remote Wakeup */ + _ux_system_slave -> ux_system_slave_remote_wakeup_capability = (configuration_descriptor.bmAttributes & 0x20) ? UX_TRUE : UX_FALSE; + + /* Search only in current configuration */ + device_framework_length = configuration_descriptor.wTotalLength; + + /* We need to scan all the interface descriptors following this + configuration descriptor and enable all endpoints associated + with the default alternate setting of each interface. */ + while (device_framework_length != 0) + { + + /* Get the length of the current descriptor. */ + descriptor_length = (ULONG) *device_framework; + + /* And its type. */ + descriptor_type = *(device_framework + 1); + + /* Check if this is an interface association descriptor. */ + if(descriptor_type == UX_INTERFACE_ASSOCIATION_DESCRIPTOR_ITEM) + { + + /* Set the IAD flag. */ + iad_flag = UX_TRUE; + + /* Get the first interface we have in the IAD. */ + iad_first_interface = (ULONG) *(device_framework + 2); + + /* Get the number of interfaces we have in the IAD. */ + iad_number_interfaces = (ULONG) *(device_framework + 3); + } + + /* Check if this is an interface descriptor. */ + if(descriptor_type == UX_INTERFACE_DESCRIPTOR_ITEM) + { + + /* Parse the descriptor in something more readable. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_interface_descriptor_structure, + UX_INTERFACE_DESCRIPTOR_ENTRIES, + (UCHAR *) &interface_descriptor); + + /* If the alternate setting is 0 for this interface, we need to + memorize its class association and start it. */ + if (interface_descriptor.bAlternateSetting == 0) + { + + /* Are we in a IAD scenario ? */ + if (iad_flag == UX_TRUE) + { + + /* Check if this is the first interface from the IAD. In this case, + we need to match a class to this interface. */ + if (interface_descriptor.bInterfaceNumber == iad_first_interface) + { + + /* First interface. Scan the list of classes to find a match. */ + class_inst = _ux_system_slave -> ux_system_slave_class_array; + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* Parse all the class drivers. */ + for (class_index = 0; class_index < _ux_system_slave -> ux_system_slave_max_class; class_index++) + { +#endif + + /* Check if this class driver is used. */ + if (class_inst -> ux_slave_class_status == UX_USED) + { + + /* Check if this is the same interface for the same configuration. */ + if ((interface_descriptor.bInterfaceNumber == class_inst -> ux_slave_class_interface_number) && + (configuration_value == class_inst -> ux_slave_class_configuration_number)) + { + + /* Memorize the class in the class/interface array. */ + _ux_system_slave -> ux_system_slave_interface_class_array[interface_descriptor.bInterfaceNumber] = class_inst; + + /* And again as the current class. */ + current_class = class_inst; + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* We are done here. */ + break; +#endif + } + } + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* Move to the next registered class. */ + class_inst ++; + } +#endif + } + else + + /* Memorize the class in the class/interface array. We use the current class. */ + _ux_system_slave -> ux_system_slave_interface_class_array[interface_descriptor.bInterfaceNumber] = current_class; + + /* Decrement the number of interfaces found in the same IAD. */ + iad_number_interfaces--; + + /* If none are left, get out of the IAD state machine. */ + if (iad_number_interfaces == 0) + + /* We have exhausted the interfaces within the IAD. */ + iad_flag = UX_FALSE; + + } + else + { + + /* First interface. Scan the list of classes to find a match. */ + class_inst = _ux_system_slave -> ux_system_slave_class_array; + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* Parse all the class drivers. */ + for (class_index = 0; class_index < _ux_system_slave -> ux_system_slave_max_class; class_index++) + { +#endif + + /* Check if this class driver is used. */ + if (class_inst -> ux_slave_class_status == UX_USED) + { + + /* Check if this is the same interface for the same configuration. */ + if ((interface_descriptor.bInterfaceNumber == class_inst -> ux_slave_class_interface_number) && + (configuration_value == class_inst -> ux_slave_class_configuration_number)) + { + + /* Memorize the class in the class/interface array. */ + _ux_system_slave -> ux_system_slave_interface_class_array[interface_descriptor.bInterfaceNumber] = class_inst; + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* We are done here. */ + break; +#endif + } + } + +#if UX_MAX_SLAVE_CLASS_DRIVER > 1 + /* Move to the next registered class. */ + class_inst ++; + } +#endif + } + + /* Set the interface. */ + _ux_device_stack_interface_set(device_framework, device_framework_length, 0); + } + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + + /* Mark the device as configured now. */ + device -> ux_slave_device_state = UX_DEVICE_CONFIGURED; + + /* The DCD needs to update the device state too. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_CHANGE_STATE, (VOID *) UX_DEVICE_CONFIGURED); + + /* Configuration mounted. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_control_request_process.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_control_request_process.c new file mode 100644 index 00000000..4dc50d03 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_control_request_process.c @@ -0,0 +1,328 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_control_request_process PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called by the DCD when the device has received a */ +/* SETUP packet. */ +/* */ +/* INPUT */ +/* */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_class_entry_function) Device class entry function */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_device_stack_alternate_setting_get */ +/* Get alternate settings */ +/* _ux_device_stack_alternate_setting_set */ +/* Set alternate settings */ +/* _ux_device_stack_clear_feature Clear feature */ +/* _ux_device_stack_configuration_get Get configuration */ +/* _ux_device_stack_configuration_set Set configuration */ +/* _ux_device_stack_descriptor_send Send descriptor */ +/* _ux_device_stack_get_status Get status */ +/* _ux_device_stack_set_feature Set feature */ +/* _ux_utility_short_get Get short value */ +/* */ +/* CALLED BY */ +/* */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed possible buffer issue */ +/* for control vendor request, */ +/* resulting in version 6.1.9 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added printer support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_control_request_process(UX_SLAVE_TRANSFER *transfer_request) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_DEVICE *device; +UX_SLAVE_CLASS *class; +UX_SLAVE_CLASS_COMMAND class_command; +ULONG request_type; +ULONG request; +ULONG request_value; +ULONG request_index; +ULONG request_length; +ULONG class_index; +UINT status = UX_ERROR; +UX_SLAVE_ENDPOINT *endpoint; +ULONG application_data_length; + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Ensure that the Setup request has been received correctly. */ + if (transfer_request -> ux_slave_transfer_request_completion_code == UX_SUCCESS) + { + + /* Seems so far, the Setup request is valid. Extract all fields of + the request. */ + request_type = *transfer_request -> ux_slave_transfer_request_setup; + request = *(transfer_request -> ux_slave_transfer_request_setup + UX_SETUP_REQUEST); + request_value = _ux_utility_short_get(transfer_request -> ux_slave_transfer_request_setup + UX_SETUP_VALUE); + request_index = _ux_utility_short_get(transfer_request -> ux_slave_transfer_request_setup + UX_SETUP_INDEX); + request_length = _ux_utility_short_get(transfer_request -> ux_slave_transfer_request_setup + UX_SETUP_LENGTH); + + /* Filter for GET_DESCRIPTOR/SET_DESCRIPTOR commands. If the descriptor to be returned is not a standard descriptor, + treat the command as a CLASS command. */ + if ((request == UX_GET_DESCRIPTOR || request == UX_SET_DESCRIPTOR) && (((request_value >> 8) & UX_REQUEST_TYPE) != UX_REQUEST_TYPE_STANDARD)) + { + + /* This request is to be handled by the class layer. */ + request_type &= (UINT)~UX_REQUEST_TYPE; + request_type |= UX_REQUEST_TYPE_CLASS; + } + + /* Check if there is a vendor registered function at the application layer. If the request + is VENDOR and the request match, pass the request to the application. */ + if ((request_type & UX_REQUEST_TYPE) == UX_REQUEST_TYPE_VENDOR) + { + + /* Check the request demanded and compare it to the application registered one. */ + if (request == _ux_system_slave -> ux_system_slave_device_vendor_request) + { + + /* This is a Microsoft extended function. It happens before the device is configured. + The request is passed to the application directly. */ + application_data_length = UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH; + status = _ux_system_slave -> ux_system_slave_device_vendor_request_function(request, request_value, + request_index, request_length, + transfer_request -> ux_slave_transfer_request_data_pointer, + &application_data_length); + + /* Check the status from the application. */ + if (status == UX_SUCCESS) + { + + /* Get the control endpoint associated with the device. */ + endpoint = &device -> ux_slave_device_control_endpoint; + + /* Get the pointer to the transfer request associated with the control endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Set the direction to OUT. */ + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT; + + /* Perform the data transfer. */ + _ux_device_stack_transfer_request(transfer_request, application_data_length, request_length); + + /* We are done here. */ + return(UX_SUCCESS); + } + else + { + + /* The application did not like the vendor command format, stall the control endpoint. */ + _ux_device_stack_endpoint_stall(&device -> ux_slave_device_control_endpoint); + + /* We are done here. */ + return(UX_SUCCESS); + } + } + } + + /* Check the destination of the request. If the request is of type CLASS or VENDOR_SPECIFIC, + the function has to be passed to the class layer. */ + if (((request_type & UX_REQUEST_TYPE) == UX_REQUEST_TYPE_CLASS) || + ((request_type & UX_REQUEST_TYPE) == UX_REQUEST_TYPE_VENDOR)) + { + + /* Build all the fields of the Class Command. */ + class_command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_REQUEST; + + /* We need to find which class this request is for. */ + for (class_index = 0; class_index < UX_MAX_SLAVE_INTERFACES; class_index ++) + { + + /* Get the class for the interface. */ + class = _ux_system_slave -> ux_system_slave_interface_class_array[class_index]; + + /* If class is not ready, try next. */ + if (class == UX_NULL) + continue; + + /* Is the request target to an interface? */ + if ((request_type & UX_REQUEST_TARGET) == UX_REQUEST_TARGET_INTERFACE) + { + + /* Yes, so the request index contains the index of the interface + the request is for. So if the current index does not match + the request index, we should go to the next one. */ + /* For printer class (0x07) GET_DEVICE_ID (0x00) the high byte of + wIndex is interface index (for recommended index sequence the interface + number is same as interface index inside configuration). */ + if (((request_index & 0xFF) != class_index) || + ((class -> ux_slave_class_interface -> ux_slave_interface_descriptor.bInterfaceClass == 0x07) && + (request == 0x00) && + *(transfer_request -> ux_slave_transfer_request_setup + UX_SETUP_INDEX + 1) != class_index)) + continue; + } + + /* Memorize the class in the command. */ + class_command.ux_slave_class_command_class_ptr = class; + + /* We have found a potential candidate. Call this registered class entry function. */ + status = class -> ux_slave_class_entry_function(&class_command); + + /* The status simply tells us if the registered class handled the + command - if there was an issue processing the command, it would've + stalled the control endpoint, notifying the host (and not us). */ + if (status == UX_SUCCESS) + + /* We are done, break the loop! */ + break; + + /* Not handled, try next. */ + } + + /* If no class handled the command, then we have an error here. */ + if (status != UX_SUCCESS) + + /* We stall the command (request not supported). */ + _ux_device_stack_endpoint_stall(&device -> ux_slave_device_control_endpoint); + + /* We are done for class/vendor request. */ + return(status); + } + + /* At this point, the request must be a standard request that the device stack should handle. */ + switch (request) + { + + case UX_GET_STATUS: + + status = _ux_device_stack_get_status(request_type, request_index, request_length); + break; + + case UX_CLEAR_FEATURE: + + status = _ux_device_stack_clear_feature(request_type, request_value, request_index); + break; + + case UX_SET_FEATURE: + + status = _ux_device_stack_set_feature(request_type, request_value, request_index); + break; + + case UX_SET_ADDRESS: + + /* Memorize the address. Some controllers memorize the address here. Some don't. */ + dcd -> ux_slave_dcd_device_address = request_value; + + /* Force the new address. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_SET_DEVICE_ADDRESS, (VOID *) (ALIGN_TYPE) request_value); + break; + + case UX_GET_DESCRIPTOR: + + status = _ux_device_stack_descriptor_send(request_value, request_index, request_length); + break; + + case UX_SET_DESCRIPTOR: + + status = UX_FUNCTION_NOT_SUPPORTED; + break; + + case UX_GET_CONFIGURATION: + + status = _ux_device_stack_configuration_get(); + break; + + case UX_SET_CONFIGURATION: + + status = _ux_device_stack_configuration_set(request_value); + break; + + case UX_GET_INTERFACE: + + status = _ux_device_stack_alternate_setting_get(request_index); + break; + + case UX_SET_INTERFACE: + + status = _ux_device_stack_alternate_setting_set(request_index,request_value); + break; + + + case UX_SYNCH_FRAME: + + status = UX_SUCCESS; + break; + + default : + + status = UX_FUNCTION_NOT_SUPPORTED; + break; + } + + if (status != UX_SUCCESS) + + /* Stall the control endpoint to issue protocol error. */ + _ux_device_stack_endpoint_stall(&device -> ux_slave_device_control_endpoint); + } + + /* Return the function status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_descriptor_send.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_descriptor_send.c new file mode 100644 index 00000000..49652a39 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_descriptor_send.c @@ -0,0 +1,486 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +#if (UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH < UX_DEVICE_DESCRIPTOR_LENGTH) || \ + (UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH < UX_DEVICE_QUALIFIER_DESCRIPTOR_LENGTH) || \ + (UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH < UX_OTG_DESCRIPTOR_LENGTH) +#error UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH too small, please check +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_descriptor_send PORTABLE C */ +/* 6.1.3 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sends back the device descriptor required by the host.*/ +/* */ +/* INPUT */ +/* */ +/* descriptor_type Descriptor type */ +/* descriptor_index Index of descriptor */ +/* host_length Length requested by host */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* _ux_device_stack_transfer_request Process transfer request */ +/* _ux_utility_descriptor_parse Parse descriptor */ +/* _ux_utility_memory_copy Memory copy */ +/* _ux_utility_short_get Get short value */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized descriptor search */ +/* logic, verified memset and */ +/* memcpy cases, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* added BOS support, */ +/* resulting in version 6.1.3 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_descriptor_send(ULONG descriptor_type, ULONG request_index, ULONG host_length) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_DEVICE *device; +ULONG descriptor_index; +ULONG parsed_descriptor_index; +UX_SLAVE_TRANSFER *transfer_request; +UX_CONFIGURATION_DESCRIPTOR configuration_descriptor; +#ifndef UX_BOS_SUPPORT_DISABLE +UX_BOS_DESCRIPTOR bos_descriptor; +#endif +UX_SLAVE_ENDPOINT *endpoint; +UCHAR *device_framework; +UCHAR *device_framework_end; +ULONG device_framework_length; +ULONG descriptor_length; +ULONG target_descriptor_length; +UINT status = UX_ERROR; +ULONG length; +UCHAR *string_memory; +UCHAR *string_framework; +ULONG string_framework_length; +ULONG string_length; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_DESCRIPTOR_SEND, descriptor_type, request_index, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Get the control endpoint associated with the device. */ + endpoint = &device -> ux_slave_device_control_endpoint; + + /* Get the pointer to the transfer request associated with the endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Set the direction to OUT. */ + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT; + + /* Isolate the descriptor index. */ + descriptor_index = descriptor_type & 0xff; + + /* Reset the parsed index. */ + parsed_descriptor_index = 0; + + /* Shift the descriptor type in the low byte field. */ + descriptor_type = (UCHAR) ((descriptor_type >> 8) & 0xff); + + /* Default descriptor length is host length. */ + length = host_length; + + /* What type of descriptor do we need to return? */ + switch (descriptor_type) + { + + case UX_DEVICE_DESCRIPTOR_ITEM: + + /* Setup device descriptor length. */ + if (host_length > UX_DEVICE_DESCRIPTOR_LENGTH) + length = UX_DEVICE_DESCRIPTOR_LENGTH; + + /* Fall through. */ + case UX_DEVICE_QUALIFIER_DESCRIPTOR_ITEM: + + /* Setup qualifier descriptor length. */ + if (descriptor_type == UX_DEVICE_QUALIFIER_DESCRIPTOR_ITEM && + host_length > UX_DEVICE_QUALIFIER_DESCRIPTOR_LENGTH) + length = UX_DEVICE_QUALIFIER_DESCRIPTOR_LENGTH; + + /* Fall through. */ + case UX_OTG_DESCRIPTOR_ITEM: + + /* Setup OTG descriptor length. */ + if (descriptor_type == UX_OTG_DESCRIPTOR_ITEM && + host_length > UX_OTG_DESCRIPTOR_LENGTH) + length = UX_OTG_DESCRIPTOR_LENGTH; + + /* We may or may not have a device qualifier descriptor. */ + device_framework = _ux_system_slave -> ux_system_slave_device_framework; + device_framework_length = _ux_system_slave -> ux_system_slave_device_framework_length; + device_framework_end = device_framework + device_framework_length; + + /* Parse the device framework and locate a device qualifier descriptor. */ + while (device_framework < device_framework_end) + { + + /* Get descriptor length. */ + descriptor_length = (ULONG) *device_framework; + + /* Check if this is a descriptor expected. */ + if (*(device_framework + 1) == descriptor_type) + { + + /* Copy the device descriptor into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer, + device_framework, length); /* Use case of memcpy is verified. */ + + /* Perform the data transfer. */ + status = _ux_device_stack_transfer_request(transfer_request, length, host_length); + break; + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + break; + +#ifndef UX_BOS_SUPPORT_DISABLE + case UX_BOS_DESCRIPTOR_ITEM: + /* Fall through. */ +#endif + case UX_OTHER_SPEED_DESCRIPTOR_ITEM: + /* Fall through. */ + case UX_CONFIGURATION_DESCRIPTOR_ITEM: + + if (descriptor_type == UX_OTHER_SPEED_DESCRIPTOR_ITEM) + { + + /* This request is used by the host to find out the capability of this device + if it was running at full speed. The behavior is the same as in a GET_CONFIGURATIOn descriptor + but we do not use the current device framework but rather the full speed framework. */ + device_framework = _ux_system_slave -> ux_system_slave_device_framework_full_speed; + device_framework_length = _ux_system_slave -> ux_system_slave_device_framework_length_full_speed; + device_framework_end = device_framework + device_framework_length; + } + else + { + + /* We may have multiple configurations !, the index will tell us what + configuration descriptor we need to return. */ + device_framework = _ux_system_slave -> ux_system_slave_device_framework; + device_framework_length = _ux_system_slave -> ux_system_slave_device_framework_length; + device_framework_end = device_framework + device_framework_length; + } + + /* Parse the device framework and locate a configuration descriptor. */ + while (device_framework < device_framework_end) + { + + /* Get descriptor length. */ + descriptor_length = (ULONG) *device_framework; + +#ifndef UX_BOS_SUPPORT_DISABLE + + /* Check if we are finding BOS descriptor. */ + if (descriptor_type == UX_BOS_DESCRIPTOR_ITEM) + { + if (*(device_framework + 1) == UX_BOS_DESCRIPTOR_ITEM) + { + + /* Parse the BOS descriptor. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_bos_descriptor_structure, + UX_BOS_DESCRIPTOR_ENTRIES, + (UCHAR *) &bos_descriptor); + + /* Get the length of entire BOS descriptor. */ + target_descriptor_length = bos_descriptor.wTotalLength; + + /* Descriptor is found. */ + status = UX_SUCCESS; + break; + } + } + else +#endif + + { + + /* Check if this is a configuration descriptor. We are cheating here. Instead of creating + a OTHER SPEED descriptor, we simply scan the configuration descriptor for the Full Speed + framework and return this configuration after we manually changed the configuration descriptor + item into a Other Speed Descriptor. */ + if (*(device_framework + 1) == UX_CONFIGURATION_DESCRIPTOR_ITEM) + { + + /* Check the index. It must be the same as the one requested. */ + if (parsed_descriptor_index == descriptor_index) + { + + /* Parse the configuration descriptor. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_configuration_descriptor_structure, + UX_CONFIGURATION_DESCRIPTOR_ENTRIES, + (UCHAR *) &configuration_descriptor); + + /* Get the length of entire configuration descriptor. */ + target_descriptor_length = configuration_descriptor.wTotalLength; + + /* Descriptor is found. */ + status = UX_SUCCESS; + break; + } + else + { + + /* There may be more configuration descriptors in this framework. */ + parsed_descriptor_index++; + } + } + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + + /* Send the descriptor. */ + if (status == UX_SUCCESS) + { + + /* Ensure the host does not demand a length beyond our descriptor (Windows does that) + and do not return more than what is allowed. */ + if (target_descriptor_length < host_length) + length = target_descriptor_length; + else + length = host_length; + + /* Check buffer length, since total descriptors length may exceed buffer... */ + if (length > UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH) + { + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_DEVICE_STACK, UX_MEMORY_INSUFFICIENT); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MEMORY_INSUFFICIENT, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Stall the endpoint. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + break; + } + + /* Copy the device descriptor into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer, + device_framework, length); /* Use case of memcpy is verified. */ + + /* Now we need to hack the found descriptor because this request expect a requested + descriptor type instead of the regular descriptor. */ + *(transfer_request -> ux_slave_transfer_request_data_pointer + 1) = (UCHAR)descriptor_type; + + /* We can return the configuration descriptor. */ + status = _ux_device_stack_transfer_request(transfer_request, length, host_length); + } + break; + + case UX_STRING_DESCRIPTOR_ITEM: + + /* We need to filter for the index 0 which is the language ID string. */ + if (descriptor_index == 0) + { + + /* We need to check request buffer size in case it's possible exceed. */ + if (_ux_system_slave -> ux_system_slave_language_id_framework_length + 2 > UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_DEVICE_STACK, UX_MEMORY_INSUFFICIENT); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MEMORY_INSUFFICIENT, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Stall the endpoint. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + break; + } + + /* We have a request to send back the language ID list. Use the transfer request buffer. */ + string_memory = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Store the total length of the response. */ + *string_memory = (UCHAR)(_ux_system_slave -> ux_system_slave_language_id_framework_length + 2); + + /* Store the descriptor type. */ + *(string_memory +1) = UX_STRING_DESCRIPTOR_ITEM; + + /* Store the language ID into the buffer. */ + _ux_utility_memory_copy(string_memory+2, _ux_system_slave -> ux_system_slave_language_id_framework, + _ux_system_slave -> ux_system_slave_language_id_framework_length); /* Use case of memcpy is verified. */ + + /* Filter the length asked/required. */ + if (host_length > _ux_system_slave -> ux_system_slave_language_id_framework_length + 2) + length = _ux_system_slave -> ux_system_slave_language_id_framework_length + 2; + else + length = host_length; + + /* We can return the string language ID descriptor. */ + status = _ux_device_stack_transfer_request(transfer_request, length, host_length); + } + else + { + + /* The host wants a specific string index returned. Get the string framework pointer + and length. */ + string_framework = _ux_system_slave -> ux_system_slave_string_framework; + string_framework_length = _ux_system_slave -> ux_system_slave_string_framework_length; + + /* We search through the string framework until we find the right index. + The index is in the lower byte of the descriptor type. */ + while (string_framework_length != 0) + { + + /* Ensure we have the correct language page. */ + if (_ux_utility_short_get(string_framework) == request_index) + { + + /* Check the index. */ + if (*(string_framework + 2) == descriptor_index) + { + + /* We need to check request buffer size in case it's possible exceed. */ + if (((*(string_framework + 3)*2) + 2) > UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_DEVICE_STACK, UX_MEMORY_INSUFFICIENT); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MEMORY_INSUFFICIENT, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Stall the endpoint. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + break; + } + + /* We have a request to send back a string. Use the transfer request buffer. */ + string_memory = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Store the length in the string buffer. The length + of the string descriptor is stored in the third byte, + hence the ' + 3'. The encoding must be in 16-bit + unicode, hence the '*2'. The length includes the size + of the length itself as well as the descriptor type, + hence the ' + 2'. */ + *string_memory = (UCHAR)((*(string_framework + 3)*2) + 2); + + /* Store the Descriptor type. */ + *(string_memory + 1) = UX_STRING_DESCRIPTOR_ITEM; + + /* Create the Unicode string. */ + for (string_length = 0; string_length < *(string_framework + 3) ; string_length ++) + { + + /* Insert a Unicode byte. */ + *(string_memory + 2 + (string_length * 2)) = *(string_framework + 4 + string_length); + + /* Insert a zero after the Unicode byte. */ + *(string_memory + 2 + (string_length * 2) + 1) = 0; + } + + /* Filter the length asked/required. */ + if (host_length > (UINT)((*(string_framework + 3)*2) + 2)) + length = (ULONG)((*(string_framework + 3)*2) + 2); + else + length = host_length; + + /* We can return the string descriptor. */ + status = _ux_device_stack_transfer_request(transfer_request, length, host_length); + break; + } + } + + /* This is the wrong string descriptor, jump to the next. */ + string_framework_length -= (ULONG) *(string_framework + 3) + 4; + string_framework += (ULONG) *(string_framework + 3) + 4; + } + + /* Have we exhausted all the string descriptors? */ + if (string_framework_length == 0) + { + + /* Could not find the required string index. Stall the endpoint. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + return(UX_ERROR); + } + } + break; + + default: + + /* Stall the endpoint. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + return(UX_ERROR); + } + + /* Return the status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_disconnect.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_disconnect.c new file mode 100644 index 00000000..83098ddc --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_disconnect.c @@ -0,0 +1,174 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_disconnect PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called when the device gets disconnected from the */ +/* host. All the device resources are freed. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_class_entry_function) Device class entry function */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* _ux_device_stack_interface_delete Delete interface */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_disconnect(VOID) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_DEVICE *device; +UX_SLAVE_INTERFACE *interface; +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 +UX_SLAVE_INTERFACE *next_interface; +#endif +UX_SLAVE_CLASS *class; +UX_SLAVE_CLASS_COMMAND class_command; +UINT status = UX_ERROR; + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_DISCONNECT, device, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_UNREGISTER(device); + + /* If the device was in the configured state, there may be interfaces + attached to the configuration. */ + if (device -> ux_slave_device_state == UX_DEVICE_CONFIGURED) + { + /* Get the pointer to the first interface. */ + interface = device -> ux_slave_device_first_interface; + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Parse all the interfaces if any. */ + while (interface != UX_NULL) + { +#endif + + /* Build all the fields of the Class Command. */ + class_command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_DEACTIVATE; + class_command.ux_slave_class_command_interface = (VOID *) interface; + + /* Get the pointer to the class container of this interface. */ + class = interface -> ux_slave_interface_class; + + /* Store the class container. */ + class_command.ux_slave_class_command_class_ptr = class; + + /* If there is a class container for this instance, deactivate it. */ + if (class != UX_NULL) + + /* Call the class with the DEACTIVATE signal. */ + class -> ux_slave_class_entry_function(&class_command); + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Get the next interface. */ + next_interface = interface -> ux_slave_interface_next_interface; +#endif + + /* Remove the interface and all endpoints associated with it. */ + _ux_device_stack_interface_delete(interface); + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Now we refresh the interface pointer. */ + interface = next_interface; + } +#endif + + /* Mark the device as attached now. */ + device -> ux_slave_device_state = UX_DEVICE_ATTACHED; + } + + /* If the device was attached, we need to destroy the control endpoint. */ + if (device -> ux_slave_device_state == UX_DEVICE_ATTACHED) + + /* Now we can destroy the default control endpoint. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_DESTROY_ENDPOINT, + (VOID *) &device -> ux_slave_device_control_endpoint); + + /* We are reverting to configuration 0. */ + device -> ux_slave_device_configuration_selected = 0; + + /* Set the device to be non attached. */ + device -> ux_slave_device_state = UX_DEVICE_RESET; + + /* Check the status change callback. */ + if(_ux_system_slave -> ux_system_slave_change_function != UX_NULL) + { + + /* Inform the application if a callback function was programmed. */ + _ux_system_slave -> ux_system_slave_change_function(UX_DEVICE_REMOVED); + } + + /* Return the status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_endpoint_stall.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_endpoint_stall.c new file mode 100644 index 00000000..4f1a5a4e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_endpoint_stall.c @@ -0,0 +1,121 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_endpoint_stall PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function stalls an endpoint. The host will need to reissue */ +/* a reset to clear the endpoint. */ +/* */ +/* INPUT */ +/* */ +/* endpoint Pointer to endpoint */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_endpoint_stall(UX_SLAVE_ENDPOINT *endpoint) +{ + +UX_INTERRUPT_SAVE_AREA + +UX_SLAVE_DCD *dcd; +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_ENDPOINT_STALL, endpoint, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Assume device is in an invalid state here in order to reduce code in following + section where interrupts are disabled. */ + status = UX_ERROR; + + /* Ensure we don't change the endpoint's state after disconnection routine + resets it. */ + UX_DISABLE + + /* Check if the device is in a valid state; as soon as the device is out + of the RESET state, transfers occur and thus endpoints may be stalled. */ + if (_ux_system_slave -> ux_system_slave_device.ux_slave_device_state != UX_DEVICE_RESET && + endpoint -> ux_slave_endpoint_state != UX_ENDPOINT_HALTED) + { + + /* Stall the endpoint. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + + /* Mark the endpoint state. */ + if ((endpoint -> ux_slave_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE) != + UX_CONTROL_ENDPOINT) + endpoint -> ux_slave_endpoint_state = UX_ENDPOINT_HALTED; + } + + /* Restore interrupts. */ + UX_RESTORE + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_get_status.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_get_status.c new file mode 100644 index 00000000..360b2d40 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_get_status.c @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_get_status PORTABLE C */ +/* 6.1.6 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function obtains the status of a USB component of the device */ +/* such as device or endpoint. */ +/* */ +/* INPUT */ +/* */ +/* request_type Request type */ +/* request_index Request index */ +/* request_length Request length */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Transfer request */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* */ +/* CALLED BY */ +/* */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* supported bi-dir-endpoints, */ +/* resulting in version 6.1.6 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_get_status(ULONG request_type, ULONG request_index, ULONG request_length) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_TRANSFER *transfer_request; +UX_SLAVE_DEVICE *device; +UX_SLAVE_ENDPOINT *endpoint; +UINT status; +ULONG data_length; + + UX_PARAMETER_NOT_USED(request_length); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_GET_STATUS, request_type, request_index, request_length, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Get the control endpoint for the device. */ + endpoint = &device -> ux_slave_device_control_endpoint; + + /* Get the pointer to the transfer request associated with the endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Reset the status buffer. */ + *transfer_request -> ux_slave_transfer_request_data_pointer = 0; + *(transfer_request -> ux_slave_transfer_request_data_pointer + 1) = 0; + + /* The default length for GET_STATUS is 2, except for OTG get Status. */ + data_length = 2; + + /* The status can be for either the device or the endpoint. */ + switch (request_type & UX_REQUEST_TARGET) + { + + case UX_REQUEST_TARGET_DEVICE: + + /* When the device is probed, it is either for the power/remote capabilities or OTG role swap. + We differentiate with the Windex, 0 or OTG status Selector. */ + if (request_index == UX_OTG_STATUS_SELECTOR) + { + + /* Set the data length to 1. */ + data_length = 1; + +#ifdef UX_OTG_SUPPORT + /* Store the Role Swap flag. */ + *transfer_request -> ux_slave_transfer_request_data_pointer = (UCHAR) _ux_system_otg -> ux_system_otg_slave_role_swap_flag; +#endif + + } + else + { + + /* Store the current power state in the status buffer. */ + if (_ux_system_slave -> ux_system_slave_power_state == UX_DEVICE_SELF_POWERED) + *transfer_request -> ux_slave_transfer_request_data_pointer = 1; + + /* Store the remote wakeup capability state in the status buffer. */ + + if (_ux_system_slave -> ux_system_slave_remote_wakeup_enabled) + *transfer_request -> ux_slave_transfer_request_data_pointer |= 2; + } + + break; + + case UX_REQUEST_TARGET_ENDPOINT: + +#ifndef UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT + + /* This feature returns the halt state of a specific endpoint. The endpoint index + is used to retrieve the endpoint container. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_ENDPOINT_STATUS, (VOID *)(ALIGN_TYPE)(request_index & (UINT)~UX_ENDPOINT_DIRECTION)); +#else + + /* This feature returns the halt state of a specific endpoint. The endpoint address + is used to retrieve the endpoint container. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_ENDPOINT_STATUS, (VOID *)(ALIGN_TYPE)(request_index)); +#endif + + /* Check the status. We may have a unknown endpoint. */ + if (status != UX_ERROR) + { + + if (status == UX_TRUE) + *transfer_request -> ux_slave_transfer_request_data_pointer = 1; + } + else + { + + /* We stall the command. Endpoint is wrong. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + + /* No more work to do here. The command failed but the upper layer does not depend on it. */ + return(UX_SUCCESS); + } + break; + + default: + + /* We stall the command. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + + /* No more work to do here. The command failed but the upper layer does not depend on it. */ + return(UX_SUCCESS); + } + + /* Set the phase of the transfer to data out. */ + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT; + + /* Send the descriptor with the appropriate length to the host. */ + status = _ux_device_stack_transfer_request(transfer_request, data_length, data_length); + + /* Return the function status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_host_wakeup.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_host_wakeup.c new file mode 100644 index 00000000..093389b4 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_host_wakeup.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_host_wakeup PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called when the device wants to wake up the host. */ +/* This command is only valid when the device is in suspend mode. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_host_wakeup(VOID) +{ + +UX_SLAVE_DCD *dcd; +UINT status = UX_FUNCTION_NOT_SUPPORTED; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_HOST_WAKEUP, 0, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Check if DEVICE_REMOTE_WAKEUP feature is enabled. */ + if (_ux_system_slave -> ux_system_slave_remote_wakeup_enabled) + + /* Send the change signal to the controller driver. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_CHANGE_STATE, (VOID *) UX_DEVICE_REMOTE_WAKEUP); + + /* Return the status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_initialize.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_initialize.c new file mode 100644 index 00000000..4bfc2165 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_initialize.c @@ -0,0 +1,454 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + +UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_MULC_ULONG(sizeof(UX_SLAVE_CLASS), UX_MAX_SLAVE_CLASS_DRIVER), UX_MAX_SLAVE_CLASS_DRIVER_mul_ovf) + +/* Define the names of all the USB Classes of USBX. */ + +UCHAR _ux_system_slave_class_storage_name[] = "ux_slave_class_storage"; +UCHAR _ux_system_slave_class_cdc_acm_name[] = "ux_slave_class_cdc_acm"; +UCHAR _ux_system_slave_class_dpump_name[] = "ux_slave_class_dpump"; +UCHAR _ux_system_slave_class_pima_name[] = "ux_slave_class_pima"; +UCHAR _ux_system_slave_class_hid_name[] = "ux_slave_class_hid"; +UCHAR _ux_system_slave_class_rndis_name[] = "ux_slave_class_rndis"; +UCHAR _ux_system_slave_class_cdc_ecm_name[] = "ux_slave_class_cdc_ecm"; +UCHAR _ux_system_slave_class_dfu_name[] = "ux_slave_class_dfu"; +UCHAR _ux_system_slave_class_audio_name[] = "ux_slave_class_audio"; + +UCHAR _ux_system_device_class_printer_name[] = "ux_device_class_printer"; + +/* Define USBX Host variable. */ +UX_SYSTEM_SLAVE *_ux_system_slave; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_initialize PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the generic portion of the device side of */ +/* USBX. */ +/* */ +/* INPUT */ +/* */ +/* device_framework_high_speed Pointer to high speed FW */ +/* device_framework_length_high_speed Length of high speed FW */ +/* device_framework_full_speed Pointer to full speed FW */ +/* device_framework_length_full_speed Length of full speed FW */ +/* string_framework Pointer to string FW */ +/* string_framework_length Length of string FW */ +/* language_id_framework Pointer to language ID FW */ +/* language_id_framework_length Length of language ID FW */ +/* (ux_system_slave_change_function) Pointer to callback function */ +/* for device changes */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_allocate Allocate memory */ +/* _ux_utility_memory_free Free memory */ +/* _ux_utility_semaphore_create Create semaphore */ +/* _ux_utility_semaphore_delete Delete semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* added printer support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_initialize(UCHAR * device_framework_high_speed, ULONG device_framework_length_high_speed, + UCHAR * device_framework_full_speed, ULONG device_framework_length_full_speed, + UCHAR * string_framework, ULONG string_framework_length, + UCHAR * language_id_framework, ULONG language_id_framework_length, + UINT (*ux_system_slave_change_function)(ULONG)) +{ +UX_SLAVE_DEVICE *device; +UX_SLAVE_ENDPOINT *endpoints_pool; +UX_SLAVE_INTERFACE *interfaces_pool; +UX_SLAVE_TRANSFER *transfer_request; +UINT status; +ULONG interfaces_found; +ULONG endpoints_found; +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) +ULONG max_interface_number; +ULONG local_interfaces_found; +ULONG local_endpoints_found; +ULONG endpoints_in_interface_found; +UCHAR *device_framework; +ULONG device_framework_length; +UCHAR descriptor_type; +ULONG descriptor_length; +#endif +UCHAR *memory; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_INITIALIZE, 0, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Store the high speed device framework address and length in the project structure. */ + _ux_system_slave -> ux_system_slave_device_framework_high_speed = device_framework_high_speed; + _ux_system_slave -> ux_system_slave_device_framework_length_high_speed = device_framework_length_high_speed; + + /* Store the string framework address and length in the project structure. */ + _ux_system_slave -> ux_system_slave_device_framework_full_speed = device_framework_full_speed; + _ux_system_slave -> ux_system_slave_device_framework_length_full_speed = device_framework_length_full_speed; + + /* Store the string framework address and length in the project structure. */ + _ux_system_slave -> ux_system_slave_string_framework = string_framework; + _ux_system_slave -> ux_system_slave_string_framework_length = string_framework_length; + + /* Store the language ID list in the project structure. */ + _ux_system_slave -> ux_system_slave_language_id_framework = language_id_framework; + _ux_system_slave -> ux_system_slave_language_id_framework_length = language_id_framework_length; + + /* Store the max number of slave class drivers in the project structure. */ + UX_SYSTEM_DEVICE_MAX_CLASS_SET(UX_MAX_SLAVE_CLASS_DRIVER); + + /* Store the device state change function callback. */ + _ux_system_slave -> ux_system_slave_change_function = ux_system_slave_change_function; + + /* Allocate memory for the classes. + * sizeof(UX_SLAVE_CLASS) * UX_MAX_SLAVE_CLASS_DRIVER) overflow is checked + * outside of the function. + */ + memory = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_SLAVE_CLASS) * UX_MAX_SLAVE_CLASS_DRIVER); + if (memory == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* Save this memory allocation in the USBX project. */ + _ux_system_slave -> ux_system_slave_class_array = (UX_SLAVE_CLASS *) ((void *) memory); + + /* Allocate some memory for the Control Endpoint. First get the address of the transfer request for the + control endpoint. */ + transfer_request = &device -> ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request; + + /* Acquire a buffer for the size of the endpoint. */ + transfer_request -> ux_slave_transfer_request_data_pointer = + _ux_utility_memory_allocate(UX_NO_ALIGN, UX_CACHE_SAFE_MEMORY, UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH); + + /* Ensure we have enough memory. */ + if (transfer_request -> ux_slave_transfer_request_data_pointer == UX_NULL) + status = UX_MEMORY_INSUFFICIENT; + else + status = UX_SUCCESS; + +#if defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) + + /* No scan, just assign predefined value. */ + interfaces_found = UX_MAX_SLAVE_INTERFACES; + endpoints_found = UX_MAX_DEVICE_ENDPOINTS; +#else + + /* Reset all values we are using during the scanning of the framework. */ + interfaces_found = 0; + endpoints_found = 0; + max_interface_number = 0; + + /* Go on to scan interfaces if no error. */ + if (status == UX_SUCCESS) + { + + /* We need to determine the maximum number of interfaces and endpoints declared in the device framework. + This mechanism requires that both framework behave the same way regarding the number of interfaces + and endpoints. */ + device_framework = _ux_system_slave -> ux_system_slave_device_framework_full_speed; + device_framework_length = _ux_system_slave -> ux_system_slave_device_framework_length_full_speed; + + /* Reset all values we are using during the scanning of the framework. */ + local_interfaces_found = 0; + local_endpoints_found = 0; + endpoints_in_interface_found = 0; + + /* Parse the device framework and locate interfaces and endpoint descriptor(s). */ + while (device_framework_length != 0) + { + + /* Get the length of this descriptor. */ + descriptor_length = (ULONG) *device_framework; + + /* And its type. */ + descriptor_type = *(device_framework + 1); + + /* Check if this is an endpoint descriptor. */ + switch(descriptor_type) + { + + case UX_INTERFACE_DESCRIPTOR_ITEM: + + /* Check if this is alternate setting 0. If not, do not add another interface found. + If this is alternate setting 0, reset the endpoints count for this interface. */ + if (*(device_framework + 3) == 0) + { + + /* Add the cumulated number of endpoints in the previous interface. */ + local_endpoints_found += endpoints_in_interface_found; + + /* Read the number of endpoints for this alternate setting. */ + endpoints_in_interface_found = (ULONG) *(device_framework + 4); + + /* Increment the number of interfaces found in the current configuration. */ + local_interfaces_found++; + } + else + { + + /* Compare the number of endpoints found in this non 0 alternate setting. */ + if (endpoints_in_interface_found < (ULONG) *(device_framework + 4)) + + /* Adjust the number of maximum endpoints in this interface. */ + endpoints_in_interface_found = (ULONG) *(device_framework + 4); + } + + /* Check and update max interface number. */ + if (*(device_framework + 2) > max_interface_number) + max_interface_number = *(device_framework + 2); + + break; + + case UX_CONFIGURATION_DESCRIPTOR_ITEM: + + /* Check if the number of interfaces found in this configuration is the maximum so far. */ + if (local_interfaces_found > interfaces_found) + + /* We need to adjust the number of maximum interfaces. */ + interfaces_found = local_interfaces_found; + + /* We have a new configuration. We need to reset the number of local interfaces. */ + local_interfaces_found = 0; + + /* Add the cumulated number of endpoints in the previous interface. */ + local_endpoints_found += endpoints_in_interface_found; + + /* Check if the number of endpoints found in the previous configuration is the maximum so far. */ + if (local_endpoints_found > endpoints_found) + + /* We need to adjust the number of maximum endpoints. */ + endpoints_found = local_endpoints_found; + + /* We have a new configuration. We need to reset the number of local endpoints. */ + local_endpoints_found = 0; + endpoints_in_interface_found = 0; + + break; + + default: + break; + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + + /* Add the cumulated number of endpoints in the previous interface. */ + local_endpoints_found += endpoints_in_interface_found; + + /* Check if the number of endpoints found in the previous interface is the maximum so far. */ + if (local_endpoints_found > endpoints_found) + + /* We need to adjust the number of maximum endpoints. */ + endpoints_found = local_endpoints_found; + + + /* Check if the number of interfaces found in this configuration is the maximum so far. */ + if (local_interfaces_found > interfaces_found) + + /* We need to adjust the number of maximum interfaces. */ + interfaces_found = local_interfaces_found; + + /* We do a sanity check on the finding. At least there must be one interface but endpoints are + not necessary. */ + if (interfaces_found == 0) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_INIT, UX_DESCRIPTOR_CORRUPTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DESCRIPTOR_CORRUPTED, device_framework, 0, 0, UX_TRACE_ERRORS, 0, 0) + + status = UX_DESCRIPTOR_CORRUPTED; + } + + /* We do a sanity check on the finding. Max interface number should not exceed limit. */ + if (status == UX_SUCCESS && + max_interface_number >= UX_MAX_SLAVE_INTERFACES) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_INIT, UX_MEMORY_INSUFFICIENT); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MEMORY_INSUFFICIENT, device_framework, 0, 0, UX_TRACE_ERRORS, 0, 0) + + status = UX_MEMORY_INSUFFICIENT; + } + } +#endif + + /* Go on to allocate interfaces pool if no error. */ + if (status == UX_SUCCESS) + { + + /* Memorize both pool sizes. */ + device -> ux_slave_device_interfaces_pool_number = interfaces_found; + device -> ux_slave_device_endpoints_pool_number = endpoints_found; + + /* We assign a pool for the interfaces. */ + interfaces_pool = _ux_utility_memory_allocate_mulc_safe(UX_NO_ALIGN, UX_REGULAR_MEMORY, interfaces_found, sizeof(UX_SLAVE_INTERFACE)); + if (interfaces_pool == UX_NULL) + status = UX_MEMORY_INSUFFICIENT; + else + + /* Save the interface pool address in the device container. */ + device -> ux_slave_device_interfaces_pool = interfaces_pool; + } + + /* Do we need an endpoint pool ? */ + if (endpoints_found != 0 && status == UX_SUCCESS) + { + + /* We assign a pool for the endpoints. */ + endpoints_pool = _ux_utility_memory_allocate_mulc_safe(UX_NO_ALIGN, UX_REGULAR_MEMORY, endpoints_found, sizeof(UX_SLAVE_ENDPOINT)); + if (endpoints_pool == UX_NULL) + status = UX_MEMORY_INSUFFICIENT; + else + { + + /* Save the endpoint pool address in the device container. */ + device -> ux_slave_device_endpoints_pool = endpoints_pool; + + /* We need to assign a transfer buffer to each endpoint. Each endpoint is assigned the + maximum buffer size. We also assign the semaphore used by the endpoint to synchronize transfer + completion. */ + while (endpoints_pool < (device -> ux_slave_device_endpoints_pool + endpoints_found)) + { + + /* Obtain some memory. */ + endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer = + _ux_utility_memory_allocate(UX_NO_ALIGN, UX_CACHE_SAFE_MEMORY, UX_SLAVE_REQUEST_DATA_MAX_LENGTH); + + /* Ensure we could allocate memory. */ + if (endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer == UX_NULL) + { + status = UX_MEMORY_INSUFFICIENT; + break; + } + + /* Create the semaphore for the endpoint. */ + status = _ux_device_semaphore_create(&endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_semaphore, + "ux_transfer_request_semaphore", 0); + + /* Check completion status. */ + if (status != UX_SUCCESS) + { + status = UX_SEMAPHORE_ERROR; + break; + } + + /* Next endpoint. */ + endpoints_pool++; + } + } + } + else + endpoints_pool = UX_NULL; + + /* Return successful completion. */ + if (status == UX_SUCCESS) + return(UX_SUCCESS); + + /* Free resources when there is error. */ + + /* Free device -> ux_slave_device_endpoints_pool. */ + if (endpoints_pool) + { + + /* In error cases creating endpoint resources, endpoints_pool is endpoint that failed. + * Previously allocated things should be freed. */ + while(endpoints_pool >= device -> ux_slave_device_endpoints_pool) + { + + /* Delete ux_slave_transfer_request_semaphore. */ + if (_ux_device_semaphore_created(&endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_semaphore)) + _ux_device_semaphore_delete(&endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_semaphore); + + /* Free ux_slave_transfer_request_data_pointer buffer. */ + if (endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer) + _ux_utility_memory_free(endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer); + + /* Move to previous endpoint. */ + endpoints_pool --; + } + + _ux_utility_memory_free(device -> ux_slave_device_endpoints_pool); + } + + /* Free device -> ux_slave_device_interfaces_pool. */ + if (device -> ux_slave_device_interfaces_pool) + _ux_utility_memory_free(device -> ux_slave_device_interfaces_pool); + + /* Free device -> ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer. */ + if (device -> ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer) + _ux_utility_memory_free(device -> ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer); + + /* Free _ux_system_slave -> ux_system_slave_class_array. */ + _ux_utility_memory_free(_ux_system_slave -> ux_system_slave_class_array); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_delete.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_delete.c new file mode 100644 index 00000000..b411b581 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_delete.c @@ -0,0 +1,134 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_interface_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes an interface. Semaphore and memory are */ +/* released and the controller driver is invoked to disable the */ +/* hardware endpoint. The interface is then removed from the */ +/* configuration. */ +/* */ +/* INPUT */ +/* */ +/* interface Pointer to interface */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_interface_delete(UX_SLAVE_INTERFACE *interface) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_DEVICE *device; +UX_SLAVE_ENDPOINT *endpoint; +UX_SLAVE_ENDPOINT *next_endpoint; + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_UNREGISTER(interface); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_INTERFACE_DELETE, interface, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Find the first endpoints associated with this interface. */ + next_endpoint = interface -> ux_slave_interface_first_endpoint; + + /* Parse all the endpoints. */ + while (next_endpoint != UX_NULL) + { + + /* Save this endpoint. */ + endpoint = next_endpoint; + + /* Find the next endpoint. */ + next_endpoint = endpoint -> ux_slave_endpoint_next_endpoint; + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave->ux_system_slave_dcd; + + /* The endpoint must be destroyed. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_DESTROY_ENDPOINT, endpoint); + + /* Free the endpoint. */ + endpoint -> ux_slave_endpoint_status = UX_UNUSED; + + /* Make sure the endpoint instance is now cleaned up. */ + endpoint -> ux_slave_endpoint_state = 0; + endpoint -> ux_slave_endpoint_next_endpoint = UX_NULL; + endpoint -> ux_slave_endpoint_interface = UX_NULL; + endpoint -> ux_slave_endpoint_device = UX_NULL; + } + + /* It's always from first one (to delete). */ + /* Rebuild the first link. */ + device -> ux_slave_device_first_interface = interface -> ux_slave_interface_next_interface; + + /* The interface is removed from the link, its memory must be cleaned and returned to the pool. */ + interface -> ux_slave_interface_class = UX_NULL; + interface -> ux_slave_interface_class_instance = UX_NULL; + interface -> ux_slave_interface_next_interface = UX_NULL; + interface -> ux_slave_interface_first_endpoint = UX_NULL; + interface -> ux_slave_interface_status = UX_UNUSED; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_get.c new file mode 100644 index 00000000..509dfb43 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_get.c @@ -0,0 +1,150 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_interface_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is deprecated, ux_device_stack_alternate_setting_get */ +/* does the same thing and used by the core stack. */ +/* */ +/* This function gets the current alternate setting for an interface. */ +/* */ +/* INPUT */ +/* */ +/* interface_value Value of the interface */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_interface_get(UINT interface_value) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_TRANSFER *transfer_request; +UX_SLAVE_INTERFACE *interface; +UX_SLAVE_DEVICE *device; +UX_SLAVE_ENDPOINT *endpoint; +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_INTERFACE_GET, interface_value, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Get the control endpoint for the device. */ + endpoint = &device -> ux_slave_device_control_endpoint; + + /* If the device was in the configured state, there may be interfaces + attached to the configuration. */ + if (device -> ux_slave_device_state == UX_DEVICE_CONFIGURED) + { + + /* Get the pointer to the first interface. */ + interface = device -> ux_slave_device_first_interface; + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Parse the interfaces if any. */ + while (interface != UX_NULL) + { +#endif + + /* Check if this is the interface we have an inquiry for. */ + if (interface -> ux_slave_interface_descriptor.bInterfaceNumber == interface_value) + { + + /* Get the pointer to the transfer request associated with the endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Set the value of the alternate setting in the buffer. */ + *transfer_request -> ux_slave_transfer_request_data_pointer = + (UCHAR) interface -> ux_slave_interface_descriptor.bAlternateSetting; + + /* Setup the length appropriately. */ + transfer_request -> ux_slave_transfer_request_requested_length = 1; + + /* Set the phase of the transfer to data out. */ + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT; + + /* Send the descriptor with the appropriate length to the host. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_TRANSFER_REQUEST, transfer_request); + + /* Return the function status code. */ + return(status); + } + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Get the next interface. */ + interface = interface -> ux_slave_interface_next_interface; + } +#endif + + } + + /* The alternate setting value was not found, so we return a stall error. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + + /* Return the status to the caller. */ + return(UX_ERROR); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_set.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_set.c new file mode 100644 index 00000000..96c5970a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_set.c @@ -0,0 +1,326 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_interface_set PORTABLE C */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets one alternate setting of one interface and */ +/* enable all endpoints associated with this alternate setting. */ +/* configuration. */ +/* */ +/* INPUT */ +/* */ +/* device_framework Address in device framework */ +/* for selected alternate setting*/ +/* device_framework_length Length of device framework */ +/* alternate_setting_value Alternate setting */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD dispatch function */ +/* _ux_device_stack_interface_start Start interface */ +/* _ux_utility_descriptor_parse Parse descriptor */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* calculated payload size, */ +/* resulting in version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_interface_set(UCHAR * device_framework, ULONG device_framework_length, + ULONG alternate_setting_value) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_DEVICE *device; +UX_SLAVE_TRANSFER *transfer_request; +UX_SLAVE_INTERFACE *interface; +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 +UX_SLAVE_INTERFACE *interface_link; +ULONG interfaces_pool_number; +#endif +UX_SLAVE_ENDPOINT *endpoint; +UX_SLAVE_ENDPOINT *endpoint_link; +ULONG descriptor_length; +UCHAR descriptor_type; +ULONG endpoints_pool_number; +UINT status; +ULONG max_transfer_length, n_trans; + + UX_PARAMETER_NOT_USED(alternate_setting_value); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_INTERFACE_SET, alternate_setting_value, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Find a free interface in the pool and hook it to the + existing interface. */ + interface = device -> ux_slave_device_interfaces_pool; + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + interfaces_pool_number = device -> ux_slave_device_interfaces_pool_number; + while (interfaces_pool_number != 0) + { + /* Check if this interface is free. */ + if (interface -> ux_slave_interface_status == UX_UNUSED) + break; + + /* Try the next interface. */ + interface++; + + /* Decrement the number of interfaces left to scan in the pool. */ + interfaces_pool_number--; + } + + /* Did we find a free interface ? */ + if (interfaces_pool_number == 0) + return(UX_MEMORY_INSUFFICIENT); +#else + + /* Check if this interface is free. */ + if (interface -> ux_slave_interface_status != UX_UNUSED) + return(UX_MEMORY_INSUFFICIENT); + +#endif + + /* Mark this interface as used now. */ + interface -> ux_slave_interface_status = UX_USED; + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_REGISTER(UX_TRACE_DEVICE_OBJECT_TYPE_INTERFACE, interface, 0, 0, 0) + + /* Parse the descriptor in something more readable. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_interface_descriptor_structure, + UX_INTERFACE_DESCRIPTOR_ENTRIES, + (UCHAR *) &interface -> ux_slave_interface_descriptor); + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + + /* Attach this interface to the end of the interface chain. */ + if (device -> ux_slave_device_first_interface == UX_NULL) + { + + device -> ux_slave_device_first_interface = interface; + } + else + { + /* Multiple interfaces exist, so find the end of the chain. */ + interface_link = device -> ux_slave_device_first_interface; + while (interface_link -> ux_slave_interface_next_interface != UX_NULL) + interface_link = interface_link -> ux_slave_interface_next_interface; + interface_link -> ux_slave_interface_next_interface = interface; + } +#else + + /* It must be very first one. */ + device -> ux_slave_device_first_interface = interface; +#endif + + /* Point beyond the interface descriptor. */ + device_framework_length -= (ULONG) *device_framework; + device_framework += (ULONG) *device_framework; + + /* Parse the device framework and locate endpoint descriptor(s). */ + while (device_framework_length != 0) + { + + /* Get the length of the current descriptor. */ + descriptor_length = (ULONG) *device_framework; + + /* And its type. */ + descriptor_type = *(device_framework + 1); + + /* Check if this is an endpoint descriptor. */ + switch(descriptor_type) + { + + case UX_ENDPOINT_DESCRIPTOR_ITEM: + + /* Find a free endpoint in the pool and hook it to the + existing interface after it's created by DCD. */ + endpoint = device -> ux_slave_device_endpoints_pool; + endpoints_pool_number = device -> ux_slave_device_endpoints_pool_number; + while (endpoints_pool_number != 0) + { + /* Check if this endpoint is free. */ + if (endpoint -> ux_slave_endpoint_status == UX_UNUSED) + { + /* Mark this endpoint as used now. */ + endpoint -> ux_slave_endpoint_status = UX_USED; + break; + } + + /* Try the next endpoint. */ + endpoint++; + + /* Decrement the number of endpoints to scan from the pool. */ + endpoints_pool_number--; + } + + /* Did we find a free endpoint ? */ + if (endpoints_pool_number == 0) + return(UX_MEMORY_INSUFFICIENT); + + /* Parse the descriptor in something more readable. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_endpoint_descriptor_structure, + UX_ENDPOINT_DESCRIPTOR_ENTRIES, + (UCHAR *) &endpoint -> ux_slave_endpoint_descriptor); + + /* Now we create a transfer request to accept transfer on this endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Validate endpoint descriptor wMaxPacketSize. */ + UX_ASSERT(endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize != 0); + + /* Calculate endpoint transfer payload max size. */ + max_transfer_length = + endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize & + UX_MAX_PACKET_SIZE_MASK; + if ((_ux_system_slave -> ux_system_slave_speed == UX_HIGH_SPEED_DEVICE) && + (endpoint -> ux_slave_endpoint_descriptor.bmAttributes & 0x1u)) + { + n_trans = endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize & + UX_MAX_NUMBER_OF_TRANSACTIONS_MASK; + if (n_trans) + { + n_trans >>= UX_MAX_NUMBER_OF_TRANSACTIONS_SHIFT; + n_trans ++; + max_transfer_length *= n_trans; + } + } + + /* Validate max transfer size and save it. */ + UX_ASSERT(max_transfer_length <= UX_SLAVE_REQUEST_DATA_MAX_LENGTH); + transfer_request -> ux_slave_transfer_request_transfer_length = max_transfer_length; + + /* We store the endpoint in the transfer request as well. */ + transfer_request -> ux_slave_transfer_request_endpoint = endpoint; + + /* By default the timeout is infinite on request. */ + transfer_request -> ux_slave_transfer_request_timeout = UX_WAIT_FOREVER; + + /* Attach the interface to the endpoint. */ + endpoint -> ux_slave_endpoint_interface = interface; + + /* Attach the device to the endpoint. */ + endpoint -> ux_slave_endpoint_device = device; + + /* Create the endpoint at the DCD level. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_CREATE_ENDPOINT, (VOID *) endpoint); + + /* Do a sanity check on endpoint creation. */ + if (status != UX_SUCCESS) + { + + /* Error was returned, endpoint cannot be created. */ + endpoint -> ux_slave_endpoint_status = UX_UNUSED; + return(status); + } + + /* Attach this endpoint to the end of the endpoint chain. */ + if (interface -> ux_slave_interface_first_endpoint == UX_NULL) + { + + interface -> ux_slave_interface_first_endpoint = endpoint; + } + else + { + /* Multiple endpoints exist, so find the end of the chain. */ + endpoint_link = interface -> ux_slave_interface_first_endpoint; + while (endpoint_link -> ux_slave_endpoint_next_endpoint != UX_NULL) + endpoint_link = endpoint_link -> ux_slave_endpoint_next_endpoint; + endpoint_link -> ux_slave_endpoint_next_endpoint = endpoint; + } + break; + + case UX_CONFIGURATION_DESCRIPTOR_ITEM: + case UX_INTERFACE_DESCRIPTOR_ITEM: + + /* If the descriptor is a configuration or interface, + we have parsed and mounted all endpoints. + The interface attached to this configuration must be started at the class level. */ + status = _ux_device_stack_interface_start(interface); + + /* Return the status to the caller. */ + return(status); + + default: + break; + } + + /* Adjust what is left of the device framework. */ + device_framework_length -= descriptor_length; + + /* Point to the next descriptor. */ + device_framework += descriptor_length; + } + + /* The interface attached to this configuration must be started at the class + level. */ + status = _ux_device_stack_interface_start(interface); + + /* Return the status to the caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_start.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_start.c new file mode 100644 index 00000000..b3268f20 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_interface_start.c @@ -0,0 +1,132 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_interface_start PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function starts an interface associated with the enabled */ +/* configuration. */ +/* */ +/* INPUT */ +/* */ +/* interface Pointer to interface */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_class_entry_function) Device class entry function */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_interface_start(UX_SLAVE_INTERFACE *interface) +{ + +UX_SLAVE_DEVICE *device; +UX_SLAVE_CLASS *class; +UINT status; +UX_SLAVE_CLASS_COMMAND class_command; + + + /* Get the class for the interface. */ + class = _ux_system_slave -> ux_system_slave_interface_class_array[interface -> ux_slave_interface_descriptor.bInterfaceNumber]; + + /* Check if class driver is available. */ + if (class == UX_NULL) + + /* There is no class driver supported. */ + return (UX_NO_CLASS_MATCH); + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Build all the fields of the Class Command. */ + class_command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_QUERY; + class_command.ux_slave_class_command_interface = (VOID *)interface; + class_command.ux_slave_class_command_class = interface -> ux_slave_interface_descriptor.bInterfaceClass; + class_command.ux_slave_class_command_subclass = interface -> ux_slave_interface_descriptor.bInterfaceSubClass; + class_command.ux_slave_class_command_protocol = interface -> ux_slave_interface_descriptor.bInterfaceProtocol; + class_command.ux_slave_class_command_vid = device -> ux_slave_device_descriptor.idVendor; + class_command.ux_slave_class_command_pid = device -> ux_slave_device_descriptor.idProduct; + + /* We can now memorize the interface pointer associated with this class. */ + class -> ux_slave_class_interface = interface; + + /* We have found a potential candidate. Call this registered class entry function. */ + status = class -> ux_slave_class_entry_function(&class_command); + + /* The status tells us if the registered class wants to own this class. */ + if (status == UX_SUCCESS) + { + + /* Store the class container. */ + class_command.ux_slave_class_command_class_ptr = class; + + /* Store the command. */ + class_command.ux_slave_class_command_request = UX_SLAVE_CLASS_COMMAND_ACTIVATE; + + /* Activate the class. */ + status = class -> ux_slave_class_entry_function(&class_command); + + /* If the class was successfully activated, set the class for the interface. */ + if(status == UX_SUCCESS) + interface -> ux_slave_interface_class = class; + + return(status); + } + + /* There is no driver who want to own this class! */ + return(UX_NO_CLASS_MATCH); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_microsoft_extension_register.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_microsoft_extension_register.c new file mode 100644 index 00000000..585ce5e5 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_microsoft_extension_register.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_microsoft_extension_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers the Microsoft extensions to support vendor */ +/* commands before the device is configured. */ +/* */ +/* INPUT */ +/* */ +/* vendor_command Vendor Command. */ +/* application_callback Application Callback */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_microsoft_extension_register(ULONG vendor_request, + UINT (*vendor_request_function)(ULONG, ULONG, ULONG, ULONG, UCHAR *, ULONG *)) +{ + + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_MICROSOFT_EXTENSION_REGISTER, 0, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Store the vendor command. */ + _ux_system_slave -> ux_system_slave_device_vendor_request = vendor_request; + _ux_system_slave -> ux_system_slave_device_vendor_request_function = vendor_request_function; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_set_feature.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_set_feature.c new file mode 100644 index 00000000..37c3bf21 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_set_feature.c @@ -0,0 +1,203 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_set_feature PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets a specific feature (Device, Interface, */ +/* Endpoint ....). */ +/* */ +/* INPUT */ +/* */ +/* request_type Request type */ +/* request_value Request value */ +/* request_index Request index */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) DCD controller function */ +/* */ +/* CALLED BY */ +/* */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, stalled on not */ +/* supported device requests, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_set_feature(ULONG request_type, ULONG request_value, ULONG request_index) +{ + +UX_SLAVE_DCD *dcd; +UX_SLAVE_DEVICE *device; +UX_SLAVE_INTERFACE *interface; +UX_SLAVE_ENDPOINT *endpoint; +UX_SLAVE_ENDPOINT *endpoint_target; + + UX_PARAMETER_NOT_USED(request_value); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_SET_FEATURE, request_value, request_index, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Get the control endpoint for the device. */ + endpoint = &device -> ux_slave_device_control_endpoint; + + /* The feature can be for either the device or the endpoint. */ + switch (request_type & UX_REQUEST_TARGET) + { + + case UX_REQUEST_TARGET_DEVICE: + + /* Check if we have a DEVICE_REMOTE_WAKEUP Feature. */ + if (request_value == UX_REQUEST_FEATURE_DEVICE_REMOTE_WAKEUP) + { + + /* Check if we have the capability. */ + if (_ux_system_slave -> ux_system_slave_remote_wakeup_capability) + { + + /* Enable the feature. */ + _ux_system_slave -> ux_system_slave_remote_wakeup_enabled = UX_TRUE; + + /* OK. */ + return (UX_SUCCESS); + } + else + + /* Protocol error. */ + return (UX_FUNCTION_NOT_SUPPORTED); + } + +#ifdef UX_OTG_SUPPORT + /* Check if we have a A_HNP_SUPPORT Feature. This is set when the Host is HNP capable. */ + if (request_value == UX_OTG_FEATURE_A_HNP_SUPPORT) + { + + /* Store the A_HNP_SUPPORT flag. */ + _ux_system_otg -> ux_system_otg_slave_set_feature_flag |= UX_OTG_FEATURE_A_HNP_SUPPORT; + + /* OK. */ + return(UX_SUCCESS); + } + + /* Check if the host asks us to perform HNP. If also we become the host. */ + if (request_value == UX_OTG_FEATURE_B_HNP_ENABLE) + { + + /* The ISR will pick up the suspend event and check if we need to become IDLE or HOST. */ + _ux_system_otg -> ux_system_otg_slave_set_feature_flag |= UX_OTG_FEATURE_B_HNP_ENABLE; + + /* OK. */ + return(UX_SUCCESS); + } +#endif + + /* Request value not supported. */ + return(UX_FUNCTION_NOT_SUPPORTED); + + case UX_REQUEST_TARGET_ENDPOINT: + + /* The only set feature for endpoint is ENDPOINT_STALL. This forces + the endpoint to the stall situation. + We need to find the endpoint through the interface(s). */ + interface = device -> ux_slave_device_first_interface; + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + while (interface != UX_NULL) + { +#endif + /* Get the first endpoint for this interface. */ + endpoint_target = interface -> ux_slave_interface_first_endpoint; + + /* Parse all the endpoints. */ + while (endpoint_target != UX_NULL) + { + + /* Check the endpoint index. */ + if (endpoint_target -> ux_slave_endpoint_descriptor.bEndpointAddress == request_index) + { + + /* Stall the endpoint. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint_target); + + /* Return the function status. */ + return(UX_SUCCESS); + } + + /* Next endpoint. */ + endpoint_target = endpoint_target -> ux_slave_endpoint_next_endpoint; + } + +#if !defined(UX_DEVICE_INITIALIZE_FRAMEWORK_SCAN_DISABLE) || UX_MAX_DEVICE_INTERFACES > 1 + /* Next interface. */ + interface = interface -> ux_slave_interface_next_interface; + } +#endif + + /* We get here when the endpoint is wrong. Should not happen though. */ + /* Intentionally fall through into the default case. */ + /* fall through */ + default: + + /* We stall the command. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_STALL_ENDPOINT, endpoint); + + /* No more work to do here. The command failed but the upper layer does not depend on it. */ + return(UX_SUCCESS); + } +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_abort.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_abort.c new file mode 100644 index 00000000..a7c57cf8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_abort.c @@ -0,0 +1,135 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_transfer_abort PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function aborts a pending transfer request that has been */ +/* previously submitted. This function only cancels a specific */ +/* transfer request. */ +/* */ +/* The call back to the function will have the */ +/* UX_TRANSFER_STATUS_ABORT status */ +/* */ +/* INPUT */ +/* */ +/* transfer_request Pointer to transfer request */ +/* completion_code Completion code */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_put Put semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* assigned aborting code, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_transfer_abort(UX_SLAVE_TRANSFER *transfer_request, ULONG completion_code) +{ + +UX_INTERRUPT_SAVE_AREA + +UX_SLAVE_DCD *dcd; + + UX_PARAMETER_NOT_USED(completion_code); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_TRANSFER_ABORT, transfer_request, completion_code, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Sets the completion code due to bus reset. */ + transfer_request -> ux_slave_transfer_request_completion_code = completion_code; + + /* Ensure we're not preempted by the transfer completion ISR. */ + UX_DISABLE + + /* It's possible the transfer already completed. Ensure it hasn't before doing the abort. */ + if (transfer_request -> ux_slave_transfer_request_status == UX_TRANSFER_STATUS_PENDING) + { + + /* Call the DCD if necessary for cleaning up the pending transfer. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_TRANSFER_ABORT, (VOID *) transfer_request); + + /* Restore interrupts. Note that the transfer request should not be modified now. */ + UX_RESTORE + + /* We need to set the completion code for the transfer to aborted. Note + that the transfer request function cannot simultaneously modify this + because if the transfer was pending, then the transfer's thread is + currently waiting for it to complete. */ + transfer_request -> ux_slave_transfer_request_status = UX_TRANSFER_STATUS_ABORT; + + /* Wake up the device driver who is waiting on the semaphore. */ + _ux_device_semaphore_put(&transfer_request -> ux_slave_transfer_request_semaphore); + } + else + { + + /* Restore interrupts. */ + UX_RESTORE + } + + /* This function never fails. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_all_request_abort.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_all_request_abort.c new file mode 100644 index 00000000..37ea1a81 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_all_request_abort.c @@ -0,0 +1,91 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_transfer_all_request_abort PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function cancels all the transfer requests attached to an */ +/* endpoint. The endpoint is not reset and its toggle state is left */ +/* the same. */ +/* */ +/* INPUT */ +/* */ +/* transfer_request Pointer to transfer request */ +/* completion_code Completion code */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_abort Transfer abort */ +/* */ +/* CALLED BY */ +/* */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_transfer_all_request_abort(UX_SLAVE_ENDPOINT *endpoint, ULONG completion_code) +{ + +UX_SLAVE_TRANSFER *transfer_request; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_TRANSFER_ALL_REQUEST_ABORT, endpoint, completion_code, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the transfer request for this endpoint. */ + transfer_request = &endpoint -> ux_slave_endpoint_transfer_request; + + /* Abort this request. */ + _ux_device_stack_transfer_abort(transfer_request, completion_code); + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_request.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_request.c new file mode 100644 index 00000000..00fdc150 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_transfer_request.c @@ -0,0 +1,205 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_transfer_request PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a USB transaction. On entry the */ +/* transfer request gives the endpoint pipe selected for this */ +/* transaction and the parameters associated with the transfer */ +/* (data payload, length of transaction). */ +/* */ +/* INPUT */ +/* */ +/* transfer_request Pointer to transfer request */ +/* slave_length Length returned by host */ +/* host_length Length asked by host */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) Slave DCD dispatch function */ +/* _ux_utility_delay_ms Delay ms */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_transfer_request(UX_SLAVE_TRANSFER *transfer_request, + ULONG slave_length, + ULONG host_length) +{ +#if defined(UX_DEVICE_STANDALONE) +UINT status; + + /* Start a transfer request without waiting it end. */ + UX_SLAVE_TRANSFER_STATE_RESET(transfer_request); + status = _ux_device_stack_transfer_run(transfer_request, slave_length, host_length); + if (status == UX_STATE_LOCK) + return(UX_BUSY); + if (status < UX_STATE_NEXT) + return(transfer_request -> ux_slave_transfer_request_completion_code); + + /* Started/done, things will be done in BG */ + return(UX_SUCCESS); +#else +UX_INTERRUPT_SAVE_AREA + +UX_SLAVE_DCD *dcd; +UINT status; +UX_SLAVE_ENDPOINT *endpoint; +ULONG device_state; + + + /* Do we have to skip this transfer? */ + if (transfer_request -> ux_slave_transfer_request_status_phase_ignore == UX_TRUE) + return(UX_SUCCESS); + + /* Disable interrupts to prevent the disconnection ISR from preempting us + while we check the device state and set the transfer status. */ + UX_DISABLE + + /* Get the device state. */ + device_state = _ux_system_slave -> ux_system_slave_device.ux_slave_device_state; + + /* We can only transfer when the device is ATTACHED, ADDRESSED OR CONFIGURED. */ + if ((device_state == UX_DEVICE_ATTACHED) || (device_state == UX_DEVICE_ADDRESSED) + || (device_state == UX_DEVICE_CONFIGURED)) + + /* Set the transfer to pending. */ + transfer_request -> ux_slave_transfer_request_status = UX_TRANSFER_STATUS_PENDING; + + else + { + + /* The device is in an invalid state. Restore interrupts and return error. */ + UX_RESTORE + return(UX_TRANSFER_NOT_READY); + } + + /* Restore interrupts. */ + UX_RESTORE + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_TRANSFER_REQUEST, transfer_request, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the endpoint associated with this transaction. */ + endpoint = transfer_request -> ux_slave_transfer_request_endpoint; + + /* If the endpoint is non Control, check the endpoint direction and set the data phase direction. */ + if ((endpoint -> ux_slave_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE) != UX_CONTROL_ENDPOINT) + { + + /* Check if the endpoint is STALLED. In this case, we must refuse the transaction until the endpoint + has been reset by the host. */ + while (endpoint -> ux_slave_endpoint_state == UX_ENDPOINT_HALTED) + + /* Wait for 100ms for endpoint to be reset by a CLEAR_FEATURE command. */ + _ux_utility_delay_ms(100); + + /* Isolate the direction from the endpoint address. */ + if ((endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress & UX_ENDPOINT_DIRECTION) == UX_ENDPOINT_IN) + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT; + else + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_IN; + } + + /* See if we need to force a zero length packet at the end of the transfer. + This happens on a DATA IN and when the host requested length is not met + and the last packet is on a boundary. If slave_length is zero, then it is + a explicit ZLP request, no need to force ZLP. */ + if ((transfer_request -> ux_slave_transfer_request_phase == UX_TRANSFER_PHASE_DATA_OUT) && + (slave_length != 0) && (host_length != slave_length) && + (slave_length % endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize) == 0) + { + + /* If so force Zero Length Packet. */ + transfer_request -> ux_slave_transfer_request_force_zlp = UX_TRUE; + } + else + { + + /* Condition is not met, do not force a Zero Length Packet. */ + transfer_request -> ux_slave_transfer_request_force_zlp = UX_FALSE; + } + + /* Reset the number of bytes sent/received. */ + transfer_request -> ux_slave_transfer_request_actual_length = 0; + + /* Determine how many bytes to send in this transaction. We keep track of the original + length and have a working length. */ + transfer_request -> ux_slave_transfer_request_requested_length = slave_length; + transfer_request -> ux_slave_transfer_request_in_transfer_length = slave_length; + + /* Save the buffer pointer. */ + transfer_request -> ux_slave_transfer_request_current_data_pointer = + transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Call the DCD driver transfer function. */ + status = dcd -> ux_slave_dcd_function(dcd, UX_DCD_TRANSFER_REQUEST, transfer_request); + + /* And return the status. */ + return(status); + +#endif +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_uninitialize.c b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_uninitialize.c new file mode 100644 index 00000000..6b97b271 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_device_stack_uninitialize.c @@ -0,0 +1,132 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_stack.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_stack_uninitialize PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function uninitializes the generic portion of the device side */ +/* of USBX. */ +/* */ +/* INPUT */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_free Free */ +/* _ux_utility_semaphore_delete Delete semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed uninitialize in case */ +/* there is no EP except EP0, */ +/* resulting in version 6.1.6 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_stack_uninitialize(VOID) +{ +UX_SLAVE_DEVICE *device; +UX_SLAVE_ENDPOINT *endpoints_pool; +UX_SLAVE_TRANSFER *transfer_request; +ULONG endpoints_found; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_INITIALIZE, 0, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Free class memory. */ + _ux_utility_memory_free(_ux_system_slave -> ux_system_slave_class_array); + + /* Allocate some memory for the Control Endpoint. First get the address of the transfer request for the + control endpoint. */ + transfer_request = &device -> ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request; + + /* Free memory for the control endpoint buffer. */ + _ux_utility_memory_free(transfer_request -> ux_slave_transfer_request_data_pointer); + + /* Get the number of endpoints found in the device framework. */ + endpoints_found = device -> ux_slave_device_endpoints_pool_number; + + /* Get the endpoint pool address in the device container. */ + endpoints_pool = device -> ux_slave_device_endpoints_pool; + + /* Parse all endpoints and fee memory and semaphore. */ + while (endpoints_found-- != 0) + { + /* Free the memory for endpoint data pointer. */ + _ux_utility_memory_free(endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer); + + /* Remove the TX semaphore for the endpoint. */ + _ux_device_semaphore_delete(&endpoints_pool -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_semaphore); + + /* Next endpoint. */ + endpoints_pool++; + } + + /* Free the endpoint pool address in the device container. */ + if (device -> ux_slave_device_endpoints_pool) + _ux_utility_memory_free(device -> ux_slave_device_endpoints_pool); + + /* Free memory for interface pool. */ + _ux_utility_memory_free(device -> ux_slave_device_interfaces_pool); + + /* Return successful completion. */ + return(UX_SUCCESS); +} + + + + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_check.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_check.c new file mode 100644 index 00000000..c2d75361 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_check.c @@ -0,0 +1,275 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +#if UX_MAX_DEVICES > 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_bandwidth_check PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will check if there is enough bandwidth on the USB */ +/* for the specified endpoint. The bandwidth requirement is calculated */ +/* by the MaxPacketSize field of endpoint and the speed of the */ +/* endpoint. If the device is on a 1.1 bus or it is a 1.1 device */ +/* behind a 2.0 hub on a 2.0 bus, the device bandwidth must be */ +/* multiplied by 8 on the 1.1 segment. */ +/* */ +/* This algorithm takes into account both TT bandwidth and HCD */ +/* bandwidth. The TTs are attached to the device structure and not */ +/* the hub structure in order to make the stack agnostic of the hub */ +/* class. */ +/* */ +/* INPUT */ +/* */ +/* HCD Pointer to HCD */ +/* endpoint Pointer to endpoint */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_bandwidth_check(UX_HCD *hcd, UX_ENDPOINT *endpoint) +{ + +UX_DEVICE *device; +UX_DEVICE *parent_device; +USHORT hcd_bandwidth_claimed; +USHORT max_packet_size; +LONG packet_size; +USHORT tt_bandwidth_claimed = 0; +ULONG port_index; +ULONG port_map; +ULONG tt_index; +const UCHAR overheads[4][3] = { +/* LS FS HS */ + {63, 45, 173}, /* Control */ + { 0, 9, 38}, /* Isochronous */ + { 0, 13, 55}, /* Bulk */ + {19, 13, 55} /* Interrupt */ +}; + + /* Get the pointer to the device. */ + device = endpoint -> ux_endpoint_device; + + /* Calculate the bandwidth. From USB spec. + * + * The frame unit consumed per byte is like follow: + * Bytes/FrameUnit FrameUnit/byte FrameUnit/byte + * (Overhead included) (HS baseline) (FS baseline) + * Low Speed 187.5 40 8 + * Full Speed 1500 5 1 + * High Speed 7500 1 1/5 + * + * The overhead is like follow: + * Control Isochronous Bulk Interrupt + * bmAttribute (0) (1) (2) (3) + * Low Speed 63 -- -- 19 + * Full Speed 45 9 13 13 + * High Speed 173 38 55 55 + * + * Worst case bit stuffing is calculated as 1.1667 (7/6) times the raw time. + */ + + /* Get maximum packet size. */ + max_packet_size = endpoint -> ux_endpoint_descriptor.wMaxPacketSize & UX_MAX_PACKET_SIZE_MASK; + + /* Rough time for possible Bit Stuffing. */ + packet_size = (max_packet_size * 7 + 5) / 6; + + /* Add overhead. */ + packet_size += overheads[endpoint -> ux_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE][device -> ux_device_speed]; + max_packet_size = (USHORT)packet_size; + + /* Check for high-speed endpoint. */ + if (device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) + { + + /* Get number of transactions. */ + max_packet_size = (USHORT)(max_packet_size * + (((endpoint -> ux_endpoint_descriptor.wMaxPacketSize & UX_MAX_NUMBER_OF_TRANSACTIONS_MASK) >> + UX_MAX_NUMBER_OF_TRANSACTIONS_SHIFT) + 1)); + } + + /* Calculate the bandwidth claimed by this endpoint for the main bus. */ + if (hcd -> ux_hcd_version != 0x200) + { + + if (device -> ux_device_speed == UX_LOW_SPEED_DEVICE) + /* Low speed transfer takes 40x more units than high speed. */ + hcd_bandwidth_claimed = (USHORT)(max_packet_size * 8 * 5); + else + { + + if (device -> ux_device_speed == UX_FULL_SPEED_DEVICE) + /* Full speed transfer takes 5x more units than high speed. */ + hcd_bandwidth_claimed = (USHORT)(max_packet_size * 5); + else + /* Use high speed timing as base for bus bandwidth calculation. */ + hcd_bandwidth_claimed = (USHORT)max_packet_size; + } + } + else + { + + hcd_bandwidth_claimed = (USHORT)max_packet_size; + if (device -> ux_device_speed == UX_LOW_SPEED_DEVICE) + /* Low speed transfer takes 8x more units than full speed. */ + tt_bandwidth_claimed = (USHORT)(max_packet_size * 8); + else + /* Use full speed timing as base for TT bandwidth calculation. */ + tt_bandwidth_claimed = (USHORT)max_packet_size; + } + + /* Do we have enough on the bus for this new endpoint? */ + if (hcd -> ux_hcd_available_bandwidth < hcd_bandwidth_claimed) + { + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_NO_BANDWIDTH_AVAILABLE, endpoint, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_NO_BANDWIDTH_AVAILABLE); + + return(UX_NO_BANDWIDTH_AVAILABLE); + } + + /* We need to take care of the case where the endpoint belongs to a USB 1.1 + device that sits behind a 2.0 hub. We ignore cases where the device + is either high speed or the bus is 1.1. */ + if ((device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) || (hcd -> ux_hcd_version != 0x200)) + { + + /* The device is high speed, therefore no need for TT. */ + return(UX_SUCCESS); + } + + /* We have a 1.1 device, check if the parent is a 2.0 hub. */ + parent_device = device -> ux_device_parent; + if (parent_device == UX_NULL) + { + + /* We are at the root, this controller must support 1.1 then! */ + return(UX_SUCCESS); + } + + /* We get here when the parent is a hub. The problem occurs when the hub is itself + connected to a chain of hubs. We need to find the first 2.0 hub parent to this + chain to check the TT. We need to remember the port on which the first 1.1 + device is hooked to. */ + port_index = device -> ux_device_port_location - 1; + + /* Scan the chain of hubs upward. */ + while (parent_device != UX_NULL) + { + + /* Determine if the device is high speed. */ + if (parent_device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) + { + + /* The device is a high speed hub, find the TT that manages the port. + The first 1.1 device is connected to. First we calculate the port + mapping bit. */ + port_map = (ULONG)(1 << port_index); + + /* Parse all the TTs attached to the hub. */ + for (tt_index = 0; tt_index < UX_MAX_TT; tt_index++) + { + + /* Check if this TT owns the port where the device is attached. */ + if ((parent_device -> ux_device_hub_tt[tt_index].ux_hub_tt_port_mapping & port_map) != 0) + { + + /* We have found the port, check if the tt can give us the bandwidth + we want to claim. */ + if (parent_device -> ux_device_hub_tt[tt_index].ux_hub_tt_max_bandwidth < tt_bandwidth_claimed) + { + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_NO_BANDWIDTH_AVAILABLE, endpoint, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_NO_BANDWIDTH_AVAILABLE); + + return(UX_NO_BANDWIDTH_AVAILABLE); + } + + else + return(UX_SUCCESS); + } + } + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_NO_BANDWIDTH_AVAILABLE, endpoint, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_NO_BANDWIDTH_AVAILABLE); + + /* We should never get here !!!!! */ + return(UX_NO_BANDWIDTH_AVAILABLE); + } + + /* We now remember where this hub is located on the parent. */ + port_index = parent_device -> ux_device_port_location - 1; + + /* We go up one level in the hub chain. */ + parent_device = parent_device -> ux_device_parent; + } + + /* We get here when we have not found a 2.0 hub in the list and we got to the root port. */ + return(UX_SUCCESS); +} +#endif /* #if UX_MAX_DEVICES > 1 */ diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_claim.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_claim.c new file mode 100644 index 00000000..01d2b2ff --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_claim.c @@ -0,0 +1,250 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +#if UX_MAX_DEVICES > 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_bandwidth_claim PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will reserve bandwidth for a periodic endpoint. The */ +/* bandwidth requirement is calculated by the MaxPacketSize field of */ +/* endpoint and the speed of the endpoint. If the device is on a 1.1 */ +/* bus or it is a 1.1 device behind a 2.0 hub on a 2.0 bus, the device */ +/* bandwidth must be multiplied by 8 on the 1.1 segment. */ +/* */ +/* This algorithm takes into account both TT bandwidth and HCD */ +/* bandwidth. The TTs are attached to the device structure and not */ +/* the hub structure in order to make the stack agnostic of the hub */ +/* class. */ +/* */ +/* INPUT */ +/* */ +/* HCD Pointer to HCD */ +/* endpoint Pointer to endpoint */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_bandwidth_claim(UX_HCD *hcd, UX_ENDPOINT *endpoint) +{ + +UX_DEVICE *device; +UX_DEVICE *parent_device; +USHORT hcd_bandwidth_claimed; +USHORT max_packet_size; +LONG packet_size; +USHORT tt_bandwidth_claimed = 0; +ULONG port_index; +ULONG port_map; +ULONG tt_index; +const UCHAR overheads[4][3] = { +/* LS FS HS */ + {63, 45, 173}, /* Control */ + { 0, 9, 38}, /* Isochronous */ + { 0, 13, 55}, /* Bulk */ + {19, 13, 55} /* Interrupt */ +}; + + /* Get the pointer to the device. */ + device = endpoint -> ux_endpoint_device; + + /* Calculate the bandwidth. From USB spec. + * + * The frame unit consumed per byte is like follow: + * Bytes/FrameUnit FrameUnit/byte FrameUnit/byte + * (Overhead included) (HS baseline) (FS baseline) + * Low Speed 187.5 40 8 + * Full Speed 1500 5 1 + * High Speed 7500 1 1/5 + * + * The overhead is like follow: + * Control Isochronous Bulk Interrupt + * bmAttribute (0) (1) (2) (3) + * Low Speed 63 -- -- 19 + * Full Speed 45 9 13 13 + * High Speed 173 38 55 55 + * + * Worst case bit stuffing is calculated as 1.1667 (7/6) times the raw time. + */ + + /* Get maximum packet size. */ + max_packet_size = endpoint -> ux_endpoint_descriptor.wMaxPacketSize & UX_MAX_PACKET_SIZE_MASK; + + /* Rough time for possible Bit Stuffing. */ + packet_size = (max_packet_size * 7 + 5) / 6; + + /* Add overhead. */ + packet_size += overheads[endpoint -> ux_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE][device -> ux_device_speed]; + max_packet_size = (USHORT)packet_size; + + /* Check for high-speed endpoint. */ + if (device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) + { + + /* Get number of transactions. */ + max_packet_size = (USHORT)(max_packet_size * + (((endpoint -> ux_endpoint_descriptor.wMaxPacketSize & UX_MAX_NUMBER_OF_TRANSACTIONS_MASK) >> + UX_MAX_NUMBER_OF_TRANSACTIONS_SHIFT) + 1)); + } + + /* Calculate the bandwidth claimed by this endpoint for the main bus. */ + if (hcd -> ux_hcd_version != 0x200) + { + + if (device -> ux_device_speed == UX_LOW_SPEED_DEVICE) + /* Low speed transfer takes 40x more units than high speed. */ + hcd_bandwidth_claimed = (USHORT)(max_packet_size * 8 * 5); + else + { + + if (device -> ux_device_speed == UX_FULL_SPEED_DEVICE) + /* Full speed transfer takes 5x more units than high speed. */ + hcd_bandwidth_claimed = (USHORT)(max_packet_size * 5); + else + /* Use high speed timing as base for bus bandwidth calculation. */ + hcd_bandwidth_claimed = (USHORT)max_packet_size; + } + } + else + { + + hcd_bandwidth_claimed = (USHORT)max_packet_size; + if (device -> ux_device_speed == UX_LOW_SPEED_DEVICE) + /* Low speed transfer takes 8x more units than full speed. */ + tt_bandwidth_claimed = (USHORT)(max_packet_size * 8); + else + /* Use full speed timing as base for TT bandwidth calculation. */ + tt_bandwidth_claimed = (USHORT)max_packet_size; + } + + /* Allocate the HCD bandwidth, since it's already checked by _bandwidth_check. */ + hcd -> ux_hcd_available_bandwidth -= hcd_bandwidth_claimed; + + /* We need to take care of the case where the endpoint belongs to a USB 1.1 + device that sits behind a 2.0 hub. We ignore cases where the device + is either high speed or the bus is 1.1. */ + if ((device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) || (hcd -> ux_hcd_version != 0x200)) + { + + /* The device is high speed, therefore no need for TT. */ + return; + } + + /* We have a 1.1 device, check if the parent is a 2.0 hub. */ + parent_device = device -> ux_device_parent; + if (parent_device == UX_NULL) + { + + /* We are at the root, must be a 1.1 controller then! */ + return; + } + + /* We get here when the parent is a hub. The problem occurs when the hub is + itself connected to a chain of hubs. We need to find the first 2.0 hub + parent to this chain to check the TT. We need to remember the port on + which the first 1.1 device is hooked to. */ + port_index = device -> ux_device_port_location - 1; + + /* Scan the chain of hubs upward. */ + while (parent_device != UX_NULL) + { + + /* Is the device high speed? */ + if (parent_device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) + { + + /* The device is a high speed hub, find the TT that manages the port. + The first 1.1 device is connected to. First we calculate the port + mapping bit. */ + port_map = (ULONG)(1 << port_index); + + /* Parse all the TTs attached to the hub. + Since we confirmed exist of TT in previous _check, + just do while loop here. + */ + tt_index = 0; + while(1) + { + /* Check if this TT owns the port where the device is attached. */ + if ((parent_device -> ux_device_hub_tt[tt_index].ux_hub_tt_port_mapping & port_map) != 0) + { + + /* We have found the port, check if the tt can give us the bandwidth + we want to claim. */ + parent_device -> ux_device_hub_tt[tt_index].ux_hub_tt_max_bandwidth -= tt_bandwidth_claimed; + return; + } + + /* Try next index. */ + tt_index ++; + } + } + + /* We now remember where this hub is located on the parent. */ + port_index = parent_device -> ux_device_port_location - 1; + + /* We go up one level in the hub chain. */ + parent_device = parent_device -> ux_device_parent; + } + + /* We get here when we have not found a 2.0 hub in the list and we got + to the root port. */ + return; +} +#endif /* #if UX_MAX_DEVICES > 1 */ diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_release.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_release.c new file mode 100644 index 00000000..35c279a4 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_bandwidth_release.c @@ -0,0 +1,245 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +#if UX_MAX_DEVICES > 1 +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_bandwidth_release PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will release bandwidth for a periodic endpoint. The */ +/* bandwidth requirement is calculated by the MaxPacketSize field of */ +/* endpoint and the speed of the endpoint. If the device is on a 1.1 */ +/* bus or it is a 1.1 device behind a 2.0 hub on a 2.0 bus, the device */ +/* bandwidth must be multiplied by 8 on the 1.1 segment. */ +/* */ +/* This algorithm takes into account both TT bandwidth and HCD */ +/* bandwidth. The TTs are attached to the device structure and not the */ +/* hub structure in order to make the stack agnostic of the hub class. */ +/* */ +/* INPUT */ +/* */ +/* HCD Pointer to HCD */ +/* endpoint Pointer to endpoint */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_bandwidth_release(UX_HCD *hcd, UX_ENDPOINT *endpoint) +{ + +UX_DEVICE *device; +UX_DEVICE *parent_device; +USHORT hcd_bandwidth_claimed; +USHORT max_packet_size; +LONG packet_size; +USHORT tt_bandwidth_claimed = 0; +ULONG port_index; +ULONG port_map; +ULONG tt_index; +const UCHAR overheads[4][3] = { +/* LS FS HS */ + {63, 45, 173}, /* Control */ + { 0, 9, 38}, /* Isochronous */ + { 0, 13, 55}, /* Bulk */ + {19, 13, 55} /* Interrupt */ +}; + + /* Get the pointer to the device. */ + device = endpoint -> ux_endpoint_device; + + /* Calculate the bandwidth. From USB spec. + * + * The frame unit consumed per byte is like follow: + * Bytes/FrameUnit FrameUnit/byte FrameUnit/byte + * (Overhead included) (HS baseline) (FS baseline) + * Low Speed 187.5 40 8 + * Full Speed 1500 5 1 + * High Speed 7500 1 1/5 + * + * The overhead is like follow: + * Control Isochronous Bulk Interrupt + * bmAttribute (0) (1) (2) (3) + * Low Speed 63 -- -- 19 + * Full Speed 45 9 13 13 + * High Speed 173 38 55 55 + * + * Worst case bit stuffing is calculated as 1.1667 (7/6) times the raw time. + */ + + /* Get maximum packet size. */ + max_packet_size = endpoint -> ux_endpoint_descriptor.wMaxPacketSize & UX_MAX_PACKET_SIZE_MASK; + + /* Rough time for possible Bit Stuffing. */ + packet_size = (max_packet_size * 7 + 5) / 6; + + /* Add overhead. */ + packet_size += overheads[endpoint -> ux_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE][device -> ux_device_speed]; + max_packet_size = (USHORT)packet_size; + + /* Check for high-speed endpoint. */ + if (device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) + { + + /* Get number of transactions. */ + max_packet_size = (USHORT)(max_packet_size * + (((endpoint -> ux_endpoint_descriptor.wMaxPacketSize & UX_MAX_NUMBER_OF_TRANSACTIONS_MASK) >> + UX_MAX_NUMBER_OF_TRANSACTIONS_SHIFT) + 1)); + } + + /* Calculate the bandwidth claimed by this endpoint for the main bus. */ + if (hcd -> ux_hcd_version != 0x200) + { + + if (device -> ux_device_speed == UX_LOW_SPEED_DEVICE) + /* Low speed transfer takes 40x more units than high speed. */ + hcd_bandwidth_claimed = (USHORT)(max_packet_size * 8 * 5); + else + { + + if (device -> ux_device_speed == UX_FULL_SPEED_DEVICE) + /* Full speed transfer takes 5x more units than high speed. */ + hcd_bandwidth_claimed = (USHORT)(max_packet_size * 5); + else + /* Use high speed timing as base for bus bandwidth calculation. */ + hcd_bandwidth_claimed = (USHORT)max_packet_size; + } + } + else + { + + hcd_bandwidth_claimed = (USHORT)max_packet_size; + if (device -> ux_device_speed == UX_LOW_SPEED_DEVICE) + /* Low speed transfer takes 8x more units than full speed. */ + tt_bandwidth_claimed = (USHORT)(max_packet_size * 8); + else + /* Use full speed timing as base for TT bandwidth calculation. */ + tt_bandwidth_claimed = (USHORT)max_packet_size; + } + + /* Free the HCD bandwidth. */ + hcd -> ux_hcd_available_bandwidth += hcd_bandwidth_claimed; + + /* We need to take care of the case where the endpoint belongs to a USB 1.1 + device that sits behind a 2.0 hub. We ignore cases where the device + is either high speed or the bus is 1.1. */ + if ((device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) || (hcd -> ux_hcd_version != 0x200)) + { + + /* The device is high speed, therefore no need for TT. */ + return; + } + + /* We have a 1.1 device, check if the parent is a 2.0 hub. */ + parent_device = device -> ux_device_parent; + if (parent_device == UX_NULL) + { + + /* We are at the root, must be a 1.1 controller then! */ + return; + } + + /* We get here when the parent is a hub. The problem occurs when the hub is itself + connected to a chain of hubs. We need to find the first 2.0 hub parent to this chain + to check the TT. We need to remember the port on which the first 1.1 device is + hooked to. */ + port_index = device -> ux_device_port_location - 1; + + /* Scan the chain of hubs upward. */ + while (parent_device != UX_NULL) + { + + /* Check for a high speed device. */ + if (parent_device -> ux_device_speed == UX_HIGH_SPEED_DEVICE) + { + + /* The device is a high speed hub, find the TT that manages the port. + The first 1.1 device is connected to. First we calculate the port mapping bit. */ + port_map = (ULONG)(1 << port_index); + + /* Parse all the TTs attached to the hub. */ + for (tt_index = 0; tt_index < UX_MAX_TT; tt_index++) + { + + /* Check if this TT owns the port where the device is attached. */ + if ((parent_device -> ux_device_hub_tt[tt_index].ux_hub_tt_port_mapping & port_map) != 0) + { + + /* We have found the port, check if the tt can give us the bandwidth + we want to claim. */ + parent_device -> ux_device_hub_tt[tt_index].ux_hub_tt_max_bandwidth += tt_bandwidth_claimed; + return; + } + } + + /* We should never get here!!!!! */ + return; + } + + /* We now remember where this hub is located on the parent. */ + port_index = parent_device -> ux_device_port_location - 1; + + /* We go up one level in the hub chain. */ + parent_device = parent_device -> ux_device_parent; + } + + /* We get here when we have not found a 2.0 hub in the list and we got + to the root port. */ + return; +} +#endif /* #if UX_MAX_DEVICES > 1 */ diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_call.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_call.c new file mode 100644 index 00000000..02f87257 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_call.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_call PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will call all the registered classes to the USBX */ +/* stack. Each class will have the possibility to own the device or */ +/* one of the interfaces of a device. */ +/* */ +/* INPUT */ +/* */ +/* class_command Class command structure */ +/* */ +/* OUTPUT */ +/* */ +/* Number of owners */ +/* */ +/* CALLS */ +/* */ +/* (ux_host_class_entry_function) Class entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UX_HOST_CLASS *_ux_host_stack_class_call(UX_HOST_CLASS_COMMAND *class_command) +{ + +UINT status = UX_NO_CLASS_MATCH; +UX_HOST_CLASS *class_inst; +#if UX_MAX_CLASS_DRIVER > 1 +ULONG class_index; +#endif + + /* Start from the 1st registered classes with USBX. */ + class_inst = _ux_system_host -> ux_system_host_class_array; + + /* Parse all the class drivers. */ +#if UX_MAX_CLASS_DRIVER > 1 + for (class_index = 0; class_index < _ux_system_host -> ux_system_host_max_class; class_index++) + { +#endif + + /* Check if this class driver is used. */ + if (class_inst -> ux_host_class_status == UX_USED) + { + + /* We have found a potential candidate. Call this registered class entry function. */ + status = class_inst -> ux_host_class_entry_function(class_command); + + /* The status tells us if the registered class wants to own this class. */ + if (status == UX_SUCCESS) + { + + /* Yes, return this class pointer. */ + return(class_inst); + } + } +#if UX_MAX_CLASS_DRIVER > 1 + /* Move to the next registered class. */ + class_inst ++; + } +#endif + + /* There is no driver who want to own this class! */ + return(UX_NULL); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_device_scan.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_device_scan.c new file mode 100644 index 00000000..6ae7592a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_device_scan.c @@ -0,0 +1,153 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +#if !defined(UX_HOST_STACK_DEVICE_DRIVER_SCAN_DISABLE) +#if defined(UX_HOST_STACK_DEVICE_DRIVER_SCAN_VIDPID_DISABLE) && \ + defined(UX_HOST_STACK_DEVICE_DRIVER_SCAN_DCSP_DISABLE) +#error When device driver scan is enabled at least one of scan method must be enabled in (VIDPID, DeviceClassSubclassProtocol) +#endif +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_device_scan PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will scan all registered classes with a device */ +/* candidate. Priority is given to the PID/VID and then the */ +/* Class/Subclass/Protocol. */ +/* */ +/* INPUT */ +/* */ +/* device Pointer to device */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_class_call Call host stack class */ +/* (ux_host_class_entry_function) Class entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used query usage of device */ +/* ClassSubclassProtocol, */ +/* resulting in version 6.1 */ +/* 06-02-2021 Bhupendra Naphade Modified comment(s), */ +/* removed duplicate line, */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_device_scan(UX_DEVICE *device) +{ +#if !defined(UX_HOST_STACK_DEVICE_DRIVER_SCAN_DISABLE) + +UINT status; +UX_HOST_CLASS *class_inst = UX_NULL; +UX_HOST_CLASS_COMMAND class_command; + + /* Perform the command initialization. */ + class_command.ux_host_class_command_request = UX_HOST_CLASS_COMMAND_QUERY; + class_command.ux_host_class_command_container = (VOID *) device; + class_command.ux_host_class_command_vid = device -> ux_device_descriptor.idVendor; + class_command.ux_host_class_command_pid = device -> ux_device_descriptor.idProduct; + class_command.ux_host_class_command_class = device -> ux_device_descriptor.bDeviceClass; + class_command.ux_host_class_command_subclass = device -> ux_device_descriptor.bDeviceSubClass; + class_command.ux_host_class_command_protocol = device -> ux_device_descriptor.bDeviceProtocol; + class_command.ux_host_class_command_iad_class = 0; + class_command.ux_host_class_command_iad_subclass = 0; + class_command.ux_host_class_command_iad_protocol = 0; + +#if !defined(UX_HOST_STACK_DEVICE_DRIVER_SCAN_VIDPID_DISABLE) + /* We start with the PID/VID for this device. */ + class_command.ux_host_class_command_usage = UX_HOST_CLASS_COMMAND_USAGE_PIDVID; + class_inst = _ux_host_stack_class_call(&class_command); +#endif + +#if !defined(UX_HOST_STACK_DEVICE_DRIVER_SCAN_DCSP_DISABLE) + /* On return, either we have found a class or the device is still an orphan. */ + if (class_inst == UX_NULL) + { + + /* It the PID/VID did not work, we continue looking for the Class\Subclass\Protocol match. */ + class_command.ux_host_class_command_usage = UX_HOST_CLASS_COMMAND_USAGE_DCSP; + class_inst = _ux_host_stack_class_call(&class_command); + + } +#endif + + /* On return, either we have found a class or the device is still an orphan. */ + if (class_inst != UX_NULL) + { + + device -> ux_device_class = class_inst; + +#if defined(UX_HOST_STANDALONE) + + /* Activation may take time, run as state machine. */ + status = UX_SUCCESS; + return(status); +#else + class_command.ux_host_class_command_class_ptr = class_inst; + class_command.ux_host_class_command_request = UX_HOST_CLASS_COMMAND_ACTIVATE; + status = device -> ux_device_class -> ux_host_class_entry_function(&class_command); + + /* Return result of activation. */ + return(status); +#endif + } + +#endif + + /* Return an error. */ + return(UX_NO_CLASS_MATCH); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_get.c new file mode 100644 index 00000000..286280a9 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_get.c @@ -0,0 +1,139 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns a pointer to the class container. A class */ +/* needs to obtain its container from the USBX stack to search for */ +/* instances when a driver or an application wants to open a device. */ +/* */ +/* Note: The C string of class_name must be NULL-terminated and the */ +/* length of it (without the NULL-terminator itself) must be no larger */ +/* than UX_MAX_CLASS_NAME_LENGTH. */ +/* */ +/* INPUT */ +/* */ +/* class_name Name of class */ +/* class Class pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check C string and return its */ +/* length if null-terminated */ +/* _ux_utility_memory_compare Compare memory blocks */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_get(UCHAR *class_name, UX_HOST_CLASS **host_class) +{ + +UX_HOST_CLASS *class_ptr; +#if !defined(UX_NAME_REFERENCED_BY_POINTER) +UINT status; +UINT class_name_length = 0; +#endif +#if UX_MAX_CLASS_DRIVER > 1 +ULONG class_index; +#endif + +#if !defined(UX_NAME_REFERENCED_BY_POINTER) + /* Get the length of the class name (exclude null-terminator). */ + status = _ux_utility_string_length_check(class_name, &class_name_length, UX_MAX_CLASS_NAME_LENGTH); + if (status) + return(status); +#endif + + /* Get first class. */ + class_ptr = _ux_system_host -> ux_system_host_class_array; + +#if UX_MAX_CLASS_DRIVER > 1 + /* We need to parse the class driver table. */ + for (class_index = 0; class_index < _ux_system_host -> ux_system_host_max_class; class_index++) + { +#endif + + /* Check if this class is already being used. */ + if (class_ptr -> ux_host_class_status == UX_USED) + { + + /* We have found a container. Check if this is the one we need (compare including null-terminator). */ + if (ux_utility_name_match(class_ptr -> ux_host_class_name, class_name, class_name_length + 1)) + { + + /* The class container was found. Update the pointer to the class container for the caller. */ + *host_class = class_ptr; + + /* Return success. */ + return(UX_SUCCESS); + } + } + +#if UX_MAX_CLASS_DRIVER > 1 + /* Move to the next class. */ + class_ptr++; + } +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_HOST_CLASS_UNKNOWN, class_name, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* This class does not exist, return an error. */ + return(UX_HOST_CLASS_UNKNOWN); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_create.c new file mode 100644 index 00000000..a13a5031 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_create.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_instance_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a new class instance for a class container. */ +/* The instance of a class is not contained in the class code to */ +/* reduce the class driver complexity. Rather, each class instance is */ +/* attached to class container. */ +/* */ +/* INPUT */ +/* */ +/* class Pointer to class */ +/* class_instance Pointer to class instance */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_instance_create(UX_HOST_CLASS *host_class, VOID *class_instance) +{ + +VOID **current_class_instance; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_CLASS_INSTANCE_CREATE, host_class, class_instance, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_REGISTER(UX_TRACE_HOST_OBJECT_TYPE_CLASS_INSTANCE, class_instance, 0, 0, 0) + + /* Start with the first class instance attached to the class container. */ + current_class_instance = host_class -> ux_host_class_first_instance; + + /* Check if there are any instances attached. */ + if (current_class_instance == UX_NULL) + { + + /* Since it is the first class, attach it to the class container. */ + host_class -> ux_host_class_first_instance = class_instance; + + /* Return successful completion. */ + return(UX_SUCCESS); + } + + /* Traverse the list of the class instances until we find the last class. */ + while (*current_class_instance != UX_NULL) + { + + /* Point to the next class instance. */ + current_class_instance = *current_class_instance; + } + + /* We have reached the last class, hook the new class to the end. This way, we preserve + the chronological order of the class instances. */ + *current_class_instance = class_instance; + + /* Return successful completion to caller. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_destroy.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_destroy.c new file mode 100644 index 00000000..c48a5ed8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_destroy.c @@ -0,0 +1,145 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_instance_destroy PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function destroys a class instance for a class container. */ +/* */ +/* INPUT */ +/* */ +/* class Pointer to class */ +/* class_instance Pointer to class instance */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_instance_destroy(UX_HOST_CLASS *host_class, VOID *class_instance) +{ + +VOID **current_class_instance; +VOID **next_class_instance; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_CLASS_INSTANCE_DESTROY, host_class, class_instance, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_UNREGISTER(class_instance); + + /* Get the pointer to the instance pointed by the instance to destroy. */ + next_class_instance = class_instance; + next_class_instance = *next_class_instance; + + /* Start with the first class instance attached to the class container. */ + current_class_instance = host_class -> ux_host_class_first_instance; + + /* Check if there are any instances attached. */ + if (current_class_instance == UX_NULL) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_HOST_CLASS_INSTANCE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_HOST_CLASS_INSTANCE_UNKNOWN, class_instance, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_HOST_CLASS_INSTANCE_UNKNOWN); + } + + /* The first instance is a special case because it is attached to the class + container. */ + if (current_class_instance == class_instance) + { + + /* Point to next class instance. */ + host_class -> ux_host_class_first_instance = next_class_instance; + + /* Return success. */ + return(UX_SUCCESS); + } + + /* Traverse the list of the class instances until we found the right one. */ + while (*current_class_instance != UX_NULL) + { + + /* Check to see if this class is the one we need to destroy. */ + if(*current_class_instance == class_instance) + { + + /* Point to next class instance. */ + *current_class_instance = next_class_instance; + + /* Return success. */ + return(UX_SUCCESS); + } + + /* Points to the next class instance. */ + current_class_instance = *current_class_instance; + } + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_HOST_CLASS_INSTANCE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_HOST_CLASS_INSTANCE_UNKNOWN, class_instance, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return error to caller. */ + return(UX_HOST_CLASS_INSTANCE_UNKNOWN); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_get.c new file mode 100644 index 00000000..b5bc6ed9 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_get.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_instance_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns a class instance pointer for a specific */ +/* class. The instance of a class is not contained in the class code */ +/* to reduce the class complexity. Rather, each class instance is */ +/* attached to class container. */ +/* */ +/* INPUT */ +/* */ +/* class Pointer to class */ +/* class_index Index of class */ +/* class_instance Destination of class instance */ +/* pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_instance_get(UX_HOST_CLASS *host_class, UINT class_index, VOID **class_instance) +{ + +VOID **current_class_instance; + + + /* Start with the first class instance attached to the class container. */ + current_class_instance = host_class -> ux_host_class_first_instance; + + /* Check if there are any instances attached. */ + if(current_class_instance == UX_NULL) + { + + return(UX_HOST_CLASS_INSTANCE_UNKNOWN); + } + + /* Traverse the list of the class instances until we found the right one. */ + while (class_index-- != 0) + { + + /* Points to the next class instance. */ + current_class_instance = *current_class_instance; + + /* Check if we have reached the end of the list of the class instances. */ + if (current_class_instance == UX_NULL) + { + + return(UX_HOST_CLASS_INSTANCE_UNKNOWN); + } + } + + /* Update the class instance pointer from the caller. */ + *class_instance = current_class_instance; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_verify.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_verify.c new file mode 100644 index 00000000..8482123e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_instance_verify.c @@ -0,0 +1,145 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_instance_verify PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function ensures that a given instance exists. An application */ +/* is not responsible for keeping the instance valid pointer. The */ +/* class is responsible for the instance checks if the instance is */ +/* still valid. */ +/* */ +/* INPUT */ +/* */ +/* class_name Name of class */ +/* class_instance Pointer to class instance */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check C string and return its */ +/* length if null-terminated */ +/* _ux_utility_memory_compare Compare blocks of memory */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_instance_verify(UCHAR *class_name, VOID *class_instance) +{ + +UX_HOST_CLASS *class_inst; +#if UX_MAX_CLASS_DRIVER > 1 +ULONG class_index; +#endif +VOID **current_class_instance; +#if !defined(UX_NAME_REFERENCED_BY_POINTER) +UINT status; +UINT class_name_length = 0; +#endif + +#if !defined(UX_NAME_REFERENCED_BY_POINTER) + /* Get the length of the class name (exclude null-terminator). */ + status = _ux_utility_string_length_check(class_name, &class_name_length, UX_MAX_CLASS_NAME_LENGTH); + if (status) + return(status); +#endif + + /* Get first class. */ + class_inst = _ux_system_host -> ux_system_host_class_array; + +#if UX_MAX_CLASS_DRIVER > 1 + /* We need to parse the class table. */ + for(class_index = 0; class_index < _ux_system_host -> ux_system_host_max_class; class_index++) + { +#endif + + /* Check if this class is already used. */ + if (class_inst -> ux_host_class_status == UX_USED) + { + + /* Start with the first class instance attached to the class container. */ + current_class_instance = class_inst -> ux_host_class_first_instance; + + /* Traverse the list of the class instances until we find the correct instance. */ + while (current_class_instance != UX_NULL) + { + + /* Check the class instance attached to the container with the caller's + instance. */ + if (current_class_instance == class_instance) + { + + /* We have found the class container. Check if this is the one we need (compare including null-terminator). */ + if (ux_utility_name_match(class_inst-> ux_host_class_name, class_name, class_name_length + 1)) + return(UX_SUCCESS); + } + + /* Points to the next class instance. */ + current_class_instance = *current_class_instance; + } + } +#if UX_MAX_CLASS_DRIVER > 1 + + /* Move to the next class. */ + class_inst ++; + } +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_HOST_CLASS_INSTANCE_UNKNOWN, class_instance, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* This class does not exist. */ + return(UX_HOST_CLASS_INSTANCE_UNKNOWN); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_interface_scan.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_interface_scan.c new file mode 100644 index 00000000..dd10214c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_interface_scan.c @@ -0,0 +1,111 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_interface_scan PORTABLE C */ +/* 6.1.4 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will scan all default interfaces for a single */ +/* configuration and call the registered class with the */ +/* Class/SubClass/Protocol of the interface. */ +/* */ +/* If the device has multiple configurations (like the Apple iPod), */ +/* the first configuration is treated as the default configuration. */ +/* If a device which has multiple configurations wants to control the */ +/* configuration selection, it must ensure that the PID/VID based */ +/* class at the device level claims the entire device. */ +/* */ +/* */ +/* For the interface, there is no reason to use the PID/VID has a */ +/* binding element as classes that trigger on PID/VID will be called */ +/* by the device descriptor scanning process. */ +/* */ +/* INPUT */ +/* */ +/* device Device pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Result of operation */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_class_call Call class command */ +/* _ux_host_stack_device_configuration_select */ +/* Select configuration */ +/* (ux_host_stack_class_call) Call class from host stack */ +/* (ux_host_class_entry_function) Class entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* used internal function call */ +/* to scan interfaces, */ +/* resulting in version 6.1.4 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_interface_scan(UX_DEVICE *device) +{ + +UX_CONFIGURATION *configuration; +UINT status; + + + /* Get the 1st and only configuration. If the device has multiple + configurations, we simply use the first one as default. */ + configuration = device -> ux_device_first_configuration; + if (configuration == UX_NULL) + return(UX_ERROR); + + /* Scan interfaces for this configuration. */ + status = _ux_host_stack_configuration_interface_scan(configuration); + + /* Return operation result. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_register.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_register.c new file mode 100644 index 00000000..4a6f583f --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_register.c @@ -0,0 +1,175 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a USB class to the USB stack. The Class */ +/* must specify an entry point for the USB stack to send commands */ +/* such as: */ +/* */ +/* UX_HOST_CLASS_COMMAND_QUERY */ +/* UX_HOST_CLASS_COMMAND_ACTIVATE */ +/* UX_HOST_CLASS_COMMAND_DESTROY */ +/* */ +/* Note: The C string of class_name must be NULL-terminated and the */ +/* length of it (without the NULL-terminator itself) must be no larger */ +/* than UX_MAX_CLASS_NAME_LENGTH. */ +/* */ +/* INPUT */ +/* */ +/* class_name Name of class */ +/* class_entry_function Entry function of the class */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check C string and return */ +/* length if null-terminated */ +/* _ux_utility_memory_copy Copy memory block */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, verified */ +/* memset and memcpy cases, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_register(UCHAR *class_name, + UINT (*class_entry_function)(struct UX_HOST_CLASS_COMMAND_STRUCT *)) +{ + +UX_HOST_CLASS *class_inst; +#if !defined(UX_NAME_REFERENCED_BY_POINTER) +UINT status; +UINT class_name_length = 0; +#endif +#if UX_MAX_CLASS_DRIVER > 1 +ULONG class_index; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_CLASS_REGISTER, class_name, class_entry_function, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + +#if !defined(UX_NAME_REFERENCED_BY_POINTER) + /* Get the length of the class name (exclude null-terminator). */ + status = _ux_utility_string_length_check(class_name, &class_name_length, UX_MAX_CLASS_NAME_LENGTH); + if (status) + return(status); +#endif + + /* Get first class. */ + class_inst = _ux_system_host -> ux_system_host_class_array; + +#if UX_MAX_CLASS_DRIVER > 1 + /* We need to parse the class table to find an empty spot. */ + for (class_index = 0; class_index < _ux_system_host -> ux_system_host_max_class; class_index++) + { +#endif + + /* Check if this class is already used. */ + if (class_inst -> ux_host_class_status == UX_UNUSED) + { + +#if defined(UX_NAME_REFERENCED_BY_POINTER) + class_inst -> ux_host_class_name = (const UCHAR *) class_name; +#else + + /* We have found a free container for the class. Copy the name (with null-terminator). */ + _ux_utility_memory_copy(class_inst -> ux_host_class_name, class_name, class_name_length + 1); /* Use case of memcpy is verified. */ +#endif + + /* Memorize the entry function of this class. */ + class_inst -> ux_host_class_entry_function = class_entry_function; + + /* Mark it as used. */ + class_inst -> ux_host_class_status = UX_USED; + + /* Return successful completion. */ + return(UX_SUCCESS); + } + + /* Do a sanity check to make sure the class is not already installed by + mistake. To verify this, we simple check for the class entry point. */ + else + { + + /* Check for an already installed class entry function. */ + if(class_inst -> ux_host_class_entry_function == class_entry_function) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_INIT, UX_HOST_CLASS_ALREADY_INSTALLED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_HOST_CLASS_ALREADY_INSTALLED, class_name, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Yes, return an error. */ + return(UX_HOST_CLASS_ALREADY_INSTALLED); + } + } +#if UX_MAX_CLASS_DRIVER > 1 + /* Move to the next class. */ + class_inst ++; + } +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MEMORY_ARRAY_FULL, class_name, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_INIT, UX_MEMORY_ARRAY_FULL); + + /* No more entries in the class table. */ + return(UX_MEMORY_ARRAY_FULL); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_unregister.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_unregister.c new file mode 100644 index 00000000..70877ad6 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_class_unregister.c @@ -0,0 +1,125 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_class_unregister PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unregisters a USB class from the USB stack. */ +/* */ +/* Note following steps must be done before host class unregister: */ +/* All devices related to the class must be removed. */ +/* */ +/* INPUT */ +/* */ +/* class_name Name of class */ +/* class_entry_function Entry function of the class */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* UX_SUCCESS Class unregistered */ +/* UX_NO_CLASS_MATCH Class not found */ +/* */ +/* CALLS */ +/* */ +/* (class_entry_function) Entry function of the class */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_class_unregister(UINT (*class_entry_function)(struct UX_HOST_CLASS_COMMAND_STRUCT *)) +{ + +UX_HOST_CLASS *class_inst; +UX_HOST_CLASS_COMMAND class_command; +#if UX_MAX_CLASS_DRIVER > 1 +ULONG class_index; +#endif + + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_CLASS_UNREGISTER, class_entry_function, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Get first class. */ + class_inst = _ux_system_host -> ux_system_host_class_array; + +#if UX_MAX_CLASS_DRIVER > 1 + /* We need to parse the class table to find right class instance. */ + for (class_index = 0; class_index < _ux_system_host -> ux_system_host_max_class; class_index++) + { +#endif + + /* Check if the class is expected. */ + if (class_inst -> ux_host_class_entry_function == class_entry_function) + { + + /* Initialize the class command with the generic parameters. */ + class_command.ux_host_class_command_request = UX_HOST_CLASS_COMMAND_DESTROY; + class_command.ux_host_class_command_class_ptr = (VOID *)class_inst; + + /* Invoke command for class destroy. */ + class_inst -> ux_host_class_entry_function(&class_command); + + /* Mark as free. */ + class_inst -> ux_host_class_entry_function = UX_NULL; + class_inst -> ux_host_class_status = UX_UNUSED; + + /* Class unregistered success. */ + return(UX_SUCCESS); + } + +#if UX_MAX_CLASS_DRIVER > 1 + /* Move to the next class. */ + class_inst ++; + } +#endif + + /* No more entries in the class table. */ + return(UX_NO_CLASS_MATCH); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_descriptor_parse.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_descriptor_parse.c new file mode 100644 index 00000000..0cac0773 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_descriptor_parse.c @@ -0,0 +1,139 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_configuration_descriptor_parse PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the entire configuration descriptor and */ +/* enumerates the interfaces, binds the interface to a class driver... */ +/* if the device has multiple configurations, we read all the */ +/* configurations but do not instantiate any configuration. Rather we */ +/* let a class driver do the work. */ +/* */ +/* INPUT */ +/* */ +/* device Pointer to device */ +/* configuration Pointer to configuration */ +/* configuration_index Index of configuration */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_interfaces_scan Scan host interfaces */ +/* _ux_host_stack_transfer_request Process transfer request */ +/* _ux_utility_memory_allocate Allocate block of memory */ +/* _ux_utility_memory_free Free block of memory */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_configuration_descriptor_parse(UX_DEVICE *device, UX_CONFIGURATION *configuration, + UINT configuration_index) +{ + +UX_TRANSFER *transfer_request; +UINT status; +UCHAR *descriptor; +UX_ENDPOINT *control_endpoint; +ULONG total_configuration_length; + + + /* Retrieve the pointer to the control endpoint and its transfer_request. */ + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Retrieve the size of all the configuration descriptor. */ + total_configuration_length = configuration -> ux_configuration_descriptor.wTotalLength; + + /* Allocate enough memory to read all descriptors attached to this configuration. */ + descriptor = _ux_utility_memory_allocate(UX_SAFE_ALIGN, UX_CACHE_SAFE_MEMORY, total_configuration_length); + + /* Determine if the memory was allocated. */ + if (descriptor == UX_NULL) + { + + /* No, return an error. */ + return(UX_MEMORY_INSUFFICIENT); + } + else + { + + /* Create a transfer_request for the GET_DESCRIPTOR request. */ + transfer_request -> ux_transfer_request_data_pointer = descriptor; + transfer_request -> ux_transfer_request_requested_length = total_configuration_length; + transfer_request -> ux_transfer_request_function = UX_GET_DESCRIPTOR; + transfer_request -> ux_transfer_request_type = UX_REQUEST_IN | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = configuration_index | (UINT)(UX_CONFIGURATION_DESCRIPTOR_ITEM << 8); + transfer_request -> ux_transfer_request_index = 0; + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Check for correct transfer and entire descriptor returned. */ + if((status == UX_SUCCESS) && (transfer_request -> ux_transfer_request_actual_length == total_configuration_length)) + { + + /* The entire descriptor now contains the configuration descriptor, + the interface(s) descriptors, all alternate settings, endpoints + and descriptor specific to the class. The descriptor is parsed for all interfaces. */ + status = _ux_host_stack_interfaces_scan(configuration, descriptor); + } + } + + /* Free all used resources. */ + _ux_utility_memory_free(descriptor); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_enumerate.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_enumerate.c new file mode 100644 index 00000000..0824d97b --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_enumerate.c @@ -0,0 +1,191 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_configuration_enumerate PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the configuration descriptor, creates the */ +/* configuration container(s) for the device, and enumerates all found */ +/* configurations. */ +/* */ +/* At this stage, only the containers for each subcomponents are */ +/* linked. No configuration, interface or endpoints are active unless */ +/* a class issues a SET_CONFIGURATION. */ +/* */ +/* INPUT */ +/* */ +/* device Pointer to device */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_configuration_descriptor_parse */ +/* Parse configuration descriptor*/ +/* _ux_host_stack_configuration_instance_delete */ +/* Delete configuration instance */ +/* _ux_host_stack_new_configuration_create */ +/* Create new configuration */ +/* _ux_host_stack_transfer_request Process transfer request */ +/* _ux_utility_descriptor_parse Parse descriptor */ +/* _ux_utility_memory_allocate Allocate block of memory */ +/* _ux_utility_memory_free Free block of memory */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_configuration_enumerate(UX_DEVICE *device) +{ + +UX_TRANSFER *transfer_request; +UINT status = UX_ERROR; +UCHAR * descriptor; +UX_ENDPOINT *control_endpoint; +UX_CONFIGURATION *configuration; +ULONG nb_configurations; +ULONG configuration_index; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_CONFIGURATION_ENUMERATE, device, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Retrieve the pointer to the control endpoint and its transfer_request. */ + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Need to allocate memory for the configuration descriptor the first time we read + only the configuration descriptor when we have the configuration descriptor, we have + the length of the entire configuration\interface\endpoint descriptors. */ + descriptor = _ux_utility_memory_allocate(UX_SAFE_ALIGN, UX_CACHE_SAFE_MEMORY, UX_CONFIGURATION_DESCRIPTOR_LENGTH); + if (descriptor == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* There maybe multiple configurations for this device. */ + nb_configurations = device -> ux_device_descriptor.bNumConfigurations; + + /* Parse all the configurations attached to the device. We start with the first index. + The index and the actual configuration value may be different according to the USB specification! */ + for (configuration_index = 0; configuration_index < nb_configurations; configuration_index++) + { + + /* Create a transfer_request for the GET_DESCRIPTOR request. */ + transfer_request -> ux_transfer_request_data_pointer = descriptor; + transfer_request -> ux_transfer_request_requested_length = UX_CONFIGURATION_DESCRIPTOR_LENGTH; + transfer_request -> ux_transfer_request_function = UX_GET_DESCRIPTOR; + transfer_request -> ux_transfer_request_type = UX_REQUEST_IN | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = configuration_index | (UINT)(UX_CONFIGURATION_DESCRIPTOR_ITEM << 8); + transfer_request -> ux_transfer_request_index = 0; + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Check for correct transfer and entire descriptor returned. */ + if ((status == UX_SUCCESS) && (transfer_request -> ux_transfer_request_actual_length == UX_CONFIGURATION_DESCRIPTOR_LENGTH)) + { + + /* Allocate some memory for the container of this descriptor. */ + configuration = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_CONFIGURATION)); + + /* Check to see if the block was allocated. */ + if (configuration != UX_NULL) + { + + /* This configuration must be linked to the device. */ + _ux_host_stack_new_configuration_create(device, configuration); + + /* The descriptor is in a packed format, parse it locally. */ + _ux_utility_descriptor_parse(descriptor, _ux_system_configuration_descriptor_structure, + UX_CONFIGURATION_DESCRIPTOR_ENTRIES, (UCHAR *) &configuration -> ux_configuration_descriptor); + + /* Parse the device descriptor so that we can retrieve the length + of the entire configuration. */ + status = _ux_host_stack_configuration_descriptor_parse(device, configuration, configuration_index); + + /* Check the completion status. */ + if (status != UX_SUCCESS) + { + /* Error, delete the configuration instance. */ + _ux_host_stack_configuration_instance_delete(configuration); + } + } + else + { + + /* Cannot allocate configuration memory. Abort enumeration */ + status = UX_MEMORY_INSUFFICIENT; + + break; + } + } + else + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DESCRIPTOR_CORRUPTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DESCRIPTOR_CORRUPTED, descriptor, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* The device descriptor does not contain the right amount of data. Maybe corruption. */ + status = UX_DESCRIPTOR_CORRUPTED; + + break; + } + + } + + /* Free all used resources. */ + _ux_utility_memory_free(descriptor); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_instance_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_instance_create.c new file mode 100644 index 00000000..5b2a306a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_instance_create.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_configuration_instance_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will create a configuration instance. It scan all the */ +/* interfaces hooked to the configuration and enable each interface */ +/* with the alternate setting 0. */ +/* */ +/* INPUT */ +/* */ +/* configuration Pointer to configuration */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_interface_instance_create Create interface instance */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_configuration_instance_create(UX_CONFIGURATION *configuration) +{ + +UX_INTERFACE *interface; +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_CONFIGURATION_INSTANCE_CREATE, configuration, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Obtain the first interface for this configuration. */ + interface = configuration -> ux_configuration_first_interface; + + /* Each selected alternate setting 0 for each interface must be created. */ + while (interface != UX_NULL) + { + + /* Check if we are dealing with the first alternate setting. */ + if (interface -> ux_interface_descriptor.bAlternateSetting == 0) + { + /* Create the interface. */ + status = _ux_host_stack_interface_instance_create(interface); + + /* Check status, the controller may have refused the endpoint creation. */ + if (status != UX_SUCCESS) + + /* An error occurred. The interface cannot be mounted. */ + return(status); + + } + + /* Next interface. */ + interface = interface -> ux_interface_next_interface; + } + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_instance_delete.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_instance_delete.c new file mode 100644 index 00000000..446accc0 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_instance_delete.c @@ -0,0 +1,109 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_configuration_instance_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will delete a configuration instance. It does not */ +/* delete configuration container but it deletes all the alternate */ +/* current alternate settings for each interface it owns. */ +/* */ +/* INPUT */ +/* */ +/* configuration Pointer to configuration */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_interface_instance_delete Delete interface instance */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_configuration_instance_delete(UX_CONFIGURATION *configuration) +{ + +UX_INTERFACE *interface; +ULONG current_alternate_setting; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_CONFIGURATION_INSTANCE_DELETE, configuration, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Obtain the first interface for this configuration. */ + interface = configuration -> ux_configuration_first_interface; + + /* In order to keep the compiler happy, we reset the alternate setting. */ + current_alternate_setting = 0; + + /* Each selected alternate setting for each interface must be deleted. */ + while (interface != UX_NULL) + { + + /* If this is the first alternate setting, the current alternate setting is maintained here. */ + if (interface -> ux_interface_descriptor.bAlternateSetting == 0) + { + + current_alternate_setting = interface -> ux_interface_current_alternate_setting; + } + + if (interface -> ux_interface_descriptor.bAlternateSetting == current_alternate_setting) + { + _ux_host_stack_interface_instance_delete(interface); + } + + interface = interface -> ux_interface_next_interface; + } + + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_interface_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_interface_get.c new file mode 100644 index 00000000..39abb4a1 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_interface_get.c @@ -0,0 +1,185 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_configuration_interface_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns an interface container based on a */ +/* configuration handle, an interface index and an alternate setting */ +/* index. */ +/* */ +/* INPUT */ +/* */ +/* configuration Pointer to configuration */ +/* interface_index Index of interface */ +/* alternate_setting_index Index of alternate setting */ +/* interface Destination of interface */ +/* pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_configuration_interface_get(UX_CONFIGURATION *configuration, + UINT interface_index, UINT alternate_setting_index, + UX_INTERFACE **interface) +{ + +UINT current_interface_number; +UINT container_index; +UX_INTERFACE *current_interface; + + + /* Do a sanity check on the configuration handle. */ + if (configuration -> ux_configuration_handle != (ULONG) (ALIGN_TYPE) configuration) + { + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_CONFIGURATION_HANDLE_UNKNOWN, configuration, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_CONFIGURATION_HANDLE_UNKNOWN); + } + + /* Start with the interface attached to the configuration. */ + current_interface = configuration -> ux_configuration_first_interface; + + /* The first interface has the index 0 */ + container_index = 0; + + /* Reset the interface number */ + current_interface_number = 0; + + /* Traverse the list of the interfaces until we found the right one */ + while (current_interface != UX_NULL) + { + + /* Check if the interface index matches the current one. */ + if (interface_index == container_index) + { + + /* We have found the correct interface, now search for the alternate setting. */ + current_interface_number = current_interface -> ux_interface_descriptor.bInterfaceNumber; + + /* The first alternate setting has the index 0. */ + container_index = 0; + + /* Loop on all the alternate settings for this interface. */ + while (current_interface != UX_NULL) + { + + /* Check if the index is matched */ + if (alternate_setting_index == container_index) + { + + /* We have found the right interface/alternate setting combination. Set the + interface return pointer. */ + *interface = current_interface; + + /* Return success to caller. */ + return(UX_SUCCESS); + } + + /* Move to next alternate setting index. */ + container_index++; + + /* Move to the next alternate setting. */ + current_interface = current_interface -> ux_interface_next_interface; + + + /* Check new interface pointer, might be the end. */ + if (current_interface != UX_NULL) + { + + /* And verify that we are still in the same interface. */ + if (current_interface -> ux_interface_descriptor.bInterfaceNumber != current_interface_number) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_INTERFACE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_INTERFACE_HANDLE_UNKNOWN, interface, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_INTERFACE_HANDLE_UNKNOWN); + } + } + } + } + + /* Check the current interface, we may already be at the end ... */ + if (current_interface != UX_NULL) + { + + /* Move to the next interface. */ + current_interface = current_interface -> ux_interface_next_interface; + + /* Move to the next interface index. */ + container_index++; + } + } + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_INTERFACE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_INTERFACE_HANDLE_UNKNOWN, interface, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Didn't find the right interface/alternate setting, return an error! */ + return(UX_INTERFACE_HANDLE_UNKNOWN); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_interface_scan.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_interface_scan.c new file mode 100644 index 00000000..fc75daa3 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_interface_scan.c @@ -0,0 +1,190 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_configuration_interface_scan PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will scan all default interfaces for a specific */ +/* configuration and call the registered class with the */ +/* Class/SubClass/Protocol of the interface. */ +/* */ +/* INPUT */ +/* */ +/* configuration Configuration pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Result of operation */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_class_call Call class command */ +/* _ux_host_stack_device_configuration_select */ +/* Select configuration */ +/* _ux_host_stack_class_call Call class from host stack */ +/* (ux_host_class_entry_function) Class entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 02-02-2021 Chaoqiong Xiao Initial Version 6.1.4 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_configuration_interface_scan(UX_CONFIGURATION *configuration) +{ + +UX_INTERFACE *interface; +UINT nb_class_owners; +UX_HOST_CLASS *class; +UX_HOST_CLASS_COMMAND class_command; +UINT status; + + + /* Initialize class owners to 0. */ + nb_class_owners = 0; + + /* Get the first interface container for this configuration. */ + interface = configuration -> ux_configuration_first_interface; + + /* We now scan all the alternate settings 0 for each of the interfaces. */ + while (interface != UX_NULL) + { + + /* Is there a default interface? */ + if(interface -> ux_interface_descriptor.bAlternateSetting == 0) + { + + /* We have a default interface for this configuration. Call each class + with the class\subclass\protocol. We include the IAD for the cdc classes. */ + class_command.ux_host_class_command_request = UX_HOST_CLASS_COMMAND_QUERY; + class_command.ux_host_class_command_container = (VOID *)interface; + class_command.ux_host_class_command_usage = UX_HOST_CLASS_COMMAND_USAGE_CSP; + class_command.ux_host_class_command_class = interface -> ux_interface_descriptor.bInterfaceClass; + class_command.ux_host_class_command_subclass = interface -> ux_interface_descriptor.bInterfaceSubClass; + class_command.ux_host_class_command_protocol = interface -> ux_interface_descriptor.bInterfaceProtocol; + class_command.ux_host_class_command_iad_class = interface -> ux_interface_iad_class ; + class_command.ux_host_class_command_iad_subclass = interface -> ux_interface_iad_subclass; + class_command.ux_host_class_command_iad_protocol = interface -> ux_interface_iad_protocol; + + class = _ux_host_stack_class_call(&class_command); + + /* On return, either we have found a class or the interface is still an orphan. */ + if (class != UX_NULL) + { + + /* There is a class. */ + nb_class_owners++; + interface -> ux_interface_class = class; + } + } + + /* point to the next interface until end of the list. */ + interface = interface -> ux_interface_next_interface; + } + +#if defined(UX_HOST_STANDALONE) + + /* Activated later in state machine. */ + status = (nb_class_owners > 0) ? UX_SUCCESS : UX_NO_CLASS_MATCH; + return(status); +#else + + /* Assume no classes. */ + status = UX_NO_CLASS_MATCH; + + /* Check the number of class owner found. */ + if (nb_class_owners != 0) + { + + /* If we have found one or more classes for any of the interfaces, + we can safely do a SET_CONFIGURATION of the device. */ + status = _ux_host_stack_device_configuration_select(configuration); + + /* Check the completion status. */ + if (status == UX_SUCCESS) + { + + /* The device is in the CONFIGURED state, we have to call each of the classes + again with an ACTIVATE signal. */ + interface = configuration -> ux_configuration_first_interface; + + while (interface != UX_NULL) + { + + /* Is there a default interface? */ + if (interface -> ux_interface_descriptor.bAlternateSetting == 0) + { + + /* We have found the default interface. If this interface is owned, + activate its class. */ + class_command.ux_host_class_command_request = UX_HOST_CLASS_COMMAND_ACTIVATE; + class_command.ux_host_class_command_container = (VOID *) interface; + + if (interface -> ux_interface_class != UX_NULL) + { + + /* Save the class in the command container */ + class_command.ux_host_class_command_class_ptr = interface -> ux_interface_class; + + /* Send the ACTIVATE command to the class */ + status = interface -> ux_interface_class -> ux_host_class_entry_function(&class_command); + + } + } + + /* Point to the next interface until end of the list. */ + interface = interface -> ux_interface_next_interface; + } + } + } + + /* Return operation result. */ + return(status); +#endif +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_set.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_set.c new file mode 100644 index 00000000..b4bd1ff2 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_configuration_set.c @@ -0,0 +1,192 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_configuration_set PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a setting of a device configuration. */ +/* */ +/* In RTOS mode, this function is blocking. */ +/* If the host is OTG capable and the device has an OTG descriptor */ +/* that supports HNP we perform a SET_FEATURE with b_hnp_support. */ +/* */ +/* In standalone mode, when device enumeration is in progress, this */ +/* function is non-blocking, it prepares transfer for enum step of */ +/* SET_CONFIGURE request. Otherwise it blocks until transfer request */ +/* done. */ +/* */ +/* INPUT */ +/* */ +/* configuration Pointer to configuration */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_transfer_request Process transfer request */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* used pointer for current */ +/* selected configuration, */ +/* resulting in version 6.1.4 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* set device power source, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_configuration_set(UX_CONFIGURATION *configuration) +{ + +UX_DEVICE *device; +UX_TRANSFER *transfer_request; +UINT status; +UX_ENDPOINT *control_endpoint; +#ifdef UX_OTG_SUPPORT +UX_HCD *hcd; +#endif + + + /* A configuration is selected. Retrieve the pointer to the control endpoint + and its transfer request. */ + device = configuration -> ux_configuration_device; + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + +#ifdef UX_OTG_SUPPORT + /* Check if the configuration has an OTG device with HNP feature. */ + if (configuration -> ux_configuration_otg_capabilities & UX_OTG_HNP_SUPPORT) + { + + /* For HNP to work the device has to be connected directly to the Root Hub and not + a down stream hub. If the parent is NULL, the device is on the root hub. */ + if (UX_DEVICE_PARENT_IS_ROOTHUB(device)) + { + + /* With the device we have the pointer to the HCD. */ + hcd = UX_DEVICE_HCD_GET(device); + + /* Check the HCD to ensure we have an OTG host controller. */ + if (hcd -> ux_hcd_otg_capabilities & UX_HCD_OTG_CAPABLE) + { + + /* The Host controller is OTG aware. Perform a SET_FEATURE with b_hnp_support. */ + transfer_request -> ux_transfer_request_data_pointer = UX_NULL; + transfer_request -> ux_transfer_request_requested_length = 0; + transfer_request -> ux_transfer_request_function = UX_SET_FEATURE; + transfer_request -> ux_transfer_request_type = UX_REQUEST_OUT| UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = UX_OTG_FEATURE_A_HNP_SUPPORT; + transfer_request -> ux_transfer_request_index = 0; + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* If the device fails this command we turn off its OTG capabilities. */ + if (status != UX_SUCCESS) + + /* Reset the OTG capabilities of the device. */ + configuration -> ux_configuration_otg_capabilities = 0; + + } + } + } +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_CONFIGURATION_SET, configuration, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Create a transfer_request for the SET_CONFIGURATION request. No data for this request. */ + transfer_request -> ux_transfer_request_requested_length = 0; + transfer_request -> ux_transfer_request_function = UX_SET_CONFIGURATION; + transfer_request -> ux_transfer_request_type = UX_REQUEST_OUT | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = (USHORT) configuration -> ux_configuration_descriptor.bConfigurationValue; + transfer_request -> ux_transfer_request_index = 0; + +#if defined(UX_HOST_STANDALONE) + if (device -> ux_device_flags &= UX_DEVICE_FLAG_ENUM) + { + + /* Special case for enumeration process, non-blocking. */ + device -> ux_device_enum_trans = transfer_request; + status = UX_SUCCESS; + return(status); + } + + /* Tend to be blocking after enumeration done. */ +#endif + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Check completion status. */ + if(status == UX_SUCCESS) + { + + /* Change the device state to configured. */ + device -> ux_device_state = UX_DEVICE_CONFIGURED; + + /* Store the new configuration value in the device container. */ + device -> ux_device_current_configuration = configuration; + + /* Save current device power source. */ + device -> ux_device_power_source = (configuration -> + ux_configuration_descriptor.bmAttributes & + UX_CONFIGURATION_DEVICE_SELF_POWERED) ? + UX_DEVICE_SELF_POWERED : UX_DEVICE_BUS_POWERED; + } + + /* Return status to caller. */ + return(status); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_delay_ms.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_delay_ms.c new file mode 100644 index 00000000..13837fb4 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_delay_ms.c @@ -0,0 +1,76 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_delay_ms PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is now obsolete. */ +/* */ +/* INPUT */ +/* */ +/* time Number of milliseconds to */ +/* wait for */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* (ux_hcd_entry_function) HCD entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_delay_ms(ULONG time) +{ + UX_PARAMETER_NOT_USED(time); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_address_set.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_address_set.c new file mode 100644 index 00000000..4fe08078 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_address_set.c @@ -0,0 +1,193 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_address_set PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets the device address to the new device. */ +/* */ +/* INPUT */ +/* */ +/* device Pointer to device */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_delay_ms Thread sleep */ +/* _ux_host_stack_transfer_request Process transfer request */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_address_set(UX_DEVICE *device) +{ + + +UINT status = UX_ERROR; +UX_TRANSFER *transfer_request; +UX_ENDPOINT *control_endpoint; +USHORT device_address; +#if UX_MAX_DEVICES > 1 +UX_HCD *hcd; +UINT address_byte_index; +UINT address_bit_index; +UCHAR device_address_byte; +#endif + + /* Retrieve the pointer to the control endpoint. */ + control_endpoint = &device -> ux_device_control_endpoint; + + /* Retrieve the transfer request pointer. */ + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Initialize device address to 1. */ + device_address = 1; + +#if UX_MAX_DEVICES > 1 + + /* We need the HCD pointer as well. */ + hcd = UX_DEVICE_HCD_GET(device); + + /* Calculate the new address of this device. We start with address 1. */ + for (address_byte_index = 0; address_byte_index < 16; address_byte_index++) + { + + /* Get the address mask byte. */ + device_address_byte = hcd -> ux_hcd_address[address_byte_index]; + + /* Scan each bit for an empty spot. */ + for (address_bit_index = 0; address_bit_index < 8; address_bit_index++) + { + + if ((device_address_byte & (1 << address_bit_index)) == 0) + { + + /* We have found an empty spot. Reserve this address. */ + device_address_byte = (UCHAR)((UCHAR)device_address_byte | (UCHAR)(1 << address_bit_index)); + + /* Store the address mask byte. */ + hcd -> ux_hcd_address[address_byte_index] = device_address_byte; + + /* OK, apply address. */ + status = UX_SUCCESS; + break; + } + + /* This address was already taken, increment to the next address. */ + device_address++; + } + + /* If address found, break the loop. */ + if (status == UX_SUCCESS) + { + break; + } + } + if (status == UX_ERROR) + + /* We should never get here! */ + return(UX_ERROR); +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_ADDRESS_SET, device, device_address, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Create a transfer request for the SET_ADDRESS request. */ + transfer_request -> ux_transfer_request_data_pointer = UX_NULL; + transfer_request -> ux_transfer_request_requested_length = 0; + transfer_request -> ux_transfer_request_function = UX_SET_ADDRESS; + transfer_request -> ux_transfer_request_type = UX_REQUEST_OUT | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = device_address; + transfer_request -> ux_transfer_request_index = 0; + +#if defined(UX_HOST_STANDALONE) + device -> ux_device_enum_trans = transfer_request; + status = UX_SUCCESS; + return(status); +#else + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Now, this address will be the one used in future transfers. The transfer may have failed and therefore + all the device resources including the new address will be free.*/ + device -> ux_device_address = (ULONG) device_address; + + /* Check completion status. */ + if (status == UX_SUCCESS) + { + + /* Mark the device as ADDRESSED now. */ + device -> ux_device_state = UX_DEVICE_ADDRESSED; + + /* Some devices need some time to accept this address. */ + _ux_utility_delay_ms(UX_DEVICE_ADDRESS_SET_WAIT); + + /* Return successful status. */ + return(status); + } + else + { + + /* We have an error at the first device transaction. This is mostly + due to the device having failed on the reset after power up. + we will try again either at the root hub or regular hub. */ + return(status); + } +#endif +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_activate.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_activate.c new file mode 100644 index 00000000..57bcfecb --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_activate.c @@ -0,0 +1,186 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_configuration_activate PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function selects a specific configuration for a device. */ +/* When this configuration is set to the device, by default all the */ +/* device interface and their associated alternate setting 0 is */ +/* activated on the device. */ +/* */ +/* INPUT */ +/* */ +/* configuration Pointer to configuration */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_get Get semaphore */ +/* _ux_utility_semaphore_put Put semaphore */ +/* _ux_host_stack_configuration_interface_scan Scan and activate */ +/* interfaces */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 02-02-2021 Chaoqiong Xiao Initial Version 6.1.4 */ +/* 06-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed trace enabled error, */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_configuration_activate(UX_CONFIGURATION *configuration) +{ +#if defined(UX_HOST_STANDALONE) +UX_INTERRUPT_SAVE_AREA +#endif +UX_DEVICE *device; +UINT status; + + + /* Check for validity of the configuration handle. */ + if (configuration -> ux_configuration_handle != (ULONG) (ALIGN_TYPE) configuration) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_CONFIGURATION_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_CONFIGURATION_HANDLE_UNKNOWN, configuration, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_CONFIGURATION_HANDLE_UNKNOWN); + } + + /* Get the device container for this configuration. */ + device = configuration -> ux_configuration_device; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_ACTIVATE, device, configuration, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + +#if defined(UX_HOST_STANDALONE) + + /* Check device lock. */ + UX_DISABLE + if (device -> ux_device_flags & UX_DEVICE_FLAG_LOCK) + { + UX_RESTORE + return(UX_BUSY); + } + device -> ux_device_flags |= UX_DEVICE_FLAG_LOCK; + UX_RESTORE +#else + + /* Protect the control endpoint semaphore here. It will be unprotected in the + transfer request function. */ + status = _ux_host_semaphore_get(&device -> ux_device_protection_semaphore, UX_WAIT_FOREVER); + + /* Check for status. */ + if (status != UX_SUCCESS) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_SEMAPHORE_ERROR); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_SEMAPHORE_ERROR, configuration, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_SEMAPHORE_ERROR); + } +#endif + + /* Check for the state of the device . If the device is already configured, + we need to cancel the existing configuration before enabling this one. */ + if (device -> ux_device_state == UX_DEVICE_CONFIGURED) + { + + /* If this configuration is already activated, we are good, + otherwise report error. */ + status = (device -> ux_device_current_configuration == configuration) ? + UX_SUCCESS : UX_ALREADY_ACTIVATED; +#if defined(UX_HOST_STANDALONE) + device -> ux_device_flags &= ~UX_DEVICE_FLAG_LOCK; +#else + _ux_host_semaphore_put(&device -> ux_device_protection_semaphore); +#endif + return(status); + } + + /* Scan and activate the interfaces. */ + status = _ux_host_stack_configuration_interface_scan(configuration); + +#if defined(UX_HOST_STANDALONE) + + if (status == UX_SUCCESS) + { + + /* Place device enum state: LOCK -> SET_CONFIGURE. */ + device -> ux_device_enum_trans = + &device -> ux_device_control_endpoint.ux_endpoint_transfer_request; + device -> ux_device_enum_state = UX_HOST_STACK_ENUM_TRANS_LOCK_WAIT; + device -> ux_device_enum_inst.configuration = configuration; + device -> ux_device_enum_next_state = UX_HOST_STACK_ENUM_CONFIG_SET; + + /* Set enumeration flag to process enumeration sequence. */ + device -> ux_device_flags |= UX_DEVICE_FLAG_ENUM; + + /* Wait until enumeration done and device removed. */ + while(device -> ux_device_enum_state != UX_STATE_IDLE) + { + _ux_system_host_tasks_run(); + } + } +#endif + + /* Return completion status. */ + return(status); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_deactivate.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_deactivate.c new file mode 100644 index 00000000..0168209a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_deactivate.c @@ -0,0 +1,191 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_configuration_deactivate PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deactivate current configuration for a device. */ +/* When this configuration is deactivated, all the device interfaces */ +/* are deactivated on the device. */ +/* */ +/* INPUT */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_get Get semaphore */ +/* _ux_utility_semaphore_put Put semaphore */ +/* (ux_host_class_entry_function) Class entry function */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 02-02-2021 Chaoqiong Xiao Initial Version 6.1.4 */ +/* 06-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed trace enabled error, */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_configuration_deactivate(UX_DEVICE *device) +{ + +#if defined(UX_HOST_STANDALONE) +UX_INTERRUPT_SAVE_AREA +#endif +UX_HOST_CLASS_COMMAND command; +UX_CONFIGURATION *configuration; +UX_INTERFACE *interface; +UINT status; + + + /* Do a sanity check on the device handle. */ + if (device -> ux_device_handle != (ULONG) (ALIGN_TYPE) device) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DEVICE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DEVICE_HANDLE_UNKNOWN, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DEVICE_HANDLE_UNKNOWN); + } + + /* Get the configuration. */ + configuration = device -> ux_device_current_configuration; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_DEACTIVATE, device, configuration, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + +#if defined(UX_HOST_STANDALONE) + + /* Check device lock. */ + UX_DISABLE + if (device -> ux_device_flags & UX_DEVICE_FLAG_LOCK) + { + UX_RESTORE + return(UX_BUSY); + } + device -> ux_device_flags |= UX_DEVICE_FLAG_LOCK; + UX_RESTORE +#else + + /* Protect the control endpoint semaphore here. It will be unprotected in the + transfer request function. */ + status = _ux_host_semaphore_get(&device -> ux_device_protection_semaphore, UX_WAIT_FOREVER); + + /* Check for status. */ + if (status != UX_SUCCESS) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_SEMAPHORE_ERROR); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_SEMAPHORE_ERROR, configuration, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_SEMAPHORE_ERROR); + } +#endif + + /* Check for the state of the device, if not configured, we are done. */ + if (device -> ux_device_state != UX_DEVICE_CONFIGURED) + { +#if defined(UX_HOST_STANDALONE) + device -> ux_device_flags &= ~UX_DEVICE_FLAG_LOCK; +#else + _ux_host_semaphore_put(&device -> ux_device_protection_semaphore); +#endif + return(UX_SUCCESS); + } + + /* Deactivate classes by command. */ + command.ux_host_class_command_request = UX_HOST_CLASS_COMMAND_DEACTIVATE; + + /* Search for the active configuration. */ + configuration = device -> ux_device_current_configuration; + + /* If device configured configuration must be activated. */ + + /* We have the correct configuration, search the interface(s). */ + interface = configuration -> ux_configuration_first_interface; + + /* Loop to perform the search. */ + while (interface != UX_NULL) + { + + /* Check if an instance of the interface is present. */ + if (interface -> ux_interface_class_instance != UX_NULL) + { + + /* We need to stop the class instance for the device. */ + command.ux_host_class_command_instance = interface -> ux_interface_class_instance; + + /* Call the class. */ + interface -> ux_interface_class -> ux_host_class_entry_function(&command); + } + + /* Move to next interface. */ + interface = interface -> ux_interface_next_interface; + } + + /* The device can now be un-configured. */ + status = _ux_host_stack_device_configuration_reset(device); + +#if defined(UX_HOST_STANDALONE) + device -> ux_device_flags &= ~UX_DEVICE_FLAG_LOCK; +#endif + + /* Return completion status. */ + return(status); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_get.c new file mode 100644 index 00000000..73e4bd5c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_get.c @@ -0,0 +1,136 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_configuration_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns a configuration container based on a device */ +/* handle and a configuration index. */ +/* */ +/* INPUT */ +/* */ +/* device Pointer to device */ +/* configuration_index Index of configuration */ +/* configuration Pointer to configuration */ +/* destination */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_configuration_get(UX_DEVICE *device, UINT configuration_index, + UX_CONFIGURATION **configuration) +{ + +UINT current_configuration_index; +UX_CONFIGURATION *current_configuration; + + /* Do a sanity check on the device handle. */ + if (device -> ux_device_handle != (ULONG) (ALIGN_TYPE) device) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DEVICE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DEVICE_HANDLE_UNKNOWN, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DEVICE_HANDLE_UNKNOWN); + } + + /* Start with the configuration attached to the device. */ + current_configuration = device -> ux_device_first_configuration; + + /* The first configuration has the index 0. */ + current_configuration_index = 0; + + /* Traverse the list of the configurations until we found the right one. */ + while (current_configuration != UX_NULL) + { + + /* Check if the configuration index matches the current one. */ + if (configuration_index == current_configuration_index) + { + + /* Return the configuration pointer. */ + *configuration = current_configuration; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_GET, device, current_configuration, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Return successful completion. */ + return(UX_SUCCESS); + } + + /* Move to the next configuration. */ + current_configuration = current_configuration -> ux_configuration_next_configuration; + + /* Move to the next index. */ + current_configuration_index++; + } + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_CONFIGURATION_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_CONFIGURATION_HANDLE_UNKNOWN, configuration, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return an error. */ + return(UX_CONFIGURATION_HANDLE_UNKNOWN); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_reset.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_reset.c new file mode 100644 index 00000000..8521e1fe --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_reset.c @@ -0,0 +1,131 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_configuration_reset PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function resets the configuration of the device to zero. */ +/* */ +/* INPUT */ +/* */ +/* configuration Pointer to configuration */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_configuration_instance_delete */ +/* Delete configuration instance*/ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* used pointer for current */ +/* selected configuration, */ +/* resulting in version 6.1.4 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* fixed device state support, */ +/* reset device power source, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_configuration_reset(UX_DEVICE *device) +{ + +UX_TRANSFER *transfer_request; +UX_ENDPOINT *control_endpoint; +UX_CONFIGURATION *current_configuration; +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_SELECT, device, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* A configuration is selected. Retrieve the pointer to the control endpoint + and its transfer request. */ + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Check for the state of the device . If the device is already configured, + we need to cancel the existing configuration before resetting it. */ + if (device -> ux_device_state == UX_DEVICE_CONFIGURED) + { + + /* The device is configured. Get the first configuration pointer. */ + current_configuration = device -> ux_device_current_configuration; + + /* Deselect this instance */ + _ux_host_stack_configuration_instance_delete(current_configuration); + } + + /* No configuration is selected now. */ + device -> ux_device_current_configuration = UX_NULL; + + /* Set state of device to ADDRESSED. */ + device -> ux_device_state = UX_DEVICE_ADDRESSED; + + /* Reset power source. */ + device -> ux_device_power_source = UX_DEVICE_BUS_POWERED; + + /* Create a transfer_request for the SET_CONFIGURATION request. No data for this request. */ + transfer_request -> ux_transfer_request_requested_length = 0; + transfer_request -> ux_transfer_request_function = UX_SET_CONFIGURATION; + transfer_request -> ux_transfer_request_type = UX_REQUEST_OUT | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = 0; + transfer_request -> ux_transfer_request_index = 0; + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Return status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_select.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_select.c new file mode 100644 index 00000000..595442ee --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_configuration_select.c @@ -0,0 +1,155 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_configuration_select PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function selects a specific configuration for a device. */ +/* When this configuration is set to the device, by default all the */ +/* device interface and their associated alternate setting 0 is */ +/* activated on the device. If the device/interface class driver */ +/* wishes to change the setting of a particular interface, it needs */ +/* to issue a select interface setting function. */ +/* */ +/* INPUT */ +/* */ +/* configuration Pointer to configuration */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_configuration_instance_create Create configuration */ +/* instance */ +/* _ux_host_stack_configuration_instance_delete Delete configuration */ +/* instance */ +/* _ux_host_stack_configuration_set Set configuration */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* used pointer for current */ +/* selected configuration, */ +/* resulting in version 6.1.4 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* refine power usage check, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_configuration_select(UX_CONFIGURATION *configuration) +{ + +UX_DEVICE *device; +UX_CONFIGURATION *current_configuration; +UINT status; + + /* Check for validity of the configuration handle. */ + if (configuration -> ux_configuration_handle != (ULONG) (ALIGN_TYPE) configuration) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_CONFIGURATION_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_CONFIGURATION_HANDLE_UNKNOWN, configuration, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_CONFIGURATION_HANDLE_UNKNOWN); + } + + /* Get the device container for this configuration. */ + device = configuration -> ux_configuration_device; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_CONFIGURATION_SELECT, device, configuration, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* We need to check the amount of power the bus powered device is consuming + before switch configuration. Otherwise we may run the risk of + an over current fault. */ + if (((configuration -> ux_configuration_descriptor.bmAttributes & UX_CONFIGURATION_DEVICE_SELF_POWERED) == 0) && + (configuration -> ux_configuration_descriptor.MaxPower > UX_DEVICE_MAX_POWER_GET(device))) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_OVER_CURRENT_CONDITION); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_OVER_CURRENT_CONDITION, configuration, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_OVER_CURRENT_CONDITION); + } + + /* Check for the state of the device . If the device is already configured, + we need to cancel the existing configuration before enabling this one. */ + if (device -> ux_device_state == UX_DEVICE_CONFIGURED) + { + + /* The device is configured. Get the first configuration pointer. */ + current_configuration = device -> ux_device_current_configuration; + + /* Deselect this instance */ + _ux_host_stack_configuration_instance_delete(current_configuration); + } + + /* The device can now be configured. */ + status = _ux_host_stack_configuration_set(configuration); + if (status != UX_SUCCESS) + return(status); + + /* Create the configuration instance. */ + status = _ux_host_stack_configuration_instance_create(configuration); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_descriptor_read.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_descriptor_read.c new file mode 100644 index 00000000..b3d2f1fb --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_descriptor_read.c @@ -0,0 +1,212 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_descriptor_read PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads the device descriptor. */ +/* */ +/* INPUT */ +/* */ +/* device Pointer to device */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_transfer_request Process transfer request */ +/* _ux_utility_descriptor_parse Parse descriptor */ +/* _ux_utility_memory_allocate Allocate memory block */ +/* _ux_utility_memory_free Free memory block */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* added bMaxPacketSize0 check,*/ +/* resulting in version 6.1.9 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* added class code checking, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_descriptor_read(UX_DEVICE *device) +{ + +UX_TRANSFER *transfer_request; +UINT status; +UCHAR * descriptor; +UX_ENDPOINT *control_endpoint; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_DESCRIPTOR_READ, device, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Retrieve the pointer to the control endpoint. */ + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Need to allocate memory for the descriptor. */ + descriptor = _ux_utility_memory_allocate(UX_SAFE_ALIGN, UX_CACHE_SAFE_MEMORY, UX_DEVICE_DESCRIPTOR_LENGTH); + if (descriptor == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* Create a transfer_request for the GET_DESCRIPTOR request. The first transfer_request asks + for the first 8 bytes only. This way we will know the real MaxPacketSize + value for the control endpoint. */ + transfer_request -> ux_transfer_request_data_pointer = descriptor; + transfer_request -> ux_transfer_request_requested_length = 8; + transfer_request -> ux_transfer_request_function = UX_GET_DESCRIPTOR; + transfer_request -> ux_transfer_request_type = UX_REQUEST_IN | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = UX_DEVICE_DESCRIPTOR_ITEM << 8; + transfer_request -> ux_transfer_request_index = 0; + +#if defined(UX_HOST_STANDALONE) + device -> ux_device_enum_trans = transfer_request; + status = UX_SUCCESS; + return(status); +#else + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Check for correct transfer and entire descriptor returned. */ + if ((status == UX_SUCCESS) && (transfer_request -> ux_transfer_request_actual_length == 8)) + { + + /* Parse the device descriptor and create the local descriptor. */ + _ux_utility_descriptor_parse(descriptor, _ux_system_device_descriptor_structure, UX_DEVICE_DESCRIPTOR_ENTRIES, + (UCHAR *) &device -> ux_device_descriptor); + } + else + { + + /* Free all used resources. */ + _ux_utility_memory_free(descriptor); + + /* Return completion status. */ + return(status); + } + + /* Validate the bMaxPacketSize0. */ + if (device -> ux_device_descriptor.bMaxPacketSize0 != 8 && + device -> ux_device_descriptor.bMaxPacketSize0 != 16 && + device -> ux_device_descriptor.bMaxPacketSize0 != 32 && + device -> ux_device_descriptor.bMaxPacketSize0 != 64) + { + _ux_utility_memory_free(descriptor); + return(UX_DESCRIPTOR_CORRUPTED); + } + +#if defined(UX_HOST_DEVICE_CLASS_CODE_VALIDATION_ENABLE) + + /* Validate the USB-IF bDeviceClass class code. */ + switch(device -> ux_device_descriptor.bDeviceClass) + { + case 0x00: /* Fall through. */ + case 0x02: /* Fall through. */ + case 0x09: /* Fall through. */ + case 0x11: /* Fall through. */ + case 0xDC: /* Fall through. */ + case 0xEF: /* Fall through. */ + case 0xFF: + break; + default: + + /* Invalid device class code. */ + _ux_utility_memory_free(descriptor); + return(UX_DESCRIPTOR_CORRUPTED); + } +#endif + + /* Update the max packet size value for the endpoint. */ + control_endpoint -> ux_endpoint_descriptor.wMaxPacketSize = device -> ux_device_descriptor.bMaxPacketSize0; + + /* Create a transfer_request for the GET_DESCRIPTOR request. This time, we have the complete length */ + transfer_request -> ux_transfer_request_data_pointer = descriptor; + transfer_request -> ux_transfer_request_requested_length = UX_DEVICE_DESCRIPTOR_LENGTH; + transfer_request -> ux_transfer_request_function = UX_GET_DESCRIPTOR; + transfer_request -> ux_transfer_request_type = UX_REQUEST_IN | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = UX_DEVICE_DESCRIPTOR_ITEM << 8; + transfer_request -> ux_transfer_request_index = 0; + transfer_request -> ux_transfer_request_packet_length = device -> ux_device_descriptor.bMaxPacketSize0; + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Check for correct transfer and entire descriptor returned. */ + if ((status == UX_SUCCESS) && (transfer_request -> ux_transfer_request_actual_length == UX_DEVICE_DESCRIPTOR_LENGTH)) + { + + /* Parse the device descriptor and create the local descriptor. */ + _ux_utility_descriptor_parse(descriptor, _ux_system_device_descriptor_structure, UX_DEVICE_DESCRIPTOR_ENTRIES, + (UCHAR *) &device -> ux_device_descriptor); + } + else + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DESCRIPTOR_CORRUPTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DESCRIPTOR_CORRUPTED, descriptor, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* The device descriptor does not contain the right amount of data. Maybe corruption. */ + status = UX_DESCRIPTOR_CORRUPTED; + } + + /* Free all used resources. */ + _ux_utility_memory_free(descriptor); + + /* Return completion status. */ + return(status); +#endif +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_get.c new file mode 100644 index 00000000..7ae1aed5 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_get.c @@ -0,0 +1,150 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns a device container based on its index. The */ +/* device index start with device 0. Note that the index is a ULONG */ +/* because we could have several controllers and a byte index might */ +/* not be enough. */ +/* */ +/* INPUT */ +/* */ +/* device_index Index of device */ +/* device Destination for device pointer*/ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_get(ULONG device_index, UX_DEVICE **device) +{ + +UX_DEVICE *current_device; +#if UX_MAX_DEVICES > 1 +ULONG current_device_index; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_GET, device_index, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Check if the device index is still within the limits. */ + if (device_index >= UX_SYSTEM_HOST_MAX_DEVICES_GET()) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DEVICE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DEVICE_HANDLE_UNKNOWN, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DEVICE_HANDLE_UNKNOWN); + } + +#if UX_MAX_DEVICES > 1 + + /* Start with the first device. */ + current_device = _ux_system_host -> ux_system_host_device_array; + current_device_index = 0; + + /* Search the list until the end. */ + while (current_device_index < _ux_system_host -> ux_system_host_max_devices) + { + + /* Check to see if this device is existing. */ + if (current_device -> ux_device_handle != UX_UNUSED) + { + + /* Have we reached the index we are looking for? */ + if (device_index == current_device_index) + { + + /* Yes, return the device pointer. */ + *device = current_device; + + /* Return successful completion. */ + return(UX_SUCCESS); + } + } + + /* Move to next device index. */ + current_device_index++; + + /* Move to next device. */ + current_device++; + } +#else + + /* Only one device, just check if it's used. */ + current_device = _ux_system_host -> ux_system_host_device_array; + if (current_device -> ux_device_handle != UX_UNUSED) + { + *device = current_device; + return(UX_SUCCESS); + } +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DEVICE_HANDLE_UNKNOWN, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return error. */ + return(UX_DEVICE_HANDLE_UNKNOWN); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_remove.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_remove.c new file mode 100644 index 00000000..e43dadda --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_remove.c @@ -0,0 +1,216 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_remove PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will remove a USB device from the bus. */ +/* */ +/* INPUT */ +/* */ +/* HCD Pointer to the HCD */ +/* parent The parent device address */ +/* port_index Index of the port on which the*/ +/* change of status occurred */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_device_resources_free Free all device resources */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* used pointer for current */ +/* selected configuration, */ +/* added notification for */ +/* device disconnection, */ +/* resulting in version 6.1.4 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_remove(UX_HCD *hcd, UX_DEVICE *parent, UINT port_index) +{ + +#if UX_MAX_DEVICES > 1 +ULONG container_index; +#endif +UX_DEVICE *device; +UX_CONFIGURATION *configuration; +UX_INTERFACE *interface; +UX_HOST_CLASS_COMMAND command; + + /* We need to find the device descriptor for the removed device. We can find it + with the parent device and the port it was attached to. Start with the first device. */ + device = _ux_system_host -> ux_system_host_device_array; + +#if UX_MAX_DEVICES > 1 + /* Start at the beginning of the list. */ + container_index = 0; + + /* Search the list until the end. */ + while (container_index++ < _ux_system_host -> ux_system_host_max_devices) + { + + /* Until we have found a used entry. */ + if (device -> ux_device_handle != UX_UNUSED) + { + + /* Check for the parent device and the port location and the controller. */ + if( UX_DEVICE_PARENT_MATCH(device, parent) && + UX_DEVICE_PORT_LOCATION_MATCH(device, port_index) && + UX_DEVICE_HCD_MATCH(device, hcd)) + break; + } + + /* Move to the next device entry. */ + device++; + } + + /* Device not found. */ + if (container_index > _ux_system_host -> ux_system_host_max_devices) +#else + UX_PARAMETER_NOT_USED(parent); + UX_PARAMETER_NOT_USED(port_index); + + /* Device is available and HCD is expected. */ + if (device -> ux_device_handle == UX_UNUSED || + !UX_DEVICE_HCD_MATCH(device, hcd)) +#endif + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DEVICE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DEVICE_HANDLE_UNKNOWN, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* We get here when we could not find the device. */ + return(UX_DEVICE_HANDLE_UNKNOWN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_REMOVE, hcd, parent, port_index, device, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* If trace is enabled, unregister this object. */ + UX_TRACE_OBJECT_UNREGISTER(device); + + /* We have found the device to be removed. */ + device -> ux_device_state = UX_DEVICE_REMOVED; + + /* We have found the device to be removed. Initialize the class + command with the generic parameters. */ + command.ux_host_class_command_request = UX_HOST_CLASS_COMMAND_DEACTIVATE; + + /* The device may have a class associated with the device container or its interfaces. */ + if (device -> ux_device_class_instance != UX_NULL) + { + + /* We need to stop the class instance for the device. */ + command.ux_host_class_command_instance = device -> ux_device_class_instance; + + /* Call the class. */ + device -> ux_device_class -> ux_host_class_entry_function(&command); + } + else + { + + /* Search for the active configuration. */ + configuration = device -> ux_device_current_configuration; + + /* If configuration is activated. */ + if (configuration != UX_NULL) + { + + /* We have the correct configuration, search the interface(s). */ + interface = configuration -> ux_configuration_first_interface; + + /* Loop to perform the search. */ + while (interface != UX_NULL) + { + + /* Check if an instance of the interface is present. */ + if (interface -> ux_interface_class_instance != UX_NULL) + { + + /* We need to stop the class instance for the device. */ + command.ux_host_class_command_instance = interface -> ux_interface_class_instance; + + /* Call the class. */ + interface -> ux_interface_class -> ux_host_class_entry_function(&command); + } + + /* Move to next interface. */ + interface = interface -> ux_interface_next_interface; + } + } + } + + /* Notify application for disconnection of existing physical device. */ + if (_ux_system_host -> ux_system_host_change_function) + { + _ux_system_host -> ux_system_host_change_function(UX_DEVICE_DISCONNECTION, UX_NULL, (VOID*)device); + } + + /* Now all the resources for this device must be free. */ + _ux_host_stack_device_resources_free(device); + + /* Decrement the number of devices on this bus. */ + hcd -> ux_hcd_nb_devices--; + + /* We are done with this device removal. */ + return(UX_SUCCESS); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_resources_free.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_resources_free.c new file mode 100644 index 00000000..6648c892 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_resources_free.c @@ -0,0 +1,261 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_resources_free PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will free all the device resources allocated. */ +/* */ +/* INPUT */ +/* */ +/* device Device pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_endpoint_transfer_abort */ +/* Abort transfer */ +/* _ux_host_stack_endpoint_instance_delete */ +/* Delete endpoint instance */ +/* _ux_utility_memory_free Free memory block */ +/* _ux_utility_memory_set Set memory with a value */ +/* _ux_utility_semaphore_delete Semaphore delete */ +/* _ux_utility_thread_schedule_other Sleep thread to let others */ +/* run */ +/* (ux_hcd_entry_function) HCD entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, verified */ +/* memset and memcpy cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_resources_free(UX_DEVICE *device) +{ + +UX_CONFIGURATION *configuration; +UX_INTERFACE *interface; +UX_ENDPOINT *endpoint; +VOID *container; +ULONG current_alternate_setting; +UX_HCD *hcd; +#if UX_MAX_DEVICES > 1 +UINT device_address_byte_index; +UINT device_address_bit_index; +UCHAR device_address_byte; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_RESOURCE_FREE, device, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + +#if defined(UX_HOST_STANDALONE) + + /* Free possible allocated enumeration resources. */ + if (device -> ux_device_flags & UX_DEVICE_FLAG_ENUM) + { + + /* If transfer buffer is not freed, free it. */ + if (device -> ux_device_enum_trans && + device -> ux_device_enum_trans -> ux_transfer_request_data_pointer) + { + _ux_utility_memory_free(device -> ux_device_enum_trans -> + ux_transfer_request_data_pointer); + } + + /* If configuration is not attached, free it. */ + if ((device -> ux_device_enum_state == UX_HOST_STACK_ENUM_CONFIG_DESCR_PARSE) || + ((device -> ux_device_enum_state == UX_HOST_STACK_ENUM_TRANS_WAIT) && + (device -> ux_device_enum_next_state == UX_HOST_STACK_ENUM_CONFIG_DESCR_PARSE))) + { + if (device -> ux_device_enum_inst.configuration && + device -> ux_device_enum_inst.configuration -> + ux_configuration_device == UX_NULL) + { + _ux_utility_memory_free(device -> ux_device_enum_inst.ptr); + } + } + } + + /* Reset device flags. */ + device -> ux_device_flags = 0; + +#endif + + /* Set the alternate setting to zero. */ + current_alternate_setting = 0; + + /* Get the first configuration registered to the device. */ + configuration = device -> ux_device_first_configuration; + + /* Parse all the configurations, remove all resources for the possible configuration. */ + while (configuration != UX_NULL) + { + + /* We have the correct configuration, search the interface(s). */ + interface = configuration -> ux_configuration_first_interface; + + /* Parse all the interfaces. */ + while (interface != UX_NULL) + { + + /* The alternate setting 0 has the selected alternate setting value. */ + if (interface -> ux_interface_descriptor.bAlternateSetting == 0) + current_alternate_setting = interface -> ux_interface_current_alternate_setting; + + /* If this is the selected interface, we need to free all the endpoints + attached to the alternate setting for this interface. */ + endpoint = interface -> ux_interface_first_endpoint; + + /* Parse all the endpoints. */ + while (endpoint != UX_NULL) + { + + /* Check if this is the selected interface. */ + if (interface -> ux_interface_descriptor.bAlternateSetting == current_alternate_setting) + { + + /* Delete the endpoint instance first. */ + _ux_host_stack_endpoint_instance_delete(endpoint); + } + + /* Memorize the endpoint container address. */ + container = (VOID *) endpoint; + + /* Get the next endpoint. */ + endpoint = endpoint -> ux_endpoint_next_endpoint; + + /* Delete the endpoint container. */ + _ux_utility_memory_free(container); + } + + + /* Memorize the interface container address. */ + container = (VOID *) interface; + + /* Get the next interface. */ + interface = interface -> ux_interface_next_interface; + + /* Delete the interface container. */ + _ux_utility_memory_free(container); + } + + /* Memorize this configuration address before we free it. */ + container = (VOID *) configuration; + + /* Move to the next configuration in the list. */ + configuration = configuration -> ux_configuration_next_configuration; + + /* Free the configuration. */ + _ux_utility_memory_free(container); + } + + /* We need the HCD address for the control endpoint removal and to free + the device address. */ + hcd = UX_DEVICE_HCD_GET(device); + + /* Was the control endpoint already created ? */ + if (device -> ux_device_control_endpoint.ux_endpoint_state != 0) + { + + /* There may be pending transactions on the control endpoint. They need to be aborted. */ + _ux_host_stack_endpoint_transfer_abort(&device -> ux_device_control_endpoint); + + /* The enumeration thread needs to sleep a while to allow the application or the class that may be using + the control endpoint to exit properly. */ + _ux_host_thread_schedule_other(UX_THREAD_PRIORITY_ENUM); + + /* The control endpoint should be destroyed at the HCD level. */ + hcd -> ux_hcd_entry_function(hcd, UX_HCD_DESTROY_ENDPOINT, (VOID *) &device -> ux_device_control_endpoint); + } + + /* The semaphore attached to the control endpoint must be destroyed. */ + _ux_host_semaphore_delete(&device -> ux_device_control_endpoint.ux_endpoint_transfer_request.ux_transfer_request_semaphore); + +#if UX_MAX_DEVICES > 1 + /* Check if the device had an assigned address. */ + if (device -> ux_device_address != 0) + { + + /* The USB address of this device can now be returned to the pool + We need the HCD pointer for this operation. */ + + /* Calculate in which byte index the device address belongs. */ + device_address_byte_index = (UINT) (device -> ux_device_address-1)/8; + + /* Now calculate the amount left in the byte index in bit. */ + device_address_bit_index = (UINT) (device -> ux_device_address-1)%8; + + /* Build the mask for the address. */ + device_address_byte = (UCHAR)(1 << device_address_bit_index); + + /* Free the address. */ + hcd -> ux_hcd_address[device_address_byte_index] &= (UCHAR)~device_address_byte; + } +#endif + + /* The semaphore for endpoint 0 protection must be destroyed. */ + _ux_host_semaphore_delete(&device -> ux_device_protection_semaphore); + + /* Now this device can be free and its container return to the pool. */ + _ux_utility_memory_set(device, 0, sizeof(UX_DEVICE)); /* Use case of memset is verified. */ + + /* Mark the device handle as unused. */ + device -> ux_device_handle = UX_UNUSED; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_string_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_string_get.c new file mode 100644 index 00000000..3cc81971 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_device_string_get.c @@ -0,0 +1,149 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_device_string_get PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function obtains the device string descriptor. */ +/* */ +/* INPUT */ +/* */ +/* device Pointer to device instance */ +/* descriptor_buffer Pointer to a buffer to fill */ +/* LANGID or STRING descriptor */ +/* length Length of buffer */ +/* language_id 0 to obtain LANGID descriptor */ +/* valid language ID to obtain */ +/* string descriptor */ +/* string_index Index of the string */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_transfer_request Process transfer request */ +/* _ux_utility_semaphore_get Get Semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 02-02-2021 Chaoqiong Xiao Initial Version 6.1.4 */ +/* 06-02-2021 Chaoqiong Xiao Modified comment(s), and */ +/* removed unnecessary header, */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_device_string_get(UX_DEVICE *device, UCHAR *descriptor_buffer, ULONG length, ULONG language_id, ULONG string_index) +{ +#if defined(UX_HOST_STANDALONE) +UX_INTERRUPT_SAVE_AREA +#endif +UX_ENDPOINT *control_endpoint; +UX_TRANSFER *transfer_request; +UINT status; + + + /* Do a sanity check on the device handle. */ + if (device -> ux_device_handle != (ULONG) (ALIGN_TYPE) device) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DEVICE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DEVICE_HANDLE_UNKNOWN, device, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DEVICE_HANDLE_UNKNOWN); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_DEVICE_STRING_GET, device, descriptor_buffer, length, (language_id << 16) | string_index, UX_TRACE_HOST_CLASS_EVENTS, 0, 0) + + /* We need to get the default control endpoint transfer request pointer. */ + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + +#if defined(UX_HOST_STANDALONE) + UX_DISABLE + if ((device -> ux_device_flags & UX_DEVICE_FLAG_LOCK) || + (transfer_request -> ux_transfer_request_flags & UX_TRANSFER_FLAG_LOCK)) + { + UX_RESTORE + return(UX_BUSY); + } + device -> ux_device_flags |= UX_DEVICE_FLAG_LOCK; + transfer_request -> ux_transfer_request_flags |= + (UX_TRANSFER_FLAG_LOCK | UX_TRANSFER_FLAG_AUTO_DEVICE_UNLOCK); + UX_RESTORE +#else + + /* Protect the control endpoint semaphore here. It will be unprotected in the + transfer request function. */ + status = _ux_host_semaphore_get(&device -> ux_device_protection_semaphore, UX_WAIT_FOREVER); + + /* Check for status. */ + if (status != UX_SUCCESS) + return(UX_SEMAPHORE_ERROR); +#endif + + /* Create a transfer request for the GET_DEVICE_ID request. */ + transfer_request -> ux_transfer_request_data_pointer = descriptor_buffer; + transfer_request -> ux_transfer_request_requested_length = length; + transfer_request -> ux_transfer_request_function = UX_GET_DESCRIPTOR; + transfer_request -> ux_transfer_request_type = UX_REQUEST_IN | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = (UX_STRING_DESCRIPTOR_ITEM << 8) | string_index; + transfer_request -> ux_transfer_request_index = (language_id); + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Return completion status. */ + return(status); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_instance_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_instance_create.c new file mode 100644 index 00000000..d6acf015 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_instance_create.c @@ -0,0 +1,162 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_endpoint_instance_create PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will create an endpoint instance. The HCD layer is */ +/* invoked to create each endpoint and the bandwidth claimed by each */ +/* endpoint is allocated. */ +/* */ +/* INPUT */ +/* */ +/* endpoint Endpoint to delete */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_bandwidth_check Check bandwidth */ +/* _ux_host_stack_bandwidth_claim Claim bandwidth */ +/* _ux_utility_semaphore_create Semaphore create */ +/* (ux_hcd_entry_function) HCD entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 06-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed trace enabled error, */ +/* filled default endpoint */ +/* request endpoint pointer, */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_endpoint_instance_create(UX_ENDPOINT *endpoint) +{ + +UX_HCD *hcd; +UINT status; +UCHAR endpoint_type; + + + /* Obtain the HCD for this endpoint. */ + hcd = UX_DEVICE_HCD_GET(endpoint -> ux_endpoint_device); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_ENDPOINT_INSTANCE_CREATE, endpoint -> ux_endpoint_device, endpoint, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + + /* If the endpoint needs guaranteed bandwidth, check if we have enough */ + endpoint_type = (endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE; + switch (endpoint_type) + { + + case UX_CONTROL_ENDPOINT: + case UX_BULK_ENDPOINT: + + break; + + default: + + /* Check the bandwidth for this endpoint */ + if (_ux_host_stack_bandwidth_check(hcd, endpoint) != UX_SUCCESS) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_NO_BANDWIDTH_AVAILABLE); + + return(UX_NO_BANDWIDTH_AVAILABLE); + } + + + break; + } + + /* Create this endpoint. */ + status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_CREATE_ENDPOINT, (VOID *) endpoint); + + /* Check status. */ + if (status != UX_SUCCESS) + { + + /* Return completion status. */ + return(status); + } + + /* Claim bandwidth if needed. */ + if ((endpoint_type == UX_INTERRUPT_ENDPOINT) || (endpoint_type == UX_ISOCHRONOUS_ENDPOINT)) + { + + /* Claim its bandwidth */ + _ux_host_stack_bandwidth_claim(hcd, endpoint); + } + + /* Create a semaphore for this endpoint to be attached to its transfer request. */ + status = _ux_host_semaphore_create(&endpoint -> ux_endpoint_transfer_request.ux_transfer_request_semaphore, + "ux_transfer_request_semaphore", 0); + + /* Check status. */ + if (status == UX_SUCCESS) + { + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_REGISTER(UX_TRACE_HOST_OBJECT_TYPE_ENDPOINT, endpoint, 0, 0, 0) + + } + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_instance_delete.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_instance_delete.c new file mode 100644 index 00000000..ea5f6870 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_instance_delete.c @@ -0,0 +1,127 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_endpoint_instance_delete PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will delete an endpoint instance. It does not delete */ +/* the endpoint container but it removes the HCD endpoint and reclaims */ +/* the bandwidth. */ +/* */ +/* INPUT */ +/* */ +/* endpoint Endpoint to delete */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_bandwidth_release Release bandwidth */ +/* _ux_utility_semaphore_delete Semaphore delete */ +/* (ux_hcd_entry_function) HCD entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 06-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed trace enabled error, */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_endpoint_instance_delete(UX_ENDPOINT *endpoint) +{ + +UX_HCD *hcd; + + + /* Obtain the HCD for this endpoint. */ + hcd = UX_DEVICE_HCD_GET(endpoint -> ux_endpoint_device); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_ENDPOINT_INSTANCE_DELETE, endpoint -> ux_endpoint_device, endpoint, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Ensure the endpoint had its physical ED allocated. */ + if (endpoint -> ux_endpoint_ed != UX_NULL) + { + + /* Destroy this endpoint. */ + hcd -> ux_hcd_entry_function(hcd, UX_HCD_DESTROY_ENDPOINT, (VOID *) endpoint); + + /* Free the semaphore previously attached to the transfer_request of this endpoint. */ + _ux_host_semaphore_delete(&endpoint -> ux_endpoint_transfer_request.ux_transfer_request_semaphore); + } + + /* If the endpoint requested guaranteed bandwidth, free it now. */ + switch ((endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE) + { + + case UX_CONTROL_ENDPOINT: + case UX_BULK_ENDPOINT: + + break; + + default: + + /* Reclaim its bandwidth. */ + _ux_host_stack_bandwidth_release(hcd, endpoint); + } + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_UNREGISTER(endpoint); + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_reset.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_reset.c new file mode 100644 index 00000000..378b3d2b --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_reset.c @@ -0,0 +1,122 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_endpoint_reset PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function resets an endpoint after a stall or other error */ +/* condition. */ +/* */ +/* INPUT */ +/* */ +/* endpoint Endpoint to abort transfer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_transfer_request Send transfer request */ +/* (ux_hcd_entry_function) HCD entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_endpoint_reset(UX_ENDPOINT *endpoint) +{ + +UX_ENDPOINT *control_endpoint; +UX_TRANSFER *transfer_request; +UX_DEVICE *device; +UX_HCD *hcd; +UINT status; + + + /* Get the device container from the endpoint */ + device = endpoint -> ux_endpoint_device; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_ENDPOINT_RESET, device, endpoint, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Get the control endpoint attached to the device. */ + control_endpoint = &device -> ux_device_control_endpoint; + + /* Retrieve the transfer_request pointer. */ + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Create a transfer_request for the CLEAR_FEATURE request. */ + transfer_request -> ux_transfer_request_data_pointer = UX_NULL; + transfer_request -> ux_transfer_request_requested_length = 0; + transfer_request -> ux_transfer_request_function = UX_CLEAR_FEATURE; + transfer_request -> ux_transfer_request_type = UX_REQUEST_OUT| UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_ENDPOINT; + transfer_request -> ux_transfer_request_value = UX_ENDPOINT_HALT; + transfer_request -> ux_transfer_request_index = endpoint -> ux_endpoint_descriptor.bEndpointAddress; + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Reset the endpoint at the HCD level. */ + if (status == UX_SUCCESS) + { + + /* Pickup HCD pointer. */ + hcd = UX_DEVICE_HCD_GET(device); + + /* Call HCD entry function. */ + status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_RESET_ENDPOINT, endpoint); + } + + /* And return the completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_transfer_abort.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_transfer_abort.c new file mode 100644 index 00000000..8092848c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_endpoint_transfer_abort.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_endpoint_transfer_abort PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function cancel all the transfer_requests attached to an */ +/* endpoint. The endpoint is not reset and its toggle state is left */ +/* the same. */ +/* */ +/* In this version of USBX, there can only be one transfer request */ +/* pending for an endpoint. It is not known at this stage if having */ +/* multiple transfer request is a benefit for USBX but this function */ +/* may be changed one day to add such functionality. */ +/* */ +/* INPUT */ +/* */ +/* endpoint Endpoint to abort transfer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_transfer_request_abort Transfer request abort */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_endpoint_transfer_abort(UX_ENDPOINT *endpoint) +{ + +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_ENDPOINT_TRANSFER_ABORT, endpoint, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Since we only have one transfer_request per endpoint, use the regular + abort transfer request function. */ + status = _ux_host_stack_transfer_request_abort(&endpoint -> ux_endpoint_transfer_request); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_enum_thread_entry.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_enum_thread_entry.c new file mode 100644 index 00000000..63536905 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_enum_thread_entry.c @@ -0,0 +1,119 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_enum_thread_entry PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains the enum thread for USBX. It is in charge of */ +/* the topology changes either from device insertion\extraction on */ +/* the root hub or on a regular hub. */ +/* */ +/* This thread ensures we never have more that 2 instances trying to */ +/* perform a change to the topology (mostly enumeration) for fear that */ +/* more than one device could answer to address 0. */ +/* */ +/* This function is the entry point of the topology thread. It waits */ +/* until one of the HCDs or a hub sets the semaphore to indicate */ +/* there has been a change in the USB topology which could be either */ +/* a insertion or extraction or eventually a hub downstream port */ +/* signal. */ +/* */ +/* This is for RTOS mode. */ +/* */ +/* INPUT */ +/* */ +/* input Not used input */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_rh_change_process Root hub processing */ +/* _ux_utility_semaphore_get Get signal semaphore */ +/* (ux_system_host_enum_hub_function) HUB enum processing function */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* refined macros names, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_enum_thread_entry(ULONG input) +{ + + UX_PARAMETER_NOT_USED(input); + + /* Loop forever waiting for changes signaled through the semaphore. */ + while (1) + { + + /* Wait for the semaphore to be put by the root hub or a regular hub. */ + _ux_host_semaphore_get_norc(&_ux_system_host -> ux_system_host_enum_semaphore, UX_WAIT_FOREVER); + +#if UX_MAX_DEVICES > 1 + /* We try the hub first. For this we look into the USBX project + structure to see if there is at least one hub. */ + if (_ux_system_host -> ux_system_host_enum_hub_function != UX_NULL) + { + + /* Yes, there is a HUB function, call it! */ + _ux_system_host -> ux_system_host_enum_hub_function(); + } +#endif + + /* The signal may be also coming from the root hub, call the root hub handler. */ + _ux_host_stack_rh_change_process(); + } +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_register.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_register.c new file mode 100644 index 00000000..a9c3706e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_register.c @@ -0,0 +1,159 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_hcd_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a USB controller driver with the USBX stack */ +/* and invokes the HCD driver's initialization function. */ +/* */ +/* Note: The C string of hcd_name must be NULL-terminated and the */ +/* length of it (without the NULL-terminator itself) must be no larger */ +/* than UX_MAX_HCD_NAME_LENGTH. */ +/* */ +/* INPUT */ +/* */ +/* hcd_name Name of HCD to register */ +/* hcd_entry_function Entry function of HCD driver */ +/* hcd_param1 Parameter 1 of HCD */ +/* hcd_param2 Parameter 2 of HCD */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check and return C string */ +/* length if no error */ +/* _ux_utility_memory_copy Copy name into HCD structure */ +/* (hcd_init_function) Init function of HCD driver */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, verified */ +/* memset and memcpy cases, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_hcd_register(UCHAR *hcd_name, + UINT (*hcd_init_function)(struct UX_HCD_STRUCT *), ULONG hcd_param1, ULONG hcd_param2) +{ + +UX_HCD *hcd; +UINT status; +#if !defined(UX_NAME_REFERENCED_BY_POINTER) +UINT hcd_name_length = 0; +#endif +#if UX_MAX_HCD > 1 +ULONG hcd_index; +#endif + + + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_HCD_REGISTER, hcd_name, hcd_param1, hcd_param2, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + +#if !defined(UX_NAME_REFERENCED_BY_POINTER) + /* Get the length of the class name (exclude null-terminator). */ + status = _ux_utility_string_length_check(hcd_name, &hcd_name_length, UX_MAX_HCD_NAME_LENGTH); + if (status) + return(status); +#endif + + /* Get HCD. */ + hcd = _ux_system_host -> ux_system_host_hcd_array; + +#if UX_MAX_HCD > 1 + /* We need to parse the controller driver table to find an empty spot. */ + for(hcd_index = 0; hcd_index < _ux_system_host -> ux_system_host_max_hcd; hcd_index++) + { +#endif + + /* Is this slot available? */ + if(hcd -> ux_hcd_status == UX_UNUSED) + { + + /* Yes, setup the new HCD entry. */ + +#if defined(UX_NAME_REFERENCED_BY_POINTER) + hcd -> ux_hcd_name = (const UCHAR *)hcd_name; +#else + + /* Initialize the array of the new controller with its name (include null-terminator). */ + _ux_utility_memory_copy(hcd -> ux_hcd_name, hcd_name, hcd_name_length + 1); /* Use case of memcpy is verified. */ +#endif + + /* Store the hardware resources of the controller */ + hcd -> ux_hcd_io = hcd_param1; + hcd -> ux_hcd_irq = hcd_param2; + + /* This controller is now used */ + hcd -> ux_hcd_status = UX_USED; + + /* And we have one new controller registered. */ + _ux_system_host -> ux_system_host_registered_hcd++; + + /* We are now calling the HCD driver initialization. */ + status = hcd_init_function(hcd); + + /* Return the completion status to the caller. */ + return(status); + } +#if UX_MAX_HCD > 1 + /* Try the next HCD structure */ + hcd++; + } +#endif + + /* We have exhausted the array of the HCDs, return an error. */ + return(UX_MEMORY_INSUFFICIENT); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_thread_entry.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_thread_entry.c new file mode 100644 index 00000000..aadf5275 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_thread_entry.c @@ -0,0 +1,131 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_hcd_thread_entry PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the entry point of the host controller thread. */ +/* The HCD thread is initialized at the system level and the thread */ +/* entry routine is invoked right away. This thread suspends until */ +/* one of the HCD resumes it due to HCD activities. */ +/* */ +/* It's for RTOS mode. */ +/* */ +/* INPUT */ +/* */ +/* input Not used input */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_get Get signal semaphore */ +/* (ux_hcd_entry_function) HCD's entry function */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 11-09-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed registered HCD scan, */ +/* resulting in version 6.1.2 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* refined macros names, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_hcd_thread_entry(ULONG input) +{ + +UINT hcd_index; +UX_HCD *hcd; +UX_INTERRUPT_SAVE_AREA + + UX_PARAMETER_NOT_USED(input); + + /* Loop forever on the semaphore. The semaphore is used to signal that + there is work for one or more HCDs. */ + while (1) + { + + /* Get the semaphore that signals something is available for this + thread to process. */ + _ux_host_semaphore_get_norc(&_ux_system_host -> ux_system_host_hcd_semaphore, UX_WAIT_FOREVER); + +#if UX_MAX_HCD > 1 + /* This thread was awaken by one or more HCD controllers. Check each of the HCDs + to see who posted work to do. */ + for(hcd_index = 0; hcd_index < _ux_system_host -> ux_system_host_max_hcd; hcd_index++) + { +#else + hcd_index = 0; +#endif + + /* Pickup HCD pointer. */ + hcd = &_ux_system_host -> ux_system_host_hcd_array[hcd_index]; + + /* Is there work to do for this HCD? */ + if((hcd -> ux_hcd_status == UX_HCD_STATUS_OPERATIONAL) && (hcd -> ux_hcd_thread_signal !=0)) + { + + /* Yes, call the HCD function to process the work. */ + hcd -> ux_hcd_entry_function(hcd, UX_HCD_PROCESS_DONE_QUEUE, UX_NULL); + UX_DISABLE + hcd -> ux_hcd_thread_signal--; + UX_RESTORE + } + +#if UX_MAX_HCD > 1 + } +#endif + } +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_transfer_request.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_transfer_request.c new file mode 100644 index 00000000..9201c2ec --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_transfer_request.c @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_hcd_transfer_request PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will route the transfer_request to the appropriate */ +/* HCD for transfer. */ +/* */ +/* INPUT */ +/* */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_hcd_entry_function) HCD's entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_hcd_transfer_request(UX_TRANSFER *transfer_request) +{ + +UINT status; +UX_HCD *hcd; + + /* Obtain the HCD. */ + hcd = UX_DEVICE_HCD_GET(transfer_request -> ux_transfer_request_endpoint -> ux_endpoint_device); + + /* Call the HCD entry function to process the transfer request. */ + status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_TRANSFER_REQUEST, (VOID *) transfer_request); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_unregister.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_unregister.c new file mode 100644 index 00000000..495910fd --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hcd_unregister.c @@ -0,0 +1,197 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_hcd_unregister PORTABLE C */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function unregisters a USB host controller driver (HCD) with */ +/* the USBX stack, removes all devices rooted from that controller and */ +/* disable/stop the controller. */ +/* */ +/* INPUT */ +/* */ +/* hcd_name Name of HCD to unregister */ +/* hcd_param1 Parameter 1 of HCD */ +/* hcd_param2 Parameter 2 of HCD */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* UX_SUCCESS HCD unregistered, related */ +/* devices removed and hardware */ +/* disabled/stopped success */ +/* UX_ERROR HCD not found */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check and return C string */ +/* length if no error */ +/* _ux_utility_memory_compare Memory compare */ +/* (ux_hcd_entry_function) HCD dispatch entry function */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* 11-09-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed HCD devices scan, */ +/* used HCD uninit command, */ +/* fixed HCD status scan, */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_hcd_unregister(UCHAR *hcd_name, + ULONG hcd_param1, ULONG hcd_param2) +{ + +UINT status; +UX_DEVICE *device; +UX_HCD *hcd; +#if UX_MAX_CLASS_DRIVER > 1 || UX_MAX_DEVICES > 1 +ULONG scan_index; +#endif +#if !defined(UX_NAME_REFERENCED_BY_POINTER) +UINT hcd_name_length = 0; +#endif + + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_HCD_UNREGISTER, hcd_name, hcd_param1, hcd_param2, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + +#if !defined(UX_NAME_REFERENCED_BY_POINTER) + /* Get the length of the class name (exclude null-terminator). */ + status = _ux_utility_string_length_check(hcd_name, + &hcd_name_length, UX_MAX_HCD_NAME_LENGTH); + if (status) + return(status); +#endif + + /* Get first HCD. */ + hcd = _ux_system_host -> ux_system_host_hcd_array; + + /* Default to not found status. */ + status = UX_FALSE; + +#if UX_MAX_CLASS_DRIVER > 1 + /* We need to parse the controller driver table to find an empty spot. */ + for (scan_index = 0; + scan_index < UX_SYSTEM_HOST_MAX_HCD_GET(); + scan_index++) + { +#endif + + /* Is this slot available and saved hcd_parameters match? */ + if (hcd -> ux_hcd_status != UX_UNUSED && + hcd -> ux_hcd_io == hcd_param1 && + hcd -> ux_hcd_irq == hcd_param2) + { + + + /* Yes, compare the name (with null terminator). */ + status = ux_utility_name_match(hcd -> ux_hcd_name, + hcd_name, hcd_name_length + 1); +#if UX_MAX_CLASS_DRIVER > 1 + + /* Break if name match (found HCD). */ + if (status == UX_TRUE) + break; +#endif + } + +#if UX_MAX_CLASS_DRIVER > 1 + /* Try the next HCD structure */ + hcd ++; + } +#endif + + /* No valid HCD found. */ + if (status != UX_TRUE) + return(UX_ERROR); + + /* Now disable controller. */ + hcd -> ux_hcd_entry_function(hcd, UX_HCD_UNINITIALIZE, UX_NULL); + + /* Get first device. */ + device = _ux_system_host -> ux_system_host_device_array; + +#if UX_MAX_DEVICES > 1 + /* Remove all devices connected to the controller. */ + for (scan_index = 0; + scan_index < _ux_system_host -> ux_system_host_max_devices; + scan_index ++) + { +#else + + /* No device. */ + if (device -> ux_device_handle == UX_UNUSED) + return(UX_SUCCESS); +#endif + + /* Is this device on the HCD root hub? */ + if (UX_DEVICE_HCD_MATCH(device, hcd) && + UX_DEVICE_PARENT_IS_ROOTHUB(device)) + { + + /* Remove the device (and downstream things connected to it). */ + _ux_host_stack_device_remove(hcd, UX_DEVICE_PARENT_GET(device), + UX_DEVICE_PORT_LOCATION_GET(device)); + + /* The device has been removed, so the port is free again. */ + hcd -> ux_hcd_rh_device_connection &= (ULONG) + ~(1 << device -> ux_device_port_location); + } + +#if UX_MAX_DEVICES > 1 + + /* Try the next device. */ + device ++; + } +#endif + + /* And we have one new controller unregistered. */ + _ux_system_host -> ux_system_host_registered_hcd --; + + return(UX_SUCCESS); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hnp_polling_thread_entry.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hnp_polling_thread_entry.c new file mode 100644 index 00000000..08fc6d01 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_hnp_polling_thread_entry.c @@ -0,0 +1,229 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +#if defined(UX_OTG_SUPPORT) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_hnp_polling_thread_entry PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is awaken every 2 seconds to check if there is a */ +/* OTG device on the bus and if so perform a GET_STATUS as the device */ +/* may request a change of role. */ +/* */ +/* INPUT */ +/* */ +/* none */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_transfer_request Transfer request */ +/* _ux_utility_thread_sleep Sleep thread */ +/* _ux_utility_semaphore_get Get semaphore */ +/* _ux_utility_memory_allocate Allocate memory */ +/* _ux_utility_memory_free Free memory */ +/* _ux_host_stack_role_swap Swapping role */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* used pointer for current */ +/* selected configuration, */ +/* resulting in version 6.1.4 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* refined macros names, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_hnp_polling_thread_entry(ULONG argument) +{ + +UINT hcd_index; +UX_DEVICE *device; +UX_CONFIGURATION *configuration; +UX_ENDPOINT *control_endpoint; +UX_TRANSFER *transfer_request; +UX_HCD *hcd; +UCHAR *otg_status; +ULONG port_index; +ULONG port_status; +ULONG container_index; +UINT status; + + UX_PARAMETER_NOT_USED(argument); + + /* This thread goes on forever once started. */ + while(1) + { + + /* We need to wake every 2 seconds or so. */ + _ux_utility_thread_sleep(UX_OTG_HNP_THREAD_SLEEP_TIME); + + /* We need to parse the controller driver table to find all controllers that registered + as OTG. */ + for (hcd_index = 0; hcd_index < _ux_system_host -> ux_system_host_registered_hcd; hcd_index++) + { + + /* Pickup HCD pointer. */ + hcd = &_ux_system_host -> ux_system_host_hcd_array[hcd_index]; + + /* Check type of controller. Is it OTG capable ? Must be operational too. */ + if ((hcd -> ux_hcd_otg_capabilities & UX_HCD_OTG_CAPABLE) && + (hcd -> ux_hcd_status == UX_HCD_STATUS_OPERATIONAL)) + { + + /* Yes, we can parse the root hub and see if any devices attached to it. */ + for (port_index = 0; port_index < hcd -> ux_hcd_nb_root_hubs; port_index++) + { + + /* Call HCD for port status. */ + port_status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_GET_PORT_STATUS, (VOID *)((ALIGN_TYPE)port_index)); + + /* Check return status. */ + if (port_status != UX_PORT_INDEX_UNKNOWN) + { + + /* the port_status value is valid and will tell us if there is + a device attached\detached on the downstream port and if the port is powered. */ + if ((port_status & UX_PS_CCS) && (port_status & UX_PS_PPS)) + { + + /* There is a device attached to one of the root hub port. Parse the device + to find out which one it is. */ + device = _ux_system_host -> ux_system_host_device_array; + + /* Start at the beginning of the list. */ + container_index = 0; + + /* Search the list until the end. */ + while (container_index++ < UX_SYSTEM_HOST_MAX_DEVICES_GET()) + { + + /* Until we have found a used entry. */ + if (device -> ux_device_handle != UX_UNUSED) + { + + /* Check for the parent device and the port location and the controller. */ + if(UX_DEVICE_PORT_LOCATION_MATCH(device, port_index) && + UX_DEVICE_HCD_MATCH(device, hcd)) + { + + /* We have a device on a OTG port. But is it a OTG HNP capable device ? + We need to parse the configuration until we find the one current. */ + configuration = device -> ux_device_current_configuration; + + /* Check for OTG HNP support. */ + if (configuration -> ux_configuration_otg_capabilities & UX_OTG_HNP_SUPPORT) + { + + /* Allocate memory for the OTG status. */ + otg_status = _ux_utility_memory_allocate(UX_SAFE_ALIGN, UX_CACHE_SAFE_MEMORY, 16); + + /* Check for status. */ + if (otg_status == UX_NULL) + return; + + /* Retrieve the control endpoint and the transfer request associated with it. */ + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Protect the control endpoint semaphore here. It will be unprotected in the + transfer request function. */ + status = _ux_host_semaphore_get(&device -> ux_device_protection_semaphore, UX_WAIT_FOREVER); + + /* Perform a GET_STATUS on this device to see if it wants to become the host. */ + /* Create a transfer_request for the SET_CONFIGURATION request. No data for this request. */ + transfer_request -> ux_transfer_request_data_pointer = otg_status; + transfer_request -> ux_transfer_request_requested_length = 1; + transfer_request -> ux_transfer_request_function = UX_GET_STATUS; + transfer_request -> ux_transfer_request_type = UX_REQUEST_IN | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = 0; + transfer_request -> ux_transfer_request_index = UX_OTG_STATUS_SELECTOR; + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Check completion status. */ + if(status == UX_SUCCESS && transfer_request -> ux_transfer_request_actual_length == 1) + { + + /* We have an answer from the device. Check the HNP flag. */ + if (*otg_status & UX_OTG_HOST_REQUEST_FLAG) + { + + /* The device has requested a Host swap. Initiate the command and perform the + stopping of the host. */ + _ux_host_stack_role_swap(device); + } + + } + + /* Free all used resources. */ + _ux_utility_memory_free(otg_status); + + } + } + } + + /* Move to the next device entry. */ + device++; + + } + } + } + } + } + } + } +} +#endif /* #if defined(UX_OTG_SUPPORT) */ diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_initialize.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_initialize.c new file mode 100644 index 00000000..718ae806 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_initialize.c @@ -0,0 +1,387 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + +UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_MULC_ULONG(sizeof(UX_HCD), UX_MAX_HCD), UX_MAX_HCD_mul_ovf) +UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_MULC_ULONG(sizeof(UX_HOST_CLASS), UX_MAX_CLASS_DRIVER), UX_MAX_CLASS_DRIVER_mul_ovf) +UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_MULC_ULONG(sizeof(UX_DEVICE), UX_MAX_DEVICES), UX_MAX_DEVICES_mul_ovf) + +#ifndef UX_HOST_HNP_POLLING_THREAD_STACK_SIZE +#define UX_HOST_HNP_POLLING_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +#endif + +/* Defined USBX host variables. */ + +UX_SYSTEM_HOST *_ux_system_host; + +/* Define table of periodic tree entries, properly indexed. */ + +UINT _ux_system_host_hcd_periodic_tree_entries[32] = { + 0x00, 0x10, 0x08, 0x18, 0x04, 0x14, 0x0c, 0x1c, + 0x02, 0x12, 0x0a, 0x1a, 0x06, 0x16, 0x0e, 0x1e, + 0x01, 0x11, 0x09, 0x19, 0x05, 0x15, 0x0d, 0x1d, + 0x03, 0x13, 0x0b, 0x1b, 0x07, 0x17, 0x0f, 0x1f}; + +/* Define the names of all the USB Classes of USBX. */ + +UCHAR _ux_system_host_class_hub_name[] = "ux_host_class_hub"; +UCHAR _ux_system_host_class_printer_name[] = "ux_host_class_printer"; +UCHAR _ux_system_host_class_storage_name[] = "ux_host_class_storage"; +UCHAR _ux_system_host_class_hid_name[] = "ux_host_class_hid"; +UCHAR _ux_system_host_class_audio_name[] = "ux_host_class_audio"; +UCHAR _ux_system_host_class_cdc_acm_name[] = "ux_host_class_cdc_acm"; +UCHAR _ux_system_host_class_cdc_dlc_name[] = "ux_host_class_cdc_dlc"; +UCHAR _ux_system_host_class_cdc_ecm_name[] = "ux_host_class_cdc_ecm"; +UCHAR _ux_system_host_class_prolific_name[] = "ux_host_class_prolific"; +UCHAR _ux_system_host_class_pima_name[] = "ux_host_class_pima"; +UCHAR _ux_system_host_class_dpump_name[] = "ux_host_class_dpump"; +UCHAR _ux_system_host_class_asix_name[] = "ux_host_class_asix"; +UCHAR _ux_system_host_class_swar_name[] = "ux_host_class_sierra_wireless"; +UCHAR _ux_system_host_class_gser_name[] = "ux_host_class_generic_serial"; +UCHAR _ux_system_host_class_hid_client_remote_control_name[] = "ux_host_class_hid_client_remote_control"; +UCHAR _ux_system_host_class_hid_client_mouse_name[] = "ux_host_class_hid_client_mouse"; +UCHAR _ux_system_host_class_hid_client_keyboard_name[] = "ux_host_class_hid_client_keyboard"; + +/* Define the name of all the USB Host Controllers of USBX. */ + +UCHAR _ux_system_host_hcd_ohci_name[] = "ux_hcd_ohci"; +UCHAR _ux_system_host_hcd_ehci_name[] = "ux_hcd_ehci"; +UCHAR _ux_system_host_hcd_isp1161_name[] = "ux_hcd_isp1161"; +UCHAR _ux_system_host_hcd_isp1362_name[] = "ux_hcd_isp1362"; +UCHAR _ux_system_host_hcd_sh2_name[] = "ux_hcd_rx"; +UCHAR _ux_system_host_hcd_rx_name[] = "ux_hcd_sh2"; +UCHAR _ux_system_host_hcd_pic32_name[] = "ux_hcd_pic32"; +UCHAR _ux_system_host_hcd_stm32_name[] = "ux_hcd_stm32"; +UCHAR _ux_system_host_hcd_musb_name[] = "ux_hcd_musb"; +UCHAR _ux_system_host_hcd_atm7_name[] = "ux_hcd_atm7"; +UCHAR _ux_system_host_hcd_simulator_name[] = "ux_hcd_simulator"; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_initialize PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes all the host code for USBX to work on a */ +/* specific platform. */ +/* */ +/* INPUT */ +/* */ +/* (ux_system_host_change_function) Function pointer to the */ +/* callback function for a */ +/* device change */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_allocate Allocate host memory */ +/* _ux_utility_semaphore_create Create host semaphore */ +/* _ux_utility_mutex_create Create host mutex */ +/* _ux_utility_thread_create Create host thread */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, used UX prefix */ +/* to refer to TX symbols */ +/* instead of using them */ +/* directly, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_initialize(UINT (*ux_system_host_change_function)(ULONG, UX_HOST_CLASS *, VOID *)) +{ + +UINT status; +UCHAR *memory; +#if defined(UX_HOST_STANDALONE) +UINT i; +UX_DEVICE *device; +#endif + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_INITIALIZE, 0, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Initialize some of the global so that we don't have to recompile the + core code when one item is adjusted. */ + _ux_system_host -> ux_system_host_max_ed = UX_MAX_ED; + _ux_system_host -> ux_system_host_max_td = UX_MAX_TD; + _ux_system_host -> ux_system_host_max_iso_td = UX_MAX_ISO_TD; + UX_SYSTEM_HOST_MAX_CLASS_SET(UX_MAX_CLASS_DRIVER); + UX_SYSTEM_HOST_MAX_HCD_SET(UX_MAX_HCD); + UX_SYSTEM_HOST_MAX_DEVICES_SET(UX_MAX_DEVICES); + + /* Set the change device function address. */ + _ux_system_host -> ux_system_host_change_function = ux_system_host_change_function; + + /* Allocate memory for the HCDs. + * sizeof(UX_HCD)*UX_MAX_HCD overflow is checked outside of the function. + */ + memory = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_HCD)*UX_MAX_HCD); + + /* Check for successful allocation. */ + if (memory == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* Set to success by default. */ + status = UX_SUCCESS; + + /* Store memory in system structure. */ + _ux_system_host -> ux_system_host_hcd_array = (UX_HCD *) memory; + + /* Allocate memory for the classes. + * sizeof(UX_HOST_CLASS)*UX_MAX_CLASS_DRIVER overflow is checked outside of the function. + */ + memory = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_HOST_CLASS)*UX_MAX_CLASS_DRIVER); + + /* Check for successful allocation. */ + if (memory == UX_NULL) + status = UX_MEMORY_INSUFFICIENT; + else + + /* Store memory in system structure. */ + _ux_system_host -> ux_system_host_class_array = (UX_HOST_CLASS *) memory; + + /* Allocate memory for the device containers. + * sizeof(UX_DEVICE)*UX_MAX_DEVICES overflow is checked outside of the function. + */ + if (status == UX_SUCCESS) + { + memory = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_DEVICE)*UX_MAX_DEVICES); + + /* Check for successful allocation. */ + if(memory == UX_NULL) + status = UX_MEMORY_INSUFFICIENT; + else + + /* Store memory in system structure. */ + _ux_system_host -> ux_system_host_device_array = (UX_DEVICE *) memory; + +#if defined(UX_HOST_STANDALONE) + + /* Add devices to the enumeration list, with ENUM flags cleared. */ + if (status == UX_SUCCESS) + { + + /* Start from the last device instance. */ + device = &_ux_system_host -> ux_system_host_device_array[UX_MAX_DEVICES - 1]; + + /* Insert all devices to enumeration list head. */ + for (i = 0; i < UX_MAX_DEVICES; i ++) + { + + /* Insert to head. */ + device -> ux_device_enum_next = _ux_system_host -> ux_system_host_enum_device; + _ux_system_host -> ux_system_host_enum_device = device; + + /* Next device. */ + device --; + } + } +#endif + + } + +#if !defined(UX_HOST_STANDALONE) + /* Obtain enough stack for the two USBX host threads. */ + if (status == UX_SUCCESS) + { + _ux_system_host -> ux_system_host_enum_thread_stack = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, + UX_HOST_ENUM_THREAD_STACK_SIZE); + + /* Check for successful allocation. */ + if (_ux_system_host -> ux_system_host_enum_thread_stack == UX_NULL) + status = UX_MEMORY_INSUFFICIENT; + } + + /* Allocate another stack area. */ + if (status == UX_SUCCESS) + { + _ux_system_host -> ux_system_host_hcd_thread_stack = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, + UX_HOST_HCD_THREAD_STACK_SIZE); + + /* Check for successful allocation. */ + if (_ux_system_host -> ux_system_host_hcd_thread_stack == UX_NULL) + status = UX_MEMORY_INSUFFICIENT; + } + + /* Create the semaphores used by the hub and root hub to awake the enumeration thread. */ + if (status == UX_SUCCESS) + { + status = _ux_utility_semaphore_create(&_ux_system_host -> ux_system_host_enum_semaphore, "ux_system_host_enum_semaphore", 0); + if(status != UX_SUCCESS) + status = UX_SEMAPHORE_ERROR; + } + + /* Create the semaphores used by the HCD to perform the completion phase of transfer_requests. */ + if (status == UX_SUCCESS) + { + status = _ux_utility_semaphore_create(&_ux_system_host -> ux_system_host_hcd_semaphore, "ux_system_host_hcd_semaphore", 0); + if(status != UX_SUCCESS) + status = UX_SEMAPHORE_ERROR; + } + + /* Create the enumeration thread of USBX. */ + if (status == UX_SUCCESS) + { + status = _ux_utility_thread_create(&_ux_system_host -> ux_system_host_enum_thread, "ux_system_host_enum_thread", _ux_host_stack_enum_thread_entry, + 0, _ux_system_host -> ux_system_host_enum_thread_stack, + UX_HOST_ENUM_THREAD_STACK_SIZE, UX_THREAD_PRIORITY_ENUM, + UX_THREAD_PRIORITY_ENUM, UX_NO_TIME_SLICE, UX_AUTO_START); + + /* Check the completion status. */ + if(status != UX_SUCCESS) + status = UX_THREAD_ERROR; + } + + /* Create the HCD thread of USBX. */ + if (status == UX_SUCCESS) + { + status = _ux_utility_thread_create(&_ux_system_host -> ux_system_host_hcd_thread, "ux_host_stack_hcd_thread", _ux_host_stack_hcd_thread_entry, + 0, _ux_system_host -> ux_system_host_hcd_thread_stack, + UX_HOST_HCD_THREAD_STACK_SIZE, UX_THREAD_PRIORITY_HCD, + UX_THREAD_PRIORITY_HCD, UX_NO_TIME_SLICE,UX_AUTO_START); + + /* Check the completion status. */ + if(status != UX_SUCCESS) + status = UX_THREAD_ERROR; + } +#endif + +#if defined(UX_OTG_SUPPORT) && !defined(UX_OTG_STANDALONE) + /* Allocate another stack area for the HNP polling thread. */ + if (status == UX_SUCCESS) + { + _ux_system_host -> ux_system_host_hnp_polling_thread_stack = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, + UX_HOST_HNP_POLLING_THREAD_STACK_SIZE); + + /* Check for successful allocation. */ + if (_ux_system_host -> ux_system_host_hnp_polling_thread_stack == UX_NULL) + status = UX_MEMORY_INSUFFICIENT; + } + + /* Create the HNP polling thread of USBX. */ + if (status == UX_SUCCESS) + { + status = _ux_utility_thread_create(&_ux_system_host -> ux_system_host_hnp_polling_thread, "ux_host_stack_hnp_polling_thread", _ux_host_stack_hnp_polling_thread_entry, + 0, _ux_system_host -> ux_system_host_hnp_polling_thread_stack, + UX_HOST_HNP_POLLING_THREAD_STACK_SIZE, UX_THREAD_PRIORITY_ENUM, + UX_THREAD_PRIORITY_ENUM, UX_NO_TIME_SLICE, UX_AUTO_START); + + /* Check the completion status. */ + if (status != UX_SUCCESS) + status = UX_THREAD_ERROR; + + /* Return success (SUCCESS). */ + else + return(status); + } + + /* Free up resources on error cases. */ + + /* Last resource, _ux_system_host -> ux_system_host_hnp_polling_thread is not created or created error, + * no need to delete it. */ + + /* Free _ux_system_host -> ux_system_host_hnp_polling_thread_stack. */ + if (_ux_system_host -> ux_system_host_hnp_polling_thread_stack) + _ux_utility_memory_free(_ux_system_host -> ux_system_host_hnp_polling_thread_stack); + + /* Delete _ux_system_host -> ux_system_host_hcd_thread. */ + if (_ux_system_host -> ux_system_host_hcd_thread.tx_thread_id != 0) + _ux_utility_thread_delete(&_ux_system_host -> ux_system_host_hcd_thread); +#else + + /* Return completion status to caller if success. */ + if (status == UX_SUCCESS) + return(status); + + /* Free up resources on error cases. */ + + /* Last resource, _ux_system_host -> ux_system_host_hcd_thread is not created or created error, + * no need to delete it. */ +#endif + +#if !defined(UX_HOST_STANDALONE) + /* Delete _ux_system_host -> ux_system_host_enum_thread. */ + if (_ux_system_host -> ux_system_host_enum_thread.tx_thread_id != 0) + _ux_utility_thread_delete(&_ux_system_host -> ux_system_host_enum_thread); + + /* Delete _ux_system_host -> ux_system_host_hcd_semaphore. */ + if (_ux_system_host -> ux_system_host_hcd_semaphore.tx_semaphore_id != 0) + _ux_utility_semaphore_delete(&_ux_system_host -> ux_system_host_hcd_semaphore); + + /* Delete _ux_system_host -> ux_system_host_enum_semaphore. */ + if (_ux_system_host -> ux_system_host_enum_semaphore.tx_semaphore_id != 0) + _ux_utility_semaphore_delete(&_ux_system_host -> ux_system_host_enum_semaphore); + + /* Free _ux_system_host -> ux_system_host_hcd_thread_stack. */ + if (_ux_system_host -> ux_system_host_hcd_thread_stack) + _ux_utility_memory_free(_ux_system_host -> ux_system_host_hcd_thread_stack); + + /* Free _ux_system_host -> ux_system_host_enum_thread_stack. */ + if (_ux_system_host -> ux_system_host_enum_thread_stack) + _ux_utility_memory_free(_ux_system_host -> ux_system_host_enum_thread_stack); +#endif + + /* Free _ux_system_host -> ux_system_host_device_array. */ + if (_ux_system_host -> ux_system_host_device_array) + _ux_utility_memory_free(_ux_system_host -> ux_system_host_device_array); + + /* Free _ux_system_host -> ux_system_host_class_array. */ + if (_ux_system_host -> ux_system_host_class_array) + _ux_utility_memory_free(_ux_system_host -> ux_system_host_class_array); + + /* Free _ux_system_host -> ux_system_host_hcd_array. */ + _ux_utility_memory_free(_ux_system_host -> ux_system_host_hcd_array); + + /* Return completion status to caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_endpoint_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_endpoint_get.c new file mode 100644 index 00000000..7a8dcfc7 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_endpoint_get.c @@ -0,0 +1,134 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_interface_endpoint_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns an endpoint container based on the interface */ +/* handle and an endpoint index. */ +/* */ +/* INPUT */ +/* */ +/* interface Pointer to interface */ +/* endpoint_index Index of endpoint to get */ +/* endpoint Destination for endpoint */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_interface_endpoint_get(UX_INTERFACE *interface, UINT endpoint_index, UX_ENDPOINT **endpoint) +{ + +UINT current_endpoint_index; +UX_ENDPOINT *current_endpoint; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_INTERFACE_ENDPOINT_GET, interface, endpoint_index, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Do a sanity check on the interface handle. */ + if (interface -> ux_interface_handle != (ULONG) (ALIGN_TYPE) interface) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_INTERFACE_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_INTERFACE_HANDLE_UNKNOWN, interface, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_INTERFACE_HANDLE_UNKNOWN); + } + + /* Start with the endpoint attached to the interface. */ + current_endpoint = interface -> ux_interface_first_endpoint; + + /* The first endpoint has the index 0. */ + current_endpoint_index = 0; + + /* Traverse the list of the endpoints until we found the right one. */ + while (current_endpoint != UX_NULL) + { + + /* Check if the endpoint index matches the current one. */ + if (endpoint_index == current_endpoint_index) + { + + /* Setup the return endpoint pointer. */ + *endpoint=current_endpoint; + + /* Return success to the caller. */ + return(UX_SUCCESS); + } + + /* Move to the next endpoint. */ + current_endpoint = current_endpoint -> ux_endpoint_next_endpoint; + + /* Move to the next index. */ + current_endpoint_index++; + } + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_ENDPOINT_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_ENDPOINT_HANDLE_UNKNOWN, endpoint, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return an error! */ + return(UX_ENDPOINT_HANDLE_UNKNOWN); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_instance_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_instance_create.c new file mode 100644 index 00000000..5e336ec7 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_instance_create.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_interface_instance_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will create an interface instance. It creates each */ +/* endpoint associated with the interface. */ +/* */ +/* INPUT */ +/* */ +/* interface Pointer to interface */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_endpoint_instance_create Create instance endpoint */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_interface_instance_create(UX_INTERFACE *interface) +{ + +UX_ENDPOINT *endpoint; +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_INTERFACE_INSTANCE_CREATE, interface, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Obtain the first endpoint for this alternate setting. */ + endpoint = interface -> ux_interface_first_endpoint; + + /* Loop to create each endpoint. */ + while (endpoint != UX_NULL) + { + + /* Create an endpoint for the instance. */ + status = _ux_host_stack_endpoint_instance_create(endpoint); + + /* Check status, the controller may have refused the endpoint creation. */ + if (status != UX_SUCCESS) + + /* An error occurred at the controller level. */ + return(status); + + /* Move to next endpoint. */ + endpoint = endpoint -> ux_endpoint_next_endpoint; + } + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_REGISTER(UX_TRACE_HOST_OBJECT_TYPE_INTERFACE, interface, 0, 0, 0); + + /* Return completion status. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_instance_delete.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_instance_delete.c new file mode 100644 index 00000000..a6e9dbf7 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_instance_delete.c @@ -0,0 +1,101 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_interface_instance_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will delete an interface instance. It does not delete */ +/* the interface container, but it removes all the endpoints */ +/* associated with alternate setting. */ +/* */ +/* INPUT */ +/* */ +/* interface Pointer to interface */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_endpoint_instance_delete Delete endpoint */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_interface_instance_delete(UX_INTERFACE *interface) +{ + +UX_ENDPOINT *endpoint; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_INTERFACE_INSTANCE_DELETE, interface, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_UNREGISTER(interface); + + /* Obtain the first endpoint for this alternate setting. */ + endpoint = interface -> ux_interface_first_endpoint; + + /* Loop to delete each endpoint. */ + while (endpoint != UX_NULL) + { + + /* Delete endpoint. */ + _ux_host_stack_endpoint_instance_delete(endpoint); + + /* Move to next endpoint. */ + endpoint = endpoint -> ux_endpoint_next_endpoint; + } + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_set.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_set.c new file mode 100644 index 00000000..25e4b239 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_set.c @@ -0,0 +1,108 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_interface_set PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a setting of an alternate setting for a */ +/* specific interface. */ +/* */ +/* INPUT */ +/* */ +/* interface Pointer to interface */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_hcd_transfer_request HCD transfer request */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_interface_set(UX_INTERFACE *interface) +{ + +UX_DEVICE *device; +UX_CONFIGURATION *configuration; +UX_TRANSFER *transfer_request; +UINT status; +UX_ENDPOINT *control_endpoint; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_INTERFACE_SET, interface, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Retrieve the pointer to the control endpoint and its transfer_request. + From the interface we go back to the configuration, then the device. + The device contains the default control endpoint container. */ + configuration = interface -> ux_interface_configuration; + device = configuration -> ux_configuration_device; + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Create a transfer_request for the SET_INTERFACE request. No data for this request */ + transfer_request -> ux_transfer_request_requested_length = 0; + transfer_request -> ux_transfer_request_function = UX_SET_INTERFACE; + transfer_request -> ux_transfer_request_type = UX_REQUEST_OUT | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_INTERFACE; + transfer_request -> ux_transfer_request_index = (USHORT) interface -> ux_interface_descriptor.bInterfaceNumber; + transfer_request -> ux_transfer_request_value = (USHORT) interface -> ux_interface_descriptor.bAlternateSetting; + + /* Send request. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* Return status completion. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_setting_select.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_setting_select.c new file mode 100644 index 00000000..9fa99ecc --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interface_setting_select.c @@ -0,0 +1,205 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_interface_setting_select PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function selects a specific alternate setting for a given */ +/* interface belonging to the selected configuration. */ +/* */ +/* INPUT */ +/* */ +/* interface Pointer to interface */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_interface_instance_create Create interface instance */ +/* _ux_host_stack_interface_instance_delete Delete interface instance */ +/* _ux_host_stack_interface_set Set interface instance */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_interface_setting_select(UX_INTERFACE *interface) +{ + +UX_CONFIGURATION *configuration; +UX_INTERFACE *current_interface; +UX_INTERFACE *previous_interface; +UX_INTERFACE *main_interface; +UINT current_interface_number; +UINT current_alternate_setting; +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_INTERFACE_SETTING_SELECT, interface, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Check this alternate setting container. It must be valid before + we continue. */ + if (interface -> ux_interface_handle != (ULONG) (ALIGN_TYPE) interface) + { + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_INTERFACE_HANDLE_UNKNOWN, interface, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_INTERFACE_HANDLE_UNKNOWN); + } + + /* From the interface, get the configuration container and the first + interface hooked to this configuration. */ + configuration = interface -> ux_interface_configuration; + current_interface_number = interface -> ux_interface_descriptor.bInterfaceNumber; + current_interface = configuration -> ux_configuration_first_interface; + + /* Remember the main interface to store the next alternate setting. We set the main interface + to the first interface to keep the compiler happy. */ + main_interface = current_interface; + + /* In order to keep the compiler happy, we reset the alternate setting. */ + current_alternate_setting = 0; + previous_interface = UX_NULL; + + /* Search for the current alternate setting for this interface. + All its endpoints will need to be destroyed. + Since interfaces in the parent configuration should be linked together + in correct way, just find it in while loop. + */ + while (1) + { + + /* Try to locate the first interface container in the interface chain which + has the same interface number as the one supplied by the caller. */ + if (current_interface -> ux_interface_descriptor.bInterfaceNumber == current_interface_number) + { + + /* The alternate setting 0 of this interface has the current selected + alternate setting. */ + if (current_interface -> ux_interface_descriptor.bAlternateSetting == 0) + { + + /* Set the alternate setting. */ + current_alternate_setting = current_interface -> ux_interface_current_alternate_setting; + + /* Remember the main interface to store the next alternate setting. */ + main_interface = current_interface; + + } + + /* See if the current alternate setting matches that of the interface alternate setting. */ + if (current_alternate_setting == current_interface -> ux_interface_descriptor.bAlternateSetting) + { + + /* Yes, save the current alternate setting. */ + previous_interface = current_interface; + + /* Then delete the current interface. */ + _ux_host_stack_interface_instance_delete(current_interface); + + /* We are done in this loop. */ + break; + + } + } + + /* Move to the next interface. */ + current_interface = current_interface -> ux_interface_next_interface; + } + + /* Remember the new alternate setting. */ + main_interface -> ux_interface_current_alternate_setting = interface -> ux_interface_descriptor.bAlternateSetting; + + /* Now, the interface must be created with the new alternate setting. */ + status = _ux_host_stack_interface_instance_create(interface); + + /* If we could not create it, we return to the default one. */ + if (status != UX_SUCCESS) + { + + /* Then delete the failed interface. */ + _ux_host_stack_interface_instance_delete(interface); + + /* Error, reset the main interface alternate setting to the default. */ + main_interface -> ux_interface_current_alternate_setting = current_alternate_setting; + + /* Re-create the previous interface with the old alternate setting. */ + _ux_host_stack_interface_instance_create(previous_interface); + + /* Return error status. */ + return(status); + } + + /* Issue a SET_INTERFACE command to the target device. */ + status = _ux_host_stack_interface_set(interface); + + /* Check completion status. */ + if (status != UX_SUCCESS) + { + + /* Error, reset the main interface alternate setting to the default. */ + main_interface -> ux_interface_current_alternate_setting = current_alternate_setting; + + /* Delete the current interface. */ + _ux_host_stack_interface_instance_delete(interface); + + /* Re-create the previous interface with the old alternate setting. */ + _ux_host_stack_interface_instance_create(previous_interface); + + /* Return error status. */ + return(status); + } + + /* Return to caller. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interfaces_scan.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interfaces_scan.c new file mode 100644 index 00000000..5e0418ff --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_interfaces_scan.c @@ -0,0 +1,203 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_interfaces_scan PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function scans all the interfaces and alternate settings for */ +/* particular configuration. */ +/* */ +/* INPUT */ +/* */ +/* configuration Where the interface(s) will */ +/* be attached */ +/* descriptor Contains the entire descriptor*/ +/* for this configuration */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_descriptor_parse Parse interface descriptor */ +/* _ux_host_stack_new_interface_create Create new interface */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_interfaces_scan(UX_CONFIGURATION *configuration, UCHAR * descriptor) +{ + +ULONG total_configuration_length; +UINT descriptor_length; +UINT descriptor_type; +ULONG status; +ULONG interface_association_descriptor_present; +ULONG interface_in_iad_count; +UX_INTERFACE_ASSOCIATION_DESCRIPTOR interface_association; + + /* Retrieve the size of all the configuration descriptor. */ + total_configuration_length = configuration -> ux_configuration_descriptor.wTotalLength; + + /* Set the IAD to false. */ + interface_association_descriptor_present = UX_FALSE; + + /* Set the IAD interface count to zero. */ + interface_in_iad_count = 0; + + /* Scan the entire descriptor and search for interfaces. We should also ensure that + the descriptor is valid by verifying the length of each descriptor scanned. */ + while (total_configuration_length) + { + + /* Gather the length and type of the descriptor. */ + descriptor_length = *descriptor; + descriptor_type = *(descriptor + 1); + + /* Make sure this descriptor has at least the minimum length. */ + if (descriptor_length < 3) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DESCRIPTOR_CORRUPTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DESCRIPTOR_CORRUPTED, descriptor, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DESCRIPTOR_CORRUPTED); + } + + /* Check the type for an interface association descriptor. */ + if (descriptor_type == UX_INTERFACE_ASSOCIATION_DESCRIPTOR_ITEM) + { + + /* Parse the interface association descriptor and make it machine independent. */ + _ux_utility_descriptor_parse(descriptor, + _ux_system_interface_association_descriptor_structure, + UX_INTERFACE_ASSOCIATION_DESCRIPTOR_ENTRIES, + (UCHAR *) &interface_association); + + /* Retrieve the CLASS/SUBCLASS from descriptor and store it in the configuration instance. */ + configuration -> ux_configuration_iad_class = interface_association.bFunctionClass; + configuration -> ux_configuration_iad_subclass = interface_association.bFunctionSubClass; + configuration -> ux_configuration_iad_protocol = interface_association.bFunctionProtocol; + + /* We have an IAD. */ + interface_association_descriptor_present = UX_TRUE; + + /* Memorize the number of interfaces attached to this IAD. */ + interface_in_iad_count = interface_association.bInterfaceCount; + } + + /* Check the type for an interface descriptor. */ + if (descriptor_type == UX_INTERFACE_DESCRIPTOR_ITEM) + { + + /* We have found an interface descriptor. This descriptor contains at least + the default alternate setting (with value 0) and may have others. */ + status = _ux_host_stack_new_interface_create(configuration, descriptor, total_configuration_length); + + /* Are we within an IAD ? */ + if (interface_association_descriptor_present == UX_TRUE) + { + + /* Decrement the number of interfaces attached here. */ + interface_in_iad_count--; + + /* Are we at the end of the interface count ? */ + if (interface_in_iad_count == 0) + { + + /* Set the IAD to false now. */ + interface_association_descriptor_present = UX_FALSE; + + /* Reset the IAD Class/Subclass/Protocol. */ + configuration -> ux_configuration_iad_class = 0; + configuration -> ux_configuration_iad_subclass = 0; + configuration -> ux_configuration_iad_protocol = 0; + + } + } + + /* Check return status. */ + if(status != UX_SUCCESS) + return(status); + } + + /* Check the type for an OTG descriptor. */ + if (descriptor_type == UX_OTG_DESCRIPTOR_ITEM) + + /* Retrieve the bmAttributes for SRP/HNP support. */ + configuration -> ux_configuration_otg_capabilities = (ULONG) *(descriptor + UX_OTG_BM_ATTRIBUTES); + + /* Verify if the descriptor is still valid. */ + if (descriptor_length > total_configuration_length) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DESCRIPTOR_CORRUPTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DESCRIPTOR_CORRUPTED, descriptor, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DESCRIPTOR_CORRUPTED); + } + /* Jump to the next descriptor if we have not reached the end. */ + descriptor += descriptor_length; + + /* And adjust the length left to parse in the descriptor. */ + total_configuration_length -= descriptor_length; + } + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_configuration_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_configuration_create.c new file mode 100644 index 00000000..8e57f454 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_configuration_create.c @@ -0,0 +1,118 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_new_configuration_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a new configuration for the current device */ +/* a device can have multiple configurations. */ +/* */ +/* INPUT */ +/* */ +/* device Pointer to the descriptor */ +/* for the device */ +/* configuration_descriptor Configuration descriptor */ +/* previously parsed */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_new_configuration_create(UX_DEVICE *device, UX_CONFIGURATION *configuration) +{ + +UX_CONFIGURATION *list_configuration; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_NEW_CONFIGURATION_CREATE, device, configuration, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* The device that owns this configuration is memorized in the + configuration container itself, easier for back chaining. */ + configuration -> ux_configuration_device = device; + + /* Save the configuration handle in the container, this is for ensuring the + configuration container is not corrupted. */ + configuration -> ux_configuration_handle = (ULONG) (ALIGN_TYPE) configuration; + + /* There is 2 cases for the creation of the configuration descriptor + if this is the first one, the configuration descriptor is hooked + to the device. If it is not the first one, the configuration is + hooked to the end of the chain of configurations. */ + if (device -> ux_device_first_configuration == UX_NULL) + { + device -> ux_device_first_configuration = configuration; + } + else + { + + /* Get the pointer to the first configuration. */ + list_configuration = device -> ux_device_first_configuration; + + /* And traverse until we have reached the end of the configuration list. */ + while (list_configuration -> ux_configuration_next_configuration != UX_NULL) + { + list_configuration = list_configuration -> ux_configuration_next_configuration; + } + + /* Hook the new configuration. */ + list_configuration -> ux_configuration_next_configuration = configuration; + } + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_device_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_device_create.c new file mode 100644 index 00000000..aa414de5 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_device_create.c @@ -0,0 +1,289 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_new_device_create PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a new device on the USB. It may be called */ +/* either by a hub or by the root hub. */ +/* */ +/* INPUT */ +/* */ +/* HCD HCD that owns that device */ +/* device_owner Either a root hub instance */ +/* or a hub instance */ +/* port_index Port the new device is mounted*/ +/* device_speed Speed at which the device is */ +/* running (low, full, high) */ +/* port_power_available Power available on the root */ +/* or hub port. This value is */ +/* used to ensure that the */ +/* device can be configured */ +/* without creating an */ +/* OVER_CURRENT condition on */ +/* the bus */ +/* created_device Destination to fill created */ +/* device instance */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* An Error code could be an indication that the device could not be */ +/* created in which case the error is fatal to the enumeration and */ +/* will not be retried. The error code can also indicate a failure */ +/* for the device to respond to the GET_DEVICE_DESCRIPTOR. This error */ +/* is not fatal and the caller should retry the enumeration process */ +/* after the port to which the device is attached has been reset. */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_class_device_scan Scan class devices */ +/* _ux_host_stack_class_interface_scan Scan class interfaces */ +/* _ux_host_stack_device_address_set Set device address */ +/* _ux_host_stack_device_descriptor_read Read device descriptor */ +/* _ux_host_stack_configuration_enumerate */ +/* Enumerate device config */ +/* _ux_host_stack_new_device_get Get new device */ +/* _ux_utility_semaphore_create Create a semaphore */ +/* (ux_hcd_entry_function) HCD entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added a new parameter to */ +/* return created device, */ +/* resulting in version 6.1.4 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* reset device power source, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_new_device_create(UX_HCD *hcd, UX_DEVICE *device_owner, + UINT port_index, UINT device_speed, + UINT port_max_power, + UX_DEVICE **created_device) +{ + +UX_DEVICE *device; +UINT status; +UX_ENDPOINT *control_endpoint; + + +#if UX_MAX_DEVICES > 1 + /* Verify the number of devices attached to the HCD already. Normally a HCD + can have up to 127 devices but that can be tailored. */ + if (hcd -> ux_hcd_nb_devices > UX_MAX_USB_DEVICES) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_TOO_MANY_DEVICES); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_TOO_MANY_DEVICES, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_TOO_MANY_DEVICES); + } +#endif + + /* Get a new device container to store this new device. */ + device = _ux_host_stack_new_device_get(); + if (device == UX_NULL) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_TOO_MANY_DEVICES); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_TOO_MANY_DEVICES, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_TOO_MANY_DEVICES); + } + + /* Store the device instance. */ + *created_device = device; + + /* Increment the number of devices on this bus. */ + hcd -> ux_hcd_nb_devices++; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_NEW_DEVICE_CREATE, hcd, device_owner, port_index, device, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* At this stage the device is attached but not configured. + we don't have to worry about power consumption yet. + Initialize the device structure. */ + device -> ux_device_handle = (ULONG) (ALIGN_TYPE) device; + device -> ux_device_state = UX_DEVICE_ATTACHED; + device -> ux_device_address = 0; + device -> ux_device_speed = device_speed; + UX_DEVICE_MAX_POWER_SET(device, port_max_power); + UX_DEVICE_PARENT_SET(device, device_owner); + UX_DEVICE_HCD_SET(device, hcd); + UX_DEVICE_PORT_LOCATION_SET(device, port_index); + device -> ux_device_power_source = UX_DEVICE_BUS_POWERED; + + /* Create a semaphore for the device. This is to protect endpoint 0 mostly for OTG HNP polling. The initial count is 1 as + a mutex mechanism. */ + status = _ux_host_semaphore_create(&device -> ux_device_protection_semaphore, "ux_host_endpoint0_semaphore", 1); + + /* Check semaphore creation. */ + if (status != UX_SUCCESS) + { + + /* Return error. Device resources that have been allocated until this + point should be freed by the caller via _ux_host_stack_device_resources_free. */ + return(UX_SEMAPHORE_ERROR); + } + + /* Initialize the default control endpoint permanently attached + to the device. */ + control_endpoint = &device -> ux_device_control_endpoint; + control_endpoint -> ux_endpoint = (ULONG) (ALIGN_TYPE) control_endpoint; + control_endpoint -> ux_endpoint_next_endpoint = UX_NULL; + control_endpoint -> ux_endpoint_interface = UX_NULL; + control_endpoint -> ux_endpoint_device = device; + control_endpoint -> ux_endpoint_transfer_request.ux_transfer_request_endpoint = control_endpoint; + + /* Create a semaphore for this endpoint to be attached to its transfer request. */ + status = _ux_host_semaphore_create(&control_endpoint -> ux_endpoint_transfer_request.ux_transfer_request_semaphore, "ux_host_transfer_request_semaphore", 0); + + /* Check semaphore creation. */ + if (status != UX_SUCCESS) + { + + /* Return error. Device resources that have been allocated until this + point should be freed by the caller via _ux_host_stack_device_resources_free. */ + return(UX_SEMAPHORE_ERROR); + } + + /* If the device is running in high speed the default max packet size for the control endpoint is 64. + All other speeds the size is 8. */ + if (device_speed == UX_HIGH_SPEED_DEVICE) + control_endpoint -> ux_endpoint_descriptor.wMaxPacketSize = UX_DEFAULT_HS_MPS; + else + control_endpoint -> ux_endpoint_descriptor.wMaxPacketSize = UX_DEFAULT_MPS; + + /* Create the default control endpoint at the HCD level. */ + status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_CREATE_ENDPOINT, (VOID *) control_endpoint); + +#if defined(UX_HOST_STANDALONE) + if (status == UX_SUCCESS) + { + + /* Now control endpoint is ready, set state to running. */ + control_endpoint -> ux_endpoint_state = UX_ENDPOINT_RUNNING; + + /* Setup default control request timeout. */ + control_endpoint -> ux_endpoint_transfer_request.ux_transfer_request_timeout_value = + UX_MS_TO_TICK_NON_ZERO(UX_CONTROL_TRANSFER_TIMEOUT); + + /* Set default control request mode to wait. */ + control_endpoint -> ux_endpoint_transfer_request.ux_transfer_request_flags |= + UX_TRANSFER_FLAG_AUTO_WAIT; + } + + /* Enumeration steps will be done in task state machine. */ + +#else + + /* Going on to do enumeration (requests). */ + if (status == UX_SUCCESS) + { + + /* Now control endpoint is ready, set state to running. */ + control_endpoint -> ux_endpoint_state = UX_ENDPOINT_RUNNING; + + /* Set the address of the device. The first time a USB device is + accessed, it responds to the address 0. We need to change the address + to a free device address between 1 and 127 ASAP. */ + status = _ux_host_stack_device_address_set(device); + if (status == UX_SUCCESS) + { + + /* Get the device descriptor. */ + status = _ux_host_stack_device_descriptor_read(device); + if (status == UX_SUCCESS) + { + + /* Get the configuration descriptor(s) for the device + and parse all the configuration, interface, endpoints... */ + status = _ux_host_stack_configuration_enumerate(device); + } + } + } + + /* Check the status of the previous operations. If there was an + error during any of the phases, the device resources must be + freed based on if we want to retry. */ + if (status == UX_SUCCESS) + { + + /* The device, configuration(s), interface(s), endpoint(s) are + now in order for this device to work. No configuration is set + yet. First we need to find a class driver that wants to own + it. There is no need to have an orphan device in a configured state. */ + status = _ux_host_stack_class_device_scan(device); + if (status == UX_NO_CLASS_MATCH) + { + + status = _ux_host_stack_class_interface_scan(device); + } + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_REGISTER(UX_TRACE_HOST_OBJECT_TYPE_DEVICE, hcd, device_owner, port_index, 0); + } +#endif + + /* Return status. If there's an error, device resources that have been + allocated until this point should be freed by the caller via _ux_host_stack_device_resources_free. */ + return(status); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_device_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_device_get.c new file mode 100644 index 00000000..bc871415 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_device_get.c @@ -0,0 +1,118 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_new_device_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function obtains a free device container for the new device. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* UX_DEVICE pointer */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_set Set memory to a value */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, verified */ +/* memset and memcpy cases, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UX_DEVICE *_ux_host_stack_new_device_get(VOID) +{ + +#if UX_MAX_DEVICES > 1 +ULONG container_index; +#endif +UX_DEVICE *device; + + + /* Start with the first device. */ + device = _ux_system_host -> ux_system_host_device_array; + +#if UX_MAX_DEVICES > 1 + /* Reset the container index. */ + container_index = 0; + + /* Search the list until the end. */ + while (container_index++ < _ux_system_host -> ux_system_host_max_devices) +#endif + { + + /* Until we have found an unused entry. */ + if (device -> ux_device_handle == UX_UNUSED) + { + + /* Reset the entire entry. */ + _ux_utility_memory_set(device, 0, sizeof(UX_DEVICE)); /* Use case of memset is verified. */ + + /* This entry is now used. */ + device -> ux_device_handle = UX_USED; + + /* Return the device pointer. */ + return(device); + } +#if UX_MAX_DEVICES > 1 + + /* Move to the next device entry. */ + device++; +#endif + } + + /* No unused devices, return NULL. */ + return(UX_NULL); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_endpoint_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_endpoint_create.c new file mode 100644 index 00000000..ae68fe29 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_endpoint_create.c @@ -0,0 +1,220 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_new_endpoint_create PORTABLE C */ +/* 6.1.9 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a new endpoint for the current interface */ +/* scanned. The endpoint is hooked to the interface that owns it. */ +/* It is not active yet until either the default interface for the */ +/* configuration is selected by a SET_CONFIGURATION or when an */ +/* alternate setting for this interface is set. */ +/* */ +/* INPUT */ +/* */ +/* interface Interface container that owns */ +/* this endpoint */ +/* endpoint_pointer Pointer to a unparsed */ +/* endpoint descriptor */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_descriptor_parse Parse the descriptor */ +/* _ux_utility_memory_allocate Allocate memory block */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* added descriptor validate, */ +/* resulting in version 6.1.9 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_new_endpoint_create(UX_INTERFACE *interface, + UCHAR * interface_endpoint) +{ + +UX_ENDPOINT *endpoint; +UX_ENDPOINT *list_endpoint; +ULONG endpoint_type; +ULONG packet_size; +ULONG n_tran; + + /* Obtain memory for storing this new endpoint. */ + endpoint = (UX_ENDPOINT *) _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_ENDPOINT)); + if (endpoint == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_NEW_ENDPOINT_CREATE, interface, endpoint, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Save the endpoint handle in the container, this is for ensuring the + endpoint container is not corrupted. */ + endpoint -> ux_endpoint = (ULONG) (ALIGN_TYPE) endpoint; + + /* The endpoint container has a built in transfer_request. + The transfer_request needs to point to the endpoint as well. */ + endpoint -> ux_endpoint_transfer_request.ux_transfer_request_endpoint = endpoint; + + /* Save the pointer to the device. This is useful for the HCD layer. */ + endpoint -> ux_endpoint_device = interface -> ux_interface_configuration -> ux_configuration_device; + + /* Parse the interface descriptor and make it machine independent. */ + _ux_utility_descriptor_parse(interface_endpoint, + _ux_system_endpoint_descriptor_structure, + UX_ENDPOINT_DESCRIPTOR_ENTRIES, + (UCHAR *) &endpoint -> ux_endpoint_descriptor); + + /* Check endpoint size and interval to see if they are valid. */ + endpoint_type = endpoint -> ux_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE; + + /* Endpoint size should not be zero. */ + if (endpoint -> ux_endpoint_descriptor.wMaxPacketSize == 0) + { + _ux_utility_memory_free(endpoint); + return(UX_DESCRIPTOR_CORRUPTED); + } + + /* Control/bulk endpoint, 8, 16, 32, 64, ... 512 can be accepted. + Note non-standard size in 2^N is accepted since they really works. */ + if (endpoint_type == UX_CONTROL_ENDPOINT || endpoint_type == UX_BULK_ENDPOINT) + { + for (packet_size = 8; packet_size <= 512; packet_size <<= 1) + { + if (packet_size == endpoint -> ux_endpoint_descriptor.wMaxPacketSize) + break; + } + + /* If endpoint size not valid, return error. */ + if (packet_size > 512) + { + _ux_utility_memory_free(endpoint); + return(UX_DESCRIPTOR_CORRUPTED); + } + } + + /* Interrupt/isochronous endpoint, max 1024 and 3 transactions can be accepted. */ + if (endpoint_type == UX_INTERRUPT_ENDPOINT || endpoint_type == UX_ISOCHRONOUS_ENDPOINT) + { + + /* Max size over 1024 is not allowed. */ + packet_size = endpoint -> ux_endpoint_descriptor.wMaxPacketSize & UX_MAX_PACKET_SIZE_MASK; + if (packet_size > 1024) + { + _ux_utility_memory_free(endpoint); + return(UX_DESCRIPTOR_CORRUPTED); + } + + /* Number transaction over 2 additional is not allowed. */ + n_tran = endpoint -> ux_endpoint_descriptor.wMaxPacketSize & UX_MAX_NUMBER_OF_TRANSACTIONS_MASK; + if (n_tran >= UX_MAX_NUMBER_OF_TRANSACTIONS_MASK) + { + _ux_utility_memory_free(endpoint); + return(UX_DESCRIPTOR_CORRUPTED); + } + + /* Isochronous/high speed interrupt interval should be 1~16. */ + if (endpoint -> ux_endpoint_descriptor.bInterval < 1) + { + _ux_utility_memory_free(endpoint); + return(UX_DESCRIPTOR_CORRUPTED); + } + if ((endpoint_type == UX_ISOCHRONOUS_ENDPOINT) || + (interface -> ux_interface_configuration -> ux_configuration_device + -> ux_device_speed == UX_HIGH_SPEED_DEVICE) + ) + { + if (endpoint -> ux_endpoint_descriptor.bInterval > 16) + { + _ux_utility_memory_free(endpoint); + return(UX_DESCRIPTOR_CORRUPTED); + } + } + + /* Save final packet size. */ + packet_size *= (n_tran + 1); + } + + /* Save transfer packet size. */ + endpoint -> ux_endpoint_transfer_request.ux_transfer_request_packet_length = packet_size; + + /* The interface that owns this endpoint is memorized in the + endpoint container itself, easier for back chaining. */ + endpoint -> ux_endpoint_interface = interface; + + /* There is 2 cases for the creation of the endpoint descriptor + if this is the first one, the endpoint descriptor is hooked + to the interface. + If it is not the first one, the endpoint is hooked to the + end of the chain of endpoints. */ + if (interface -> ux_interface_first_endpoint == UX_NULL) + { + + interface -> ux_interface_first_endpoint = endpoint; + } + else + { + + list_endpoint = interface -> ux_interface_first_endpoint; + + /* Traverse the list until the end. */ + while (list_endpoint -> ux_endpoint_next_endpoint != UX_NULL) + list_endpoint = list_endpoint -> ux_endpoint_next_endpoint; + + /* Hook the endpoint. */ + list_endpoint -> ux_endpoint_next_endpoint = endpoint; + } + + /* Return successful status. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_interface_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_interface_create.c new file mode 100644 index 00000000..25548091 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_new_interface_create.c @@ -0,0 +1,209 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_new_interface_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a new interface for the current configuration */ +/* scanned. A device has at least 1 alternate setting per interface */ +/* which is the default one. */ +/* */ +/* The interface is hooked to the configuration that owns it. */ +/* */ +/* From the interface descriptor, all the endpoints are hooked but */ +/* not activated. */ +/* */ +/* INPUT */ +/* */ +/* configuration Configuration container that */ +/* owns this interface */ +/* interface_pointer Pointer to a unparsed */ +/* interface descriptor */ +/* length Length remaining in this */ +/* descriptor */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_new_endpoint_create Create new endpoint */ +/* _ux_utility_descriptor_parse Parse the descriptor */ +/* _ux_utility_memory_allocate Allocate memory block */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_new_interface_create(UX_CONFIGURATION *configuration, + UCHAR * descriptor, ULONG length) +{ + +UX_INTERFACE *list_interface; +UX_INTERFACE *interface; +UINT number_endpoints; +UINT descriptor_length; +UINT descriptor_type; +UINT status; +UCHAR *this_interface_descriptor; + + /* Obtain memory for storing this new interface. */ + interface = (UX_INTERFACE *) _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_INTERFACE)); + + /* If no memory left, exit with error. */ + if (interface == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* Save the interface handle in the container, this is for ensuring the + interface container is not corrupted. */ + interface -> ux_interface_handle = (ULONG) (ALIGN_TYPE) interface; + + /* Parse the interface descriptor and make it machine independent. */ + _ux_utility_descriptor_parse(descriptor, + _ux_system_interface_descriptor_structure, + UX_INTERFACE_DESCRIPTOR_ENTRIES, + (UCHAR *) &interface -> ux_interface_descriptor); + + /* The configuration that owns this interface is memorized in the + interface container itself, easier for back chaining. */ + interface -> ux_interface_configuration = configuration; + + /* If the interface belongs to an IAD, remember the IAD Class/SubClass/Protocol. */ + interface -> ux_interface_iad_class = configuration -> ux_configuration_iad_class; + interface -> ux_interface_iad_subclass = configuration -> ux_configuration_iad_subclass; + interface -> ux_interface_iad_protocol = configuration -> ux_configuration_iad_protocol; + + /* There is 2 cases for the creation of the interface descriptor + if this is the first one, the interface descriptor is hooked + to the configuration. If it is not the first one, the interface + is hooked to the end of the chain of interfaces. */ + if (configuration -> ux_configuration_first_interface == UX_NULL) + { + configuration -> ux_configuration_first_interface = interface; + } + else + { + + list_interface = configuration -> ux_configuration_first_interface; + + /* Traverse the list until we reach the end */ + while (list_interface -> ux_interface_next_interface != UX_NULL) + { + + list_interface = list_interface -> ux_interface_next_interface; + } + + /* Hook the interface. */ + list_interface -> ux_interface_next_interface = interface; + } + + /* Traverse the interface in search of all endpoints that belong to it. + We need the length remaining in the descriptor and the number of endpoints + reported for this interface. */ + number_endpoints = interface -> ux_interface_descriptor.bNumEndpoints; + + this_interface_descriptor = descriptor; + + while (length && (number_endpoints != 0)) + { + + /* Gather the length and type of the descriptor. */ + descriptor_length = *descriptor; + descriptor_type = *(descriptor+1); + + /* make sure this descriptor has at least the minimum length. */ + if (descriptor_length < 3) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DESCRIPTOR_CORRUPTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DESCRIPTOR_CORRUPTED, descriptor, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DESCRIPTOR_CORRUPTED); + } + + /* Check the type for an interface descriptor. */ + if (descriptor_type == UX_ENDPOINT_DESCRIPTOR_ITEM) + { + + /* We have found an endpoint descriptor for this interface. */ + status = _ux_host_stack_new_endpoint_create(interface, descriptor); + + /* Check return status. */ + if(status != UX_SUCCESS) + return(status); + + number_endpoints--; + } + + /* Verify if the descriptor is still valid, or we moved to next interface. */ + if ((descriptor_length > length) || (descriptor_type == UX_INTERFACE_DESCRIPTOR_ITEM && descriptor != this_interface_descriptor)) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ENUMERATOR, UX_DESCRIPTOR_CORRUPTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DESCRIPTOR_CORRUPTED, descriptor, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DESCRIPTOR_CORRUPTED); + } + + /* Jump to the next descriptor if we have not reached the end. */ + descriptor += descriptor_length; + length -= descriptor_length; + } + + /* Return success! */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_change_process.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_change_process.c new file mode 100644 index 00000000..dc4f1d4a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_change_process.c @@ -0,0 +1,179 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_rh_change_process PORTABLE C */ +/* 6.1.2 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks for changes in topology in each of the */ +/* installed HCDs. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_rh_device_insertion Process device insertion */ +/* _ux_host_stack_rh_device_extraction Process device extraction */ +/* (ux_hcd_entry_function) HCD entry function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used new interrupt macros, */ +/* resulting in version 6.1 */ +/* 11-09-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed registered HCD scan, */ +/* resulting in version 6.1.2 */ +/* */ +/**************************************************************************/ +VOID _ux_host_stack_rh_change_process(VOID) +{ + +UX_HCD *hcd; +UINT hcd_index; +ULONG port_status; +UINT port_index; +UX_INTERRUPT_SAVE_AREA + + /* This thread was maybe awaken by one or more HCD controllers. Check each + of the HCD to see where there has been a change of topology. */ + for(hcd_index = 0; hcd_index < UX_SYSTEM_HOST_MAX_HCD_GET(); hcd_index++) + { + + /* Pickup HCD pointer. */ + hcd = &_ux_system_host -> ux_system_host_hcd_array[hcd_index]; + + /* Is this HCD operational? */ + if (hcd -> ux_hcd_status == UX_HCD_STATUS_OPERATIONAL) + { + + /* On each port of the root hub of the controller, get the port status */ + for (port_index = 0; port_index < hcd -> ux_hcd_nb_root_hubs; port_index++) + { + + /* Was there any activity on this port ? */ + if (hcd -> ux_hcd_root_hub_signal[port_index] != 0) + { + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_RH_CHANGE_PROCESS, port_index, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Reset that port activity signal. */ + UX_DISABLE + hcd -> ux_hcd_root_hub_signal[port_index]--; + UX_RESTORE + + /* Call HCD for port status. */ + port_status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_GET_PORT_STATUS, (VOID *)((ALIGN_TYPE)port_index)); + + /* Check return status. */ + if (port_status != UX_PORT_INDEX_UNKNOWN) + { + + /* The port_status value is valid and will tell us if there is + a device attached\detached on the downstream port. */ + if (port_status & UX_PS_CCS) + { + + /* There is a device attached to this port. Check if we know + about it. If not, this is a device insertion signal. */ + if ((hcd -> ux_hcd_rh_device_connection & (ULONG)(1 << port_index)) == 0) + { + + /* We have a simple device insertion, we have not lost any signals. + the root hub and the stack enumeration module are in synch. */ + _ux_host_stack_rh_device_insertion(hcd,port_index); + } + else + { + /* We can get here when there has been multiple events on the hardware root hub + but we may have missed them of they were too close or the stack got too busy. + We check the number of events in the root hub signal. If it is not zero + we are out of synch, meaning we got a disconnection followed very quickly + by a insertion. */ + + if (hcd -> ux_hcd_root_hub_signal[port_index] != 0) + { + + /* We need to get back in synch now. */ + UX_DISABLE + hcd -> ux_hcd_root_hub_signal[port_index] = 0; + UX_RESTORE + + /* First extract the device. */ + _ux_host_stack_rh_device_extraction(hcd,port_index); + + /* Now, insert it again. */ + _ux_host_stack_rh_device_insertion(hcd,port_index); + + + } + + } + } + else + { + + /* There is no device attached to this port. Check if we know + about it. If not, this is a device removal signal. */ + if ((hcd -> ux_hcd_rh_device_connection & (ULONG)(1 << port_index)) !=0) + { + _ux_host_stack_rh_device_extraction(hcd,port_index); + } + } + } + } + } + } + } +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_device_extraction.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_device_extraction.c new file mode 100644 index 00000000..9702da82 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_device_extraction.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_rh_device_extraction PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a device extraction on a downstream port */ +/* of the root hub pointed by HCD. */ +/* */ +/* INPUT */ +/* */ +/* HCD Pointer to HCD structure */ +/* port_index Port index of insertion */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_host_stack_device_remove Remove device */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_rh_device_extraction(UX_HCD *hcd, UINT port_index) +{ + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_RH_DEVICE_EXTRACTION, hcd, port_index, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Ask the stack to remove the device, pass the value 0 as the parent root hub. */ + _ux_host_stack_device_remove(hcd, 0, port_index); + + /* The device has been removed, so the port is free again. */ + hcd -> ux_hcd_rh_device_connection &= (ULONG)~(1 << port_index); + + /* That command should never fail! */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_device_insertion.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_device_insertion.c new file mode 100644 index 00000000..db425fdf --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_rh_device_insertion.c @@ -0,0 +1,251 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_rh_device_insertion PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles a device insertion on a downstream port of */ +/* the root hub pointed by HCD. */ +/* */ +/* INPUT */ +/* */ +/* HCD Pointer to HCD structure */ +/* port_index Port index of insertion */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_delay_ms Thread sleep */ +/* _ux_host_stack_new_device_create New device create */ +/* _ux_host_stack_device_remove Device remove */ +/* (hcd_entry_function) Entry function of HCD driver */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* checked HCD status before */ +/* retrying enumeration, */ +/* resulting in version 6.1 */ +/* 02-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* handled more fail cases, */ +/* updated internal call, */ +/* added notification for */ +/* device connection, */ +/* added disconnection check */ +/* in enumeration retries, */ +/* resulting in version 6.1.4 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_rh_device_insertion(UX_HCD *hcd, UINT port_index) +{ +#if defined(UX_HOST_STANDALONE) +UX_DEVICE *device; +UINT status; + + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_RH_DEVICE_INSERTION, hcd, port_index, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Anyway there is device connected. */ + hcd -> ux_hcd_rh_device_connection |= (ULONG)(1 << port_index); + + /* Create a new device slot for enumeration. */ + status = _ux_host_stack_new_device_create(hcd, UX_NULL, port_index, + UX_FULL_SPEED_DEVICE, UX_MAX_SELF_POWER, + &device); + + /* Link the device in enumeration list. */ + if (status == UX_SUCCESS) + { + + /* Set enumeration flag to process enumeration sequence. */ + device -> ux_device_flags |= UX_DEVICE_FLAG_ENUM; + + /* Done success. */ + return(UX_SUCCESS); + } + +#else +UX_DEVICE *device; +UINT index_loop; +UINT device_speed; +ULONG port_status; +UINT status; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_RH_DEVICE_INSERTION, hcd, port_index, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* Perform a PORT_ENABLE command. */ + port_status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_ENABLE_PORT, (VOID *)((ALIGN_TYPE)port_index)); + + /* Check return status. */ + if (port_status == UX_PORT_INDEX_UNKNOWN) + return(port_status); + + /* A debounce interval with a minimum duration of 100 ms on attach. */ + _ux_utility_delay_ms(100); + + /* The first attempts to do a device enumeration may fail. + Typically, after the port is reset and the first command is sent to + the device, there is no answer. In this case, we reset the port again + and retry. Usually that does the trick! */ + for (index_loop = 0; index_loop < UX_RH_ENUMERATION_RETRY; index_loop++) + { + + /* Now we have to do a PORT_RESET command. */ + port_status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_RESET_PORT, (VOID *)((ALIGN_TYPE)port_index)); + if (port_status == UX_SUCCESS) + { + + /* The port reset phase was successful. Before we invoke the device enumeration function, + we need to know the speed of the device. */ + port_status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_GET_PORT_STATUS, (VOID *)((ALIGN_TYPE)port_index)); + + /* Check return status. */ + if (port_status == UX_PORT_INDEX_UNKNOWN) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ROOT_HUB, UX_DEVICE_ENUMERATION_FAILURE); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DEVICE_ENUMERATION_FAILURE, port_index, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_DEVICE_ENUMERATION_FAILURE); + } + + /* Check if device is still connected. */ + if ((port_status & UX_PS_CCS) == 0) + { + + /* Device disconnected during enumeration retries. */ + return(UX_DEVICE_ENUMERATION_FAILURE); + } + + /* Set the device speed. */ + device_speed = port_status >> UX_PS_DS; + + /* Ask the USB stack to enumerate this device. A root hub is considered self + powered. */ + status = _ux_host_stack_new_device_create(hcd, UX_NULL, port_index, device_speed, UX_MAX_SELF_POWER, &device); + + /* Check return status. */ + if (status == UX_SUCCESS) + { + + /* Successful device create. */ + + /* The device has been mounted properly, we have to remember this + so when the device is removed, we have to invoke the enumeration + function again */ + hcd -> ux_hcd_rh_device_connection |= (ULONG)(1 << port_index); + + /* If the device instance is ready, notify application for connection. */ + if (_ux_system_host -> ux_system_host_change_function) + { + _ux_system_host -> ux_system_host_change_function(UX_DEVICE_CONNECTION, UX_NULL, (VOID*)device); + } + + /* Return success to the caller. */ + return(UX_SUCCESS); + } + else + { + + /* Return error if HCD is dead. */ + if (hcd -> ux_hcd_status != UX_HCD_STATUS_OPERATIONAL) + return(UX_CONTROLLER_DEAD); + + /* No retry if there are too many devices. */ + if (status == UX_TOO_MANY_DEVICES) + break; + + /* No retry if there is no class found. */ + if (status == UX_NO_CLASS_MATCH) + break; + + /* Simulate remove to free allocated resources if retry. */ + if (index_loop < UX_RH_ENUMERATION_RETRY - 1) + _ux_host_stack_device_remove(hcd, UX_NULL, port_index); + } + } + + /* We get here if something did not go well. Either the port did not respond + well to the ENABLE\RESET phases or the device did not enumerate well + so we try again ! */ + _ux_utility_delay_ms(UX_RH_ENUMERATION_RETRY_DELAY); + } +#endif /* defined(UX_HOST_STANDALONE) */ + + /* If we get here, the device did not enumerate completely. + The device is still attached to the root hub and therefore + there could be a physical connection with a unconfigured device. */ + hcd -> ux_hcd_rh_device_connection |= (ULONG)(1 << port_index); + + /* Notify application for a physical connection failed to be enumed. + Device instance NULL indicates too many devices. + Device state unconfigured indicates enumeration fail. */ + if (_ux_system_host -> ux_system_host_change_function) + { + _ux_system_host -> ux_system_host_change_function(UX_DEVICE_CONNECTION, UX_NULL, (VOID*)device); + } + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_ROOT_HUB, UX_DEVICE_ENUMERATION_FAILURE); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_DEVICE_ENUMERATION_FAILURE, port_index, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return a failed enumeration. */ + return(UX_DEVICE_ENUMERATION_FAILURE); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_role_swap.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_role_swap.c new file mode 100644 index 00000000..f5eb93a6 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_role_swap.c @@ -0,0 +1,128 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_role_swap PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is called when the host or the device demand a role */ +/* swap. This function may be called by an application or by the HNP */ +/* thread. */ +/* */ +/* INPUT */ +/* */ +/* hcd Pointer to HCD */ +/* device Device pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_get Get semaphore */ +/* _ux_host_stack_transfer_request Transfer request */ +/* */ +/* CALLED BY */ +/* */ +/* Application of HNP thread. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* refined macros names, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_role_swap(UX_DEVICE *device) +{ + +#if !defined(UX_OTG_SUPPORT) + + UX_PARAMETER_NOT_USED(device); + return(UX_FUNCTION_NOT_SUPPORTED); +#else + +UX_ENDPOINT *control_endpoint; +UX_TRANSFER *transfer_request; +UINT status; + + /* Retrieve the control endpoint and the transfer request associated with it. */ + control_endpoint = &device -> ux_device_control_endpoint; + transfer_request = &control_endpoint -> ux_endpoint_transfer_request; + + /* Protect the control endpoint semaphore here. It will be unprotected in the + transfer request function. */ + status = _ux_host_semaphore_get(&device -> ux_device_protection_semaphore, UX_WAIT_FOREVER); + + /* Perform a SET_FEATURE on this device to inform the it we are ready to change role. */ + transfer_request -> ux_transfer_request_requested_length = 0; + transfer_request -> ux_transfer_request_function = UX_SET_FEATURE; + transfer_request -> ux_transfer_request_type = UX_REQUEST_OUT | UX_REQUEST_TYPE_STANDARD | UX_REQUEST_TARGET_DEVICE; + transfer_request -> ux_transfer_request_value = UX_OTG_FEATURE_B_HNP_ENABLE; + transfer_request -> ux_transfer_request_index = 0; + + /* Send request to HCD layer. */ + status = _ux_host_stack_transfer_request(transfer_request); + + /* If the status fails, simply ignore the command but do not proceed. */ + if (status != UX_SUCCESS) + + /* We have an error. Do not proceed. */ + return(status); + + /* Keep track of the event for HNP synchronization. */ + _ux_system_otg -> ux_system_otg_change_mode_event = UX_OTG_HOST_TO_SLAVE; + + /* Call the OTG function that will perform the swap. */ + _ux_system_otg -> ux_system_otg_function(UX_OTG_HOST_TO_SLAVE); + + /* Reset the event. */ + _ux_system_otg -> ux_system_otg_change_mode_event = 0; + + return(UX_SUCCESS); +#endif +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_transfer_request.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_transfer_request.c new file mode 100644 index 00000000..8c5dbccb --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_transfer_request.c @@ -0,0 +1,219 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_transfer_request PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a USB transaction. On entry the transfer */ +/* request gives the endpoint pipe selected for this transaction and */ +/* the parameters associated with the transfer (data payload, length */ +/* of transaction) */ +/* */ +/* For Control pipe, the transaction is blocking and will only return */ +/* when the 3 phases of the control transfer have been completed or if */ +/* there is a previous error. For other pipes, the USB stack will */ +/* schedule the transaction on the USB but will not wait for its */ +/* completion. Each request for non blocking pipes has to specify a */ +/* completion routine. */ +/* */ +/* INPUT */ +/* */ +/* transfer_request Transfer request structure */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status If UX_SUCCESS, transfer was */ +/* successfully started */ +/* */ +/* CALLS */ +/* */ +/* HCD Entry Function */ +/* _ux_utility_semaphore_put Put semaphore */ +/* _ux_utility_semaphore_get Get semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, used UX prefix */ +/* to refer to TX symbols */ +/* instead of using them */ +/* directly, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_transfer_request(UX_TRANSFER *transfer_request) +{ +#if defined(UX_HOST_STANDALONE) +UINT status; + + UX_TRANSFER_STATE_RESET(transfer_request); + _ux_host_stack_transfer_run(transfer_request); + if ((transfer_request -> ux_transfer_request_flags & UX_TRANSFER_FLAG_AUTO_WAIT)) + { + while(1) + { + + /* Allow tasks running during waiting. */ + _ux_system_host_tasks_run(); + + if (transfer_request -> ux_transfer_request_state <= UX_STATE_NEXT) + break; + } + status = transfer_request -> ux_transfer_request_completion_code; + } + else + { + + /* In this mode, transfer pending is a success started case. */ + if (transfer_request -> ux_transfer_request_completion_code == UX_TRANSFER_STATUS_PENDING) + status = UX_SUCCESS; + else + status = transfer_request -> ux_transfer_request_completion_code; + } + + /* Return transfer completion status. */ + return(status); +#else +UX_INTERRUPT_SAVE_AREA + +UX_ENDPOINT *endpoint; +UX_DEVICE *device; +UX_HCD *hcd; +UINT status; + + + /* Get the endpoint container from the transfer_request */ + endpoint = transfer_request -> ux_transfer_request_endpoint; + + /* Get the device container from the endpoint. */ + device = endpoint -> ux_endpoint_device; + + /* Ensure we are not preempted by the enum thread while we check the device + state and set the transfer status. */ + UX_DISABLE + + /* We can only transfer when the device is ATTACHED, ADDRESSED OR CONFIGURED. */ + if ((device -> ux_device_state == UX_DEVICE_ATTACHED) || (device -> ux_device_state == UX_DEVICE_ADDRESSED) + || (device -> ux_device_state == UX_DEVICE_CONFIGURED)) + { + + /* Set the transfer to pending. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_STATUS_PENDING; +#if !defined(UX_HOST_STANDALONE) + /* Save the thread making this transfer. If we're under interrupt, this + will be null. */ + transfer_request -> ux_transfer_request_thread_pending = _ux_utility_thread_identify(); +#endif + } + else + { + + /* The device is in an invalid state. Restore interrupts and return error. */ + UX_RESTORE + + /* Check if this is endpoint 0. */ + if ((endpoint -> ux_endpoint_descriptor.bEndpointAddress & (UINT)~UX_ENDPOINT_DIRECTION) == 0) + { + + /* Check if the class has already protected it. */ + if (!_ux_host_semaphore_waiting(&device -> ux_device_protection_semaphore)) + { + + /* Class is using endpoint 0. Unprotect semaphore. */ + _ux_host_semaphore_put(&device -> ux_device_protection_semaphore); + } + } + + return(UX_TRANSFER_NOT_READY); + } + + /* Restore interrupts. */ + UX_RESTORE + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_TRANSFER_REQUEST, device, endpoint, transfer_request, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* With the device we have the pointer to the HCD. */ + hcd = UX_DEVICE_HCD_GET(device); + + /* If this is endpoint 0, we protect the endpoint from a possible re-entry. */ + if ((endpoint -> ux_endpoint_descriptor.bEndpointAddress & (UINT)~UX_ENDPOINT_DIRECTION) == 0) + { + + /* Check if the class has already protected it. */ + if (_ux_host_semaphore_waiting(&device -> ux_device_protection_semaphore)) + { + + /* We are using endpoint 0. Protect with semaphore. */ + status = _ux_host_semaphore_get(&device -> ux_device_protection_semaphore, UX_WAIT_FOREVER); + + /* Check for status. */ + if (status != UX_SUCCESS) + + /* Something went wrong. */ + return(status); + } + } + + /* Send the command to the controller. */ + status = hcd -> ux_hcd_entry_function(hcd, UX_HCD_TRANSFER_REQUEST, transfer_request); + + /* If this is endpoint 0, we unprotect the endpoint. */ + if ((endpoint -> ux_endpoint_descriptor.bEndpointAddress & (UINT)~UX_ENDPOINT_DIRECTION) == 0) + + /* We are using endpoint 0. Unprotect with semaphore. */ + _ux_host_semaphore_put(&device -> ux_device_protection_semaphore); + + /* And return the status. */ + return(status); +#endif +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_transfer_request_abort.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_transfer_request_abort.c new file mode 100644 index 00000000..5be063b1 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_transfer_request_abort.c @@ -0,0 +1,144 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_transfer_request_abort PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function aborts a pending transfer request that has been */ +/* previously submitted. This function only cancels the specific */ +/* transfer request. */ +/* */ +/* The call back to the function will have the */ +/* UX_TRANSFER_STATUS_ABORT status. */ +/* */ +/* INPUT */ +/* */ +/* transfer_request Transfer request structure */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status If UX_SUCCESS, transfer was */ +/* successfully aborted */ +/* */ +/* CALLS */ +/* */ +/* HCD Entry Function */ +/* Transfer Completion Function */ +/* _ux_utility_semaphore_put Put semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized based on compile */ +/* definitions, */ +/* resulting in version 6.1 */ +/* 06-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed trace enabled error, */ +/* resulting in version 6.1.7 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_transfer_request_abort(UX_TRANSFER *transfer_request) +{ + +UX_HCD *hcd; +ULONG completion_code; + + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_TRANSFER_REQUEST_ABORT, + transfer_request -> ux_transfer_request_endpoint -> ux_endpoint_device, + transfer_request -> ux_transfer_request_endpoint, + transfer_request, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + + /* With the device we have the pointer to the HCD. */ + hcd = UX_DEVICE_HCD_GET(transfer_request -> ux_transfer_request_endpoint -> ux_endpoint_device); + + /* Check pending transaction. */ + if (transfer_request -> ux_transfer_request_completion_code == UX_TRANSFER_STATUS_PENDING) + { + + /* Send the abort command to the controller. */ + hcd -> ux_hcd_entry_function(hcd, UX_HCD_TRANSFER_ABORT, transfer_request); + + /* Save the completion code since we're about to set it to ABORT. The + reason we can't just assume its value is PENDING is that in between + the completion code check and this line, it's possible that the transfer + completed, which would've changed the completion code to SUCCESS. + Such a case is valid, and we want to make sure we don't put() the + transfer request's semaphore again. */ + completion_code = transfer_request -> ux_transfer_request_completion_code; + + /* Set the transfer_request status to abort. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_STATUS_ABORT; + + /* We need to inform the class that owns this transfer_request of the + abort if there is a call back mechanism. */ + if (transfer_request -> ux_transfer_request_completion_function != UX_NULL) + transfer_request -> ux_transfer_request_completion_function(transfer_request); + + /* Is a thread waiting on the semaphore? */ + if (/* Is the transfer pending? */ + completion_code == UX_TRANSFER_STATUS_PENDING && +#if !defined(UX_HOST_STANDALONE) + /* Is the thread waiting not this one? (clearly we're not waiting!) */ + transfer_request -> ux_transfer_request_thread_pending != _ux_utility_thread_identify() && +#endif + /* Does the transfer request not have a completion function? */ + transfer_request -> ux_transfer_request_completion_function == UX_NULL) + + /* Wake up the semaphore for this request. */ + _ux_host_semaphore_put(&transfer_request -> ux_transfer_request_semaphore); + } + + /* This function never fails! */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_uninitialize.c b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_uninitialize.c new file mode 100644 index 00000000..15603b5c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_host_stack_uninitialize.c @@ -0,0 +1,129 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_host_stack_uninitialize PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function uninitializes all the host code for USBX to work on a */ +/* specific platform. */ +/* */ +/* Note following steps must be done before host stack uninitialize: */ +/* All HCDs must be unregistered (devices also removed). */ +/* All classes unregistered (clients attached also removed). */ +/* */ +/* INPUT */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* UX_SUCCESS Uninitialized success */ +/* */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_free Free host memory */ +/* _ux_utility_thread_delete Delete host thread */ +/* _ux_utility_semaphore_delete Delete host semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* 08-02-2021 Xiuwen Cai Modified comment(s), */ +/* fixed compile issue, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_host_stack_uninitialize(VOID) +{ + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_HOST_STACK_UNINITIALIZE, 0, 0, 0, 0, UX_TRACE_HOST_STACK_EVENTS, 0, 0) + +#if !defined(UX_HOST_STANDALONE) + /* Delete enumeration thread. */ + _ux_utility_thread_delete(&_ux_system_host -> ux_system_host_enum_thread); + + /* Delete enumeration semaphore. */ + _ux_utility_semaphore_delete(&_ux_system_host -> ux_system_host_enum_semaphore); + + /* Free enumeration thread stack. */ + _ux_utility_memory_free(_ux_system_host -> ux_system_host_enum_thread_stack); + + /* Delete HCD thread. */ + _ux_utility_thread_delete(&_ux_system_host -> ux_system_host_hcd_thread); + + /* Delete HCD semaphore. */ + _ux_utility_semaphore_delete(&_ux_system_host -> ux_system_host_hcd_semaphore); + + /* Free HCD thread stack. */ + _ux_utility_memory_free(_ux_system_host -> ux_system_host_hcd_thread_stack); +#endif + +#if defined(UX_OTG_SUPPORT) && !defined(UX_OTG_STANDALONE) + + /* Delete HNP thread. */ + _ux_utility_thread_delete(&_ux_system_host -> ux_system_host_hnp_polling_thread); + + /* Free HNP thread stack. */ + _ux_utility_memory_free(_ux_system_host -> ux_system_host_hnp_polling_thread_stack); +#endif + + /* Free HCD array. */ + _ux_utility_memory_free(_ux_system_host -> ux_system_host_hcd_array); + + /* Free Class array. */ + _ux_utility_memory_free(_ux_system_host -> ux_system_host_class_array); + + /* Free Device array. */ + _ux_utility_memory_free(_ux_system_host -> ux_system_host_device_array); + + /* Return success to caller. */ + return(UX_SUCCESS); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_system_error_handler.c b/src/Middlewares/ST/usbx/common/core/src/ux_system_error_handler.c new file mode 100644 index 00000000..861d17c1 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_system_error_handler.c @@ -0,0 +1,90 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +#ifndef UX_DISABLE_ERROR_HANDLER +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_system_error_handler PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function saves the last critical error from USBX functions. */ +/* It is mainly used for debugging purpose to trap where error occurred*/ +/* */ +/* */ +/* INPUT */ +/* */ +/* error_code */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_system_error_handler(UINT system_level, UINT system_context, UINT error_code) +{ + + /* Save the last system error code. */ + _ux_system -> ux_system_last_error = error_code; + + /* Increment the total number of system errors. */ + _ux_system -> ux_system_error_count++; + + /* Is there an application call back function to call ? */ + if (_ux_system -> ux_system_error_callback_function != UX_NULL) + { + + /* The callback function is defined, call it. */ + _ux_system -> ux_system_error_callback_function(system_level, system_context, error_code); + } +} +#endif diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_system_initialize.c b/src/Middlewares/ST/usbx/common/core/src/ux_system_initialize.c new file mode 100644 index 00000000..0cca5a0d --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_system_initialize.c @@ -0,0 +1,270 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Define UX_SYSTEM_INIT to bring in the USBX version ID string. */ + +#define UX_SYSTEM_INIT + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_system.h" + +/* Define the USBX system data structure. */ + +UX_SYSTEM *_ux_system; +UX_SYSTEM_OTG *_ux_system_otg; + +/* Define names of all the packed descriptors in USBX. */ + +UCHAR _ux_system_endpoint_descriptor_structure[] = {1,1,1,1,2,1 }; +UCHAR _ux_system_device_descriptor_structure[] = {1,1,2,1,1,1,1,2,2,2,1,1,1,1}; +UCHAR _ux_system_configuration_descriptor_structure[] = {1,1,2,1,1,1,1,1}; +UCHAR _ux_system_interface_descriptor_structure[] = {1,1,1,1,1,1,1,1,1}; +UCHAR _ux_system_interface_association_descriptor_structure[] = {1,1,1,1,1,1,1,1}; +UCHAR _ux_system_string_descriptor_structure[] = {1,1,2}; +UCHAR _ux_system_dfu_functional_descriptor_structure[] = {1,1,1,2,2,2}; +UCHAR _ux_system_class_audio_interface_descriptor_structure[] = {1,1,1,1,1,1,1,1}; +UCHAR _ux_system_class_audio_input_terminal_descriptor_structure[] = {1,1,1,1,2,1,1,2,1,1}; +UCHAR _ux_system_class_audio_output_terminal_descriptor_structure[] = {1,1,1,1,2,1,1,1}; +UCHAR _ux_system_class_audio_feature_unit_descriptor_structure[] = {1,1,1,1,1,1,1}; +UCHAR _ux_system_class_audio_streaming_interface_descriptor_structure[] = {1,1,1,1,1,1}; +UCHAR _ux_system_class_audio_streaming_endpoint_descriptor_structure[] = {1,1,1,1,1,1}; +UCHAR _ux_system_hub_descriptor_structure[] = {1,1,1,2,1,1,1,1}; +UCHAR _ux_system_hid_descriptor_structure[] = {1,1,2,1,1,1,2}; +UCHAR _ux_system_class_pima_storage_structure[] = {2,2,2,4,4,4,4,4}; +UCHAR _ux_system_class_pima_object_structure[] = {4,2,2,4,2,4,4,4,4,4,4,4,2,4,4}; +UCHAR _ux_system_ecm_interface_descriptor_structure[] = {1,1,1,1,4,2,2,1}; + +UCHAR _ux_system_bos_descriptor_structure[] = {1,1,2,1}; +UCHAR _ux_system_usb_2_0_extension_descriptor_structure[] = {1,1,1,4}; +UCHAR _ux_system_container_id_descriptor_structure[] = {1,1,1,1,4,4,4,4}; + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_system_initialize PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the various control data structures for */ +/* the USBX system. */ +/* */ +/* INPUT */ +/* */ +/* regular_memory_pool_start Start of non cached memory pool */ +/* regular_memory_size Size of non cached memory pool */ +/* cache_safe_memory_pool_start Start of cached memory pool */ +/* cache_safe_memory_size Size of cached memory pool */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_allocate Allocate memory */ +/* _ux_utility_memory_set Set memory */ +/* _ux_utility_mutex_create Create mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* added BOS support, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_system_initialize(VOID *regular_memory_pool_start, ULONG regular_memory_size, + VOID *cache_safe_memory_pool_start, ULONG cache_safe_memory_size) +{ + +UX_MEMORY_BLOCK *memory_block; +ALIGN_TYPE int_memory_pool_start; +VOID *regular_memory_pool_end; +ULONG memory_pool_offset; +#if !defined(UX_STANDALONE) +UINT status; +#endif + + + /* Reset memory block */ + _ux_utility_memory_set(regular_memory_pool_start, 0, regular_memory_size); /* Use case of memset is verified. */ + + /* Set the _ux_system structure at the start of our regular memory */ + _ux_system = (UX_SYSTEM *) regular_memory_pool_start; + + /* Add to the memory offset the size of the allocated block. */ + memory_pool_offset = sizeof(UX_SYSTEM); + +#ifndef UX_DEVICE_SIDE_ONLY + + /* Set the _ux_system_host structure. */ + _ux_system_host = (UX_SYSTEM_HOST *) (((UCHAR *) regular_memory_pool_start) + memory_pool_offset); + + /* Add to the memory offset the size of the allocated block. */ + memory_pool_offset += (ULONG)sizeof(UX_SYSTEM_HOST); + +#endif + +#ifndef UX_HOST_SIDE_ONLY + + /* Set the _ux_system_slave structure. */ + _ux_system_slave = (UX_SYSTEM_SLAVE *) (((UCHAR *) regular_memory_pool_start) + memory_pool_offset); + + /* Add to the memory offset the size of the allocated block. */ + memory_pool_offset += (ULONG)sizeof(UX_SYSTEM_SLAVE); + +#endif + + +#ifdef UX_OTG_SUPPORT + + /* Set the _ux_system_otg structure. */ + _ux_system_otg = (UX_SYSTEM_OTG *) (((UCHAR *) regular_memory_pool_start) + memory_pool_offset); + + /* Add to the memory offset the size of the allocated block. */ + memory_pool_offset += (ULONG)sizeof(UX_SYSTEM_OTG); +#endif + + + /* Set the cache safe memory for the dynamic pool */ + _ux_system -> ux_system_regular_memory_pool_start = (UX_MEMORY_BLOCK *) (((UCHAR *) regular_memory_pool_start) + + memory_pool_offset); + + /* Make sure the regular memory pool is aligned properly */ + int_memory_pool_start = (ALIGN_TYPE) _ux_system -> ux_system_regular_memory_pool_start; + int_memory_pool_start += UX_ALIGN_MIN; + int_memory_pool_start &= ~((ALIGN_TYPE)UX_ALIGN_MIN); + + /* Set the end of the regular memory pool. */ + regular_memory_pool_end = (void *) (((UCHAR *) regular_memory_pool_start) + regular_memory_size); + + /* Check if we have memory available. */ + if (int_memory_pool_start >= (ALIGN_TYPE)regular_memory_pool_end) + { + + /* No memory available. */ + return(UX_MEMORY_INSUFFICIENT); + } + + /* Now, we have a project structure allocated, save the regular memory allocation details */ + _ux_system -> ux_system_regular_memory_pool_size = (ULONG) (((ALIGN_TYPE) regular_memory_pool_end) - int_memory_pool_start); + _ux_system -> ux_system_regular_memory_pool_free = _ux_system -> ux_system_regular_memory_pool_size; + _ux_system -> ux_system_regular_memory_pool_start = (UX_MEMORY_BLOCK *) int_memory_pool_start; + + /* Build the first free memory block */ + memory_block = _ux_system -> ux_system_regular_memory_pool_start; + memory_block -> ux_memory_block_size = _ux_system -> ux_system_regular_memory_pool_size - (ULONG)sizeof(UX_MEMORY_BLOCK); + memory_block -> ux_memory_block_status = UX_MEMORY_UNUSED; + + /* Check the definition of the cache safe pool. If the application or controller do not require any cache safe memory, + define the cached safe memory region as the regular memory region. */ + if (cache_safe_memory_pool_start == UX_NULL) + { + + /* Cache safe memory is the same as regular memory. */ + _ux_system -> ux_system_cache_safe_memory_pool_size = _ux_system -> ux_system_regular_memory_pool_size; + _ux_system -> ux_system_cache_safe_memory_pool_free = _ux_system -> ux_system_regular_memory_pool_free; + _ux_system -> ux_system_cache_safe_memory_pool_start = _ux_system -> ux_system_regular_memory_pool_start; + } + else + { + + /* Make sure the cache safe memory pool is aligned properly */ + int_memory_pool_start = (ALIGN_TYPE) cache_safe_memory_pool_start; + int_memory_pool_start += UX_ALIGN_MIN; + int_memory_pool_start &= ~((ALIGN_TYPE)UX_ALIGN_MIN); + + /* Save the cache safe memory allocation details */ + _ux_system -> ux_system_cache_safe_memory_pool_size = cache_safe_memory_size - UX_ALIGN_MIN; + _ux_system -> ux_system_cache_safe_memory_pool_free = _ux_system -> ux_system_cache_safe_memory_pool_size; + _ux_system -> ux_system_cache_safe_memory_pool_start = (UX_MEMORY_BLOCK *) int_memory_pool_start; + + /* Reset this memory block */ + _ux_utility_memory_set(_ux_system -> ux_system_cache_safe_memory_pool_start, 0, _ux_system -> ux_system_cache_safe_memory_pool_size); /* Use case of memset is verified. */ + + /* Build the first free memory block */ + memory_block = _ux_system -> ux_system_cache_safe_memory_pool_start; + memory_block -> ux_memory_block_size = _ux_system -> ux_system_cache_safe_memory_pool_size - (ULONG)sizeof(UX_MEMORY_BLOCK); + memory_block -> ux_memory_block_status = UX_MEMORY_UNUSED; + } + +#ifdef UX_ENABLE_MEMORY_STATISTICS + _ux_system -> ux_system_regular_memory_pool_base = (UCHAR *) _ux_system -> ux_system_regular_memory_pool_start; + _ux_system -> ux_system_regular_memory_pool_min_free = _ux_system -> ux_system_regular_memory_pool_free; + _ux_system -> ux_system_cache_safe_memory_pool_base = (UCHAR *) _ux_system -> ux_system_cache_safe_memory_pool_start; + _ux_system -> ux_system_cache_safe_memory_pool_min_free = _ux_system -> ux_system_cache_safe_memory_pool_free; + + /* Other fields are kept zero. */ +#endif + +#ifdef UX_ENABLE_DEBUG_LOG + + /* Obtain memory for storing the debug log. */ + _ux_system -> ux_system_debug_log_buffer = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, UX_DEBUG_LOG_SIZE); + if (_ux_system -> ux_system_debug_log_buffer == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* Setup the head and tail pointers. */ + _ux_system -> ux_system_debug_log_head = _ux_system -> ux_system_debug_log_buffer; + _ux_system -> ux_system_debug_log_tail = _ux_system -> ux_system_debug_log_buffer; + + /* Keep the size in system structure variable. */ + _ux_system -> ux_system_debug_log_size = UX_DEBUG_LOG_SIZE; + +#endif + +#if !defined(UX_STANDALONE) + + /* Create the Mutex object used by USBX to control critical sections. */ + status = _ux_system_mutex_create(&_ux_system -> ux_system_mutex, "ux_system_mutex"); + if(status != UX_SUCCESS) + return(UX_MUTEX_ERROR); +#endif + + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_system_uninitialize.c b/src/Middlewares/ST/usbx/common/core/src/ux_system_uninitialize.c new file mode 100644 index 00000000..fcafd929 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_system_uninitialize.c @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** System */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_system.h" +#include "ux_utility.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_system_uninitialize PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function uninitializes the various control data structures for */ +/* the USBX system. */ +/* */ +/* INPUT */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_mutex_delete ThreadX delete mutex */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_system_uninitialize(VOID) +{ + + /* Delete the Mutex object used by USBX to control critical sections. */ + _ux_system_mutex_delete(&_ux_system -> ux_system_mutex); + + return(UX_SUCCESS); +} + + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_debug_callback_register.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_debug_callback_register.c new file mode 100644 index 00000000..0081057f --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_debug_callback_register.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +#ifdef UX_ENABLE_DEBUG_LOG + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_debug_callback_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a callback for sending formatted debug */ +/* messages to the application. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* debug_callback */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_debug_callback_register(VOID (*debug_callback)(UCHAR *, ULONG)) + +{ + + /* The callback function is defined. */ + _ux_system -> ux_system_debug_callback_function = debug_callback; + + /* We are done here. No return codes. */ + return; +} + +#endif diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_debug_log.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_debug_log.c new file mode 100644 index 00000000..3c21154d --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_debug_log.c @@ -0,0 +1,319 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +#ifdef UX_ENABLE_DEBUG_LOG + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_debug_log PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function logs a debug msg in a circular queue. The queue */ +/* must be initialized during the init of USBX. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* debug_location C string to locate the debug, */ +/* for example source file name. */ +/* debug_message C string of message */ +/* debug_code Debug code */ +/* debug_parameter_1 First parameter */ +/* debug_parameter_2 Second parameter */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check C string and return */ +/* its length if null-terminated */ +/* _tx_time_get Return system clock time */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* verified memset and memcpy */ +/* cases, used UX prefix to */ +/* refer to TX symbols instead */ +/* of using them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_debug_log(UCHAR *debug_location, UCHAR *debug_message, ULONG debug_code, + ULONG debug_parameter_1, ULONG debug_parameter_2) +{ + +UINT debug_location_string_length; +UINT debug_message_string_length; +ULONG total_debug_message_length; +ULONG parameter_length; +ULONG parameter_shift; +UCHAR parameter_hexa; +ULONG local_parameter_value; +ULONG current_time; +UX_INTERRUPT_SAVE_AREA + + /* Is USBX system completely initialized ? */ + if (_ux_system -> ux_system_debug_log_size == 0) + + /* Not yet. */ + return; + + /* Entering critical area. Disable interrupts. */ + UX_DISABLE + + /* Store the debug value as the last debug value recorded. */ + _ux_system -> ux_system_debug_code = debug_code; + + /* Increment the debug value code count. */ + _ux_system -> ux_system_debug_count++; + + /* Calculate the string length. */ + debug_location_string_length = UX_DEBUG_LOG_SIZE; + _ux_utility_string_length_check(source, &debug_location_string_length, UX_DEBUG_LOG_SIZE); + debug_message_string_length = UX_DEBUG_LOG_SIZE; + _ux_utility_string_length_check(source, &debug_message_string_length, UX_DEBUG_LOG_SIZE); + + /* Calculate the length of the entire message string. 1 fixed string, then 1 hexa + decimal, then 2 strings then 2 hexa decimal numbers in the format 0x00000000 + separated by commas and . at the end, zero terminated. */ + total_debug_message_length = debug_location_string_length + debug_message_string_length + 10 + 10 + 10 + 10 + 5; + + /* Can we accommodate this debug value message at the current location ? */ + if (total_debug_message_length >= _ux_system -> ux_system_debug_log_size) + return; + if (_ux_system -> ux_system_debug_log_head + total_debug_message_length > + ux_system -> ux_system_debug_log_buffer + _ux_system -> ux_system_debug_log_size) + { + + /* The debug value log to insert goes beyond the end of the log buffer, rewind to the beginning. */ + _ux_system -> ux_system_debug_log_head = _ux_system -> ux_system_debug_log_buffer; + } + + /* Copy the time strings and parameters in the log buffer. */ + _ux_utility_memory_copy(_ux_system -> ux_system_debug_log_head, "At time : ", 10); /* Use case of memcpy is verified. */ + _ux_system -> ux_system_debug_log_head += 10; + + /* Get the time value from TX. */ + current_time = _tx_time_get(); + + /* Reset the value of the length.*/ + parameter_length = 0; + + /* Init the shift value. */ + parameter_shift = 32 - 4; + + /* We parse the hexa value parameter and build the hexa value one byte at a type. */ + while(parameter_length < 8) + { + + /* Shift the 4 bit value we are interested in. We keep the lowest nibble. */ + local_parameter_value = (current_time >> parameter_shift) & 0x0f; + + /* See if this value is from 0-9 or A to F. */ + if (local_parameter_value <= 9) + + /* We have a digit. */ + parameter_hexa = (UCHAR) (local_parameter_value + '0'); + + else + + /* We have 'A' to 'F' value. */ + parameter_hexa = (UCHAR) (local_parameter_value - 10 + 'A'); + + /* Store the converted hexa value. */ + *_ux_system -> ux_system_debug_log_head = parameter_hexa; + + /* Next position. */ + _ux_system -> ux_system_debug_log_head++; + + /* Update length. */ + parameter_length++; + + /* Continue shifting by one nibble. */ + parameter_shift = parameter_shift - 4; + } + + /* Add the comma after the time. */ + *_ux_system -> ux_system_debug_log_head = ','; + _ux_system -> ux_system_debug_log_head++; + + /* Copy the strings and parameters in the log buffer. */ + _ux_utility_memory_copy(_ux_system -> ux_system_debug_log_head, debug_location, debug_location_string_length); /* Use case of memcpy is verified. */ + _ux_system -> ux_system_debug_log_head += debug_location_string_length; + *_ux_system -> ux_system_debug_log_head = ','; + _ux_system -> ux_system_debug_log_head++; + _ux_utility_memory_copy(_ux_system -> ux_system_debug_log_head, debug_message, debug_message_string_length); /* Use case of memcpy is verified. */ + _ux_system -> ux_system_debug_log_head += debug_message_string_length; + *_ux_system -> ux_system_debug_log_head = ','; + _ux_system -> ux_system_debug_log_head++; + + /* Create the hexa string for parameter 1. */ + *_ux_system -> ux_system_debug_log_head = '0'; + _ux_system -> ux_system_debug_log_head++; + *_ux_system -> ux_system_debug_log_head = 'x'; + _ux_system -> ux_system_debug_log_head++; + + /* Reset the value of the length.*/ + parameter_length = 0; + + /* Init the shift value. */ + parameter_shift = 32 - 4; + + /* We parse the hexa value parameter and build the hexa value one byte at a type. */ + while(parameter_length < 8) + { + + /* Shift the 4 bit value we are interested in. We keep the lowest nibble. */ + local_parameter_value = (debug_parameter_1 >> parameter_shift) & 0x0f; + + /* See if this value is from 0-9 or A to F. */ + if (local_parameter_value <= 9) + + /* We have a digit. */ + parameter_hexa = (UCHAR) (local_parameter_value + '0'); + + else + + /* We have 'A' to 'F' value. */ + parameter_hexa = (UCHAR) (local_parameter_value - 10 + 'A'); + + /* Store the converted hexa value. */ + *_ux_system -> ux_system_debug_log_head = parameter_hexa; + + /* Next position. */ + _ux_system -> ux_system_debug_log_head++; + + /* Update length. */ + parameter_length++; + + /* Continue shifting by one nibble. */ + parameter_shift = parameter_shift - 4; + } + + /* Add the comma between the 2 hexa values. */ + *_ux_system -> ux_system_debug_log_head = ','; + _ux_system -> ux_system_debug_log_head++; + + /* Create the hexa string for parameter 2. */ + *_ux_system -> ux_system_debug_log_head = '0'; + _ux_system -> ux_system_debug_log_head++; + *_ux_system -> ux_system_debug_log_head = 'x'; + _ux_system -> ux_system_debug_log_head++; + + /* Reset the value of the length.*/ + parameter_length = 0; + + /* Init the shift value. */ + parameter_shift = 32 - 4; + + /* We parse the hexa value parameter and build the hexa value one byte at a type. */ + while(parameter_length < 8) + { + + /* Shift the 4 bit value we are interested in. We keep the lowest nibble. */ + local_parameter_value = (debug_parameter_2 >> parameter_shift) & 0x0f; + + /* See if this value is from 0-9 or A to F. */ + if (local_parameter_value <= 9) + + /* We have a digit. */ + parameter_hexa = (UCHAR) (local_parameter_value + '0'); + + else + + /* We have 'A' to 'F' value. */ + parameter_hexa = (UCHAR) (local_parameter_value - 10 + 'A'); + + /* Store the converted hexa value. */ + *_ux_system -> ux_system_debug_log_head = parameter_hexa; + + /* Next position. */ + _ux_system -> ux_system_debug_log_head++; + + /* Update length. */ + parameter_length++; + + /* Continue shifting by one nibble. */ + parameter_shift = parameter_shift - 4; + } + + /* Add the termination dot at the end. */ + *_ux_system -> ux_system_debug_log_head = '.'; + _ux_system -> ux_system_debug_log_head++; + + /* Add the CR/LF end of the string. */ + *_ux_system -> ux_system_debug_log_head = 0x0d; + _ux_system -> ux_system_debug_log_head++; + *_ux_system -> ux_system_debug_log_head = 0x0a; + _ux_system -> ux_system_debug_log_head++; + + /* Add the zero end of the string. */ + *_ux_system -> ux_system_debug_log_head = 0x00; + _ux_system -> ux_system_debug_log_head++; + + /* The log string is put into the log buffer. It can stay here until + a break into debugger by the developer or be passed to a callback registered + by the application. */ + if (_ux_system -> ux_system_debug_callback_function != UX_NULL) + { + + /* The callback function is defined, call it. */ + _ux_system -> ux_system_debug_callback_function(_ux_system -> ux_system_debug_log_tail, debug_code); + + /* Update the tail. */ + _ux_system -> ux_system_debug_log_tail += total_debug_message_length; + + } + + /* Restore interrupts. */ + UX_RESTORE + + /* We are done here. No return codes. */ + return; +} + +#endif diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_delay_ms.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_delay_ms.c new file mode 100644 index 00000000..7d2d77aa --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_delay_ms.c @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Host Stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_delay_ms PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function causes the calling thread to sleep for the */ +/* specified number of milliseconds */ +/* */ +/* INPUT */ +/* */ +/* ms_wait Number of milliseconds to */ +/* wait for */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_sleep ThreadX sleep function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 11-09-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed compile warnings 64b, */ +/* resulting in version 6.1.2 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_delay_ms(ULONG ms_wait) +{ + +ULONG ticks; + +#if defined(UX_STANDALONE) + + /* Get current time. */ + ticks = _ux_utility_time_get(); + + /* Wait until timeout. */ + while(_ux_utility_time_elapsed(ticks, _ux_utility_time_get()) < + UX_MS_TO_TICK_NON_ZERO(ms_wait)); +#else + + /* translate ms into ticks. */ + ticks = (ULONG)(ms_wait * UX_PERIODIC_RATE) / 1000; + + /* For safety add 1 to ticks. */ + ticks++; + + /* Call ThreadX sleep function. */ + tx_thread_sleep(ticks); +#endif + + /* Return completion status. */ + return; +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_descriptor_pack.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_descriptor_pack.c new file mode 100644 index 00000000..28cdb529 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_descriptor_pack.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_descriptor_pack PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will pack an application structure into a USB */ +/* descriptor. */ +/* */ +/* INPUT */ +/* */ +/* descriptor Pointer to the unpacked */ +/* descriptor */ +/* descriptor_structure Components of the descriptor */ +/* descriptor_entries Number of entries in the */ +/* descriptor */ +/* raw_descriptor Pointer to packed descriptor */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_long_put Put 32-bit value */ +/* _ux_utility_short_put Put 16-bit value */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_descriptor_pack(UCHAR * descriptor, UCHAR * descriptor_structure, + UINT descriptor_entries, UCHAR * raw_descriptor) +{ + + /* Loop on all the entries in this descriptor. */ + while(descriptor_entries--) + { + + /* Get the length of that component. */ + switch(*descriptor_structure++) + { + + /* Check the size then build the component from the source and + insert it into the target descriptor. */ + case 4: + + _ux_utility_long_put(raw_descriptor, *((ULONG *) descriptor)); + raw_descriptor += 4; + break; + + case 2: + + _ux_utility_short_put(raw_descriptor, (USHORT)*((ULONG *) descriptor)); + raw_descriptor += 2; + break; + + default: + + *raw_descriptor = (UCHAR) *((ULONG *) descriptor); + raw_descriptor++; + } + + /* Add the size of the component to the destination. */ + descriptor += 4; + } + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_descriptor_parse.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_descriptor_parse.c new file mode 100644 index 00000000..3921e486 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_descriptor_parse.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_descriptor_parse PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will unpack a USB descriptor from the bus into a */ +/* memory aligned structure. */ +/* */ +/* INPUT */ +/* */ +/* raw_descriptor Pointer to packed descriptor */ +/* descriptor_structure Components of the descriptor */ +/* descriptor_entries Number of entries in the */ +/* descriptor */ +/* descriptor Pointer to the unpacked */ +/* descriptor */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_long_get Get 32-bit value */ +/* _ux_utility_short_get Get 16-bit value */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_descriptor_parse(UCHAR * raw_descriptor, UCHAR * descriptor_structure, + UINT descriptor_entries, UCHAR * descriptor) +{ + + /* Loop on all the entries in this descriptor. */ + while(descriptor_entries--) + { + + /* Get the length of that component. */ + switch(*descriptor_structure++) + { + + /* Check the size then build the component from the source and + insert it into the target descriptor. */ + case 4: + + *((ULONG *) descriptor) = _ux_utility_long_get(raw_descriptor); + raw_descriptor += 4; + break; + + case 2: + + *((ULONG *) descriptor) = (ULONG) _ux_utility_short_get(raw_descriptor); + raw_descriptor += 2; + break; + + default: + + *((ULONG *) descriptor) = (ULONG) *raw_descriptor; + raw_descriptor++; + } + + /* Add the size of the component to the destination. */ + descriptor += 4; + } + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_error_callback_register.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_error_callback_register.c new file mode 100644 index 00000000..b147b7fb --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_error_callback_register.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +#ifndef UX_DISABLE_ERROR_HANDLER +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_error_callback_register PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function registers a callback for sending formatted errors to */ +/* the application. */ +/* */ +/* */ +/* INPUT */ +/* */ +/* error_callback */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* Application */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_error_callback_register(VOID (*error_callback)(UINT system_level, UINT system_context, UINT error_code)) + +{ + + /* The callback function is defined. */ + _ux_system -> ux_system_error_callback_function = error_callback; + + /* We are done here. No return codes. */ + return; +} +#endif + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_create.c new file mode 100644 index 00000000..f4daa52e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_create.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_event_flags_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a threadx group of flags */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Event flag control group */ +/* name Pointer to thread name string */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_event_flags_create ThreadX create event flag */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_event_flags_create(UX_EVENT_FLAGS_GROUP*group_ptr, CHAR *name) +{ + +UINT status; + + /* Call ThreadX to create the event flags. */ + status = tx_event_flags_create(group_ptr, name); + + /* Check for status. */ + if (status != UX_SUCCESS) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, UX_EVENT_ERROR); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_EVENT_ERROR, group_ptr, 0, 0, UX_TRACE_ERRORS, 0, 0) + + } + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_delete.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_delete.c new file mode 100644 index 00000000..9da76248 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_delete.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_event_flags_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a threadx group of flags */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Event flag control group */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_event_flags_delete ThreadX delete event flag */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_event_flags_delete(UX_EVENT_FLAGS_GROUP*group_ptr) +{ + +UINT status; + + /* Call ThreadX to delete the event flags. */ + status = tx_event_flags_delete(group_ptr); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_get.c new file mode 100644 index 00000000..099ea8c5 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_get.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_event_flags_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function get event flags from event flag group */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Event flag control group */ +/* requested_flags 32 bits variable event flags */ +/* get_option AND/OR/CLEAR ... options */ +/* actual_flag_ptr where the flags are placed */ +/* wait_option waiting option */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_event_flags_get ThreadX get event flag */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_event_flags_get(UX_EVENT_FLAGS_GROUP*group_ptr, ULONG requested_flags, + UINT get_option, ULONG *actual_flags_ptr, ULONG wait_option) +{ + +UINT status; +ULONG local_actual_flags_ptr; + + /* Call ThreadX to get the event flags. */ + status = tx_event_flags_get(group_ptr, requested_flags, get_option, &local_actual_flags_ptr, wait_option); + + /* Update the actual flags. */ + *actual_flags_ptr = local_actual_flags_ptr; + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_set.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_set.c new file mode 100644 index 00000000..c211b4e9 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_event_flags_set.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_event_flags_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function set event flags from event flag group */ +/* */ +/* INPUT */ +/* */ +/* group_ptr Event flag control group */ +/* flags_to_set 32 bits variable event flags */ +/* set_option set option */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_event_flags_set ThreadX set event flag */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_event_flags_set(UX_EVENT_FLAGS_GROUP*group_ptr, ULONG flags_to_set, + UINT set_option) +{ + +UINT status; + + /* Call ThreadX to set the event flags. */ + status = tx_event_flags_set(group_ptr, flags_to_set, set_option); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_get.c new file mode 100644 index 00000000..9900c8af --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_get.c @@ -0,0 +1,86 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_long_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads a 32-bit value. */ +/* */ +/* INPUT */ +/* */ +/* address Source address */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit value */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _ux_utility_long_get(UCHAR * address) +{ + +ULONG value; + + + /* In order to make this function endian agnostic and memory alignment + independent, we read a byte at a time from the address. */ + value = (ULONG) *address++; + value |= (ULONG)*address++ << 8; + value |= (ULONG)*address++ << 16; + value |= (ULONG)*address << 24; + + /* Return 32-bit value. */ + return(value); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_get_big_endian.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_get_big_endian.c new file mode 100644 index 00000000..067200b6 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_get_big_endian.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_long_get_big_endian PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads a 32-bit value in big endian format. */ +/* */ +/* INPUT */ +/* */ +/* address Source address */ +/* */ +/* OUTPUT */ +/* */ +/* 16-bit value */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _ux_utility_long_get_big_endian(UCHAR * address) +{ + +ULONG value; + + + /* We read a byte at a time from the address. */ + value = (ULONG) ((*address++) << 24); + value |= (ULONG) ((*address++) << 16); + value |= (ULONG) ((*address++) << 8); + value |= (ULONG) *address; + + /* Return 32-bit value. */ + return(value); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_put.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_put.c new file mode 100644 index 00000000..066c82f9 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_put.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_long_put PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes a 32-bit value. */ +/* */ +/* INPUT */ +/* */ +/* address Destination address */ +/* value 32-bit value */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_long_put(UCHAR * address, ULONG value) +{ + + /* In order to make this function endian agnostic and memory alignment + independent, we write a byte at a time from the address. */ + *address++ = (UCHAR) (value & 0xff); + *address++ = (UCHAR) ((value >> 8) & 0xff); + *address++ = (UCHAR) ((value >> 16) & 0xff); + *address = (UCHAR) ((value >> 24) & 0xff); + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_put_big_endian.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_put_big_endian.c new file mode 100644 index 00000000..041980af --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_long_put_big_endian.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_long_put_big_endian PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes a 32-bit value in big endian format. */ +/* */ +/* INPUT */ +/* */ +/* address Destination address */ +/* value 32-bit value */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_long_put_big_endian(UCHAR * address, ULONG value) +{ + +ULONG low_word_value; +ULONG high_word_value; + + /* First we swap the value words. */ + low_word_value = value >> 16; + high_word_value = value << 16; + value = high_word_value | low_word_value; + + /* In order to make this function endian agnostic and memory alignment + independent, we write a byte at a time from the address. */ + *address++ = (UCHAR) ((value >> 8) & 0xff); + *address++ = (UCHAR) (value & 0xff); + *address++ = (UCHAR) ((value >> 24 ) & 0xff); + *address = (UCHAR) ((value >> 16) & 0xff); + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate.c new file mode 100644 index 00000000..7ff518fa --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate.c @@ -0,0 +1,402 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_allocate PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a block of memory for the specified size */ +/* and alignment. */ +/* */ +/* INPUT */ +/* */ +/* memory_alignment Memory alignment required */ +/* memory_cache_flag Memory pool source */ +/* memory_size_requested Number of bytes required */ +/* */ +/* OUTPUT */ +/* */ +/* Pointer to block of memory */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_free_block_best_get Get best fit block of memory */ +/* _ux_utility_memory_set Set block of memory */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID *_ux_utility_memory_allocate(ULONG memory_alignment, ULONG memory_cache_flag, + ULONG memory_size_requested) +{ + +UX_MEMORY_BLOCK *memory_block; +UX_MEMORY_BLOCK *new_memory_block; +UX_MEMORY_BLOCK *leftover_memory_block; +ULONG memory_for_alignment; +ULONG memory_removed_from_pool; +ULONG leftover; +UCHAR *memory_buffer; +ALIGN_TYPE int_memory_buffer; + + + /* Get the mutex as this is a critical section. */ + _ux_system_mutex_on(&_ux_system -> ux_system_mutex); + +#ifdef UX_ENFORCE_SAFE_ALIGNMENT + + /* Check if safe alignment requested, in this case switch to UX_NO_ALIGN. */ + if (memory_alignment == UX_SAFE_ALIGN) + { + + /* We will use the memory_size_requested for the alignment. + But we check to see if we have a minimum or maximum alignment. */ + if (memory_size_requested < UX_ALIGN_MIN) + + /* No need to bother about alignment for small packets sizes. */ + memory_alignment = UX_NO_ALIGN; + + else + { + + /* Check if we are over the maximum. */ + if (memory_size_requested > UX_MAX_SCATTER_GATHER_ALIGNMENT) + + /* We are over the max alignment required. Use the maximum instead. */ + memory_alignment = UX_MAX_SCATTER_GATHER_ALIGNMENT - 1; + + else + { + /* We are not over the maximum, so approximate the alignment according to the size of the memory. + Check range for alignment on 4096 bytes. */ + if (memory_size_requested >= UX_ALIGN_2048 + 1) + memory_alignment = UX_ALIGN_4096; + + else + { + + /* Check range for alignment on 2048 bytes. */ + if (memory_size_requested >= UX_ALIGN_1024 + 1) + memory_alignment = UX_ALIGN_2048; + + else + { + + /* Check range for alignment on 1024 bytes. */ + if (memory_size_requested >= UX_ALIGN_512 + 1) + memory_alignment = UX_ALIGN_1024; + + else + { + + /* Check range for alignment on 512 bytes. */ + if (memory_size_requested >= UX_ALIGN_256 + 1) + memory_alignment = UX_ALIGN_512; + + else + { + + /* Check range for alignment on 256 bytes. */ + if (memory_size_requested >= UX_ALIGN_128 + 1) + memory_alignment = UX_ALIGN_256; + + else + { + + /* Check range for alignment on 128 bytes. */ + if (memory_size_requested >= UX_ALIGN_64 + 1) + memory_alignment = UX_ALIGN_128; + + else + { + + /* Check range for alignment on 128 bytes. */ + if (memory_size_requested >= UX_ALIGN_64 + 1) + memory_alignment = UX_ALIGN_128; + + else + { + + /* Check range for alignment on 64 bytes. */ + if (memory_size_requested >= UX_ALIGN_32 + 1) + memory_alignment = UX_ALIGN_64; + + else + { + + /* Check range for alignment on 32 bytes. */ + if (memory_size_requested >= UX_ALIGN_16 + 1) + memory_alignment = UX_ALIGN_32; + + else + memory_alignment = UX_ALIGN_MIN; + + + } + } + } + } + } + } + } + } + } + } + } + +#else + + /* Check if safe alignment requested, in this case switch to UX_NO_ALIGN. */ + if (memory_alignment == UX_SAFE_ALIGN) + memory_alignment = UX_NO_ALIGN; + +#endif + + /* Ensure the alignment meats the minimum. */ + if (memory_alignment < UX_ALIGN_MIN) + memory_alignment = UX_ALIGN_MIN; + + /* Adjust the memory alignment since our macros are one minus the desired alignment. + Also determine the amount of extra memory we need for the alignment, which is one + minus the actual alignment. */ + memory_for_alignment = memory_alignment; + memory_alignment++; + + /* We need to make sure that the next memory block buffer is 16-byte aligned too. We + do this by first adjusting the requested memory to be 16-byte aligned. One problem + now is that the memory block might not be a size that is a multiple of 16, so we need + to add the amount of memory required such that the memory buffer after the block has + the correct alignment. For example, if the memory block has a size of 24, then we need + to make sure it is placed on an 8-byte alignment that is after a 16-byte alignment so + that the memory right after the memory block is 16-byte aligned (8 + 24 = 32). */ + memory_size_requested = (memory_size_requested + UX_ALIGN_MIN) & (~(ULONG)UX_ALIGN_MIN); + memory_size_requested += (((ULONG)sizeof(UX_MEMORY_BLOCK) + UX_ALIGN_MIN) & (~(ULONG)UX_ALIGN_MIN)) - (ULONG)sizeof(UX_MEMORY_BLOCK); + + /* Try to find the best block for this memory by requesting the maximum amount of + memory we'll need which is calculated as follows: the amount memory requested by + the caller plus the maximum amount of memory wasted due to alignment plus 2 memory + blocks structs - one for the new memory block we'll create for the user block and one + that we might create if there is extra memory after doing the alignment. */ + memory_block = _ux_utility_memory_free_block_best_get(memory_cache_flag, memory_size_requested + memory_for_alignment + (ULONG)sizeof(UX_MEMORY_BLOCK)); + + /* If the block returned is NULL, there is no free memory in the pool + for that size. */ + if (memory_block == UX_NULL) + { + + /* Release the protection. */ + _ux_system_mutex_off(&_ux_system -> ux_system_mutex); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MEMORY_INSUFFICIENT, memory_size_requested, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, UX_MEMORY_INSUFFICIENT); + + /* Return NULL to indicate no block was found. */ + return(UX_NULL); + } + + /* Get the memory buffer for this block. */ + int_memory_buffer = (ALIGN_TYPE) ((UCHAR *) memory_block + sizeof(UX_MEMORY_BLOCK)); + + /* Are we already aligned? */ + if ((int_memory_buffer & (memory_alignment - 1)) == 0) + { + + /* Setup the new memory block. */ + new_memory_block = (UX_MEMORY_BLOCK *) ((UCHAR *) memory_block + sizeof(UX_MEMORY_BLOCK) + memory_size_requested); + new_memory_block -> ux_memory_block_next = memory_block -> ux_memory_block_next; + new_memory_block -> ux_memory_block_previous = memory_block; + new_memory_block -> ux_memory_block_size = memory_block -> ux_memory_block_size - memory_size_requested - (ULONG)sizeof(UX_MEMORY_BLOCK); + new_memory_block -> ux_memory_block_status = UX_MEMORY_UNUSED; + + /* Update the current memory block. */ + memory_block -> ux_memory_block_size = memory_size_requested; + memory_block -> ux_memory_block_next = new_memory_block; + memory_block -> ux_memory_block_status = UX_MEMORY_USED | memory_cache_flag; + + /* Declare how much memory we removed from the pool. */ + memory_removed_from_pool = memory_block -> ux_memory_block_size + (ULONG)sizeof(UX_MEMORY_BLOCK); + } + else + { + + /* Align the buffer. The first thing we do is increment by the size of a + memory block because we have to make sure we have enough memory for at + least that. */ + int_memory_buffer += (ULONG)sizeof(UX_MEMORY_BLOCK); + int_memory_buffer += memory_alignment - 1; + int_memory_buffer &= ~(((ALIGN_TYPE) memory_alignment) - 1); + + /* Setup the new memory block. Note that its size is updated again later. */ + new_memory_block = (UX_MEMORY_BLOCK *) (int_memory_buffer - (ULONG)sizeof(UX_MEMORY_BLOCK)); + new_memory_block -> ux_memory_block_previous = memory_block; + new_memory_block -> ux_memory_block_next = memory_block -> ux_memory_block_next; + new_memory_block -> ux_memory_block_size = memory_block -> ux_memory_block_size; + new_memory_block -> ux_memory_block_status = UX_MEMORY_USED | memory_cache_flag; + + /* Update the current memory block. */ + int_memory_buffer = (ALIGN_TYPE) ((UCHAR *) memory_block + sizeof(UX_MEMORY_BLOCK)); + memory_block -> ux_memory_block_next = new_memory_block; + memory_block -> ux_memory_block_size = (ULONG) ((ALIGN_TYPE) new_memory_block - int_memory_buffer); + + /* Update the new memory block's size. */ + new_memory_block -> ux_memory_block_size -= (memory_block -> ux_memory_block_size + (ULONG)sizeof(UX_MEMORY_BLOCK)); + + /* Calculate how much memory is leftover in the new memory block after doing + the alignment. */ + leftover = new_memory_block -> ux_memory_block_size - memory_size_requested; + + /* Can we fit another block after the new block? */ + if (leftover > sizeof(UX_MEMORY_BLOCK)) + { + + /* Setup the leftover memory block. */ + leftover_memory_block = (UX_MEMORY_BLOCK *) ((ALIGN_TYPE) new_memory_block + sizeof(UX_MEMORY_BLOCK) + memory_size_requested); + leftover_memory_block -> ux_memory_block_next = new_memory_block -> ux_memory_block_next; + leftover_memory_block -> ux_memory_block_previous = new_memory_block; + leftover_memory_block -> ux_memory_block_size = leftover - (ULONG)sizeof(UX_MEMORY_BLOCK); + leftover_memory_block -> ux_memory_block_status = UX_MEMORY_UNUSED; + + new_memory_block -> ux_memory_block_next = leftover_memory_block; + new_memory_block -> ux_memory_block_size -= leftover; + } + + /* Declare how much memory we removed from the pool. */ + memory_removed_from_pool = new_memory_block -> ux_memory_block_size + (ULONG)sizeof(UX_MEMORY_BLOCK); + + /* The new memory block is the one we give to the user. */ + memory_block = new_memory_block; + } + + /* The memory to be returned is after the block header. */ + memory_buffer = ((UCHAR *) memory_block) + sizeof(UX_MEMORY_BLOCK); + + /* Clear the memory block. */ + _ux_utility_memory_set(memory_buffer, 0, memory_size_requested); /* Use case of memset is verified. */ + + /* Update the memory free in the pool. */ + if (_ux_system -> ux_system_cache_safe_memory_pool_start == _ux_system -> ux_system_regular_memory_pool_start) + { + + /* There is only one memory pool. */ + _ux_system -> ux_system_regular_memory_pool_free -= memory_removed_from_pool; + } + else + { + + switch (memory_cache_flag) + { + + case UX_CACHE_SAFE_MEMORY: + /* Update the amount of free memory in the cache safe memory pool. */ + _ux_system -> ux_system_cache_safe_memory_pool_free -= memory_removed_from_pool; + + break; + + default: + /* Update the amount of free memory in the regular memory pool. */ + _ux_system -> ux_system_regular_memory_pool_free -= memory_removed_from_pool; + break; + + } + } + +#ifdef UX_ENABLE_MEMORY_STATISTICS + + /* Update allocate count, total size. */ + if (memory_cache_flag == UX_REGULAR_MEMORY) + { + _ux_system -> ux_system_regular_memory_pool_alloc_count ++; + _ux_system -> ux_system_regular_memory_pool_alloc_total += memory_size_requested; + if (_ux_system -> ux_system_regular_memory_pool_alloc_max_count < _ux_system -> ux_system_regular_memory_pool_alloc_count) + _ux_system -> ux_system_regular_memory_pool_alloc_max_count = _ux_system -> ux_system_regular_memory_pool_alloc_count; + if (_ux_system -> ux_system_regular_memory_pool_alloc_max_total < _ux_system -> ux_system_regular_memory_pool_alloc_total) + _ux_system -> ux_system_regular_memory_pool_alloc_max_total = _ux_system -> ux_system_regular_memory_pool_alloc_total; + } + else + { + _ux_system -> ux_system_cache_safe_memory_pool_alloc_count ++; + _ux_system -> ux_system_cache_safe_memory_pool_alloc_total += memory_size_requested; + if (_ux_system -> ux_system_cache_safe_memory_pool_alloc_max_count < _ux_system -> ux_system_cache_safe_memory_pool_alloc_count) + _ux_system -> ux_system_cache_safe_memory_pool_alloc_max_count = _ux_system -> ux_system_cache_safe_memory_pool_alloc_count; + if (_ux_system -> ux_system_cache_safe_memory_pool_alloc_max_total < _ux_system -> ux_system_cache_safe_memory_pool_alloc_total) + _ux_system -> ux_system_cache_safe_memory_pool_alloc_max_total = _ux_system -> ux_system_cache_safe_memory_pool_alloc_total; + } + + /* Log max usage of regular memory pool. */ + memory_removed_from_pool = (ALIGN_TYPE)_ux_system -> ux_system_regular_memory_pool_start - + (ALIGN_TYPE)_ux_system -> ux_system_regular_memory_pool_base; + if (memory_removed_from_pool > _ux_system -> ux_system_regular_memory_pool_max_start_offset) + _ux_system -> ux_system_regular_memory_pool_max_start_offset = memory_removed_from_pool; + if (_ux_system -> ux_system_regular_memory_pool_min_free > _ux_system -> ux_system_regular_memory_pool_free) + _ux_system -> ux_system_regular_memory_pool_min_free = _ux_system -> ux_system_regular_memory_pool_free; + + /* Log max usage of cache safe memory pool. */ + memory_removed_from_pool = (ALIGN_TYPE)_ux_system -> ux_system_cache_safe_memory_pool_start - + (ALIGN_TYPE)_ux_system -> ux_system_cache_safe_memory_pool_base; + if (memory_removed_from_pool > _ux_system -> ux_system_cache_safe_memory_pool_max_start_offset) + _ux_system -> ux_system_cache_safe_memory_pool_max_start_offset = memory_removed_from_pool; + if (_ux_system -> ux_system_cache_safe_memory_pool_min_free > _ux_system -> ux_system_cache_safe_memory_pool_free) + _ux_system -> ux_system_cache_safe_memory_pool_min_free = _ux_system -> ux_system_cache_safe_memory_pool_free; + +#endif + + /* Release the protection. */ + _ux_system_mutex_off(&_ux_system -> ux_system_mutex); + + /* The memory block pointer contains a memory area properly + aligned. */ + return(memory_buffer); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_add_safe.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_add_safe.c new file mode 100644 index 00000000..d7b29535 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_add_safe.c @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_allocate_add_safe PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a block of memory for the specified added */ +/* size and alignment. */ +/* */ +/* Note if adding result overflow, no memory is allocated. */ +/* */ +/* INPUT */ +/* */ +/* align Memory alignment required */ +/* cache Memory pool source */ +/* size_add_a Number of bytes a to add */ +/* size_add_b Number of bytes b to add */ +/* */ +/* OUTPUT */ +/* */ +/* Pointer to block of memory */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_allocate Allocate block of memory */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID* _ux_utility_memory_allocate_add_safe(ULONG align,ULONG cache,ULONG size_add_a,ULONG size_add_b) +{ + return UX_UTILITY_MEMORY_ALLOCATE_ADD_SAFE(align, cache, size_add_a, size_add_b); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_mulc_safe.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_mulc_safe.c new file mode 100644 index 00000000..505cb71c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_mulc_safe.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_allocate_mulc_safe PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a block of memory for the specified */ +/* multiplied size and alignment. */ +/* */ +/* Note if multiplying result overflow, no memory is allocated. */ +/* Note it's assumed at least the last factor to multiply is const for */ +/* possible code optimization. */ +/* */ +/* INPUT */ +/* */ +/* align Memory alignment required */ +/* cache Memory pool source */ +/* size_mul_v Number of bytes variable to */ +/* multiply */ +/* size_mul_c Number of bytes const to */ +/* multiply */ +/* */ +/* OUTPUT */ +/* */ +/* Pointer to block of memory */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_allocate Allocate block of memory */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID* _ux_utility_memory_allocate_mulc_safe(ULONG align,ULONG cache,ULONG size_mul_v,ULONG size_mul_c) +{ + return UX_UTILITY_MEMORY_ALLOCATE_MULC_SAFE(align, cache, size_mul_v, size_mul_c); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_mulv_safe.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_mulv_safe.c new file mode 100644 index 00000000..021c4303 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_allocate_mulv_safe.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_allocate_mulv_safe PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allocates a block of memory for the specified */ +/* multiplied size and alignment. */ +/* */ +/* Note if multiplying result overflow, no memory is allocated. */ +/* Note it's assumed all factors to multiply is variables for */ +/* possible code optimization. */ +/* */ +/* INPUT */ +/* */ +/* align Memory alignment required */ +/* cache Memory pool source */ +/* size_mul_v0 Number of bytes variable to */ +/* multiply */ +/* size_mul_v1 Number of bytes variable to */ +/* multiply */ +/* */ +/* OUTPUT */ +/* */ +/* Pointer to block of memory */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_allocate Allocate block of memory */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID* _ux_utility_memory_allocate_mulv_safe(ULONG align,ULONG cache,ULONG size_mul_v0,ULONG size_mul_v1) +{ + return UX_UTILITY_MEMORY_ALLOCATE_MULV_SAFE(align, cache, size_mul_v0, size_mul_v1); +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_compare.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_compare.c new file mode 100644 index 00000000..79f38b27 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_compare.c @@ -0,0 +1,100 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_compare PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function compares two memory blocks. */ +/* */ +/* INPUT */ +/* */ +/* memory_source Pointer to source */ +/* memory_destination Pointer to destination */ +/* length Number of bytes to compare */ +/* */ +/* OUTPUT */ +/* */ +/* UX_SUCCESS If blocks are equal */ +/* UX_ERROR If blocks are not equal */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_memory_compare(VOID *memory_source, VOID *memory_destination, ULONG length) +{ + +UCHAR * source; +UCHAR * destination; + + + /* Setup source and destination byte oriented pointers. */ + source = (UCHAR *) memory_source; + destination = (UCHAR *) memory_destination; + + /* Loop to compare blocks. */ + while(length--) + { + + /* Compare a single byte. */ + if(*destination++ != *source++) + { + + /* Not equal, return an error. */ + return(UX_ERROR); + } + } + + /* Blocks are equal, return success. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_copy.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_copy.c new file mode 100644 index 00000000..9a06d2c8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_copy.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_copy PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function copies a block of memory from a source to a */ +/* destination. */ +/* */ +/* INPUT */ +/* */ +/* memory_destination Pointer to destination */ +/* memory_source Pointer to source */ +/* length Number of bytes to copy */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_memory_copy(VOID *memory_destination, VOID *memory_source, ULONG length) +{ + +UCHAR * source; +UCHAR * destination; + + /* Setup byte oriented source and destination pointers. */ + source = (UCHAR *) memory_source; + destination = (UCHAR *) memory_destination; + + /* Loop to perform the copy. */ + while(length--) + { + + /* Copy one byte. */ + *destination++ = *source++; + } + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_free.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_free.c new file mode 100644 index 00000000..24607df8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_free.c @@ -0,0 +1,233 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_free PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function frees a previously allocated memory block. */ +/* */ +/* INPUT */ +/* */ +/* memory Pointer to memory block */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_mutex_on Start system protection */ +/* _ux_utility_mutex_off End system protection */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_memory_free(VOID *memory) +{ + +UX_MEMORY_BLOCK *memory_block; +UX_MEMORY_BLOCK *next_block; +ULONG memory_size_returned; +UCHAR *memory_address; +#ifdef UX_ENABLE_MEMORY_POOL_SANITY_CHECK +UCHAR *regular_start, *regular_end; +UCHAR *cache_safe_start, *cache_safe_end; +#endif + + /* Get the mutex as this is a critical section. */ + _ux_system_mutex_on(&_ux_system -> ux_system_mutex); + +#ifdef UX_ENABLE_MEMORY_POOL_SANITY_CHECK + + /* Sanity check, check if the memory is in memory pool. */ + regular_start = (UCHAR *)_ux_system -> ux_system_regular_memory_pool_start; + regular_end = regular_start + _ux_system -> ux_system_regular_memory_pool_size; + regular_start += sizeof(UX_MEMORY_BLOCK); + cache_safe_start = (UCHAR *)_ux_system -> ux_system_cache_safe_memory_pool_start; + cache_safe_end = cache_safe_start + _ux_system -> ux_system_cache_safe_memory_pool_size; + cache_safe_start += sizeof(UX_MEMORY_BLOCK); + memory_address = (UCHAR *)memory; + if (!((memory_address >= regular_start && memory_address < regular_end) || + (memory_address >= cache_safe_start && memory_address < cache_safe_end))) + { + + /* Not valid. Release the protection. */ + _ux_system_mutex_off(&_ux_system -> ux_system_mutex); + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, + UX_SYSTEM_CONTEXT_UTILITY, UX_MEMORY_CORRUPTED); + + /* No action taken. */ + return; + } +#endif + + /* The memory block for this memory pointer is located right before the + memory. */ + memory_block = (UX_MEMORY_BLOCK *) (((UCHAR *) memory) - sizeof(UX_MEMORY_BLOCK)); + + /* Keep track of the memory returned to the pool. */ + memory_size_returned = memory_block -> ux_memory_block_size + (ULONG)sizeof(UX_MEMORY_BLOCK); + + /* Check this memory block to see if it valid. */ + if (memory_block -> ux_memory_block_status != (UX_MEMORY_USED | UX_REGULAR_MEMORY) && + memory_block -> ux_memory_block_status != (UX_MEMORY_USED | UX_CACHE_SAFE_MEMORY)) + { + + /* Not valid. Release the protection. */ + _ux_system_mutex_off(&_ux_system -> ux_system_mutex); + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, UX_MEMORY_CORRUPTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MEMORY_CORRUPTED, memory, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return to caller. */ + return; + } + +#ifdef UX_ENABLE_MEMORY_STATISTICS + + /* Update allocate count, total size. */ + if (memory_block -> ux_memory_block_status == (UX_MEMORY_USED | UX_REGULAR_MEMORY)) + { + _ux_system -> ux_system_regular_memory_pool_alloc_count --; + _ux_system -> ux_system_regular_memory_pool_alloc_total -= memory_block -> ux_memory_block_size; + } + else + { + _ux_system -> ux_system_cache_safe_memory_pool_alloc_count --; + _ux_system -> ux_system_cache_safe_memory_pool_alloc_total -= memory_block -> ux_memory_block_size; + } +#endif + + /* We mark this memory block as being unused. */ + memory_block -> ux_memory_block_status = UX_MEMORY_UNUSED; + + /* Now we must concatenate as many free blocks as possible, + that include the blocks before and the blocks after the current + block. Scan memory backwards. */ + + while (memory_block -> ux_memory_block_previous !=UX_NULL) + { + + /* Check if the block is free. */ + if (memory_block -> ux_memory_block_previous -> ux_memory_block_status == UX_MEMORY_UNUSED) + + /* The memory block before is free. This will be our starting point to + concatenate memory. */ + memory_block = memory_block -> ux_memory_block_previous; + + else + + /* The previous memory block is not free. */ + break; + } + + /* The pointer to the memory block is now our first free block. We use this + starting address to concatenate all the contiguous memory block. */ + next_block = memory_block -> ux_memory_block_next; + while (next_block != UX_NULL) + { + + /* Determine if the memory block is used. */ + if (next_block -> ux_memory_block_status != UX_MEMORY_UNUSED) + { + + /* Yes, move to next block. */ + memory_block -> ux_memory_block_next = next_block; + next_block -> ux_memory_block_previous = memory_block; + break; + } + + memory_block -> ux_memory_block_next = next_block -> ux_memory_block_next; + memory_block -> ux_memory_block_size += next_block -> ux_memory_block_size + (ULONG)sizeof(UX_MEMORY_BLOCK); + next_block = next_block -> ux_memory_block_next; + } + + /* Update the memory free in the appropriate pool. We need to know if this + block is in regular memory or cache safe memory. */ + if(_ux_system -> ux_system_cache_safe_memory_pool_start == _ux_system -> ux_system_regular_memory_pool_start) + { + + /* There is only one regular memory pool. */ + _ux_system -> ux_system_regular_memory_pool_free += memory_size_returned; + + } + else + { + + /* Which pool is this memory in ? */ + memory_address = (UCHAR *) _ux_system -> ux_system_regular_memory_pool_start; + + /* If the memory address is in this range, we are in the regular memory pool. */ + if ((UCHAR *) memory_block >= memory_address && (UCHAR *) memory_block < (memory_address + _ux_system -> ux_system_regular_memory_pool_size)) + + /* Update the regular memory pool. */ + _ux_system -> ux_system_regular_memory_pool_free += memory_size_returned; + + else + + /* Update the cache safe memory pool. */ + _ux_system -> ux_system_cache_safe_memory_pool_free += memory_size_returned; + + } + + /* Release the protection. */ + _ux_system_mutex_off(&_ux_system -> ux_system_mutex); + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_free_block_best_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_free_block_best_get.c new file mode 100644 index 00000000..604a02a4 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_free_block_best_get.c @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** USBX main stack */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_free_block_best_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns the best free memory block. */ +/* */ +/* INPUT */ +/* */ +/* memory_cache_flag Memory pool source */ +/* memory_size_requested Size of memory requested */ +/* */ +/* OUTPUT */ +/* */ +/* Pointer to best free block */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UX_MEMORY_BLOCK *_ux_utility_memory_free_block_best_get(ULONG memory_cache_flag, + ULONG memory_size_requested) +{ + +UX_MEMORY_BLOCK *memory_block; +UX_MEMORY_BLOCK *best_memory_block; + + + /* Reset the free memory block. */ + best_memory_block = UX_NULL; + + /* Check the type of memory we need. */ + switch (memory_cache_flag) + { + + case UX_REGULAR_MEMORY : + + /* Start at the beginning of the regular memory pool. */ + memory_block = _ux_system -> ux_system_regular_memory_pool_start; + break; + + case UX_CACHE_SAFE_MEMORY : + + /* Start at the beginning of the cache safe memory pool. */ + memory_block = _ux_system -> ux_system_cache_safe_memory_pool_start; + break; + + default : + + /* Wrong memory type. */ + return(UX_NULL); + + } + + /* Loop on all memory blocks from the beginning. */ + while (memory_block != UX_NULL) + { + + /* Check the memory block status. */ + if (memory_block -> ux_memory_block_status == UX_MEMORY_UNUSED) + { + + /* Check the size of this free block and see if it will + fit the memory requirement. */ + if (memory_block -> ux_memory_block_size > memory_size_requested) + { + + /* This memory block will do. Now see if it is the best. + The best memory block is the one whose memory is closest + to the memory requested. */ + if (best_memory_block == UX_NULL) + + /* Initialize the best block with the first free one. */ + best_memory_block = memory_block; + else + { + + if (memory_block -> ux_memory_block_size < best_memory_block -> ux_memory_block_size) + + /* We have discovered a better fit block. */ + best_memory_block = memory_block; + } + } + } + + /* Search the next free block until the end. */ + memory_block = memory_block -> ux_memory_block_next; + } + + /* If no free memory block was found, the return value will be NULL. */ + return(best_memory_block); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_set.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_set.c new file mode 100644 index 00000000..34808b09 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_memory_set.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_memory_set PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets a memory block with a specific value. */ +/* */ +/* INPUT */ +/* */ +/* destination Destination address */ +/* value 8-bit value */ +/* length Size of memory to set */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_memory_set(VOID *destination, UCHAR value, ULONG length) +{ + +UCHAR * work_ptr; + + + /* Setup the working pointer */ + work_ptr = (UCHAR *) destination; + + /* Loop to set the memory. */ + while(length--) + { + + /* Set a byte. */ + *work_ptr++ = value; + } + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_create.c new file mode 100644 index 00000000..a46a4bf0 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_create.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_mutex_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a protection mutex. */ +/* */ +/* INPUT */ +/* */ +/* mutex Pointer to mutex */ +/* mutex_name Name of mutex */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_mutex_create ThreadX mutex create */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_mutex_create(UX_MUTEX *mutex, CHAR *mutex_name) +{ + +UINT status; + + + /* Call ThreadX to create the Mutex object. */ + status = tx_mutex_create(mutex, (CHAR *) mutex_name, TX_NO_INHERIT); + + /* Check for status. */ + if (status != UX_SUCCESS) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, status); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MUTEX_ERROR, mutex, 0, 0, UX_TRACE_ERRORS, 0, 0) + + } + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_delete.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_delete.c new file mode 100644 index 00000000..4cbaf2cd --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_delete.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_mutex_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes a protection mutex. */ +/* */ +/* INPUT */ +/* */ +/* mutex Pointer to mutex */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_mutex_create ThreadX mutex create */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_mutex_delete(UX_MUTEX *mutex) +{ + +UINT status; + + + /* Call ThreadX to delete the Mutex object. */ + status = tx_mutex_delete(mutex); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_off.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_off.c new file mode 100644 index 00000000..aca726fa --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_off.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_mutex_off PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function releases system protection. */ +/* */ +/* INPUT */ +/* */ +/* Mutex */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* tx_mutex_put ThreadX mutex put */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_mutex_off(UX_MUTEX *mutex) +{ + + /* Call ThreadX to release protection. */ + tx_mutex_put(mutex); + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_on.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_on.c new file mode 100644 index 00000000..f2f2bb0f --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_mutex_on.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_mutex_on PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets system protection. */ +/* */ +/* INPUT */ +/* */ +/* Mutex */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* tx_mutex_get ThreadX mutex get */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_mutex_on(UX_MUTEX *mutex) +{ + +UINT status; + + /* Call ThreadX to get system mutex. */ + status = tx_mutex_get(mutex, TX_WAIT_FOREVER); + + /* Check for status. */ + if (status != UX_SUCCESS) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, status); + } + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_class_scan.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_class_scan.c new file mode 100644 index 00000000..8ce710c9 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_class_scan.c @@ -0,0 +1,132 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_pci_class_scan PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function scans the PCI bus from a certain position for a */ +/* specific PCI class. */ +/* */ +/* INPUT */ +/* */ +/* pci_class PCI class requested */ +/* bus_number PCI bus number */ +/* device_number Device number */ +/* function_number Function number */ +/* current_bus_number Current bus number */ +/* current_device_number Current device number */ +/* current_function_number Current function number */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit value */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_pci_read PCI read utility */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _ux_utility_pci_class_scan(ULONG pci_class, ULONG bus_number, ULONG device_number, + ULONG function_number, ULONG *current_bus_number, + ULONG *current_device_number, ULONG *current_function_number) +{ + +ULONG bus_number_index; +ULONG device_number_index; +ULONG function_number_index; +ULONG value; +ULONG current_pci_class; + + + /* Scan all bus. */ + for (bus_number_index = bus_number; bus_number_index <= UX_PCI_NB_BUS; bus_number_index++) + { + + /* Scan all devices. */ + for(device_number_index = device_number;device_number_index <= UX_PCI_NB_DEVICE; device_number_index++) + { + + /* Scan all functions. */ + for(function_number_index = function_number; function_number_index <= UX_PCI_NB_FUNCTIONS; function_number_index++) + { + + /* Reset all PCI address for next loop. */ + function_number = 0; + device_number = 0; + bus_number = 0; + + /* Read the PCI class bus/device/function. */ + value = _ux_utility_pci_read(bus_number_index, device_number_index, function_number_index, + UX_PCI_CFG_REVISION,32); + + /* Isolate the class code which is in the upper 3 bytes. */ + current_pci_class = (value >> 8) & 0x00ffffff; + + /* Do we have a match with the demanded class? */ + if(current_pci_class == pci_class) + { + + /* Return the position of this device on the PCI */ + *current_bus_number = bus_number_index; + *current_device_number = device_number_index; + *current_function_number = function_number_index; + + /* Return success! */ + return(UX_SUCCESS); + } + } + } + } + + /* Return an error since we didn't find anything. */ + return(UX_ERROR); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_read.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_read.c new file mode 100644 index 00000000..19a6dcd6 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_read.c @@ -0,0 +1,125 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_pci_read PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads a 32/16/8 bit value from a specific PCI bus */ +/* at a certain offset. */ +/* */ +/* INPUT */ +/* */ +/* bus_number PCI bus number */ +/* device_number Device number */ +/* function_number Function number */ +/* offset Offset */ +/* read_size Size of read */ +/* */ +/* OUTPUT */ +/* */ +/* 32-bit value */ +/* */ +/* CALLS */ +/* */ +/* inpl PCI input long */ +/* inpw PCI input word */ +/* inpb PCI input byte */ +/* outpl PCI output function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _ux_utility_pci_read(ULONG bus_number, ULONG device_number, ULONG function_number, + ULONG offset, UINT read_size) +{ + +ULONG destination_address; +ULONG cfg_ctrl; + + + /* Calculate the destination address. */ + destination_address = (((bus_number << 16) & 0x00ff0000) | ((device_number << 11) & 0x0000f800) | + ((function_number << 8) & 0x00000700)); + + /* Calculate the configure control value. */ + cfg_ctrl = destination_address | offset | 0x80000000; + + /* Read based on the size requested. */ + switch(read_size) + { + + case 32: + + /* Write the address we need to read from. */ + outpl(UX_PCI_CFG_CTRL_ADDRESS, cfg_ctrl); + + /* Return the 32 bit content of this address. */ + return(inpl(UX_PCI_CFG_DATA_ADDRESS)); + + case 16: + + /* Write the address we need to read from. */ + outpl(UX_PCI_CFG_CTRL_ADDRESS, cfg_ctrl); + + /* Return the 16 bit content of this address. */ + return((USHORT)(inpw(UX_PCI_CFG_DATA_ADDRESS))); + + case 8: + + /* Write the address we need to read from. */ + outpl(UX_PCI_CFG_CTRL_ADDRESS, cfg_ctrl); + + /* Return the 8 bit content of this address */ + return((ULONG)(inpb(UX_PCI_CFG_DATA_ADDRESS))); + + default: + + return(0); + } +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_write.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_write.c new file mode 100644 index 00000000..7081b3de --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_pci_write.c @@ -0,0 +1,129 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_pci_write PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes a 32/16/8 bit value to a specific PCI bus */ +/* at a certain offset. */ +/* */ +/* INPUT */ +/* */ +/* bus_number PCI bus number */ +/* device_number Device number */ +/* function_number Function number */ +/* offset Offset */ +/* value Value to write */ +/* write_size Size of write */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* outpl PCI output long function */ +/* outpw PCI output word function */ +/* outpb PCI output byte function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_pci_write(ULONG bus_number, ULONG device_number, ULONG function_number, + ULONG offset, ULONG value, UINT write_size) +{ + +ULONG destination_address; +ULONG cfg_ctrl; + + + /* Calculate the destination address. */ + destination_address = (((bus_number << 16) & 0x00ff0000) | ((device_number << 11) & 0x0000f800) | + ((function_number << 8) & 0x00000700)); + + /* Calculate the configure control value. */ + cfg_ctrl = destination_address | offset | 0x80000000; + + /* Process relative to write size. */ + switch(write_size) + { + + case 32: + + /* Write the address we need to write to. */ + outpl(UX_PCI_CFG_CTRL_ADDRESS, cfg_ctrl); + + /* Write the 32 bit content of this address. */ + outpl(UX_PCI_CFG_DATA_ADDRESS, value); + break; + + case 16: + + /* Write the address we need to write to. */ + outpl(UX_PCI_CFG_CTRL_ADDRESS, cfg_ctrl); + + /* Write the 16 bit content of this address. */ + outpw(UX_PCI_CFG_DATA_ADDRESS + (offset & 2), (USHORT) value); + break; + + case 8: + + /* Write the address we need to write to. */ + outpl(UX_PCI_CFG_CTRL_ADDRESS, cfg_ctrl); + + /* Write the 8 bit content of this address */ + outpb(UX_PCI_CFG_DATA_ADDRESS + (offset & 3), (UCHAR) value); + break; + + default: + + break; + } +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_physical_address.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_physical_address.c new file mode 100644 index 00000000..28b5af2a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_physical_address.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_physical_address PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns a physical address given the supplied */ +/* virtual address. */ +/* */ +/* INPUT */ +/* */ +/* virtual_address Physical address */ +/* */ +/* OUTPUT */ +/* */ +/* physical_address Virtual address */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID *_ux_utility_physical_address(VOID *virtual_address) +{ + +VOID *physical_address; + + /* Any code to translate the virtual address into a physical address + will be below. If there is no translation, the physical address= + the virtual address. */ + + physical_address = virtual_address; + + return(physical_address); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_create.c new file mode 100644 index 00000000..13f19611 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_create.c @@ -0,0 +1,98 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_semaphore_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a semaphore. */ +/* */ +/* INPUT */ +/* */ +/* semaphore Semaphore to create */ +/* semaphore_name Semaphore name */ +/* initial_count Initial semaphore count */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_semaphore_create ThreadX semaphore create */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_semaphore_create(UX_SEMAPHORE *semaphore, CHAR *semaphore_name, UINT initial_count) +{ + +UINT status; + + /* Call ThreadX to create the semaphore. */ + status = tx_semaphore_create(semaphore, (CHAR *) semaphore_name, initial_count); + + /* Check for status. */ + if (status != UX_SUCCESS) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, status); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_SEMAPHORE_ERROR, semaphore, 0, 0, UX_TRACE_ERRORS, 0, 0) + + } + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_delete.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_delete.c new file mode 100644 index 00000000..53acb35c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_delete.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_semaphore_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes the specified semaphore. */ +/* */ +/* INPUT */ +/* */ +/* semaphore Semaphore to delete */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_semaphore_delete ThreadX semaphore delete */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_semaphore_delete(UX_SEMAPHORE *semaphore) +{ + +UINT status; + + /* Call ThreadX Semaphore delete function. */ + status = tx_semaphore_delete(semaphore); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_get.c new file mode 100644 index 00000000..ae5410c0 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_get.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_semaphore_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function gets a semaphore signal. */ +/* */ +/* INPUT */ +/* */ +/* semaphore Semaphore to get signal from */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_identify ThreadX identify thread */ +/* tx_thread_info_get ThreadX get thread info */ +/* tx_semaphore_get ThreadX semaphore get */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_semaphore_get(UX_SEMAPHORE *semaphore, ULONG semaphore_signal) +{ + +UINT status; +UX_THREAD *my_thread; +CHAR *name; +UINT state; +ULONG run_count; +UINT priority; +UINT preemption_threshold; +ULONG time_slice; +UX_THREAD *next_thread; +UX_THREAD *suspended_thread; + + /* Call TX to know my own tread. */ + my_thread = tx_thread_identify(); + + /* Retrieve information about the previously created thread "my_thread." */ + tx_thread_info_get(my_thread, &name, &state, &run_count, + &priority, &preemption_threshold, + &time_slice, &next_thread,&suspended_thread); + + /* Is this the lowest priority thread in the system trying to use TX services ? */ + if (priority > _ux_system -> ux_system_thread_lowest_priority) + { + + /* We need to remember this thread priority. */ + _ux_system -> ux_system_thread_lowest_priority = priority; + + } + + /* Get ThreadX semaphore instance. */ + status = tx_semaphore_get(semaphore, semaphore_signal); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_put.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_put.c new file mode 100644 index 00000000..18ea5be7 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_semaphore_put.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_semaphore_put PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sets a semaphore signal. */ +/* */ +/* INPUT */ +/* */ +/* semaphore Semaphore to signal */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_semaphore_put ThreadX semaphore put */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_semaphore_put(UX_SEMAPHORE *semaphore) +{ + +UINT status; + + /* Put a ThreadX semaphore. */ + status = tx_semaphore_put(semaphore); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_set_interrupt_handler.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_set_interrupt_handler.c new file mode 100644 index 00000000..bf150cd2 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_set_interrupt_handler.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_set_interrupt_handler PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function installs an interrupt handler for USBX. */ +/* */ +/* INPUT */ +/* */ +/* irq Interrupt to install */ +/* interrupt_handler Pointer to interrupt handler */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_set_interrupt_handler(UINT irq, VOID (*interrupt_handler)(VOID)) +{ + + UX_PARAMETER_NOT_USED(interrupt_handler); + UX_PARAMETER_NOT_USED(irq); + + /* Unimplemented, just return. */ + return; +} diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_get.c new file mode 100644 index 00000000..84abbba2 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_get.c @@ -0,0 +1,84 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_short_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads a 16-bit value. */ +/* */ +/* INPUT */ +/* */ +/* address Source address */ +/* */ +/* OUTPUT */ +/* */ +/* 16-bit value */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _ux_utility_short_get(UCHAR * address) +{ + +USHORT value; + + + /* In order to make this function endian agnostic and memory alignment + independent, we read a byte at a time from the address. */ + value = (USHORT) *address++; + value |= (USHORT)(*address << 8); + + /* Return to caller. */ + return((ULONG) value); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_get_big_endian.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_get_big_endian.c new file mode 100644 index 00000000..54fb14af --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_get_big_endian.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_short_get_big_endian PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function reads a 16-bit value in big endian format. */ +/* */ +/* INPUT */ +/* */ +/* address Source address */ +/* */ +/* OUTPUT */ +/* */ +/* 16-bit value */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _ux_utility_short_get_big_endian(UCHAR * address) +{ + +USHORT value; + + /* We read a byte at a time from the address. */ + value = (USHORT)((*address++) << 8); + value = (USHORT)(value | *address); + + /* Return 16-bit value. */ + return((ULONG) value); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_put.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_put.c new file mode 100644 index 00000000..d25f5eae --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_put.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_short_put PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes a 16-bit value. */ +/* */ +/* INPUT */ +/* */ +/* address Destination address */ +/* value 16-bit value */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_short_put(UCHAR * address, USHORT value) +{ + + /* In order to make this function endian agnostic and memory alignment + independent, we write a byte at a time from the address */ + *address++ = (UCHAR) (value & 0xff); + *address = (UCHAR) ((value >> 8) & 0xff); + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_put_big_endian.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_put_big_endian.c new file mode 100644 index 00000000..2c3cfaaf --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_short_put_big_endian.c @@ -0,0 +1,91 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_short_put_big_endian PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function writes a 16-bit value in big endian format. */ +/* */ +/* INPUT */ +/* */ +/* address Destination address */ +/* value 16-bit value */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_short_put_big_endian(UCHAR * address, USHORT value) +{ + +USHORT low_byte_value; +USHORT high_byte_value; + + + /* First we swap the value bytes. */ + low_byte_value = value >> 8; + high_byte_value = (USHORT)(value<< 8); + value = high_byte_value | low_byte_value; + + /* In order to make this function endian agnostic and memory alignment + independent, we write a byte at a time from the address. */ + *address++ = (UCHAR) (value & 0xff); + *address= (UCHAR) ((value >> 8) & 0xff); + + /* Return to caller. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_length_check.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_length_check.c new file mode 100644 index 00000000..6e31fd9a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_length_check.c @@ -0,0 +1,112 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_string_length_check PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function checks if a NULL-terminated C string reaches its end */ +/* before specified length exceeds. */ +/* */ +/* On success the actual length of C string is written back to UINT */ +/* variable pointed by string_length_ptr (if not NULL). */ +/* Otherwise the variable keeps untouched. */ +/* */ +/* INPUT */ +/* */ +/* string Pointer to string */ +/* string_length_ptr Pointer to UINT to receive */ +/* the string length */ +/* max_string_length Max string length */ +/* */ +/* OUTPUT */ +/* */ +/* returns success if the string length was less than the max length, */ +/* else it returns error */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_string_length_check(UCHAR *string, UINT *string_length_ptr, UINT max_string_length) +{ + +UINT string_length; + + + if (string == UX_NULL) + return(UX_ERROR); + + string_length = 0; + + while (1) + { + + if (string[string_length] == '\0') + break; + + string_length++; + if (string_length > max_string_length) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, UX_ERROR); + + return(UX_ERROR); + } + } + + if (string_length_ptr) + *string_length_ptr = string_length; + + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_length_get.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_length_get.c new file mode 100644 index 00000000..15b7897a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_length_get.c @@ -0,0 +1,93 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_string_length_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function derives the length of a NULL-terminated string. */ +/* */ +/* This function is deprecated, for the possible issue of operating on */ +/* a buffer that is not NULL-terminated. As a replacement, */ +/* _ux_utility_string_length_check should be used, where the length of */ +/* the buffer is introduced to validate the string by checking for the */ +/* NULL-terminator within the buffer length. */ +/* */ +/* INPUT */ +/* */ +/* string Pointer to string */ +/* */ +/* OUTPUT */ +/* */ +/* length of string */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +ULONG _ux_utility_string_length_get(UCHAR *string) +{ + +ULONG length = 0; + + /* Loop to find the length of the string. */ + length = 0; + while (string[length]) + { + + /* Move to next position. */ + length++; + } + + /* Return length to caller. */ + return(length); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_to_unicode.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_to_unicode.c new file mode 100644 index 00000000..697a1113 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_string_to_unicode.c @@ -0,0 +1,111 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_string_to_unicode PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts a ascii string to a unicode string. */ +/* */ +/* Note: */ +/* The unicode string length (including NULL-terminator) is limited by */ +/* length in a byte, so max ascii string length must be no more than */ +/* 254 (NULL-terminator excluded). Only first 254 characters */ +/* are converted if the string is too long. */ +/* The buffer of destination must have enough space for result, at */ +/* least 1 + (strlen(source) + 1) * 2 bytes. */ +/* */ +/* INPUT */ +/* */ +/* source Ascii String */ +/* destination Unicode String */ +/* */ +/* OUTPUT */ +/* */ +/* none */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_string_length_check Check and return C string */ +/* length */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_string_to_unicode(UCHAR *source, UCHAR *destination) +{ + +UINT string_length; + + /* Get the ascii string length, when there is error length is not modified so max length is used. */ + string_length = 254; + _ux_utility_string_length_check(source, &string_length, 254); + + /* Set the length of the string as the first byte of the unicode string. + The length is casted as a byte since Unicode strings cannot be more than 255 chars. */ + *destination++ = (UCHAR)(string_length + 1); + + while(string_length--) + { + /* First character is from the source. */ + *destination++ = *source++; + + /* Second character of unicode word is 0. */ + *destination++ = 0; + } + + /* Finish with a 0. */ + *destination++ = 0; + + /* Finish with a 0. */ + *destination++ = 0; + + /* We are done. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_create.c new file mode 100644 index 00000000..899185f8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_create.c @@ -0,0 +1,110 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_thread_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a thread for USBX. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* name Pointer to thread name string */ +/* entry_function Entry function of the thread */ +/* entry_input 32-bit input value to thread */ +/* stack_start Pointer to start of stack */ +/* stack_size Stack size in bytes */ +/* priority Priority of thread (0-31) */ +/* preempt_threshold Preemption threshold */ +/* time_slice Thread time-slice value */ +/* auto_start Automatic start selection */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_create ThreadX create thread function*/ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_thread_create(UX_THREAD *thread_ptr, CHAR *name, + VOID (*entry_function)(ULONG), ULONG entry_input, + VOID *stack_start, ULONG stack_size, + UINT priority, UINT preempt_threshold, + ULONG time_slice, UINT auto_start) +{ + +UINT status; + + + /* Call ThreadX to create USBX thread. */ + status = tx_thread_create(thread_ptr,name,entry_function,entry_input, + stack_start,stack_size, priority,preempt_threshold,time_slice,auto_start); + + /* Check for status. */ + if (status != UX_SUCCESS) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, status); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_THREAD_ERROR, thread_ptr, 0, 0, UX_TRACE_ERRORS, 0, 0) + + } + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_delete.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_delete.c new file mode 100644 index 00000000..b1043ffa --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_delete.c @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_thread_delete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deletes a thread for USBX. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_terminate ThreadX terminate thread */ +/* tx_thread_delete ThreadX delete thread service */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_thread_delete(UX_THREAD *thread_ptr) +{ + +UINT status; + + + /* Call ThreadX to terminate the USBX thread. */ + tx_thread_terminate(thread_ptr); + + /* Call ThreadX to delete the USBX thread. */ + status = tx_thread_delete(thread_ptr); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_identify.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_identify.c new file mode 100644 index 00000000..80677066 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_identify.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "tx_thread.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_thread_identify PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function return a pointer to the calling thread. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_identify ThreadX identify function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UX_THREAD *_ux_utility_thread_identify(VOID) +{ + + + /* If we're under interrupt, the thread returned by tx_thread_identify + is the thread running prior to the ISR. Instead, we set it to null. */ + return(UX_THREAD_GET_SYSTEM_STATE() ? UX_NULL : tx_thread_identify()); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_relinquish.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_relinquish.c new file mode 100644 index 00000000..4d271ce3 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_relinquish.c @@ -0,0 +1,75 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_thread_relinquish PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function helps the thread relinquish its control. */ +/* */ +/* INPUT */ +/* */ +/* */ +/* OUTPUT */ +/* */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_relinquish ThreadX relinquish thread */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_thread_relinquish(VOID) +{ + + /* Call ThreadX to relinquish a USBX thread. */ + tx_thread_relinquish(); + +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_resume.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_resume.c new file mode 100644 index 00000000..6f93ef63 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_resume.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_thread_resume PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function resumes a thread for USBX. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_resume ThreadX resume thread function*/ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_thread_resume(UX_THREAD *thread_ptr) +{ + +UINT status; + + + /* Call ThreadX to resume USBX thread. */ + status = tx_thread_resume(thread_ptr); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_schedule_other.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_schedule_other.c new file mode 100644 index 00000000..e25f8f59 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_schedule_other.c @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_thread_schedule_other PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function force the scheduling of all other threads. */ +/* */ +/* INPUT */ +/* */ +/* caller_priority Priority to restore. */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_identify ThreadX identify */ +/* tx_thread_priority_change ThreadX priority change */ +/* tx_thread_relinquish ThreadX relinquish */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_thread_schedule_other(UINT caller_priority) +{ + +UINT status; +UINT old_priority; +UX_THREAD *my_thread; + + UX_PARAMETER_NOT_USED(caller_priority); + + /* Call TX to know my own tread. */ + my_thread = tx_thread_identify(); + + /* Call ThreadX to change thread priority . */ + status = tx_thread_priority_change(my_thread, _ux_system -> ux_system_thread_lowest_priority, &old_priority); + + /* Check for error. */ + if (status == TX_SUCCESS) + { + + /* Wait until all other threads passed into the scheduler. */ + _ux_utility_thread_relinquish(); + + /* And now return the priority of the thread to normal. */ + status = tx_thread_priority_change(my_thread, old_priority, &old_priority); + + } + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_sleep.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_sleep.c new file mode 100644 index 00000000..e99f4f83 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_sleep.c @@ -0,0 +1,81 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_thread_sleep PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function causes the calling thread to sleep for the */ +/* specified number of ticks. */ +/* */ +/* INPUT */ +/* */ +/* ticks Number of ticks to sleep */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_sleep ThreadX sleep function */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_thread_sleep(ULONG ticks) +{ + +UINT status; + + /* Call ThreadX sleep function. */ + status = tx_thread_sleep(ticks); + + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_suspend.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_suspend.c new file mode 100644 index 00000000..0faccc97 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_thread_suspend.c @@ -0,0 +1,85 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_thread_suspend PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function suspends thread for USBX. */ +/* */ +/* INPUT */ +/* */ +/* thread_ptr Thread control block pointer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_thread_suspend ThreadX suspend thread service*/ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_thread_suspend(UX_THREAD *thread_ptr) +{ + +UINT status; + + + /* Call ThreadX to suspend USBX thread. */ + status = tx_thread_suspend(thread_ptr); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_timer_create.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_timer_create.c new file mode 100644 index 00000000..2655e94a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_timer_create.c @@ -0,0 +1,92 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_timer_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function creates a timer. */ +/* */ +/* INPUT */ +/* */ +/* timer Pointer to timer */ +/* timer_name Name of timer */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* tx_timer_create ThreadX timer create */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_utility_timer_create(TX_TIMER *timer, CHAR *timer_name, VOID (*expiration_function) (ULONG), + ULONG expiration_input, ULONG initial_ticks, ULONG reschedule_ticks, + UINT activation_flag) +{ + +UINT status; + + + /* Call ThreadX to create the timer object. */ + status = tx_timer_create(timer, (CHAR *) timer_name, expiration_function, expiration_input, + initial_ticks, reschedule_ticks, activation_flag); + + /* Check status. */ + if (status != UX_SUCCESS) + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_UTILITY, status); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_unicode_to_string.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_unicode_to_string.c new file mode 100644 index 00000000..9d725d30 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_unicode_to_string.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_unicode_to_string PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function converts a unicode string to a zero terminated */ +/* ascii string. */ +/* */ +/* INPUT */ +/* */ +/* source Unicode String */ +/* destination Ascii String */ +/* */ +/* OUTPUT */ +/* */ +/* none */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_utility_unicode_to_string(UCHAR *source, UCHAR *destination) +{ +ULONG string_length; + + /* Obtain the length of the unicode string. This is the first byte*/ + string_length = (ULONG) *source++; + + /* Parse the unicode string. First byte is always 0, second byte is the + ASCII character. */ + while(string_length--) + { + /* First character is from the source. */ + *destination++ = *source++; + + /* Second character of unicode word is 0. */ + source++; + } + + /* We are done with the ascii string. Insert a zero at the end. */ + *destination = 0; + + /* Finished. */ + return; +} + diff --git a/src/Middlewares/ST/usbx/common/core/src/ux_utility_virtual_address.c b/src/Middlewares/ST/usbx/common/core/src/ux_utility_virtual_address.c new file mode 100644 index 00000000..4e614b31 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/core/src/ux_utility_virtual_address.c @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Utility */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_utility_virtual_address PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function returns a virtual address given the supplied */ +/* physical address. */ +/* */ +/* INPUT */ +/* */ +/* physical_address Virtual address */ +/* */ +/* OUTPUT */ +/* */ +/* virtual_address Physical address */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Components */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID *_ux_utility_virtual_address(VOID *physical_address) +{ + +VOID *virtual_address; + + /* Any code to translate the physical address into a virtual address + will be below. If there is no translation, the physical address= + the virtual address. */ + + virtual_address = physical_address; + return(virtual_address); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio.h new file mode 100644 index 00000000..c5cf0814 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio.h @@ -0,0 +1,476 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Audio Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_audio.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX audio class. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 08-02-2021 Wen Wang Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added feedback support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_AUDIO_H +#define UX_DEVICE_CLASS_AUDIO_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Compile option: if defined, audio feedback endpoint is supported. */ +/* #define UX_DEVICE_CLASS_AUDIO_FEEDBACK_SUPPORT */ + + +/* Define Audio Class function (AF) constants. */ + +#define UX_DEVICE_CLASS_AUDIO_FUNCTION_CLASS 1 +#define UX_DEVICE_CLASS_AUDIO_FUNCTION_SUBCLASS_UNDEFINED 0 +#define UX_DEVICE_CLASS_AUDIO_FUNCTION_PROTOCOL_UNDEFINED 0 +#define UX_DEVICE_CLASS_AUDIO_FUNCTION_PROTOCOL_VERSION_02_00 0x20 + +/* Define Audio Class interface constants. */ + +#define UX_DEVICE_CLASS_AUDIO_CLASS 1 + +#define UX_DEVICE_CLASS_AUDIO_SUBCLASS_UNDEFINED 0 +#define UX_DEVICE_CLASS_AUDIO_SUBCLASS_CONTROL 1 +#define UX_DEVICE_CLASS_AUDIO_SUBCLASS_AUDIOSTREAMING 2 +#define UX_DEVICE_CLASS_AUDIO_SUBCLASS_MIDISTREAMING 3 + +#define UX_DEVICE_CLASS_AUDIO_PROTOCOL_UNDEFINED 0 +#define UX_DEVICE_CLASS_AUTIO_PROTOCOL_VERSION_02_00 0x20 + + +/* Define Audio Class-specific (CS) descriptor types. */ + +#define UX_DEVICE_CLASS_AUDIO_CS_UNDEFINED 0x20 +#define UX_DEVICE_CLASS_AUDIO_CS_DEVICE 0x21 +#define UX_DEVICE_CLASS_AUDIO_CS_CONFIGURATION 0x22 +#define UX_DEVICE_CLASS_AUDIO_CS_STRING 0x23 +#define UX_DEVICE_CLASS_AUDIO_CS_INTERFACE 0x24 +#define UX_DEVICE_CLASS_AUDIO_CS_ENDPOINT 0x25 + + +/* Define Audio Class specific AC interface descriptor subclasses. */ + +#define UX_DEVICE_CLASS_AUDIO_AC_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO_AC_HEADER 0x01 +#define UX_DEVICE_CLASS_AUDIO_AC_INPUT_TERMINAL 0x02 +#define UX_DEVICE_CLASS_AUDIO_AC_OUTPUT_TERMINAL 0x03 +#define UX_DEVICE_CLASS_AUDIO_AC_FEATURE_UNIT 0x06 + + +/* Define Audio Class specific AS interface descriptor subclasses. */ + +#define UX_DEVICE_CLASS_AUDIO_AS_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO_AS_GENERAL 0x01 +#define UX_DEVICE_CLASS_AUDIO_AS_FORMAT_TYPE 0x02 + + +/* Define Audio Class data endpoint descriptor attributes. */ + +#define UX_DEVICE_CLASS_AUDIO_EP_TRANSFER_TYPE_MASK (0x3u<<0) +#define UX_DEVICE_CLASS_AUDIO_EP_TRANSFER_TYPE_ISOCHRONOUS (0x1u<<0) + +#define UX_DEVICE_CLASS_AUDIO_EP_SYNCHRONIZATION_TYPE_MASK (0x3u<<2) +#define UX_DEVICE_CLASS_AUDIO_EP_SYNCHRONIZATION_TYPE_ASYNCHRONOUS (0x1u<<2) +#define UX_DEVICE_CLASS_AUDIO_EP_SYNCHRONIZATION_TYPE_ADAPTIVE (0x2u<<2) +#define UX_DEVICE_CLASS_AUDIO_EP_SYNCHRONIZATION_TYPE_SYNCHRONOUS (0x3u<<2) + +#define UX_DEVICE_CLASS_AUDIO_EP_USAGE_TYPE_MASK (0x3u<<4) +#define UX_DEVICE_CLASS_AUDIO_EP_USAGE_TYPE_DATA (0x0u<<4) +#define UX_DEVICE_CLASS_AUDIO_EP_USAGE_TYPE_FEEDBACK (0x1u<<4) +#define UX_DEVICE_CLASS_AUDIO_EP_USAGE_TYPE_IMPLICIT_FEEDBACK (0x2u<<4) + + +/* Define Audio Class specific endpoint descriptor subtypes. */ + +#define UX_DEVICE_CLASS_AUDIO_EP_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO_EP_GENERAL 0x01 + + +/* Define Audio Class specific request codes. */ + +#define UX_DEVICE_CLASS_AUDIO_REQUEST_CODE_UNDEFINED 0x00 + +#define UX_DEVICE_CLASS_AUDIO_bmRequestType_GET_INTERFACE 0xA1 +#define UX_DEVICE_CLASS_AUDIO_bmRequestType_SET_INTERFACE 0x21 +#define UX_DEVICE_CLASS_AUDIO_bmRequestType_GET_ENDPOINT 0xA2 +#define UX_DEVICE_CLASS_AUDIO_bmRequestType_SET_ENDPOINT 0x22 + +#define UX_DEVICE_CLASS_AUDIO_REQUEST_REQUEST_TYPE 0 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_REQUEST 1 + +#define UX_DEVICE_CLASS_AUDIO_REQUEST_VALUE_LOW 2 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_CHANNEL_NUMBER 2 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_CN 2 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_MIXER_CONTROL_NUMBER 2 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_MCN 2 + +#define UX_DEVICE_CLASS_AUDIO_REQUEST_VALUE_HIGH 3 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_CONTROL_SELECTOR 3 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_CS 3 + +#define UX_DEVICE_CLASS_AUDIO_REQUEST_INDEX_LOW 4 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_ENDPOINT 4 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_INTERFACE 4 + +#define UX_DEVICE_CLASS_AUDIO_REQUEST_INDEX_HIGH 5 +#define UX_DEVICE_CLASS_AUDIO_REQUEST_ENEITY_ID 5 + +#define UX_DEVICE_CLASS_AUDIO_REQUEST_LENGTH 6 + + +/* Define Audio Class terminal types. */ + +#define UX_DEVICE_CLASS_AUDIO_UNDEFINED 0x0100 +#define UX_DEVICE_CLASS_AUDIO_USB_STREAMING 0x0101 +#define UX_DEVICE_CLASS_AUDIO_USB_VENDOR_SPECIFIC 0x01FF + + +/* Define Audio Class input terminal types. */ + +#define UX_DEVICE_CLASS_AUDIO_INPUT 0x0200 +#define UX_DEVICE_CLASS_AUDIO_MICROPHONE 0x0201 +#define UX_DEVICE_CLASS_AUDIO_DESKTOP_MICROPHONE 0x0202 +#define UX_DEVICE_CLASS_AUDIO_PERSONAL_MICROPHONE 0x0203 +#define UX_DEVICE_CLASS_AUDIO_OMNI_DIRECTIONAL_MICROPHONE 0x0204 +#define UX_DEVICE_CLASS_AUDIO_MICROPHONE_ARRAY 0x0205 +#define UX_DEVICE_CLASS_AUDIO_PROCESSING_MICROPHONE_ARRAY 0x0206 + + +/* Define Audio Class output terminal types. */ + +#define UX_DEVICE_CLASS_AUDIO_OUTPUT 0x0300 +#define UX_DEVICE_CLASS_AUDIO_SPEAKER 0x0301 +#define UX_DEVICE_CLASS_AUDIO_HEADPHONES 0x0302 +#define UX_DEVICE_CLASS_AUDIO_HEAD_MOUNTED_DISPLAY 0x0303 +#define UX_DEVICE_CLASS_AUDIO_DESKTOP_SPEAKER 0x0304 +#define UX_DEVICE_CLASS_AUDIO_ROOM_SPEAKER 0x0305 +#define UX_DEVICE_CLASS_AUDIO_COMMUNICATION_SPEAKER 0x0306 +#define UX_DEVICE_CLASS_AUDIO_LOW_FREQUENCY_SPEAKER 0x0307 + + +/* Define Audio Class bidirectional terminal types. */ + +#define UX_DEVICE_CLASS_AUDIO_BIDIRECTIONAL_UNDEFINED 0x0400 +#define UX_DEVICE_CLASS_AUDIO_HANDSET 0x0401 +#define UX_DEVICE_CLASS_AUDIO_HEADSET 0x0402 +#define UX_DEVICE_CLASS_AUDIO_SPEAKERPHONE 0x0403 +#define UX_DEVICE_CLASS_AUDIO_ECHO_SUPRESS_SPEAKERPHONE 0x0404 +#define UX_DEVICE_CLASS_AUDIO_ECHO_CANCEL_SPEAKERPHONE 0x0405 + + +/* Define Audio Class telephony terminal types. */ + +#define UX_DEVICE_CLASS_AUDIO_TELEPHONTY_UNDEFINED 0x0500 +#define UX_DEVICE_CLASS_AUDIO_PHONE_LINE 0x0501 +#define UX_DEVICE_CLASS_AUDIO_TELEPHONE 0x0502 +#define UX_DEVICE_CLASS_AUDIO_DOWN_LINE_PHONE 0x0503 + + +/* Define Audio Class external terminal types. */ + +#define UX_DEVICE_CLASS_AUDIO_EXTERNAL_UNDEFINED 0x0600 +#define UX_DEVICE_CLASS_AUDIO_ANALOG_CONNECTOR 0x0601 +#define UX_DEVICE_CLASS_AUDIO_DIGITAL_AUDIO_INTERFACE 0x0602 +#define UX_DEVICE_CLASS_AUDIO_LINE_CONNECTOR 0x0603 +#define UX_DEVICE_CLASS_AUDIO_LEGACY_AUDIO_CONNECTOR 0x0604 +#define UX_DEVICE_CLASS_AUDIO_S_PDIF_INTERFACE 0x0605 +#define UX_DEVICE_CLASS_AUDIO_1394_DA_STREAM 0x0606 +#define UX_DEVICE_CLASS_AUDIO_1394_DV_STREAM_SOUNDTRACK 0x0607 +#define UX_DEVICE_CLASS_AUDIO_ADAT_LIGHTPIPE 0x0608 +#define UX_DEVICE_CLASS_AUDIO_TDIF 0x0609 +#define UX_DEVICE_CLASS_AUDIO_MADI 0x060A + + +/* Define Audio Class embedded function terminal types. */ + +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_UNDEFINED 0x0700 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_LEVEL_CALIB_NOISE_SRC 0x0701 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_EQUALIZATION_NOISE 0x0702 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_CD_PLAYER 0x0703 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_DAT 0x0704 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_DCC 0x0705 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_MINIDISK 0x0706 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_ANALOG_TAPE 0x0707 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_PHONOGRAPH 0x0708 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_VCR_AUDIO 0x0709 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_VIDEO_DISC_AUDIO 0x070A +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_DVD_AUDIO 0x070B +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_TV_TUNER_AUDIO 0x070C +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_SATELLITE_RECEIVER_AUDIO 0x070D +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_CABLE_TUNER_AUDIO 0x070E +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_DSS_AUDIO 0x070F +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_RADIO_RECEIVER 0x0710 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_RADIO_TRANSMITTER 0x0711 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_MULTI_TRACK_RECORDER 0x0712 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_SYNTHESIZER 0x0713 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_PIANO 0x0714 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_GUITAR 0x0715 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_DRUMS_RHYTHM 0x0716 +#define UX_DEVICE_CLASS_AUDIO_EMBEDDED_OTHER 0x0717 + + +/* Define Audio Class encoding format types. */ + +#define UX_DEVICE_CLASS_AUDIO_FORMAT_TYPE_UNDEFINED 0 +#define UX_DEVICE_CLASS_AUDIO_FORMAT_TYPE_I 1 +#define UX_DEVICE_CLASS_AUDIO_FORMAT_TYPE_II 2 +#define UX_DEVICE_CLASS_AUDIO_FORMAT_TYPE_III 3 +#define UX_DEVICE_CLASS_AUDIO_FORMAT_TYPE_IV 4 +#define UX_DEVICE_CLASS_AUDIO_EXT_FORMAT_TYPE_I 0x81 +#define UX_DEVICE_CLASS_AUDIO_EXT_FORMAT_TYPE_II 0x82 +#define UX_DEVICE_CLASS_AUDIO_EXT_FORMAT_TYPE_III 0x83 + + +/* Define channels. */ + +#define UX_DEVICE_CLASS_AUDIO_MASTER_CHANNEL 0 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_1 1 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_2 2 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_3 3 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_4 4 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_5 5 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_6 6 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_7 7 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_8 8 +#define UX_DEVICE_CLASS_AUDIO_CHANNEL_9 9 + + +/* Define IOCTL code. + ux_device_class_audio_ioctl(audio, IOCTL_CODE, parameter). + */ + +#define UX_DEVICE_CLASS_AUDIO_IOCTL_GET_ARG 1 + + +/* Define Audio Class callback structure. */ + +struct UX_DEVICE_CLASS_AUDIO_STREAM_STRUCT; +struct UX_DEVICE_CLASS_AUDIO_STRUCT; + +typedef struct UX_DEVICE_CLASS_AUDIO_CALLBACKS_STRUCT +{ + + VOID (*ux_slave_class_audio_instance_activate)(VOID *); + VOID (*ux_slave_class_audio_instance_deactivate)(VOID *); + UINT (*ux_device_class_audio_control_process)(struct UX_DEVICE_CLASS_AUDIO_STRUCT *, UX_SLAVE_TRANSFER *); + VOID *ux_device_class_audio_arg; +} UX_DEVICE_CLASS_AUDIO_CALLBACKS; + +typedef struct UX_DEVICE_CLASS_AUDIO_STREAM_CALLBACKS_STRUCT +{ + VOID (*ux_device_class_audio_stream_change)(struct UX_DEVICE_CLASS_AUDIO_STREAM_STRUCT *, ULONG); + VOID (*ux_device_class_audio_stream_frame_done)(struct UX_DEVICE_CLASS_AUDIO_STREAM_STRUCT *, ULONG); +} UX_DEVICE_CLASS_AUDIO_STREAM_CALLBACKS; + + +/* Define Audio Class Calling Parameter structure */ + +typedef struct UX_DEVICE_CLASS_AUDIO_STREAM_PARAMETER_STRUCT +{ + ULONG ux_device_class_audio_stream_parameter_thread_stack_size; + VOID (*ux_device_class_audio_stream_parameter_thread_entry)(ULONG id); +#if defined(UX_DEVICE_CLASS_AUDIO_FEEDBACK_SUPPORT) + ULONG ux_device_class_audio_stream_parameter_feedback_thread_stack_size; + VOID (*ux_device_class_audio_stream_parameter_feedback_thread_entry)(ULONG id); +#endif + UX_DEVICE_CLASS_AUDIO_STREAM_CALLBACKS ux_device_class_audio_stream_parameter_callbacks; + + ULONG ux_device_class_audio_stream_parameter_max_frame_buffer_size; + ULONG ux_device_class_audio_stream_parameter_max_frame_buffer_nb; +} UX_DEVICE_CLASS_AUDIO_STREAM_PARAMETER; + +typedef struct UX_DEVICE_CLASS_AUDIO_PARAMETER_STRUCT +{ + ULONG ux_device_class_audio_parameter_master_interface; + UX_DEVICE_CLASS_AUDIO_CALLBACKS ux_device_class_audio_parameter_callbacks; + + ULONG ux_device_class_audio_parameter_streams_nb; + UX_DEVICE_CLASS_AUDIO_STREAM_PARAMETER *ux_device_class_audio_parameter_streams; +} UX_DEVICE_CLASS_AUDIO_PARAMETER; + + +/* Define Audio Class instance structure. */ + +typedef struct UX_DEVICE_CLASS_AUDIO_FRAME_STRUCT +{ + + ULONG ux_device_class_audio_frame_length; + ULONG ux_device_class_audio_frame_pos; + UCHAR ux_device_class_audio_frame_data[4]; +} UX_DEVICE_CLASS_AUDIO_FRAME; + +typedef struct UX_DEVICE_CLASS_AUDIO_STREAM_STRUCT +{ + + struct UX_DEVICE_CLASS_AUDIO_STRUCT *ux_device_class_audio_stream_audio; + UX_SLAVE_INTERFACE *ux_device_class_audio_stream_interface; + UX_SLAVE_ENDPOINT *ux_device_class_audio_stream_endpoint; + +#if defined(UX_DEVICE_CLASS_AUDIO_FEEDBACK_SUPPORT) + UX_SLAVE_ENDPOINT *ux_device_class_audio_stream_feedback; + + UCHAR *ux_device_class_audio_stream_feedback_thread_stack; + UX_THREAD ux_device_class_audio_stream_feedback_thread; +#endif + + UX_DEVICE_CLASS_AUDIO_STREAM_CALLBACKS ux_device_class_audio_stream_callbacks; + + UCHAR *ux_device_class_audio_stream_thread_stack; + UX_THREAD ux_device_class_audio_stream_thread; + + UCHAR *ux_device_class_audio_stream_buffer; + ULONG ux_device_class_audio_stream_buffer_size; + ULONG ux_device_class_audio_stream_frame_buffer_size; + + UX_DEVICE_CLASS_AUDIO_FRAME *ux_device_class_audio_stream_transfer_pos; + UX_DEVICE_CLASS_AUDIO_FRAME *ux_device_class_audio_stream_access_pos; +} UX_DEVICE_CLASS_AUDIO_STREAM; + +typedef struct UX_DEVICE_CLASS_AUDIO_STRUCT +{ + + UX_SLAVE_CLASS *ux_device_class_audio_class; + UX_SLAVE_DEVICE *ux_device_class_audio_device; + UX_SLAVE_INTERFACE *ux_device_class_audio_interface; + + UX_DEVICE_CLASS_AUDIO_CALLBACKS ux_device_class_audio_callbacks; + + ULONG ux_device_class_audio_streams_nb; + UX_DEVICE_CLASS_AUDIO_STREAM *ux_device_class_audio_streams; +} UX_DEVICE_CLASS_AUDIO; + + +/* Define Audio Class function prototypes. */ + +UINT _ux_device_class_audio_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_audio_uninitialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_audio_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_audio_change(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_audio_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_audio_control_request(UX_SLAVE_CLASS_COMMAND *command); + +UINT _ux_device_class_audio_entry(UX_SLAVE_CLASS_COMMAND *command); + +UINT _ux_device_class_audio_ioctl(UX_DEVICE_CLASS_AUDIO *audio, ULONG ioctl_function, + VOID *parameter); + +UINT _ux_device_class_audio_stream_get(UX_DEVICE_CLASS_AUDIO *audio, ULONG stream_index, UX_DEVICE_CLASS_AUDIO_STREAM **stream); + +VOID _ux_device_class_audio_write_thread_entry(ULONG audio_stream); +VOID _ux_device_class_audio_read_thread_entry(ULONG audio_stream); + +UINT _ux_device_class_audio_reception_start(UX_DEVICE_CLASS_AUDIO_STREAM *audio); +UINT _ux_device_class_audio_sample_read8(UX_DEVICE_CLASS_AUDIO_STREAM *audio, UCHAR *sample); +UINT _ux_device_class_audio_sample_read16(UX_DEVICE_CLASS_AUDIO_STREAM *audio, USHORT *sample); +UINT _ux_device_class_audio_sample_read24(UX_DEVICE_CLASS_AUDIO_STREAM *audio, ULONG *sample); +UINT _ux_device_class_audio_sample_read32(UX_DEVICE_CLASS_AUDIO_STREAM *audio, ULONG *sample); + +UINT _ux_device_class_audio_read_frame_get(UX_DEVICE_CLASS_AUDIO_STREAM *audio, UCHAR **frame_data, ULONG *frame_length); +UINT _ux_device_class_audio_read_frame_free(UX_DEVICE_CLASS_AUDIO_STREAM *audio); + +UINT _ux_device_class_audio_transmission_start(UX_DEVICE_CLASS_AUDIO_STREAM *audio); +UINT _ux_device_class_audio_frame_write(UX_DEVICE_CLASS_AUDIO_STREAM *audio, UCHAR *frame, ULONG length); + +UINT _ux_device_class_audio_write_frame_get(UX_DEVICE_CLASS_AUDIO_STREAM *audio, UCHAR **buffer, ULONG *max_length); +UINT _ux_device_class_audio_write_frame_commit(UX_DEVICE_CLASS_AUDIO_STREAM *audio, ULONG length); + +VOID _ux_device_class_audio_feedback_thread_entry(ULONG audio_stream); +UINT _ux_device_class_audio_feedback_set(UX_DEVICE_CLASS_AUDIO_STREAM *audio, UCHAR *encoded_feedback); +UINT _ux_device_class_audio_feedback_get(UX_DEVICE_CLASS_AUDIO_STREAM *audio, UCHAR *encoded_feedback); +ULONG _ux_device_class_audio_speed_get(UX_DEVICE_CLASS_AUDIO_STREAM *audio); + + +/* Define Device Class Audio API prototypes. */ + +#define ux_device_class_audio_entry _ux_device_class_audio_entry + +#define ux_device_class_audio_read_thread_entry _ux_device_class_audio_read_thread_entry +#define ux_device_class_audio_write_thread_entry _ux_device_class_audio_write_thread_entry + +#define ux_device_class_audio_stream_get _ux_device_class_audio_stream_get + +#define ux_device_class_audio_reception_start _ux_device_class_audio_reception_start +#define ux_device_class_audio_sample_read8 _ux_device_class_audio_sample_read8 +#define ux_device_class_audio_sample_read16 _ux_device_class_audio_sample_read16 +#define ux_device_class_audio_sample_read24 _ux_device_class_audio_sample_read24 +#define ux_device_class_audio_sample_read32 _ux_device_class_audio_sample_read32 + +#define ux_device_class_audio_read_frame_get _ux_device_class_audio_read_frame_get +#define ux_device_class_audio_read_frame_free _ux_device_class_audio_read_frame_free + +#define ux_device_class_audio_transmission_start _ux_device_class_audio_transmission_start +#define ux_device_class_audio_frame_write _ux_device_class_audio_frame_write + +#define ux_device_class_audio_write_frame_get _ux_device_class_audio_write_frame_get +#define ux_device_class_audio_write_frame_commit _ux_device_class_audio_write_frame_commit + +#define ux_device_class_audio_ioctl _ux_device_class_audio_ioctl + +#define ux_device_class_audio_speed_get _ux_device_class_audio_speed_get +#define ux_device_class_audio_feedback_thread_entry _ux_device_class_audio_feedback_thread_entry +#define ux_device_class_audio_feedback_get _ux_device_class_audio_feedback_get +#define ux_device_class_audio_feedback_set _ux_device_class_audio_feedback_set + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef UX_DEVICE_CLASS_AUDIO_H */ diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio10.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio10.h new file mode 100644 index 00000000..2c84b99d --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio10.h @@ -0,0 +1,386 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Audio Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_audio10.h PORTABLE C */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX audio class version 1.0. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added volume RES support, */ +/* resulting in version 6.1.6 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_AUDIO10_H +#define UX_DEVICE_CLASS_AUDIO10_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define Audio Class specific AC interface descriptor subclasses. */ + +#define UX_DEVICE_CLASS_AUDIO10_AC_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO10_AC_HEADER 0x01 +#define UX_DEVICE_CLASS_AUDIO10_AC_INPUT_TERMINAL 0x02 +#define UX_DEVICE_CLASS_AUDIO10_AC_OUTPUT_TERMINAL 0x03 +#define UX_DEVICE_CLASS_AUDIO10_AC_MIXER_UNIT 0x04 +#define UX_DEVICE_CLASS_AUDIO10_AC_SELECTOR_UNIT 0x05 +#define UX_DEVICE_CLASS_AUDIO10_AC_FEATURE_UNIT 0x06 +#define UX_DEVICE_CLASS_AUDIO10_AC_PROCESSING_UNIT 0x07 +#define UX_DEVICE_CLASS_AUDIO10_AC_EXTENSION_UNIT 0x08 + + +/* Define Audio Class specific AS interface descriptor subclasses. */ + +#define UX_DEVICE_CLASS_AUDIO10_AS_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO10_AS_GENERAL 0x01 +#define UX_DEVICE_CLASS_AUDIO10_AS_FORMAT_TYPE 0x02 +#define UX_DEVICE_CLASS_AUDIO10_AS_FORMAT_SPECIFIC 0x03 + + +/* Define Audio Class specific endpoint descriptor subtypes. */ + +#define UX_DEVICE_CLASS_AUDIO10_EP_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO10_EP_GENERAL 0x01 + + +/* Define Audio Class specific request codes. */ + +#define UX_DEVICE_CLASS_AUDIO10_REQUEST_CODE_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO10_SET_CUR 0x01 +#define UX_DEVICE_CLASS_AUDIO10_GET_CUR 0x81 +#define UX_DEVICE_CLASS_AUDIO10_SET_MIN 0x02 +#define UX_DEVICE_CLASS_AUDIO10_GET_MIN 0x82 +#define UX_DEVICE_CLASS_AUDIO10_SET_MAX 0x03 +#define UX_DEVICE_CLASS_AUDIO10_GET_MAX 0x83 +#define UX_DEVICE_CLASS_AUDIO10_SET_RES 0x04 +#define UX_DEVICE_CLASS_AUDIO10_GET_RES 0x84 +#define UX_DEVICE_CLASS_AUDIO10_SET_MEM 0x05 +#define UX_DEVICE_CLASS_AUDIO10_GET_MEM 0x85 +#define UX_DEVICE_CLASS_AUDIO10_GET_STAT 0xFF + + +/* Define Audio Class specific terminal control selectors. */ + +#define UX_DEVICE_CLASS_AUDIO10_TE_CONTROL_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO10_TE_COPY_PROTECT_CONTROL 0x01 + + +/* Define Audio Class specific feature unit control selectors. */ + +#define UX_DEVICE_CLASS_AUDIO10_FU_CONTROL_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO10_FU_MUTE_CONTROL 0x01 +#define UX_DEVICE_CLASS_AUDIO10_FU_VOLUME_CONTROL 0x02 +#define UX_DEVICE_CLASS_AUDIO10_FU_BASS_CONTROL 0x03 +#define UX_DEVICE_CLASS_AUDIO10_FU_MID_CONTROL 0x04 +#define UX_DEVICE_CLASS_AUDIO10_FU_TREBLE_CONTROL 0x05 +#define UX_DEVICE_CLASS_AUDIO10_FU_GRAPHIC_EQUALIZER_CONTROL 0x06 +#define UX_DEVICE_CLASS_AUDIO10_FU_AUTOMATIC_GAIN_CONTROL 0x07 +#define UX_DEVICE_CLASS_AUDIO10_FU_DELAY_CONTROL 0x08 +#define UX_DEVICE_CLASS_AUDIO10_FU_BASS_BOOST_CONTROL 0x09 +#define UX_DEVICE_CLASS_AUDIO10_FU_LOUNDNESS_CONTROL 0x0A + + +/* Define Audio Class encoding format types. */ + +#define UX_DEVICE_CLASS_AUDIO10_FORMAT_PCM 1 +#define UX_DEVICE_CLASS_AUDIO10_FORMAT_PCM8 2 +#define UX_DEVICE_CLASS_AUDIO10_FORMAT_IEEE_FLOAT 3 +#define UX_DEVICE_CLASS_AUDIO10_FORMAT_ALAW 4 +#define UX_DEVICE_CLASS_AUDIO10_FORMAT_MULAW 5 + + +/* Audio Class Control interface structures. */ + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_HEADER1_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bcdADC; + ULONG wTotalLength; + ULONG bInCollection; + ULONG baInterfaceNr1; +} UX_DEVICE_CLASS_AUDIO10_AC_HEADER1_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_HEADER2_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bcdADC; + ULONG wTotalLength; + ULONG bInCollection; + ULONG baInterfaceNr1; + ULONG baInterfaceNr2; +} UX_DEVICE_CLASS_AUDIO10_AC_HEADER2_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_HEADER3_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bcdADC; + ULONG wTotalLength; + ULONG bInCollection; + ULONG baInterfaceNr1; + ULONG baInterfaceNr2; + ULONG baInterfaceNr3; +} UX_DEVICE_CLASS_AUDIO10_AC_HEADER3_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_HEADER6_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bcdADC; + ULONG wTotalLength; + ULONG bInCollection; + ULONG baInterfaceNr1; + ULONG baInterfaceNr2; + ULONG baInterfaceNr3; + ULONG baInterfaceNr4; + ULONG baInterfaceNr5; + ULONG baInterfaceNr6; +} UX_DEVICE_CLASS_AUDIO10_AC_HEADER6_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_HEADER7_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bcdADC; + ULONG wTotalLength; + ULONG bInCollection; + ULONG baInterfaceNr1; + ULONG baInterfaceNr2; + ULONG baInterfaceNr3; + ULONG baInterfaceNr4; + ULONG baInterfaceNr5; + ULONG baInterfaceNr6; + ULONG baInterfaceNr7; +} UX_DEVICE_CLASS_AUDIO10_AC_HEADER7_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_HEADER8_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bcdADC; + ULONG wTotalLength; + ULONG bInCollection; + ULONG baInterfaceNr1; + ULONG baInterfaceNr2; + ULONG baInterfaceNr3; + ULONG baInterfaceNr4; + ULONG baInterfaceNr5; + ULONG baInterfaceNr6; + ULONG baInterfaceNr7; + ULONG baInterfaceNr8; +} UX_DEVICE_CLASS_AUDIO10_AC_HEADER8_DESCRIPTOR; + + +/* Define Audio Class specific input terminal interface descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_INPUT_TERMINAL_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bTerminalID; + ULONG wTerminalType; + ULONG bAssocTerminal; + ULONG bNrChannels; + ULONG wChannelConfig; + ULONG iChannelNames; + ULONG iTerminal; +} UX_DEVICE_CLASS_AUDIO10_AC_INPUT_TERMINAL_DESCRIPTOR; + + +/* Define Audio Class specific output terminal interface descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_OUTPUT_TERMINAL_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bTerminalID; + ULONG wTerminalType; + ULONG bAssocTerminal; + ULONG bSourceID; + ULONG iTerminal; +} UX_DEVICE_CLASS_AUDIO10_AC_OUTPUT_TERMINAL_DESCRIPTOR; + + +/* Define Audio Class specific feature unit descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO10_AC_FEATURE_UNIT_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bUnitID; + ULONG bSourceID; + ULONG bControlSize; + ULONG bmaControls; +} UX_DEVICE_CLASS_AUDIO10_AC_FEATURE_UNIT_DESCRIPTOR; + + +/* Define Audio Class streaming interface descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO10_AS_INTERFACE_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bTerminalLink; + ULONG bDelay; + ULONG wFormatTag; +} UX_DEVICE_CLASS_AUDIO10_AS_INTERFACE_DESCRIPTOR; + + +/* Define Audio Class type I format type descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO10_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bFormatType; + ULONG bNrChannels; + ULONG bSubframeSize; + ULONG bBitResolution; + ULONG bSamFreqType; + ULONG SamplingFrequency; +} UX_DEVICE_CLASS_AUDIO10_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR; + +#define UX_DEVICE_CLASS_AUDIO_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR_FORMAT_TYPE 3 +#define UX_DEVICE_CLASS_AUDIO_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR_NR_CHANNELS 4 +#define UX_DEVICE_CLASS_AUDIO_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR_SUBFRAME_SIZE 5 +#define UX_DEVICE_CLASS_AUDIO_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR_BIT_RESOLUTION 6 +#define UX_DEVICE_CLASS_AUDIO_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR_SAM_FREQ_TYPE 7 +#define UX_DEVICE_CLASS_AUDIO_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR_SAM_FREQ_TABLE 8 + + +/* Define Audio Class specific streaming endpoint descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO10_AS_ENDPOINT_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bmAttributes; + ULONG wMaxPacketSize; + ULONG bInterval; + ULONG bRefresh; + ULONG bSynchAddress; +} UX_DEVICE_CLASS_AUDIO10_AS_ENDPOINT_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO10_AS_DATA_ENDPOINT_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bmAttributes; + ULONG bLockDelayUnits; + ULONG wLockDelay; +} UX_DEVICE_CLASS_AUDIO10_AS_DATA_ENDPOINT_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO10_CONTROL_STRUCT +{ + ULONG ux_device_class_audio10_control_fu_id; + + ULONG ux_device_class_audio10_control_changed; + + USHORT ux_device_class_audio10_control_mute[1]; + SHORT ux_device_class_audio10_control_volume_min[1]; + SHORT ux_device_class_audio10_control_volume_max[1]; + USHORT ux_device_class_audio10_control_volume_res[1]; + SHORT ux_device_class_audio10_control_volume[1]; +} UX_DEVICE_CLASS_AUDIO10_CONTROL; + +#define UX_DEVICE_CLASS_AUDIO10_CONTROL_MUTE_CHANGED 1 +#define UX_DEVICE_CLASS_AUDIO10_CONTROL_VOLUME_CHANGED 2 + +typedef struct UX_DEVICE_CLASS_AUDIO10_CONTROL_GROUP_STRUCT +{ + ULONG ux_device_class_audio10_control_group_controls_nb; + UX_DEVICE_CLASS_AUDIO10_CONTROL *ux_device_class_audio10_control_group_controls; +} UX_DEVICE_CLASS_AUDIO10_CONTROL_GROUP; + +UINT _ux_device_class_audio10_control_process(UX_DEVICE_CLASS_AUDIO *audio, + UX_SLAVE_TRANSFER *transfer_request, + UX_DEVICE_CLASS_AUDIO10_CONTROL_GROUP *group); + +#define ux_device_class_audio10_control_process _ux_device_class_audio10_control_process + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef UX_DEVICE_CLASS_AUDIO10_H */ diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio20.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio20.h new file mode 100644 index 00000000..00250fc2 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_audio20.h @@ -0,0 +1,444 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Audio Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_audio20.h PORTABLE C */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX audio class version 2.0. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added volume RES support, */ +/* resulting in version 6.1.6 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_AUDIO20_H +#define UX_DEVICE_CLASS_AUDIO20_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define Audio Class function category codes. */ + +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_DESKTOP_SPEAKER 0x01 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_HOME_THEATER 0x02 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_MICROPHONE 0x03 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_HEADSET 0x04 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_TELEPHONE 0x05 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_CONVERTER 0x06 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_VOICE_SOUND_RECORDER 0x07 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_I_O_BOX 0x08 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_MUSICAL_INSTRUMENT 0x09 +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_PRO_AUDIO 0x0A +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_AUDIO_VIDEO 0x0B +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_CONTROL_PANEL 0x0C +#define UX_DEVICE_CLASS_AUDIO20_CATEGORY_OTHER 0xFF + + +/* Define Audio Class specific AC interface descriptor subclasses. */ + +#define UX_DEVICE_CLASS_AUDIO20_AC_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_AC_HEADER 0x01 +#define UX_DEVICE_CLASS_AUDIO20_AC_INPUT_TERMINAL 0x02 +#define UX_DEVICE_CLASS_AUDIO20_AC_OUTPUT_TERMINAL 0x03 +#define UX_DEVICE_CLASS_AUDIO20_AC_MIXER_UNIT 0x04 +#define UX_DEVICE_CLASS_AUDIO20_AC_SELECTOR_UNIT 0x05 +#define UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT 0x06 +#define UX_DEVICE_CLASS_AUDIO20_AC_EFFECT_UNIT 0x07 +#define UX_DEVICE_CLASS_AUDIO20_AC_PROCESSING_UNIT 0x08 +#define UX_DEVICE_CLASS_AUDIO20_AC_EXTENSION_UNIT 0x09 +#define UX_DEVICE_CLASS_AUDIO20_AC_CLOCK_SOURCE 0x0A +#define UX_DEVICE_CLASS_AUDIO20_AC_CLOCK_SELECTOR 0x0B +#define UX_DEVICE_CLASS_AUDIO20_AC_CLOCK_MULTIPLIER 0x0C +#define UX_DEVICE_CLASS_AUDIO20_AC_SAMPLE_RATE_CONVERTER 0x0D + + +/* Define Audio Class specific AS interface descriptor subclasses. */ + +#define UX_DEVICE_CLASS_AUDIO20_AS_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_AS_GENERAL 0x01 +#define UX_DEVICE_CLASS_AUDIO20_AS_FORMAT_TYPE 0x02 +#define UX_DEVICE_CLASS_AUDIO20_AS_ENCODER 0x03 +#define UX_DEVICE_CLASS_AUDIO20_AS_DECODER 0x04 + + +/* Define Audio Class specific endpoint descriptor subtypes. */ + +#define UX_DEVICE_CLASS_AUDIO20_EP_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_EP_GENERAL 0x01 + + +/* Define Audio Class specific request codes. */ + +#define UX_DEVICE_CLASS_AUDIO20_REQUEST_CODE_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_CUR 0x01 +#define UX_DEVICE_CLASS_AUDIO20_RANGE 0x02 +#define UX_DEVICE_CLASS_AUDIO20_MEM 0x03 + + +/* Define Audio Class specific clock source control selectors. */ + +#define UX_DEVICE_CLASS_AUDIO20_CS_CONTROL_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_CS_SAM_FREQ_CONTROL 0x01 +#define UX_DEVICE_CLASS_AUDIO20_CS_CLOCK_VALID_CONTROL 0x02 + + +/* Define Audio Class specific clock selector control selectors. */ + + +#define UX_DEVICE_CLASS_AUDIO20_CX_CONTROL_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_CX_CLOCK_SELECTOR_CONTROL 0x01 + +/* Define Audio Class specific terminal control selectors. */ + +#define UX_DEVICE_CLASS_AUDIO20_TE_CONTROL_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_TE_COPY_PROTECT_CONTROL 0x01 +#define UX_DEVICE_CLASS_AUDIO20_TE_CONNECTOR_CONTROL 0x02 +#define UX_DEVICE_CLASS_AUDIO20_TE_OVERLOAD_CONTROL 0x03 +#define UX_DEVICE_CLASS_AUDIO20_TE_CLUSTER_CONTROL 0x04 +#define UX_DEVICE_CLASS_AUDIO20_TE_UNDERFLOW_CONTROL 0x05 +#define UX_DEVICE_CLASS_AUDIO20_TE_OVERFLOW_CONTROL 0x06 +#define UX_DEVICE_CLASS_AUDIO20_TE_LATENCY_CONTROL 0x07 + + +/* Define Audio Class specific feature unit control selectors. */ + +#define UX_DEVICE_CLASS_AUDIO20_FU_CONTROL_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_AUDIO20_FU_MUTE_CONTROL 0x01 +#define UX_DEVICE_CLASS_AUDIO20_FU_VOLUME_CONTROL 0x02 +#define UX_DEVICE_CLASS_AUDIO20_FU_BASS_CONTROL 0x03 +#define UX_DEVICE_CLASS_AUDIO20_FU_MID_CONTROL 0x04 +#define UX_DEVICE_CLASS_AUDIO20_FU_TREBLE_CONTROL 0x05 +#define UX_DEVICE_CLASS_AUDIO20_FU_GRAPHIC_EQUALIZER_CONTROL 0x06 +#define UX_DEVICE_CLASS_AUDIO20_FU_AUTOMATIC_GAIN_CONTROL 0x07 +#define UX_DEVICE_CLASS_AUDIO20_FU_DELAY_CONTROL 0x08 +#define UX_DEVICE_CLASS_AUDIO20_FU_BASS_BOOST_CONTROL 0x09 +#define UX_DEVICE_CLASS_AUDIO20_FU_LOUNDNESS_CONTROL 0x0A +#define UX_DEVICE_CLASS_AUDIO20_FU_INPUT_GAIN_CONTROL 0x0B +#define UX_DEVICE_CLASS_AUDIO20_FU_INPUT_GAIN_PAD_CONTROL 0x0C +#define UX_DEVICE_CLASS_AUDIO20_FU_PHASE_INVERTER_CONTROL 0x0D +#define UX_DEVICE_CLASS_AUDIO20_FU_UNDERFLOW_CONTROL 0x0E +#define UX_DEVICE_CLASS_AUDIO20_FU_OVERFLOW_CONTROL 0x0F +#define UX_DEVICE_CLASS_AUDIO20_FU_LATENCY_CONTROL 0x10 + + +/* Define Audio Class encoding format type bit allocations. */ + +#define UX_DEVICE_CLASS_AUDIO20_FORMAT_PCM (1u << 0) +#define UX_DEVICE_CLASS_AUDIO20_FORMAT_PCM8 (1u << 1) +#define UX_DEVICE_CLASS_AUDIO20_FORMAT_IEEE_FLOAT (1u << 2) +#define UX_DEVICE_CLASS_AUDIO20_FORMAT_ALAW (1u << 3) +#define UX_DEVICE_CLASS_AUDIO20_FORMAT_MULAW (1u << 4) +#define UX_DEVICE_CLASS_AUDIO20_FORMAT_RAW (1u << 31) + + +/* Audio Class Control header descriptor structures. */ + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_HEADER_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bcdADC; + ULONG bCategory; + ULONG wTotalLength; + ULONG bmControls; +} UX_DEVICE_CLASS_AUDIO20_AC_HEADER_DESCRIPTOR; + + +/* Define Audio Class specific clock source descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_CLOCK_SOURCE_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bClockID; + ULONG bmAttributes; + ULONG bmControls; + ULONG bAssocTerminal; + ULONG iClockSource; +} UX_DEVICE_CLASS_AUDIO20_AC_CLOCK_SOURCE_DESCRIPTOR; + + +/* Define Audio Class specific input terminal interface descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_INPUT_TERMINAL_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bTerminalID; + ULONG wTerminalType; + ULONG bAssocTerminal; + ULONG bCSourceID; + ULONG bNrChannels; + ULONG bmChannelConfig; + ULONG iChannelNames; + ULONG bmControls; + ULONG iTerminal; +} UX_DEVICE_CLASS_AUDIO20_AC_INPUT_TERMINAL_DESCRIPTOR; + + +/* Define Audio Class specific output terminal interface descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_OUTPUT_TERMINAL_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bTerminalID; + ULONG wTerminalType; + ULONG bAssocTerminal; + ULONG bSourceID; + ULONG bCSourceID; + ULONG bmControls; + ULONG iTerminal; +} UX_DEVICE_CLASS_AUDIO20_AC_OUTPUT_TERMINAL_DESCRIPTOR; + + +/* Define Audio Class specific feature unit descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bUnitID; + ULONG bSourceID; + ULONG bmaControls; +} UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT1_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bUnitID; + ULONG bSourceID; + ULONG bmaControls0; + ULONG bmaControls1; +} UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT1_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT2_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bUnitID; + ULONG bSourceID; + ULONG bmaControls0; + ULONG bmaControls1; + ULONG bmaControls2; +} UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT2_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT3_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bUnitID; + ULONG bSourceID; + ULONG bmaControls0; + ULONG bmaControls1; + ULONG bmaControls2; + ULONG bmaControls3; +} UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT3_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT6_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bUnitID; + ULONG bSourceID; + ULONG bmaControls0; + ULONG bmaControls1; + ULONG bmaControls2; + ULONG bmaControls3; + ULONG bmaControls4; + ULONG bmaControls5; + ULONG bmaControls6; +} UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT6_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT7_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bUnitID; + ULONG bSourceID; + ULONG bmaControls0; + ULONG bmaControls1; + ULONG bmaControls2; + ULONG bmaControls3; + ULONG bmaControls4; + ULONG bmaControls5; + ULONG bmaControls6; + ULONG bmaControls7; +} UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT7_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT8_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubType; + ULONG bUnitID; + ULONG bSourceID; + ULONG bmaControls0; + ULONG bmaControls1; + ULONG bmaControls2; + ULONG bmaControls3; + ULONG bmaControls4; + ULONG bmaControls5; + ULONG bmaControls6; + ULONG bmaControls7; + ULONG bmaControls8; +} UX_DEVICE_CLASS_AUDIO20_AC_FEATURE_UNIT8_DESCRIPTOR; + + +/* Define Audio Class streaming interface descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO20_AS_INTERFACE_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bTerminalLink; + ULONG bmControls; + ULONG bFormatType; + ULONG bmFormats; + ULONG bNrChannels; + ULONG bmChannelConfig; + ULONG iChannelNames; +} UX_DEVICE_CLASS_AUDIO20_AS_INTERFACE_DESCRIPTOR; + + +/* Define Audio Class type I format type descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO20_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bFormatType; + ULONG bSubslotSize; + ULONG bBitResolution; +} UX_DEVICE_CLASS_AUDIO20_AS_TYPE_I_FORMAT_TYPE_DESCRIPTOR; + + +/* Define Audio Class specific streaming endpoint descriptor. */ + +typedef struct UX_DEVICE_CLASS_AUDIO20_AS_DATA_ENDPOINT_DESCRIPTOR_STRUCT +{ + + ULONG bLength; + ULONG bDescriptorType; + ULONG bDescriptorSubtype; + ULONG bmAttributes; + ULONG bmControls; + ULONG bLockDelayUnits; + ULONG wLockDelay; +} UX_DEVICE_CLASS_AUDIO20_AS_DATA_ENDPOINT_DESCRIPTOR; + +typedef struct UX_DEVICE_CLASS_AUDIO20_CONTROL_STRUCT +{ + ULONG ux_device_class_audio20_control_cs_id; + ULONG ux_device_class_audio20_control_fu_id; + ULONG ux_device_class_audio20_control_sampling_frequency; + + ULONG ux_device_class_audio20_control_changed; + + USHORT ux_device_class_audio20_control_mute[1]; + SHORT ux_device_class_audio20_control_volume_min[1]; + SHORT ux_device_class_audio20_control_volume_max[1]; + USHORT ux_device_class_audio20_control_volume_res[1]; + SHORT ux_device_class_audio20_control_volume[1]; +} UX_DEVICE_CLASS_AUDIO20_CONTROL; + +#define UX_DEVICE_CLASS_AUDIO20_CONTROL_MUTE_CHANGED 1 +#define UX_DEVICE_CLASS_AUDIO20_CONTROL_VOLUME_CHANGED 2 + +typedef struct UX_DEVICE_CLASS_AUDIO20_CONTROL_GROUP_STRUCT +{ + ULONG ux_device_class_audio20_control_group_controls_nb; + UX_DEVICE_CLASS_AUDIO20_CONTROL *ux_device_class_audio20_control_group_controls; +} UX_DEVICE_CLASS_AUDIO20_CONTROL_GROUP; + + +UINT _ux_device_class_audio20_control_process(UX_DEVICE_CLASS_AUDIO *audio, + UX_SLAVE_TRANSFER *transfer, + UX_DEVICE_CLASS_AUDIO20_CONTROL_GROUP *group); + +#define ux_device_class_audio20_control_process _ux_device_class_audio20_control_process + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif /* ifndef UX_DEVICE_CLASS_AUDIO20_H */ diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_cdc_acm.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_cdc_acm.h new file mode 100644 index 00000000..2580f8f8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_cdc_acm.h @@ -0,0 +1,335 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** CDC Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_cdc_acm.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the equivalences for the USBX Device Class CDC */ +/* ACM component. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added macro to disable */ +/* transmission support, */ +/* resulting in version 6.1.6 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_CDC_ACM_H +#define UX_DEVICE_CLASS_CDC_ACM_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define CDC Class USB Class constants. */ +#define UX_SLAVE_CLASS_CDC_ACM_CLASS 10 + +/* Device CDC Requests */ +#define UX_SLAVE_CLASS_CDC_ACM_SEND_ENCAPSULATED_COMMAND 0x00 +#define UX_SLAVE_CLASS_CDC_ACM_GET_ENCAPSULATED_RESPONSE 0x01 +#define UX_SLAVE_CLASS_CDC_ACM_SET_COMM_FEATURE 0x02 +#define UX_SLAVE_CLASS_CDC_ACM_GET_COMM_FEATURE 0x03 +#define UX_SLAVE_CLASS_CDC_ACM_CLEAR_COMM_FEATURE 0x04 +#define UX_SLAVE_CLASS_CDC_ACM_SET_AUX_LINE_STATE 0x10 +#define UX_SLAVE_CLASS_CDC_ACM_SET_HOOK_STATE 0x11 +#define UX_SLAVE_CLASS_CDC_ACM_PULSE_SETUP 0x12 +#define UX_SLAVE_CLASS_CDC_ACM_SEND_PULSE 0x13 +#define UX_SLAVE_CLASS_CDC_ACM_SET_PULSE_TIME 0x14 +#define UX_SLAVE_CLASS_CDC_ACM_RING_AUX_JACK 0x15 +#define UX_SLAVE_CLASS_CDC_ACM_SET_LINE_CODING 0x20 +#define UX_SLAVE_CLASS_CDC_ACM_GET_LINE_CODING 0x21 +#define UX_SLAVE_CLASS_CDC_ACM_SET_CONTROL_LINE_STATE 0x22 +#define UX_SLAVE_CLASS_CDC_ACM_SEND_BREAK 0x23 +#define UX_SLAVE_CLASS_CDC_ACM_SET_RINGER_PARMS 0x30 +#define UX_SLAVE_CLASS_CDC_ACM_GET_RINGER_PARMS 0x31 +#define UX_SLAVE_CLASS_CDC_ACM_SET_OPERATION_PARMS 0x32 +#define UX_SLAVE_CLASS_CDC_ACM_GET_OPERATION_PARMS 0x33 +#define UX_SLAVE_CLASS_CDC_ACM_SET_LINE_PARMS 0x34 +#define UX_SLAVE_CLASS_CDC_ACM_GET_LINE_PARMS 0x35 +#define UX_SLAVE_CLASS_CDC_ACM_DIAL_DIGITS 0x36 +#define UX_SLAVE_CLASS_CDC_ACM_SET_UNIT_PARAMETER 0x37 +#define UX_SLAVE_CLASS_CDC_ACM_GET_UNIT_PARAMETER 0x38 +#define UX_SLAVE_CLASS_CDC_ACM_CLEAR_UNIT_PARAMETER 0x39 +#define UX_SLAVE_CLASS_CDC_ACM_GET_PROFILE 0x3A +#define UX_SLAVE_CLASS_CDC_ACM_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define UX_SLAVE_CLASS_CDC_ACM_SET_ETHERNET_POWER_MANAGEMENT_PATTERN 0x41 +#define UX_SLAVE_CLASS_CDC_ACM_GET_ETHERNET_POWER_MANAGEMENT_PATTERN 0x42 +#define UX_SLAVE_CLASS_CDC_ACM_SET_ETHERNET_PACKET_FILTER 0x43 +#define UX_SLAVE_CLASS_CDC_ACM_GET_ETHERNET_STATISTIC 0x44 +#define UX_SLAVE_CLASS_CDC_ACM_SET_ATM_DATA_FORMAT 0x50 +#define UX_SLAVE_CLASS_CDC_ACM_GET_ATM_DEVICE_STATISTICS 0x51 +#define UX_SLAVE_CLASS_CDC_ACM_SET_ATM_DEFAULT_VC 0x52 +#define UX_SLAVE_CLASS_CDC_ACM_GET_ATM_VC_STATISTICS 0x53 + +/* Default line coding values. */ +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_BAUDRATE 115200 +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_STOP_BIT 1 +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_PARITY 0 +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_DATA_BIT 8 + +/* Define line coding structure. */ +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_BAUDRATE_STRUCT 0 +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_STOP_BIT_STRUCT 4 +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_PARITY_STRUCT 5 +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_DATA_BIT_STRUCT 6 +#define UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_RESPONSE_SIZE 7 + +/* Define line state bits. */ +#define UX_SLAVE_CLASS_CDC_ACM_LINE_STATE_DTR 1 +#define UX_SLAVE_CLASS_CDC_ACM_LINE_STATE_RTS 2 + +/* Define Transfer direction bits. */ +#define UX_SLAVE_CLASS_CDC_ACM_ENDPOINT_XMIT 1 +#define UX_SLAVE_CLASS_CDC_ACM_ENDPOINT_RCV 2 + +/* Define IOCTL functions. */ +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_SET_LINE_CODING 1 +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_GET_LINE_CODING 2 +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_GET_LINE_STATE 3 +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_ABORT_PIPE 4 +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_SET_LINE_STATE 5 +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_TRANSMISSION_START 6 +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_TRANSMISSION_STOP 7 +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_SET_READ_TIMEOUT 8 +#define UX_SLAVE_CLASS_CDC_ACM_IOCTL_SET_WRITE_TIMEOUT 9 + +/* Define event group flag. */ +#define UX_DEVICE_CLASS_CDC_ACM_WRITE_EVENT 1 + + +/* CDC ACM read state machine states. */ +#define UX_DEVICE_CLASS_CDC_ACM_READ_START (UX_STATE_STEP + 1) +#define UX_DEVICE_CLASS_CDC_ACM_READ_WAIT (UX_STATE_STEP + 2) + +/* CDC ACM write state machine states. */ +#define UX_DEVICE_CLASS_CDC_ACM_WRITE_START (UX_STATE_STEP + 1) +#define UX_DEVICE_CLASS_CDC_ACM_WRITE_WAIT (UX_STATE_STEP + 2) + + +/* Define Slave CDC Class Calling Parameter structure */ + +typedef struct UX_SLAVE_CLASS_CDC_ACM_PARAMETER_STRUCT +{ + VOID (*ux_slave_class_cdc_acm_instance_activate)(VOID *); + VOID (*ux_slave_class_cdc_acm_instance_deactivate)(VOID *); + VOID (*ux_slave_class_cdc_acm_parameter_change)(VOID *); + +} UX_SLAVE_CLASS_CDC_ACM_PARAMETER; + +/* Define CDC Class structure. */ + +typedef struct UX_SLAVE_CLASS_CDC_ACM_STRUCT +{ + UX_SLAVE_INTERFACE *ux_slave_class_cdc_acm_interface; + UX_SLAVE_CLASS_CDC_ACM_PARAMETER ux_slave_class_cdc_acm_parameter; + +#if !defined(UX_DEVICE_STANDALONE) + UX_MUTEX ux_slave_class_cdc_acm_endpoint_in_mutex; + UX_MUTEX ux_slave_class_cdc_acm_endpoint_out_mutex; +#else + UCHAR *ux_device_class_cdc_acm_read_buffer; + ULONG ux_device_class_cdc_acm_read_requested_length; + ULONG ux_device_class_cdc_acm_read_transfer_length; + ULONG ux_device_class_cdc_acm_read_actual_length; + UINT ux_device_class_cdc_acm_read_status; + UINT ux_device_class_cdc_acm_read_state; + + UCHAR *ux_device_class_cdc_acm_write_buffer; + ULONG ux_device_class_cdc_acm_write_transfer_length; + ULONG ux_device_class_cdc_acm_write_requested_length; + ULONG ux_device_class_cdc_acm_write_actual_length; + UINT ux_device_class_cdc_acm_write_status; + UINT ux_device_class_cdc_acm_write_state; +#endif + + ULONG ux_slave_class_cdc_acm_baudrate; + UCHAR ux_slave_class_cdc_acm_stop_bit; + UCHAR ux_slave_class_cdc_acm_parity; + UCHAR ux_slave_class_cdc_acm_data_bit; + UCHAR ux_slave_class_cdc_acm_data_dtr_state; + UCHAR ux_slave_class_cdc_acm_data_rts_state; + UCHAR reserved[3]; + +#ifndef UX_DEVICE_CLASS_CDC_ACM_TRANSMISSION_DISABLE +#if !defined(UX_DEVICE_STANDALONE) + UX_THREAD ux_slave_class_cdc_acm_bulkin_thread; + UX_THREAD ux_slave_class_cdc_acm_bulkout_thread; + UX_EVENT_FLAGS_GROUP ux_slave_class_cdc_acm_event_flags_group; + UCHAR *ux_slave_class_cdc_acm_bulkin_thread_stack; + UCHAR *ux_slave_class_cdc_acm_bulkout_thread_stack; +#endif + UINT (*ux_device_class_cdc_acm_write_callback)(struct UX_SLAVE_CLASS_CDC_ACM_STRUCT *cdc_acm, UINT status, ULONG length); + UINT (*ux_device_class_cdc_acm_read_callback)(struct UX_SLAVE_CLASS_CDC_ACM_STRUCT *cdc_acm, UINT status, UCHAR *data_pointer, ULONG length); + ULONG ux_slave_class_cdc_acm_transmission_status; + ULONG ux_slave_class_cdc_acm_scheduled_write; +#if !defined(UX_DEVICE_STANDALONE) + ULONG ux_slave_class_cdc_acm_callback_total_length; + UCHAR *ux_slave_class_cdc_acm_callback_data_pointer; + UCHAR *ux_slave_class_cdc_acm_callback_current_data_pointer; +#endif +#endif +} UX_SLAVE_CLASS_CDC_ACM; + +/* Define some CDC Class structures */ + +typedef struct UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_PARAMETER_STRUCT +{ + ULONG ux_slave_class_cdc_acm_parameter_baudrate; + UCHAR ux_slave_class_cdc_acm_parameter_stop_bit; + UCHAR ux_slave_class_cdc_acm_parameter_parity; + UCHAR ux_slave_class_cdc_acm_parameter_data_bit; + +} UX_SLAVE_CLASS_CDC_ACM_LINE_CODING_PARAMETER; + +typedef struct UX_SLAVE_CLASS_CDC_ACM_LINE_STATE_PARAMETER_STRUCT +{ + UCHAR ux_slave_class_cdc_acm_parameter_rts; + UCHAR ux_slave_class_cdc_acm_parameter_dtr; + +} UX_SLAVE_CLASS_CDC_ACM_LINE_STATE_PARAMETER; + +typedef struct UX_SLAVE_CLASS_CDC_ACM_CALLBACK_PARAMETER_STRUCT +{ + UINT (*ux_device_class_cdc_acm_parameter_write_callback)(struct UX_SLAVE_CLASS_CDC_ACM_STRUCT *cdc_acm, UINT status, ULONG length); + UINT (*ux_device_class_cdc_acm_parameter_read_callback)(struct UX_SLAVE_CLASS_CDC_ACM_STRUCT *cdc_acm, UINT status, UCHAR *data_pointer, ULONG length); + +} UX_SLAVE_CLASS_CDC_ACM_CALLBACK_PARAMETER; + + + +/* Requests - Ethernet Networking Control Model */ + +#define UX_SLAVE_CLASS_CDC_ACM_SEND_ENCAPSULATED_COMMAND 0x00 + /* Issues a command in the format of the supported control + protocol. The intent of this mechanism is to support + networking devices (e.g., host-based cable modems) + that require an additional vendor-defined interface for + media specific hardware configuration and + management. */ +#define UX_SLAVE_CLASS_CDC_ACM_GET_ENCAPSULATED_RESPONSE 0x01 + /* Requests a response in the format of the supported + control protocol. */ +#define UX_SLAVE_CLASS_CDC_ACM_SET_ETHERNET_MULTICAST_FILTERS 0x40 + /* As applications are loaded and unloaded on the host, + the networking transport will instruct the device's MAC + driver to change settings of the Networking device's + multicast filters. */ +#define UX_SLAVE_CLASS_CDC_ACM_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 0x41 + /* Some hosts are able to conserve energy and stay quiet + in a 'sleeping' state while not being used. USB + Networking devices may provide special pattern filtering + hardware that enables it to wake up the attached host + on demand when something is attempting to contact the + host (e.g., an incoming web browser connection). + Primitives are needed in management plane to negotiate + the setting of these special filters */ +#define UX_SLAVE_CLASS_CDC_ACM_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 0x42 + /* Retrieves the status of the above power management + pattern filter setting */ +#define UX_SLAVE_CLASS_CDC_ACM_SET_ETHERNET_PACKET_FILTER 0x43 + /* Sets device filter for running a network analyzer + application on the host machine */ +#define UX_SLAVE_CLASS_CDC_ACM_GET_ETHERNET_STATISTIC 0x44 + /* Retrieves Ethernet device statistics such as frames + transmitted, frames received, and bad frames received. */ + +/* Define buffer length for IN/OUT pipes. */ + +#define UX_SLAVE_CLASS_CDC_ACM_BUFFER_SIZE 4096 + + +/* Define Device CDC Class prototypes. */ + +UINT _ux_device_class_cdc_acm_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_acm_control_request(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_acm_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_acm_entry(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_acm_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_acm_uninitialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_acm_write(UX_SLAVE_CLASS_CDC_ACM *cdc_acm, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_device_class_cdc_acm_read(UX_SLAVE_CLASS_CDC_ACM *cdc_acm, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_device_class_cdc_acm_ioctl(UX_SLAVE_CLASS_CDC_ACM *cdc_acm, ULONG ioctl_function, + VOID *parameter); +VOID _ux_device_class_cdc_acm_bulkin_thread(ULONG class_pointer); +VOID _ux_device_class_cdc_acm_bulkout_thread(ULONG class_pointer); +UINT _ux_device_class_cdc_acm_write_with_callback(UX_SLAVE_CLASS_CDC_ACM *cdc_acm, UCHAR *buffer, + ULONG requested_length); + +UINT _ux_device_class_cdc_acm_write_run(UX_SLAVE_CLASS_CDC_ACM *cdc_acm, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_device_class_cdc_acm_read_run(UX_SLAVE_CLASS_CDC_ACM *cdc_acm, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); + +UINT _ux_device_class_cdc_acm_tasks_run(VOID *instance); + +/* Define Device CDC Class API prototypes. */ + +#define ux_device_class_cdc_acm_entry _ux_device_class_cdc_acm_entry +#define ux_device_class_cdc_acm_read _ux_device_class_cdc_acm_read +#define ux_device_class_cdc_acm_write _ux_device_class_cdc_acm_write +#define ux_device_class_cdc_acm_ioctl _ux_device_class_cdc_acm_ioctl +#define ux_device_class_cdc_acm_write_with_callback _ux_device_class_cdc_acm_write_with_callback + +#define ux_device_class_cdc_acm_read_run _ux_device_class_cdc_acm_read_run +#define ux_device_class_cdc_acm_write_run _ux_device_class_cdc_acm_write_run + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif /* UX_DEVICE_CLASS_CDC_ACM_H */ diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_cdc_ecm.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_cdc_ecm.h new file mode 100644 index 00000000..722b0c03 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_cdc_ecm.h @@ -0,0 +1,363 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** CDC_ECM Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_cdc_ecm.h PORTABLE C */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the equivalences for the USBX Device Class */ +/* CDC_ECM component. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 08-02-2021 Wen Wang Modified comment(s), */ +/* fixed spelling error, */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_CDC_ECM_H +#define UX_DEVICE_CLASS_CDC_ECM_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + +#include "nx_api.h" +#include "ux_network_driver.h" + +/* Define generic CDC_ECM equivalences. */ +#define UX_DEVICE_CLASS_CDC_ECM_CLASS_COMMUNICATION_CONTROL 0x02 +#define UX_DEVICE_CLASS_CDC_ECM_SUBCLASS_COMMUNICATION_CONTROL 0x06 +#define UX_DEVICE_CLASS_CDC_ECM_CLASS_COMMUNICATION_DATA 0x0A +#define UX_DEVICE_CLASS_CDC_ECM_NEW_INTERRUPT_EVENT 0x01 +#define UX_DEVICE_CLASS_CDC_ECM_NEW_BULKOUT_EVENT 0x02 +#define UX_DEVICE_CLASS_CDC_ECM_NEW_BULKIN_EVENT 0x04 +#define UX_DEVICE_CLASS_CDC_ECM_NEW_DEVICE_STATE_CHANGE_EVENT 0x08 +#define UX_DEVICE_CLASS_CDC_ECM_NETWORK_NOTIFICATION_EVENT 0x10 +#define UX_DEVICE_CLASS_CDC_ECM_INTERRUPT_RESPONSE_LENGTH 8 +#define UX_DEVICE_CLASS_CDC_ECM_MAX_CONTROL_RESPONSE_LENGTH 256 +#define UX_DEVICE_CLASS_CDC_ECM_INTERRUPT_RESPONSE_AVAILABLE_FLAG 1 +#define UX_DEVICE_CLASS_CDC_ECM_BASE_IP_ADDRESS 0xC0A80001 +#define UX_DEVICE_CLASS_CDC_ECM_BASE_IP_MASK 0xFFFFFF00 +#define UX_DEVICE_CLASS_CDC_ECM_MAX_MTU 1518 +#define UX_DEVICE_CLASS_CDC_ECM_ETHERNET_IP 0x0800 +#define UX_DEVICE_CLASS_CDC_ECM_ETHERNET_ARP 0x0806 +#define UX_DEVICE_CLASS_CDC_ECM_ETHERNET_RARP 0x8035 +#define UX_DEVICE_CLASS_CDC_ECM_ETHERNET_PACKET_SIZE 1536 +#define UX_DEVICE_CLASS_CDC_ECM_NX_ALIGN_PADDING 2 +#ifndef UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES +#define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 +#endif + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PACKET_SIZE sizeof(NX_PACKET) + +#define UX_DEVICE_CLASS_CDC_ECM_NX_PAYLOAD_SIZE_ASSERT UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_ADD_ULONG(UX_DEVICE_CLASS_CDC_ECM_ETHERNET_PACKET_SIZE, UX_DEVICE_CLASS_CDC_ECM_NX_ALIGN_PADDING), UX_DEVICE_CLASS_CDC_ECM_NX_PAYLOAD_SIZE_calc_ovf) +#define UX_DEVICE_CLASS_CDC_ECM_NX_PAYLOAD_SIZE (UX_DEVICE_CLASS_CDC_ECM_ETHERNET_PACKET_SIZE + UX_DEVICE_CLASS_CDC_ECM_NX_ALIGN_PADDING) + +#define UX_DEVICE_CLASS_CDC_ECM_NX_BUFF_SIZE_ASSERT \ + UX_DEVICE_CLASS_CDC_ECM_NX_PAYLOAD_SIZE_ASSERT \ + UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_ADD_ULONG( \ + UX_DEVICE_CLASS_CDC_ECM_NX_PAYLOAD_SIZE, \ + UX_DEVICE_CLASS_CDC_ECM_NX_PACKET_SIZE), \ + UX_DEVICE_CLASS_CDC_ECM_NX_BUFF_SIZE_calc_ovf) +#define UX_DEVICE_CLASS_CDC_ECM_NX_BUFF_SIZE (UX_DEVICE_CLASS_CDC_ECM_NX_PAYLOAD_SIZE + UX_DEVICE_CLASS_CDC_ECM_NX_PACKET_SIZE) + +#define UX_DEVICE_CLASS_CDC_ECM_NX_ETHERNET_POOL_ALLOCSIZE_ASSERT \ + UX_DEVICE_CLASS_CDC_ECM_NX_BUFF_SIZE_ASSERT \ + UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_MULC_ULONG( \ + UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES, \ + UX_DEVICE_CLASS_CDC_ECM_NX_BUFF_SIZE), \ + UX_DEVICE_CLASS_CDC_ECM_NX_ETHERNET_POOL_ALLOCSIZE_calc1_ovf) \ + UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_ADD_ULONG( \ + UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES * \ + UX_DEVICE_CLASS_CDC_ECM_NX_BUFF_SIZE, \ + 32), UX_DEVICE_CLASS_CDC_ECM_NX_ETHERNET_POOL_ALLOCSIZE_calc2_ovf) +#define UX_DEVICE_CLASS_CDC_ECM_NX_ETHERNET_POOL_ALLOCSIZE (UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES * UX_DEVICE_CLASS_CDC_ECM_NX_BUFF_SIZE + 32) + +#define UX_DEVICE_CLASS_CDC_ECM_ETHERNET_SIZE 14 +#define UX_DEVICE_CLASS_CDC_ECM_NODE_ID_LENGTH 6 +#define UX_DEVICE_CLASS_CDC_ECM_VENDOR_DESCRIPTION_MAX_LENGTH 64 +#define UX_DEVICE_CLASS_CDC_ECM_MAC_OPTIONS 8 +#define UX_DEVICE_CLASS_CDC_ECM_PACKET_HEADER_MSG 1 + +/* Device CDC_ECM Requests */ +#define UX_DEVICE_CLASS_CDC_ECM_SEND_ENCAPSULATED_COMMAND 0x00 +#define UX_DEVICE_CLASS_CDC_ECM_GET_ENCAPSULATED_RESPONSE 0x01 +#define UX_DEVICE_CLASS_CDC_ECM_SET_ETHERNET_MULTICAST_FILTER 0x40 +#define UX_DEVICE_CLASS_CDC_ECM_SET_ETHERNET_POWER_MANAGEMENT_FILTER 0x41 +#define UX_DEVICE_CLASS_CDC_ECM_GET_ETHERNET_POWER_MANAGEMENT_FILTER 0x42 +#define UX_DEVICE_CLASS_CDC_ECM_SET_ETHERNET_PACKET_FILTER 0x43 + +/* Define CDC_ECM Versions. Set to 1.0 here. */ +#define UX_DEVICE_CLASS_CDC_ECM_VERSION_MAJOR 0x00000001 +#define UX_DEVICE_CLASS_CDC_ECM_VERSION_MINOR 0x00000000 + +/* Define CDC_ECM Connection type supported. Set to conectionless. */ +#define UX_DEVICE_CLASS_CDC_ECM_DF_CONNECTIONLESS 0x00000001 +#define UX_DEVICE_CLASS_CDC_ECM_DF_CONNECTION_ORIENTED 0x00000002 +#define UX_DEVICE_CLASS_CDC_ECM_DF_CONNECTION_SUPPORTED UX_DEVICE_CLASS_CDC_ECM_DF_CONNECTIONLESS + +/* Define CDC_ECM Medium supported by the device. */ +#define UX_DEVICE_CLASS_CDC_ECM_MEDIUM_SUPPORTED 0x00000000 + +/* Define CDC_ECM Packet size and types supported. */ +#define UX_DEVICE_CLASS_CDC_ECM_MAX_PACKET_PER_TRANSFER 0x00000001 +#define UX_DEVICE_CLASS_CDC_ECM_MAX_PACKET_TRANSFER_SIZE 0x00000640 +#define UX_DEVICE_CLASS_CDC_ECM_PACKET_ALIGNEMENT_FACTOR 0x00000003 +#define UX_DEVICE_CLASS_CDC_ECM_MAX_FRAME_SIZE 0x000005DC +#define UX_DEVICE_CLASS_CDC_ECM_MAX_PACKET_LENGTH 0x000005EA + +/* Define LINK speeds. */ +#define UX_DEVICE_CLASS_CDC_ECM_LINK_SPEED_FS 0x0001D4C0 + +/* Define LINK statess. */ +#define UX_DEVICE_CLASS_CDC_ECM_LINK_STATE_DOWN 0 +#define UX_DEVICE_CLASS_CDC_ECM_LINK_STATE_UP 1 +#define UX_DEVICE_CLASS_CDC_ECM_LINK_STATE_PENDING_UP 2 +#define UX_DEVICE_CLASS_CDC_ECM_LINK_STATE_PENDING_DOWN 3 + +/* Define media connection values. */ +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_CONNECTED 0x00000000 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_DISCONNECTED 0x00000001 + +/* Define media supported values. */ +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_802_3 0x00000000 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_802_5 0x00000001 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_FDDI 0x00000002 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_WAN 0x00000003 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_LOCAL_TALK 0x00000004 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_DIX 0x00000005 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_ARCNET_RAW 0x00000006 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_ARCNET_878_2 0x00000007 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_ATM 0x00000008 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_WIRELESS_WAN 0x00000009 +#define UX_DEVICE_CLASS_CDC_ECM_MEDIA_IRDA 0x0000000A + +/* Define CDC_ECM status values. */ +#define UX_DEVICE_CLASS_CDC_ECM_STATUS_SUCCESS 0x00000000 +#define UX_DEVICE_CLASS_CDC_ECM_STATUS_FAILURE 0xC0000001 +#define UX_DEVICE_CLASS_CDC_ECM_STATUS_INVALID_DATA 0xC0010015 +#define UX_DEVICE_CLASS_CDC_ECM_STATUS_NOT_SUPPORTED 0xC00000BB +#define UX_DEVICE_CLASS_CDC_ECM_STATUS_MEDIA_CONNECTED 0x4001000B +#define UX_DEVICE_CLASS_CDC_ECM_STATUS_MEDIA_DISCONNECT 0x4001000C + +/* Define CDC_ECM Control Messages values. */ + +/* Define CDC_ECM State machine. */ +#define UX_DEVICE_CLASS_CDC_ECM_STATE_UNINITIALIZED 0x00000000 +#define UX_DEVICE_CLASS_CDC_ECM_STATE_INITIALIZED 0x00000001 +#define UX_DEVICE_CLASS_CDC_ECM_STATE_DATA_INITIALIZED 0x00000002 + +/* Define NetX errors inside the CDC_ECM class. */ +#define UX_DEVICE_CLASS_CDC_ECM_NX_SUCCESS 0x00 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NO_PACKET 0x01 +#define UX_DEVICE_CLASS_CDC_ECM_NX_UNDERFLOW 0x02 +#define UX_DEVICE_CLASS_CDC_ECM_NX_OVERFLOW 0x03 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NO_MAPPING 0x04 +#define UX_DEVICE_CLASS_CDC_ECM_NX_DELETED 0x05 +#define UX_DEVICE_CLASS_CDC_ECM_NX_POOL_ERROR 0x06 +#define UX_DEVICE_CLASS_CDC_ECM_NX_PTR_ERROR 0x07 +#define UX_DEVICE_CLASS_CDC_ECM_NX_WAIT_ERROR 0x08 +#define UX_DEVICE_CLASS_CDC_ECM_NX_SIZE_ERROR 0x09 +#define UX_DEVICE_CLASS_CDC_ECM_NX_OPTION_ERROR 0x0a +#define UX_DEVICE_CLASS_CDC_ECM_NX_DELETE_ERROR 0x10 +#define UX_DEVICE_CLASS_CDC_ECM_NX_CALLER_ERROR 0x11 +#define UX_DEVICE_CLASS_CDC_ECM_NX_INVALID_PACKET 0x12 +#define UX_DEVICE_CLASS_CDC_ECM_NX_INVALID_SOCKET 0x13 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NOT_ENABLED 0x14 +#define UX_DEVICE_CLASS_CDC_ECM_NX_ALREADY_ENABLED 0x15 +#define UX_DEVICE_CLASS_CDC_ECM_NX_ENTRY_NOT_FOUND 0x16 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NO_MORE_ENTRIES 0x17 +#define UX_DEVICE_CLASS_CDC_ECM_NX_ARP_TIMER_ERROR 0x18 +#define UX_DEVICE_CLASS_CDC_ECM_NX_RESERVED_CODE0 0x19 +#define UX_DEVICE_CLASS_CDC_ECM_NX_WAIT_ABORTED 0x1A +#define UX_DEVICE_CLASS_CDC_ECM_NX_IP_INTERNAL_ERROR 0x20 +#define UX_DEVICE_CLASS_CDC_ECM_NX_IP_ADDRESS_ERROR 0x21 +#define UX_DEVICE_CLASS_CDC_ECM_NX_ALREADY_BOUND 0x22 +#define UX_DEVICE_CLASS_CDC_ECM_NX_PORT_UNAVAILABLE 0x23 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NOT_BOUND 0x24 +#define UX_DEVICE_CLASS_CDC_ECM_NX_RESERVED_CODE1 0x25 +#define UX_DEVICE_CLASS_CDC_ECM_NX_SOCKET_UNBOUND 0x26 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NOT_CREATED 0x27 +#define UX_DEVICE_CLASS_CDC_ECM_NX_SOCKETS_BOUND 0x28 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NO_RESPONSE 0x29 +#define UX_DEVICE_CLASS_CDC_ECM_NX_POOL_DELETED 0x30 +#define UX_DEVICE_CLASS_CDC_ECM_NX_ALREADY_RELEASED 0x31 +#define UX_DEVICE_CLASS_CDC_ECM_NX_RESERVED_CODE2 0x32 +#define UX_DEVICE_CLASS_CDC_ECM_NX_MAX_LISTEN 0x33 +#define UX_DEVICE_CLASS_CDC_ECM_NX_DUPLICATE_LISTEN 0x34 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NOT_CLOSED 0x35 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NOT_LISTEN_STATE 0x36 +#define UX_DEVICE_CLASS_CDC_ECM_NX_IN_PROGRESS 0x37 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NOT_CONNECTED 0x38 +#define UX_DEVICE_CLASS_CDC_ECM_NX_WINDOW_OVERFLOW 0x39 +#define UX_DEVICE_CLASS_CDC_ECM_NX_ALREADY_SUSPENDED 0x40 +#define UX_DEVICE_CLASS_CDC_ECM_NX_DISCONNECT_FAILED 0x41 +#define UX_DEVICE_CLASS_CDC_ECM_NX_STILL_BOUND 0x42 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NOT_SUCCESSFUL 0x43 +#define UX_DEVICE_CLASS_CDC_ECM_NX_UNHANDLED_COMMAND 0x44 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NO_FREE_PORTS 0x45 +#define UX_DEVICE_CLASS_CDC_ECM_NX_INVALID_PORT 0x46 +#define UX_DEVICE_CLASS_CDC_ECM_NX_INVALID_RELISTEN 0x47 +#define UX_DEVICE_CLASS_CDC_ECM_NX_CONNECTION_PENDING 0x48 +#define UX_DEVICE_CLASS_CDC_ECM_NX_TX_QUEUE_DEPTH 0x49 +#define UX_DEVICE_CLASS_CDC_ECM_NX_NOT_IMPLEMENTED 0x80 + +/* Define timeout packet allocation value. */ +#ifndef UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT +#define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 1000 +#endif + +/* Define Slave CDC_ECM Class Calling Parameter structure */ + +typedef struct UX_SLAVE_CLASS_CDC_ECM_PARAMETER_STRUCT +{ + VOID (*ux_slave_class_cdc_ecm_instance_activate)(VOID *); + VOID (*ux_slave_class_cdc_ecm_instance_deactivate)(VOID *); + ULONG ux_slave_class_cdc_ecm_parameter_media; + ULONG ux_slave_class_cdc_ecm_parameter_vendor_id; + ULONG ux_slave_class_cdc_ecm_parameter_driver_version; + UCHAR ux_slave_class_cdc_ecm_parameter_vendor_description[UX_DEVICE_CLASS_CDC_ECM_VENDOR_DESCRIPTION_MAX_LENGTH]; + UCHAR ux_slave_class_cdc_ecm_parameter_local_node_id[UX_DEVICE_CLASS_CDC_ECM_NODE_ID_LENGTH]; + UCHAR ux_slave_class_cdc_ecm_parameter_remote_node_id[UX_DEVICE_CLASS_CDC_ECM_NODE_ID_LENGTH]; +} UX_SLAVE_CLASS_CDC_ECM_PARAMETER; + +/* Define CDC_ECM Class structure. */ + +typedef struct UX_SLAVE_CLASS_CDC_ECM_STRUCT +{ + UX_SLAVE_INTERFACE *ux_slave_class_cdc_ecm_interface; + UX_SLAVE_CLASS_CDC_ECM_PARAMETER ux_slave_class_cdc_ecm_parameter; + UX_SLAVE_ENDPOINT *ux_slave_class_cdc_ecm_bulkin_endpoint; + UX_SLAVE_ENDPOINT *ux_slave_class_cdc_ecm_bulkout_endpoint; + UX_SLAVE_ENDPOINT *ux_slave_class_cdc_ecm_interrupt_endpoint; + ULONG ux_slave_class_cdc_ecm_state; + ULONG ux_slave_class_cdc_ecm_current_alternate_setting; + ULONG ux_slave_class_cdc_ecm_max_transfer_size; + ULONG ux_slave_class_cdc_ecm_request_id; + ULONG ux_slave_class_cdc_ecm_statistics_xmit_ok; + ULONG ux_slave_class_cdc_ecm_statistics_rcv_ok; + ULONG ux_slave_class_cdc_ecm_statistics_xmit_error; + ULONG ux_slave_class_cdc_ecm_statistics_rcv_error; + ULONG ux_slave_class_cdc_ecm_statistics_rcv_no_buffer; + ULONG ux_slave_class_cdc_ecm_statistics_rcv_error_alignment; + ULONG ux_slave_class_cdc_ecm_statistics_xmit_one_collision; + ULONG ux_slave_class_cdc_ecm_statistics_xmit_more_collisions; + ULONG ux_slave_class_cdc_ecm_ethernet_multicast_filter; + ULONG ux_slave_class_cdc_ecm_ethernet_power_management_filter; + ULONG ux_slave_class_cdc_ecm_ethernet_packet_filter; + UX_EVENT_FLAGS_GROUP ux_slave_class_cdc_ecm_event_flags_group; + UCHAR ux_slave_class_cdc_ecm_local_node_id[UX_DEVICE_CLASS_CDC_ECM_NODE_ID_LENGTH]; + UCHAR ux_slave_class_cdc_ecm_remote_node_id[UX_DEVICE_CLASS_CDC_ECM_NODE_ID_LENGTH]; + NX_IP *ux_slave_class_cdc_ecm_nx_ip; + ULONG ux_slave_class_cdc_ecm_nx_ip_address; + ULONG ux_slave_class_cdc_ecm_nx_ip_network_mask; + NX_INTERFACE *ux_slave_class_cdc_ecm_nx_interface; + NX_PACKET *ux_slave_class_cdc_ecm_xmit_queue; + NX_PACKET *ux_slave_class_cdc_ecm_xmit_queue_tail; + NX_PACKET *ux_slave_class_cdc_ecm_receive_queue; + UCHAR *ux_slave_class_cdc_ecm_pool_memory; + NX_PACKET_POOL ux_slave_class_cdc_ecm_packet_pool; + UX_THREAD ux_slave_class_cdc_ecm_bulkin_thread; + UX_THREAD ux_slave_class_cdc_ecm_bulkout_thread; + UX_THREAD ux_slave_class_cdc_ecm_interrupt_thread; + UCHAR *ux_slave_class_cdc_ecm_bulkin_thread_stack; + UCHAR *ux_slave_class_cdc_ecm_bulkout_thread_stack; + UCHAR *ux_slave_class_cdc_ecm_interrupt_thread_stack; + ULONG ux_slave_class_cdc_ecm_link_state; + UX_MUTEX ux_slave_class_cdc_ecm_mutex; + VOID *ux_slave_class_cdc_ecm_network_handle; + +} UX_SLAVE_CLASS_CDC_ECM; + + +/* Requests - Ethernet Networking Control Model */ + +#define UX_DEVICE_CLASS_CDC_ECM_SEND_ENCAPSULATED_COMMAND 0x00 + /* Issues a command in the format of the supported control + protocol. The intent of this mechanism is to support + networking devices (e.g., host-based cable modems) + that require an additional vendor-defined interface for + media specific hardware configuration and + management. */ +#define UX_DEVICE_CLASS_CDC_ECM_GET_ENCAPSULATED_RESPONSE 0x01 + /* Requests a response in the format of the supported + control protocol. */ + + +/* Define buffer length for IN/OUT pipes. */ + +#define UX_DEVICE_CLASS_CDC_ECM_BUFFER_SIZE 4096 + + +/* Define Device CDC_ECM Class prototypes. */ + +UINT _ux_device_class_cdc_ecm_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_ecm_control_request(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_ecm_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_ecm_change(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_ecm_entry(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_ecm_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_ecm_uninitialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_cdc_ecm_write(VOID *cdc_ecm_class, NX_PACKET *packet); +VOID _ux_device_class_cdc_ecm_bulkin_thread(ULONG cdc_ecm_class); +VOID _ux_device_class_cdc_ecm_bulkout_thread(ULONG cdc_ecm_class); +VOID _ux_device_class_cdc_ecm_interrupt_thread(ULONG cdc_ecm_class); + + +/* Define Device CDC Class API prototypes. */ + +#define ux_device_class_cdc_ecm_entry _ux_device_class_cdc_ecm_entry +#define ux_device_class_cdc_ecm_read _ux_device_class_cdc_ecm_read +#define ux_device_class_cdc_ecm_write _ux_device_class_cdc_ecm_write + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif /* UX_DEVICE_CLASS_CDC_ECM_H */ diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_dfu.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_dfu.h new file mode 100644 index 00000000..d7f3e0ab --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_dfu.h @@ -0,0 +1,264 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** DFU Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_dfu.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the equivalences for the USBX Device Class DFU */ +/* ACM component. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added DFU_UPLOAD support, */ +/* refined dfu_read prototype, */ +/* removed block count (it's */ +/* from host request wValue), */ +/* resulting in version 6.1.6 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_DFU_H +#define UX_DEVICE_CLASS_DFU_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + +/* Define DFU class descriptor capabilities. */ +#define UX_SLAVE_CLASS_DFU_CAPABILITY_WILL_DETACH 0x08 +#define UX_SLAVE_CLASS_DFU_CAPABILITY_MANIFESTATION_TOLERANT 0x04 +#define UX_SLAVE_CLASS_DFU_CAPABILITY_CAN_UPLOAD 0x02 +#define UX_SLAVE_CLASS_DFU_CAPABILITY_CAN_DOWNLOAD 0x01 + +/* Define DFU Class USB Class constants. */ +#define UX_SLAVE_CLASS_DFU_CLASS 0xFE +#define UX_SLAVE_CLASS_DFU_SUBCLASS 0x01 +#define UX_SLAVE_CLASS_DFU_PROTOCOL_RUNTIME 0x01 +#define UX_SLAVE_CLASS_DFU_PROTOCOL_DFU_MODE 0x02 + +/* Define DFU MODES signals. */ +#define UX_DEVICE_CLASS_DFU_MODE_RUNTIME 1 +#define UX_DEVICE_CLASS_DFU_MODE_DFU 2 + + + + +/* Device DFU Requests */ +#define UX_SLAVE_CLASS_DFU_COMMAND_DETACH 0 +#define UX_SLAVE_CLASS_DFU_COMMAND_DOWNLOAD 1 +#define UX_SLAVE_CLASS_DFU_COMMAND_UPLOAD 2 +#define UX_SLAVE_CLASS_DFU_COMMAND_GET_STATUS 3 +#define UX_SLAVE_CLASS_DFU_COMMAND_CLEAR_STATUS 4 +#define UX_SLAVE_CLASS_DFU_COMMAND_GET_STATE 5 +#define UX_SLAVE_CLASS_DFU_COMMAND_ABORT 6 + +/* Device DFU Status values */ +#define UX_SLAVE_CLASS_DFU_STATUS_OK 0x00 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_TARGET 0x01 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_FILE 0x02 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_WRITE 0x03 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_ERASE 0x04 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_CHECK_ERASED 0x05 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_PROG 0x06 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_VERIFY 0x07 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_ADDRESS 0x08 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_NOTDONE 0x09 +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_FIRMWARE 0x0A +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_VENDOR 0x0B +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_USBR 0x0C +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_POR 0x0D +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_UNKNOWN 0x0E +#define UX_SLAVE_CLASS_DFU_STATUS_ERROR_STALLEDPKT 0x0F + +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_APP_IDLE 0 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_APP_DETACH 1 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_IDLE 2 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_DNLOAD_SYNC 3 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_DNBUSY 4 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_DNLOAD_IDLE 5 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_MANIFEST_SYNC 6 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_MANIFEST 7 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_MANIFEST_WAIT_RESET 8 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_UPLOAD_IDLE 9 +#define UX_SLAVE_CLASS_DFU_STATUS_STATE_DFU_ERROR 10 + +/* Define DFU class GET_STATUS command response. */ +#define UX_SLAVE_CLASS_DFU_GET_STATUS_STATUS 0 +#define UX_SLAVE_CLASS_DFU_GET_STATUS_POLL_TIMEOUT 1 +#define UX_SLAVE_CLASS_DFU_GET_STATUS_STATE 4 +#define UX_SLAVE_CLASS_DFU_GET_STATUS_STRING 5 +#define UX_SLAVE_CLASS_DFU_GET_STATUS_LENGTH 6 + +/* Status mode for DFU_GETSTATUS + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ +#ifndef UX_DEVICE_CLASS_DFU_STATUS_MODE +#define UX_DEVICE_CLASS_DFU_STATUS_MODE (0) +#endif + +/* Status mode 0 bwPollTimeout (width: 3 bytes, ~0xFFFFFF). */ +#ifndef UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT +#define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT (1) +#endif + + +/* Define DFU class GET_STATE command response. */ +#define UX_SLAVE_CLASS_DFU_GET_STATE_STATE 0 +#define UX_SLAVE_CLASS_DFU_GET_STATE_LENGTH 1 + +/* Define DFU application notification signals. */ +#define UX_SLAVE_CLASS_DFU_NOTIFICATION_BEGIN_DOWNLOAD 0x1u +#define UX_SLAVE_CLASS_DFU_NOTIFICATION_END_DOWNLOAD 0x2u +#define UX_SLAVE_CLASS_DFU_NOTIFICATION_ABORT_DOWNLOAD 0x3u +#define UX_SLAVE_CLASS_DFU_NOTIFICATION_BEGIN_UPLOAD 0x5u +#define UX_SLAVE_CLASS_DFU_NOTIFICATION_END_UPLOAD 0x6u +#define UX_SLAVE_CLASS_DFU_NOTIFICATION_ABORT_UPLOAD 0x7u + +/* Define DFU application notification signals. */ +#define UX_SLAVE_CLASS_DFU_MEDIA_STATUS_OK 0 +#define UX_SLAVE_CLASS_DFU_MEDIA_STATUS_BUSY 1 +#define UX_SLAVE_CLASS_DFU_MEDIA_STATUS_ERROR 2 + +/* Define DFU thread event signals. */ +#define UX_DEVICE_CLASS_DFU_THREAD_EVENT_DISCONNECT 0x1u +#define UX_DEVICE_CLASS_DFU_THREAD_EVENT_WAIT_RESET 0x2u + +/* Define Slave DFU Class Calling Parameter structure */ + +typedef struct UX_SLAVE_CLASS_DFU_PARAMETER_STRUCT +{ + + ULONG ux_slave_class_dfu_parameter_will_detach; + ULONG ux_slave_class_dfu_parameter_capabilities; + VOID (*ux_slave_class_dfu_parameter_instance_activate)(VOID *); + VOID (*ux_slave_class_dfu_parameter_instance_deactivate)(VOID *); + UINT (*ux_slave_class_dfu_parameter_read)(VOID *dfu, ULONG block_number, UCHAR * data_pointer, ULONG length, ULONG *actual_length); + UINT (*ux_slave_class_dfu_parameter_write)(VOID *dfu, ULONG block_number, UCHAR * data_pointer, ULONG length, ULONG *media_status); + UINT (*ux_slave_class_dfu_parameter_get_status)(VOID *dfu, ULONG *media_status); + UINT (*ux_slave_class_dfu_parameter_notify)(VOID *dfu, ULONG notification); +#ifdef UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE + UINT (*ux_device_class_dfu_parameter_custom_request)(VOID *dfu, UX_SLAVE_TRANSFER *transfer); +#endif + UCHAR *ux_slave_class_dfu_parameter_framework; + ULONG ux_slave_class_dfu_parameter_framework_length; + +} UX_SLAVE_CLASS_DFU_PARAMETER; + +/* Define DFU Class structure. */ + +typedef struct UX_SLAVE_CLASS_DFU_STRUCT +{ + UX_SLAVE_INTERFACE *ux_slave_class_dfu_interface; + ULONG ux_slave_class_dfu_status; + VOID (*ux_slave_class_dfu_instance_activate)(VOID *); + VOID (*ux_slave_class_dfu_instance_deactivate)(VOID *); + UINT (*ux_slave_class_dfu_read)(VOID *dfu, ULONG block_number, UCHAR * data_pointer, ULONG length, ULONG *actual_length); + UINT (*ux_slave_class_dfu_write)(VOID *dfu, ULONG block_number, UCHAR * data_pointer, ULONG length, ULONG *media_status); + UINT (*ux_slave_class_dfu_get_status)(VOID *dfu, ULONG *media_status); + UINT (*ux_slave_class_dfu_notify)(VOID *dfu, ULONG notification); +#ifdef UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE + UINT (*ux_device_class_dfu_custom_request)(VOID *dfu, UX_SLAVE_TRANSFER *transfer); +#endif + +#if !defined(UX_DEVICE_STANDALONE) + UX_THREAD ux_slave_class_dfu_thread; + UCHAR *ux_slave_class_dfu_thread_stack; + UX_EVENT_FLAGS_GROUP ux_slave_class_dfu_event_flags_group; +#else + ULONG ux_device_class_dfu_flags; +#endif +} UX_SLAVE_CLASS_DFU; + +#if !defined(UX_DEVICE_STANDALONE) +#define _ux_device_class_dfu_event_flags_set(dfu, flags) do { \ + _ux_utility_event_flags_set(&(dfu) -> ux_slave_class_dfu_event_flags_group, flags, UX_OR); \ + } while(0) +#else +#define _ux_device_class_dfu_event_flags_set(dfu, flags) do { \ + (dfu) -> ux_device_class_dfu_flags |= flags; \ + } while(0) +#endif + +/* Define Device DFU Class prototypes. */ + +UINT _ux_device_class_dfu_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_dfu_control_request(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_dfu_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_dfu_entry(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_dfu_initialize(UX_SLAVE_CLASS_COMMAND *command); +VOID _ux_device_class_dfu_thread(ULONG dfu_class); + +UCHAR _ux_device_class_dfu_state_get(UX_SLAVE_CLASS_DFU *dfu); +VOID _ux_device_class_dfu_state_sync(UX_SLAVE_CLASS_DFU *dfu); + +UINT _ux_device_class_dfu_tasks_run(VOID *class_instance); + +/* Define Device DFU Class API prototypes. */ + +#define ux_device_class_dfu_entry _ux_device_class_dfu_entry +#define ux_device_class_dfu_state_get _ux_device_class_dfu_state_get +#define ux_device_class_dfu_state_sync _ux_device_class_dfu_state_sync + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif /* UX_DEVICE_CLASS_DFU_H */ diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_hid.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_hid.h new file mode 100644 index 00000000..6532c91d --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_hid.h @@ -0,0 +1,315 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** HID Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_hid.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX HID class. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* added Get/Set Protocol */ +/* request support, */ +/* resulting in version 6.1.3 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* added interrupt OUT support,*/ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_HID_H +#define UX_DEVICE_CLASS_HID_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + +/* Device HID Compile Options. */ + +/* If defined, interrupt OUT transfer is supported. */ +/* #define UX_DEVICE_CLASS_HID_INTERRUPT_OUT_SUPPORT */ + +/* Use UX general thread stack size for receiver thread. */ +#define UX_DEVICE_CLASS_HID_RECEIVER_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + +/* Use UX general thread stack size for HID class thread. */ +#define UX_DEVICE_CLASS_HID_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE + + +/* Define HID Class constants. */ + +#define UX_DEVICE_CLASS_HID_CLASS 0x03 +#define UX_DEVICE_CLASS_HID_SUBCLASS 0X00 +#define UX_DEVICE_CLASS_HID_PROTOCOL 0X00 + +/* Define HID Class commands. */ + +#define UX_DEVICE_CLASS_HID_COMMAND_GET_REPORT 0x01 +#define UX_DEVICE_CLASS_HID_COMMAND_GET_IDLE 0x02 +#define UX_DEVICE_CLASS_HID_COMMAND_GET_PROTOCOL 0x03 +#define UX_DEVICE_CLASS_HID_COMMAND_SET_REPORT 0x09 +#define UX_DEVICE_CLASS_HID_COMMAND_SET_IDLE 0x0A +#define UX_DEVICE_CLASS_HID_COMMAND_SET_PROTOCOL 0x0B + +/* Define HID Class Descriptor types. */ + +#define UX_DEVICE_CLASS_HID_DESCRIPTOR_HID 0x21 +#define UX_DEVICE_CLASS_HID_DESCRIPTOR_REPORT 0x22 +#define UX_DEVICE_CLASS_HID_DESCRIPTOR_PHYSICAL 0x23 + +/* Define HID Report Types. */ + +#define UX_DEVICE_CLASS_HID_REPORT_TYPE_INPUT 0x1 +#define UX_DEVICE_CLASS_HID_REPORT_TYPE_OUTPUT 0x2 +#define UX_DEVICE_CLASS_HID_REPORT_TYPE_FEATURE 0x3 + +/* Define HID Protocols. */ + +#define UX_DEVICE_CLASS_HID_PROTOCOL_BOOT 0 +#define UX_DEVICE_CLASS_HID_PROTOCOL_REPORT 1 + +/* Define HID event info structure. */ + +#ifndef UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH +#define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 32 +#endif + +/* Ensure the event buffer can fit inside the control endpoint's data buffer. */ +#if UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH > UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH +#error "Error: the event buffer cannot fit inside the control endpoint's data buffer. Reduce UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH such that it is less than or equal to UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH." +#endif + +/* Ensure the event buffer can fit inside the interrupt endpoint's data buffer. */ +#if UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH > UX_SLAVE_REQUEST_DATA_MAX_LENGTH +#error "Error: the event buffer cannot fit inside the interrupt endpoint's data buffer. Reduce UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH such that it is less than or equal to UX_SLAVE_REQUEST_DATA_MAX_LENGTH." +#endif + +#ifndef UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE +#define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 16 +#endif + +#define UX_DEVICE_CLASS_HID_NEW_EVENT 1u +#define UX_DEVICE_CLASS_HID_NEW_IDLE_RATE 2u +#define UX_DEVICE_CLASS_HID_EVENTS_MASK 3u /* Mask _NEW_EVENT and _NEW_IDLE_RATE */ + +#define UX_DEVICE_CLASS_HID_RECEIVER_RESTART 4u + +#define UX_DEVICE_CLASS_HID_EVENTS_ALL_MASK 7u /* Mask all event flags. */ + +typedef struct UX_SLAVE_CLASS_HID_EVENT_STRUCT +{ + ULONG ux_device_class_hid_event_report_id; + ULONG ux_device_class_hid_event_report_type; + UCHAR ux_device_class_hid_event_buffer[UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH]; + ULONG ux_device_class_hid_event_length; + +} UX_SLAVE_CLASS_HID_EVENT; + +/* Define HID structure. */ + +typedef struct UX_SLAVE_CLASS_HID_STRUCT +{ + + UX_SLAVE_INTERFACE *ux_slave_class_hid_interface; + UX_SLAVE_ENDPOINT *ux_device_class_hid_interrupt_endpoint; + UINT ux_device_class_hid_state; + UINT (*ux_device_class_hid_callback)(struct UX_SLAVE_CLASS_HID_STRUCT *hid, UX_SLAVE_CLASS_HID_EVENT *); + UINT (*ux_device_class_hid_get_callback)(struct UX_SLAVE_CLASS_HID_STRUCT *hid, UX_SLAVE_CLASS_HID_EVENT *); + VOID (*ux_slave_class_hid_instance_activate)(VOID *); + VOID (*ux_slave_class_hid_instance_deactivate)(VOID *); + UCHAR *ux_device_class_hid_report_address; + ULONG ux_device_class_hid_report_id; + ULONG ux_device_class_hid_report_length; +#if !defined(UX_DEVICE_STANDALONE) + UX_EVENT_FLAGS_GROUP ux_device_class_hid_event_flags_group; +#else + UINT ux_device_class_hid_event_state; + ULONG ux_device_class_hid_event_wait_start; + UX_SLAVE_CLASS_HID_EVENT ux_device_class_hid_event; +#endif + ULONG ux_device_class_hid_event_idle_rate; + ULONG ux_device_class_hid_event_wait_timeout; + ULONG ux_device_class_hid_protocol; + UX_SLAVE_CLASS_HID_EVENT *ux_device_class_hid_event_array; + UX_SLAVE_CLASS_HID_EVENT *ux_device_class_hid_event_array_head; + UX_SLAVE_CLASS_HID_EVENT *ux_device_class_hid_event_array_tail; + UX_SLAVE_CLASS_HID_EVENT *ux_device_class_hid_event_array_end; + +#if defined(UX_DEVICE_CLASS_HID_INTERRUPT_OUT_SUPPORT) + UX_SLAVE_ENDPOINT *ux_device_class_hid_read_endpoint; + struct UX_DEVICE_CLASS_HID_RECEIVER_STRUCT + *ux_device_class_hid_receiver; +#if !defined(UX_DEVICE_STANDALONE) + UX_MUTEX ux_device_class_hid_read_mutex; +#else + UCHAR *ux_device_class_hid_read_buffer; + UCHAR ux_device_class_hid_read_requested_length; + UCHAR ux_device_class_hid_read_actual_length; + UCHAR ux_device_class_hid_read_transfer_length; + UINT ux_device_class_hid_read_state; +#endif +#endif + +} UX_SLAVE_CLASS_HID; + + +/* HID interrupt OUT support extensions. */ + +typedef struct UX_DEVICE_CLASS_HID_RECEIVED_EVENT_STRUCT +{ + ULONG ux_device_class_hid_received_event_length; + UCHAR *ux_device_class_hid_received_event_data; +} UX_DEVICE_CLASS_HID_RECEIVED_EVENT; + +typedef struct UX_DEVICE_CLASS_HID_RECEIVER_STRUCT +{ + + VOID (*ux_device_class_hid_receiver_uninitialize)(struct UX_DEVICE_CLASS_HID_RECEIVER_STRUCT *receiver); + + ULONG ux_device_class_hid_receiver_event_buffer_size; + UX_DEVICE_CLASS_HID_RECEIVED_EVENT + *ux_device_class_hid_receiver_events; + UX_DEVICE_CLASS_HID_RECEIVED_EVENT + *ux_device_class_hid_receiver_events_end; + UX_DEVICE_CLASS_HID_RECEIVED_EVENT + *ux_device_class_hid_receiver_event_read_pos; + UX_DEVICE_CLASS_HID_RECEIVED_EVENT + *ux_device_class_hid_receiver_event_save_pos; + +#if !defined(UX_DEVICE_STANDALONE) + UX_THREAD ux_device_class_hid_receiver_thread; +#else + VOID (*ux_device_class_hid_receiver_tasks_run)(struct UX_SLAVE_CLASS_HID_STRUCT *hid); +#endif +} UX_DEVICE_CLASS_HID_RECEIVER; + + +/* Define HID initialization command structure. */ + +typedef struct UX_SLAVE_CLASS_HID_PARAMETER_STRUCT +{ + + VOID (*ux_slave_class_hid_instance_activate)(VOID *); + VOID (*ux_slave_class_hid_instance_deactivate)(VOID *); + UCHAR *ux_device_class_hid_parameter_report_address; + ULONG ux_device_class_hid_parameter_report_id; + ULONG ux_device_class_hid_parameter_report_length; + UINT (*ux_device_class_hid_parameter_callback)(struct UX_SLAVE_CLASS_HID_STRUCT *hid, UX_SLAVE_CLASS_HID_EVENT *); + UINT (*ux_device_class_hid_parameter_get_callback)(struct UX_SLAVE_CLASS_HID_STRUCT *hid, UX_SLAVE_CLASS_HID_EVENT *); +#if defined(UX_DEVICE_CLASS_HID_INTERRUPT_OUT_SUPPORT) + UINT (*ux_device_class_hid_parameter_receiver_initialize)(UX_SLAVE_CLASS_HID *hid, struct UX_SLAVE_CLASS_HID_PARAMETER_STRUCT *parameter, UX_DEVICE_CLASS_HID_RECEIVER **receiver); + ULONG ux_device_class_hid_parameter_receiver_event_max_number; + ULONG ux_device_class_hid_parameter_receiver_event_max_length; +#endif + +} UX_SLAVE_CLASS_HID_PARAMETER; + + +/* Define HID Class function prototypes. */ +UINT _ux_device_class_hid_descriptor_send(UX_SLAVE_CLASS_HID *hid, ULONG descriptor_type, + ULONG request_index, ULONG host_length); +UINT _ux_device_class_hid_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_hid_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_hid_control_request(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_hid_entry(UX_SLAVE_CLASS_COMMAND *command); +VOID _ux_device_class_hid_interrupt_thread(ULONG hid_class); +UINT _ux_device_class_hid_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_hid_uninitialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_hid_event_set(UX_SLAVE_CLASS_HID *hid, + UX_SLAVE_CLASS_HID_EVENT *hid_event); +UINT _ux_device_class_hid_event_get(UX_SLAVE_CLASS_HID *hid, + UX_SLAVE_CLASS_HID_EVENT *hid_event); +UINT _ux_device_class_hid_report_set(UX_SLAVE_CLASS_HID *hid, ULONG descriptor_type, + ULONG request_index, ULONG host_length); +UINT _ux_device_class_hid_report_get(UX_SLAVE_CLASS_HID *hid, ULONG descriptor_type, + ULONG request_index, ULONG host_length); + +UINT _ux_device_class_hid_tasks_run(VOID *class_instance); + +UINT _ux_device_class_hid_read(UX_SLAVE_CLASS_HID *hid, + UCHAR *buffer, ULONG requested_length, + ULONG *actual_length); + +VOID _ux_device_class_hid_receiver_thread(ULONG hid_class); +UINT _ux_device_class_hid_receiver_initialize(UX_SLAVE_CLASS_HID *hid, + UX_SLAVE_CLASS_HID_PARAMETER *parameter, + UX_DEVICE_CLASS_HID_RECEIVER **receiver); +VOID _ux_device_class_hid_receiver_uninitialize(UX_DEVICE_CLASS_HID_RECEIVER *receiver); +UINT _ux_device_class_hid_receiver_event_get(UX_SLAVE_CLASS_HID *hid, + UX_DEVICE_CLASS_HID_RECEIVED_EVENT *event); +UINT _ux_device_class_hid_receiver_event_free(UX_SLAVE_CLASS_HID *hid); + + +/* Define Device HID Class API prototypes. */ + +#define ux_device_class_hid_entry _ux_device_class_hid_entry +#define ux_device_class_hid_event_set _ux_device_class_hid_event_set +#define ux_device_class_hid_event_get _ux_device_class_hid_event_get +#define ux_device_class_hid_report_set _ux_device_class_hid_report_set +#define ux_device_class_hid_report_get _ux_device_class_hid_report_get + +#define ux_device_class_hid_protocol_get(hid) (hid -> ux_device_class_hid_protocol) + +#define ux_device_class_hid_read _ux_device_class_hid_read + +#define ux_device_class_hid_receiver_initialize _ux_device_class_hid_receiver_initialize +#define ux_device_class_hid_receiver_event_get _ux_device_class_hid_receiver_event_get +#define ux_device_class_hid_receiver_event_free _ux_device_class_hid_receiver_event_free + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_pima.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_pima.h new file mode 100644 index 00000000..d489f800 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_pima.h @@ -0,0 +1,1040 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** PIMA Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_pima.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX PIMA class. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 08-02-2021 Wen Wang Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* updated definitions, */ +/* improved internal function, */ +/* added cancel callback, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_PIMA_H +#define UX_DEVICE_CLASS_PIMA_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + +/* Define PIMA Class constants. */ + +#define UX_DEVICE_CLASS_PIMA_TRANSFER_BUFFER_LENGTH UX_SLAVE_REQUEST_DATA_MAX_LENGTH +#define UX_DEVICE_CLASS_PIMA_MAX_PAYLOAD (UX_DEVICE_CLASS_PIMA_TRANSFER_BUFFER_LENGTH - UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE) +#define UX_DEVICE_CLASS_PIMA_OBJECT_INFO_BUFFER_SIZE (UX_DEVICE_CLASS_PIMA_MAX_PAYLOAD) +#define UX_DEVICE_CLASS_PIMA_DEVICE_INFO_BUFFER_SIZE (UX_DEVICE_CLASS_PIMA_MAX_PAYLOAD) +#define UX_DEVICE_CLASS_PIMA_STORAGE_INFO_BUFFER_SIZE (UX_DEVICE_CLASS_PIMA_MAX_PAYLOAD) +#define UX_DEVICE_CLASS_PIMA_ARRAY_BUFFER_SIZE (UX_DEVICE_CLASS_PIMA_MAX_PAYLOAD) +#define UX_DEVICE_CLASS_PIMA_DEVICE_PROP_VALUE_BUFFER_SIZE (UX_DEVICE_CLASS_PIMA_MAX_PAYLOAD) +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_VALUE_BUFFER_SIZE (UX_DEVICE_CLASS_PIMA_MAX_PAYLOAD) + +#define UX_DEVICE_CLASS_PIMA_CLASS_TRANSFER_TIMEOUT 300000 +#define UX_DEVICE_CLASS_PIMA_CLASS 0x06 +#define UX_DEVICE_CLASS_PIMA_SUBCLASS 0X01 +#define UX_DEVICE_CLASS_PIMA_PROTOCOL 0X01 +#define UX_DEVICE_CLASS_PIMA_MAGIC_NUMBER 0x50494D41 +#define UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH 256 +#define UX_DEVICE_CLASS_PIMA_DATE_TIME_STRING_MAX_LENGTH 64 +#define UX_DEVICE_CLASS_PIMA_MAX_EVENTS_QUEUE 16 +#define UX_DEVICE_CLASS_PIMA_MAX_STORAGE_IDS 1 +#define UX_DEVICE_CLASS_PIMA_ARRAY_MAX_LENGTH 256 +#define UX_DEVICE_CLASS_PIMA_DEVICE_PROPERTIES_ARRAY_MAX_ITEMS 32 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROPERTIES_ARRAY_MAX_ITEMS 128 +#define UX_DEVICE_CLASS_PIMA_PROP_VALUE_SIZE 256 +#define UX_DEVICE_CLASS_PIMA_MICROSOFT_VENDOR_COMMAND_CODE 0x54 + +/* Define PIMA versions. */ +#define UX_DEVICE_CLASS_PIMA_STANDARD_VERSION 100 +#define UX_DEVICE_CLASS_PIMA_VENDOR_EXTENSION_ID 6 +#define UX_DEVICE_CLASS_PIMA_EXTENSION_VERSION 100 +#define UX_DEVICE_CLASS_PIMA_STANDARD_MODE 0 + + +/* Define PIMA phases. */ + +#define UX_DEVICE_CLASS_PIMA_PHASE_IDLE 0 +#define UX_DEVICE_CLASS_PIMA_PHASE_COMMAND 1 +#define UX_DEVICE_CLASS_PIMA_PHASE_RESPONSE 2 +#define UX_DEVICE_CLASS_PIMA_PHASE_DATA_IN 3 +#define UX_DEVICE_CLASS_PIMA_PHASE_DATA_OUT 4 + +/* Define PIMA data phases. */ + +#define UX_DEVICE_CLASS_PIMA_DATA_PHASE_NONE 0 +#define UX_DEVICE_CLASS_PIMA_DATA_PHASE_IN 1 +#define UX_DEVICE_CLASS_PIMA_DATA_PHASE_OUT 2 + +/* Define PIMA session states. */ + +#define UX_DEVICE_CLASS_PIMA_SESSION_STATE_CLOSED 0 +#define UX_DEVICE_CLASS_PIMA_SESSION_STATE_OPENED 1 + +/* Define PIMA object and thumb states. */ + +#define UX_DEVICE_CLASS_PIMA_OBJECT_STATE_CLOSED 0 +#define UX_DEVICE_CLASS_PIMA_OBJECT_STATE_OPENED 1 + +/* Define PIMA object and thumb transfer status. */ + +#define UX_DEVICE_CLASS_PIMA_OBJECT_TRANSFER_STATUS_INACTIVE 0 +#define UX_DEVICE_CLASS_PIMA_OBJECT_TRANSFER_STATUS_ACTIVE 1 +#define UX_DEVICE_CLASS_PIMA_OBJECT_TRANSFER_STATUS_COMPLETED 2 +#define UX_DEVICE_CLASS_PIMA_OBJECT_TRANSFER_STATUS_ABORTED 3 + +/* Define PIMA object and thumb transfer phase. */ + +#define UX_DEVICE_CLASS_PIMA_OBJECT_TRANSFER_PHASE_ACTIVE 0 +#define UX_DEVICE_CLASS_PIMA_OBJECT_TRANSFER_PHASE_COMPLETED 1 +#define UX_DEVICE_CLASS_PIMA_OBJECT_TRANSFER_PHASE_COMPLETED_ERROR 2 + + +/* Define PIMA Cancel Request equivalences. */ + +#define UX_DEVICE_CLASS_PIMA_REQUEST_CANCEL_COMMAND 0x64 +#define UX_DEVICE_CLASS_PIMA_REQUEST_CANCEL_DATA_LENGTH 0x06 +#define UX_DEVICE_CLASS_PIMA_REQUEST_CANCEL_CODE 0x04001 +#define UX_DEVICE_CLASS_PIMA_REQUEST_CANCEL_OFFSET_CODE 0x00 +#define UX_DEVICE_CLASS_PIMA_REQUEST_CANCEL_OFFSET_TRANSACTION_ID 0x02 + +/* Define PIMA Reset Request equivalences. */ + +#define UX_DEVICE_CLASS_PIMA_REQUEST_RESET_DEVICE 0x66 + +/* Define PIMA Status Request equivalences. */ + +#define UX_DEVICE_CLASS_PIMA_REQUEST_STATUS_COMMAND 0x67 +#define UX_DEVICE_CLASS_PIMA_REQUEST_STATUS_DATA_LENGTH 0x40 +#define UX_DEVICE_CLASS_PIMA_REQUEST_STATUS_OFFSET_LENGTH 0x00 +#define UX_DEVICE_CLASS_PIMA_REQUEST_STATUS_OFFSET_CODE 0x02 +#define UX_DEVICE_CLASS_PIMA_REQUEST_STATUS_COMMAND_COUNTER 16 +#define UX_DEVICE_CLASS_PIMA_REQUEST_STATUS_COMMAND_DELAY (1 * UX_PERIODIC_RATE) + +/* Define PIMA command container type. */ + +#define UX_DEVICE_CLASS_PIMA_CT_UNDEFINED 0x00 +#define UX_DEVICE_CLASS_PIMA_CT_COMMAND_BLOCK 0x01 +#define UX_DEVICE_CLASS_PIMA_CT_DATA_BLOCK 0x02 +#define UX_DEVICE_CLASS_PIMA_CT_RESPONSE_BLOCK 0x03 +#define UX_DEVICE_CLASS_PIMA_CT_EVENT_BLOCK 0x04 + +/* Define PIMA Extended Event Data Request payload Format. */ + +#define UX_DEVICE_CLASS_PIMA_EEDR_EVENT_CODE 0x00 +#define UX_DEVICE_CLASS_PIMA_EEDR_TRANSACTION_ID 0x02 +#define UX_DEVICE_CLASS_PIMA_EEDR_NUMBER_PARAMETERS 0x06 +#define UX_DEVICE_CLASS_PIMA_EEDR_SIZE_PARAMETER 0x08 + +/* Define PIMA Device Status Data Format. */ + +#define UX_DEVICE_CLASS_PIMA_DSD_LENGTH 0x00 +#define UX_DEVICE_CLASS_PIMA_DSD_CODE 0x02 +#define UX_DEVICE_CLASS_PIMA_DSD_PARAMETER 0x04 + +/* Define PIMA Command Header Format. */ + +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_LENGTH 0x00 +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_TYPE 0x04 +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_CODE 0x06 +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_TRANSACTION_ID 0x08 +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_PARAMETER_1 0x0C +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_PARAMETER_2 0x10 +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_PARAMETER_3 0x14 +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_PARAMETER_4 0x18 +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_PARAMETER_5 0x1C + +#define UX_DEVICE_CLASS_PIMA_COMMAND_HEADER_SIZE 0x0C +#define UX_DEVICE_CLASS_PIMA_CONTAINER_SIZE 0x40 +#define UX_DEVICE_CLASS_PIMA_ALL_HEADER_SIZE 0x20 + +/* Define PIMA Data Header Format. */ + +#define UX_DEVICE_CLASS_PIMA_DATA_HEADER_LENGTH 0x00 +#define UX_DEVICE_CLASS_PIMA_DATA_HEADER_TYPE 0x04 +#define UX_DEVICE_CLASS_PIMA_DATA_HEADER_CODE 0x06 +#define UX_DEVICE_CLASS_PIMA_DATA_HEADER_TRANSACTION_ID 0x08 +#define UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE 0x0C + + +/* Define PIMA Response Header Format. */ + +#define UX_DEVICE_CLASS_PIMA_RESPONSE_HEADER_LENGTH 0x00 +#define UX_DEVICE_CLASS_PIMA_RESPONSE_HEADER_TYPE 0x04 +#define UX_DEVICE_CLASS_PIMA_RESPONSE_HEADER_CODE 0x06 +#define UX_DEVICE_CLASS_PIMA_RESPONSE_HEADER_TRANSACTION_ID 0x08 +#define UX_DEVICE_CLASS_PIMA_RESPONSE_HEADER_PARAMETERS 0x0C +#define UX_DEVICE_CLASS_PIMA_RESPONSE_HEADER_SIZE 0x0C + +/* Define PIMA Asynchronous Event Interrupt Data Format. */ + +#define UX_DEVICE_CLASS_PIMA_AEI_DATA_LENGTH 0x00 +#define UX_DEVICE_CLASS_PIMA_AEI_TYPE 0x04 +#define UX_DEVICE_CLASS_PIMA_AEI_EVENT_CODE 0x06 +#define UX_DEVICE_CLASS_PIMA_AEI_TRANSACTION_ID 0x08 +#define UX_DEVICE_CLASS_PIMA_AEI_PARAMETER_1 0x0C +#define UX_DEVICE_CLASS_PIMA_AEI_PARAMETER_2 0x10 +#define UX_DEVICE_CLASS_PIMA_AEI_PARAMETER_3 0x14 +#define UX_DEVICE_CLASS_PIMA_AEI_MAX_LENGTH 0x18 + +/* Define PIMA Operation Commands. */ + +#define UX_DEVICE_CLASS_PIMA_OC_UNDEFINED 0x1000 +#define UX_DEVICE_CLASS_PIMA_OC_GET_DEVICE_INFO 0x1001 +#define UX_DEVICE_CLASS_PIMA_OC_OPEN_SESSION 0x1002 +#define UX_DEVICE_CLASS_PIMA_OC_CLOSE_SESSION 0x1003 +#define UX_DEVICE_CLASS_PIMA_OC_GET_STORAGE_IDS 0x1004 +#define UX_DEVICE_CLASS_PIMA_OC_GET_STORAGE_INFO 0x1005 +#define UX_DEVICE_CLASS_PIMA_OC_GET_NUM_OBJECTS 0x1006 +#define UX_DEVICE_CLASS_PIMA_OC_GET_OBJECT_HANDLES 0x1007 +#define UX_DEVICE_CLASS_PIMA_OC_GET_OBJECT_INFO 0x1008 +#define UX_DEVICE_CLASS_PIMA_OC_GET_OBJECT 0x1009 +#define UX_DEVICE_CLASS_PIMA_OC_GET_THUMB 0x100A +#define UX_DEVICE_CLASS_PIMA_OC_DELETE_OBJECT 0x100B +#define UX_DEVICE_CLASS_PIMA_OC_SEND_OBJECT_INFO 0x100C +#define UX_DEVICE_CLASS_PIMA_OC_SEND_OBJECT 0x100D +#define UX_DEVICE_CLASS_PIMA_OC_INITIATE_CAPTURE 0x100E +#define UX_DEVICE_CLASS_PIMA_OC_FORMAT_STORE 0x100F +#define UX_DEVICE_CLASS_PIMA_OC_RESET_DEVICE 0x1010 +#define UX_DEVICE_CLASS_PIMA_OC_SELF_TEST 0x1011 +#define UX_DEVICE_CLASS_PIMA_OC_SET_OBJECT_PROTECTION 0x1012 +#define UX_DEVICE_CLASS_PIMA_OC_POWER_DOWN 0x1013 +#define UX_DEVICE_CLASS_PIMA_OC_GET_DEVICE_PROP_DESC 0x1014 +#define UX_DEVICE_CLASS_PIMA_OC_GET_DEVICE_PROP_VALUE 0x1015 +#define UX_DEVICE_CLASS_PIMA_OC_SET_DEVICE_PROP_VALUE 0x1016 +#define UX_DEVICE_CLASS_PIMA_OC_RESET_DEVICE_PROP_VALUE 0x1017 +#define UX_DEVICE_CLASS_PIMA_OC_TERMINATE_OPEN_CAPTURE 0x1018 +#define UX_DEVICE_CLASS_PIMA_OC_MOVE_OBJECT 0x1019 +#define UX_DEVICE_CLASS_PIMA_OC_COPY_OBJECT 0x101A +#define UX_DEVICE_CLASS_PIMA_OC_GET_PARTIAL_OBJECT 0x101B +#define UX_DEVICE_CLASS_PIMA_OC_INITIATE_OPEN_CAPTURE 0x101C +#define UX_DEVICE_CLASS_PIMA_OC_GET_OBJECT_PROPS_SUPPORTED 0x9801 +#define UX_DEVICE_CLASS_PIMA_OC_GET_OBJECT_PROP_DESC 0x9802 +#define UX_DEVICE_CLASS_PIMA_OC_GET_OBJECT_PROP_VALUE 0x9803 +#define UX_DEVICE_CLASS_PIMA_OC_SET_OBJECT_PROP_VALUE 0x9804 +#define UX_DEVICE_CLASS_PIMA_OC_GET_OBJECT_REFERENCES 0x9810 +#define UX_DEVICE_CLASS_PIMA_OC_SET_OBJECT_REFERENCES 0x9811 + +/* Define PIMA Response Codes. */ + +#define UX_DEVICE_CLASS_PIMA_RC_UNDEFINED 0x2000 +#define UX_DEVICE_CLASS_PIMA_RC_OK 0x2001 +#define UX_DEVICE_CLASS_PIMA_RC_GENERAL_ERROR 0x2002 +#define UX_DEVICE_CLASS_PIMA_RC_SESSION_NOT_OPEN 0x2003 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_TRANSACTION_ID 0x2004 +#define UX_DEVICE_CLASS_PIMA_RC_OPERATION_NOT_SUPPORTED 0x2005 +#define UX_DEVICE_CLASS_PIMA_RC_PARAMETER_NOT_SUPPORTED 0x2006 +#define UX_DEVICE_CLASS_PIMA_RC_INCOMPLETE_TRANSFER 0x2007 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_STORAGE_ID 0x2008 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_OBJECT_HANDLE 0x2009 +#define UX_DEVICE_CLASS_PIMA_RC_DEVICE_PROP_NOT_SUPPORTED 0x200A +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_OBJECT_FORMAT_CODE 0x200B +#define UX_DEVICE_CLASS_PIMA_RC_STORE_FULL 0x200C +#define UX_DEVICE_CLASS_PIMA_RC_OBJECT_WRITE_PROTECTED 0x200D +#define UX_DEVICE_CLASS_PIMA_RC_STORE_READ_ONLY 0x200E +#define UX_DEVICE_CLASS_PIMA_RC_ACCESS_DENIED 0x200F +#define UX_DEVICE_CLASS_PIMA_RC_NO_THUMBNAIL_PRESENT 0x2010 +#define UX_DEVICE_CLASS_PIMA_RC_SELF_TEST_FAILED 0x2011 +#define UX_DEVICE_CLASS_PIMA_RC_PARTIAL_DELETION 0x2012 +#define UX_DEVICE_CLASS_PIMA_RC_STORE_NOT_AVAILABLE 0x2013 +#define UX_DEVICE_CLASS_PIMA_RC_FORMAT_UNSUPPORTED 0x2014 +#define UX_DEVICE_CLASS_PIMA_RC_NO_VALID_OBJECT_INFO 0x2015 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_CODE_FORMAT 0x2016 +#define UX_DEVICE_CLASS_PIMA_RC_UNKNOWN_VENDOR_CODE 0x2017 +#define UX_DEVICE_CLASS_PIMA_RC_CAPTURE_ALREADY_TERMINATED 0x2018 +#define UX_DEVICE_CLASS_PIMA_RC_DEVICE_BUSY 0x2019 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_PARENT_OBJECT 0x201A +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_DEVICE_PROP_FORMAT 0x201B +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_DEVICE_PROP_VALUE 0x201C +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_PARAMETER 0x201D +#define UX_DEVICE_CLASS_PIMA_RC_SESSION_ALREADY_OPENED 0x201E +#define UX_DEVICE_CLASS_PIMA_RC_TRANSACTION_CANCELED 0x201F +#define UX_DEVICE_CLASS_PIMA_RC_DESTINATION_UNSUPPORTED 0x2020 +#define UX_DEVICE_CLASS_PIMA_RC_OBJECT_ALREADY_OPENED 0x2021 +#define UX_DEVICE_CLASS_PIMA_RC_OBJECT_ALREADY_CLOSED 0x2022 +#define UX_DEVICE_CLASS_PIMA_RC_OBJECT_NOT_OPENED 0x2023 + +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_OBJECT_PROP_CODE 0xA801 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_OBJECT_PROP_FORMAT 0xA802 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_OBJECT_PROP_VALUE 0xA803 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_OBJECT_REFERENCE 0xA804 +#define UX_DEVICE_CLASS_PIMA_RC_INVALID_DATASET 0xA806 +#define UX_DEVICE_CLASS_PIMA_RC_SPECIFICATION_BY_GROUP_UNSUPPORTED 0xA807 +#define UX_DEVICE_CLASS_PIMA_RC_SPECIFICATION_BY_DEPTH_UNSUPPORTED 0xA808 +#define UX_DEVICE_CLASS_PIMA_RC_OBJECT_TOO_LARGE 0xA809 +#define UX_DEVICE_CLASS_PIMA_RC_OBJECT_PROP_NOT_SUPPORTED 0xA80A + +/* Define PIMA Event Codes. */ + +#define UX_DEVICE_CLASS_PIMA_EC_UNDEFINED 0x4000 +#define UX_DEVICE_CLASS_PIMA_EC_CANCEL_TRANSACTION 0x4001 +#define UX_DEVICE_CLASS_PIMA_EC_OBJECT_ADDED 0x4002 +#define UX_DEVICE_CLASS_PIMA_EC_OBJECT_REMOVED 0x4003 +#define UX_DEVICE_CLASS_PIMA_EC_STORE_ADDED 0x4004 +#define UX_DEVICE_CLASS_PIMA_EC_STORE_REMOVED 0x4005 +#define UX_DEVICE_CLASS_PIMA_EC_DEVICE_PROP_CHANGED 0x4006 +#define UX_DEVICE_CLASS_PIMA_EC_OBJECT_INFO_CHANGED 0x4007 +#define UX_DEVICE_CLASS_PIMA_EC_DEVICE_INFO_CHANGED 0x4008 +#define UX_DEVICE_CLASS_PIMA_EC_REQUEST_OBJECT_TRANSFER 0x4009 +#define UX_DEVICE_CLASS_PIMA_EC_STORE_FULL 0x400A +#define UX_DEVICE_CLASS_PIMA_EC_DEVICE_RESET 0x400B +#define UX_DEVICE_CLASS_PIMA_EC_STORAGE_INFO_CHANGED 0x400C +#define UX_DEVICE_CLASS_PIMA_EC_CAPTURE_COMPLETE 0x400D +#define UX_DEVICE_CLASS_PIMA_EC_UNREPORTED_STATUS 0x400E + +/* Define PIMA Object Format Codes. */ + +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED 0x3000 +#define UX_DEVICE_CLASS_PIMA_OFC_ASSOCIATION 0x3001 +#define UX_DEVICE_CLASS_PIMA_OFC_SCRIPT 0x3002 +#define UX_DEVICE_CLASS_PIMA_OFC_EXECUTABLE 0x3003 +#define UX_DEVICE_CLASS_PIMA_OFC_TEXT 0x3004 +#define UX_DEVICE_CLASS_PIMA_OFC_HTML 0x3005 +#define UX_DEVICE_CLASS_PIMA_OFC_DPOF 0x3006 +#define UX_DEVICE_CLASS_PIMA_OFC_AIFF 0x3007 +#define UX_DEVICE_CLASS_PIMA_OFC_WAV 0x3008 +#define UX_DEVICE_CLASS_PIMA_OFC_MP3 0x3009 +#define UX_DEVICE_CLASS_PIMA_OFC_AVI 0x300A +#define UX_DEVICE_CLASS_PIMA_OFC_MPEG 0x300B +#define UX_DEVICE_CLASS_PIMA_OFC_ASF 0x300C +#define UX_DEVICE_CLASS_PIMA_OFC_DEFINED 0x3800 +#define UX_DEVICE_CLASS_PIMA_OFC_EXIF_JPEG 0x3801 +#define UX_DEVICE_CLASS_PIMA_OFC_TIFF_EP 0x3802 +#define UX_DEVICE_CLASS_PIMA_OFC_FLASHPIX 0x3803 +#define UX_DEVICE_CLASS_PIMA_OFC_BMP 0x3804 +#define UX_DEVICE_CLASS_PIMA_OFC_CIFF 0x3805 +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_2 0x3806 +#define UX_DEVICE_CLASS_PIMA_OFC_GIF 0x3807 +#define UX_DEVICE_CLASS_PIMA_OFC_JFIF 0x3808 +#define UX_DEVICE_CLASS_PIMA_OFC_CD 0x3809 +#define UX_DEVICE_CLASS_PIMA_OFC_PICT 0x380A +#define UX_DEVICE_CLASS_PIMA_OFC_PNG 0x380B +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_3 0x380C +#define UX_DEVICE_CLASS_PIMA_OFC_TIFF 0x380D +#define UX_DEVICE_CLASS_PIMA_OFC_TIFF_IT 0x380E +#define UX_DEVICE_CLASS_PIMA_OFC_JP2 0x380F +#define UX_DEVICE_CLASS_PIMA_OFC_JPX 0x3810 +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_FIRMWARE 0xB802 +#define UX_DEVICE_CLASS_PIMA_OFC_WINDOWS_IMAGE_FORMAT 0xB881 +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_AUDIO 0xB900 +#define UX_DEVICE_CLASS_PIMA_OFC_WMA 0xB901 +#define UX_DEVICE_CLASS_PIMA_OFC_OGG 0xB902 +#define UX_DEVICE_CLASS_PIMA_OFC_AAC 0xB903 +#define UX_DEVICE_CLASS_PIMA_OFC_AUDIBLE 0xB904 +#define UX_DEVICE_CLASS_PIMA_OFC_FLAC 0xB906 +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_VIDEO 0xB980 +#define UX_DEVICE_CLASS_PIMA_OFC_WMV 0xB981 +#define UX_DEVICE_CLASS_PIMA_OFC_MP4_CONTAINER 0xB982 +#define UX_DEVICE_CLASS_PIMA_OFC_MP2 0xB983 +#define UX_DEVICE_CLASS_PIMA_OFC_3GP_CONTAINER 0xB984 +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_COLLECTION 0xBA00 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_MULTIMEDIA_ALBUM 0xBA01 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_IMAGE_ALBUM 0xBA02 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_AUDIO_ALBUM 0xBA03 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_VIDEO_ALBUM 0xBA04 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_AUDIO_AND_VIDEO_PLAYLIST 0xBA05 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_CONTACT_GROUP 0xBA06 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_MESSAGE_FOLDER 0xBA07 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_CHAPTERED_PRODUCTION 0xBA08 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_AUDIO_PLAYLIST 0xBA09 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_VIDEO_PLAYLIST 0xBA0A +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_MEDIACAST 0xBA0B +#define UX_DEVICE_CLASS_PIMA_OFC_WPL_PLAYLIST 0xBA10 +#define UX_DEVICE_CLASS_PIMA_OFC_M3U_PLAYLIST 0xBA11 +#define UX_DEVICE_CLASS_PIMA_OFC_MPL_PLAYLIST 0xBA12 +#define UX_DEVICE_CLASS_PIMA_OFC_ASX_PLAYLIST 0xBA13 +#define UX_DEVICE_CLASS_PIMA_OFC_PLS_PLAYLIST 0xBA14 +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_DOCUMENT 0xBA80 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_DOCUMENT 0xBA81 +#define UX_DEVICE_CLASS_PIMA_OFC_XML_DOCUMENT 0xBA82 +#define UX_DEVICE_CLASS_PIMA_OFC_MICROSOFT_WORD_DOCUMENT 0xBA83 +#define UX_DEVICE_CLASS_PIMA_OFC_MHT_COMPILED_HTML_DOCUMENT 0xBA84 +#define UX_DEVICE_CLASS_PIMA_OFC_MICROSOFT_EXCEL_SPREADSHEET 0xBA85 +#define UX_DEVICE_CLASS_PIMA_OFC_MICROSOFT_POWERPOINT_PRESENTATION 0xBA86 +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_MESSAGE 0xBB00 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_MESSAGE 0xBB01 +#define UX_DEVICE_CLASS_PIMA_OFC_UNDEFINED_CONTACT 0xBB80 +#define UX_DEVICE_CLASS_PIMA_OFC_ABSTRACT_CONTACT 0xBB81 +#define UX_DEVICE_CLASS_PIMA_OFC_VCARD2 0xBB82 + +/* Define PIMA Device Format Codes. */ + +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_UNDEFINED 0x5000 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_BATTERY_LEVEL 0x5001 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_FUNCTIONAL_MODE 0x5002 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_IMAGE_SIZE 0x5003 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_COMPRESSION_SETTING 0x5004 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_WHITE_BALANCE 0x5005 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_RGB_GAIN 0x5006 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_F_NUMBER 0x5007 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_FOCAL_LENGTH 0x5008 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_FOCUS_DISTANCE 0x5009 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_FOCUS_MODE 0x500A +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_EXPOSURE_METERING_MODE 0x500B +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_FLASH_MODE 0x500C +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_EXPOSURE_TIME 0x500D +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_EXPOSURE_PROGRAM_MODE 0x500E +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_EXPOSURE_INDEX 0x500F +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_EXPOSURE_BIAS_COMPENSATION 0x5010 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_DATE_TIME 0x5011 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_CAPTURE_DELAY 0x5012 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_STILL_CAPTURE_MODE 0x5013 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_CONTRAST 0x5014 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_SHARPNESS 0x5015 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_DIGITAL_ZOOM 0x5016 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_EFFECT_MODE 0x5017 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_BURST_NUMBER 0x5018 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_BURST_INTERVAL 0x5019 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_TIME_LAPSE_NUMBER 0x501A +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_TIME_LAPSE_INTERVAL 0x501B +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_FOCUS_METERING_MODE 0x501C +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_UPLOAD_URL 0x501D +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_ARTIST 0x501E +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_COPYRIGHT_INFO 0x501F +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_SYNCHRONIZATION_PARTNER 0xD401 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_DEVICE_FRIENDLY_NAME 0xD402 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_VOLUME 0xD403 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_SUPPORTED_FORMATS_ORDERED 0xD404 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_DEVICE_ICON 0xD405 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_PLAYBACK_RATE 0xD410 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_PLAYBACK_OBJECT 0xD411 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_PLAYBACK_CONTAINER 0xD412 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_SESSION_INITIATOR_VERSION_INFO 0xD406 +#define UX_DEVICE_CLASS_PIMA_DEV_PROP_PERCEIVED_DEVICE_TYPE 0xD407 + +/* Define PIMA Object Format Codes. */ + +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_STORAGEID 0xDC01 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_OBJECT_FORMAT 0xDC02 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PROTECTION_STATUS 0xDC03 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_OBJECT_SIZE 0xDC04 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ASSOCIATION_TYPE 0xDC05 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ASSOCIATION_DESC 0xDC06 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_OBJECT_FILE_NAME 0xDC07 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_DATE_CREATED 0xDC08 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_DATE_MODIFIED 0xDC09 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_KEYWORDS 0xDC0A +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PARENT_OBJECT 0xDC0B +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ALLOWED_FOLDER_CONTENTS 0xDC0C +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_HIDDEN 0xDC0D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SYSTEM_OBJECT 0xDC0E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PERSISTENT_UNIQUE_OBJECT_IDENTIFIER 0xDC41 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SYNCID 0xDC42 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PROPERTY_BAG 0xDC43 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_NAME 0xDC44 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_CREATED_BY 0xDC45 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ARTIST 0xDC46 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_DATE_AUTHORED 0xDC47 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_DESCRIPTION 0xDC48 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_URL_REFERENCE 0xDC49 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_LANGUAGE_LOCALE 0xDC4A +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_COPYRIGHT_INFORMATION 0xDC4B +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SOURCE 0xDC4C +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ORIGIN_LOCATION 0xDC4D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_DATE_ADDED 0xDC4E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_NON_CONSUMABLE 0xDC4F +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_CORRUPT_UNPLAYABLE 0xDC50 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PRODUCER_SERIA_LNUMBER 0xDC51 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_REPRESENTATIVE_SAMPLE_FORMAT 0xDC81 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_REPRESENTATIVE_SAMPLE_SIZE 0xDC82 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_REPRESENTATIVE_SAMPLE_HEIGHT 0xDC83 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_REPRESENTATIVE_SAMPLE_WIDTH 0xDC84 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_REPRESENTATIVE_SAMPLE_DURATION 0xDC85 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_REPRESENTATIVE_SAMPLE_DATA 0xDC86 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_WIDTH 0xDC87 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_HEIGHT 0xDC88 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_DURATION 0xDC89 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_RATING 0xDC8A +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_TRACK 0xDC8B +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_GENRE 0xDC8C +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_CREDITS 0xDC8D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_LYRICS 0xDC8E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SUBSCRIPTION_CONTENT_ID 0xDC8F +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PRODUCED_BY 0xDC90 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_USE_COUNT 0xDC91 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SKIP_COUNT 0xDC92 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_LAST_ACCESSED 0xDC93 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PARENTAL_RATING 0xDC94 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_META_GENRE 0xDC95 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_COMPOSER 0xDC96 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EFFECTIVE_RATING 0xDC97 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SUBTITLE 0xDC98 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ORIGINAL_RELEASE_DATE 0xDC99 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ALBUM_NAME 0xDC9A +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ALBUM_ARTIST 0xDC9B +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MOOD 0xDC9C +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_DRM_STATUS 0xDC9D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SUB_DESCRIPTION 0xDC9E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_IS_CROPPED 0xDCD1 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_IS_COLOUR_CORRECTED 0xDCD2 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_IMAGE_BIT_DEPTH 0xDCD3 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_FNUMBER 0xDCD4 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EXPOSURE_TIME 0xDCD5 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EXPOSURE_INDEX 0xDCD6 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_TOTAL_BITRATE 0xDE91 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_BITRATE_TYPE 0xDE92 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SAMPLE_RATE 0xDE93 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_NUMBER_OF_CHANNELS 0xDE94 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_AUDIO_BITDEPTH 0xDE95 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SCAN_TYPE 0xDE97 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_AUDIO_WAVE_CODEC 0xDE99 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_AUDIO_BITRATE 0xDE9A +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_VIDEO_FOURCC_CODEC 0xDE9B +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_VIDEO_BITRATE 0xDE9C +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_FRAMES_PER_THOUSAND_SECONDS 0xDE9D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_KEYFRAME_DISTANCE 0xDE9E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_BUFFER_SIZE 0xDE9F +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ENCODING_QUALITY 0xDEA0 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ENCODING_PROFILE 0xDEA1 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_DISPLAY_NAME 0xDCE0 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_BODY_TEXT 0xDCE1 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SUBJECT 0xDCE2 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PRIORITY 0xDCE3 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_GIVEN_NAME 0xDD00 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MIDDLE_NAMES 0xDD01 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_FAMILY_NAME 0xDD02 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PREFIX 0xDD03 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_SUFFIX 0xDD04 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONETIC_GIVEN_NAME 0xDD05 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONETIC_FAMILY_NAME 0xDD06 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EMAIL_PRIMARY 0xDD07 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EMAIL_PERSONAL_1 0xDD08 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EMAIL_PERSONAL_2 0xDD09 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EMAIL_BUSINESS_1 0xDD0A +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EMAIL_BUSINESS_2 0xDD0B +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EMAIL_OTHERS 0xDD0C +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONE_NUMBER_PRIMARY 0xDD0D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONE_NUMBER_PERSONAL 0xDD0E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONE_NUMBER_PERSONAL_2 0xDD0F +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONE_NUMBER_BUSINESS 0xDD10 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONE_NUMBER_BUSINESS_2 0xDD11 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONE_NUMBER_MOBILE 0xDD12 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONE_NUMBER_MOBILE_2 0xDD13 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_FAX_NUMBER_PRIMARY 0xDD14 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_FAX_NUMBER_PERSONAL 0xDD15 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_FAX_NUMBER_BUSINESS 0xDD16 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PAGER_NUMBER 0xDD17 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONE_NUMBER_OTHERS 0xDD18 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PRIMARY_WEB_ADDRESS 0xDD19 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PERSONAL_WEB_ADDRESS 0xDD1A +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_BUSINESS_WEB_ADDRESS 0xDD1B +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_INSTANT_MESSENGER_ADDRESS 0xDD1C +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_INSTANT_MESSENGER_ADDRESS_2 0xDD1D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_INSTANT_MESSENGER_ADDRESS_3 0xDD1E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_PERSONAL_FULL 0xDD1F +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_PERSONAL_LINE_1 0xDD20 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_PERSONAL_LINE_2 0xDD21 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_PERSONAL_CITY 0xDD22 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_PERSONAL_REGION 0xDD23 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_PERSONAL_POSTAL_CODE 0xDD24 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_PERSONAL_COUNTRY 0xDD25 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_BUSINESS_FULL 0xDD26 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_BUSINESS_LINE_1 0xDD27 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_BUSINESS_LINE_2 0xDD28 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_BUSINESS_CITY 0xDD29 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_BUSINESS_REGION 0xDD2A +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_BUSINESS_POSTAL_CODE 0xDD2B +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_BUSINESS_COUNTRY 0xDD2C +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_OTHER_FULL 0xDD2D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_OTHER_LINE_1 0xDD2E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_OTHER_LINE_2 0xDD2F +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_OTHER_CITY 0xDD30 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_OTHER_REGION 0xDD31 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_OTHER_POSTAL_CODE 0xDD32 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_POSTAL_ADDRESS_OTHER_COUNTRY 0xDD33 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ORGANIZATION_NAME 0xDD34 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_PHONETIC_ORGANIZATION_NAME 0xDD35 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ROLE 0xDD36 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_BIRTHDATE 0xDD37 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MESSAGE_TO 0xDD40 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MESSAGE_CC 0xDD41 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MESSAGE_BCC 0xDD42 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MESSAGE_READ 0xDD43 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MESSAGE_RECEIVED_TIME 0xDD44 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MESSAGE_SENDER 0xDD45 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ACTIVITY_BEGIN_TIME 0xDD50 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ACTIVITY_END_TIME 0xDD51 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ACTIVITY_LOCATION 0xDD52 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ACTIVITY_REQUIRED_ATTENDEES 0xDD54 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ACTIVITY_OPTIONAL_ATTENDEES 0xDD55 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ACTIVITY_RESOURCES 0xDD56 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_ACTIVITY_ACCEPTED 0xDD57 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_OWNER 0xDD5D +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_EDITOR 0xDD5E +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_WEBMASTER 0xDD5F +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_URL_SOURCE 0xDD60 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_URL_DESTINATION 0xDD61 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_TIME_BOOKMARK 0xDD62 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_OBJECT_BOOKMARK 0xDD63 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_BYTE_BOOKMARK 0xDD64 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_LAST_BUILD_DATE 0xDD70 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_TIME_TO_LIVE 0xDD71 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROP_MEDIA_GUID 0xDD72 + +/* Define PIMA Object Protection Status Values. */ + +#define UX_DEVICE_CLASS_PIMA_OPS_NO_PROTECTION 0x0000 +#define UX_DEVICE_CLASS_PIMA_OPS_READ_ONLY 0x0001 + +/* Define PIMA Storage Types Codes. */ + +#define UX_DEVICE_CLASS_PIMA_STC_UNDEFINED 0x0000 +#define UX_DEVICE_CLASS_PIMA_STC_FIXED_ROM 0x0001 +#define UX_DEVICE_CLASS_PIMA_STC_REMOVABLE_ROM 0x0002 +#define UX_DEVICE_CLASS_PIMA_STC_FIXED_RAM 0x0003 +#define UX_DEVICE_CLASS_PIMA_STC_REMOVABLE_RAM 0x0004 + +/* Define PIMA File System Types Codes. */ + +#define UX_DEVICE_CLASS_PIMA_FSTC_UNDEFINED 0x0000 +#define UX_DEVICE_CLASS_PIMA_FSTC_GENERIC_FLAT 0x0001 +#define UX_DEVICE_CLASS_PIMA_FSTC_GENERIC_HIERARCHICAL 0x0002 +#define UX_DEVICE_CLASS_PIMA_FSTC_DCF 0x0003 + +/* Define PIMA File System Access Types Codes. */ + +#define UX_DEVICE_CLASS_PIMA_AC_READ_WRITE 0x0000 +#define UX_DEVICE_CLASS_PIMA_AC_RO_WITHOUT_OBJECT_DELETION 0x0001 +#define UX_DEVICE_CLASS_PIMA_AC_RO_WITH_OBJECT_DELETION 0x0002 + +/* Define PIMA types. */ +#define UX_DEVICE_CLASS_PIMA_TYPES_INT8 0x0001 +#define UX_DEVICE_CLASS_PIMA_TYPES_UINT8 0x0002 +#define UX_DEVICE_CLASS_PIMA_TYPES_INT16 0x0003 +#define UX_DEVICE_CLASS_PIMA_TYPES_UINT16 0x0004 +#define UX_DEVICE_CLASS_PIMA_TYPES_INT32 0x0005 +#define UX_DEVICE_CLASS_PIMA_TYPES_UINT32 0x0006 +#define UX_DEVICE_CLASS_PIMA_TYPES_INT64 0x0007 +#define UX_DEVICE_CLASS_PIMA_TYPES_UINT64 0x0008 +#define UX_DEVICE_CLASS_PIMA_TYPES_INT128 0x0009 +#define UX_DEVICE_CLASS_PIMA_TYPES_UINT128 0x000A +#define UX_DEVICE_CLASS_PIMA_TYPES_AINT8 0x4001 +#define UX_DEVICE_CLASS_PIMA_TYPES_AUINT8 0x4002 +#define UX_DEVICE_CLASS_PIMA_TYPES_AINT16 0x4003 +#define UX_DEVICE_CLASS_PIMA_TYPES_AUINT16 0x4004 +#define UX_DEVICE_CLASS_PIMA_TYPES_AINT32 0x4005 +#define UX_DEVICE_CLASS_PIMA_TYPES_AUINT32 0x4006 +#define UX_DEVICE_CLASS_PIMA_TYPES_AINT64 0x4007 +#define UX_DEVICE_CLASS_PIMA_TYPES_AUINT64 0x4008 +#define UX_DEVICE_CLASS_PIMA_TYPES_AINT128 0x4009 +#define UX_DEVICE_CLASS_PIMA_TYPES_AUINT128 0x400A +#define UX_DEVICE_CLASS_PIMA_TYPES_STR 0xFFFF + +/* Define PIMA Device Info fields. */ + +#define UX_DEVICE_CLASS_PIMA_DEVICE_INFO_STANDARD_VERSION (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 0x0000) +#define UX_DEVICE_CLASS_PIMA_DEVICE_INFO_VENDOR_EXTENSION_ID (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 0x0002) +#define UX_DEVICE_CLASS_PIMA_DEVICE_INFO_VENDOR_EXTENSION_VERSION (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 0x0006) +#define UX_DEVICE_CLASS_PIMA_DEVICE_INFO_VENDOR_EXTENSION_DESC (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 0x0008) + +/* Define PIMA MTP OBJECT PROPERTY DATASET. */ +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROPERTY_DATASET_CODE 0x0000 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROPERTY_DATASET_DATATYPE 0x0002 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROPERTY_DATASET_GETSET 0x0004 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROPERTY_DATASET_VALUE 0x0005 + +/* Define PIMA Dataset equivalences. */ +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROPERTY_DATASET_VALUE_GET 0x00 +#define UX_DEVICE_CLASS_PIMA_OBJECT_PROPERTY_DATASET_VALUE_GETSET 0x01 + +/* Define PIMA event info structure. */ + +typedef struct UX_SLAVE_CLASS_PIMA_EVENT_STRUCT +{ + ULONG ux_device_class_pima_event_code; + ULONG ux_device_class_pima_event_session_id; + ULONG ux_device_class_pima_event_transaction_id; + ULONG ux_device_class_pima_event_parameter_1; + ULONG ux_device_class_pima_event_parameter_2; + ULONG ux_device_class_pima_event_parameter_3; + +} UX_SLAVE_CLASS_PIMA_EVENT; + +/* Define PIMA object info structure. */ + +typedef struct UX_SLAVE_CLASS_PIMA_OBJECT_STRUCT +{ + + ULONG ux_device_class_pima_object_storage_id; + ULONG ux_device_class_pima_object_format; + ULONG ux_device_class_pima_object_protection_status; + ULONG ux_device_class_pima_object_compressed_size; + ULONG ux_device_class_pima_object_thumb_format; + ULONG ux_device_class_pima_object_thumb_compressed_size; + ULONG ux_device_class_pima_object_thumb_pix_width; + ULONG ux_device_class_pima_object_thumb_pix_height; + ULONG ux_device_class_pima_object_image_pix_width; + ULONG ux_device_class_pima_object_image_pix_height; + ULONG ux_device_class_pima_object_image_bit_depth; + ULONG ux_device_class_pima_object_parent_object; + ULONG ux_device_class_pima_object_association_type; + ULONG ux_device_class_pima_object_association_desc; + ULONG ux_device_class_pima_object_sequence_number; + UCHAR ux_device_class_pima_object_filename[UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH]; + UCHAR ux_device_class_pima_object_capture_date[UX_DEVICE_CLASS_PIMA_DATE_TIME_STRING_MAX_LENGTH]; + UCHAR ux_device_class_pima_object_modification_date[UX_DEVICE_CLASS_PIMA_DATE_TIME_STRING_MAX_LENGTH]; + UCHAR ux_device_class_pima_object_keywords[UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH]; + ULONG ux_device_class_pima_object_state; + ULONG ux_device_class_pima_object_offset; + ULONG ux_device_class_pima_object_transfer_status; + ULONG ux_device_class_pima_object_handle_id; + ULONG ux_device_class_pima_object_length; + UCHAR *ux_device_class_pima_object_buffer; + +} UX_SLAVE_CLASS_PIMA_OBJECT; + +#define UX_SLAVE_CLASS_PIMA_OBJECT_DATA_LENGTH ((15 * sizeof(ULONG)) + \ + UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH + \ + UX_DEVICE_CLASS_PIMA_DATE_TIME_STRING_MAX_LENGTH + \ + UX_DEVICE_CLASS_PIMA_DATE_TIME_STRING_MAX_LENGTH + \ + UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH) + +/* Define PIMA session info structure. Not used in the device. Here for structure compatibility. */ + +typedef struct UX_SLAVE_CLASS_PIMA_SESSION_STRUCT +{ + + ULONG ux_device_class_pima_session_id; + +} UX_SLAVE_CLASS_PIMA_SESSION; + +/* Define PIMA device info structure. */ + +typedef struct UX_SLAVE_CLASS_PIMA_DEVICE_STRUCT +{ + + ULONG ux_device_class_pima_device_standard_version; + ULONG ux_device_class_pima_device_vendor_extension_id; + ULONG ux_device_class_pima_device_vendor_extension_version; + UCHAR ux_device_class_pima_device_vendor_extension_desc[UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH]; + ULONG ux_device_class_pima_device_functional_mode; + UCHAR ux_device_class_pima_device_operations_supported[UX_DEVICE_CLASS_PIMA_ARRAY_MAX_LENGTH]; + UCHAR ux_device_class_pima_device_events_supported[UX_DEVICE_CLASS_PIMA_ARRAY_MAX_LENGTH]; + UCHAR ux_device_class_pima_device_properties_supported[UX_DEVICE_CLASS_PIMA_ARRAY_MAX_LENGTH]; + UCHAR ux_device_class_pima_device_capture_formats[UX_DEVICE_CLASS_PIMA_ARRAY_MAX_LENGTH]; + UCHAR ux_device_class_pima_device_image_formats[UX_DEVICE_CLASS_PIMA_ARRAY_MAX_LENGTH]; + UCHAR ux_device_class_pima_device_manufacturer[UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH]; + UCHAR ux_device_class_pima_device_model[UX_DEVICE_CLASS_PIMA_DATE_TIME_STRING_MAX_LENGTH]; + UCHAR ux_device_class_pima_device_version[UX_DEVICE_CLASS_PIMA_DATE_TIME_STRING_MAX_LENGTH]; + UCHAR ux_device_class_pima_device_serial_number[UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH]; + +} UX_SLAVE_CLASS_PIMA_DEVICE; + +/* Define PIMA storage info structure. */ + +typedef struct UX_SLAVE_CLASS_PIMA_STORAGE_STRUCT +{ + + ULONG ux_device_class_pima_storage_type; + ULONG ux_device_class_pima_storage_file_system_type; + ULONG ux_device_class_pima_storage_access_capability; + ULONG ux_device_class_pima_storage_max_capacity_low; + ULONG ux_device_class_pima_storage_max_capacity_high; + ULONG ux_device_class_pima_storage_free_space_bytes_low; + ULONG ux_device_class_pima_storage_free_space_bytes_high; + ULONG ux_device_class_pima_storage_free_space_images; + UCHAR ux_device_class_pima_storage_description[UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH]; + UCHAR ux__class_pima_storage_volume_label[UX_DEVICE_CLASS_PIMA_UNICODE_MAX_LENGTH]; + +} UX_SLAVE_CLASS_PIMA_STORAGE; + +/* Define PIMA structure. */ + +typedef struct UX_SLAVE_CLASS_PIMA_STRUCT +{ + + UX_SLAVE_INTERFACE *ux_slave_class_pima_interface; + UX_SLAVE_ENDPOINT *ux_device_class_pima_bulk_in_endpoint; + UX_SLAVE_ENDPOINT *ux_device_class_pima_bulk_out_endpoint; + UX_SLAVE_ENDPOINT *ux_device_class_pima_interrupt_endpoint; + UINT ux_device_class_pima_state; + USHORT ux_device_class_pima_device_status; + ULONG ux_device_class_pima_session_id; + ULONG ux_device_class_pima_current_object_handle; + ULONG ux_device_class_pima_transaction_id; + UCHAR *ux_device_class_pima_manufacturer; + UCHAR *ux_device_class_pima_model; + UCHAR *ux_device_class_pima_device_version; + UCHAR *ux_device_class_pima_serial_number; + ULONG ux_device_class_pima_storage_id; + ULONG ux_device_class_pima_storage_type; + ULONG ux_device_class_pima_storage_file_system_type; + ULONG ux_device_class_pima_storage_access_capability; + ULONG ux_device_class_pima_storage_max_capacity_low; + ULONG ux_device_class_pima_storage_max_capacity_high; + ULONG ux_device_class_pima_storage_free_space_low; + ULONG ux_device_class_pima_storage_free_space_high; + ULONG ux_device_class_pima_storage_free_space_image; + UCHAR *ux_device_class_pima_storage_description; + UCHAR *ux_device_class_pima_storage_volume_label; + UX_SEMAPHORE ux_device_class_pima_semaphore; + UX_THREAD ux_device_class_pima_interrupt_thread; + UCHAR *ux_device_class_pima_interrupt_thread_stack; + UX_SEMAPHORE ux_device_class_pima_interrupt_thread_semaphore; + UX_SLAVE_CLASS_PIMA_EVENT + *ux_device_class_pima_event_array; + UX_SLAVE_CLASS_PIMA_EVENT + *ux_device_class_pima_event_array_head; + UX_SLAVE_CLASS_PIMA_EVENT + *ux_device_class_pima_event_array_tail; + UX_SLAVE_CLASS_PIMA_EVENT + *ux_device_class_pima_event_array_end; + USHORT *ux_device_class_pima_device_properties_list; + USHORT *ux_device_class_pima_supported_capture_formats_list; + USHORT *ux_device_class_pima_supported_image_formats_list; + USHORT *ux_device_class_pima_object_properties_list; + UINT (*ux_device_class_pima_cancel)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima); + UINT (*ux_device_class_pima_device_reset)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima); + + UINT (*ux_device_class_pima_device_prop_desc_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG device_property, UCHAR **device_prop_dataset, ULONG *device_prop_dataset_length); + UINT (*ux_device_class_pima_device_prop_value_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG device_property, UCHAR **device_prop_value, ULONG *device_prop_value_length); + UINT (*ux_device_class_pima_device_prop_value_set)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG device_property, UCHAR *device_prop_value, ULONG device_prop_value_length); + + UINT (*ux_device_class_pima_storage_format)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG storage_id); + UINT (*ux_device_class_pima_storage_info_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG storage_id); + UINT (*ux_device_class_pima_object_number_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_format_code, ULONG object_association, ULONG *object_number); + UINT (*ux_device_class_pima_object_handles_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handles_format_code, + ULONG object_handles_association, + ULONG *object_handles_array, + ULONG object_handles_max_number); + UINT (*ux_device_class_pima_object_info_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, UX_SLAVE_CLASS_PIMA_OBJECT **object); + UINT (*ux_device_class_pima_object_data_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, UCHAR *object_buffer, ULONG object_offset, + ULONG object_length_requested, ULONG *object_actual_length); + UINT (*ux_device_class_pima_object_info_send)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, UX_SLAVE_CLASS_PIMA_OBJECT *object, ULONG storage_id, ULONG parent_object_handle, ULONG *object_handle); + UINT (*ux_device_class_pima_object_data_send)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, ULONG phase, UCHAR *object_buffer, ULONG object_offset, + ULONG object_length); + UINT (*ux_device_class_pima_object_delete)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle); + UINT (*ux_device_class_pima_object_prop_desc_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_property, ULONG object_format_code, UCHAR **object_prop_value_dataset, ULONG *object_prop_value_dataset_length); + UINT (*ux_device_class_pima_object_prop_value_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, ULONG object_property, UCHAR **object_prop_value, ULONG *object_prop_value_length); + UINT (*ux_device_class_pima_object_prop_value_set)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, ULONG object_property, UCHAR *object_prop_value, ULONG object_prop_value_length); + UINT (*ux_device_class_pima_object_references_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, UCHAR **object_handle_array, ULONG *object_handle_array_length); + UINT (*ux_device_class_pima_object_references_set)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, UCHAR *object_handle_array, ULONG object_handle_array_length); + VOID *ux_device_class_pima_application; + VOID (*ux_device_class_pima_instance_activate)(VOID *); + VOID (*ux_device_class_pima_instance_deactivate)(VOID *); + + +} UX_SLAVE_CLASS_PIMA; + +/* Define PIMA initialization command structure. */ + +typedef struct UX_SLAVE_CLASS_PIMA_PARAMETER_STRUCT +{ + + VOID (*ux_device_class_pima_instance_activate)(VOID *); + VOID (*ux_device_class_pima_instance_deactivate)(VOID *); + UCHAR *ux_device_class_pima_parameter_manufacturer; + UCHAR *ux_device_class_pima_parameter_model; + UCHAR *ux_device_class_pima_parameter_device_version; + UCHAR *ux_device_class_pima_parameter_serial_number; + ULONG ux_device_class_pima_parameter_storage_id; + ULONG ux_device_class_pima_parameter_storage_type; + ULONG ux_device_class_pima_parameter_storage_file_system_type; + ULONG ux_device_class_pima_parameter_storage_access_capability; + ULONG ux_device_class_pima_parameter_storage_max_capacity_low; + ULONG ux_device_class_pima_parameter_storage_max_capacity_high; + ULONG ux_device_class_pima_parameter_storage_free_space_low; + ULONG ux_device_class_pima_parameter_storage_free_space_high; + ULONG ux_device_class_pima_parameter_storage_free_space_image; + UCHAR *ux_device_class_pima_parameter_storage_description; + UCHAR *ux_device_class_pima_parameter_storage_volume_label; + USHORT *ux_device_class_pima_parameter_device_properties_list; + USHORT *ux_device_class_pima_parameter_supported_capture_formats_list; + USHORT *ux_device_class_pima_parameter_supported_image_formats_list; + USHORT *ux_device_class_pima_parameter_object_properties_list; + + /* PIMA callbacks, return UX success, or PIMA RC code. */ + UINT (*ux_device_class_pima_parameter_cancel)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima); + UINT (*ux_device_class_pima_parameter_device_reset)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima); + UINT (*ux_device_class_pima_parameter_device_prop_desc_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG device_property, UCHAR **device_prop_dataset, ULONG *device_prop_dataset_length); + UINT (*ux_device_class_pima_parameter_device_prop_value_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG device_property, UCHAR **device_prop_value, ULONG *device_prop_value_length); + UINT (*ux_device_class_pima_parameter_device_prop_value_set)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG device_property, UCHAR *device_prop_value, ULONG device_prop_value_length); + UINT (*ux_device_class_pima_parameter_storage_format)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG storage_id); + UINT (*ux_device_class_pima_parameter_storage_info_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG storage_id); + UINT (*ux_device_class_pima_parameter_object_number_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_format_code, ULONG object_association, ULONG *object_number); + UINT (*ux_device_class_pima_parameter_object_handles_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handles_format_code, + ULONG object_handles_association, + ULONG *object_handles_array, + ULONG object_handles_max_number); + UINT (*ux_device_class_pima_parameter_object_info_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, UX_SLAVE_CLASS_PIMA_OBJECT **object); + UINT (*ux_device_class_pima_parameter_object_data_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, UCHAR *object_buffer, ULONG object_offset, + ULONG object_length_requested, ULONG *object_actual_length); + + UINT (*ux_device_class_pima_parameter_object_info_send)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, UX_SLAVE_CLASS_PIMA_OBJECT *object, ULONG storage_id, ULONG parent_object_handle, ULONG *object_handle); + UINT (*ux_device_class_pima_parameter_object_data_send)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, ULONG phase ,UCHAR *object_buffer, ULONG object_offset, + ULONG object_length); + UINT (*ux_device_class_pima_parameter_object_delete)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle); + UINT (*ux_device_class_pima_parameter_object_prop_desc_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, ULONG object_property, UCHAR **object_prop_dataset, ULONG *object_prop_dataset_length); + UINT (*ux_device_class_pima_parameter_object_prop_value_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, ULONG object_property, UCHAR **object_prop_value, ULONG *object_prop_value_length); + UINT (*ux_device_class_pima_parameter_object_prop_value_set)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, ULONG object_property, UCHAR *object_prop_value, ULONG object_prop_value_length); + UINT (*ux_device_class_pima_parameter_object_references_get)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, UCHAR **object_handle_array, ULONG *object_handle_array_length); + UINT (*ux_device_class_pima_parameter_object_references_set)(struct UX_SLAVE_CLASS_PIMA_STRUCT *pima, ULONG object_handle, UCHAR *object_handle_array, ULONG object_handle_array_length); + VOID *ux_device_class_pima_parameter_application; + + +} UX_SLAVE_CLASS_PIMA_PARAMETER; + + +/* Define PIMA Object decompaction structure. */ + +#define UX_DEVICE_CLASS_PIMA_OBJECT_MAX_LENGTH 512 +#define UX_DEVICE_CLASS_PIMA_OBJECT_VARIABLE_OFFSET 52 +#define UX_DEVICE_CLASS_PIMA_OBJECT_ENTRIES 15 + + +/* Define PIMA storage decompaction structure. */ + +#define UX_DEVICE_CLASS_PIMA_STORAGE_TYPE (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 0 ) +#define UX_DEVICE_CLASS_PIMA_STORAGE_FILE_SYSTEM_TYPE (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 2 ) +#define UX_DEVICE_CLASS_PIMA_STORAGE_ACCESS_CAPABILITY (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 4 ) +#define UX_DEVICE_CLASS_PIMA_STORAGE_MAX_CAPACITY_LOW (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 6 ) +#define UX_DEVICE_CLASS_PIMA_STORAGE_MAX_CAPACITY_HIGH (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 10) +#define UX_DEVICE_CLASS_PIMA_STORAGE_FREE_SPACE_LOW (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 14) +#define UX_DEVICE_CLASS_PIMA_STORAGE_FREE_SPACE_HIGH (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 18) +#define UX_DEVICE_CLASS_PIMA_STORAGE_FREE_SPACE_IMAGE (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 22) +#define UX_DEVICE_CLASS_PIMA_STORAGE_FREE_STORAGE_DESCRIPTION (UX_DEVICE_CLASS_PIMA_DATA_HEADER_SIZE + 26) + +/* Define Pima Class function prototypes. */ +UINT _ux_device_class_pima_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_pima_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_pima_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_pima_control_request(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_pima_device_info_send(UX_SLAVE_CLASS_PIMA *pima); +UINT _ux_device_class_pima_entry(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_pima_event_get(UX_SLAVE_CLASS_PIMA *pima, + UX_SLAVE_CLASS_PIMA_EVENT *pima_event); +UINT _ux_device_class_pima_event_set(UX_SLAVE_CLASS_PIMA *pima, + UX_SLAVE_CLASS_PIMA_EVENT *pima_event); +VOID _ux_device_class_pima_interrupt_thread(ULONG pima_class); +UINT _ux_device_class_pima_response_send(UX_SLAVE_CLASS_PIMA *pima, ULONG response_code, + ULONG number_parameters, + ULONG parameter_1, ULONG parameter_2, ULONG paramater_3); +VOID _ux_device_class_pima_thread(ULONG pima_class); +UINT _ux_device_class_pima_object_handles_send(UX_SLAVE_CLASS_PIMA *pima, + ULONG storage_id, + ULONG object_format_code, + ULONG object_association); +UINT _ux_device_class_pima_objects_number_send(UX_SLAVE_CLASS_PIMA *pima, + ULONG storage_id, + ULONG object_format_code, + ULONG object_association); + +UINT _ux_device_class_pima_device_prop_desc_get(UX_SLAVE_CLASS_PIMA *pima, ULONG device_property_code); +UINT _ux_device_class_pima_device_prop_value_get(UX_SLAVE_CLASS_PIMA *pima, ULONG device_property_code); +UINT _ux_device_class_pima_device_prop_value_set(UX_SLAVE_CLASS_PIMA *pima, ULONG device_property_code); +UINT _ux_device_class_pima_object_info_get(UX_SLAVE_CLASS_PIMA *pima, ULONG object_handle); +UINT _ux_device_class_pima_object_info_send(UX_SLAVE_CLASS_PIMA *pima, ULONG storage_id, ULONG parent_object_handle); +UINT _ux_device_class_pima_object_data_get(UX_SLAVE_CLASS_PIMA *pima, ULONG object_handle); +UINT _ux_device_class_pima_object_data_send(UX_SLAVE_CLASS_PIMA *pima); +UINT _ux_device_class_pima_object_delete(UX_SLAVE_CLASS_PIMA *pima, ULONG object_handle, ULONG object_format); +UINT _ux_device_class_pima_object_add(UX_SLAVE_CLASS_PIMA *pima, ULONG object_handle); +UINT _ux_device_class_pima_partial_object_data_get(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_handle, + ULONG offset_requested, + ULONG length_requested); + +UINT _ux_device_class_pima_storage_id_send(UX_SLAVE_CLASS_PIMA *pima); +UINT _ux_device_class_pima_storage_info_get(UX_SLAVE_CLASS_PIMA *pima, ULONG storage_id); +UINT _ux_device_class_pima_object_props_supported_get(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_format_code); +UINT _ux_device_class_pima_object_prop_value_get(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_handle, + ULONG object_property_code); +UINT _ux_device_class_pima_object_prop_value_set(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_handle, + ULONG object_property_code); +UINT _ux_device_class_pima_object_prop_desc_get(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_property, + ULONG object_format_code); +UINT _ux_device_class_pima_object_references_get(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_handle); +UINT _ux_device_class_pima_object_references_set(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_handle); +UINT _ux_device_class_pima_object_prop_value_get(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_handle, + ULONG object_property_code); +UINT _ux_device_class_pima_object_prop_value_set(UX_SLAVE_CLASS_PIMA *pima, + ULONG object_handle, + ULONG object_property_code); +UINT _ux_device_class_pima_storage_format(UX_SLAVE_CLASS_PIMA *pima, ULONG storage_id); +UINT _ux_device_class_pima_device_reset(UX_SLAVE_CLASS_PIMA *pima); + +/* Define Device PIMA Class API prototypes. */ + +#define ux_device_class_pima_initialize _ux_device_class_pima_initialize +#define ux_device_class_pima_activate _ux_device_class_pima_activate +#define ux_device_class_pima_dectivate _ux_device_class_pima_dectivate +#define ux_device_class_pima_entry _ux_device_class_pima_entry +#define ux_device_class_pima_control_request _ux_device_class_pima_control_request +#define ux_device_class_pima_object_add _ux_device_class_pima_object_add + +/* Define Pima Class data prototypes. */ + +extern UCHAR _ux_device_class_pima_vendor_extension_descriptor[]; +extern USHORT _ux_device_class_pima_supported_operations[]; +extern USHORT _ux_device_class_pima_supported_events[]; +extern USHORT _ux_device_class_pima_supported_capture_formats[]; +extern USHORT _ux_device_class_pima_supported_image_formats[]; +extern USHORT _ux_device_class_pima_device_prop_supported[]; + + + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_printer.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_printer.h new file mode 100644 index 00000000..2c2a1b1d --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_printer.h @@ -0,0 +1,146 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Printer Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_printer.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the equivalences for the USBX Device Class */ +/* Printer component. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-31-2022 Chaoqiong Xiao Initial Version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_PRINTER_H +#define UX_DEVICE_CLASS_PRINTER_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + + +/* Define Printer Class USB Class constants. */ +#define UX_DEVICE_CLASS_PRINTER_CLASS 7 + +#define UX_DEVICE_CLASS_PRINTER_SUBCLASS 1 + +#define UX_DEVICE_CLASS_PRINTER_PROTOCOL_UNIDIRECTIONAL 1 +#define UX_DEVICE_CLASS_PRINTER_PROTOCOL_BIDIRECTIONAL 2 +#define UX_DEVICE_CLASS_PRINTER_PROTOCOL_1284_4_COMPATIBLE_BIDIR 3 + + +/* Device Printer Requests */ +#define UX_DEVICE_CLASS_PRINTER_GET_DEVICE_ID 0x00 +#define UX_DEVICE_CLASS_PRINTER_GET_PORT_STATUS 0x01 +#define UX_DEVICE_CLASS_PRINTER_SOFT_RESET 0x02 + + +/* Printer Port Status. */ +#define UX_DEVICE_CLASS_PRINTER_PAPER_EMPTY (1u << 5) +#define UX_DEVICE_CLASS_PRINTER_SELECT (1u << 4) +#define UX_DEVICE_CLASS_PRINTER_NOT_ERROR (1u << 3) + + +/* Printer IOCTL code. */ +#define UX_DEVICE_CLASS_PRINTER_IOCTL_PORT_STATUS_SET 1 +#define UX_DEVICE_CLASS_PRINTER_IOCTL_READ_TIMEOUT_SET 2 +#define UX_DEVICE_CLASS_PRINTER_IOCTL_WRITE_TIMEOUT_SET 3 + + +/* Define Device Printer Class Calling Parameter structure */ + +typedef struct UX_DEVICE_CLASS_PRINTER_PARAMETER_STRUCT +{ + UCHAR *ux_device_class_printer_device_id; /* IEEE 1284 string, first 2 big endian length. */ + VOID (*ux_device_class_printer_instance_activate)(VOID *); + VOID (*ux_device_class_printer_instance_deactivate)(VOID *); + VOID (*ux_device_class_printer_soft_reset)(VOID *); +} UX_DEVICE_CLASS_PRINTER_PARAMETER; + + +/* Define Printer Class structure. */ + +typedef struct UX_DEVICE_CLASS_PRINTER_STRUCT +{ + UX_SLAVE_INTERFACE *ux_device_class_printer_interface; + UX_SLAVE_ENDPOINT *ux_device_class_printer_endpoint_out; + UX_SLAVE_ENDPOINT *ux_device_class_printer_endpoint_in; + ULONG ux_device_class_printer_port_status; + UX_DEVICE_CLASS_PRINTER_PARAMETER + ux_device_class_printer_parameter; + UX_MUTEX ux_device_class_printer_endpoint_out_mutex; + UX_MUTEX ux_device_class_printer_endpoint_in_mutex; +} UX_DEVICE_CLASS_PRINTER; + + +/* Define Device Printer Class prototypes. */ + +UINT _ux_device_class_printer_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_printer_control_request(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_printer_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_printer_entry(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_printer_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_printer_uninitialize(UX_SLAVE_CLASS_COMMAND *command); + +VOID _ux_device_class_printer_soft_reset(UX_DEVICE_CLASS_PRINTER *printer); + +UINT _ux_device_class_printer_write(UX_DEVICE_CLASS_PRINTER *printer, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); +UINT _ux_device_class_printer_read(UX_DEVICE_CLASS_PRINTER *printer, UCHAR *buffer, + ULONG requested_length, ULONG *actual_length); + +UINT _ux_device_class_printer_ioctl(UX_DEVICE_CLASS_PRINTER *printer, ULONG ioctl_function, + VOID *parameter); + + +/* Define Device Printer Class API prototypes. */ + +#define ux_device_class_printer_entry _ux_device_class_printer_entry +#define ux_device_class_printer_read _ux_device_class_printer_read +#define ux_device_class_printer_write _ux_device_class_printer_write +#define ux_device_class_printer_ioctl _ux_device_class_printer_ioctl + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif /* UX_DEVICE_CLASS_PRINTER_H */ diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_rndis.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_rndis.h new file mode 100644 index 00000000..f236c5c9 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_rndis.h @@ -0,0 +1,596 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** RNDIS Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_rndis.h PORTABLE C */ +/* 6.1.8 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the equivalences for the USBX Device Class RNDIS */ +/* component. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 08-02-2021 Wen Wang Modified comment(s), */ +/* fixed spelling error, */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_RNDIS_H +#define UX_DEVICE_CLASS_RNDIS_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + +#include "nx_api.h" +#include "ux_network_driver.h" + +/* Define generic RNDIS equivalences. */ +#define UX_DEVICE_CLASS_RNDIS_CLASS_COMMUNICATION_CONTROL 0x02 +#define UX_DEVICE_CLASS_RNDIS_CLASS_COMMUNICATION_DATA 0x0A +#define UX_DEVICE_CLASS_RNDIS_NEW_INTERRUPT_EVENT 1 +#define UX_DEVICE_CLASS_RNDIS_NEW_BULKOUT_EVENT 2 +#define UX_DEVICE_CLASS_RNDIS_NEW_BULKIN_EVENT 4 +#define UX_DEVICE_CLASS_RNDIS_NEW_DEVICE_STATE_CHANGE_EVENT 8 +#define UX_DEVICE_CLASS_RNDIS_INTERRUPT_RESPONSE_LENGTH 8 +#define UX_DEVICE_CLASS_RNDIS_INTERRUPT_RESPONSE_AVAILABLE_FLAG 1 +#define UX_DEVICE_CLASS_RNDIS_BASE_IP_ADDRESS 0xC0A80001 +#define UX_DEVICE_CLASS_RNDIS_BASE_IP_MASK 0xFFFFFF00 +#define UX_DEVICE_CLASS_RNDIS_MAX_MTU 1518 +#define UX_DEVICE_CLASS_RNDIS_ETHERNET_IP 0x0800 +#define UX_DEVICE_CLASS_RNDIS_ETHERNET_ARP 0x0806 +#define UX_DEVICE_CLASS_RNDIS_ETHERNET_RARP 0x8035 +#define UX_DEVICE_CLASS_RNDIS_ETHERNET_PACKET_SIZE 1536 +#define UX_DEVICE_CLASS_RNDIS_NX_ALIGN_PADDING 2 +#define UX_DEVICE_CLASS_RNDIS_NX_PKPOOL_ENTRIES 8 + +#define UX_DEVICE_CLASS_RNDIS_NX_PACKET_SIZE sizeof(NX_PACKET) + +#define UX_DEVICE_CLASS_RNDIS_NX_PAYLOAD_SIZE_ASSERT UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_ADD_ULONG(UX_DEVICE_CLASS_RNDIS_ETHERNET_PACKET_SIZE, UX_DEVICE_CLASS_RNDIS_NX_ALIGN_PADDING), UX_DEVICE_CLASS_RNDIS_NX_PAYLOAD_SIZE_calc_ovf) +#define UX_DEVICE_CLASS_RNDIS_NX_PAYLOAD_SIZE (UX_DEVICE_CLASS_RNDIS_ETHERNET_PACKET_SIZE + UX_DEVICE_CLASS_RNDIS_NX_ALIGN_PADDING) + +#define UX_DEVICE_CLASS_RNDIS_NX_BUFF_SIZE_ASSERT \ + UX_DEVICE_CLASS_RNDIS_NX_PAYLOAD_SIZE_ASSERT \ + UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_ADD_ULONG( \ + UX_DEVICE_CLASS_RNDIS_NX_PAYLOAD_SIZE, \ + UX_DEVICE_CLASS_RNDIS_NX_PACKET_SIZE), \ + UX_DEVICE_CLASS_RNDIS_NX_BUFF_SIZE_calc_ovf) +#define UX_DEVICE_CLASS_RNDIS_NX_BUFF_SIZE (UX_DEVICE_CLASS_RNDIS_NX_PAYLOAD_SIZE + UX_DEVICE_CLASS_RNDIS_NX_PACKET_SIZE) + +#define UX_DEVICE_CLASS_RNDIS_NX_ETHERNET_POOL_ALLOCSIZE_ASSERT \ + UX_DEVICE_CLASS_RNDIS_NX_BUFF_SIZE_ASSERT \ + UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_MULC_ULONG( \ + UX_DEVICE_CLASS_RNDIS_NX_PKPOOL_ENTRIES, \ + UX_DEVICE_CLASS_RNDIS_NX_BUFF_SIZE), \ + UX_DEVICE_CLASS_RNDIS_NX_ETHERNET_POOL_ALLOCSIZE_calc1_ovf) \ + UX_COMPILE_TIME_ASSERT(!UX_OVERFLOW_CHECK_ADD_ULONG( \ + UX_DEVICE_CLASS_RNDIS_NX_PKPOOL_ENTRIES * \ + UX_DEVICE_CLASS_RNDIS_NX_BUFF_SIZE, \ + 32), UX_DEVICE_CLASS_RNDIS_NX_ETHERNET_POOL_ALLOCSIZE_calc2_ovf) +#define UX_DEVICE_CLASS_RNDIS_NX_ETHERNET_POOL_ALLOCSIZE (UX_DEVICE_CLASS_RNDIS_NX_PKPOOL_ENTRIES * UX_DEVICE_CLASS_RNDIS_NX_BUFF_SIZE + 32) + +#define UX_DEVICE_CLASS_RNDIS_ETHERNET_SIZE 14 +#define UX_DEVICE_CLASS_RNDIS_NODE_ID_LENGTH 6 +#define UX_DEVICE_CLASS_RNDIS_VENDOR_DESCRIPTION_MAX_LENGTH 64 +#define UX_DEVICE_CLASS_RNDIS_MAC_OPTIONS 8 +#define UX_DEVICE_CLASS_RNDIS_PACKET_HEADER_MSG 1 + +#define UX_DEVICE_CLASS_RNDIS_OID_SUPPORTED_LIST_LENGTH 30 + +/* Device RNDIS Requests */ +#define UX_DEVICE_CLASS_RNDIS_SEND_ENCAPSULATED_COMMAND 0x00 +#define UX_DEVICE_CLASS_RNDIS_GET_ENCAPSULATED_RESPONSE 0x01 + +/* Define RNDIS Versions. Set to 1.0 here. */ +#define UX_DEVICE_CLASS_RNDIS_VERSION_MAJOR 0x00000001 +#define UX_DEVICE_CLASS_RNDIS_VERSION_MINOR 0x00000000 + +/* Define RNDIS Connection type supported. Set to conectionless. */ +#define UX_DEVICE_CLASS_RNDIS_DF_CONNECTIONLESS 0x00000001 +#define UX_DEVICE_CLASS_RNDIS_DF_CONNECTION_ORIENTED 0x00000002 +#define UX_DEVICE_CLASS_RNDIS_DF_CONNECTION_SUPPORTED UX_DEVICE_CLASS_RNDIS_DF_CONNECTIONLESS + +/* Define RNDIS Medium supported by the device. */ +#define UX_DEVICE_CLASS_RNDIS_MEDIUM_SUPPORTED 0x00000000 + +/* Define RNDIS Packet size and types supported. */ +#define UX_DEVICE_CLASS_RNDIS_MAX_PACKET_PER_TRANSFER 0x00000001 +#define UX_DEVICE_CLASS_RNDIS_MAX_PACKET_TRANSFER_SIZE 0x00000640 +#define UX_DEVICE_CLASS_RNDIS_PACKET_ALIGNEMENT_FACTOR 0x00000003 +#define UX_DEVICE_CLASS_RNDIS_MAX_FRAME_SIZE 0x000005DC +#define UX_DEVICE_CLASS_RNDIS_MAX_PACKET_LENGTH 0x000005EA + +/* Define LINK speeds. */ +#define UX_DEVICE_CLASS_RNDIS_LINK_SPEED_FS 0x0001D4C0 + +/* Define LINK statess. */ +#define UX_DEVICE_CLASS_RNDIS_LINK_STATE_DOWN 0 +#define UX_DEVICE_CLASS_RNDIS_LINK_STATE_UP 1 +#define UX_DEVICE_CLASS_RNDIS_LINK_STATE_PENDING_UP 2 +#define UX_DEVICE_CLASS_RNDIS_LINK_STATE_PENDING_DOWN 3 + +/* Define media connection values. */ +#define UX_DEVICE_CLASS_RNDIS_MEDIA_CONNECTED 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_DISCONNECTED 0x00000001 + +/* Define media supported values. */ +#define UX_DEVICE_CLASS_RNDIS_MEDIA_802_3 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_802_5 0x00000001 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_FDDI 0x00000002 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_WAN 0x00000003 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_LOCAL_TALK 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_DIX 0x00000005 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_ARCNET_RAW 0x00000006 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_ARCNET_878_2 0x00000007 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_ATM 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_WIRELESS_WAN 0x00000009 +#define UX_DEVICE_CLASS_RNDIS_MEDIA_IRDA 0x0000000A + +/* Define RNDIS status values. */ +#define UX_DEVICE_CLASS_RNDIS_STATUS_SUCCESS 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_STATUS_FAILURE 0xC0000001 +#define UX_DEVICE_CLASS_RNDIS_STATUS_INVALID_DATA 0xC0010015 +#define UX_DEVICE_CLASS_RNDIS_STATUS_NOT_SUPPORTED 0xC00000BB +#define UX_DEVICE_CLASS_RNDIS_STATUS_MEDIA_CONNECTED 0x4001000B +#define UX_DEVICE_CLASS_RNDIS_STATUS_MEDIA_DISCONNECT 0x4001000C + +/* Define RNDIS Control Messages values. */ +#define UX_DEVICE_CLASS_RNDIS_MSG_INITIALIZE 0x00000002 +#define UX_DEVICE_CLASS_RNDIS_MSG_HALT 0x00000003 +#define UX_DEVICE_CLASS_RNDIS_MSG_QUERY 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MSG_SET 0x00000005 +#define UX_DEVICE_CLASS_RNDIS_MSG_RESET 0x00000006 +#define UX_DEVICE_CLASS_RNDIS_MSG_INDICATE_STATUS 0x00000007 +#define UX_DEVICE_CLASS_RNDIS_MSG_KEEP_ALIVE 0x00000008 + +/* Define RNDIS Control Completion values. */ +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE 0x80000002 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY 0x80000004 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_SET 0x80000005 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_RESET 0x80000006 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_KEEP_ALIVE 0x80000008 + +/* Define RNDIS Control Messages : MSG_INITIALIZE offsets. */ +#define UX_DEVICE_CLASS_RNDIS_MSG_INITIALIZE_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MSG_INITIALIZE_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MSG_INITIALIZE_REQUEST_ID 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_MSG_INITIALIZE_MAJOR_VERSION 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_MSG_INITIALIZE_MINOR_VERSION 0x00000010 +#define UX_DEVICE_CLASS_RNDIS_MSG_INITIALIZE_MAX_TRANSFER_SIZE 0x00000014 + +/* Define RNDIS Control Messages : CMPLT_INITIALIZE offsets. */ +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_REQUEST_ID 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_STATUS 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_MAJOR_VERSION 0x00000010 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_MINOR_VERSION 0x00000014 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_DEVICE_FLAGS 0x00000018 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_MEDIUM 0x0000001C +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_MAX_PACKETS_PER_TRANSFER 0x00000020 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_MAX_TRANSFER_SIZE 0x00000024 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_PACKET_ALIGNMENT 0x00000028 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_AFL_LIST_OFFSET 0x0000002C +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_AFL_LIST_SIZE 0x00000030 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_RESPONSE_LENGTH 0x00000034 + +/* Define RNDIS Control Messages : MSG_HALT offsets. */ +#define UX_DEVICE_CLASS_RNDIS_MSG_HALT_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MSG_HALT_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MSG_HALT_REQUEST_ID 0x00000008 + +/* Define RNDIS Control Messages : MSG_QUERY offsets. */ +#define UX_DEVICE_CLASS_RNDIS_MSG_QUERY_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MSG_QUERY_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MSG_QUERY_REQUEST_ID 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_MSG_QUERY_OID 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_MSG_QUERY_INFO_BUFFER_LENGTH 0x00000010 +#define UX_DEVICE_CLASS_RNDIS_MSG_QUERY_INFO_BUFFER_OFFSET 0x00000014 +#define UX_DEVICE_CLASS_RNDIS_MSG_QUERY_DEVICE_VC_HANDLE 0x00000018 + +#define UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_REQUEST_ID 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_STATUS 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_INFO_BUFFER_LENGTH 0x00000010 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_INFO_BUFFER_OFFSET 0x00000014 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_INFO_BUFFER 0x00000018 + +/* Define RNDIS Control Messages : MSG_SET offsets. */ +#define UX_DEVICE_CLASS_RNDIS_MSG_SET_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MSG_SET_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MSG_SET_REQUEST_ID 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_MSG_SET_OID 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_MSG_SET_INFO_BUFFER_LENGTH 0x00000010 +#define UX_DEVICE_CLASS_RNDIS_MSG_SET_INFO_BUFFER_OFFSET 0x00000014 +#define UX_DEVICE_CLASS_RNDIS_MSG_SET_DEVICE_VC_HANDLE 0x00000018 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_SET_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_SET_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_SET_REQUEST_ID 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_SET_STATUS 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_CMPLT_SET_RESPONSE_LENGTH 0x00000010 + +/* Define RNDIS Control Messages : MSG_RESET offsets. */ +#define UX_DEVICE_CLASS_RNDIS_MSG_RESET_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MSG_RESET_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MSG_RESET_RESERVED 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_RESET_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_RESET_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_RESET_STATUS 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_RESET_ADDRESSING_RESET 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_CMPLT_RESET_RESPONSE_LENGTH 0x00000010 + +/* Define RNDIS Control Messages : MSG_INDICATE_STATUS offsets. */ +#define UX_DEVICE_CLASS_RNDIS_MSG_INDICATE_STATUS_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MSG_INDICATE_STATUS_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MSG_INDICATE_STATUS_STATUS 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_MSG_INDICATE_STATUS_STATUS_BUFFER_LENGTH 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_MSG_INDICATE_STATUS_STATUS_BUFFER_OFFSET 0x00000010 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INDICATE_STATUS_DIAG 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_INDICATE_STATUS_ERROR_OFFSET 0x00000004 + +/* Define RNDIS Control Messages : MSG_KEEP_ALIVE offsets. */ +#define UX_DEVICE_CLASS_RNDIS_MSG_KEEP_ALIVE_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_MSG_KEEP_ALIVE_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_MSG_KEEP_ALIVE_REQUEST_ID 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_KEEP_ALIVE_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_KEEP_ALIVE_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_KEEP_ALIVE_REQUEST_ID 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_CMPLT_KEEP_ALIVE_STATUS 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_CMPLT_KEEP_ALIVE_RESPONSE_LENGTH 0x00000010 + +/* Define RNDIS State machine. */ +#define UX_DEVICE_CLASS_RNDIS_STATE_UNINITIALIZED 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_STATE_INITIALIZED 0x00000001 +#define UX_DEVICE_CLASS_RNDIS_STATE_DATA_INITIALIZED 0x00000002 + +/* Define Required Object IDs (OIDs) */ +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_SUPPORTED_LIST 0x00010101 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_HARDWARE_STATUS 0x00010102 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MEDIA_SUPPORTED 0x00010103 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MEDIA_IN_USE 0x00010104 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MAXIMUM_LOOKAHEAD 0x00010105 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_LINK_SPEED 0x00010107 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_TRANSMIT_BUFFER_SPACE 0x00010108 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RECEIVE_BUFFER_SPACE 0x00010109 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010A +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010B +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_VENDOR_ID 0x0001010C +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_VENDOR_DESCRIPTION 0x0001010D +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_CURRENT_PACKET_FILTER 0x0001010E +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_CURRENT_LOOKAHEAD 0x0001010F +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_DRIVER_VERSION 0x00010110 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_PROTOCOL_OPTIONS 0x00010112 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MAC_OPTIONS 0x00010113 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MEDIA_CONNECT_STATUS 0x00010114 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_VENDOR_DRIVER_VERSION 0x00010116 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_SUPPORTED_GUIDS 0x00010117 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_NETWORK_LAYER_ADDRESSES 0x00010118 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_TRANSPORT_HEADER_OFFSET 0x00010119 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MACHINE_NAME 0x0001021A +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RNDIS_CONFIG_PARAMETER 0x0001021B +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_VLAN_ID 0x0001021C + +/* Define Optional OIDs */ +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MEDIA_CAPABILITIES 0x00010201 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_PHYSICAL_MEDIUM 0x00010202 + +/* Define Required statistics OIDs */ +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_XMIT_OK 0x00020101 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RCV_OK 0x00020102 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_XMIT_ERROR 0x00020103 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RCV_ERROR 0x00020104 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RCV_NO_BUFFER 0x00020105 + +/* Define Optional statistics OIDs */ +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_DIRECTED_BYTES_RCV 0x00020207 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MULTICAST_BYTES_RCV 0x00020209 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_BROADCAST_BYTES_RCV 0x0002020B +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RCV_CRC_ERROR 0x0002020D +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_GET_TIME_CAPS 0x0002020F +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_GET_NETCARD_TIME 0x00020210 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_NETCARD_LOAD 0x00020211 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_DEVICE_PROFILE 0x00020212 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_INIT_TIME_MS 0x00020213 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RESET_COUNTS 0x00020214 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MEDIA_SENSE_COUNTS 0x00020215 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_FRIENDLY_NAME 0x00020216 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_MINIPORT_INFO 0x00020217 +#define UX_DEVICE_CLASS_RNDIS_OID_GEN_RESET_VERIFY_PARAMETERS 0x00020218 + +/* Define IEEE 802.3 (Ethernet) OIDs */ + +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_PERMANENT_ADDRESS 0x01010101 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_CURRENT_ADDRESS 0x01010102 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_MULTICAST_LIST 0x01010103 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_MAC_OPTIONS 0x01010105 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_XMIT_ONE_COLLISION 0x01020102 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_XMIT_DEFERRED 0x01020201 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_XMIT_MAX_COLLISIONS 0x01020202 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_RCV_OVERRUN 0x01020203 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_XMIT_UNDERRUN 0x01020204 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_XMIT_HEARTBEAT_FAILURE 0x01020205 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206 +#define UX_DEVICE_CLASS_RNDIS_OID_802_3_XMIT_LATE_COLLISIONS 0x01020207 + +/* Define Hardware status code. */ +#define UX_DEVICE_CLASS_RNDIS_OID_HW_STATUS_READY 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_OID_HW_STATUS_INITIALIZING 0x00000001 +#define UX_DEVICE_CLASS_RNDIS_OID_HW_STATUS_RESET 0x00000002 +#define UX_DEVICE_CLASS_RNDIS_OID_HW_STATUS_CLOSING 0x00000003 +#define UX_DEVICE_CLASS_RNDIS_OID_HW_STATUS_NOT_READY 0x00000004 + +/* Define RNDIS Packet Header format. */ +#define UX_DEVICE_CLASS_RNDIS_PACKET_MESSAGE_TYPE 0x00000000 +#define UX_DEVICE_CLASS_RNDIS_PACKET_MESSAGE_LENGTH 0x00000004 +#define UX_DEVICE_CLASS_RNDIS_PACKET_DATA_OFFSET 0x00000008 +#define UX_DEVICE_CLASS_RNDIS_PACKET_DATA_LENGTH 0x0000000C +#define UX_DEVICE_CLASS_RNDIS_PACKET_OOB_DATA_OFFSET 0x00000010 +#define UX_DEVICE_CLASS_RNDIS_PACKET_OOB_DATA_LENGTH 0x00000014 +#define UX_DEVICE_CLASS_RNDIS_PACKET_NUM_OOB_DATA_ELEMENTS 0x00000018 +#define UX_DEVICE_CLASS_RNDIS_PACKET_INFO_OFFSET 0x0000001C +#define UX_DEVICE_CLASS_RNDIS_PACKET_INFO_LENGTH 0x00000020 +#define UX_DEVICE_CLASS_RNDIS_PACKET_VC_HANDLE 0x00000024 +#define UX_DEVICE_CLASS_RNDIS_PACKET_RESERVED 0x00000028 +#define UX_DEVICE_CLASS_RNDIS_PACKET_BUFFER 0x0000002C +#define UX_DEVICE_CLASS_RNDIS_PACKET_HEADER_LENGTH 0x0000002C + +/* Define NetX errors inside the RNDIS class. */ +#define UX_DEVICE_CLASS_RNDIS_NX_SUCCESS 0x00 +#define UX_DEVICE_CLASS_RNDIS_NX_NO_PACKET 0x01 +#define UX_DEVICE_CLASS_RNDIS_NX_UNDERFLOW 0x02 +#define UX_DEVICE_CLASS_RNDIS_NX_OVERFLOW 0x03 +#define UX_DEVICE_CLASS_RNDIS_NX_NO_MAPPING 0x04 +#define UX_DEVICE_CLASS_RNDIS_NX_DELETED 0x05 +#define UX_DEVICE_CLASS_RNDIS_NX_POOL_ERROR 0x06 +#define UX_DEVICE_CLASS_RNDIS_NX_PTR_ERROR 0x07 +#define UX_DEVICE_CLASS_RNDIS_NX_WAIT_ERROR 0x08 +#define UX_DEVICE_CLASS_RNDIS_NX_SIZE_ERROR 0x09 +#define UX_DEVICE_CLASS_RNDIS_NX_OPTION_ERROR 0x0a +#define UX_DEVICE_CLASS_RNDIS_NX_DELETE_ERROR 0x10 +#define UX_DEVICE_CLASS_RNDIS_NX_CALLER_ERROR 0x11 +#define UX_DEVICE_CLASS_RNDIS_NX_INVALID_PACKET 0x12 +#define UX_DEVICE_CLASS_RNDIS_NX_INVALID_SOCKET 0x13 +#define UX_DEVICE_CLASS_RNDIS_NX_NOT_ENABLED 0x14 +#define UX_DEVICE_CLASS_RNDIS_NX_ALREADY_ENABLED 0x15 +#define UX_DEVICE_CLASS_RNDIS_NX_ENTRY_NOT_FOUND 0x16 +#define UX_DEVICE_CLASS_RNDIS_NX_NO_MORE_ENTRIES 0x17 +#define UX_DEVICE_CLASS_RNDIS_NX_ARP_TIMER_ERROR 0x18 +#define UX_DEVICE_CLASS_RNDIS_NX_RESERVED_CODE0 0x19 +#define UX_DEVICE_CLASS_RNDIS_NX_WAIT_ABORTED 0x1A +#define UX_DEVICE_CLASS_RNDIS_NX_IP_INTERNAL_ERROR 0x20 +#define UX_DEVICE_CLASS_RNDIS_NX_IP_ADDRESS_ERROR 0x21 +#define UX_DEVICE_CLASS_RNDIS_NX_ALREADY_BOUND 0x22 +#define UX_DEVICE_CLASS_RNDIS_NX_PORT_UNAVAILABLE 0x23 +#define UX_DEVICE_CLASS_RNDIS_NX_NOT_BOUND 0x24 +#define UX_DEVICE_CLASS_RNDIS_NX_RESERVED_CODE1 0x25 +#define UX_DEVICE_CLASS_RNDIS_NX_SOCKET_UNBOUND 0x26 +#define UX_DEVICE_CLASS_RNDIS_NX_NOT_CREATED 0x27 +#define UX_DEVICE_CLASS_RNDIS_NX_SOCKETS_BOUND 0x28 +#define UX_DEVICE_CLASS_RNDIS_NX_NO_RESPONSE 0x29 +#define UX_DEVICE_CLASS_RNDIS_NX_POOL_DELETED 0x30 +#define UX_DEVICE_CLASS_RNDIS_NX_ALREADY_RELEASED 0x31 +#define UX_DEVICE_CLASS_RNDIS_NX_RESERVED_CODE2 0x32 +#define UX_DEVICE_CLASS_RNDIS_NX_MAX_LISTEN 0x33 +#define UX_DEVICE_CLASS_RNDIS_NX_DUPLICATE_LISTEN 0x34 +#define UX_DEVICE_CLASS_RNDIS_NX_NOT_CLOSED 0x35 +#define UX_DEVICE_CLASS_RNDIS_NX_NOT_LISTEN_STATE 0x36 +#define UX_DEVICE_CLASS_RNDIS_NX_IN_PROGRESS 0x37 +#define UX_DEVICE_CLASS_RNDIS_NX_NOT_CONNECTED 0x38 +#define UX_DEVICE_CLASS_RNDIS_NX_WINDOW_OVERFLOW 0x39 +#define UX_DEVICE_CLASS_RNDIS_NX_ALREADY_SUSPENDED 0x40 +#define UX_DEVICE_CLASS_RNDIS_NX_DISCONNECT_FAILED 0x41 +#define UX_DEVICE_CLASS_RNDIS_NX_STILL_BOUND 0x42 +#define UX_DEVICE_CLASS_RNDIS_NX_NOT_SUCCESSFUL 0x43 +#define UX_DEVICE_CLASS_RNDIS_NX_UNHANDLED_COMMAND 0x44 +#define UX_DEVICE_CLASS_RNDIS_NX_NO_FREE_PORTS 0x45 +#define UX_DEVICE_CLASS_RNDIS_NX_INVALID_PORT 0x46 +#define UX_DEVICE_CLASS_RNDIS_NX_INVALID_RELISTEN 0x47 +#define UX_DEVICE_CLASS_RNDIS_NX_CONNECTION_PENDING 0x48 +#define UX_DEVICE_CLASS_RNDIS_NX_TX_QUEUE_DEPTH 0x49 +#define UX_DEVICE_CLASS_RNDIS_NX_NOT_IMPLEMENTED 0x80 + +/* Define timeout packet allocation value. */ +#ifndef UX_DEVICE_CLASS_RNDIS_PACKET_POOL_WAIT +#define UX_DEVICE_CLASS_RNDIS_PACKET_POOL_WAIT 10 +#endif + +/* Calculate response buffer length. */ +#define UX_DEVICE_CLASS_RNDIS_OID_SUPPORTED_RESPONSE_LENGTH (UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_INFO_BUFFER + UX_DEVICE_CLASS_RNDIS_OID_SUPPORTED_LIST_LENGTH * 4) +#define UX_DEVICE_CLASS_RNDIS_VENDOR_DESCRIPTION_MAX_RESPONSE_LENGTH (UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_INFO_BUFFER + UX_DEVICE_CLASS_RNDIS_VENDOR_DESCRIPTION_MAX_LENGTH) +#define UX_DEVICE_CLASS_RNDIS_NODE_ID_RESPONSE_LENGTH (UX_DEVICE_CLASS_RNDIS_CMPLT_QUERY_INFO_BUFFER + UX_DEVICE_CLASS_RNDIS_NODE_ID_LENGTH) + +/* Decide maximum size of RNDIS response buffer (with 1 ~ 4 bytes as padding and aligned to 4 bytes). */ +#define UX_DEVICE_CLASS_RNDIS_MAX(a, b) (((a) > (b)) ? (a) : (b)) +#define UX_DEVICE_CLASS_RNDIS_MAX_CONTROL_RESPONSE_LENGTH ((( \ + UX_DEVICE_CLASS_RNDIS_MAX(UX_DEVICE_CLASS_RNDIS_CMPLT_INITIALIZE_RESPONSE_LENGTH, \ + UX_DEVICE_CLASS_RNDIS_MAX(UX_DEVICE_CLASS_RNDIS_CMPLT_KEEP_ALIVE_RESPONSE_LENGTH, \ + UX_DEVICE_CLASS_RNDIS_MAX(UX_DEVICE_CLASS_RNDIS_CMPLT_RESET_RESPONSE_LENGTH, \ + UX_DEVICE_CLASS_RNDIS_MAX(UX_DEVICE_CLASS_RNDIS_CMPLT_SET_RESPONSE_LENGTH, \ + UX_DEVICE_CLASS_RNDIS_MAX(UX_DEVICE_CLASS_RNDIS_OID_SUPPORTED_RESPONSE_LENGTH, \ + UX_DEVICE_CLASS_RNDIS_MAX(UX_DEVICE_CLASS_RNDIS_VENDOR_DESCRIPTION_MAX_RESPONSE_LENGTH, \ + UX_DEVICE_CLASS_RNDIS_NODE_ID_RESPONSE_LENGTH))))))) & (~0x3)) + 0x4) + +/* Ensure maximum-sized RNDIS response can fit in the control endpoint's transfer buffer. */ +#if UX_DEVICE_CLASS_RNDIS_MAX_CONTROL_RESPONSE_LENGTH > UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH +#error "Error: the maximum-sized RNDIS response cannot fit inside the control endpoint's data buffer. Increase UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH." +#endif + +/* Define Slave RNDIS Class Calling Parameter structure */ + +typedef struct UX_SLAVE_CLASS_RNDIS_PARAMETER_STRUCT +{ + VOID (*ux_slave_class_rndis_instance_activate)(VOID *); + VOID (*ux_slave_class_rndis_instance_deactivate)(VOID *); + ULONG ux_slave_class_rndis_parameter_media; + ULONG ux_slave_class_rndis_parameter_vendor_id; + ULONG ux_slave_class_rndis_parameter_driver_version; + UCHAR ux_slave_class_rndis_parameter_vendor_description[UX_DEVICE_CLASS_RNDIS_VENDOR_DESCRIPTION_MAX_LENGTH]; + UCHAR ux_slave_class_rndis_parameter_local_node_id[UX_DEVICE_CLASS_RNDIS_NODE_ID_LENGTH]; + UCHAR ux_slave_class_rndis_parameter_remote_node_id[UX_DEVICE_CLASS_RNDIS_NODE_ID_LENGTH]; + NX_IP *ux_slave_class_rndis_parameter_nx_ip; + ULONG ux_slave_class_rndis_parameter_nx_ip_address; + ULONG ux_slave_class_rndis_parameter_nx_ip_network_mask; + +} UX_SLAVE_CLASS_RNDIS_PARAMETER; + +/* Define RNDIS Class structure. */ + +typedef struct UX_SLAVE_CLASS_RNDIS_STRUCT +{ + UX_SLAVE_INTERFACE *ux_slave_class_rndis_interface; + UX_SLAVE_CLASS_RNDIS_PARAMETER ux_slave_class_rndis_parameter; + UX_SEMAPHORE ux_slave_class_rndis_semaphore; + UX_SLAVE_ENDPOINT *ux_slave_class_rndis_interrupt_endpoint; + UX_SLAVE_ENDPOINT *ux_slave_class_rndis_bulkin_endpoint; + UX_SLAVE_ENDPOINT *ux_slave_class_rndis_bulkout_endpoint; + UCHAR ux_slave_class_rndis_response[UX_DEVICE_CLASS_RNDIS_MAX_CONTROL_RESPONSE_LENGTH]; + ULONG ux_slave_class_rndis_response_length; + ULONG ux_slave_class_rndis_state; + ULONG ux_slave_class_rndis_major_version; + ULONG ux_slave_class_rndis_minor_version; + ULONG ux_slave_class_rndis_max_transfer_size; + ULONG ux_slave_class_rndis_request_id; + ULONG ux_slave_class_rndis_statistics_xmit_ok; + ULONG ux_slave_class_rndis_statistics_rcv_ok; + ULONG ux_slave_class_rndis_statistics_xmit_error; + ULONG ux_slave_class_rndis_statistics_rcv_error; + ULONG ux_slave_class_rndis_statistics_rcv_no_buffer; + ULONG ux_slave_class_rndis_statistics_rcv_error_alignment; + ULONG ux_slave_class_rndis_statistics_xmit_one_collision; + ULONG ux_slave_class_rndis_statistics_xmit_more_collisions; + UX_EVENT_FLAGS_GROUP ux_slave_class_rndis_event_flags_group; + UCHAR ux_slave_class_rndis_local_node_id[UX_DEVICE_CLASS_RNDIS_NODE_ID_LENGTH]; + UCHAR ux_slave_class_rndis_remote_node_id[UX_DEVICE_CLASS_RNDIS_NODE_ID_LENGTH]; + NX_IP *ux_slave_class_rndis_nx_ip; + ULONG ux_slave_class_rndis_nx_ip_address; + ULONG ux_slave_class_rndis_nx_ip_network_mask; + NX_INTERFACE *ux_slave_class_rndis_nx_interface; + NX_PACKET *ux_slave_class_rndis_xmit_queue; + NX_PACKET *ux_slave_class_rndis_receive_queue; + UCHAR *ux_slave_class_rndis_pool_memory; + NX_PACKET_POOL ux_slave_class_rndis_packet_pool; + UX_THREAD ux_slave_class_rndis_interrupt_thread; + UX_THREAD ux_slave_class_rndis_bulkin_thread; + UX_THREAD ux_slave_class_rndis_bulkout_thread; + UCHAR *ux_slave_class_rndis_interrupt_thread_stack; + UCHAR *ux_slave_class_rndis_bulkin_thread_stack; + UCHAR *ux_slave_class_rndis_bulkout_thread_stack; + ULONG ux_slave_class_rndis_link_state; + UX_MUTEX ux_slave_class_rndis_mutex; + VOID *ux_slave_class_rndis_network_handle; + +} UX_SLAVE_CLASS_RNDIS; + + +/* Requests - Ethernet Networking Control Model */ + +#define UX_DEVICE_CLASS_RNDIS_SEND_ENCAPSULATED_COMMAND 0x00 + /* Issues a command in the format of the supported control + protocol. The intent of this mechanism is to support + networking devices (e.g., host-based cable modems) + that require an additional vendor-defined interface for + media specific hardware configuration and + management. */ +#define UX_DEVICE_CLASS_RNDIS_GET_ENCAPSULATED_RESPONSE 0x01 + /* Requests a response in the format of the supported + control protocol. */ + + +/* Define buffer length for IN/OUT pipes. */ + +#define UX_DEVICE_CLASS_RNDIS_BUFFER_SIZE 4096 + + +/* Define Device RNDIS Class prototypes. */ + +UINT _ux_device_class_rndis_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_rndis_control_request(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_rndis_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_rndis_entry(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_rndis_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_rndis_write(VOID *rndis_class, NX_PACKET *packet); +UINT _ux_device_class_rndis_msg_query(UX_SLAVE_CLASS_RNDIS *rndis, UX_SLAVE_TRANSFER *transfer_request); +UINT _ux_device_class_rndis_msg_reset(UX_SLAVE_CLASS_RNDIS *rndis, UX_SLAVE_TRANSFER *transfer_request); +UINT _ux_device_class_rndis_msg_set(UX_SLAVE_CLASS_RNDIS *rndis, UX_SLAVE_TRANSFER *transfer_request); +UINT _ux_device_class_rndis_msg_initialize(UX_SLAVE_CLASS_RNDIS *rndis, UX_SLAVE_TRANSFER *transfer_request); +UINT _ux_device_class_rndis_msg_keep_alive(UX_SLAVE_CLASS_RNDIS *rndis, UX_SLAVE_TRANSFER *transfer_request); +VOID _ux_device_class_rndis_interrupt_thread(ULONG rndis_class); +VOID _ux_device_class_rndis_bulkin_thread(ULONG rndis_class); +VOID _ux_device_class_rndis_bulkout_thread(ULONG rndis_class); + + +/* Define Device RNDIS Class API prototypes. */ + +#define ux_device_class_rndis_entry _ux_device_class_rndis_entry + + +/* Define OID supported List. */ +extern ULONG ux_device_class_rndis_oid_supported_list[]; + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif /* UX_DEVICE_CLASS_RNDIS_H */ diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_storage.h b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_storage.h new file mode 100644 index 00000000..868d69f0 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/inc/ux_device_class_storage.h @@ -0,0 +1,655 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_device_class_storage.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX device storage class. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 08-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* added extern "C" keyword */ +/* for compatibility with C++, */ +/* resulting in version 6.1.8 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* improved TAG management, */ +/* resulting in version 6.1.9 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DEVICE_CLASS_STORAGE_H +#define UX_DEVICE_CLASS_STORAGE_H + +/* Determine if a C++ compiler is being used. If so, ensure that standard + C is used to process the API information. */ + +#ifdef __cplusplus + +/* Yes, C++ compiler is present. Use standard C. */ +extern "C" { + +#endif + +/* Define User configurable Storage Class constants. */ + +#ifndef UX_MAX_SLAVE_LUN +#define UX_MAX_SLAVE_LUN 2 +#endif + + +/* Define Storage Class USB Class constants. */ + +#define UX_SLAVE_CLASS_STORAGE_CLASS 8 +#define UX_SLAVE_CLASS_STORAGE_SUBCLASS_RBC 1 +#define UX_SLAVE_CLASS_STORAGE_SUBCLASS_SFF8020 2 +#define UX_SLAVE_CLASS_STORAGE_SUBCLASS_UFI 4 +#define UX_SLAVE_CLASS_STORAGE_SUBCLASS_SFF8070 5 +#define UX_SLAVE_CLASS_STORAGE_SUBCLASS_SCSI 6 +#define UX_SLAVE_CLASS_STORAGE_PROTOCOL_CBI 0 +#define UX_SLAVE_CLASS_STORAGE_PROTOCOL_CB 1 +#define UX_SLAVE_CLASS_STORAGE_PROTOCOL_BO 0x50 + +/* Define Storage Class USB MEDIA types. */ +#define UX_SLAVE_CLASS_STORAGE_MEDIA_FAT_DISK 0 +#define UX_SLAVE_CLASS_STORAGE_MEDIA_CDROM 5 +#define UX_SLAVE_CLASS_STORAGE_MEDIA_OPTICAL_DISK 7 +#define UX_SLAVE_CLASS_STORAGE_MEDIA_IOMEGA_CLICK 0x55 + + + +/* Define Storage Class SCSI command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_SCSI_TEST_READY 0x00 +#define UX_SLAVE_CLASS_STORAGE_SCSI_REQUEST_SENSE 0x03 +#define UX_SLAVE_CLASS_STORAGE_SCSI_FORMAT 0x04 +#define UX_SLAVE_CLASS_STORAGE_SCSI_INQUIRY 0x12 +#define UX_SLAVE_CLASS_STORAGE_SCSI_MODE_SENSE_SHORT 0x1a +#define UX_SLAVE_CLASS_STORAGE_SCSI_START_STOP 0x1b +#define UX_SLAVE_CLASS_STORAGE_SCSI_PREVENT_ALLOW_MEDIA_REMOVAL 0x1e +#define UX_SLAVE_CLASS_STORAGE_SCSI_READ_FORMAT_CAPACITY 0x23 +#define UX_SLAVE_CLASS_STORAGE_SCSI_READ_CAPACITY 0x25 +#define UX_SLAVE_CLASS_STORAGE_SCSI_READ16 0x28 +#define UX_SLAVE_CLASS_STORAGE_SCSI_WRITE16 0x2a +#define UX_SLAVE_CLASS_STORAGE_SCSI_VERIFY 0x2f +#define UX_SLAVE_CLASS_STORAGE_SCSI_SYNCHRONIZE_CACHE 0x35 +#define UX_SLAVE_CLASS_STORAGE_SCSI_READ_TOC 0x43 +#define UX_SLAVE_CLASS_STORAGE_SCSI_GET_CONFIGURATION 0x46 +#define UX_SLAVE_CLASS_STORAGE_SCSI_GET_STATUS_NOTIFICATION 0x4A +#define UX_SLAVE_CLASS_STORAGE_SCSI_READ_DISK_INFORMATION 0x51 +#define UX_SLAVE_CLASS_STORAGE_SCSI_MODE_SELECT 0x55 +#define UX_SLAVE_CLASS_STORAGE_SCSI_MODE_SENSE 0x5a +#define UX_SLAVE_CLASS_STORAGE_SCSI_READ32 0xa8 +#define UX_SLAVE_CLASS_STORAGE_SCSI_REPORT_KEY 0xa4 +#define UX_SLAVE_CLASS_STORAGE_SCSI_WRITE32 0xaa +#define UX_SLAVE_CLASS_STORAGE_SCSI_GET_PERFORMANCE 0xac +#define UX_SLAVE_CLASS_STORAGE_SCSI_READ_DVD_STRUCTURE 0xad + +/* Define Storage Class SCSI command block wrapper constants. */ + +#define UX_SLAVE_CLASS_STORAGE_CBW_SIGNATURE_MASK 0x43425355 +#define UX_SLAVE_CLASS_STORAGE_CBW_SIGNATURE 0 +#define UX_SLAVE_CLASS_STORAGE_CBW_TAG 4 +#define UX_SLAVE_CLASS_STORAGE_CBW_DATA_LENGTH 8 +#define UX_SLAVE_CLASS_STORAGE_CBW_FLAGS 12 +#define UX_SLAVE_CLASS_STORAGE_CBW_LUN 13 +#define UX_SLAVE_CLASS_STORAGE_CBW_CB_LENGTH 14 +#define UX_SLAVE_CLASS_STORAGE_CBW_CB 15 +#define UX_SLAVE_CLASS_STORAGE_CBW_LENGTH 31 + +#define UX_DEVICE_CLASS_STORAGE_CBW_FLAG_DIR (1u<<7) +#define UX_DEVICE_CLASS_STORAGE_CBW_FLAG_IN (1u<<7) +#define UX_DEVICE_CLASS_STORAGE_CBW_FLAG_D2H (1u<<7) +#define UX_DEVICE_CLASS_STORAGE_CBW_FLAG_OUT (0u) +#define UX_DEVICE_CLASS_STORAGE_CBW_FLAG_H2D (0u) + + +/* Define Storage Class SCSI response status wrapper constants. */ + +#define UX_SLAVE_CLASS_STORAGE_CSW_SIGNATURE_MASK 0x53425355 +#define UX_SLAVE_CLASS_STORAGE_CSW_SIGNATURE 0 +#define UX_SLAVE_CLASS_STORAGE_CSW_TAG 4 +#define UX_SLAVE_CLASS_STORAGE_CSW_DATA_RESIDUE 8 +#define UX_SLAVE_CLASS_STORAGE_CSW_STATUS 12 +#define UX_SLAVE_CLASS_STORAGE_CSW_LENGTH 13 + + +/* Define Storage Class SCSI inquiry command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_LUN 1 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_PAGE_CODE 2 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_ALLOCATION_LENGTH 4 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_COMMAND_LENGTH_UFI 12 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_COMMAND_LENGTH_SBC 06 + + +/* Define Storage Class SCSI inquiry response constants. */ + +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_PERIPHERAL_TYPE 0 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_REMOVABLE_MEDIA 1 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_DATA_FORMAT 3 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_ADDITIONAL_LENGTH 4 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_VENDOR_INFORMATION 8 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_PRODUCT_ID 16 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_PRODUCT_REVISION 32 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_LENGTH 36 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_LENGTH_CD_ROM 0x5b + + +/* Define Storage Class SCSI start/stop command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_START_STOP_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_START_STOP_LBUFLAGS 1 +#define UX_SLAVE_CLASS_STORAGE_START_STOP_START_BIT 4 +#define UX_SLAVE_CLASS_STORAGE_START_STOP_COMMAND_LENGTH_UFI 12 +#define UX_SLAVE_CLASS_STORAGE_START_STOP_COMMAND_LENGTH_SBC 6 + + +/* Define Storage Class SCSI mode sense command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_LUN 1 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PC_PAGE_CODE 2 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_LIST_LENGTH_6 4 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_LIST_LENGTH_10 7 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_ALLOCATION_LENGTH_6 4 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_ALLOCATION_LENGTH_10 7 + +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_MEDIUM_TYPE_6 1 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_MEDIUM_TYPE_10 2 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_FLAGS_6 2 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_FLAGS_10 3 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_FLAG_WP 0x80 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_HEADER_LENGTH_6 4 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_HEADER_LENGTH_10 8 + +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_COMMAND_LENGTH_UFI 12 +#define UX_SLAVE_CLASS_STORAGE_MODE_SENSE_COMMAND_LENGTH_SBC 12 + +#define UX_SLAVE_CLASS_STORAGE_IEC_MODE_PAGE_PAGE_LENGTH 0x0A + +#define UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_PAGE_LENGTH 0x12 +#define UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_CODE 0 +#define UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_LENGTH 1 +#define UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_FLAGS 2 +#define UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_FLAG_WCE (1u<<2) + + +/* Define Storage Class SCSI request sense command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_LUN 1 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_ALLOCATION_LENGTH 4 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_COMMAND_LENGTH_UFI 12 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_COMMAND_LENGTH_SBC 12 + + +/* Define Storage Class request sense response constants. */ + +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_ERROR_CODE 0 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_SENSE_KEY 2 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_INFORMATION 3 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_ADD_LENGTH 7 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_CODE 12 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_CODE_QUALIFIER 13 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_LENGTH 18 +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_HEADER_LENGTH 8 + + +/* Define Storage Class read capacity command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_LUN 1 +#define UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_LBA 2 +#define UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_COMMAND_LENGTH_UFI 12 +#define UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_COMMAND_LENGTH_SBC 10 + + +/* Define Storage Class read capacity response constants. */ + +#define UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LAST_LBA 0 +#define UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_BLOCK_SIZE 4 +#define UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LENGTH 8 + +/* Define Storage Class read capacity response constants. */ + +#define UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_SIZE 0 +#define UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LAST_LBA 4 +#define UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_DESC_CODE 8 +#define UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_BLOCK_SIZE 8 +#define UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LENGTH 12 + +/* Define Storage Class test unit read command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_TEST_READY_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_TEST_READY_LUN 1 +#define UX_SLAVE_CLASS_STORAGE_TEST_READY_COMMAND_LENGTH_UFI 12 +#define UX_SLAVE_CLASS_STORAGE_TEST_READY_COMMAND_LENGTH_SBC 6 + + +/* Define Storage Class SCSI read command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_READ_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_READ_LUN 1 +#define UX_SLAVE_CLASS_STORAGE_READ_LBA 2 +#define UX_SLAVE_CLASS_STORAGE_READ_TRANSFER_LENGTH_32 6 +#define UX_SLAVE_CLASS_STORAGE_READ_TRANSFER_LENGTH_16 7 +#define UX_SLAVE_CLASS_STORAGE_READ_COMMAND_LENGTH_UFI 12 +#define UX_SLAVE_CLASS_STORAGE_READ_COMMAND_LENGTH_SBC 10 + + +/* Define Storage Class SCSI write command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_WRITE_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_WRITE_LUN 1 +#define UX_SLAVE_CLASS_STORAGE_WRITE_LBA 2 +#define UX_SLAVE_CLASS_STORAGE_WRITE_TRANSFER_LENGTH_32 6 +#define UX_SLAVE_CLASS_STORAGE_WRITE_TRANSFER_LENGTH_16 7 +#define UX_SLAVE_CLASS_STORAGE_WRITE_COMMAND_LENGTH_UFI 12 +#define UX_SLAVE_CLASS_STORAGE_WRITE_COMMAND_LENGTH_SBC 10 + + +/* Define Storage Class SCSI sense key definition constants. */ + +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_NO_SENSE 0x0 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_RECOVERED_ERROR 0x1 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_NOT_READY 0x2 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_MEDIUM_ERROR 0x3 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_HARDWARE_ERROR 0x4 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_ILLEGAL_REQUEST 0x5 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_UNIT_ATTENTION 0x6 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_DATA_PROTECT 0x7 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_BLANK_CHECK 0x8 +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_ABORTED_COMMAND 0x0b +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_VOLUME_OVERFLOW 0x0d +#define UX_SLAVE_CLASS_STORAGE_SENSE_KEY_MISCOMPARE 0x0e + + +/* Define Storage Class SCSI sense key definition constants. */ + +#define UX_SLAVE_CLASS_STORAGE_REQUEST_CODE_MEDIA_PROTECTED 0x27 + +/* Define Storage Class SCSI GET CONFIGURATION command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_GET_CONFIGURATION_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_GET_CONFIGURATION_RT 1 +#define UX_SLAVE_CLASS_STORAGE_GET_CONFIGURATION_STARTING_FEATURE 2 +#define UX_SLAVE_CLASS_STORAGE_GET_CONFIGURATION_ALLOCATION_LENGTH 7 +#define UX_SLAVE_CLASS_STORAGE_GET_CONFIGURATION_COMMAND_LENGTH_SBC 9 + +/* Define Storage Class SCSI ASC return codes. */ +#define UX_SLAVE_CLASS_STORAGE_ASC_KEY_INVALID_COMMAND 0x20 + +/* Define Storage Class CSW status. */ + +#define UX_SLAVE_CLASS_STORAGE_CSW_PASSED 0 +#define UX_SLAVE_CLASS_STORAGE_CSW_FAILED 1 +#define UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR 2 + +/* Define generic SCSI values. */ + +#define UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_ERROR_CODE_VALUE 0x70 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_PAGE_CODE_STANDARD 0x00 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_PAGE_CODE_SERIAL 0x80 +#define UX_SLAVE_CLASS_STORAGE_INQUIRY_PERIPHERAL_TYPE 0x00 +#define UX_SLAVE_CLASS_STORAGE_RESET 0xff +#define UX_SLAVE_CLASS_STORAGE_GET_MAX_LUN 0xfe +#define UX_SLAVE_CLASS_STORAGE_MAX_LUN 0 +#define UX_SLAVE_CLASS_STORAGE_RESPONSE_LENGTH 64 + +/* Define Storage Class SCSI read disk information command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_READ_DISK_INFORMATION_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_READ_DISK_INFORMATION_STATUS 2 +#define UX_SLAVE_CLASS_STORAGE_READ_DISK_INFORMATION_ALLOCATION_LENGTH 7 +#define UX_SLAVE_CLASS_STORAGE_READ_DISK_INFORMATION_LENGTH 10 + +/* Define Storage Class Feature Descriptor generic format. */ + +#define USBX_DEVICE_CLASS_STORAGE_FEATURE_DESCRIPTOR_FEATURE_CODE 0 +#define USBX_DEVICE_CLASS_STORAGE_FEATURE_DESCRIPTOR_FEATURE_PARAMETER 2 +#define USBX_DEVICE_CLASS_STORAGE_FEATURE_DESCRIPTOR_FEATURE_ADD_LENGTH 3 +#define USBX_DEVICE_CLASS_STORAGE_FEATURE_DESCRIPTOR_FEATURE_LENGTH 4 + + +/* Define Storage Class SCSI REPORT_KEY command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_OPERATION 0 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ALLOCATION_LENGTH 8 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_FORMAT 10 + +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_LENGTH 8 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_PAYLOAD 6 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_RESET_FIELD 4 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_REGION_MASK 5 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_RPC_SCHEME 6 + + +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_FORMAT_AGID 0 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_FORMAT_CHALLENGE 1 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_FORMAT_KEY2 2 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_FORMAT_TITLE 4 +#define UX_SLAVE_CLASS_STORAGE_REPORT_KEY_FORMAT_RPC 8 + +/* Define Storage Class SCSI get event status notification command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_EVENT_NOTIFICATION_OPCODE 0 +#define UX_SLAVE_CLASS_STORAGE_EVENT_NOTIFICATION_IMMEDIATE 1 +#define UX_SLAVE_CLASS_STORAGE_EVENT_NOTIFICATION_CLASS_REQUEST 4 +#define UX_SLAVE_CLASS_STORAGE_EVENT_NOTIFICATION_ALLOCATION_LENGTH 7 +#define UX_SLAVE_CLASS_STORAGE_EVENT_NOTIFICATION_LENGTH 10 + +/* Define Storage Class SCSI read toc command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_READ_TOC_OPCODE 0 +#define UX_SLAVE_CLASS_STORAGE_READ_TOC_FORMAT 2 +#define UX_SLAVE_CLASS_STORAGE_READ_TOC_TRACK_NUMBER 6 +#define UX_SLAVE_CLASS_STORAGE_READ_TOC_ALLOCATION_LENGTH 7 + +/* Define Storage Class SCSI read DVD structure command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_READ_DVD_STRUCTURE_OPCODE 0 +#define UX_SLAVE_CLASS_STORAGE_READ_DVD_STRUCTURE_ADDRESS 2 +#define UX_SLAVE_CLASS_STORAGE_READ_DVD_STRUCTURE_FORMAT 7 +#define UX_SLAVE_CLASS_STORAGE_READ_DVD_STRUCTURE_ALLOCATION_LENGTH 8 + +#define UX_SLAVE_CLASS_STORAGE_READ_DVD_STRUCTURE_RESP_LENGTH 0 +#define UX_SLAVE_CLASS_STORAGE_READ_DVD_STRUCTURE_BOOK_TYPE 4 +#define UX_SLAVE_CLASS_STORAGE_READ_DVD_STRUCTURE_DS_MR 5 + + +/* Define Storage Class SCSI get performance command constants. */ + +#define UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAGE 1 +#define UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAGE_14 0x14 +#define UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAGE_0 0x00 +#define UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAYLOAD_LENGTH 4 +#define UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_RESPONSE_LENGTH 8 +#define UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAYLOAD 0x20000000 + +/* Define buffer length for IN/OUT pipes. This should match the size of the endpoint maximum buffer size. */ + +#define UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE UX_SLAVE_REQUEST_DATA_MAX_LENGTH + + +/* Define MMC2 CD-ROM / DVD-ROM bit fields */ + +#define UX_SLAVE_CLASS_STORAGE_MMC2_DISK_STATUS_EMPTY 0 +#define UX_SLAVE_CLASS_STORAGE_MMC2_DISK_STATUS_INCOMPLETE 1 +#define UX_SLAVE_CLASS_STORAGE_MMC2_DISK_STATUS_COMPLETE 2 +#define UX_SLAVE_CLASS_STORAGE_MMC2_DISK_STATUS_OTHERS 3 + +#define UX_SLAVE_CLASS_STORAGE_MMC2_LAT_SESSION_EMPTY 0 +#define UX_SLAVE_CLASS_STORAGE_MMC2_LAT_SESSION_INCOMPLETE 1 +#define UX_SLAVE_CLASS_STORAGE_MMC2_LAT_SESSION_COMPLETE 3 + + +/* Define Storage Class SCSI synchronize cache constants. */ + +#define UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_FLAGS 1 +#define UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_LBA 2 +#define UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_NUMBER_OF_BLOCKS 7 + +#define UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_FLAGS_IMMED 0x02 + + +/* Define MODE SENSE Page Codes. */ +#define UX_SLAVE_CLASS_STORAGE_MMC2_PAGE_CODE_CDROM 0x2a + +#define UX_SLAVE_CLASS_STORAGE_PAGE_CODE_CACHE 0x08 +#define UX_SLAVE_CLASS_STORAGE_PAGE_CODE_IEC 0x1C +#define UX_SLAVE_CLASS_STORAGE_PAGE_CODE_ALL 0x3F + +#if defined(UX_DEVICE_STANDALONE) + +/* Define Device Storage Class states. */ + +#define UX_DEVICE_CLASS_STORAGE_STATE_IDLE (UX_STATE_STEP + 0) +#define UX_DEVICE_CLASS_STORAGE_STATE_RESET (UX_STATE_STEP + 1) +#define UX_DEVICE_CLASS_STORAGE_STATE_RESET_WAIT (UX_STATE_STEP + 2) +#define UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START (UX_STATE_STEP + 3) +#define UX_DEVICE_CLASS_STORAGE_STATE_TRANS_WAIT (UX_STATE_STEP + 4) +#define UX_DEVICE_CLASS_STORAGE_STATE_TRANS_NEXT (UX_STATE_STEP + 5) +#define UX_DEVICE_CLASS_STORAGE_STATE_DISK_WAIT (UX_STATE_STEP + 6) +#define UX_DEVICE_CLASS_STORAGE_STATE_DISK_ERROR (UX_STATE_STEP + 7) + +#define UX_DEVICE_CLASS_STORAGE_DISK_IDLE (0) +#define UX_DEVICE_CLASS_STORAGE_DISK_OP_START (1) +#define UX_DEVICE_CLASS_STORAGE_DISK_OP_WAIT (2) +#define UX_DEVICE_CLASS_STORAGE_DISK_OP_NEXT (3) +#define UX_DEVICE_CLASS_STORAGE_DISK_USB_WAIT (4) +#define UX_DEVICE_CLASS_STORAGE_DISK_USB_ERROR (5) + +#define UX_DEVICE_CLASS_STORAGE_BUFFER_IDLE (0) +#define UX_DEVICE_CLASS_STORAGE_BUFFER_EMPTY (1) +#define UX_DEVICE_CLASS_STORAGE_BUFFER_FULL (2) + +#define UX_DEVICE_CLASS_STORAGE_CMD_IDLE (0) +#define UX_DEVICE_CLASS_STORAGE_CMD_CBW (1) +#define UX_DEVICE_CLASS_STORAGE_CMD_ERR (2) +#define UX_DEVICE_CLASS_STORAGE_CMD_CSW (3) +#define UX_DEVICE_CLASS_STORAGE_CMD_WRITE (4) +#define UX_DEVICE_CLASS_STORAGE_CMD_READ (5) +#define UX_DEVICE_CLASS_STORAGE_CMD_DISK_OP (6) + +#endif + +/* Define Slave Storage Class LUN structure. */ + +typedef struct UX_SLAVE_CLASS_STORAGE_LUN_STRUCT +{ + ULONG ux_slave_class_storage_media_last_lba; + ULONG ux_slave_class_storage_media_block_length; + ULONG ux_slave_class_storage_media_type; + ULONG ux_slave_class_storage_media_removable_flag; + ULONG ux_slave_class_storage_media_read_only_flag; + ULONG ux_slave_class_storage_media_id; + ULONG ux_slave_class_storage_request_sense_status; + ULONG ux_slave_class_storage_disk_status; + ULONG ux_slave_class_storage_last_session_state; + + UINT (*ux_slave_class_storage_media_read)(VOID *storage, ULONG lun, UCHAR *data_pointer, ULONG number_blocks, ULONG lba, ULONG *media_status); + UINT (*ux_slave_class_storage_media_write)(VOID *storage, ULONG lun, UCHAR *data_pointer, ULONG number_blocks, ULONG lba, ULONG *media_status); + UINT (*ux_slave_class_storage_media_flush)(VOID *storage, ULONG lun, ULONG number_blocks, ULONG lba, ULONG *media_status); + UINT (*ux_slave_class_storage_media_status)(VOID *storage, ULONG lun, ULONG media_id, ULONG *media_status); + UINT (*ux_slave_class_storage_media_notification)(VOID *storage, ULONG lun, ULONG media_id, ULONG notification_class, UCHAR **media_notification, ULONG *media_notification_length); +} UX_SLAVE_CLASS_STORAGE_LUN; + +/* Sense status value (key at bit0-7, code at bit8-15 and qualifier at bit16-23). */ + +#define UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(key,code,qualifier) (((key) & 0xFF)|(((code) & 0xFF) << 8)|(((qualifier) & 0xFF) << 16)) +#define UX_DEVICE_CLASS_STORAGE_SENSE_KEY(status) ((status) & 0xFF) +#define UX_DEVICE_CLASS_STORAGE_SENSE_CODE(status) (((status) >> 8) & 0xFF) +#define UX_DEVICE_CLASS_STORAGE_SENSE_QUALIFIER(status) (((status) >> 16) & 0xFF) + + +/* Define Slave Storage Class structure. */ + +typedef struct UX_SLAVE_CLASS_STORAGE_STRUCT +{ + UX_SLAVE_INTERFACE *ux_slave_class_storage_interface; + ULONG ux_slave_class_storage_number_lun; + UX_SLAVE_CLASS_STORAGE_LUN ux_slave_class_storage_lun[UX_MAX_SLAVE_LUN]; + ULONG ux_slave_class_storage_host_length; + UCHAR ux_slave_class_storage_cbw_flags; + UCHAR ux_slave_class_storage_cbw_lun; + UCHAR ux_slave_class_storage_reserved[2]; + ULONG ux_slave_class_storage_scsi_tag; + ULONG ux_slave_class_storage_csw_residue; + ULONG ux_slave_class_storage_csw_status; + VOID (*ux_slave_class_storage_instance_activate)(VOID *); + VOID (*ux_slave_class_storage_instance_deactivate)(VOID *); + UCHAR *ux_slave_class_storage_vendor_id; + UCHAR *ux_slave_class_storage_product_id; + UCHAR *ux_slave_class_storage_product_rev; + UCHAR *ux_slave_class_storage_product_serial; + +#if defined(UX_DEVICE_STANDALONE) + UCHAR *ux_device_class_storage_buffer[2]; + UCHAR ux_device_class_storage_buffer_state[2]; + UCHAR ux_device_class_storage_buffer_usb; + UCHAR ux_device_class_storage_buffer_disk; + + UCHAR ux_device_class_storage_cmd; + UCHAR ux_device_class_storage_cmd_state; + UCHAR ux_device_class_storage_disk_state; + UCHAR ux_device_class_storage_state; + + UX_SLAVE_ENDPOINT *ux_device_class_storage_ep_out; + UX_SLAVE_ENDPOINT *ux_device_class_storage_ep_in; + UX_SLAVE_TRANSFER *ux_device_class_storage_transfer; + + ULONG ux_device_class_storage_device_length; + UCHAR *ux_device_class_storage_data_buffer; + ULONG ux_device_class_storage_data_length; + ULONG ux_device_class_storage_data_count; + ULONG ux_device_class_storage_trans_host_length; + ULONG ux_device_class_storage_trans_device_length; + + ULONG ux_device_class_storage_cmd_lba; + ULONG ux_device_class_storage_cmd_n_lb; + ULONG ux_device_class_storage_disk_n_lb; + ULONG ux_device_class_storage_media_status; +#endif + +} UX_SLAVE_CLASS_STORAGE; + +#define UX_DEVICE_CLASS_STORAGE_CSW_STATUS(p) (((UCHAR*)(p))[0]) +#define UX_DEVICE_CLASS_STORAGE_CSW_SKIP(p) (((UCHAR*)(p))[3]) + +/* Define Slave Storage Class Calling Parameter structure */ + +typedef struct UX_SLAVE_CLASS_STORAGE_PARAMETER_STRUCT +{ + VOID (*ux_slave_class_storage_instance_activate)(VOID *); + VOID (*ux_slave_class_storage_instance_deactivate)(VOID *); + ULONG ux_slave_class_storage_parameter_number_lun; + UX_SLAVE_CLASS_STORAGE_LUN ux_slave_class_storage_parameter_lun[UX_MAX_SLAVE_LUN]; + UCHAR *ux_slave_class_storage_parameter_vendor_id; + UCHAR *ux_slave_class_storage_parameter_product_id; + UCHAR *ux_slave_class_storage_parameter_product_rev; + UCHAR *ux_slave_class_storage_parameter_product_serial; + +} UX_SLAVE_CLASS_STORAGE_PARAMETER; + +/* Define Device Storage Class prototypes. */ + +UINT _ux_device_class_storage_initialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_storage_uninitialize(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_storage_activate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_storage_control_request(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_storage_csw_send(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, UCHAR csw_status); +UINT _ux_device_class_storage_deactivate(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_storage_entry(UX_SLAVE_CLASS_COMMAND *command); +UINT _ux_device_class_storage_format(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_inquiry(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_mode_select(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_mode_sense(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_prevent_allow_media_removal(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb); +UINT _ux_device_class_storage_read(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb, UCHAR scsi_command); +UINT _ux_device_class_storage_read_capacity(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_read_format_capacity(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_read_toc(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb); +UINT _ux_device_class_storage_request_sense(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_start_stop(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_test_ready(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +VOID _ux_device_class_storage_thread(ULONG storage_instance); +UINT _ux_device_class_storage_verify(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_write(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb, UCHAR scsi_command); +UINT _ux_device_class_storage_synchronize_cache(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb, UCHAR scsi_command); +UINT _ux_device_class_storage_read_disk_information(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); + +UINT _ux_device_class_storage_get_configuration(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_get_status_notification(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); +UINT _ux_device_class_storage_report_key(UX_SLAVE_CLASS_STORAGE *storage, + ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, + UCHAR *cbwcb); + +UINT _ux_device_class_storage_get_performance(UX_SLAVE_CLASS_STORAGE *storage, + ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, + UCHAR *cbwcb); +UINT _ux_device_class_storage_read_dvd_structure(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb); + +UINT _ux_device_class_storage_tasks_run(VOID *instance); + +/* Define Device Storage Class API prototypes. */ + +#define ux_device_class_storage_entry _ux_device_class_storage_entry + +/* Determine if a C++ compiler is being used. If so, complete the standard + C conditional started above. */ +#ifdef __cplusplus +} +#endif + +#endif diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_activate.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_activate.c new file mode 100644 index 00000000..8779b994 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_activate.c @@ -0,0 +1,165 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_activate PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function activates the USB storage device. */ +/* */ +/* INPUT */ +/* */ +/* command Pointer to storage command */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_thread_resume Resume thread */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_activate(UX_SLAVE_CLASS_COMMAND *command) +{ + +UINT status = UX_SUCCESS; +UX_SLAVE_INTERFACE *interface; +UX_SLAVE_CLASS_STORAGE *storage; +UX_SLAVE_CLASS *class_inst; +#if defined(UX_DEVICE_STANDALONE) +UX_SLAVE_ENDPOINT *endpoint; +#endif + + + /* Get the class container. */ + class_inst = command -> ux_slave_class_command_class_ptr; + + /* Get the class instance in the container. */ + storage = (UX_SLAVE_CLASS_STORAGE *)class_inst -> ux_slave_class_instance; + + /* Get the interface that owns this instance. */ + interface = (UX_SLAVE_INTERFACE *) command -> ux_slave_class_command_interface; + + /* Store the class instance into the interface. */ + interface -> ux_slave_interface_class_instance = (VOID *)storage; + + /* Now the opposite, store the interface in the class instance. */ + storage -> ux_slave_class_storage_interface = interface; + +#if !defined(UX_DEVICE_STANDALONE) + + /* Resume thread. */ + _ux_device_thread_resume(&class_inst -> ux_slave_class_thread); + +#else + + /* Locate the endpoints. */ + /* Check the first endpoint direction, if IN we have the correct endpoint. */ + endpoint = interface -> ux_slave_interface_first_endpoint; + if ((endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress & UX_ENDPOINT_DIRECTION) != UX_ENDPOINT_IN) + { + + /* Wrong direction, we found the OUT endpoint first. */ + storage -> ux_device_class_storage_ep_out = endpoint; + + /* So the next endpoint has to be the IN endpoint. */ + storage -> ux_device_class_storage_ep_in = endpoint -> ux_slave_endpoint_next_endpoint; + } + else + { + + /* We found the IN endpoint first. */ + storage -> ux_device_class_storage_ep_in = endpoint; + + /* So the next endpoint has to be the OUT endpoint. */ + storage -> ux_device_class_storage_ep_out = endpoint -> ux_slave_endpoint_next_endpoint; + } + + /* Reset states. */ + storage -> ux_device_class_storage_buffer[0] = storage -> ux_device_class_storage_ep_out -> + ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer; + storage -> ux_device_class_storage_buffer[1] = storage -> ux_device_class_storage_ep_in -> + ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer; + storage -> ux_device_class_storage_data_buffer = UX_NULL; + storage -> ux_device_class_storage_state = UX_STATE_RESET; + storage -> ux_device_class_storage_disk_state = UX_DEVICE_CLASS_STORAGE_DISK_IDLE; + storage -> ux_device_class_storage_buffer_state[0] = UX_DEVICE_CLASS_STORAGE_BUFFER_IDLE; + storage -> ux_device_class_storage_buffer_state[1] = UX_DEVICE_CLASS_STORAGE_BUFFER_IDLE; + storage -> ux_device_class_storage_buffer_usb = 0; + storage -> ux_device_class_storage_buffer_disk = 0; + UX_SLAVE_TRANSFER_STATE_RESET(&storage -> ux_device_class_storage_ep_out -> ux_slave_endpoint_transfer_request); + UX_SLAVE_TRANSFER_STATE_RESET(&storage -> ux_device_class_storage_ep_in -> ux_slave_endpoint_transfer_request); + + status = UX_SUCCESS; +#endif + + /* If there is a activate function call it. */ + if (storage -> ux_slave_class_storage_instance_activate != UX_NULL) + { + /* Invoke the application. */ + storage -> ux_slave_class_storage_instance_activate(storage); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_ACTIVATE, storage, 0, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_REGISTER(UX_TRACE_DEVICE_OBJECT_TYPE_INTERFACE, storage, 0, 0, 0) + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_control_request.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_control_request.c new file mode 100644 index 00000000..62bf01e7 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_control_request.c @@ -0,0 +1,196 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_control_request PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function manages the based sent by the host on the control */ +/* endpoints with a CLASS or VENDOR SPECIFIC type. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_stack_transfer_abort Abort Transfer */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_control_request(UX_SLAVE_CLASS_COMMAND *command) +{ + +UX_SLAVE_TRANSFER *transfer_request; +UX_SLAVE_DEVICE *device; +UX_SLAVE_CLASS *class; +ULONG request; +ULONG request_value; +ULONG request_length; +UX_SLAVE_CLASS_STORAGE *storage; +#if !defined(UX_DEVICE_STANDALONE) +UX_SLAVE_INTERFACE *interface; +#endif +UX_SLAVE_ENDPOINT *endpoint_in; +UX_SLAVE_ENDPOINT *endpoint_out; + + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Get the pointer to the transfer request associated with the control endpoint. */ + transfer_request = &device -> ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request; + + /* Extract the request type from the SETUP packet.. */ + request = *(transfer_request -> ux_slave_transfer_request_setup + UX_SETUP_REQUEST); + request_value = _ux_utility_short_get(transfer_request -> ux_slave_transfer_request_setup + UX_SETUP_VALUE); + request_length = _ux_utility_short_get(transfer_request -> ux_slave_transfer_request_setup + UX_SETUP_LENGTH); + + /* Check if wValue is valid. */ + if (request_value != 0) + return(UX_ERROR); + + /* Get the class container. */ + class = command -> ux_slave_class_command_class_ptr; + + /* Get the storage instance from this class container. */ + storage = (UX_SLAVE_CLASS_STORAGE *) class -> ux_slave_class_instance; + + /* Here we proceed only the standard request we know of at the device level. */ + switch (request) + { + + case UX_SLAVE_CLASS_STORAGE_RESET: + + /* Check if wLength is valid. */ + if (request_length != 0) + return(UX_ERROR); + +#if defined(UX_DEVICE_STANDALONE) + endpoint_in = storage -> ux_device_class_storage_ep_in; + endpoint_out = storage -> ux_device_class_storage_ep_out; +#else + + /* We need the interface to the class. */ + interface = storage -> ux_slave_class_storage_interface; + + /* Locate the endpoints. */ + endpoint_in = interface -> ux_slave_interface_first_endpoint; + + /* Check the endpoint direction, if IN we have the correct endpoint. */ + if ((endpoint_in -> ux_slave_endpoint_descriptor.bEndpointAddress & UX_ENDPOINT_DIRECTION) != UX_ENDPOINT_IN) + { + + /* Wrong direction, we found the OUT endpoint first. */ + endpoint_out = endpoint_in; + + /* So the next endpoint has to be the IN endpoint. */ + endpoint_in = endpoint_out -> ux_slave_endpoint_next_endpoint; + } + else + { + + /* We found the endpoint IN first, so next endpoint is OUT. */ + endpoint_out = endpoint_in -> ux_slave_endpoint_next_endpoint; + } +#endif + + /* First cancel any transfer on the endpoint OUT, from the host. */ + transfer_request = &endpoint_out -> ux_slave_endpoint_transfer_request; + _ux_device_stack_transfer_abort(transfer_request, UX_TRANSFER_APPLICATION_RESET); + + /* Then cancel any transfer on the endpoint IN, from the host. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + _ux_device_stack_transfer_abort(transfer_request, UX_TRANSFER_APPLICATION_RESET); + + /* Reset phase error. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + break; + + case UX_SLAVE_CLASS_STORAGE_GET_MAX_LUN: + + /* Check if wLength is valid. */ + if (request_length < 1) + return(UX_ERROR); + + /* Set the value of the number of LUN in the buffer. The max number of LUN is the + number of declared LUN - 1. */ + *transfer_request -> ux_slave_transfer_request_data_pointer = (UCHAR)(storage -> ux_slave_class_storage_number_lun -1); + + /* Set the phase of the transfer to data out. */ + transfer_request -> ux_slave_transfer_request_phase = UX_TRANSFER_PHASE_DATA_OUT; + + /* We can return the LUN number. */ + _ux_device_stack_transfer_request(transfer_request, 1, 1); + break; + + default: + + /* Unknown function. It's not handled. */ + return(UX_ERROR); + } + + /* It's handled. */ + return(UX_SUCCESS); +} diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_csw_send.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_csw_send.c new file mode 100644 index 00000000..f1ad7289 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_csw_send.c @@ -0,0 +1,164 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + +#if UX_SLAVE_REQUEST_DATA_MAX_LENGTH < UX_SLAVE_CLASS_STORAGE_CSW_LENGTH +#error UX_SLAVE_REQUEST_DATA_MAX_LENGTH too small, please check +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_csw_send PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function sends the status phase of SCSI transaction. Note that */ +/* dCSWDataResidue is always set to 0 because we either transfer all */ +/* the data, or report command failure. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* status Status of CSW */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_utility_long_put Put long word */ +/* _ux_utility_memory_copy Copy memory */ +/* _ux_utility_memory_set Set memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* improved TAG management, */ +/* resulting in version 6.1.9 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_csw_send(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, UCHAR csw_status) +{ + +UINT status = UX_SUCCESS; +UX_SLAVE_TRANSFER *transfer_request; +UCHAR *csw_buffer; + + + UX_PARAMETER_NOT_USED(csw_status); + UX_PARAMETER_NOT_USED(lun); + +#if defined(UX_DEVICE_STANDALONE) + + /* Reset transfer request buffer pointers. */ + storage -> ux_device_class_storage_ep_out -> ux_slave_endpoint_transfer_request. + ux_slave_transfer_request_data_pointer = storage -> ux_device_class_storage_buffer[0]; + storage -> ux_device_class_storage_ep_in -> ux_slave_endpoint_transfer_request. + ux_slave_transfer_request_data_pointer = storage -> ux_device_class_storage_buffer[1]; +#endif + + /* If CSW skipped, just return. */ + if (UX_DEVICE_CLASS_STORAGE_CSW_SKIP(&storage -> ux_slave_class_storage_csw_status)) + return(UX_SUCCESS); + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Get CSW buffer pointer. */ + csw_buffer = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Ensure it is cleaned. */ + _ux_utility_memory_set(csw_buffer, 0, UX_SLAVE_CLASS_STORAGE_CSW_LENGTH); /* Use case of memset is verified. */ + + /* Store the signature of the CSW. */ + _ux_utility_long_put(&csw_buffer[UX_SLAVE_CLASS_STORAGE_CSW_SIGNATURE], UX_SLAVE_CLASS_STORAGE_CSW_SIGNATURE_MASK); + + /* Store the SCSI tag from the CBW. */ + _ux_utility_long_put(&csw_buffer[UX_SLAVE_CLASS_STORAGE_CSW_TAG], storage -> ux_slave_class_storage_scsi_tag); + + /* Store the dCSWDataResidue. */ + _ux_utility_long_put(&csw_buffer[UX_SLAVE_CLASS_STORAGE_CSW_DATA_RESIDUE], storage -> ux_slave_class_storage_csw_residue); + + /* Store the status of the previous operation. */ + csw_buffer[UX_SLAVE_CLASS_STORAGE_CSW_STATUS] = (UCHAR)storage -> ux_slave_class_storage_csw_status; + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (CSW). */ + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_CSW; + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_transfer = transfer_request; + + storage -> ux_device_class_storage_device_length = UX_SLAVE_CLASS_STORAGE_CSW_LENGTH; + storage -> ux_device_class_storage_data_length = UX_SLAVE_CLASS_STORAGE_CSW_LENGTH; + storage -> ux_device_class_storage_data_count = 0; + +#else + + /* We may be in a special state machine condition where the endpoint is stalled waiting for + a CLEAR_FEATURE. We will wait until the host clears the endpoint. + The transfer_request function does that. */ + /* Send the CSW back to the host. */ + status = _ux_device_stack_transfer_request(transfer_request, UX_SLAVE_CLASS_STORAGE_CSW_LENGTH, + UX_SLAVE_CLASS_STORAGE_CSW_LENGTH); +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_deactivate.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_deactivate.c new file mode 100644 index 00000000..9e6bd197 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_deactivate.c @@ -0,0 +1,143 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_deactivate PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deactivate an instance of the storage class. */ +/* */ +/* INPUT */ +/* */ +/* command Pointer to a class command */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_all_request_abort Abort all transfers */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_deactivate(UX_SLAVE_CLASS_COMMAND *command) +{ + +UX_SLAVE_CLASS_STORAGE *storage; +UX_SLAVE_ENDPOINT *endpoint_in; +UX_SLAVE_ENDPOINT *endpoint_out; +UX_SLAVE_CLASS *class; + + /* Get the class container. */ + class = command -> ux_slave_class_command_class_ptr; + + /* Get the class instance in the container. */ + storage = (UX_SLAVE_CLASS_STORAGE *)class -> ux_slave_class_instance; + +#if defined(UX_DEVICE_STANDALONE) + + endpoint_in = storage -> ux_device_class_storage_ep_in; + endpoint_out = storage -> ux_device_class_storage_ep_out; + _ux_device_stack_transfer_all_request_abort(endpoint_in, UX_TRANSFER_BUS_RESET); + _ux_device_stack_transfer_all_request_abort(endpoint_out, UX_TRANSFER_BUS_RESET); + endpoint_out -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer = + storage -> ux_device_class_storage_buffer[0]; + endpoint_in -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer = + storage -> ux_device_class_storage_buffer[1]; +#else + + /* Locate the endpoints. */ + endpoint_in = storage -> ux_slave_class_storage_interface -> ux_slave_interface_first_endpoint; + + /* Check the endpoint direction, if IN we have the correct endpoint. */ + if ((endpoint_in -> ux_slave_endpoint_descriptor.bEndpointAddress & UX_ENDPOINT_DIRECTION) != UX_ENDPOINT_IN) + { + + /* Wrong direction, we found the OUT endpoint first. */ + endpoint_out = endpoint_in; + + /* So the next endpoint has to be the IN endpoint. */ + endpoint_in = endpoint_out -> ux_slave_endpoint_next_endpoint; + } + else + { + + /* We found the endpoint IN first, so next endpoint is OUT. */ + endpoint_out = endpoint_in -> ux_slave_endpoint_next_endpoint; + } + + /* Terminate the transactions pending on the endpoints. */ + _ux_device_stack_transfer_all_request_abort(endpoint_in, UX_TRANSFER_BUS_RESET); + _ux_device_stack_transfer_all_request_abort(endpoint_out, UX_TRANSFER_BUS_RESET); +#endif + + /* If there is a deactivate function call it. */ + if (storage -> ux_slave_class_storage_instance_deactivate != UX_NULL) + { + + /* Invoke the application. */ + storage -> ux_slave_class_storage_instance_deactivate(storage); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_DEACTIVATE, storage, 0, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_UNREGISTER(storage); + + /* Return completion status. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_entry.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_entry.c new file mode 100644 index 00000000..a59b4fc0 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_entry.c @@ -0,0 +1,155 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_entry PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the entry point of the device storage class. It */ +/* will be called by the device stack enumeration module when the */ +/* host has sent a SET_CONFIGURATION command and the storage interface */ +/* needs to be mounted. */ +/* */ +/* INPUT */ +/* */ +/* command Pointer to class command */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_initialize Initialize storage class */ +/* _ux_device_class_storage_uninitialize Uninitialize storage class */ +/* _ux_device_class_storage_activate Activate storage class */ +/* _ux_device_class_storage_deactivate Deactivate storage class */ +/* _ux_device_class_storage_control_request */ +/* Request control */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_entry(UX_SLAVE_CLASS_COMMAND *command) +{ + +UINT status; + + + /* The command request will tell us we need to do here, either a enumeration + query, an activation or a deactivation. */ + switch (command -> ux_slave_class_command_request) + { + + case UX_SLAVE_CLASS_COMMAND_INITIALIZE: + + /* Call the init function of the Storage class. */ + status = _ux_device_class_storage_initialize(command); + + /* Return the completion status. */ + return(status); + + case UX_SLAVE_CLASS_COMMAND_UNINITIALIZE: + + /* Call the init function of the Storage class. */ + status = _ux_device_class_storage_uninitialize(command); + + /* Return the completion status. */ + return(status); + + + case UX_SLAVE_CLASS_COMMAND_QUERY: + + /* Check the CLASS definition in the interface descriptor. */ + if (command -> ux_slave_class_command_class == UX_SLAVE_CLASS_STORAGE_CLASS) + return(UX_SUCCESS); + else + return(UX_NO_CLASS_MATCH); + + case UX_SLAVE_CLASS_COMMAND_ACTIVATE: + + /* The activate command is used when the host has sent a SET_CONFIGURATION command + and this interface has to be mounted. Both Bulk endpoints have to be mounted + and the storage thread needs to be activated. */ + status = _ux_device_class_storage_activate(command); + + /* Return the completion status. */ + return(status); + + case UX_SLAVE_CLASS_COMMAND_DEACTIVATE: + + /* The deactivate command is used when the device has been extracted. + The device endpoints have to be dismounted and the storage thread canceled. */ + status = _ux_device_class_storage_deactivate(command); + + /* Return the completion status. */ + return(status); + + case UX_SLAVE_CLASS_COMMAND_REQUEST: + + /* The request command is used when the host sends a command on the control endpoint. */ + status = _ux_device_class_storage_control_request(command); + + /* Return the completion status. */ + return(status); + + default: + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_CLASS, UX_FUNCTION_NOT_SUPPORTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_FUNCTION_NOT_SUPPORTED, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return an error. */ + return(UX_FUNCTION_NOT_SUPPORTED); + } +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_format.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_format.c new file mode 100644 index 00000000..a98777cb --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_format.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_format PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function formats the local media. It is not supported in this */ +/* release. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_endpoint_stall Endpoint stall */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_format(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb) +{ + + UX_PARAMETER_NOT_USED(cbwcb); + UX_PARAMETER_NOT_USED(endpoint_in); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_FORMAT, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + +#if !defined(UX_DEVICE_STANDALONE) + + /* This command is not yet supported. So Stall the endpoint. We stall the + OUT endpoint because we expect the host to send parameters. */ + _ux_device_stack_endpoint_stall(endpoint_out); +#else + + UX_PARAMETER_NOT_USED(endpoint_out); +#endif + + /* And update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(0x05,0x26,0x01); + + /* Now we set the CSW with failure. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_FUNCTION_NOT_SUPPORTED, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return not supported error. */ + return(UX_FUNCTION_NOT_SUPPORTED); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_configuration.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_configuration.c new file mode 100644 index 00000000..617dbb61 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_configuration.c @@ -0,0 +1,545 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_PROFILE_LENGTH 228 +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_HEADER_LENGTH 8 +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_DESCRIPTOR_LENGTH 32 +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_HEADER_LENGTH 4 +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_LENGTH (USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_PROFILE_LENGTH - USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_DESCRIPTOR_LENGTH - USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_HEADER_LENGTH) +UCHAR usbx_device_class_storage_configuration_profile[] = { + + /* Feature Header */ + 0x00, 0x00, /* Entire length of profile filled by firmware */ + 0x00, 0x00, + 0x00, 0x00, + 0x00, 0x00, /* Current profile */ + + /* Feature Descriptor */ + 0x00, 0x00, /* Feature Code : profile list */ + 0x00, /* Persistent/current */ + 0x1c, /* Additional Length */ + + 0x00, 0x12, 0x00, 0x00, /* DVD-RAM */ + 0x00, 0x11, 0x00, 0x00, /* DVD-R */ + 0x00, 0x10, 0x00, 0x00, /* DVD-ROM */ + 0x00, 0x0A, 0x00, 0x00, /* CD-RW */ + 0x00, 0x09, 0x00, 0x00, /* CD-R */ + 0x00, 0x08, 0x00, 0x00, /* CD-ROM */ + 0x00, 0x02, 0x00, 0x00, /* Writable capable with removable media. */ + + + /* Feature Descriptor */ + 0x00, 0x01, /* Feature Code : core feature */ + 0x0b, /* Persistent/current */ + 0x08, /* Additional Length */ + + 0x00, 0x00, 0x00, 0x07, /* Physical Interface Standard */ + 0x01, 0x00, 0x00, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x02, /* Feature Code : morphing (Ability to notify initiator about + operational changes and accept initiator requests to prevent + operational changes) */ + 0x07, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x02, 0x00, 0x00, 0x00, /* Physical Interface Standard */ + + /* Feature Descriptor */ + 0x00, 0x03, /* Feature Code : Removable Medium (The medium may be removed + from the device ) */ + 0x0b, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x2b, 0x00, 0x00, 0x00, /* Physical Interface Standard */ + + /* Feature Descriptor */ + 0x00, 0x10, /* Feature Code : Random Readable (Read ability for storage devices + with random addressing) */ + 0x00, /* Persistent/current */ + 0x08, /* Additional Length */ + + 0x00, 0x00, 0x08, 0x00, /* */ + 0x00, 0x01, 0x01, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x1d, /* Feature Code : MultiRead (The logical unit can read all CD media types) */ + 0x00, /* Persistent/current */ + 0x00, /* Additional Length */ + + + /* Feature Descriptor */ + 0x00, 0x1e, /* Feature Code : CD Read (The ability to read CD specific structures) */ + 0x08, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x03, 0x00, 0x00, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x1f, /* Feature Code : DVD Read (The ability to read DVD specific structures) */ + 0x08, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x01, 0x00, 0x01, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x20, /* Feature Code : Random Writable (Write support for randomly addressed writes) */ + 0x04, /* Persistent/current */ + 0x0c, /* Additional Length */ + + 0x00, 0x00, 0x00, 0x00, /* */ + 0x00, 0x00, 0x08, 0x00, /* */ + 0x00, 0x00, 0x01, 0x00, /* */ + + + /* Feature Descriptor */ + 0x00, 0x21, /* Feature Code : Incremental Streaming Writable (Write support for sequential recording) */ + 0x0C, /* Persistent/current */ + 0x08, /* Additional Length */ + + 0x00, 0x00, 0x00, 0x00, /* */ + 0x00, 0x00, 0x00, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x23, /* Feature Code : Formattable (Support for formatting of media.) */ + 0x08, /* Persistent/current */ + 0x08, /* Additional Length */ + + 0x00, 0x00, 0x00, 0x00, /* */ + 0x00, 0x00, 0x00, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x24, /* Feature Code : Defect Management (Ability of the drive/media system to provide an + apparently defect-free space.) */ + 0x04, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x80, 0x00, 0x00, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x26, /* Feature Code : Restricted Overwrite (Write support for media that must be written + in multiples of logical blocks.) */ + 0x00, /* Persistent/current */ + 0x00, /* Additional Length */ + + + /* Feature Descriptor */ + 0x00, 0x2d, /* Feature Code : CD Track at Once (Ability to write CD with Track at Once recording) */ + 0x08, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x46, 0x00, 0x3f, 0x0f, /* */ + + /* Feature Descriptor */ + 0x00, 0x2e, /* Feature Code : CD Mastering (The ability to write CD with Session at Once or Raw write methods.) */ + 0x04, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x7f, 0x00, 0x0d, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x2f, /* Feature Code : DVD-R Write (The ability to write DVD specific structures) */ + 0x08, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x4e, 0x00, 0x00, 0x00, /* */ + + + 0x01, 0x00, /* Feature Code : Power Management (Initiator and device directed power management) */ + 0x07, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x00, 0x00, 0x00, 0x00, /* */ + + + 0x01, 0x01, /* Feature Code : S.M.A.R.T. (Self Monitoring Analysis and Reporting Technology (Failure prediction)) */ + 0x00, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x00, 0x00, 0x00, 0x00, /* */ + + 0x01, 0x08, /* Feature Code : Logical Unit serial number (Logical unit has a unique identifier) */ + 0x03, /* Persistent/current */ + 0x10, /* Additional Length */ + + 0x53, 0x31, 0x33, 0x36, /* Serial Number */ + 0x36, 0x59, 0x42, 0x46, + 0x37, 0x30, 0x30, 0x39, + 0x45, 0x48, 0x20, 0x20, + + 0x01, 0x0a, /* Feature Code : Not sure : says FDC STC TOC */ + 0x00, /* Persistent/current */ + 0x0c, /* Additional Length */ + + 0x46, 0x44, 0x43, 0x00, + 0x53, 0x54, 0x43, 0x00, + 0x54, 0x4F, 0x43, 0x00, + }; + + +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_PROFILE_LENGTH 112 +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_HEADER_LENGTH 8 +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_FEATURE_DESCRIPTOR_LENGTH 32 +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_FEATURE_HEADER_LENGTH 4 +#define USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_FEATURE_LENGTH (USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_PROFILE_LENGTH - USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_FEATURE_DESCRIPTOR_LENGTH - USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_HEADER_LENGTH) +UCHAR usbx_device_class_storage_configuration_active_profile[] = { + + /* Feature Header */ + 0x00, 0x00, /* Entire length of profile filled by firmware */ + 0x00, 0x00, + 0x00, 0x00, + 0x00, 0x08, /* Current profile is CD-ROM*/ + + /* Feature Descriptor */ + 0x00, 0x00, /* Feature Code : profile list */ + 0x00, /* Persistent/current */ + 0x1c, /* Additional Length */ + + 0x00, 0x12, 0x00, 0x00, /* DVD-RAM */ + 0x00, 0x11, 0x00, 0x00, /* DVD-R */ + 0x00, 0x10, 0x00, 0x00, /* DVD-ROM */ + 0x00, 0x0A, 0x00, 0x00, /* CD-RW */ + 0x00, 0x09, 0x00, 0x00, /* CD-R */ + 0x00, 0x08, 0x01, 0x00, /* CD-ROM : active profile */ + 0x00, 0x02, 0x00, 0x00, /* Writable capable with removable media. */ + + + /* Feature Descriptor */ + 0x00, 0x01, /* Feature Code : core feature */ + 0x0b, /* Persistent/current */ + 0x08, /* Additional Length */ + + 0x00, 0x00, 0x00, 0x07, /* Physical Interface Standard */ + 0x01, 0x00, 0x00, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x02, /* Feature Code : morphing (Ability to notify initiator about + operational changes and accept initiator requests to prevent + operational changes) */ + 0x07, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x02, 0x00, 0x00, 0x00, /* Physical Interface Standard */ + + /* Feature Descriptor */ + 0x00, 0x03, /* Feature Code : Removable Medium (The medium may be removed + from the device ) */ + 0x0b, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x2b, 0x00, 0x00, 0x00, /* Physical Interface Standard */ + + /* Feature Descriptor */ + 0x00, 0x10, /* Feature Code : Random Readable (Read ability for storage devices + with random addressing) */ + 0x01, /* Persistent/current */ + 0x08, /* Additional Length */ + + 0x00, 0x00, 0x08, 0x00, /* */ + 0x00, 0x01, 0x01, 0x00, /* */ + + /* Feature Descriptor */ + 0x00, 0x1d, /* Feature Code : MultiRead (The logical unit can read all CD media types) */ + 0x01, /* Persistent/current */ + 0x00, /* Additional Length */ + + + /* Feature Descriptor */ + 0x00, 0x1e, /* Feature Code : CD Read (The ability to read CD specific structures) */ + 0x09, /* Persistent/current */ + 0x04, /* Additional Length */ + + 0x03, 0x00, 0x00, 0x00, /* */ + + + 0x01, 0x08, /* Feature Code : Logical Unit serial number (Logical unit has a unique identifier) */ + 0x03, /* Persistent/current */ + 0x10, /* Additional Length */ + + 0x53, 0x31, 0x33, 0x36, /* Serial Number */ + 0x36, 0x59, 0x42, 0x46, + 0x37, 0x30, 0x30, 0x39, + 0x45, 0x48, 0x20, 0x20, + + }; + +#if (UX_SLAVE_REQUEST_DATA_MAX_LENGTH < USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_PROFILE_LENGTH) ||\ + (UX_SLAVE_REQUEST_DATA_MAX_LENGTH < USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_PROFILE_LENGTH) +#error UX_SLAVE_REQUEST_DATA_MAX_LENGTH too small, please check +#endif + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_get_configuration PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a GET_CONFIGURATION command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_utility_short_get_big_endian Get 16-bit big endian */ +/* _ux_utility_long_put_big_endian Put 32-bit big endian */ +/* _ux_utility_memory_copy Copy memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_get_configuration(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status = 0; +UX_SLAVE_TRANSFER *transfer_request; +ULONG starting_feature; +ULONG allocation_length; +ULONG additional_length; +ULONG profile_counter; +UCHAR *profile_pointer; +ULONG feature; + + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_GET_CONFIGURATION, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Initialize the length of the configuration profile. */ + _ux_utility_long_put_big_endian(usbx_device_class_storage_configuration_profile, (USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_PROFILE_LENGTH - 4)); + + /* Initialize the length of the active configuration profile. */ + _ux_utility_long_put_big_endian(usbx_device_class_storage_configuration_active_profile, (USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_PROFILE_LENGTH - 4)); + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Get the Starting Feature. */ + starting_feature = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_GET_CONFIGURATION_STARTING_FEATURE); + + /* Get the allocation length. */ + allocation_length = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_GET_CONFIGURATION_ALLOCATION_LENGTH); + + /* Default CSW to success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Is the request demanding all the features ? */ + if (starting_feature == 0) + { + + /* Is the requester demanding the active profile ? */ + if ((*(cbwcb + UX_SLAVE_CLASS_STORAGE_GET_CONFIGURATION_RT) & 3) == 1) + { + + /* We get the active profile. */ + /* Can we send all the activeconfiguration profile ? If not, the host may demand the first part of the configuration to get the entire length. + In this case, return the length demanded by the host. */ + if (allocation_length >= USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_PROFILE_LENGTH) + + /* Adjust allocation length to maximum allowed. */ + allocation_length = USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_ACTIVE_PROFILE_LENGTH; + + /* Copy the CSW into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer, + usbx_device_class_storage_configuration_active_profile, + allocation_length); /* Use case of memcpy is verified. */ + } + else + { + + /* We get the whole profile. */ + /* Can we send all the configuration profile ? If not, the host may demand the first part of the configuration to get the entire length. + In this case, return the length demanded by the host. */ + if (allocation_length >= USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_PROFILE_LENGTH) + + /* Adjust allocation length to maximum allowed. */ + allocation_length = USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_PROFILE_LENGTH; + + /* Copy the CSW into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer, + usbx_device_class_storage_configuration_profile, + allocation_length); /* Use case of memcpy is verified. */ + + } + + /* Now success. */ + status = UX_SUCCESS; + } + else + { + + /* The caller has demanded a specific feature. Scan our configuration profile. Jump over the beginning sections. */ + profile_pointer = usbx_device_class_storage_configuration_profile + USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_HEADER_LENGTH + + USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_DESCRIPTOR_LENGTH; + profile_counter = USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_LENGTH; + + /* Scan our configuration profile. */ + while (profile_counter != 0) + { + + /* Extract the feature from the configuration profile. */ + feature = _ux_utility_short_get_big_endian(profile_pointer + USBX_DEVICE_CLASS_STORAGE_FEATURE_DESCRIPTOR_FEATURE_CODE); + + /* Extract the feature length from the configuration profile. */ + additional_length = (ULONG ) *(profile_pointer + USBX_DEVICE_CLASS_STORAGE_FEATURE_DESCRIPTOR_FEATURE_ADD_LENGTH); + + /* Compare the Feature extracted with the one demanded. */ + if (feature == starting_feature) + { + + /* We found the feature, we check if the requester has enough space for us to return it. */ + if (allocation_length >= (additional_length + USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_HEADER_LENGTH + + USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_HEADER_LENGTH)) + + /* Need to adjust the allocation length. */ + allocation_length = additional_length + USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_HEADER_LENGTH + + USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_HEADER_LENGTH; + + /* Copy the CSW into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer, + profile_pointer, + allocation_length); /* Use case of memcpy is verified. */ + + /* Now success. */ + status = UX_SUCCESS; + + /* Get out of the loop. */ + break; + } + else + { + + /* We have not yet found the feature, keep parsing. */ + if (profile_counter - additional_length - USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_HEADER_LENGTH <= 0) + { + + /* We are either at the end of the profile or the profile is corrupted. */ + + /* And update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(UX_SLAVE_CLASS_STORAGE_SENSE_KEY_ILLEGAL_REQUEST,0x26,0x02); + + /* Now we set the CSW with failure. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + + /* Set status to error. */ + status = UX_ERROR; + + /* Get out of the loop. */ + break; + + } + else + { + + /* Update the profile pointer. */ + profile_pointer += additional_length + USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_HEADER_LENGTH; + + /* Update the length remaining to parse in profile. */ + profile_counter -= additional_length + USBX_DEVICE_CLASS_STORAGE_CONFIGURATION_FEATURE_HEADER_LENGTH; + } + } + } + } + + /* Success, send data. */ + if (status == UX_SUCCESS) + { + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = allocation_length; + storage -> ux_device_class_storage_data_length = allocation_length; + storage -> ux_device_class_storage_data_count = 0; + UX_SLAVE_TRANSFER_STATE_RESET(storage -> ux_device_class_storage_transfer); +#else + + /* Send a data payload with the read_capacity response buffer. */ + _ux_device_stack_transfer_request(transfer_request, + allocation_length, + allocation_length); +#endif + + } + else + { + + /* Error, stall. */ +#if !defined(UX_DEVICE_STANDALONE) + _ux_device_stack_endpoint_stall(endpoint_in); +#endif + } + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_performance.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_performance.c new file mode 100644 index 00000000..ed5f9819 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_performance.c @@ -0,0 +1,181 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + +#define USBX_DEVICE_CLASS_STORAGE_GET_PERFORMANCE_0_LENGTH 16 +#if UX_SLAVE_REQUEST_DATA_MAX_LENGTH < (USBX_DEVICE_CLASS_STORAGE_GET_PERFORMANCE_0_LENGTH + 8) +#error UX_SLAVE_REQUEST_DATA_MAX_LENGTH too small, please check +#endif +UCHAR usbx_device_class_storage_performance[] = { + + 0x08, 0x00, 0x00, 0x00, 0x00, 0x23, 0x12, 0x80, + 0x00, 0x00, 0x10, 0x89, 0x00, 0x00, 0x10, 0x89 +}; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_get_performance PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a GET_PERFORMANCE SCSI command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_utility_memory_set Set memory */ +/* _ux_utility_memory_copy Copy memory */ +/* _ux_utility_long_put_big_endian Put 32-bit big endian */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_get_performance(UX_SLAVE_CLASS_STORAGE *storage, + ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, + UCHAR *cbwcb) +{ + +UINT status; +UX_SLAVE_TRANSFER *transfer_request; +ULONG performance_page; +ULONG data_length = 0; + + + UX_PARAMETER_NOT_USED(lun); + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_OTHER, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Ensure memory buffer cleaned. */ + _ux_utility_memory_set(transfer_request -> ux_slave_transfer_request_data_pointer, 0, 64); /* Use case of memset is verified. */ + + /* Get the performance page code. */ + performance_page = (ULONG) *(cbwcb + UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAGE); + + /* Filter it as the response depends on it. */ + switch (performance_page) + { + + case UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAGE_14 : + + /* Put the length to be returned. */ + _ux_utility_long_put_big_endian(transfer_request -> ux_slave_transfer_request_data_pointer, + UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAYLOAD_LENGTH); + + /* Put the payload to be returned. */ + _ux_utility_long_put_big_endian(transfer_request -> ux_slave_transfer_request_data_pointer + 4, + UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAYLOAD); + + data_length = UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_RESPONSE_LENGTH; + break; + + case UX_SLAVE_CLASS_STORAGE_GET_PERFORMANCE_PAGE_0 : + + /* Put the length to be returned. */ + _ux_utility_long_put_big_endian(transfer_request -> ux_slave_transfer_request_data_pointer, + USBX_DEVICE_CLASS_STORAGE_GET_PERFORMANCE_0_LENGTH + 8); + + /* Copy the CSW into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer + 8, + usbx_device_class_storage_performance, USBX_DEVICE_CLASS_STORAGE_GET_PERFORMANCE_0_LENGTH); /* Use case of memcpy is verified. */ + + data_length = USBX_DEVICE_CLASS_STORAGE_GET_PERFORMANCE_0_LENGTH + 8; + break; + + default: + data_length = 0; + } + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = data_length; + storage -> ux_device_class_storage_data_length = data_length; + storage -> ux_device_class_storage_data_count = 0; + UX_SLAVE_TRANSFER_STATE_RESET(storage -> ux_device_class_storage_transfer); + +#else + + /* Send a data payload with the read_capacity response buffer. */ + _ux_device_stack_transfer_request(transfer_request, data_length, data_length); +#endif + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + status = UX_SUCCESS; + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_status_notification.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_status_notification.c new file mode 100644 index 00000000..af4b2bb7 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_get_status_notification.c @@ -0,0 +1,198 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_get_status_notification PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a GET_STATUS_NOTIFICATION command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_utility_short_put_big_endian Put 16-bit big endian */ +/* _ux_utility_memory_copy Copy memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_get_status_notification(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status; +UX_SLAVE_TRANSFER *transfer_request; +UCHAR *media_notification; +ULONG media_notification_length; +ULONG notification_class; + + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_READ_CAPACITY, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0); + + /* Default CSW to failed. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + + /* Ensure the callback has been initialized. */ + if (storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_notification == UX_NULL) + { + +#if !defined(UX_DEVICE_STANDALONE) + + /* We need to STALL the IN endpoint. The endpoint will be reset by the host. */ + _ux_device_stack_endpoint_stall(endpoint_in); +#endif + + /* And update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(0x05,0x26,0x01); + + /* Return error. */ + return(UX_FUNCTION_NOT_SUPPORTED); + } + + /* Extract the notification from the cbwcb. */ + notification_class = (ULONG) *(cbwcb + UX_SLAVE_CLASS_STORAGE_EVENT_NOTIFICATION_CLASS_REQUEST); + + /* Obtain the notification of the device. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_notification(storage, lun, + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_id, + notification_class, + &media_notification, + &media_notification_length); + + /* Check the notification length. */ + if (media_notification_length > UX_SLAVE_REQUEST_DATA_MAX_LENGTH - sizeof(USHORT)) + { + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_MEMORY_INSUFFICIENT, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Error callback. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_CLASS, UX_MEMORY_INSUFFICIENT); + + /* Set status code. */ + status = UX_MEMORY_INSUFFICIENT; + } + + /* Check the status for error. */ + if (status != UX_SUCCESS) + { + +#if !defined(UX_DEVICE_STANDALONE) + + /* We need to STALL the IN endpoint. The endpoint will be reset by the host. */ + _ux_device_stack_endpoint_stall(endpoint_in); +#endif + } + else + { + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Put the length of the notification length in the buffer. */ + _ux_utility_short_put_big_endian(transfer_request -> ux_slave_transfer_request_data_pointer, (USHORT)media_notification_length); + + /* Copy the CSW into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer + sizeof (USHORT), + media_notification, + media_notification_length); /* Use case of memcpy is verified. */ + + /* Update the notification length. */ + media_notification_length += (ULONG)sizeof (USHORT); + +#if !defined(UX_DEVICE_STANDALONE) + /* Send a data payload with the notification buffer. */ + _ux_device_stack_transfer_request(transfer_request, + media_notification_length, + media_notification_length); +#else + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = media_notification_length; + storage -> ux_device_class_storage_data_length = media_notification_length; + storage -> ux_device_class_storage_data_count = 0; + UX_SLAVE_TRANSFER_STATE_RESET(storage -> ux_device_class_storage_transfer); +#endif + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + status = UX_SUCCESS; + } + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_initialize.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_initialize.c new file mode 100644 index 00000000..b4b27f20 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_initialize.c @@ -0,0 +1,225 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + +/* Define the Slave Storage Class Inquiry data : DO NOT CHANGE THE LENGTH OF THESE ITEMS */ + +UCHAR _ux_system_slave_class_storage_vendor_id[] = "AzureRTO"; +UCHAR _ux_system_slave_class_storage_product_id[] = "USBX storage dev"; +UCHAR _ux_system_slave_class_storage_product_rev[] = "2000"; +UCHAR _ux_system_slave_class_storage_product_serial[] = "12345678901234567890"; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_initialize PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the USB storage device. */ +/* */ +/* INPUT */ +/* */ +/* command Pointer to storage command */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_allocate Allocate memory */ +/* _ux_utility_memory_free Free memory */ +/* _ux_device_thread_create Create thread */ +/* _ux_device_thread_delete Delete thread */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_initialize(UX_SLAVE_CLASS_COMMAND *command) +{ + +UINT status = UX_SUCCESS; +UX_SLAVE_CLASS_STORAGE *storage; +UX_SLAVE_CLASS_STORAGE_PARAMETER *storage_parameter; +UX_SLAVE_CLASS *class_inst; +ULONG lun_index; + + + /* Get the pointer to the application parameters for the storage class. */ + storage_parameter = command -> ux_slave_class_command_parameter; + + /* Ensure the number of LUN declared by the caller does not exceed the + max number allowed for LUN storage. */ + if (storage_parameter -> ux_slave_class_storage_parameter_number_lun > UX_MAX_SLAVE_LUN) + return UX_ERROR; + + /* Get the class container. */ + class_inst = command -> ux_slave_class_command_class_ptr; + + /* Create an instance of the device storage class. */ + storage = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_SLAVE_CLASS_STORAGE)); + + /* Check for successful allocation. */ + if (storage == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + +#if !defined(UX_DEVICE_STANDALONE) + + /* Allocate some memory for the thread stack. */ + class_inst -> ux_slave_class_thread_stack = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, UX_THREAD_STACK_SIZE); + + /* If it's OK, create thread. */ + if (class_inst -> ux_slave_class_thread_stack != UX_NULL) + + /* This instance needs to be running in a different thread. So start + a new thread. We pass a pointer to the class to the new thread. This thread + does not start until we have a instance of the class. */ + status = _ux_device_thread_create(&class_inst -> ux_slave_class_thread, "ux_slave_storage_thread", + _ux_device_class_storage_thread, + (ULONG) (ALIGN_TYPE) class_inst, (VOID *) class_inst -> ux_slave_class_thread_stack, + UX_THREAD_STACK_SIZE, UX_THREAD_PRIORITY_CLASS, + UX_THREAD_PRIORITY_CLASS, UX_NO_TIME_SLICE, UX_DONT_START); + else + status = UX_MEMORY_INSUFFICIENT; +#else + + /* Save tasks run entry. */ + class_inst -> ux_slave_class_task_function = _ux_device_class_storage_tasks_run; + + status = UX_SUCCESS; +#endif + + /* If thread resources allocated, go on. */ + if (status == UX_SUCCESS) + { + + UX_THREAD_EXTENSION_PTR_SET(&(class_inst -> ux_slave_class_thread), class_inst) + + /* Store the number of LUN declared. */ + storage -> ux_slave_class_storage_number_lun = storage_parameter -> ux_slave_class_storage_parameter_number_lun; + + /* Copy each individual LUN parameters. */ + for (lun_index = 0; lun_index < storage -> ux_slave_class_storage_number_lun; lun_index++) + { + + /* Check block length size. */ + if (storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_block_length > UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE) + { + /* Cannot proceed. */ + status = (UX_MEMORY_INSUFFICIENT); + break; + } + + /* Store all the application parameter information about the media. */ + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_last_lba = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_last_lba; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_block_length = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_block_length; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_type = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_type; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_removable_flag = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_removable_flag; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_read_only_flag = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_read_only_flag; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_read = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_read; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_flush = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_flush; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_write = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_write; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_status = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_status; + storage -> ux_slave_class_storage_lun[lun_index].ux_slave_class_storage_media_notification = storage_parameter -> ux_slave_class_storage_parameter_lun[lun_index].ux_slave_class_storage_media_notification; + } + + /* If it's OK, complete it. */ + if (status == UX_SUCCESS) + { + + /* Store the start and stop signals if needed by the application. */ + storage -> ux_slave_class_storage_instance_activate = storage_parameter -> ux_slave_class_storage_instance_activate; + storage -> ux_slave_class_storage_instance_deactivate = storage_parameter -> ux_slave_class_storage_instance_deactivate; + + /* Store the vendor id, product id, product revision and product serial. */ + if (storage_parameter -> ux_slave_class_storage_parameter_vendor_id) + storage -> ux_slave_class_storage_vendor_id = storage_parameter -> ux_slave_class_storage_parameter_vendor_id; + else + storage -> ux_slave_class_storage_vendor_id = _ux_system_slave_class_storage_vendor_id; + + if (storage_parameter -> ux_slave_class_storage_parameter_product_id) + storage -> ux_slave_class_storage_product_id = storage_parameter -> ux_slave_class_storage_parameter_product_id; + else + storage -> ux_slave_class_storage_product_id = _ux_system_slave_class_storage_product_id; + + if (storage_parameter -> ux_slave_class_storage_parameter_product_rev) + storage -> ux_slave_class_storage_product_rev = storage_parameter -> ux_slave_class_storage_parameter_product_rev; + else + storage -> ux_slave_class_storage_product_rev = _ux_system_slave_class_storage_product_rev; + + if (storage_parameter -> ux_slave_class_storage_parameter_product_serial) + storage -> ux_slave_class_storage_product_serial = storage_parameter -> ux_slave_class_storage_parameter_product_serial; + else + storage -> ux_slave_class_storage_product_serial = _ux_system_slave_class_storage_product_serial; + + /* Save the address of the STORAGE instance inside the STORAGE container. */ + class_inst -> ux_slave_class_instance = (VOID *) storage; + + return(UX_SUCCESS); + } + + /* Free thread resources. */ + _ux_device_thread_delete(&class_inst -> ux_slave_class_thread); + } + +#if !defined(UX_DEVICE_STANDALONE) + if (class_inst -> ux_slave_class_thread_stack != UX_NULL) + _ux_utility_memory_free(&class_inst -> ux_slave_class_thread_stack); +#endif + + /* Free instance. */ + _ux_utility_memory_free(storage); + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_inquiry.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_inquiry.c new file mode 100644 index 00000000..e4520df0 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_inquiry.c @@ -0,0 +1,248 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +#if UX_SLAVE_REQUEST_DATA_MAX_LENGTH < 24 +#error UX_SLAVE_REQUEST_DATA_MAX_LENGTH is too small, please check +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_inquiry PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a INQUIRY command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_utility_memory_copy Copy memory */ +/* _ux_utility_memory_set Set memory */ +/* _ux_utility_short_put_big_endian Put 16-bit big endian */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_inquiry(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status = UX_SUCCESS; +UX_SLAVE_TRANSFER *transfer_request; +UCHAR inquiry_page_code; +ULONG inquiry_length; +UCHAR *inquiry_buffer; + + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_INQUIRY, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + +#if !defined(UX_DEVICE_STANDALONE) + + /* Check direction. */ + if (storage -> ux_slave_class_storage_host_length && + (storage -> ux_slave_class_storage_cbw_flags & 0x80) == 0) + { + _ux_device_stack_endpoint_stall(endpoint_out); + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + return(UX_ERROR); + } +#endif + + /* From the SCSI Inquiry payload, get the page code. */ + inquiry_page_code = *(cbwcb + UX_SLAVE_CLASS_STORAGE_INQUIRY_PAGE_CODE); + + /* And the length to be returned. */ + inquiry_length = storage -> ux_slave_class_storage_host_length; + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Obtain inquiry buffer pointer. */ + inquiry_buffer = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Ensure the data buffer is cleaned. */ + _ux_utility_memory_set(inquiry_buffer, 0, UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_LENGTH); /* Use case of memset is verified. */ + + /* Check for the maximum length to be returned. */ + if (inquiry_length > UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_LENGTH) + inquiry_length = UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_LENGTH; + + /* Default CSW to passed. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Ensure we know about the page code. */ + switch (inquiry_page_code) + { + + case UX_SLAVE_CLASS_STORAGE_INQUIRY_PAGE_CODE_STANDARD: + + /* Store the product type. */ + inquiry_buffer[UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_PERIPHERAL_TYPE] = (UCHAR)storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_type; + + /* Store the Media Removable bit. */ + inquiry_buffer[UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_REMOVABLE_MEDIA] = (UCHAR)storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_removable_flag; + + /* Store the Data Format bit. */ + if (storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_type == UX_SLAVE_CLASS_STORAGE_MEDIA_CDROM) + inquiry_buffer[UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_DATA_FORMAT] = 0x32; + else + inquiry_buffer[UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_DATA_FORMAT] = 0x00; + + /* Store the length of the response. There is a hack here. For CD-ROM, the data lg is fixed to 0x5B ! */ + if (storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_type != UX_SLAVE_CLASS_STORAGE_MEDIA_CDROM) + inquiry_buffer[UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_ADDITIONAL_LENGTH] = UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_LENGTH; + else + inquiry_buffer[UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_ADDITIONAL_LENGTH] = UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_LENGTH_CD_ROM; + + /* Fill in the storage vendor ID. */ + _ux_utility_memory_copy(inquiry_buffer + UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_VENDOR_INFORMATION, + storage -> ux_slave_class_storage_vendor_id, 8); /* Use case of memcpy is verified. */ + + /* Fill in the product vendor ID. */ + _ux_utility_memory_copy(inquiry_buffer + UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_PRODUCT_ID, + storage -> ux_slave_class_storage_product_id, 16); /* Use case of memcpy is verified. */ + + /* Fill in the product revision number. */ + _ux_utility_memory_copy(inquiry_buffer + UX_SLAVE_CLASS_STORAGE_INQUIRY_RESPONSE_PRODUCT_REVISION, + storage -> ux_slave_class_storage_product_rev, 4); /* Use case of memcpy is verified. */ + + break; + + case UX_SLAVE_CLASS_STORAGE_INQUIRY_PAGE_CODE_SERIAL: + + /* Initialize the page code in response buffer. */ + _ux_utility_short_put_big_endian(transfer_request -> ux_slave_transfer_request_data_pointer, UX_SLAVE_CLASS_STORAGE_INQUIRY_PAGE_CODE_SERIAL); + + /* Initialize the length of the serial number in response buffer. */ + _ux_utility_short_put_big_endian(transfer_request -> ux_slave_transfer_request_data_pointer + 2, 20); + + /* Copy the serial number buffer into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer + 4, storage -> ux_slave_class_storage_product_serial, 20); /* Use case of memcpy is verified. */ + + /* Send a data payload with the inquiry response buffer. */ + if (inquiry_length > 24) + inquiry_length = 24; + + break; + + default: + +#if !defined(UX_DEVICE_STANDALONE) + /* The page code is not supported. */ + _ux_device_stack_endpoint_stall(endpoint_in); +#endif + + /* And update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(0x05,0x26,0x01); + + /* Now we set the CSW with failure. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + + /* Return error. */ + status = UX_ERROR; + + break; + } + + /* Error cases. */ + if (status != UX_SUCCESS) + return(status); + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = inquiry_length; + storage -> ux_device_class_storage_data_length = inquiry_length; + storage -> ux_device_class_storage_data_count = 0; + +#else + + /* Send a data payload with the inquiry response buffer. */ + if (inquiry_length) + _ux_device_stack_transfer_request(transfer_request, inquiry_length, inquiry_length); + + /* Check length. */ + if (storage -> ux_slave_class_storage_host_length != inquiry_length) + { + _ux_device_stack_endpoint_stall(endpoint_in); + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_mode_select.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_mode_select.c new file mode 100644 index 00000000..de376b87 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_mode_select.c @@ -0,0 +1,124 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_mode_select PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a MODE_SELECT SCSI command. It is not */ +/* supported in this release. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_mode_select(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + + UX_PARAMETER_NOT_USED(endpoint_in); + UX_PARAMETER_NOT_USED(cbwcb); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_MODE_SELECT, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* This command is not yet supported. So Stall the endpoint. */ + if (storage -> ux_slave_class_storage_host_length) + { + +#if !defined(UX_DEVICE_STANDALONE) + _ux_device_stack_endpoint_stall(endpoint_out); +#else + UX_PARAMETER_NOT_USED(endpoint_out); +#endif + + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length; + } + + /* And update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(0x05,0x26,0x01); + + /* Now we set the CSW with failure. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_CLASS, UX_FUNCTION_NOT_SUPPORTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_FUNCTION_NOT_SUPPORTED, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Return not supported error! */ + return(UX_FUNCTION_NOT_SUPPORTED); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_mode_sense.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_mode_sense.c new file mode 100644 index 00000000..a3ee5443 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_mode_sense.c @@ -0,0 +1,281 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + +#ifdef UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC +#define USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_CDROM_LENGTH (0x42 + 2) +UCHAR usbx_device_class_storage_mode_sense_page_cdrom[USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_CDROM_LENGTH] = { + + 0x2A, 0x42, 0x3F, 0x37, 0xF1, 0x77, 0x29, 0x23, + 0x10, 0x89, 0x01, 0x00, 0x02, 0x00, 0x05, 0x84, + 0x00, 0x10, 0x10, 0x89, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 + +}; +#else +#define USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_CDROM_LENGTH (0) +#endif +#define USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_CACHE_LENGTH (UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_PAGE_LENGTH + 2) +#define USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_IEC_LENGTH (UX_SLAVE_CLASS_STORAGE_IEC_MODE_PAGE_PAGE_LENGTH + 2) + +/* Ensure sense pages can fit in the bulk in endpoint's transfer buffer. */ +#define USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_ALL_RESPONSE_LENGTH ( \ + UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_HEADER_LENGTH_10 + \ + USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_CDROM_LENGTH + \ + USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_CACHE_LENGTH + \ + USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_IEC_LENGTH) +#if USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_ALL_RESPONSE_LENGTH > UX_SLAVE_REQUEST_DATA_MAX_LENGTH +#error "The maximum-sized MODE_SENSE response cannot fit inside the bulk in endpoint's data buffer." +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_mode_sense PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a MODE_SENSE SCSI command. It supports */ +/* the standard page for the CD-ROM. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_utility_short_get_big_endian Get 16-bit big endian */ +/* _ux_utility_short_put_big_endian Put 16-bit big endian */ +/* _ux_utility_memory_set Set memory */ +/* _ux_utility_memory_copy Copy memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_mode_sense(UX_SLAVE_CLASS_STORAGE *storage, + ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, + UCHAR *cbwcb) +{ + +UINT status; +UX_SLAVE_TRANSFER *transfer_request; +ULONG mode_sense_reply_length; +ULONG page_code; +ULONG mode_sense_command; +UCHAR read_only_flag; +ULONG response_header_length; +ULONG flags_index; +ULONG mode_data_length; +UCHAR *page_pointer; +ULONG page_length; + + + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_MODE_SENSE, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Get the command format : we have 1a and 5a. */ + mode_sense_command = (ULONG) *(cbwcb + UX_SLAVE_CLASS_STORAGE_MODE_SENSE_OPERATION); + + /* Extract the notification from the cbwcb. */ + page_code = (ULONG) *(cbwcb + UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PC_PAGE_CODE); + + /* Check the command. */ + if (mode_sense_command == UX_SLAVE_CLASS_STORAGE_SCSI_MODE_SENSE_SHORT) + { + + /* Extract the length to be returned by the cbwcb. */ + mode_sense_reply_length = (ULONG) *(cbwcb + UX_SLAVE_CLASS_STORAGE_MODE_SENSE_ALLOCATION_LENGTH_6); + flags_index = UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_FLAGS_6; + response_header_length = UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_HEADER_LENGTH_6; + } + + else + { + + /* Extract the length to be returned by the cbwcb. */ + mode_sense_reply_length = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_MODE_SENSE_ALLOCATION_LENGTH_10); + flags_index = UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_FLAGS_10; + response_header_length = UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_HEADER_LENGTH_10; + } + + /* Ensure reply not exceed storage buffer. */ + if (mode_sense_reply_length > UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE) + mode_sense_reply_length = UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE; + + /* Ensure memory buffer cleaned. */ + _ux_utility_memory_set(transfer_request -> ux_slave_transfer_request_data_pointer, 0, mode_sense_reply_length); /* Use case of memset is verified. */ + + /* Establish READ ONLY flag. */ + if (storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_read_only_flag == UX_TRUE) + + /* This device is Read Only. */ + read_only_flag = UX_SLAVE_CLASS_STORAGE_MODE_SENSE_PARAMETER_FLAG_WP; + + else + + /* This device can be written to. */ + read_only_flag = 0; + + /* Build response based on expected page codes. */ + + /* Initialize length and page pointer. */ + mode_data_length = response_header_length; + page_pointer = transfer_request -> ux_slave_transfer_request_data_pointer + response_header_length; + +#ifdef UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC + /* CD Capabilities and Mechanical Status mode page. */ + if(page_code == UX_SLAVE_CLASS_STORAGE_MMC2_PAGE_CODE_CDROM || + page_code == UX_SLAVE_CLASS_STORAGE_PAGE_CODE_ALL) + { + page_length = USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_CDROM_LENGTH; + + /* Copy page data. */ + _ux_utility_memory_copy(page_pointer, usbx_device_class_storage_mode_sense_page_cdrom, page_length); /* Use case of memcpy is verified. */ + + /* Update pointer and length. */ + mode_data_length += page_length; + page_pointer += page_length; + } +#endif + + /* Caching mode page is returned if cache flush callback implemented. */ + if (storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_flush != UX_NULL && + (page_code == UX_SLAVE_CLASS_STORAGE_PAGE_CODE_CACHE || + page_code == UX_SLAVE_CLASS_STORAGE_PAGE_CODE_ALL)) + { + page_length = USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_CACHE_LENGTH; + + /* Store page code. */ + *(page_pointer) = UX_SLAVE_CLASS_STORAGE_PAGE_CODE_CACHE; + + /* Store the length of the page data. */ + *(page_pointer + UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_LENGTH) = + UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_PAGE_LENGTH; + + /* Set the Write Cache Enabled (WCE) bit. */ + *(page_pointer + UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_FLAGS) |= + UX_SLAVE_CLASS_STORAGE_CACHING_MODE_PAGE_FLAG_WCE; + + mode_data_length += page_length; + page_pointer += page_length; + } + + /* Informational Exceptions Control mode page. */ + if (page_code == UX_SLAVE_CLASS_STORAGE_PAGE_CODE_IEC || + page_code == UX_SLAVE_CLASS_STORAGE_PAGE_CODE_ALL) + { + page_length = USBX_DEVICE_CLASS_STORAGE_MODE_SENSE_PAGE_IEC_LENGTH; + + /* Store page code. */ + *(page_pointer) = UX_SLAVE_CLASS_STORAGE_PAGE_CODE_IEC; + + /* Store the length of the page data. */ + *(page_pointer + 1) = UX_SLAVE_CLASS_STORAGE_IEC_MODE_PAGE_PAGE_LENGTH; + + mode_data_length += page_length; + page_pointer += page_length; + } + + /* Put the payload length in the header. */ + if (mode_sense_command == UX_SLAVE_CLASS_STORAGE_SCSI_MODE_SENSE_SHORT) + * transfer_request -> ux_slave_transfer_request_data_pointer = (UCHAR)(mode_data_length); + else + _ux_utility_short_put_big_endian(transfer_request -> ux_slave_transfer_request_data_pointer, (USHORT)mode_data_length); + + /* Store the write protection flag. */ + *(transfer_request -> ux_slave_transfer_request_data_pointer + flags_index) = read_only_flag; + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = mode_data_length; + storage -> ux_device_class_storage_data_length = mode_data_length; + storage -> ux_device_class_storage_data_count = 0; + +#else + + /* Send a payload with the response buffer. */ + _ux_device_stack_transfer_request(transfer_request, mode_sense_reply_length, mode_sense_reply_length); +#endif + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + status = UX_SUCCESS; + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_prevent_allow_media_removal.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_prevent_allow_media_removal.c new file mode 100644 index 00000000..3eaffac4 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_prevent_allow_media_removal.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_prevent_allow_media_removal */ +/* PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function allows or prevents the removal of the media. We don't */ +/* do anything here, just the CSW is returned with a SUCCESS code. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_prevent_allow_media_removal(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + + UX_PARAMETER_NOT_USED(lun); + UX_PARAMETER_NOT_USED(endpoint_in); + UX_PARAMETER_NOT_USED(endpoint_out); + UX_PARAMETER_NOT_USED(cbwcb); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_PREVENT_ALLOW_MEDIA_REMOVAL, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* We set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read.c new file mode 100644 index 00000000..9ce4ce4e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read.c @@ -0,0 +1,313 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_read PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a READ command in 32 or 16 bits. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* scsi_command SCSI command */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_class_storage_media_read) Read from media */ +/* (ux_slave_class_storage_media_status) Get media status */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_utility_long_get_big_endian Get 32-bit big endian */ +/* _ux_utility_short_get_big_endian Get 16-bit big endian */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_read(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb, UCHAR scsi_command) +{ + +UINT status; +ULONG lba; +UX_SLAVE_TRANSFER *transfer_request; +ULONG total_number_blocks; +ULONG media_status; +ULONG total_length; + +#if !defined(UX_DEVICE_STANDALONE) +ULONG number_blocks; +ULONG transfer_length; +ULONG done_length; +#endif + + + UX_PARAMETER_NOT_USED(endpoint_out); + + /* Get the LBA from the CBWCB. */ + lba = _ux_utility_long_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_READ_LBA); + + /* The type of commands will tell us the width of the field containing the number + of sectors to read. */ + if (scsi_command == UX_SLAVE_CLASS_STORAGE_SCSI_READ16) + + /* Get the number of blocks from the CBWCB in 16 bits. */ + total_number_blocks = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_READ_TRANSFER_LENGTH_16); + + else + + /* Get the number of blocks from the CBWCB in 32 bits. */ + total_number_blocks = _ux_utility_long_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_READ_TRANSFER_LENGTH_32); + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Compute the total length to transfer and how much remains. */ + total_length = total_number_blocks * storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_block_length; + + /* Default CSW to failed. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + +#if defined(UX_DEVICE_STANDALONE) + + /* Obtain the status of the device. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_status(storage, lun, + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_id, &media_status); + + /* Update the request sense. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* Update the request to use. */ + storage -> ux_device_class_storage_transfer = transfer_request; + + /* If there is a problem, return a failed command. */ + if (status != UX_SUCCESS) + { + + /* Update residue. */ + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length; + + /* Return an error. */ + return(UX_ERROR); + } + + /* Next: Disk read -> Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_DISK_WAIT; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + storage -> ux_device_class_storage_disk_state = UX_DEVICE_CLASS_STORAGE_DISK_OP_START; + storage -> ux_device_class_storage_buffer_state[0] = UX_DEVICE_CLASS_STORAGE_BUFFER_EMPTY; + storage -> ux_device_class_storage_buffer_state[1] = UX_DEVICE_CLASS_STORAGE_BUFFER_EMPTY; + storage -> ux_device_class_storage_buffer_usb = 1; + storage -> ux_device_class_storage_buffer_disk = 1; + + storage -> ux_device_class_storage_device_length = total_length; + storage -> ux_device_class_storage_data_length = + UX_MIN(total_length , storage -> ux_slave_class_storage_host_length); + storage -> ux_device_class_storage_data_count = 0; + + storage -> ux_device_class_storage_cmd_lba = lba; + storage -> ux_device_class_storage_cmd_n_lb = total_number_blocks; + +#else + + /* Check transfer length. */ + + /* Case (7). Host length < device length. */ + if (total_length > storage -> ux_slave_class_storage_host_length) + { + _ux_device_stack_endpoint_stall(endpoint_in); + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + return(UX_ERROR); + } + + /* Case (8). Hi <> Do. */ + if ((storage -> ux_slave_class_storage_cbw_flags & 0x80) == 0) + { + _ux_device_stack_endpoint_stall(endpoint_out); + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + return(UX_ERROR); + } + + /* It may take several transfers to send the requested data. */ + done_length = 0; + while (total_number_blocks) + { + + /* Obtain the status of the device. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_status(storage, lun, + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_id, &media_status); + + /* Update the request sense. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* If there is a problem, return a failed command. */ + if (status != UX_SUCCESS) + { + + /* We have a problem, media status error. Return a bad completion and wait for the + REQUEST_SENSE command. */ + _ux_device_stack_endpoint_stall(endpoint_in); + + /* Update residue. */ + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length - done_length; + + /* Return an error. */ + return(UX_ERROR); + } + + /* How much can we send in this transfer? */ + if (total_length > UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE) + + /* Compute the transfer length based on the maximum allowed. */ + transfer_length = UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE; + + else + + /* Compute the transfer length based on what is left to transfer. */ + transfer_length = total_length; + + /* Compute the number of blocks to transfer. */ + number_blocks = transfer_length / storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_block_length; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_READ, storage, lun, transfer_request -> ux_slave_transfer_request_data_pointer, + number_blocks, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Execute the read command from the local media. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_read(storage, lun, + transfer_request -> ux_slave_transfer_request_data_pointer, number_blocks, lba, &media_status); + + /* If there is a problem, return a failed command. */ + if (status != UX_SUCCESS) + { + + /* We have a problem, request error. Return a bad completion and wait for the + REQUEST_SENSE command. */ + _ux_device_stack_endpoint_stall(endpoint_in); + + /* Update residue. */ + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length - done_length; + + /* And update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* Return an error. */ + return(UX_ERROR); + } + + /* Sends the data payload back to the caller. */ + status = _ux_device_stack_transfer_request(transfer_request, transfer_length, transfer_length); + + /* Check the status. */ + if(status != UX_SUCCESS) + { + + /* We have a problem, request error. Return a bad completion and wait for the + REQUEST_SENSE command. */ + _ux_device_stack_endpoint_stall(endpoint_in); + + /* Update residue. */ + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length - done_length; + + /* Update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(0x02,0x54,0x00); + + /* Return an error. */ + return(UX_ERROR); + + } + + /* Update the LBA address. */ + lba += number_blocks; + + /* Update the length to remain. */ + total_length -= transfer_length; + done_length += transfer_length; + + /* Update the number of blocks to read. */ + total_number_blocks -= number_blocks; + } + + /* Case (4), (5). Host length too large. */ + if (storage -> ux_slave_class_storage_host_length > done_length) + { + + /* Stall Bulk-In. */ + _ux_device_stack_endpoint_stall(endpoint_in); + + /* Update residure. */ + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length - done_length; + } + +#endif /* else defined(UX_DEVICE_STANDALONE) */ + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Return completion status. */ + return(UX_SUCCESS); +} diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_capacity.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_capacity.c new file mode 100644 index 00000000..fe937815 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_capacity.c @@ -0,0 +1,177 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +#if UX_SLAVE_REQUEST_DATA_MAX_LENGTH < UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LENGTH +#error UX_SLAVE_REQUEST_DATA_MAX_LENGTH is too small, please check +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_read_capacity PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a READ_CAPACITY command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_utility_long_put_big_endian Put 32-bit big endian */ +/* _ux_utility_memory_copy Copy memory */ +/* _ux_utility_memory_set Set memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_read_capacity(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status; +ULONG media_status; +UX_SLAVE_TRANSFER *transfer_request; +UCHAR *read_capacity_buffer; + + UX_PARAMETER_NOT_USED(cbwcb); + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_READ_CAPACITY, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the status of the device. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_status(storage, lun, + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_id, &media_status); + + /* Update the request sense. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* Check the status for error. */ + if (status != UX_SUCCESS) + { + +#if !defined(UX_DEVICE_STANDALONE) + + /* We need to STALL the IN endpoint. The endpoint will be reset by the host. */ + _ux_device_stack_endpoint_stall(endpoint_in); +#endif + + /* Now we set the CSW with Error. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + status = UX_SUCCESS; + } + else + { + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Obtain read capacity response buffer. */ + read_capacity_buffer = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Ensure it is cleaned. */ + _ux_utility_memory_set(read_capacity_buffer, 0, UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LENGTH); /* Use case of memcpy is verified. */ + + /* Insert the last LBA address in the response. */ + _ux_utility_long_put_big_endian(&read_capacity_buffer[UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LAST_LBA], + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_last_lba); + + /* Insert the block length in the response. */ + _ux_utility_long_put_big_endian(&read_capacity_buffer[UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_BLOCK_SIZE], + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_block_length); + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = + UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LENGTH; + storage -> ux_device_class_storage_data_length = + UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LENGTH; + storage -> ux_device_class_storage_data_count = 0; + UX_SLAVE_TRANSFER_STATE_RESET(storage -> ux_device_class_storage_transfer); + +#else + + /* Send a data payload with the read_capacity response buffer. */ + _ux_device_stack_transfer_request(transfer_request, + UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LENGTH, + UX_SLAVE_CLASS_STORAGE_READ_CAPACITY_RESPONSE_LENGTH); +#endif + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + status = UX_SUCCESS; + } + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_disk_information.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_disk_information.c new file mode 100644 index 00000000..3bb3bd4e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_disk_information.c @@ -0,0 +1,186 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + +#define USBX_DEVICE_CLASS_STORAGE_DISK_INFORMATION_LENGTH 34 +#if UX_SLAVE_REQUEST_DATA_MAX_LENGTH < USBX_DEVICE_CLASS_STORAGE_DISK_INFORMATION_LENGTH +#error UX_SLAVE_REQUEST_DATA_MAX_LENGTH is too small, please check +#endif +UCHAR usbx_device_class_storage_disk_information[] = { + + 0x00, 0x00, /* Entire length of disk_information */ + 0x0e, /* Erasable/state of last session/disk status ...*/ + 0x01, /* Number of first track on disk. */ + 0x01, /* Number of sessions. */ + 0x01, /* First track number in last session. */ + 0x01, /* Last track number in last session. */ + + 0x00, /* DID_V, DBC_V, URU .... */ + 0x00, /* Disk type */ + 0x00, /* Number of sessions */ + 0x00, /* First Track Number in last session */ + 0x00, /* Last Track Number in last session */ + + 0x00, 0x00, 0x00, 0x00, /* Disk Identification */ + 0xff, 0xff, 0xff, 0xff, /* Last session lead in start time */ + 0xff, 0xff, 0xff, 0xff, /* Last possible start time for SOLO */ + 0x00, 0x00, 0x00, 0x00, /* Disk Bar Code */ + 0x00, /* Reserved */ + 0x00, /* Number of OPC table entries. */ + 0x00, 0x00, 0x00, 0x00, /* Some padding ? */ + 0x00, 0x00 /* */ + + }; + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_read_disk_information PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a READ_DISK_INFORMATION command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_utility_short_put_big_endian Put 16-bit big endian */ +/* _ux_utility_memory_copy Copy memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_read_disk_information(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status; +UX_SLAVE_TRANSFER *transfer_request; +ULONG allocation_length; + + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_GET_CONFIGURATION, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Initialize the length of the disk information field. */ + _ux_utility_short_put_big_endian(usbx_device_class_storage_disk_information, (USBX_DEVICE_CLASS_STORAGE_DISK_INFORMATION_LENGTH - 2)); + + /* Clean the disk status. */ + usbx_device_class_storage_disk_information[2] &= (UCHAR)~3; + + /* Update the disk status. */ + usbx_device_class_storage_disk_information[2] = (UCHAR)(usbx_device_class_storage_disk_information[2] | (storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_disk_status & 3)); + + /* Clean the last session state. */ + usbx_device_class_storage_disk_information[2] &= (UCHAR)~0x0c; + + /* Update the last session state. */ + usbx_device_class_storage_disk_information[2] = (UCHAR)(usbx_device_class_storage_disk_information[2] | ((storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_last_session_state << 2) & 0x0c)); + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Get the allocation length. */ + allocation_length = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_READ_DISK_INFORMATION_ALLOCATION_LENGTH); + + /* Can we send all the disk information ? */ + if (allocation_length > USBX_DEVICE_CLASS_STORAGE_DISK_INFORMATION_LENGTH) + + /* Yes, so send only the disk information profile. */ + allocation_length = USBX_DEVICE_CLASS_STORAGE_DISK_INFORMATION_LENGTH; + + /* Copy the CSW into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer, + usbx_device_class_storage_disk_information, + allocation_length); /* Use case of memcpy is verified. */ + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = allocation_length; + storage -> ux_device_class_storage_data_length = allocation_length; + storage -> ux_device_class_storage_data_count = 0; + UX_SLAVE_TRANSFER_STATE_RESET(storage -> ux_device_class_storage_transfer); + +#else + + /* Send a data payload with the read_capacity response buffer. */ + _ux_device_stack_transfer_request(transfer_request, + allocation_length, + allocation_length); +#endif + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + status = UX_SUCCESS; + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_dvd_structure.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_dvd_structure.c new file mode 100644 index 00000000..a39c9dfe --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_dvd_structure.c @@ -0,0 +1,306 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + +#define USBX_DEVICE_CLASS_STORAGE_DVD_STRUCTURE_LENGTH (2048 + 4) +UCHAR usbx_device_class_storage_dvd_structure[] = { + 0x08, 0x02, 0x00, 0x00, 0x25, 0x0F, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0xAF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0x00, 0x00, 0x04, 0x6E, 0xA0, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 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+/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_read_dvd_structure PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a READ_DVD_STRUCTURE command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_utility_short_get_big_endian Get 16-bit big endian */ +/* _ux_utility_memory_copy Copy memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_read_dvd_structure(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status; +UX_SLAVE_TRANSFER *transfer_request; +ULONG allocation_length; +UCHAR *dvd_structure_pointer; + +#if !defined(UX_DEVICE_STANDALONE) +ULONG transfer_length = 0; +#endif + + + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_OTHER, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Get the allocation length. */ + allocation_length = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_READ_DISK_INFORMATION_ALLOCATION_LENGTH); + + /* Can we send all the disk information ? */ + if (allocation_length > USBX_DEVICE_CLASS_STORAGE_DVD_STRUCTURE_LENGTH) + + /* Yes, so send only the disk information profile. */ + allocation_length = USBX_DEVICE_CLASS_STORAGE_DVD_STRUCTURE_LENGTH; + + /* Set dvd structure pointer. */ + dvd_structure_pointer = usbx_device_class_storage_dvd_structure; + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = allocation_length; + storage -> ux_device_class_storage_data_buffer = dvd_structure_pointer; + storage -> ux_device_class_storage_data_length = allocation_length; + storage -> ux_device_class_storage_data_count = 0; + UX_SLAVE_TRANSFER_STATE_RESET(storage -> ux_device_class_storage_transfer); + +#else + + /* Send back everything in chunks. */ + while (allocation_length) + { + + /* Check length. Is it more than one packet ? */ + if (allocation_length > UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE) + + /* Compute the transfer length based on the maximum allowed. */ + transfer_length = UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE; + + else + + /* Compute the transfer length based on what is left to transfer. */ + transfer_length = allocation_length; + + /* Copy the CSW into the transfer request memory. */ + _ux_utility_memory_copy(transfer_request -> ux_slave_transfer_request_data_pointer, + dvd_structure_pointer, + transfer_length); /* Use case of memcpy is verified. */ + + /* Send a data payload with the read_capacity response buffer. */ + status = _ux_device_stack_transfer_request(transfer_request, + transfer_length, + transfer_length); + + /* Check transfer completion status. */ + if (status != UX_SUCCESS) + return(status); + + /* Advance pointer to dvd structure. */ + dvd_structure_pointer += transfer_length; + + /* Subtract what is left to send out. */ + allocation_length -= transfer_length; + } +#endif + + /* Now we set the CSW with success. */ + UX_PARAMETER_NOT_USED(lun); + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + status = UX_SUCCESS; + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_format_capacity.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_format_capacity.c new file mode 100644 index 00000000..68688f8f --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_format_capacity.c @@ -0,0 +1,156 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +#if UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE < UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LENGTH +#error UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE too small, please check +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_read_format_capacity PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a READ_FORMAT_CAPACITY command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_utility_memory_set Set memory */ +/* _ux_utility_long_put_big_endian Put 32-bit big endian */ +/* _ux_utility_memory_copy Copy memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_read_format_capacity(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status; +UX_SLAVE_TRANSFER *transfer_request; +UCHAR *read_format_capacity_buffer; + + UX_PARAMETER_NOT_USED(cbwcb); + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_READ_FORMAT_CAPACITY, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Get read format capacity response buffer. */ + read_format_capacity_buffer = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Ensure it is cleaned. */ + _ux_utility_memory_set(read_format_capacity_buffer, 0, UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LENGTH); /* Use case of memset is verified. */ + + /* Insert the size of the response block. */ + _ux_utility_long_put_big_endian(&read_format_capacity_buffer[UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_SIZE], 8); + + /* Insert the last LBA address in the response. */ + _ux_utility_long_put_big_endian(&read_format_capacity_buffer[UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LAST_LBA], + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_last_lba); + + /* Insert the block length in the response. This is in 3 bytes. */ + _ux_utility_long_put_big_endian(&read_format_capacity_buffer[UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_BLOCK_SIZE], + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_block_length); + + /* Insert the response code : always 2. */ + read_format_capacity_buffer[UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_DESC_CODE] = 2; + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = + UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LENGTH; + storage -> ux_device_class_storage_data_length = + UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LENGTH; + storage -> ux_device_class_storage_data_count = 0; + UX_SLAVE_TRANSFER_STATE_RESET(storage -> ux_device_class_storage_transfer); + +#else + + /* Send a data payload with the read_capacity response buffer. */ + _ux_device_stack_transfer_request(transfer_request, + UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LENGTH, + UX_SLAVE_CLASS_STORAGE_READ_FORMAT_CAPACITY_RESPONSE_LENGTH); +#endif + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + status = UX_SUCCESS; + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_toc.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_toc.c new file mode 100644 index 00000000..e8af7f28 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_read_toc.c @@ -0,0 +1,217 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +#if UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE < 20 +#error UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE too small, please check +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_read_toc PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a READ_TOC SCSI command. This is only for */ +/* supporting CD-ROM emulation and is hardwired to what Windows wants. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_utility_memory_set Set memory */ +/* _ux_utility_memory_copy Copy memory */ +/* _ux_utility_short_get_big_endian Get 16-bit big endian */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_read_toc(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status; +UX_SLAVE_TRANSFER *transfer_request; +ULONG allocation_length; +ULONG toc_length; +UCHAR *toc_buffer; + + + UX_PARAMETER_NOT_USED(lun); + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_READ_TOC, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Obtain TOC buffer. */ + toc_buffer = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Reset this buffer. */ + _ux_utility_memory_set(toc_buffer,0,20); /* Use case of memset is verified. */ + + /* Get the allocation length. */ + allocation_length = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_READ_TOC_ALLOCATION_LENGTH); + + /* Insert the fist and last tack number. */ + toc_buffer[2] = 0x01; + toc_buffer[3] = 0x01; + + /* Set TOC length by default. */ + toc_length = 20; + + /* Insert the ADR and control values. */ + toc_buffer[5] = 0x14; + + /* Insert the TOC tack number. */ + toc_buffer[6] = 0x01; + + /* Check if the request is for the TOC or time stamp. */ + switch (*(cbwcb + UX_SLAVE_CLASS_STORAGE_READ_TOC_FORMAT)) + { + + case 0x02 : + + /* Set the toc buffer length. */ + toc_length = 20; + + /* Insert the TOC buffer length. */ + toc_buffer[1] = 0x12; + + /* Insert some time values. */ + toc_buffer[10] = 0x02; + toc_buffer[13] = 0x17; + toc_buffer[14] = 0xAA; + toc_buffer[18] = 0x04; + toc_buffer[19] = 0x1a; + + break; + + case 0x01 : + + /* Set the toc buffer length. */ + toc_length = 19; + + /* Insert the TOC buffer length. */ + toc_buffer[1] = 0x12; + + toc_buffer[13] = 0x17; + toc_buffer[14] = 0xAA; + toc_buffer[19] = 0xb0; + + break; + + case 0x00 : + + /* Set the toc buffer length. */ + toc_length = 20; + + /* Insert the TOC buffer length. */ + toc_buffer[1] = 0x12; + + /* Insert some time values. */ + toc_buffer[10] = 0x02; + toc_buffer[13] = 0x17; + toc_buffer[14] = 0xAA; + toc_buffer[18] = 0x04; + toc_buffer[19] = 0x1a; + + break; + } + + /* Check how much we can send back. */ + if (allocation_length > toc_length) + + /* We return less than demanded. */ + allocation_length = toc_length; + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = allocation_length; + storage -> ux_device_class_storage_data_length = allocation_length; + storage -> ux_device_class_storage_data_count = 0; + +#else + + /* Send a data payload with the TOC response buffer. */ + _ux_device_stack_transfer_request(transfer_request, allocation_length, allocation_length); +#endif + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + status = UX_SUCCESS; + + /* Return completion status. */ + return(status); + +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_report_key.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_report_key.c new file mode 100644 index 00000000..e692dfab --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_report_key.c @@ -0,0 +1,179 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +#if UX_SLAVE_REQUEST_DATA_MAX_LENGTH < UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_LENGTH +#error UX_SLAVE_REQUEST_DATA_MAX_LENGTH too small, please check +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_report_key PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a REPORT_KEY SCSI command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_utility_memory_set Set memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed compile warning, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_report_key(UX_SLAVE_CLASS_STORAGE *storage, + ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, + UCHAR *cbwcb) +{ + +UINT status = UX_SUCCESS; +UX_SLAVE_TRANSFER *transfer_request; +ULONG allocation_length; +ULONG key_format; + + + UX_PARAMETER_NOT_USED(lun); + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_OTHER, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Get the report key. */ + key_format = (ULONG) *(cbwcb + UX_SLAVE_CLASS_STORAGE_REPORT_KEY_FORMAT); + + /* Extract the length to be returned by the cbwcb. */ + allocation_length = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ALLOCATION_LENGTH); + + /* Ensure memory buffer cleaned. */ + _ux_utility_memory_set(transfer_request -> ux_slave_transfer_request_data_pointer, 0, UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_LENGTH); /* Use case of memset is verified. */ + + /* Filter page code. This is necessary to isolate the CD-ROM mode sense response. */ + switch (key_format) + { + + case UX_SLAVE_CLASS_STORAGE_REPORT_KEY_FORMAT_RPC : + + + /* Put the length to be returned. */ + _ux_utility_short_put_big_endian(transfer_request -> ux_slave_transfer_request_data_pointer, + UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_PAYLOAD); + + /* Put the reset field. */ + *(transfer_request -> ux_slave_transfer_request_data_pointer + UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_RESET_FIELD) = 0x25; + + /* Put the region mask. */ + *(transfer_request -> ux_slave_transfer_request_data_pointer + UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_REGION_MASK) = 0xFF; + + /* No region code. */ + *(transfer_request -> ux_slave_transfer_request_data_pointer + UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_RPC_SCHEME) = 0x00; + + /* Compute the payload to return. Depends on the request. */ + if (allocation_length > UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_LENGTH) + + /* Adjust the reply. */ + allocation_length = UX_SLAVE_CLASS_STORAGE_REPORT_KEY_ANSWER_LENGTH; + + break; + + default : + allocation_length = 0; + break; + + } + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = allocation_length; + storage -> ux_device_class_storage_data_length = allocation_length; + storage -> ux_device_class_storage_data_count = 0; + UX_SLAVE_TRANSFER_STATE_RESET(storage -> ux_device_class_storage_transfer); + +#else + + /* Send a data payload with the read_capacity response buffer. */ + status = _ux_device_stack_transfer_request(transfer_request, allocation_length, allocation_length); /* Use case of memset is verified. */ +#endif + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_request_sense.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_request_sense.c new file mode 100644 index 00000000..60bc9ba2 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_request_sense.c @@ -0,0 +1,175 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +#if UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE < UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_LENGTH +#error UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE too small, please check +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_request_sense PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a request sense command. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_utility_memory_copy Copy memory */ +/* _ux_utility_memory_set Set memory */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* verified memset and memcpy */ +/* cases, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_request_sense(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status = UX_SUCCESS; +UX_SLAVE_TRANSFER *transfer_request; +UCHAR *sense_buffer; +UCHAR key, code, qualifier; +ULONG sense_length; + + + UX_PARAMETER_NOT_USED(cbwcb); + UX_PARAMETER_NOT_USED(endpoint_out); + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_in -> ux_slave_endpoint_transfer_request; + + /* Get length. */ + sense_length = storage -> ux_slave_class_storage_host_length; + if (sense_length > UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_LENGTH) + sense_length = UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_LENGTH; + + /* Obtain sense buffer. */ + sense_buffer = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Ensure it is cleaned. */ + _ux_utility_memory_set(sense_buffer, 0, sense_length); /* Use case of memset is verified. */ + + /* Initialize the response buffer with the error code. */ + sense_buffer[UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_ERROR_CODE] = + UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_ERROR_CODE_VALUE; + + /* Extract sense key, code, qualifier. */ + key = UX_DEVICE_CLASS_STORAGE_SENSE_KEY(storage -> ux_slave_class_storage_lun[lun]. + ux_slave_class_storage_request_sense_status); + code = UX_DEVICE_CLASS_STORAGE_SENSE_CODE(storage -> ux_slave_class_storage_lun[lun]. + ux_slave_class_storage_request_sense_status); + qualifier = UX_DEVICE_CLASS_STORAGE_SENSE_QUALIFIER(storage -> ux_slave_class_storage_lun[lun]. + ux_slave_class_storage_request_sense_status); + + /* Initialize the response buffer with the sense key. */ + sense_buffer[UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_SENSE_KEY] = key; + + /* Initialize the response buffer with the code. */ + sense_buffer[UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_CODE] = code; + + /* Initialize the response buffer with the code qualifier. */ + sense_buffer[UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_CODE_QUALIFIER] = qualifier; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_REQUEST_SENSE, storage, lun, + key, code, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Initialize the response buffer with the additional length. */ + sense_buffer[UX_SLAVE_CLASS_STORAGE_REQUEST_SENSE_RESPONSE_ADD_LENGTH] = 10; + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_READ; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = sense_length; + storage -> ux_device_class_storage_data_length = sense_length; + storage -> ux_device_class_storage_data_count = 0; + +#else + + /* Send a data payload with the sense codes. */ + if (sense_length) + _ux_device_stack_transfer_request(transfer_request, sense_length, sense_length); + + /* Check length. */ + if (storage -> ux_slave_class_storage_host_length != sense_length) + { + _ux_device_stack_endpoint_stall(endpoint_in); + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_start_stop.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_start_stop.c new file mode 100644 index 00000000..33bcf0ef --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_start_stop.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_start_stop PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function starts or stops the media. This command will not do */ +/* anything here, just the CSW is returned with a SUCCESS code. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_start_stop(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + + UX_PARAMETER_NOT_USED(lun); + UX_PARAMETER_NOT_USED(endpoint_in); + UX_PARAMETER_NOT_USED(endpoint_out); + UX_PARAMETER_NOT_USED(cbwcb); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_START_STOP, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* We set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_synchronize_cache.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_synchronize_cache.c new file mode 100644 index 00000000..ea926976 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_synchronize_cache.c @@ -0,0 +1,203 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_synchronize_cache PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a SYNCHRONIZE_CACHE command in 32 or 16 */ +/* bits. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to the CBWCB */ +/* scsi_command SCSI command */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_class_storage_media_status) Get media status */ +/* (ux_slave_class_storage_media_flush) Flush media */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_utility_long_get_big_endian Get 32-bit big endian */ +/* _ux_utility_short_get_big_endian Get 16-bit big endian */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_synchronize_cache(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR *cbwcb, UCHAR scsi_command) +{ + +UINT status; +ULONG lba; +USHORT number_blocks; +ULONG media_status; + +#if !defined(UX_DEVICE_STANDALONE) +UCHAR flags; +#endif + + + UX_PARAMETER_NOT_USED(endpoint_out); + UX_PARAMETER_NOT_USED(scsi_command); + + /* By default status is passed. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Is there not an implementation? */ + if (storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_flush == UX_NULL) + { + + /* This means the application is not using a cache. */ + + /* Return success. */ + return(UX_SUCCESS); + } + + /* Get the LBA and number of blocks from the CBWCB in 16 bits. */ + lba = _ux_utility_long_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_LBA); + number_blocks = (USHORT)_ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_NUMBER_OF_BLOCKS); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_SYNCHRONIZE_CACHE, storage, lun, lba, number_blocks, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the status of the device. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_status(storage, + lun, storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_id, &media_status); + + /* Update the request sense. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* If there is a problem, return a failed command. */ + if (status != UX_SUCCESS) + { + + /* We have a problem, media status error. Return a bad completion and wait for the + REQUEST_SENSE command. */ +#if !defined(UX_DEVICE_STANDALONE) + _ux_device_stack_endpoint_stall(endpoint_in); +#else + UX_PARAMETER_NOT_USED(endpoint_in); + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_ERR; +#endif + + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + + /* We are done here. */ + return(UX_ERROR); + } + + /* Now it's OK to perform synchronize cache. */ + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Disk (SYNC). */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_DISK_WAIT; + storage -> ux_device_class_storage_disk_state = UX_DEVICE_CLASS_STORAGE_DISK_OP_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_DISK_OP; + + storage -> ux_device_class_storage_cmd_lba = lba; + storage -> ux_device_class_storage_cmd_n_lb = number_blocks; + +#else + + /* Get the flags. */ + flags = *(cbwcb + UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_FLAGS); + + /* If the immediate bit is set, we return a CSW before flush. */ + if ((flags & UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_FLAGS_IMMED) != 0) + _ux_device_class_storage_csw_send(storage, lun, endpoint_in, UX_SLAVE_CLASS_STORAGE_CSW_PASSED); + + /* Send the flush command to the local media. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_flush(storage, lun, number_blocks, lba, &media_status); + + /* Update the request sense. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* If the immediate bit is set, we are already done, no matter what local operation status is. */ + if ((flags & UX_SLAVE_CLASS_STORAGE_SYNCHRONIZE_CACHE_FLAGS_IMMED) != 0) + { + + /* CSW skipped since already sent in this function. */ + UX_DEVICE_CLASS_STORAGE_CSW_SKIP(&storage -> ux_slave_class_storage_csw_status) = UX_TRUE; + return(status); + } + + /* If there is a problem, return a failed command. */ + if (status != UX_SUCCESS) + { + + /* We have a problem, request error. Return a bad completion and wait for the + REQUEST_SENSE command. */ + _ux_device_stack_endpoint_stall(endpoint_in); + + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + + /* Return an error. */ + return(UX_ERROR); + } +#endif + + /* Return completion status. */ + return(status); +} diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_test_ready.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_test_ready.c new file mode 100644 index 00000000..dc89c27c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_test_ready.c @@ -0,0 +1,126 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_test_ready PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function tests if the SCSI slave device is ready. */ +/* The status function of the storage devices is called. If there is */ +/* an error, the request sense parameters are set for the host to */ +/* investigate. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_class_storage_media_status) Get media status */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_test_ready(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + +UINT status; +ULONG media_status; + + UX_PARAMETER_NOT_USED(lun); + UX_PARAMETER_NOT_USED(endpoint_in); + UX_PARAMETER_NOT_USED(endpoint_out); + UX_PARAMETER_NOT_USED(cbwcb); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_TEST_READY, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the status of the device. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_status(storage, lun, + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_id, &media_status); + + /* Set the sense/code/qualifier codes for the REQUEST_SENSE command. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* Return CSW with success/error. */ + storage -> ux_slave_class_storage_csw_status = (status == UX_SUCCESS) ? + UX_SLAVE_CLASS_STORAGE_CSW_PASSED : UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + status = UX_SUCCESS; + +#if !defined(UX_DEVICE_STANDALONE) + + /* Case (9) Ho > Dn. */ + if (storage -> ux_slave_class_storage_host_length) + { + _ux_device_stack_endpoint_stall(endpoint_out); + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length; + } +#endif + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_thread.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_thread.c new file mode 100644 index 00000000..2fc84a62 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_thread.c @@ -0,0 +1,464 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +#if !defined(UX_DEVICE_STANDALONE) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_thread PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the thread of the storage class. */ +/* */ +/* It's for RTOS mode. */ +/* */ +/* INPUT */ +/* */ +/* class Address of storage class */ +/* container */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_format Storage class format */ +/* _ux_device_class_storage_inquiry Storage class inquiry */ +/* _ux_device_class_storage_mode_select Mode select */ +/* _ux_device_class_storage_mode_sense Mode sense */ +/* _ux_device_class_storage_prevent_allow_media_removal */ +/* Prevent media removal */ +/* _ux_device_class_storage_read Read */ +/* _ux_device_class_storage_read_capacity */ +/* Read capacity */ +/* _ux_device_class_storage_read_format_capacity */ +/* Read format capacity */ +/* _ux_device_class_storage_request_sense */ +/* Sense request */ +/* _ux_device_class_storage_start_stop Start/Stop */ +/* _ux_device_class_storage_synchronize_cache */ +/* Synchronize cache */ +/* _ux_device_class_storage_test_ready Ready test */ +/* _ux_device_class_storage_verify Verify */ +/* _ux_device_class_storage_write Write */ +/* _ux_device_stack_endpoint_stall Endpoint stall */ +/* _ux_device_stack_interface_delete Interface delete */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_utility_long_get Get 32-bit value */ +/* _ux_utility_memory_allocate Allocate memory */ +/* _ux_device_semaphore_create Create semaphore */ +/* _ux_utility_delay_ms Sleep thread for several ms */ +/* _ux_device_thread_suspend Suspend thread */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* used sleep instead of */ +/* relinquish on error, */ +/* optimized command logic, */ +/* used UX prefix to refer to */ +/* TX symbols instead of using */ +/* them directly, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 04-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* fixed compile issues with */ +/* some macro options, */ +/* resulting in version 6.1.6 */ +/* 06-02-2021 Chaoqiong Xiao Modified comment(s), */ +/* get interface and endpoints */ +/* from configured device, */ +/* resulting in version 6.1.7 */ +/* 10-15-2021 Chaoqiong Xiao Modified comment(s), */ +/* improved TAG management, */ +/* resulting in version 6.1.9 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* refined macros names, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _ux_device_class_storage_thread(ULONG storage_class) +{ + +UX_SLAVE_CLASS *class; +UX_SLAVE_CLASS_STORAGE *storage; +UX_SLAVE_TRANSFER *transfer_request; +UX_SLAVE_DEVICE *device; +UX_SLAVE_INTERFACE *interface; +UX_SLAVE_ENDPOINT *endpoint_in; +UX_SLAVE_ENDPOINT *endpoint_out; +UINT status; +ULONG length; +ULONG cbwcb_length; +ULONG lun; +UCHAR *scsi_command; +UCHAR *cbw_cb; + + + /* This thread runs forever but can be suspended or resumed. */ + while(1) + { + + /* Cast properly the storage instance. */ + UX_THREAD_EXTENSION_PTR_GET(class, UX_SLAVE_CLASS, storage_class) + + /* Get the storage instance from this class container. */ + storage = (UX_SLAVE_CLASS_STORAGE *) class -> ux_slave_class_instance; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* As long as the device is in the CONFIGURED state. */ + while (device -> ux_slave_device_state == UX_DEVICE_CONFIGURED) + { + + /* We assume the worst situation. */ + status = UX_ERROR; + + /* We are activated. We need the interface to the class. */ + interface = storage -> ux_slave_class_storage_interface; + + /* We assume the worst situation. */ + status = UX_ERROR; + + /* Locate the endpoints. */ + endpoint_in = interface -> ux_slave_interface_first_endpoint; + + /* Check the endpoint direction, if IN we have the correct endpoint. */ + if ((endpoint_in -> ux_slave_endpoint_descriptor.bEndpointAddress & UX_ENDPOINT_DIRECTION) != UX_ENDPOINT_IN) + { + + /* Wrong direction, we found the OUT endpoint first. */ + endpoint_out = endpoint_in; + + /* So the next endpoint has to be the IN endpoint. */ + endpoint_in = endpoint_out -> ux_slave_endpoint_next_endpoint; + } + else + { + + /* We found the endpoint IN first, so next endpoint is OUT. */ + endpoint_out = endpoint_in -> ux_slave_endpoint_next_endpoint; + } + + /* All SCSI commands are on the endpoint OUT, from the host. */ + transfer_request = &endpoint_out -> ux_slave_endpoint_transfer_request; + + /* Check state, they must be both RESET. */ + if (endpoint_out -> ux_slave_endpoint_state == UX_ENDPOINT_RESET && + (UCHAR)storage -> ux_slave_class_storage_csw_status != UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR) + { + + /* Send the request to the device controller. */ + status = _ux_device_stack_transfer_request(transfer_request, 64, 64); + + } + + /* Check the status. Our status is UX_ERROR if one of the endpoint was STALLED. We must wait for the host + to clear the mess. */ + if (status == UX_SUCCESS) + { + + /* Obtain the length of the transaction. */ + length = transfer_request -> ux_slave_transfer_request_actual_length; + + /* Obtain the buffer address containing the SCSI command. */ + scsi_command = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Obtain the lun from the CBW. */ + lun = (ULONG) *(scsi_command + UX_SLAVE_CLASS_STORAGE_CBW_LUN); + storage -> ux_slave_class_storage_cbw_lun = (UCHAR)lun; + + /* We have to memorize the SCSI command tag for the CSW phase. */ + storage -> ux_slave_class_storage_scsi_tag = _ux_utility_long_get(scsi_command + UX_SLAVE_CLASS_STORAGE_CBW_TAG); + + /* Get dCBWDataTransferLength: number of bytes to transfer. */ + storage -> ux_slave_class_storage_host_length = _ux_utility_long_get(scsi_command + UX_SLAVE_CLASS_STORAGE_CBW_DATA_LENGTH); + + /* Save bmCBWFlags. */ + storage -> ux_slave_class_storage_cbw_flags = *(scsi_command + UX_SLAVE_CLASS_STORAGE_CBW_FLAGS); + + /* Reset CSW status. */ + storage -> ux_slave_class_storage_csw_residue = 0; + storage -> ux_slave_class_storage_csw_status = 0; + + /* Ensure the LUN number is within our declared values and check the command + content and format. First we make sure we have a complete CBW. */ + if ((lun < storage -> ux_slave_class_storage_number_lun) && (length == UX_SLAVE_CLASS_STORAGE_CBW_LENGTH)) + { + + /* The length of the CBW is correct, analyze the header. */ + if (_ux_utility_long_get(scsi_command) == UX_SLAVE_CLASS_STORAGE_CBW_SIGNATURE_MASK) + { + + /* Get the length of the CBWCB. */ + cbwcb_length = (ULONG) *(scsi_command + UX_SLAVE_CLASS_STORAGE_CBW_CB_LENGTH); + + /* Check the length of the CBWCB to ensure there is at least a command. */ + if (cbwcb_length != 0) + { + + /* Analyze the command stored in the CBWCB. */ + cbw_cb = scsi_command + UX_SLAVE_CLASS_STORAGE_CBW_CB; + switch (*(cbw_cb)) + { + + case UX_SLAVE_CLASS_STORAGE_SCSI_TEST_READY: + + _ux_device_class_storage_test_ready(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_REQUEST_SENSE: + + _ux_device_class_storage_request_sense(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_FORMAT: + + _ux_device_class_storage_format(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_INQUIRY: + + _ux_device_class_storage_inquiry(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_START_STOP: + + _ux_device_class_storage_start_stop(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_PREVENT_ALLOW_MEDIA_REMOVAL: + + _ux_device_class_storage_prevent_allow_media_removal(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_READ_FORMAT_CAPACITY: + + _ux_device_class_storage_read_format_capacity(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_READ_CAPACITY: + + _ux_device_class_storage_read_capacity(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_VERIFY: + + _ux_device_class_storage_verify(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_MODE_SELECT: + + _ux_device_class_storage_mode_select(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_MODE_SENSE_SHORT: + case UX_SLAVE_CLASS_STORAGE_SCSI_MODE_SENSE: + + _ux_device_class_storage_mode_sense(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_READ32: + + _ux_device_class_storage_read(storage, lun, endpoint_in, endpoint_out, cbw_cb, + UX_SLAVE_CLASS_STORAGE_SCSI_READ32); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_READ16: + + _ux_device_class_storage_read(storage, lun, endpoint_in, endpoint_out, cbw_cb, + UX_SLAVE_CLASS_STORAGE_SCSI_READ16); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_WRITE32: + + _ux_device_class_storage_write(storage, lun, endpoint_in, endpoint_out, cbw_cb, + UX_SLAVE_CLASS_STORAGE_SCSI_WRITE32); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_WRITE16: + + _ux_device_class_storage_write(storage, lun, endpoint_in, endpoint_out, cbw_cb, + UX_SLAVE_CLASS_STORAGE_SCSI_WRITE16); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_SYNCHRONIZE_CACHE: + + _ux_device_class_storage_synchronize_cache(storage, lun, endpoint_in, endpoint_out, cbw_cb, *(cbw_cb)); + break; + +#ifdef UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC + case UX_SLAVE_CLASS_STORAGE_SCSI_GET_STATUS_NOTIFICATION: + + _ux_device_class_storage_get_status_notification(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_GET_CONFIGURATION: + + _ux_device_class_storage_get_configuration(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_READ_DISK_INFORMATION: + + _ux_device_class_storage_read_disk_information(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_REPORT_KEY: + + _ux_device_class_storage_report_key(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_GET_PERFORMANCE: + + _ux_device_class_storage_get_performance(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_READ_DVD_STRUCTURE: + + _ux_device_class_storage_read_dvd_structure(storage, lun, endpoint_in, endpoint_out, cbw_cb); + break; + + case UX_SLAVE_CLASS_STORAGE_SCSI_READ_TOC: + + status = _ux_device_class_storage_read_toc(storage, lun, endpoint_in, endpoint_out, cbw_cb); + + /* Special treatment of TOC command. If error, default to Stall endpoint. */ + if (status == UX_SUCCESS) + break; +#endif + + /* fall through */ + default: + + /* The command is unknown or unsupported, so we stall the endpoint. */ + + if (storage -> ux_slave_class_storage_host_length > 0 && + ((storage -> ux_slave_class_storage_cbw_flags & 0x80) == 0)) + + /* Data-Out from host to device, stall OUT. */ + _ux_device_stack_endpoint_stall(endpoint_out); + else + + /* Data-In from device to host, stall IN. */ + _ux_device_stack_endpoint_stall(endpoint_in); + + /* Initialize the request sense keys. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(UX_SLAVE_CLASS_STORAGE_SENSE_KEY_ILLEGAL_REQUEST, + UX_SLAVE_CLASS_STORAGE_ASC_KEY_INVALID_COMMAND,0); + + /* This is the tricky part of the SCSI state machine. We must send the CSW BUT need to wait + for the endpoint_in to be reset by the host. */ + while (device -> ux_slave_device_state == UX_DEVICE_CONFIGURED) + { + + /* Check the endpoint state. */ + if (endpoint_in -> ux_slave_endpoint_state == UX_ENDPOINT_RESET) + { + + /* Now we set the CSW with failure. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + break; + } + + else + + /* We must therefore wait a while. */ + _ux_device_thread_relinquish(); + } + break; + } + + /* Send CSW if not SYNC_CACHE. */ + status = _ux_device_class_storage_csw_send(storage, lun, endpoint_in, 0 /* Don't care */); + + /* Check error code. */ + if (status != UX_SUCCESS) + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_CLASS, status); + } + else + + /* Phase error! */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + } + + else + + /* Phase error! */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + } + else + + /* Phase error! */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + } + else + { + + if ((UCHAR)storage -> ux_slave_class_storage_csw_status == UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR) + { + + /* We should keep the endpoints stalled. */ + _ux_device_stack_endpoint_stall(endpoint_out); + _ux_device_stack_endpoint_stall(endpoint_in); + } + + /* We must therefore wait a while. */ + _ux_utility_delay_ms(2); + } + } + + /* We need to suspend ourselves. We will be resumed by the + device enumeration module. */ + _ux_device_thread_suspend(&class -> ux_slave_class_thread); + } +} +#endif diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_uninitialize.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_uninitialize.c new file mode 100644 index 00000000..a0159142 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_uninitialize.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_uninitialize PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function deinitializes the USB storage device. */ +/* */ +/* INPUT */ +/* */ +/* command Pointer to storage command */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_free Free memory */ +/* _ux_device_thread_delete Delete thread */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_uninitialize(UX_SLAVE_CLASS_COMMAND *command) +{ + +UX_SLAVE_CLASS_STORAGE *storage; +UX_SLAVE_CLASS *class; + + /* Get the class container. */ + class = command -> ux_slave_class_command_class_ptr; + + /* Get the class instance in the container. */ + storage = (UX_SLAVE_CLASS_STORAGE *) class -> ux_slave_class_instance; + + /* Sanity check. */ + if (storage != UX_NULL) + { + + /* Remove STORAGE thread. */ + _ux_device_thread_delete(&class -> ux_slave_class_thread); + +#if !(defined(UX_DEVICE_STANDALONE) || defined(UX_STANDALONE)) + /* Remove the thread used by STORAGE. */ + _ux_utility_memory_free(class -> ux_slave_class_thread_stack); +#endif + + /* Free the resources. */ + _ux_utility_memory_free(storage); + } + + /* Return completion status. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_verify.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_verify.c new file mode 100644 index 00000000..7b50f8d3 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_verify.c @@ -0,0 +1,96 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_verify PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function verifies a previous write command. */ +/* Here, the CSW is returned with a SUCCESS code. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to CBWCB */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_verify(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb) +{ + + UX_PARAMETER_NOT_USED(lun); + UX_PARAMETER_NOT_USED(cbwcb); + UX_PARAMETER_NOT_USED(endpoint_in); + UX_PARAMETER_NOT_USED(endpoint_out); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_VERIFY, storage, lun, 0, 0, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* We set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Return success! */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_write.c b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_write.c new file mode 100644 index 00000000..a6e6da30 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_device_classes/src/ux_device_class_storage_write.c @@ -0,0 +1,300 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Device Storage Class */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_device_class_storage.h" +#include "ux_device_stack.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_device_class_storage_write PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a WRITE command in 32 or 16 bits. */ +/* */ +/* INPUT */ +/* */ +/* storage Pointer to storage class */ +/* endpoint_in Pointer to IN endpoint */ +/* endpoint_out Pointer to OUT endpoint */ +/* cbwcb Pointer to the CBWCB */ +/* scsi_command SCSI command */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_class_storage_media_status) Get media status */ +/* (ux_slave_class_storage_media_write) Write to media */ +/* _ux_device_class_storage_csw_send Send CSW */ +/* _ux_device_stack_endpoint_stall Stall endpoint */ +/* _ux_device_stack_transfer_request Transfer request */ +/* _ux_utility_long_get_big_endian Get 32-bit big endian */ +/* _ux_utility_memory_allocate Allocate memory */ +/* _ux_utility_memory_free Release memory */ +/* _ux_utility_long_get_big_endian Get 32-bit big endian */ +/* _ux_utility_short_get_big_endian Get 16-bit big endian */ +/* */ +/* CALLED BY */ +/* */ +/* Device Storage Class */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* optimized command logic, */ +/* resulting in version 6.1 */ +/* 12-31-2020 Chaoqiong Xiao Modified comment(s), */ +/* fixed USB CV test issues, */ +/* resulting in version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_device_class_storage_write(UX_SLAVE_CLASS_STORAGE *storage, ULONG lun, + UX_SLAVE_ENDPOINT *endpoint_in, + UX_SLAVE_ENDPOINT *endpoint_out, UCHAR * cbwcb, UCHAR scsi_command) +{ + +UINT status; +UX_SLAVE_TRANSFER *transfer_request; +ULONG lba; +ULONG total_number_blocks; +ULONG media_status; +ULONG total_length; + +#if !defined(UX_DEVICE_STANDALONE) +ULONG number_blocks; +ULONG transfer_length; +ULONG done_length; +#endif + + + UX_PARAMETER_NOT_USED(endpoint_in); + + /* Get the LBA from the CBWCB. */ + lba = _ux_utility_long_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_WRITE_LBA); + + /* The type of commands will tell us the width of the field containing the number + of sectors to read. */ + if (scsi_command == UX_SLAVE_CLASS_STORAGE_SCSI_WRITE16) + + /* Get the number of blocks from the CBWCB in 16 bits. */ + total_number_blocks = _ux_utility_short_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_WRITE_TRANSFER_LENGTH_16); + + else + + /* Get the number of blocks from the CBWCB in 32 bits. */ + total_number_blocks = _ux_utility_long_get_big_endian(cbwcb + UX_SLAVE_CLASS_STORAGE_WRITE_TRANSFER_LENGTH_32); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_CLASS_STORAGE_WRITE, storage, lun, lba, total_number_blocks, UX_TRACE_DEVICE_CLASS_EVENTS, 0, 0) + + /* Obtain the pointer to the transfer request. */ + transfer_request = &endpoint_out -> ux_slave_endpoint_transfer_request; + + /* Obtain the status of the device. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_status(storage, + lun, storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_id, &media_status); + + /* Update the request sense. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* Default CSW to failed. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_FAILED; + + /* If there is a problem, return a failed command. */ + if (status != UX_SUCCESS) + { + + /* We have a problem, media status error. Return a bad completion and wait for the + REQUEST_SENSE command. */ +#if !defined(UX_DEVICE_STANDALONE) + _ux_device_stack_endpoint_stall(endpoint_out); +#endif + + /* We are done here. */ + return(UX_ERROR); + } + + /* Check Read Only flag. */ + if (storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_read_only_flag == UX_TRUE) + { + + /* Update the request sense. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(UX_SLAVE_CLASS_STORAGE_SENSE_KEY_DATA_PROTECT, + UX_SLAVE_CLASS_STORAGE_REQUEST_CODE_MEDIA_PROTECTED,0); + + /* We have a problem, cannot write to RO drive. Return a bad completion and wait for the + REQUEST_SENSE command. */ +#if !defined(UX_DEVICE_STANDALONE) + _ux_device_stack_endpoint_stall(endpoint_out); +#endif + + /* We are done here. */ + return(UX_ERROR); + } + + /* Compute the total length to transfer and how much remains. */ + total_length = total_number_blocks * storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_block_length; + +#if defined(UX_DEVICE_STANDALONE) + + /* Next: Transfer (DATA) -> Disk write. */ + storage -> ux_device_class_storage_state = UX_DEVICE_CLASS_STORAGE_STATE_TRANS_START; + storage -> ux_device_class_storage_cmd_state = UX_DEVICE_CLASS_STORAGE_CMD_WRITE; + storage -> ux_device_class_storage_disk_state = UX_DEVICE_CLASS_STORAGE_DISK_USB_WAIT; + storage -> ux_device_class_storage_buffer_state[0] = UX_DEVICE_CLASS_STORAGE_BUFFER_EMPTY; + storage -> ux_device_class_storage_buffer_state[1] = UX_DEVICE_CLASS_STORAGE_BUFFER_EMPTY; + storage -> ux_device_class_storage_buffer_usb = 0; + storage -> ux_device_class_storage_buffer_disk = 0; + + storage -> ux_device_class_storage_transfer = transfer_request; + storage -> ux_device_class_storage_device_length = total_length; + storage -> ux_device_class_storage_data_length = total_length; + storage -> ux_device_class_storage_data_count = 0; + + storage -> ux_device_class_storage_cmd_lba = lba; + storage -> ux_device_class_storage_cmd_n_lb = total_number_blocks; + +#else + + /* Check transfer length. */ + + /* Case (3) Hn < Do. */ + if (total_length > storage -> ux_slave_class_storage_host_length) + { + _ux_device_stack_endpoint_stall(endpoint_out); + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + return(UX_ERROR); + } + + /* Case (8). Hi <> Do. */ + if ((storage -> ux_slave_class_storage_cbw_flags & 0x80) != 0) + { + _ux_device_stack_endpoint_stall(endpoint_in); + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PHASE_ERROR; + return(UX_ERROR); + } + + /* Default status to success. */ + status = UX_SUCCESS; + + /* It may take several transfers to send the requested data. */ + done_length = 0; + while (total_length) + { + + /* How much can we receive in this transfer? */ + if (total_length > UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE) + transfer_length = UX_SLAVE_CLASS_STORAGE_BUFFER_SIZE; + else + transfer_length = total_length; + + /* Get the data payload from the host. */ + status = _ux_device_stack_transfer_request(transfer_request, transfer_length, transfer_length); + + /* Check the status. */ + if (status != UX_SUCCESS) + { + + /* We have a problem, request error. Return a bad completion and wait for the + REQUEST_SENSE command. */ + _ux_device_stack_endpoint_stall(endpoint_out); + + /* Update residue. */ + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length - done_length; + + /* And update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = + UX_DEVICE_CLASS_STORAGE_SENSE_STATUS(0x02,0x54,0x00); + + /* Return an error. */ + return(UX_ERROR); + } + + /* Compute the number of blocks to transfer. */ + number_blocks = transfer_length / storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_block_length; + + /* Execute the write command to the local media. */ + status = storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_media_write(storage, lun, transfer_request -> ux_slave_transfer_request_data_pointer, number_blocks, lba, &media_status); + + /* If there is a problem, return a failed command. */ + if (status != UX_SUCCESS) + { + + /* We have a problem, request error. Return a bad completion and wait for the + REQUEST_SENSE command. */ + _ux_device_stack_endpoint_stall(endpoint_out); + + /* Update residue. */ + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length - done_length; + + /* And update the REQUEST_SENSE codes. */ + storage -> ux_slave_class_storage_lun[lun].ux_slave_class_storage_request_sense_status = media_status; + + /* Return an error. */ + return(UX_ERROR); + } + + /* Update the lba. */ + lba += number_blocks; + + /* Update the length to remain. */ + total_length -= transfer_length; + done_length += transfer_length; + } + + /* Update residue. */ + storage -> ux_slave_class_storage_csw_residue = storage -> ux_slave_class_storage_host_length - done_length; + + /* Case (9), (11). If host expects more transfer, stall it. */ + if (storage -> ux_slave_class_storage_csw_residue) + _ux_device_stack_endpoint_stall(endpoint_out); + +#endif /* else defined(UX_DEVICE_STANDALONE) */ + + /* Now we set the CSW with success. */ + storage -> ux_slave_class_storage_csw_status = UX_SLAVE_CLASS_STORAGE_CSW_PASSED; + + /* Return completion status. */ + return(status); +} diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32.h b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32.h new file mode 100644 index 00000000..a51a989b --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32.h @@ -0,0 +1,180 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_dcd_stm32.h PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file defines the USB OTG device equivalences for the STM32 */ +/* controller. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* added bi-dir EP support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_DCD_STM32_H +#define UX_DCD_STM32_H + +#include "ux_stm32_config.h" + +/* Define STM32 generic equivalences. */ + +#define UX_DCD_STM32_SLAVE_CONTROLLER 0x80 +#ifndef UX_DCD_STM32_MAX_ED +#define UX_DCD_STM32_MAX_ED 4 +#endif /* UX_DCD_STM32_MAX_ED */ +#define UX_DCD_STM32_IN_FIFO 3 + + +#define UX_DCD_STM32_FLUSH_RX_FIFO 0x00000010 +#define UX_DCD_STM32_FLUSH_TX_FIFO 0x00000020 +#define UX_DCD_STM32_FLUSH_FIFO_ALL 0x00000010 +#define UX_DCD_STM32_ENDPOINT_SPACE_SIZE 0x00000020 +#define UX_DCD_STM32_ENDPOINT_CHANNEL_SIZE 0x00000020 + + +/* Define USB STM32 physical endpoint status definition. */ + +#define UX_DCD_STM32_ED_STATUS_UNUSED 0u +#define UX_DCD_STM32_ED_STATUS_USED 1u +#define UX_DCD_STM32_ED_STATUS_TRANSFER 2u +#define UX_DCD_STM32_ED_STATUS_STALLED 4u +#define UX_DCD_STM32_ED_STATUS_DONE 8u +#define UX_DCD_STM32_ED_STATUS_SETUP_IN (1u<<8) +#define UX_DCD_STM32_ED_STATUS_SETUP_STATUS (2u<<8) +#define UX_DCD_STM32_ED_STATUS_SETUP_OUT (3u<<8) +#define UX_DCD_STM32_ED_STATUS_SETUP (3u<<8) +#define UX_DCD_STM32_ED_STATUS_TASK_PENDING (1u<<10) + +/* Define USB STM32 physical endpoint state machine definition. */ + +#define UX_DCD_STM32_ED_STATE_IDLE 0 +#define UX_DCD_STM32_ED_STATE_DATA_TX 1 +#define UX_DCD_STM32_ED_STATE_DATA_RX 2 +#define UX_DCD_STM32_ED_STATE_STATUS_TX 3 +#define UX_DCD_STM32_ED_STATE_STATUS_RX 4 + +/* Define USB STM32 endpoint transfer status definition. */ + +#define UX_DCD_STM32_ED_TRANSFER_STATUS_IDLE 0 +#define UX_DCD_STM32_ED_TRANSFER_STATUS_SETUP 1 +#define UX_DCD_STM32_ED_TRANSFER_STATUS_IN_COMPLETION 2 +#define UX_DCD_STM32_ED_TRANSFER_STATUS_OUT_COMPLETION 3 + +/* Define USB STM32 physical endpoint structure. */ + +typedef struct UX_DCD_STM32_ED_STRUCT +{ + struct UX_SLAVE_ENDPOINT_STRUCT + *ux_dcd_stm32_ed_endpoint; + ULONG ux_dcd_stm32_ed_status; + UCHAR ux_dcd_stm32_ed_state; + UCHAR ux_dcd_stm32_ed_index; + UCHAR ux_dcd_stm32_ed_direction; + UCHAR reserved; +} UX_DCD_STM32_ED; + + +/* Define USB STM32 DCD structure definition. */ + +typedef struct UX_DCD_STM32_STRUCT +{ + + struct UX_SLAVE_DCD_STRUCT + *ux_dcd_stm32_dcd_owner; + struct UX_DCD_STM32_ED_STRUCT + ux_dcd_stm32_ed[UX_DCD_STM32_MAX_ED]; +#if defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) + struct UX_DCD_STM32_ED_STRUCT + ux_dcd_stm32_ed_in[UX_DCD_STM32_MAX_ED]; +#endif /* defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) */ + PCD_HandleTypeDef *pcd_handle; +} UX_DCD_STM32; + +static inline struct UX_DCD_STM32_ED_STRUCT *_stm32_ed_get(UX_DCD_STM32 *dcd_stm32, ULONG ep_addr) +{ +#if defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) +ULONG ep_dir = ep_addr & 0x80u; +#endif /* defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) */ +ULONG ep_num = ep_addr & 0x7Fu; + + if (ep_num >= UX_DCD_STM32_MAX_ED || + ep_num >= dcd_stm32->pcd_handle->Init.dev_endpoints) + return(UX_NULL); + +#if defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) + if (ep_dir) + return(&dcd_stm32->ux_dcd_stm32_ed_in[ep_num]); +#endif /* defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) */ + + return(&dcd_stm32->ux_dcd_stm32_ed[ep_num]); +} + + +/* Define USB STM32 DCD prototypes. */ + +UINT _ux_dcd_stm32_endpoint_create(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_dcd_stm32_endpoint_destroy(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_dcd_stm32_endpoint_reset(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_dcd_stm32_endpoint_stall(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_ENDPOINT *endpoint); +UINT _ux_dcd_stm32_endpoint_status(UX_DCD_STM32 *dcd_stm32, ULONG endpoint_index); +UINT _ux_dcd_stm32_frame_number_get(UX_DCD_STM32 *dcd_stm32, ULONG *frame_number); +UINT _ux_dcd_stm32_function(UX_SLAVE_DCD *dcd, UINT function, VOID *parameter); +UINT _ux_dcd_stm32_initialize_complete(VOID); +VOID _ux_dcd_stm32_interrupt_handler(VOID); +UINT _ux_dcd_stm32_transfer_abort(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_TRANSFER *transfer_request); + +#if !defined(UX_DEVICE_STANDALONE) +UINT _ux_dcd_stm32_transfer_request(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_TRANSFER *transfer_request); +#else +UINT _ux_dcd_stm32_transfer_run(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_TRANSFER *transfer_request); +#endif /* !defined(UX_DEVICE_STANDALONE) */ + +UINT _ux_dcd_stm32_initialize(ULONG dcd_io, ULONG parameter); +UINT _ux_dcd_stm32_uninitialize(ULONG dcd_io, ULONG parameter); + + +#define ux_dcd_stm32_initialize _ux_dcd_stm32_initialize +#define ux_dcd_stm32_interrupt_handler _ux_dcd_stm32_interrupt_handler + +#endif /* UX_DCD_STM32_H */ + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_callback.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_callback.c new file mode 100644 index 00000000..2626b79b --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_callback.c @@ -0,0 +1,963 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" +#include "ux_utility.h" + + +static inline void _ux_dcd_stm32_setup_in(UX_DCD_STM32_ED * ed, UX_SLAVE_TRANSFER *transfer_request) +{ + + /* The endpoint is IN. This is important to memorize the direction for the control endpoint + in case of a STALL. */ + ed -> ux_dcd_stm32_ed_direction = UX_ENDPOINT_IN; + + /* Set the state to TX. */ + ed -> ux_dcd_stm32_ed_state = UX_DCD_STM32_ED_STATE_DATA_TX; + + /* Call the Control Transfer dispatcher. */ + _ux_device_stack_control_request_process(transfer_request); +} + +static inline void _ux_dcd_stm32_setup_out(UX_DCD_STM32_ED * ed, UX_SLAVE_TRANSFER *transfer_request, + PCD_HandleTypeDef *hpcd) +{ + + /* Set the completion code to no error. */ + transfer_request -> ux_slave_transfer_request_completion_code = UX_SUCCESS; + + /* The endpoint is IN. This is important to memorize the direction for the control endpoint + in case of a STALL. */ + ed -> ux_dcd_stm32_ed_direction = UX_ENDPOINT_IN; + + /* We are using a Control endpoint on a OUT transaction and there was a payload. */ + if (_ux_device_stack_control_request_process(transfer_request) == UX_SUCCESS) + { + + /* Set the state to STATUS phase TX. */ + ed -> ux_dcd_stm32_ed_state = UX_DCD_STM32_ED_STATE_STATUS_TX; + + /* Arm the status transfer. */ + HAL_PCD_EP_Transmit(hpcd, 0x00U, UX_NULL, 0U); + } +} + +static inline void _ux_dcd_stm32_setup_status(UX_DCD_STM32_ED * ed, UX_SLAVE_TRANSFER *transfer_request, + PCD_HandleTypeDef *hpcd) +{ + + /* The endpoint is IN. This is important to memorize the direction for the control endpoint + in case of a STALL. */ + ed -> ux_dcd_stm32_ed_direction = UX_ENDPOINT_IN; + + /* Call the Control Transfer dispatcher. */ + if (_ux_device_stack_control_request_process(transfer_request) == UX_SUCCESS) + { + + /* Set the state to STATUS RX. */ + ed -> ux_dcd_stm32_ed_state = UX_DCD_STM32_ED_STATE_STATUS_RX; + HAL_PCD_EP_Transmit(hpcd, 0x00U, UX_NULL, 0U); + } +} + +#if defined(UX_DEVICE_STANDALONE) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_setup_isr_pending PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles pending control ISR from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hpcd Pointer to PCD handle */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_control_request_process */ +/* Process control request */ +/* HAL_PCD_EP_Transmit Transmit data */ +/* HAL_PCD_EP_Receive Receive data */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 HAL Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-31-2022 Chaoqiong Xiao Initial Version 6.1.10 */ +/* */ +/**************************************************************************/ +VOID _ux_dcd_stm32_setup_isr_pending(UX_DCD_STM32 *dcd_stm32) +{ +UX_INTERRUPT_SAVE_AREA +UX_DCD_STM32_ED *ed; +UX_SLAVE_TRANSFER *transfer_request; +ULONG ed_status; + + /* Fetch the address of the physical endpoint. */ + ed = &dcd_stm32 -> ux_dcd_stm32_ed[0]; + + /* Get the pointer to the transfer request. */ + transfer_request = &ed -> ux_dcd_stm32_ed_endpoint -> ux_slave_endpoint_transfer_request; + + UX_DISABLE + + /* Get the ED status. */ + ed_status = ed -> ux_dcd_stm32_ed_status; + + /* Check if Task is pending to avoid re-entry. */ + if (ed_status & UX_DCD_STM32_ED_STATUS_TASK_PENDING) + { + UX_RESTORE + return; + } + + /* Check if SETUP ISR is pending. */ + ed_status &= UX_DCD_STM32_ED_STATUS_SETUP; + if (ed_status == 0) + { + UX_RESTORE + return; + } + ed -> ux_dcd_stm32_ed_status &= ~UX_DCD_STM32_ED_STATUS_SETUP; + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_TASK_PENDING; + UX_RESTORE + + /* Handle different SETUP cases. */ + switch(ed_status) + { + case UX_DCD_STM32_ED_STATUS_SETUP_IN: + _ux_dcd_stm32_setup_in(ed, transfer_request); + break; + + case UX_DCD_STM32_ED_STATUS_SETUP_OUT: + _ux_dcd_stm32_setup_out(ed, transfer_request, dcd_stm32 -> pcd_handle); + break; + + default: /* UX_DCD_STM32_ED_STATUS_SETUP_STATUS */ + _ux_dcd_stm32_setup_status(ed, transfer_request, dcd_stm32 -> pcd_handle); + break; + } + + /* Task is done. */ + ed -> ux_dcd_stm32_ed_status &= ~UX_DCD_STM32_ED_STATUS_TASK_PENDING; +} +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_PCD_SetupStageCallback PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hpcd Pointer to PCD handle */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_control_request_process */ +/* Process control request */ +/* HAL_PCD_EP_Transmit Transmit data */ +/* HAL_PCD_EP_Receive Receive data */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 HAL Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) +{ + +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; +UX_DCD_STM32_ED *ed; +UX_SLAVE_TRANSFER *transfer_request; +UX_SLAVE_ENDPOINT *endpoint; + + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the STM32 DCD. */ + dcd_stm32 = (UX_DCD_STM32 *) dcd -> ux_slave_dcd_controller_hardware; + + /* Fetch the address of the physical endpoint. */ + ed = &dcd_stm32 -> ux_dcd_stm32_ed[0]; + + /* Get the pointer to the transfer request. */ + transfer_request = &ed -> ux_dcd_stm32_ed_endpoint -> ux_slave_endpoint_transfer_request; + + /* Copy setup data to transfer request. */ + _ux_utility_memory_copy(transfer_request->ux_slave_transfer_request_setup, hpcd -> Setup, UX_SETUP_SIZE); + + /* Clear the length of the data received. */ + transfer_request -> ux_slave_transfer_request_actual_length = 0; + + /* Mark the phase as SETUP. */ + transfer_request -> ux_slave_transfer_request_type = UX_TRANSFER_PHASE_SETUP; + + /* Mark the transfer as successful. */ + transfer_request -> ux_slave_transfer_request_completion_code = UX_SUCCESS; + + /* Set the status of the endpoint to not stalled. */ + ed -> ux_dcd_stm32_ed_status &= ~(UX_DCD_STM32_ED_STATUS_STALLED | + UX_DCD_STM32_ED_STATUS_TRANSFER | + UX_DCD_STM32_ED_STATUS_DONE); + + /* Check if the transaction is IN. */ + if (*transfer_request -> ux_slave_transfer_request_setup & UX_REQUEST_IN) + { +#if defined(UX_DEVICE_STANDALONE) + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_SETUP_IN; +#else + _ux_dcd_stm32_setup_in(ed, transfer_request); +#endif + } + else + { + + /* The endpoint is OUT. This is important to memorize the direction for the control endpoint + in case of a STALL. */ + ed -> ux_dcd_stm32_ed_direction = UX_ENDPOINT_OUT; + + /* We are in a OUT transaction. Check if there is a data payload. If so, wait for the payload + to be delivered. */ + if (*(transfer_request -> ux_slave_transfer_request_setup + 6) == 0 && + *(transfer_request -> ux_slave_transfer_request_setup + 7) == 0) + { +#if defined(UX_DEVICE_STANDALONE) + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_SETUP_STATUS; +#else + _ux_dcd_stm32_setup_status(ed, transfer_request, hpcd); +#endif + } + else + { + + /* Get the pointer to the logical endpoint from the transfer request. */ + endpoint = transfer_request -> ux_slave_transfer_request_endpoint; + + /* Get the length we expect from the SETUP packet. */ + transfer_request -> ux_slave_transfer_request_requested_length = _ux_utility_short_get(transfer_request -> ux_slave_transfer_request_setup + 6); + + /* Check if we have enough space for the request. */ + if (transfer_request -> ux_slave_transfer_request_requested_length > UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH) + { + + /* No space available, stall the endpoint. */ + _ux_dcd_stm32_endpoint_stall(dcd_stm32, endpoint); + + /* Next phase is a SETUP. */ + ed -> ux_dcd_stm32_ed_state = UX_DCD_STM32_ED_STATE_IDLE; + +#if defined(UX_DEVICE_STANDALONE) + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_SETUP_STATUS; +#endif + + /* We are done. */ + return; + } + else + { + + /* Reset what we have received so far. */ + transfer_request -> ux_slave_transfer_request_actual_length = 0; + + /* And reprogram the current buffer address to the beginning of the buffer. */ + transfer_request -> ux_slave_transfer_request_current_data_pointer = transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Receive data. */ + HAL_PCD_EP_Receive(hpcd, + endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress, + transfer_request -> ux_slave_transfer_request_current_data_pointer, + transfer_request -> ux_slave_transfer_request_requested_length); + + /* Set the state to RX. */ + ed -> ux_dcd_stm32_ed_state = UX_DCD_STM32_ED_STATE_DATA_RX; + } + } + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_PCD_DataInStageCallback PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hpcd Pointer to PCD handle */ +/* epnum Endpoint number */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_put Put semaphore */ +/* HAL_PCD_EP_Transmit Transmit data */ +/* HAL_PCD_EP_Receive Receive data */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 HAL Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* added bi-dir EP support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; +UX_DCD_STM32_ED *ed; +UX_SLAVE_TRANSFER *transfer_request; +ULONG transfer_length; +UX_SLAVE_ENDPOINT *endpoint; + + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the STM32 DCD. */ + dcd_stm32 = (UX_DCD_STM32 *) dcd -> ux_slave_dcd_controller_hardware; + + /* Fetch the address of the physical endpoint. */ +#if defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) + if ((epnum & 0xF) != 0) + ed = &dcd_stm32 -> ux_dcd_stm32_ed_in[epnum & 0xF]; + else +#endif /* defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) */ + ed = &dcd_stm32 -> ux_dcd_stm32_ed[epnum & 0xF]; + + /* Get the pointer to the transfer request. */ + transfer_request = &(ed -> ux_dcd_stm32_ed_endpoint -> ux_slave_endpoint_transfer_request); + + /* Endpoint 0 is different. */ + if (epnum == 0U) + { + + /* Get the pointer to the logical endpoint from the transfer request. */ + endpoint = transfer_request -> ux_slave_transfer_request_endpoint; + + /* Check if we need to send data again on control endpoint. */ + if (ed -> ux_dcd_stm32_ed_state == UX_DCD_STM32_ED_STATE_DATA_TX) + { + + /* Arm Status transfer. */ + HAL_PCD_EP_Receive(hpcd, 0, 0, 0); + + /* Are we done with this transfer ? */ + if (transfer_request -> ux_slave_transfer_request_in_transfer_length <= + endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize) + { + + /* There is no data to send but we may need to send a Zero Length Packet. */ + if (transfer_request -> ux_slave_transfer_request_force_zlp == UX_TRUE) + { + + /* Arm a ZLP packet on IN. */ + HAL_PCD_EP_Transmit(hpcd, + endpoint->ux_slave_endpoint_descriptor.bEndpointAddress, 0, 0); + + /* Reset the ZLP condition. */ + transfer_request -> ux_slave_transfer_request_force_zlp = UX_FALSE; + + } + else + { + + /* Set the completion code to no error. */ + transfer_request -> ux_slave_transfer_request_completion_code = UX_SUCCESS; + + /* The transfer is completed. */ + transfer_request -> ux_slave_transfer_request_status = UX_TRANSFER_STATUS_COMPLETED; + transfer_request -> ux_slave_transfer_request_actual_length = + transfer_request -> ux_slave_transfer_request_requested_length; + +#if defined(UX_DEVICE_STANDALONE) + + /* Control status phase done. */ + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_DONE; +#endif + + /* We are using a Control endpoint, if there is a callback, invoke it. We are still under ISR. */ + if (transfer_request -> ux_slave_transfer_request_completion_function) + transfer_request -> ux_slave_transfer_request_completion_function (transfer_request) ; + + /* State is now STATUS RX. */ + ed -> ux_dcd_stm32_ed_state = UX_DCD_STM32_ED_STATE_STATUS_RX; + } + } + else + { + + /* Get the size of the transfer. */ + transfer_length = transfer_request -> ux_slave_transfer_request_in_transfer_length - endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize; + + /* Check if the endpoint size is bigger that data requested. */ + if (transfer_length > endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize) + { + + /* Adjust the transfer size. */ + transfer_length = endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize; + } + + /* Adjust the data pointer. */ + transfer_request -> ux_slave_transfer_request_current_data_pointer += endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize; + + /* Adjust the transfer length remaining. */ + transfer_request -> ux_slave_transfer_request_in_transfer_length -= transfer_length; + + /* Transmit data. */ + HAL_PCD_EP_Transmit(hpcd, + endpoint->ux_slave_endpoint_descriptor.bEndpointAddress, + transfer_request->ux_slave_transfer_request_current_data_pointer, + transfer_length); + } + } + } + else + { + + /* Set the completion code to no error. */ + transfer_request -> ux_slave_transfer_request_completion_code = UX_SUCCESS; + + /* The transfer is completed. */ + transfer_request -> ux_slave_transfer_request_status = UX_TRANSFER_STATUS_COMPLETED; + transfer_request -> ux_slave_transfer_request_actual_length = + transfer_request -> ux_slave_transfer_request_requested_length; + +#if defined(UX_DEVICE_STANDALONE) + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_DONE; +#else + + /* Non control endpoint operation, use semaphore. */ + _ux_utility_semaphore_put(&transfer_request -> ux_slave_transfer_request_semaphore); +#endif /* defined(UX_DEVICE_STANDALONE) */ + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_PCD_DataOutStageCallback PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hpcd Pointer to PCD handle */ +/* epnum Endpoint number */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_control_request_process */ +/* Process control request */ +/* _ux_utility_semaphore_put Put semaphore */ +/* HAL_PCD_EP_Transmit Transmit data */ +/* HAL_PCD_EP_Receive Receive data */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 HAL Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ + +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; +UX_DCD_STM32_ED *ed; +UX_SLAVE_TRANSFER *transfer_request; +ULONG transfer_length; +UX_SLAVE_ENDPOINT *endpoint; + + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the STM32 DCD. */ + dcd_stm32 = (UX_DCD_STM32 *) dcd -> ux_slave_dcd_controller_hardware; + + /* Fetch the address of the physical endpoint. */ + ed = &dcd_stm32 -> ux_dcd_stm32_ed[epnum & 0xF]; + + /* Get the pointer to the transfer request. */ + transfer_request = &(ed -> ux_dcd_stm32_ed_endpoint -> ux_slave_endpoint_transfer_request); + + /* Endpoint 0 is different. */ + if (epnum == 0U) + { + + /* Check if we have received something on endpoint 0 during data phase . */ + if (ed -> ux_dcd_stm32_ed_state == UX_DCD_STM32_ED_STATE_DATA_RX) + { + + /* Get the pointer to the logical endpoint from the transfer request. */ + endpoint = transfer_request -> ux_slave_transfer_request_endpoint; + + /* Read the received data length for the Control endpoint. */ + transfer_length = HAL_PCD_EP_GetRxCount(hpcd, epnum); + + /* Update the length of the data received. */ + transfer_request -> ux_slave_transfer_request_actual_length += transfer_length; + + /* Can we accept this much? */ + if (transfer_request -> ux_slave_transfer_request_actual_length <= + transfer_request -> ux_slave_transfer_request_requested_length) + { + + /* Are we done with this transfer ? */ + if ((transfer_request -> ux_slave_transfer_request_actual_length == + transfer_request -> ux_slave_transfer_request_requested_length) || + (transfer_length != endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize)) + { +#if defined(UX_DEVICE_STANDALONE) + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_SETUP_OUT; +#else + _ux_dcd_stm32_setup_out(ed, transfer_request, hpcd); +#endif + } + else + { + + /* Rearm the OUT control endpoint for one packet. */ + transfer_request -> ux_slave_transfer_request_current_data_pointer += endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize; + HAL_PCD_EP_Receive(hpcd, + endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress, + transfer_request -> ux_slave_transfer_request_current_data_pointer, + endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize); + } + } + else + { + + /* We have an overflow situation. Set the completion code to overflow. */ + transfer_request -> ux_slave_transfer_request_completion_code = UX_TRANSFER_BUFFER_OVERFLOW; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_TRANSFER_BUFFER_OVERFLOW, transfer_request, 0, 0, UX_TRACE_ERRORS, 0, 0) + +#if defined(UX_DEVICE_STANDALONE) + + /* Control status phase done. */ + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_DONE; +#endif + + /* We are using a Control endpoint, if there is a callback, invoke it. We are still under ISR. */ + if (transfer_request -> ux_slave_transfer_request_completion_function) + transfer_request -> ux_slave_transfer_request_completion_function (transfer_request) ; + } + } + } + else + { + + + /* Update the length of the data sent in previous transaction. */ + transfer_request -> ux_slave_transfer_request_actual_length = HAL_PCD_EP_GetRxCount(hpcd, epnum); + + /* Set the completion code to no error. */ + transfer_request -> ux_slave_transfer_request_completion_code = UX_SUCCESS; + + /* The transfer is completed. */ + transfer_request -> ux_slave_transfer_request_status = UX_TRANSFER_STATUS_COMPLETED; + +#if defined(UX_DEVICE_STANDALONE) + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_DONE; +#else + + /* Non control endpoint operation, use semaphore. */ + _ux_utility_semaphore_put(&transfer_request -> ux_slave_transfer_request_semaphore); +#endif + } + +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_PCD_ResetCallback PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hpcd Pointer to PCD handle */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_disconnect Disconnect device */ +/* _ux_dcd_stm32_initialize_complete Complete initialization */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 HAL Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) +{ + + /* If the device is attached or configured, we need to disconnect it. */ + if (_ux_system_slave -> ux_system_slave_device.ux_slave_device_state != UX_DEVICE_RESET) + { + + /* Disconnect the device. */ + _ux_device_stack_disconnect(); + } + + /* Set USB Current Speed */ + switch(hpcd -> Init.speed) + { +#ifdef PCD_SPEED_HIGH + case PCD_SPEED_HIGH: + + /* We are connected at high speed. */ + _ux_system_slave -> ux_system_slave_speed = UX_HIGH_SPEED_DEVICE; + break; +#endif + case PCD_SPEED_FULL: + + /* We are connected at full speed. */ + _ux_system_slave -> ux_system_slave_speed = UX_FULL_SPEED_DEVICE; + break; + + default: + + /* We are connected at full speed. */ + _ux_system_slave -> ux_system_slave_speed = UX_FULL_SPEED_DEVICE; + break; + } + + /* Complete the device initialization. */ + _ux_dcd_stm32_initialize_complete(); + + /* Mark the device as attached now. */ + _ux_system_slave -> ux_system_slave_device.ux_slave_device_state = UX_DEVICE_ATTACHED; +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_PCD_DisconnectCallback PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hpcd Pointer to PCD handle */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* _ux_device_stack_disconnect Disconnect device */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 HAL Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) +{ + + /* Check if the device is attached or configured. */ + if (_ux_system_slave -> ux_system_slave_device.ux_slave_device_state != UX_DEVICE_RESET) + { + + /* Disconnect the device. */ + _ux_device_stack_disconnect(); + } +} + +#if defined(USBD_HAL_ISOINCOMPLETE_CALLBACK) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_PCD_ISOINIncompleteCallback PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hpcd Pointer to PCD handle */ +/* epnum Endpoint number */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_EP_Transmit Transmit data */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 HAL Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-31-2022 Chaoqiong Xiao Initial Version 6.1.10 */ +/* */ +/**************************************************************************/ +void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; +UX_DCD_STM32_ED *ed; +UX_SLAVE_ENDPOINT *endpoint; + + UX_PARAMETER_NOT_USED(epnum); + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the STM32 DCD. */ + dcd_stm32 = (UX_DCD_STM32 *) dcd -> ux_slave_dcd_controller_hardware; + +#if defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) + ed = &dcd_stm32 -> ux_dcd_stm32_ed_in[epnum & 0xF]; +#else + ed = &dcd_stm32 -> ux_dcd_stm32_ed[epnum & 0xF]; +#endif /* defined(UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT) */ + + if ((ed -> ux_dcd_stm32_ed_status & UX_DCD_STM32_ED_STATUS_USED) == 0U) + return; + + endpoint = ed->ux_dcd_stm32_ed_endpoint; + + if ((endpoint->ux_slave_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE) == 1 && + (endpoint->ux_slave_endpoint_descriptor.bEndpointAddress & UX_ENDPOINT_DIRECTION) != 0) + { + + /* Incomplete, discard data and retry. */ + HAL_PCD_EP_Transmit(dcd_stm32 -> pcd_handle, + endpoint->ux_slave_endpoint_descriptor.bEndpointAddress, + endpoint->ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer, + endpoint->ux_slave_endpoint_transfer_request.ux_slave_transfer_request_requested_length); + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_PCD_ISOOUTIncompleteCallback PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hpcd Pointer to PCD handle */ +/* epnum Endpoint number */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_EP_Receive Receive data */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 HAL Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-31-2022 Chaoqiong Xiao Initial Version 6.1.10 */ +/* */ +/**************************************************************************/ +void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) +{ +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; +UX_DCD_STM32_ED *ed; +UX_SLAVE_ENDPOINT *endpoint; + + UX_PARAMETER_NOT_USED(epnum); + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the STM32 DCD. */ + dcd_stm32 = (UX_DCD_STM32 *) dcd -> ux_slave_dcd_controller_hardware; + + ed = &dcd_stm32 -> ux_dcd_stm32_ed[epnum & 0xF]; + if ((ed -> ux_dcd_stm32_ed_status & UX_DCD_STM32_ED_STATUS_USED) == 0) + return; + + endpoint = ed->ux_dcd_stm32_ed_endpoint; + + if ((endpoint->ux_slave_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE) == 1 && + (endpoint->ux_slave_endpoint_descriptor.bEndpointAddress & UX_ENDPOINT_DIRECTION) == 0) + { + + /* Incomplete, discard data and retry. */ + HAL_PCD_EP_Receive(dcd_stm32 -> pcd_handle, + endpoint->ux_slave_endpoint_descriptor.bEndpointAddress, + endpoint->ux_slave_endpoint_transfer_request.ux_slave_transfer_request_data_pointer, + endpoint->ux_slave_endpoint_transfer_request.ux_slave_transfer_request_requested_length); + } +} +#endif /* defined(USBD_HAL_ISOINCOMPLETE_CALLBACK) */ diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_create.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_create.c new file mode 100644 index 00000000..48b0f713 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_create.c @@ -0,0 +1,128 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_endpoint_create PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will create a physical endpoint. */ +/* */ +/* INPUT */ +/* */ +/* dcd_stm32 Pointer to device controller */ +/* endpoint Pointer to endpoint container */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_EP_Open Open endpoint */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_endpoint_create(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_ENDPOINT *endpoint) +{ + +UX_DCD_STM32_ED *ed; +ULONG stm32_endpoint_index; + + + /* The endpoint index in the array of the STM32 must match the endpoint number. */ + stm32_endpoint_index = endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress & ~UX_ENDPOINT_DIRECTION; + + /* Get STM32 ED. */ + ed = _stm32_ed_get(dcd_stm32, endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress); + + if (ed == UX_NULL) + return(UX_NO_ED_AVAILABLE); + + /* Check the endpoint status, if it is free, reserve it. If not reject this endpoint. */ + if ((ed -> ux_dcd_stm32_ed_status & UX_DCD_STM32_ED_STATUS_USED) == 0) + { + + /* We can use this endpoint. */ + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_USED; + + /* Keep the physical endpoint address in the endpoint container. */ + endpoint -> ux_slave_endpoint_ed = (VOID *) ed; + + /* Save the endpoint pointer. */ + ed -> ux_dcd_stm32_ed_endpoint = endpoint; + + /* And its index. */ + ed -> ux_dcd_stm32_ed_index = stm32_endpoint_index; + + /* And its direction. */ + ed -> ux_dcd_stm32_ed_direction = endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress & UX_ENDPOINT_DIRECTION; + + /* Check if it is non-control endpoint. */ + if (stm32_endpoint_index != 0) + { + + /* Open the endpoint. */ + HAL_PCD_EP_Open(dcd_stm32 -> pcd_handle, endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress, + endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize, + endpoint -> ux_slave_endpoint_descriptor.bmAttributes & UX_MASK_ENDPOINT_TYPE); + } + + /* Return successful completion. */ + return(UX_SUCCESS); + } + + /* Return an error. */ + return(UX_NO_ED_AVAILABLE); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_destroy.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_destroy.c new file mode 100644 index 00000000..ecc45f94 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_destroy.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_endpoint_destroy PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will destroy a physical endpoint. */ +/* */ +/* INPUT */ +/* */ +/* dcd_stm32 Pointer to device controller */ +/* endpoint Pointer to endpoint container */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_EP_Close Deactivate endpoint */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_endpoint_destroy(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_ENDPOINT *endpoint) +{ + +UX_DCD_STM32_ED *ed; + + + /* Keep the physical endpoint address in the endpoint container. */ + ed = (UX_DCD_STM32_ED *) endpoint -> ux_slave_endpoint_ed; + + /* We can free this endpoint. */ + ed -> ux_dcd_stm32_ed_status = UX_DCD_STM32_ED_STATUS_UNUSED; + + /* Deactivate the endpoint. */ + HAL_PCD_EP_Close(dcd_stm32 -> pcd_handle, endpoint->ux_slave_endpoint_descriptor.bEndpointAddress); + + /* This function never fails. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_reset.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_reset.c new file mode 100644 index 00000000..1f603600 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_reset.c @@ -0,0 +1,116 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_endpoint_reset PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will reset a physical endpoint. */ +/* */ +/* INPUT */ +/* */ +/* dcd_stm32 Pointer to device controller */ +/* endpoint Pointer to endpoint container */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_EP_ClrStall Clear STALL */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_endpoint_reset(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_ENDPOINT *endpoint) +{ + +UX_INTERRUPT_SAVE_AREA +UX_DCD_STM32_ED *ed; + + + /* Get the physical endpoint address in the endpoint container. */ + ed = (UX_DCD_STM32_ED *) endpoint -> ux_slave_endpoint_ed; + + UX_DISABLE + + /* Set the status of the endpoint to not stalled. */ + ed -> ux_dcd_stm32_ed_status &= ~(UX_DCD_STM32_ED_STATUS_STALLED | + UX_DCD_STM32_ED_STATUS_DONE | + UX_DCD_STM32_ED_STATUS_SETUP); + + /* Set the state of the endpoint to IDLE. */ + ed -> ux_dcd_stm32_ed_state = UX_DCD_STM32_ED_STATE_IDLE; + + /* Clear STALL condition. */ + HAL_PCD_EP_ClrStall(dcd_stm32 -> pcd_handle, endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress); + + /* Flush buffer. */ + HAL_PCD_EP_Flush(dcd_stm32 -> pcd_handle, endpoint->ux_slave_endpoint_descriptor.bEndpointAddress); + +#ifndef UX_DEVICE_STANDALONE + + /* Wakeup pending thread. */ + if (endpoint -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_semaphore.tx_semaphore_suspended_count) + _ux_utility_semaphore_put(&endpoint -> ux_slave_endpoint_transfer_request.ux_slave_transfer_request_semaphore); +#endif + + UX_RESTORE + + /* This function never fails. */ + return(UX_SUCCESS); +} diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_stall.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_stall.c new file mode 100644 index 00000000..bece7b5e --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_stall.c @@ -0,0 +1,94 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_endpoint_stall PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will stall a physical endpoint. */ +/* */ +/* INPUT */ +/* */ +/* dcd_stm32 Pointer to device controller */ +/* endpoint Pointer to endpoint container */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_EP_SetStall Set STALL condition */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_endpoint_stall(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_ENDPOINT *endpoint) +{ + +UX_DCD_STM32_ED *ed; + + + /* Get the physical endpoint address in the endpoint container. */ + ed = (UX_DCD_STM32_ED *) endpoint -> ux_slave_endpoint_ed; + + /* Set the endpoint to stall. */ + ed -> ux_dcd_stm32_ed_status |= UX_DCD_STM32_ED_STATUS_STALLED; + + /* Stall the endpoint. */ + HAL_PCD_EP_SetStall(dcd_stm32 -> pcd_handle, endpoint->ux_slave_endpoint_descriptor.bEndpointAddress | ed -> ux_dcd_stm32_ed_direction); + + /* This function never fails. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_status.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_status.c new file mode 100644 index 00000000..cf85e3b4 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_endpoint_status.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_endpoint_status PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will retrieve the status of the endpoint. */ +/* */ +/* INPUT */ +/* */ +/* dcd_stm32 Pointer to device controller */ +/* endpoint_index Endpoint index */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added bi-dir EP support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_endpoint_status(UX_DCD_STM32 *dcd_stm32, ULONG endpoint_index) +{ + +UX_DCD_STM32_ED *ed; + + + /* Fetch the address of the physical endpoint. */ + ed = _stm32_ed_get(dcd_stm32, endpoint_index); + + /* Check the endpoint status, if it is free, we have a illegal endpoint. */ + if ((ed -> ux_dcd_stm32_ed_status & UX_DCD_STM32_ED_STATUS_USED) == 0) + return(UX_ERROR); + + /* Check if the endpoint is stalled. */ + if ((ed -> ux_dcd_stm32_ed_status & UX_DCD_STM32_ED_STATUS_STALLED) == 0) + return(UX_FALSE); + else + return(UX_TRUE); +} diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_frame_number_get.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_frame_number_get.c new file mode 100644 index 00000000..08628e56 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_frame_number_get.c @@ -0,0 +1,83 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_frame_number_get PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will return the frame number currently used by the */ +/* controller. This function is mostly used for isochronous purposes. */ +/* */ +/* INPUT */ +/* */ +/* dcd_stm32 Pointer to device controller */ +/* frame_number Destination for frame number */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_dcd_stm32_register_read Read register */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_frame_number_get(UX_DCD_STM32 *dcd_stm32, ULONG *frame_number) +{ + + /* This function never fails. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_function.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_function.c new file mode 100644 index 00000000..ee6c5408 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_function.c @@ -0,0 +1,203 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +#if defined(UX_DEVICE_STANDALONE) +extern VOID _ux_dcd_stm32_setup_isr_pending(UX_DCD_STM32 *); +#endif + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_function PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function dispatches the DCD function internally to the STM32 */ +/* controller. */ +/* */ +/* INPUT */ +/* */ +/* dcd Pointer to device controller */ +/* function Function requested */ +/* parameter Pointer to function parameters*/ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_dcd_stm32_endpoint_create Create endpoint */ +/* _ux_dcd_stm32_endpoint_destroy Destroy endpoint */ +/* _ux_dcd_stm32_endpoint_reset Reset endpoint */ +/* _ux_dcd_stm32_endpoint_stall Stall endpoint */ +/* _ux_dcd_stm32_endpoint_status Get endpoint status */ +/* _ux_dcd_stm32_frame_number_get Get frame number */ +/* _ux_dcd_stm32_transfer_request Request data transfer */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* added standalone support, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_function(UX_SLAVE_DCD *dcd, UINT function, VOID *parameter) +{ + +UINT status; +UX_DCD_STM32 *dcd_stm32; + + + /* Check the status of the controller. */ + if (dcd -> ux_slave_dcd_status == UX_UNUSED) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_DCD, UX_CONTROLLER_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_CONTROLLER_UNKNOWN, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_CONTROLLER_UNKNOWN); + } + + /* Get the pointer to the STM32 DCD. */ + dcd_stm32 = (UX_DCD_STM32 *) dcd -> ux_slave_dcd_controller_hardware; + + /* Look at the function and route it. */ + switch(function) + { + + case UX_DCD_GET_FRAME_NUMBER: + + status = _ux_dcd_stm32_frame_number_get(dcd_stm32, (ULONG *) parameter); + break; + + case UX_DCD_TRANSFER_REQUEST: + +#if defined(UX_DEVICE_STANDALONE) + status = _ux_dcd_stm32_transfer_run(dcd_stm32, (UX_SLAVE_TRANSFER *) parameter); +#else + status = _ux_dcd_stm32_transfer_request(dcd_stm32, (UX_SLAVE_TRANSFER *) parameter); +#endif /* defined(UX_DEVICE_STANDALONE) */ + break; + + case UX_DCD_TRANSFER_ABORT: + status = _ux_dcd_stm32_transfer_abort(dcd_stm32, parameter); + break; + + case UX_DCD_CREATE_ENDPOINT: + + status = _ux_dcd_stm32_endpoint_create(dcd_stm32, parameter); + break; + + case UX_DCD_DESTROY_ENDPOINT: + + status = _ux_dcd_stm32_endpoint_destroy(dcd_stm32, parameter); + break; + + case UX_DCD_RESET_ENDPOINT: + + status = _ux_dcd_stm32_endpoint_reset(dcd_stm32, parameter); + break; + + case UX_DCD_STALL_ENDPOINT: + + status = _ux_dcd_stm32_endpoint_stall(dcd_stm32, parameter); + break; + + case UX_DCD_SET_DEVICE_ADDRESS: + + status = HAL_PCD_SetAddress(dcd_stm32 -> pcd_handle, (uint8_t)(ULONG) parameter); + break; + + case UX_DCD_CHANGE_STATE: + + if ((ULONG) parameter == UX_DEVICE_FORCE_DISCONNECT) + { + /* Disconnect the USB device */ + status = HAL_PCD_Stop(dcd_stm32 -> pcd_handle); + } + else + { + status = UX_SUCCESS; + } + + break; + + case UX_DCD_ENDPOINT_STATUS: + + status = _ux_dcd_stm32_endpoint_status(dcd_stm32, (ULONG) parameter); + break; + +#if defined(UX_DEVICE_STANDALONE) + case UX_DCD_ISR_PENDING: + + _ux_dcd_stm32_setup_isr_pending(dcd_stm32); + status = UX_SUCCESS; + break; +#endif /* defined(UX_DEVICE_STANDALONE) */ + + default: + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_DCD, UX_FUNCTION_NOT_SUPPORTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_FUNCTION_NOT_SUPPORTED, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + status = UX_FUNCTION_NOT_SUPPORTED; + break; + } + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_initialize.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_initialize.c new file mode 100644 index 00000000..0b3c84e8 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_initialize.c @@ -0,0 +1,122 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_initialize PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the USB device controller of the STM32 */ +/* microcontroller from ST. */ +/* */ +/* Note: only software structures that are necessary for STM32 HAL to */ +/* work is initialized, STM32 HAL APIs should be used to initialize */ +/* controller hardware AFTER the function is invoked. */ +/* */ +/* INPUT */ +/* */ +/* dcd_io Address of DCD, not used */ +/* parameter Parameter, STM32 HAL PCD */ +/* pointer is expected */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_Init Initialize LL driver */ +/* _ux_utility_memory_allocate Allocate memory */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_initialize(ULONG dcd_io, ULONG parameter) +{ + +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; + + + UX_PARAMETER_NOT_USED(dcd_io); + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* The controller initialized here is of STM32 type. */ + dcd -> ux_slave_dcd_controller_type = UX_DCD_STM32_SLAVE_CONTROLLER; + + /* Allocate memory for this STM32 DCD instance. */ + dcd_stm32 = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_DCD_STM32)); + + /* Check if memory was properly allocated. */ + if(dcd_stm32 == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* Set the pointer to the STM32 DCD. */ + dcd -> ux_slave_dcd_controller_hardware = (VOID *) dcd_stm32; + + /* Set the generic DCD owner for the STM32 DCD. */ + dcd_stm32 -> ux_dcd_stm32_dcd_owner = dcd; + + /* Initialize the function collector for this DCD. */ + dcd -> ux_slave_dcd_function = _ux_dcd_stm32_function; + + dcd_stm32 -> pcd_handle = (PCD_HandleTypeDef *)parameter; + + /* Set the state of the controller to OPERATIONAL now. */ + dcd -> ux_slave_dcd_status = UX_DCD_STATUS_OPERATIONAL; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_initialize_complete.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_initialize_complete.c new file mode 100644 index 00000000..a14eca24 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_initialize_complete.c @@ -0,0 +1,215 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_system.h" +#include "ux_utility.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_initialize_complete PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function completes the initialization of the USB slave */ +/* controller for the STM32 chip. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* (ux_slave_dcd_function) Process the DCD function */ +/* _ux_utility_descriptor_parse Parse descriptor */ +/* _ux_utility_memory_allocate Allocate memory */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), */ +/* prefixed UX to MS_TO_TICK, */ +/* used ST HAL library to */ +/* drive the controller, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_initialize_complete(VOID) +{ + +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; +UX_SLAVE_DEVICE *device; +UCHAR *device_framework; +UX_SLAVE_TRANSFER *transfer_request; + + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the STM32 DCD. */ + dcd_stm32 = (UX_DCD_STM32 *) dcd -> ux_slave_dcd_controller_hardware; + + /* Get the pointer to the device. */ + device = &_ux_system_slave -> ux_system_slave_device; + + /* Are we in DFU mode ? If so, check if we are in a Reset mode. */ + if (_ux_system_slave -> ux_system_slave_device_dfu_state_machine == UX_SYSTEM_DFU_STATE_APP_DETACH) + { + + /* The device is now in DFU reset mode. Switch to the DFU device framework. */ + _ux_system_slave -> ux_system_slave_device_framework = _ux_system_slave -> ux_system_slave_dfu_framework; + _ux_system_slave -> ux_system_slave_device_framework_length = _ux_system_slave -> ux_system_slave_dfu_framework_length; + + } + else + { + + /* Set State to App Idle. */ + _ux_system_slave -> ux_system_slave_device_dfu_state_machine = UX_SYSTEM_DFU_STATE_APP_IDLE; + + /* Check the speed and set the correct descriptor. */ + if (_ux_system_slave -> ux_system_slave_speed == UX_FULL_SPEED_DEVICE) + { + + /* The device is operating at full speed. */ + _ux_system_slave -> ux_system_slave_device_framework = _ux_system_slave -> ux_system_slave_device_framework_full_speed; + _ux_system_slave -> ux_system_slave_device_framework_length = _ux_system_slave -> ux_system_slave_device_framework_length_full_speed; + } + else + { + + /* The device is operating at high speed. */ + _ux_system_slave -> ux_system_slave_device_framework = _ux_system_slave -> ux_system_slave_device_framework_high_speed; + _ux_system_slave -> ux_system_slave_device_framework_length = _ux_system_slave -> ux_system_slave_device_framework_length_high_speed; + } + } + + /* Get the device framework pointer. */ + device_framework = _ux_system_slave -> ux_system_slave_device_framework; + + /* And create the decompressed device descriptor structure. */ + _ux_utility_descriptor_parse(device_framework, + _ux_system_device_descriptor_structure, + UX_DEVICE_DESCRIPTOR_ENTRIES, + (UCHAR *) &device -> ux_slave_device_descriptor); + + /* Now we create a transfer request to accept the first SETUP packet + and get the ball running. First get the address of the endpoint + transfer request container. */ + transfer_request = &device -> ux_slave_device_control_endpoint.ux_slave_endpoint_transfer_request; + + /* Set the timeout to be for Control Endpoint. */ + transfer_request -> ux_slave_transfer_request_timeout = UX_MS_TO_TICK(UX_CONTROL_TRANSFER_TIMEOUT); + + /* Adjust the current data pointer as well. */ + transfer_request -> ux_slave_transfer_request_current_data_pointer = + transfer_request -> ux_slave_transfer_request_data_pointer; + + /* Update the transfer request endpoint pointer with the default endpoint. */ + transfer_request -> ux_slave_transfer_request_endpoint = &device -> ux_slave_device_control_endpoint; + + /* The control endpoint max packet size needs to be filled manually in its descriptor. */ + transfer_request -> ux_slave_transfer_request_endpoint -> ux_slave_endpoint_descriptor.wMaxPacketSize = + device -> ux_slave_device_descriptor.bMaxPacketSize0; + + /* On the control endpoint, always expect the maximum. */ + transfer_request -> ux_slave_transfer_request_requested_length = + device -> ux_slave_device_descriptor.bMaxPacketSize0; + + /* Attach the control endpoint to the transfer request. */ + transfer_request -> ux_slave_transfer_request_endpoint = &device -> ux_slave_device_control_endpoint; + + /* Create the default control endpoint attached to the device. + Once this endpoint is enabled, the host can then send a setup packet + The device controller will receive it and will call the setup function + module. */ + dcd -> ux_slave_dcd_function(dcd, UX_DCD_CREATE_ENDPOINT, + (VOID *) &device -> ux_slave_device_control_endpoint); + + /* Open Control OUT endpoint. */ + HAL_PCD_EP_Flush(dcd_stm32 -> pcd_handle, 0x00U); + HAL_PCD_EP_Open(dcd_stm32 -> pcd_handle, 0x00U, device -> ux_slave_device_descriptor.bMaxPacketSize0, UX_CONTROL_ENDPOINT); + + /* Open Control IN endpoint. */ + HAL_PCD_EP_Flush(dcd_stm32 -> pcd_handle, 0x80U); + HAL_PCD_EP_Open(dcd_stm32 -> pcd_handle, 0x80U, device -> ux_slave_device_descriptor.bMaxPacketSize0, UX_CONTROL_ENDPOINT); + + /* Ensure the control endpoint is properly reset. */ + device -> ux_slave_device_control_endpoint.ux_slave_endpoint_state = UX_ENDPOINT_RESET; + + /* Mark the phase as SETUP. */ + transfer_request -> ux_slave_transfer_request_type = UX_TRANSFER_PHASE_SETUP; + + /* Mark this transfer request as pending. */ + transfer_request -> ux_slave_transfer_request_status = UX_TRANSFER_STATUS_PENDING; + + /* Ask for 8 bytes of the SETUP packet. */ + transfer_request -> ux_slave_transfer_request_requested_length = UX_SETUP_SIZE; + transfer_request -> ux_slave_transfer_request_in_transfer_length = UX_SETUP_SIZE; + + /* Reset the number of bytes sent/received. */ + transfer_request -> ux_slave_transfer_request_actual_length = 0; + + /* Check the status change callback. */ + if(_ux_system_slave -> ux_system_slave_change_function != UX_NULL) + { + + /* Inform the application if a callback function was programmed. */ + _ux_system_slave -> ux_system_slave_change_function(UX_DEVICE_ATTACHED); + } + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_DEVICE_STACK_CONNECT, 0, 0, 0, 0, UX_TRACE_DEVICE_STACK_EVENTS, 0, 0) + + /* If trace is enabled, register this object. */ + UX_TRACE_OBJECT_REGISTER(UX_TRACE_DEVICE_OBJECT_TYPE_DEVICE, device, 0, 0, 0) + + /* We are now ready for the USB device to accept the first packet when connected. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_interrupt_handler.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_interrupt_handler.c new file mode 100644 index 00000000..cd00cf00 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_interrupt_handler.c @@ -0,0 +1,95 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" +#include "ux_system.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_interrupt_handler PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the interrupt handler for the STM32 controller. */ +/* The controller will trigger an interrupt when something happens on */ +/* an endpoint whose mask has been set in the interrupt enable */ +/* register, or when a bus reset is detected. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_IRQHandler HAL IRQ handler */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +VOID _ux_dcd_stm32_interrupt_handler(VOID) +{ + + +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; + + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Get the pointer to the STM32 DCD. */ + dcd_stm32 = (UX_DCD_STM32 *) dcd -> ux_slave_dcd_controller_hardware; + + /* Call the actual interrupt handler function. */ + HAL_PCD_IRQHandler(dcd_stm32 -> pcd_handle); + +} diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_transfer_abort.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_transfer_abort.c new file mode 100644 index 00000000..d79c6401 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_transfer_abort.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_utility.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_transfer_request PORTABLE C */ +/* 6.1.10 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will initiate a transfer to a specific endpoint. */ +/* If the endpoint is IN, the endpoint register will be set to accept */ +/* the request. */ +/* */ +/* If the endpoint is IN, the endpoint FIFO will be filled with the */ +/* buffer and the endpoint register set. */ +/* */ +/* INPUT */ +/* */ +/* dcd_stm32 Pointer to device controller */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_EP_Transmit Transmit data */ +/* HAL_PCD_EP_Receive Receive data */ +/* _ux_utility_semaphore_get Get semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 01-31-2022 Chaoqiong Xiao Initial Version 6.1.10 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_transfer_abort(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_TRANSFER *transfer_request) +{ + +UX_SLAVE_ENDPOINT *endpoint; + + + /* Get the pointer to the logical endpoint from the transfer request. */ + endpoint = transfer_request -> ux_slave_transfer_request_endpoint; + + HAL_PCD_EP_Abort(dcd_stm32 -> pcd_handle, endpoint->ux_slave_endpoint_descriptor.bEndpointAddress); + HAL_PCD_EP_Flush(dcd_stm32 -> pcd_handle, endpoint->ux_slave_endpoint_descriptor.bEndpointAddress); + + /* No semaphore put here since it's already done in stack. */ + + /* Return to caller with success. */ + return(UX_SUCCESS); +} diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_transfer_request.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_transfer_request.c new file mode 100644 index 00000000..b7634835 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_transfer_request.c @@ -0,0 +1,166 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_utility.h" +#include "ux_device_stack.h" + + +#if !defined(UX_DEVICE_STANDALONE) +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_transfer_request PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will initiate a transfer to a specific endpoint. */ +/* If the endpoint is IN, the endpoint register will be set to accept */ +/* the request. */ +/* */ +/* If the endpoint is IN, the endpoint FIFO will be filled with the */ +/* buffer and the endpoint register set. */ +/* */ +/* INPUT */ +/* */ +/* dcd_stm32 Pointer to device controller */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* */ +/* CALLS */ +/* */ +/* HAL_PCD_EP_Transmit Transmit data */ +/* HAL_PCD_EP_Receive Receive data */ +/* _ux_utility_semaphore_get Get semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* 09-30-2020 Chaoqiong Xiao Modified comment(s), used ST */ +/* HAL library to drive the */ +/* controller, */ +/* resulting in version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_transfer_request(UX_DCD_STM32 *dcd_stm32, UX_SLAVE_TRANSFER *transfer_request) +{ + +UX_SLAVE_ENDPOINT *endpoint; +UINT status; + + + /* Get the pointer to the logical endpoint from the transfer request. */ + endpoint = transfer_request -> ux_slave_transfer_request_endpoint; + + /* Check for transfer direction. Is this a IN endpoint ? */ + if (transfer_request -> ux_slave_transfer_request_phase == UX_TRANSFER_PHASE_DATA_OUT) + { + + /* Transmit data. */ + HAL_PCD_EP_Transmit(dcd_stm32 -> pcd_handle, + endpoint->ux_slave_endpoint_descriptor.bEndpointAddress, + transfer_request->ux_slave_transfer_request_data_pointer, + transfer_request->ux_slave_transfer_request_requested_length); + + /* If the endpoint is a Control endpoint, all this is happening under Interrupt and there is no + thread to suspend. */ + if ((endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress & (UINT)~UX_ENDPOINT_DIRECTION) != 0) + { + + /* We should wait for the semaphore to wake us up. */ + status = _ux_utility_semaphore_get(&transfer_request -> ux_slave_transfer_request_semaphore, + (ULONG)transfer_request -> ux_slave_transfer_request_timeout); + + /* Check the completion code. */ + if (status != UX_SUCCESS) + return(status); + + transfer_request -> ux_slave_transfer_request_actual_length = transfer_request->ux_slave_transfer_request_requested_length; + + /* Check the transfer request completion code. We may have had a BUS reset or + a device disconnection. */ + if (transfer_request -> ux_slave_transfer_request_completion_code != UX_SUCCESS) + return(transfer_request -> ux_slave_transfer_request_completion_code); + + /* Return to caller with success. */ + return(UX_SUCCESS); + } + } + else + { + + /* We have a request for a SETUP or OUT Endpoint. */ + /* Receive data. */ + HAL_PCD_EP_Receive(dcd_stm32 -> pcd_handle, + endpoint->ux_slave_endpoint_descriptor.bEndpointAddress, + transfer_request->ux_slave_transfer_request_data_pointer, + transfer_request->ux_slave_transfer_request_requested_length); + + /* If the endpoint is a Control endpoint, all this is happening under Interrupt and there is no + thread to suspend. */ + if ((endpoint -> ux_slave_endpoint_descriptor.bEndpointAddress & (UINT)~UX_ENDPOINT_DIRECTION) != 0) + { + + /* We should wait for the semaphore to wake us up. */ + status = _ux_utility_semaphore_get(&transfer_request -> ux_slave_transfer_request_semaphore, + (ULONG)transfer_request -> ux_slave_transfer_request_timeout); + + /* Check the completion code. */ + if (status != UX_SUCCESS) + return(status); + + /* Check the transfer request completion code. We may have had a BUS reset or + a device disconnection. */ + if (transfer_request -> ux_slave_transfer_request_completion_code != UX_SUCCESS) + return(transfer_request -> ux_slave_transfer_request_completion_code); + + /* Return to caller with success. */ + return(UX_SUCCESS); + } + } + + /* Return to caller with success. */ + return(UX_SUCCESS); +} +#endif diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_uninitialize.c b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_uninitialize.c new file mode 100644 index 00000000..21ff23c7 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_device_controllers/ux_dcd_stm32_uninitialize.c @@ -0,0 +1,105 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +#define UX_SOURCE_CODE +#define UX_DCD_STM32_SOURCE_CODE + + +/* Include necessary system files. */ + +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_dcd_stm32_uninitialize PORTABLE C */ +/* 6.1 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function uninitializes the USB device controller of the STM32 */ +/* microcontroller from ST. */ +/* */ +/* Note: only software structures are uninitialized. STM32 HAL APIs */ +/* must be used to uninitialize controller hardware BEFORE the */ +/* function is invoked. */ +/* */ +/* INPUT */ +/* */ +/* dcd Address of DCD, not used */ +/* parameter Parameter, STM32 HAL PCD */ +/* pointer is expected */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* */ +/* CALLED BY */ +/* */ +/* USBX Device Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 09-30-2020 Chaoqiong Xiao Initial Version 6.1 */ +/* */ +/**************************************************************************/ +UINT _ux_dcd_stm32_uninitialize(ULONG dcd_io, ULONG parameter) +{ + +UX_SLAVE_DCD *dcd; +UX_DCD_STM32 *dcd_stm32; + + + UX_PARAMETER_NOT_USED(dcd_io); + + /* Get the pointer to the DCD. */ + dcd = &_ux_system_slave -> ux_system_slave_dcd; + + /* Set the state of the controller to HALTED now. */ + dcd -> ux_slave_dcd_status = UX_DCD_STATUS_HALTED; + + /* Get controller driver. */ + dcd_stm32 = (UX_DCD_STM32 *)dcd -> ux_slave_dcd_controller_hardware; + + /* Check parameter. */ + if ((ULONG)dcd_stm32 -> pcd_handle == parameter) + { + _ux_utility_memory_free(dcd_stm32); + dcd -> ux_slave_dcd_controller_hardware = UX_NULL; + return(UX_SUCCESS); + } + + /* Parameter not correct. */ + return(UX_ERROR); +} diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32.h b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32.h new file mode 100644 index 00000000..507ef6d0 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32.h @@ -0,0 +1,157 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* COMPONENT DEFINITION RELEASE */ +/* */ +/* ux_hcd_stm32.h PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains all the header and extern functions used by the */ +/* USBX host STM32 Controller. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ + +#ifndef UX_HCD_STM32_H +#define UX_HCD_STM32_H + +#include "ux_stm32_config.h" + +/* Define STM32 HCD generic definitions. */ + + +#define UX_HCD_STM32_CONTROLLER 6 +#ifndef UX_HCD_STM32_MAX_NB_CHANNELS +#define UX_HCD_STM32_MAX_NB_CHANNELS 12 +#endif /* UX_HCD_STM32_MAX_NB_CHANNELS */ +#define UX_HCD_STM32_NB_ROOT_PORTS 1 +#define UX_HCD_STM32_NO_CHANNEL_ASSIGNED 0xff +#define UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_ATTACHED 0x01 +#define UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_DETACHED 0x02 +#define UX_HCD_STM32_CONTROLLER_FLAG_SOF 0x04 +#define UX_HCD_STM32_CONTROLLER_FLAG_TRANSFER_DONE 0x08 +#define UX_HCD_STM32_CONTROLLER_FLAG_TRANSFER_ERROR 0x10 +#define UX_HCD_STM32_CONTROLLER_LOW_SPEED_DEVICE 0x20 +#define UX_HCD_STM32_CONTROLLER_FULL_SPEED_DEVICE 0x40 +#define UX_HCD_STM32_CONTROLLER_HIGH_SPEED_DEVICE 0x80 +#define UX_HCD_STM32_MAX_PACKET_COUNT 256 + +#define UX_HCD_STM32_ED_STATUS_FREE 0x00 +#define UX_HCD_STM32_ED_STATUS_ALLOCATED 0x01 +#define UX_HCD_STM32_ED_STATUS_ABORTED 0x02 +#define UX_HCD_STM32_ED_STATUS_CONTROL_SETUP 0x03 +#define UX_HCD_STM32_ED_STATUS_CONTROL_DATA_IN 0x04 +#define UX_HCD_STM32_ED_STATUS_CONTROL_DATA_OUT 0x05 +#define UX_HCD_STM32_ED_STATUS_CONTROL_STATUS_IN 0x06 +#define UX_HCD_STM32_ED_STATUS_CONTROL_STATUS_OUT 0x07 +#define UX_HCD_STM32_ED_STATUS_BULK_IN 0x08 +#define UX_HCD_STM32_ED_STATUS_BULK_OUT 0x09 +#define UX_HCD_STM32_ED_STATUS_PERIODIC_TRANSFER 0x0A + + +/* Define STM32 static definition. */ + +#define UX_HCD_STM32_AVAILABLE_BANDWIDTH 6000 + + +/* Define STM32 structure. */ + +typedef struct UX_HCD_STM32_STRUCT +{ + + struct UX_HCD_STRUCT *ux_hcd_stm32_hcd_owner; + struct UX_HCD_STM32_ED_STRUCT *ux_hcd_stm32_ed_list; + struct UX_HCD_STM32_ED_STRUCT *ux_hcd_stm32_channels_ed[UX_HCD_STM32_MAX_NB_CHANNELS]; + ULONG ux_hcd_stm32_nb_channels; + UINT ux_hcd_stm32_queue_empty; + UINT ux_hcd_stm32_periodic_scheduler_active; + ULONG ux_hcd_stm32_controller_flag; + HCD_HandleTypeDef *hcd_handle; + struct UX_HCD_STM32_ED_STRUCT *ux_hcd_stm32_periodic_ed_head; +} UX_HCD_STM32; + + +/* Define STM32 ED structure. */ + +typedef struct UX_HCD_STM32_ED_STRUCT +{ + + struct UX_HCD_STM32_ED_STRUCT *ux_stm32_ed_next_ed; + struct UX_ENDPOINT_STRUCT *ux_stm32_ed_endpoint; + struct UX_TRANSFER_STRUCT *ux_stm32_ed_transfer_request; + UCHAR ux_stm32_ed_status; + UCHAR ux_stm32_ed_channel; + UCHAR ux_stm32_ed_interval_mask; + UCHAR ux_stm32_ed_interval_position; +} UX_HCD_STM32_ED; + + +#define USBH_PID_SETUP 0U +#define USBH_PID_DATA 1U + + +/* Define STM32 function prototypes. */ + +UINT _ux_hcd_stm32_controller_disable(UX_HCD_STM32 *hcd_stm32); +UX_HCD_STM32_ED * _ux_hcd_stm32_ed_obtain(UX_HCD_STM32 *hcd_stm32); +UINT _ux_hcd_stm32_endpoint_create(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint); +UINT _ux_hcd_stm32_endpoint_destroy(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint); +UINT _ux_hcd_stm32_endpoint_reset(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint); +UINT _ux_hcd_stm32_entry(UX_HCD *hcd, UINT function, VOID *parameter); +UINT _ux_hcd_stm32_frame_number_get(UX_HCD_STM32 *hcd_stm32, ULONG *frame_number); +UINT _ux_hcd_stm32_initialize(UX_HCD *hcd); +VOID _ux_hcd_stm32_interrupt_handler(VOID); +UINT _ux_hcd_stm32_least_traffic_list_get(UX_HCD_STM32 *hcd_stm32); +UINT _ux_hcd_stm32_periodic_schedule(UX_HCD_STM32 *hcd_stm32); +UINT _ux_hcd_stm32_port_disable(UX_HCD_STM32 *hcd_stm32, ULONG port_index); +UINT _ux_hcd_stm32_port_enable(UX_HCD_STM32 *hcd_stm32, ULONG port_index); +UINT _ux_hcd_stm32_port_reset(UX_HCD_STM32 *hcd_stm32, ULONG port_index); +UINT _ux_hcd_stm32_port_resume(UX_HCD_STM32 *hcd_stm32, UINT port_index); +ULONG _ux_hcd_stm32_port_status_get(UX_HCD_STM32 *hcd_stm32, ULONG port_index); +UINT _ux_hcd_stm32_port_suspend(UX_HCD_STM32 *hcd_stm32, ULONG port_index); +UINT _ux_hcd_stm32_power_down_port(UX_HCD_STM32 *hcd_stm32, ULONG port_index); +UINT _ux_hcd_stm32_power_on_port(UX_HCD_STM32 *hcd_stm32, ULONG port_index); +UINT _ux_hcd_stm32_request_bulk_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request); +UINT _ux_hcd_stm32_request_control_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request); +UINT _ux_hcd_stm32_request_periodic_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request); +UINT _ux_hcd_stm32_request_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request); +UINT _ux_hcd_stm32_transfer_abort(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request); + +#define ux_hcd_stm32_initialize _ux_hcd_stm32_initialize +#define ux_hcd_stm32_interrupt_handler _ux_hcd_stm32_interrupt_handler + + +#endif + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_callback.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_callback.c new file mode 100644 index 00000000..91e990c5 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_callback.c @@ -0,0 +1,383 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_HCD_Connect_Callback PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hhcd Pointer to HCD handle */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_put Put semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* stm32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd) +{ + +UX_HCD *hcd; +UX_HCD_STM32 *hcd_stm32; + + + /* Get the pointer to the HCD & HCD_STM32. */ + hcd = (UX_HCD*)hhcd -> pData; + hcd_stm32 = (UX_HCD_STM32*)hcd -> ux_hcd_controller_hardware; + + /* Something happened on the root hub port. Signal it to the root hub thread. */ + hcd -> ux_hcd_root_hub_signal[0]++; + + /* The controller has issued a ATTACH Root HUB signal. */ + hcd_stm32 -> ux_hcd_stm32_controller_flag |= UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_ATTACHED; + hcd_stm32 -> ux_hcd_stm32_controller_flag &= ~UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_DETACHED; + + /* Wake up the root hub thread. */ + _ux_utility_semaphore_put(&_ux_system_host -> ux_system_host_enum_semaphore); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_HCD_Disconnect_Callback PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hhcd Pointer to HCD handle */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_put Put semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* stm32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd) +{ + +UX_HCD *hcd; +UX_HCD_STM32 *hcd_stm32; + + + /* Get the pointer to the HCD & HCD_STM32. */ + hcd = (UX_HCD*)hhcd -> pData; + hcd_stm32 = (UX_HCD_STM32*)hcd -> ux_hcd_controller_hardware; + + /* Something happened on the root hub port. Signal it to the root hub thread. */ + hcd -> ux_hcd_root_hub_signal[0]++; + + /* The controller has issued a DETACH Root HUB signal. */ + hcd_stm32 -> ux_hcd_stm32_controller_flag |= UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_DETACHED; + hcd_stm32 -> ux_hcd_stm32_controller_flag &= ~UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_ATTACHED; + + /* Wake up the root hub thread. */ + _ux_utility_semaphore_put(&_ux_system_host -> ux_system_host_enum_semaphore); +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_HCD_Disconnect_Callback PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hhcd Pointer to HCD handle */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_put Put semaphore */ +/* HAL_HCD_HC_SubmitRequest Submit request */ +/* HAL_HCD_HC_Halt Halt channel */ +/* HAL_HCD_HC_GetXferCount Get transfer count */ +/* */ +/* CALLED BY */ +/* */ +/* stm32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state) +{ + +UX_HCD *hcd; +UX_HCD_STM32 *hcd_stm32; +UX_HCD_STM32_ED *ed; +UX_TRANSFER *transfer_request; + + + /* Check the URB state. */ + if (urb_state == URB_DONE || urb_state == URB_STALL || urb_state == URB_ERROR || urb_state == URB_NOTREADY) + { + + /* Get the pointer to the HCD & HCD_STM32. */ + hcd = (UX_HCD*)hhcd -> pData; + hcd_stm32 = (UX_HCD_STM32*)hcd -> ux_hcd_controller_hardware; + + /* Check if driver is still valid. */ + if (hcd_stm32 == UX_NULL) + return; + + /* Load the ED for the channel. */ + ed = hcd_stm32 -> ux_hcd_stm32_channels_ed[chnum]; + + /* Check if ED is still valid. */ + if (ed == UX_NULL) + { + + return; + } + + /* Get transfer request. */ + transfer_request = ed -> ux_stm32_ed_transfer_request; + + /* Check if ED is still valid. */ + if (transfer_request == UX_NULL) + { + + return; + } + + /* Check if URB state is not URB_NOTREADY. */ + if (urb_state != URB_NOTREADY) + { + + /* Handle URB states. */ + switch (urb_state) + { + case URB_STALL: + + /* Set the completion code to stalled. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_STALLED; + break; + case URB_DONE: + + /* Check the request direction. */ + if ((((ed->ux_stm32_ed_endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE) != UX_CONTROL_ENDPOINT) && + (transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN) + { + + /* Get transfer size for receiving direction. */ + transfer_request -> ux_transfer_request_actual_length = HAL_HCD_HC_GetXferCount(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel); + } + + /* Check if the request is for bulk OUT or control OUT. */ + if ((((ed -> ux_stm32_ed_endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE) == UX_BULK_ENDPOINT || + ((ed -> ux_stm32_ed_endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE) == UX_CONTROL_ENDPOINT) && + (transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_OUT) + { + + /* Update actual transfer length. */ + transfer_request -> ux_transfer_request_actual_length += transfer_request -> ux_transfer_request_packet_length; + + /* Check if there is more data to send. */ + if (transfer_request -> ux_transfer_request_requested_length > transfer_request -> ux_transfer_request_actual_length) + { + + /* Adjust the transmit length. */ + transfer_request -> ux_transfer_request_packet_length = UX_MIN(ed->ux_stm32_ed_endpoint->ux_endpoint_descriptor.wMaxPacketSize, + transfer_request -> ux_transfer_request_requested_length - transfer_request -> ux_transfer_request_actual_length); + + /* Submit the transmit request. */ + HAL_HCD_HC_SubmitRequest(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel, + 0, EP_TYPE_BULK, USBH_PID_DATA, + transfer_request->ux_transfer_request_data_pointer + transfer_request -> ux_transfer_request_actual_length, + transfer_request -> ux_transfer_request_packet_length, 0); + return; + } + } + + /* Set the completion code to SUCCESS. */ + transfer_request -> ux_transfer_request_completion_code = UX_SUCCESS; + break; + default: + /* Set the completion code to transfer error. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_ERROR; + } + + /* Move to next transfer. */ + ed -> ux_stm32_ed_transfer_request = transfer_request -> ux_transfer_request_next_transfer_request; + + /* Invoke callback function. */ + if (transfer_request -> ux_transfer_request_completion_function) + transfer_request -> ux_transfer_request_completion_function(transfer_request); + + /* Wake up the transfer request thread. */ + _ux_utility_semaphore_put(&transfer_request -> ux_transfer_request_semaphore); + + } + else + { + + /* Handle URB_NOTREADY state here. */ + /* Check if we need to retry the transfer by checking the status. */ + if ((ed -> ux_stm32_ed_status == UX_HCD_STM32_ED_STATUS_CONTROL_SETUP) || + (ed -> ux_stm32_ed_status == UX_HCD_STM32_ED_STATUS_CONTROL_DATA_OUT) || + (ed -> ux_stm32_ed_status == UX_HCD_STM32_ED_STATUS_CONTROL_STATUS_OUT) || + (ed -> ux_stm32_ed_status == UX_HCD_STM32_ED_STATUS_BULK_OUT)) + { + + /* Submit the transmit request. */ + HAL_HCD_HC_SubmitRequest(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel, 0, + ((ed -> ux_stm32_ed_endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE) == UX_BULK_ENDPOINT ? EP_TYPE_BULK : EP_TYPE_CTRL, + ed -> ux_stm32_ed_status == UX_HCD_STM32_ED_STATUS_CONTROL_SETUP ? USBH_PID_SETUP : USBH_PID_DATA, + transfer_request -> ux_transfer_request_data_pointer + transfer_request -> ux_transfer_request_actual_length, + transfer_request -> ux_transfer_request_packet_length, 0); + } + + } + } +} + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* HAL_HCD_SOF_Callback PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function handles callback from HAL driver. */ +/* */ +/* INPUT */ +/* */ +/* hhcd Pointer to HCD handle */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_semaphore_put Put semaphore */ +/* */ +/* CALLED BY */ +/* */ +/* stm32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd) +{ + +UX_HCD *hcd; +UX_HCD_STM32 *hcd_stm32; + + + /* Get the pointer to the HCD & HCD_STM32. */ + hcd = (UX_HCD*)hhcd -> pData; + hcd_stm32 = (UX_HCD_STM32*)hcd -> ux_hcd_controller_hardware; + + if ((hcd_stm32 -> ux_hcd_stm32_controller_flag & UX_HCD_STM32_CONTROLLER_FLAG_SOF) == 0) + { + hcd_stm32 -> ux_hcd_stm32_controller_flag |= UX_HCD_STM32_CONTROLLER_FLAG_SOF; + hcd -> ux_hcd_thread_signal++; + + /* Wake up the scheduler. */ + _ux_utility_semaphore_put(&_ux_system_host -> ux_system_host_hcd_semaphore); + } +} diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_controller_disable.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_controller_disable.c new file mode 100644 index 00000000..b69aa234 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_controller_disable.c @@ -0,0 +1,89 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_controller_disable PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will disable the STM32 controller. The controller */ +/* will release all its resources (memory, IO ...). After this, the */ +/* controller will not send SOF any longer. */ +/* */ +/* All transactions should have been completed, all classes should */ +/* have been closed. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_controller_disable(UX_HCD_STM32 *hcd_stm32) +{ + +UX_HCD *hcd; + + /* Point to the generic portion of the host controller structure instance. */ + hcd = hcd_stm32 -> ux_hcd_stm32_hcd_owner; + + /* Reflect the state of the controller in the main structure. */ + hcd -> ux_hcd_status = UX_HCD_STATUS_HALTED; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_ed_obtain.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_ed_obtain.c new file mode 100644 index 00000000..41142088 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_ed_obtain.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_ed_obtain PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function obtains a free ED from the ED list. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* */ +/* OUTPUT */ +/* */ +/* UX_HCD_STM32_ED * Pointer to ED */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_set Set memory block */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UX_HCD_STM32_ED *_ux_hcd_stm32_ed_obtain(UX_HCD_STM32 *hcd_stm32) +{ + +UX_HCD_STM32_ED *ed; +ULONG ed_index; + + + /* Start the search from the beginning of the list. */ + ed = hcd_stm32 -> ux_hcd_stm32_ed_list; + for (ed_index = 0; ed_index < _ux_system_host -> ux_system_host_max_ed; ed_index++) + { + + /* Check the ED status, a free ED is marked with the UNUSED flag. */ + if (ed -> ux_stm32_ed_status == UX_HCD_STM32_ED_STATUS_FREE) + { + + /* The ED may have been used, so we reset all fields. */ + _ux_utility_memory_set(ed, 0, sizeof(UX_HCD_STM32_ED)); + + /* This ED is now marked as ALLOCATED. */ + ed -> ux_stm32_ed_status = UX_HCD_STM32_ED_STATUS_ALLOCATED; + + /* Reset the channel. */ + ed -> ux_stm32_ed_channel = UX_HCD_STM32_NO_CHANNEL_ASSIGNED; + + /* Return ED pointer. */ + return(ed); + } + + /* Point to the next ED. */ + ed++; + } + + /* There is no available ED in the ED list. */ + return(UX_NULL); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_create.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_create.c new file mode 100644 index 00000000..1a74e625 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_create.c @@ -0,0 +1,218 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_endpoint_create PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will create an endpoint. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* endpoint Pointer to endpoint */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_hcd_stm32_ed_obtain Obtain STM32 ED */ +/* _ux_hcd_stm32_least_traffic_list_get Get least traffic list */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_endpoint_create(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint) +{ + +UX_HCD_STM32_ED *ed; +UX_DEVICE *device; +ULONG channel_index; +UINT device_speed; +UINT endpoint_type; + + + /* Get the pointer to the device. */ + device = endpoint -> ux_endpoint_device; + + /* Set device speed. */ + switch (device -> ux_device_speed) + { + case UX_HIGH_SPEED_DEVICE: + device_speed = HCD_DEVICE_SPEED_HIGH; + break; + case UX_FULL_SPEED_DEVICE: + device_speed = HCD_DEVICE_SPEED_FULL; + break; + case UX_LOW_SPEED_DEVICE: + device_speed = HCD_DEVICE_SPEED_LOW; + break; + default: + return(UX_ERROR); + } + + /* Set endpoint type. */ + switch ((endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE) + { + case UX_CONTROL_ENDPOINT: + endpoint_type = EP_TYPE_CTRL; + break; + case UX_BULK_ENDPOINT: + endpoint_type = EP_TYPE_BULK; + break; + case UX_INTERRUPT_ENDPOINT: + endpoint_type = EP_TYPE_INTR; + break; + case UX_ISOCHRONOUS_ENDPOINT: + endpoint_type = EP_TYPE_ISOC; + break; + default: + return(UX_FUNCTION_NOT_SUPPORTED); + } + + /* Obtain a ED for this new endpoint. This ED will live as long as the endpoint is active + and will be the container for the tds. */ + ed = _ux_hcd_stm32_ed_obtain(hcd_stm32); + if (ed == UX_NULL) + return(UX_NO_ED_AVAILABLE); + + /* And get a channel. */ + for (channel_index = 0; channel_index < hcd_stm32 -> ux_hcd_stm32_nb_channels; channel_index++) + { + + /* Check if that Channel is free. */ + if (hcd_stm32 -> ux_hcd_stm32_channels_ed[channel_index] == UX_NULL) + { + + /* We have a channel. Save it. */ + hcd_stm32 -> ux_hcd_stm32_channels_ed[channel_index] = ed; + + /* And in the endpoint too. */ + ed -> ux_stm32_ed_channel = channel_index; + + /* Done here. */ + break; + + } + } + + /* Check for channel assignment. */ + if (ed -> ux_stm32_ed_channel == UX_HCD_STM32_NO_CHANNEL_ASSIGNED) + { + + /* Free the ED. */ + ed -> ux_stm32_ed_status = UX_HCD_STM32_ED_STATUS_FREE; + + /* Could not allocate a channel. */ + return(UX_NO_ED_AVAILABLE); + } + + /* Check for interrupt and isochronous endpoints. */ + if ((endpoint_type == EP_TYPE_INTR) || (endpoint_type == EP_TYPE_ISOC)) + { + + /* Check endpoint type and device speed. */ + if (endpoint_type == EP_TYPE_ISOC || device_speed == HCD_DEVICE_SPEED_HIGH) + { + + /* Set the interval mask for high speed or isochronous endpoints. */ + ed -> ux_stm32_ed_interval_mask = (UCHAR)(1 << (endpoint -> ux_endpoint_descriptor.bInterval - 1)) - 1; + } + else + { + + /* Set the interval mask for other endpoints. */ + ed -> ux_stm32_ed_interval_mask = endpoint -> ux_endpoint_descriptor.bInterval; + ed -> ux_stm32_ed_interval_mask |= ed -> ux_stm32_ed_interval_mask >> 1; + ed -> ux_stm32_ed_interval_mask |= ed -> ux_stm32_ed_interval_mask >> 2; + ed -> ux_stm32_ed_interval_mask |= ed -> ux_stm32_ed_interval_mask >> 4; + ed -> ux_stm32_ed_interval_mask >>= 1; + } + + /* Select a transfer time slot with least traffic. */ + ed -> ux_stm32_ed_interval_position = (UCHAR)_ux_hcd_stm32_least_traffic_list_get(hcd_stm32); + + /* Attach the ed to periodic ed list. */ + ed -> ux_stm32_ed_next_ed = hcd_stm32 -> ux_hcd_stm32_periodic_ed_head; + hcd_stm32 -> ux_hcd_stm32_periodic_ed_head = ed; + + /* Activate periodic scheduler. */ + hcd_stm32 -> ux_hcd_stm32_periodic_scheduler_active ++; + } + + /* Attach the ED to the endpoint container. */ + endpoint -> ux_endpoint_ed = (VOID *) ed; + + /* Now do the opposite, attach the ED container to the physical ED. */ + ed -> ux_stm32_ed_endpoint = endpoint; + + /* Call HAL to initialize the host channel. */ + HAL_HCD_HC_Init(hcd_stm32->hcd_handle, + channel_index, + endpoint -> ux_endpoint_descriptor.bEndpointAddress, + device -> ux_device_address, + device_speed, + endpoint_type, + endpoint -> ux_endpoint_descriptor.wMaxPacketSize); + + /* Reset toggles. */ + hcd_stm32 -> hcd_handle -> hc[ed -> ux_stm32_ed_channel].toggle_in = 0; + hcd_stm32 -> hcd_handle -> hc[ed -> ux_stm32_ed_channel].toggle_out = 0; + + /* We need to take into account the nature of the HCD to define the max size + of any transfer in the transfer request. */ + endpoint -> ux_endpoint_transfer_request.ux_transfer_request_maximum_length = UX_HCD_STM32_MAX_PACKET_COUNT * + endpoint -> ux_endpoint_descriptor.wMaxPacketSize; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_destroy.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_destroy.c new file mode 100644 index 00000000..784c9c9a --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_destroy.c @@ -0,0 +1,151 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_endpoint_destroy PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will destroy an endpoint. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* endpoint Pointer to endpoint */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_virtual_address Get virtual address */ +/* _ux_utility_delay_ms Delay ms */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_endpoint_destroy(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint) +{ + +UX_HCD_STM32_ED *ed; +UX_HCD_STM32_ED *next_ed; +UINT endpoint_type; + + /* From the endpoint container fetch the STM32 ED descriptor. */ + ed = (UX_HCD_STM32_ED *) endpoint -> ux_endpoint_ed; + + /* Check if this physical endpoint has been initialized properly! */ + if (ed == UX_NULL) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_ENDPOINT_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_ENDPOINT_HANDLE_UNKNOWN, endpoint, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_ENDPOINT_HANDLE_UNKNOWN); + + } + + + /* Wait for the controller to finish the current frame processing. */ + _ux_utility_delay_ms(1); + + /* We need to free the channel. */ + hcd_stm32 -> ux_hcd_stm32_channels_ed[ed -> ux_stm32_ed_channel] = UX_NULL; + + /* Get endpoint type. */ + endpoint_type = (endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE; + + /* Check for periodic endpoints. */ + if ((endpoint_type == UX_INTERRUPT_ENDPOINT) || (endpoint_type == UX_ISOCHRONOUS_ENDPOINT)) + { + + /* Remove the ED from periodic ED list. */ + if (hcd_stm32 -> ux_hcd_stm32_periodic_ed_head == ed) + { + + /* The only one in the list, just set the pointer to null. */ + hcd_stm32 -> ux_hcd_stm32_periodic_ed_head = UX_NULL; + } + else + { + + /* Get the first ED in the list. */ + next_ed = hcd_stm32 -> ux_hcd_stm32_periodic_ed_head; + + /* Search for the ED in the list. */ + while( (next_ed != UX_NULL) && (next_ed -> ux_stm32_ed_next_ed != ed) ) + { + + /* Move to next ED. */ + next_ed = next_ed -> ux_stm32_ed_next_ed; + } + + /* Check if we found the ED. */ + if (next_ed) + { + + /* Remove the ED from list. */ + next_ed -> ux_stm32_ed_next_ed = next_ed -> ux_stm32_ed_next_ed -> ux_stm32_ed_next_ed; + } + } + + /* Decrease the periodic active count. */ + hcd_stm32 -> ux_hcd_stm32_periodic_scheduler_active --; + } + + /* Now we can safely make the ED free. */ + ed -> ux_stm32_ed_status = UX_HCD_STM32_ED_STATUS_FREE; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_reset.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_reset.c new file mode 100644 index 00000000..5635b12d --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_endpoint_reset.c @@ -0,0 +1,88 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_endpoint_reset PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will reset an endpoint. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* endpoint Pointer to endpoint */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_endpoint_reset(UX_HCD_STM32 *hcd_stm32, UX_ENDPOINT *endpoint) +{ + +UX_HCD_STM32_ED *ed; + + + /* From the endpoint container fetch the STM32 ED descriptor. */ + ed = (UX_HCD_STM32_ED *) endpoint -> ux_endpoint_ed; + + /* Reset the data0/data1 toggle bit. */ + hcd_stm32 -> hcd_handle -> hc[ed -> ux_stm32_ed_channel].toggle_in = 0; + hcd_stm32 -> hcd_handle -> hc[ed -> ux_stm32_ed_channel].toggle_out = 0; + + /* This operation never fails. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_entry.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_entry.c new file mode 100644 index 00000000..a6939521 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_entry.c @@ -0,0 +1,249 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_entry PORTABLE C */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function dispatch the HCD function internally to the STM32 */ +/* controller driver. */ +/* */ +/* INPUT */ +/* */ +/* HCD Pointer to HCD */ +/* function Function for driver to perform*/ +/* parameter Pointer to parameter(s) */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_hcd_stm32_asynchronous_endpoint_create Create async endpoint */ +/* _ux_hcd_stm32_asynchronous_endpoint_destroy Destroy async endpoint */ +/* _ux_hcd_stm32_controller_disable Disable controller */ +/* _ux_hcd_stm32_endpoint_reset Reset endpoint */ +/* _ux_hcd_stm32_frame_number_get Get frame number */ +/* _ux_hcd_stm32_interrupt_endpoint_create Create endpoint */ +/* _ux_hcd_stm32_periodic_endpoint_destroy Destroy endpoint */ +/* _ux_hcd_stm32_periodic_schedule Schedule periodic */ +/* _ux_hcd_stm32_port_enable Enable port */ +/* _ux_hcd_stm32_port_disable Disable port */ +/* _ux_hcd_stm32_port_reset Reset port */ +/* _ux_hcd_stm32_port_resume Resume port */ +/* _ux_hcd_stm32_port_status_get Get port status */ +/* _ux_hcd_stm32_port_suspend Suspend port */ +/* _ux_hcd_stm32_power_down_port Power down port */ +/* _ux_hcd_stm32_power_on_port Power on port */ +/* _ux_hcd_stm32_request_transfer Request transfer */ +/* _ux_hcd_stm32_transfer_abort Abort transfer */ +/* */ +/* CALLED BY */ +/* */ +/* Host Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* xx-xx-xxxx Chaoqiong Xiao Modified comment(s), */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_entry(UX_HCD *hcd, UINT function, VOID *parameter) +{ + +UINT status; +UX_HCD_STM32 *hcd_stm32; +UX_INT_SAVE_AREA + + + /* Check the status of the controller. */ + if (hcd -> ux_hcd_status == UX_UNUSED) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_CONTROLLER_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_CONTROLLER_UNKNOWN, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_CONTROLLER_UNKNOWN); + } + + /* Get the pointer to the STM32 HCD. */ + hcd_stm32 = (UX_HCD_STM32 *) hcd -> ux_hcd_controller_hardware; + + /* look at the function and route it. */ + switch(function) + { + + case UX_HCD_DISABLE_CONTROLLER: + + status = _ux_hcd_stm32_controller_disable(hcd_stm32); + break; + + + case UX_HCD_GET_PORT_STATUS: + + status = _ux_hcd_stm32_port_status_get(hcd_stm32, (ULONG) parameter); + break; + + + case UX_HCD_ENABLE_PORT: + + status = _ux_hcd_stm32_port_enable(hcd_stm32, (ULONG) parameter); + break; + + + case UX_HCD_DISABLE_PORT: + + status = _ux_hcd_stm32_port_disable(hcd_stm32, (ULONG) parameter); + break; + + + case UX_HCD_POWER_ON_PORT: + + status = _ux_hcd_stm32_power_on_port(hcd_stm32, (ULONG) parameter); + break; + + + case UX_HCD_POWER_DOWN_PORT: + + status = _ux_hcd_stm32_power_down_port(hcd_stm32, (ULONG) parameter); + break; + + + case UX_HCD_SUSPEND_PORT: + + status = _ux_hcd_stm32_port_suspend(hcd_stm32, (ULONG) parameter); + break; + + + case UX_HCD_RESUME_PORT: + + status = _ux_hcd_stm32_port_resume(hcd_stm32, (UINT) parameter); + break; + + + case UX_HCD_RESET_PORT: + + status = _ux_hcd_stm32_port_reset(hcd_stm32, (ULONG) parameter); + break; + + + case UX_HCD_GET_FRAME_NUMBER: + + status = _ux_hcd_stm32_frame_number_get(hcd_stm32, (ULONG *) parameter); + break; + + + case UX_HCD_TRANSFER_REQUEST: + + status = _ux_hcd_stm32_request_transfer(hcd_stm32, (UX_TRANSFER *) parameter); + break; + + + case UX_HCD_TRANSFER_ABORT: + + status = _ux_hcd_stm32_transfer_abort(hcd_stm32, (UX_TRANSFER *) parameter); + break; + + + case UX_HCD_CREATE_ENDPOINT: + + status = _ux_hcd_stm32_endpoint_create(hcd_stm32, (UX_ENDPOINT*) parameter); + break; + + case UX_HCD_DESTROY_ENDPOINT: + + status = _ux_hcd_stm32_endpoint_destroy(hcd_stm32, (UX_ENDPOINT*) parameter); + break; + + case UX_HCD_RESET_ENDPOINT: + + status = _ux_hcd_stm32_endpoint_reset(hcd_stm32, (UX_ENDPOINT*) parameter); + break; + + case UX_HCD_PROCESS_DONE_QUEUE: + + /* Process periodic queue. */ + _ux_hcd_stm32_periodic_schedule(hcd_stm32); + + /* Reset the SOF flag. */ + UX_DISABLE_INTS + hcd_stm32 -> ux_hcd_stm32_controller_flag &= ~UX_HCD_STM32_CONTROLLER_FLAG_SOF; + UX_RESTORE_INTS + + status = UX_SUCCESS; + break; + + case UX_HCD_UNINITIALIZE: + + /* free HCD resources */ + if (hcd_stm32 != UX_NULL) + { + _ux_utility_memory_free(hcd_stm32 -> ux_hcd_stm32_ed_list); + _ux_utility_memory_free(hcd_stm32); + } + + status = UX_SUCCESS; + break; + + default: + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_FUNCTION_NOT_SUPPORTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_FUNCTION_NOT_SUPPORTED, 0, 0, 0, UX_TRACE_ERRORS, 0, 0) + + /* Unknown request, return an error. */ + status = UX_FUNCTION_NOT_SUPPORTED; + break; + + } + + /* Return completion status. */ + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_frame_number_get.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_frame_number_get.c new file mode 100644 index 00000000..29ea8e11 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_frame_number_get.c @@ -0,0 +1,82 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_frame_number_get PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will return the frame number currently used by the */ +/* controller. This function is mostly used for isochronous purposes. */ +/* */ +/* Note since ThreadX delay is used, the function must not be used in */ +/* interrupts. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* frame_number Frame number to set */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_frame_number_get(UX_HCD_STM32 *hcd_stm32, ULONG *frame_number) +{ + + /* Call HAL to get the frame number. */ + *frame_number = (ULONG)HAL_HCD_GetCurrentFrame(hcd_stm32 -> hcd_handle); + + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_initialize.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_initialize.c new file mode 100644 index 00000000..0a53981c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_initialize.c @@ -0,0 +1,152 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_initialize PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function initializes the STM32 HS USB host controller. This */ +/* is not for the OTG mode. It forces the chip in Host mode only. */ +/* For OTG support, the filex in the usbx_otg subdirectory must be */ +/* used. */ +/* */ +/* INPUT */ +/* */ +/* HCD Pointer to HCD */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_memory_allocate Allocate memory block */ +/* */ +/* CALLED BY */ +/* */ +/* Host Stack */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_initialize(UX_HCD *hcd) +{ + +UX_HCD_STM32 *hcd_stm32; + + + /* The controller initialized here is of STM32 type. */ + hcd -> ux_hcd_controller_type = UX_HCD_STM32_CONTROLLER; + + /* Initialize the max bandwidth for periodic endpoints. On STM32, the spec says + no more than 90% to be allocated for periodic. */ +#if UX_MAX_DEVICES > 1 + hcd -> ux_hcd_available_bandwidth = UX_HCD_STM32_AVAILABLE_BANDWIDTH; +#endif + + /* Allocate memory for this STM32 HCD instance. */ + hcd_stm32 = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_HCD_STM32)); + if (hcd_stm32 == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* Set the pointer to the STM32 HCD. */ + hcd -> ux_hcd_controller_hardware = (VOID *) hcd_stm32; + + /* Set the generic HCD owner for the STM32 HCD. */ + hcd_stm32 -> ux_hcd_stm32_hcd_owner = hcd; + + /* Initialize the function collector for this HCD. */ + hcd -> ux_hcd_entry_function = _ux_hcd_stm32_entry; + + /* Set the state of the controller to HALTED first. */ + hcd -> ux_hcd_status = UX_HCD_STATUS_HALTED; + + /* Initialize the number of channels. */ + hcd_stm32 -> ux_hcd_stm32_nb_channels = UX_HCD_STM32_MAX_NB_CHANNELS; + + /* Check if the parameter is null. */ + if (hcd -> ux_hcd_irq == 0) + { + _ux_utility_memory_free(hcd_stm32); + return(UX_ERROR); + } + + /* Get HCD handle from parameter. */ + hcd_stm32 -> hcd_handle = (HCD_HandleTypeDef*)hcd -> ux_hcd_irq; + hcd_stm32 -> hcd_handle -> pData = hcd; + + /* Allocate the list of eds. */ + hcd_stm32 -> ux_hcd_stm32_ed_list = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, sizeof(UX_HCD_STM32_ED) *_ux_system_host -> ux_system_host_max_ed); + if (hcd_stm32 -> ux_hcd_stm32_ed_list == UX_NULL) + { + _ux_utility_memory_free(hcd_stm32); + return(UX_MEMORY_INSUFFICIENT); + } + + /* Since we know this is a high-speed controller, we can hardwire the version. */ +#if UX_MAX_DEVICES > 1 + hcd -> ux_hcd_version = 0x200; +#endif + + /* The number of ports on the controller is fixed to 1. The number of ports needs to be reflected both + for the generic HCD container and the local stm32 container. */ + hcd -> ux_hcd_nb_root_hubs = UX_HCD_STM32_NB_ROOT_PORTS; + + /* The root port must now be powered to pick up device insertion. */ + _ux_hcd_stm32_power_on_port(hcd_stm32, 0); + + /* The asynchronous queues are empty for now. */ + hcd_stm32 -> ux_hcd_stm32_queue_empty = UX_TRUE; + + /* The periodic scheduler is not active. */ + hcd_stm32 -> ux_hcd_stm32_periodic_scheduler_active = 0; + + /* Set the host controller into the operational state. */ + hcd -> ux_hcd_status = UX_HCD_STATUS_OPERATIONAL; + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_interrupt_handler.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_interrupt_handler.c new file mode 100644 index 00000000..cdc5b893 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_interrupt_handler.c @@ -0,0 +1,97 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_interrupt_handler PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the interrupt handler for the USB interrupts. */ +/* This function calls HAL driver for interrupt handling. */ +/* */ +/* INPUT */ +/* */ +/* None */ +/* */ +/* OUTPUT */ +/* */ +/* None */ +/* */ +/* CALLS */ +/* */ +/* HAL_HCD_IRQHandler Interrupt handler */ +/* */ +/* CALLED BY */ +/* */ +/* ThreadX Interrupt Handler */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +VOID _ux_hcd_stm32_interrupt_handler(VOID) +{ + +UINT hcd_index; +UX_HCD *hcd; +UX_HCD_STM32 *hcd_stm32; + + + /* We need to parse the controller driver table to find all controllers that + are registered as STM32. */ + for (hcd_index = 0; hcd_index < _ux_system_host -> ux_system_host_registered_hcd; hcd_index++) + { + + /* Check type of controller. */ + if (_ux_system_host -> ux_system_host_hcd_array[hcd_index].ux_hcd_controller_type == UX_HCD_STM32_CONTROLLER) + { + + /* Get the pointers to the generic HCD and STM32 specific areas. */ + hcd = &_ux_system_host -> ux_system_host_hcd_array[hcd_index]; + hcd_stm32 = (UX_HCD_STM32 *) hcd -> ux_hcd_controller_hardware; + + /* Call HAL interrupt handler. */ + HAL_HCD_IRQHandler(hcd_stm32 -> hcd_handle); + } + } +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_least_traffic_list_get.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_least_traffic_list_get.c new file mode 100644 index 00000000..fe3a1b9f --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_least_traffic_list_get.c @@ -0,0 +1,130 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_least_traffic_list_get PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function return a pointer to the first ED in the periodic */ +/* tree that has the least traffic registered. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* */ +/* OUTPUT */ +/* */ +/* UX_HCD_STM32_ED * Pointer to STM32 ED */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_least_traffic_list_get(UX_HCD_STM32 *hcd_stm32) +{ + +UX_HCD_STM32_ED *ed; +UINT list_index; +ULONG min_bandwidth_used; +ULONG bandwidth_used; +UINT min_bandwidth_slot; + + + /* Set the min bandwidth used to a arbitrary maximum value. */ + min_bandwidth_used = 0xffffffff; + + /* The first ED is the list candidate for now. */ + min_bandwidth_slot = 0; + + /* All list will be scanned. */ + for (list_index = 0; list_index < 32; list_index++) + { + + /* Reset the bandwidth for this list. */ + bandwidth_used = 0; + + /* Get the ED of the beginning of the list we parse now. */ + ed = hcd_stm32 -> ux_hcd_stm32_periodic_ed_head; + + /* Parse the eds in the list. */ + while (ed != UX_NULL) + { + + if ((list_index & ed -> ux_stm32_ed_interval_mask) == ed -> ux_stm32_ed_interval_position) + { + + /* Add to the bandwidth used the max packet size pointed by this ED. */ + bandwidth_used += (ULONG) ed -> ux_stm32_ed_endpoint -> ux_endpoint_descriptor.wMaxPacketSize; + } + + /* Move to next ED. */ + ed = ed -> ux_stm32_ed_next_ed; + } + + /* We have processed a list, check the bandwidth used by this list. + If this bandwidth is the minimum, we memorize the ED. */ + if (bandwidth_used < min_bandwidth_used) + { + + /* We have found a better list with a lower used bandwidth, memorize the bandwidth + for this list. */ + min_bandwidth_used = bandwidth_used; + + /* Memorize the begin ED for this list. */ + min_bandwidth_slot = list_index; + } + } + + /* Return the ED list with the lowest bandwidth. */ + return(min_bandwidth_slot); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_periodic_schedule.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_periodic_schedule.c new file mode 100644 index 00000000..859f1e1c --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_periodic_schedule.c @@ -0,0 +1,122 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_periodic_schedule PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function schedules new transfers from the periodic interrupt */ +/* list. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* */ +/* OUTPUT */ +/* */ +/* TRUE or FALSE */ +/* */ +/* CALLS */ +/* */ +/* HAL_HCD_GetCurrentFrame Get frame number */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_periodic_schedule(UX_HCD_STM32 *hcd_stm32) +{ + +UX_HCD_STM32_ED *ed; +ULONG frame_number; +ULONG ep_bmAttributes; +UX_TRANSFER *transfer_request; + + + /* Get the current frame number. */ + frame_number = HAL_HCD_GetCurrentFrame(hcd_stm32 -> hcd_handle); + + /* Get the first ED in the periodic list. */ + ed = hcd_stm32 -> ux_hcd_stm32_periodic_ed_head; + + /* Search for an entry in the periodic tree. */ + while (ed != UX_NULL) + { + + /* Check if the periodic transfer should be scheduled in this frame. */ + if ((frame_number & ed -> ux_stm32_ed_interval_mask) == ed -> ux_stm32_ed_interval_position) + { + + /* Get the transfer request. */ + transfer_request = ed -> ux_stm32_ed_transfer_request; + + /* Check if there is transfer pending. */ + if (transfer_request) + { + + /* Get Endpoint bmAttributes */ + ep_bmAttributes = ed -> ux_stm32_ed_endpoint -> ux_endpoint_descriptor.bmAttributes; + + /* Call HAL driver to submit the transfer request. */ + HAL_HCD_HC_SubmitRequest(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel, + (transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN ? 1 : 0, + (ep_bmAttributes & UX_MASK_ENDPOINT_TYPE) == UX_INTERRUPT_ENDPOINT ? EP_TYPE_INTR : EP_TYPE_ISOC, + USBH_PID_DATA, + transfer_request -> ux_transfer_request_data_pointer, + transfer_request -> ux_transfer_request_requested_length, 0); + } + } + + /* Point to the next ED in the list. */ + ed = ed -> ux_stm32_ed_next_ed; + } + + /* Return to caller. */ + return(UX_FALSE); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_disable.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_disable.c new file mode 100644 index 00000000..8d57dc78 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_disable.c @@ -0,0 +1,78 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_port_disable PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will disable a specific port attached to the root */ +/* HUB. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* port_index Port index */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_port_disable(UX_HCD_STM32 *hcd_stm32, ULONG port_index) +{ + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_enable.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_enable.c new file mode 100644 index 00000000..181dc9ac --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_enable.c @@ -0,0 +1,77 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_port_enable PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will enable a specific port attached to the root */ +/* HUB. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* port_index Port index */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_port_enable(UX_HCD_STM32 *hcd_stm32, ULONG port_index) +{ + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_reset.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_reset.c new file mode 100644 index 00000000..b67ca34f --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_reset.c @@ -0,0 +1,114 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_port_reset PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will reset a specific port attached to the root */ +/* HUB. */ +/* */ +/* Note since ThreadX delay is used, the function must not be used in */ +/* interrupts. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* port_index Port index */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_hcd_stm32_hcor_register_read Read STM32 register */ +/* _ux_hcd_stm32_hcor_register_write Write STM32 register */ +/* _ux_utility_delay_ms Delay */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_port_reset(UX_HCD_STM32 *hcd_stm32, ULONG port_index) +{ + + /* Check to see if this port is valid on this controller. On STM32, there is only one. */ + if (port_index != 0) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_PORT_INDEX_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_PORT_INDEX_UNKNOWN, port_index, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_PORT_INDEX_UNKNOWN); + } + + /* Ensure that the downstream port has a device attached. It is unnatural + to perform a port reset if there is no device. */ + if ((hcd_stm32 -> ux_hcd_stm32_controller_flag & UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_ATTACHED) == 0) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_NO_DEVICE_CONNECTED); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_NO_DEVICE_CONNECTED, port_index, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_NO_DEVICE_CONNECTED); + } + + HAL_HCD_ResetPort(hcd_stm32 -> hcd_handle); + + /* This function should never fail. */ + return(UX_SUCCESS); + +} + diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_resume.c similarity index 74% rename from src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S rename to src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_resume.c index 2b514e73..2d18964c 100644 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_restore.S +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_resume.c @@ -13,38 +13,47 @@ /**************************************************************************/ /**************************************************************************/ /** */ -/** ThreadX Component */ +/** USBX Component */ /** */ -/** Thread */ +/** STM32 Controller Driver */ /** */ /**************************************************************************/ /**************************************************************************/ - .text 32 - .align 4 - .syntax unified + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_restore Cortex-M7/GNU */ -/* 6.1.7 */ +/* _ux_hcd_stm32_port_resume PORTABLE C */ +/* 6.0 */ /* AUTHOR */ /* */ -/* Scott Larson, Microsoft Corporation */ +/* Chaoqiong Xiao, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function is responsible for restoring the previous */ -/* interrupt lockout posture. */ +/* This function will resume a specific port attached to the root */ +/* HUB. */ /* */ /* INPUT */ /* */ -/* previous_posture Previous interrupt posture */ +/* hcd_stm32 Pointer to STM32 controller */ +/* port_index Port index */ /* */ /* OUTPUT */ /* */ -/* None */ +/* Completion Status */ /* */ /* CALLS */ /* */ @@ -52,25 +61,19 @@ /* */ /* CALLED BY */ /* */ -/* Application Code */ +/* STM32 Controller Driver */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ /* */ /**************************************************************************/ -// VOID _tx_thread_interrupt_restore(UINT previous_posture) -// { - .global _tx_thread_interrupt_restore - .thumb_func -_tx_thread_interrupt_restore: - /* Restore previous interrupt lockout posture. */ -#ifdef TX_PORT_USE_BASEPRI - MSR BASEPRI, r0 -#else - MSR PRIMASK, r0 -#endif - BX lr -// } +UINT _ux_hcd_stm32_port_resume(UX_HCD_STM32 *hcd_stm32, UINT port_index) +{ + + /* Return error status. */ + return(UX_FUNCTION_NOT_SUPPORTED); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_status_get.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_status_get.c new file mode 100644 index 00000000..144a8193 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_status_get.c @@ -0,0 +1,151 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_port_status_get PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will return the status for each port attached to the */ +/* root HUB. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* port_index Port index */ +/* */ +/* OUTPUT */ +/* */ +/* STM32 Port Status */ +/* */ +/* Where port status has the following format: */ +/* */ +/* bit 0 device connection status */ +/* if 0 : no device connected */ +/* if 1 : device connected to the port */ +/* bit 1 port enable status */ +/* if 0 : port disabled */ +/* if 1 : port enabled */ +/* bit 2 port suspend status */ +/* if 0 : port is not suspended */ +/* if 1 : port is suspended */ +/* bit 3 port overcurrent status */ +/* if 0 : port has no overcurrent condition */ +/* if 1 : port has overcurrent condition */ +/* bit 4 port reset status */ +/* if 0 : port is not in reset */ +/* if 1 : port is in reset */ +/* bit 5 port power status */ +/* if 0 : port power is off */ +/* if 1 : port power is on */ +/* bit 6-7 device attached speed */ +/* if 00 : low speed device attached */ +/* if 01 : full speed device attached */ +/* if 10 : high speed device attached */ +/* */ +/* CALLS */ +/* */ +/* HAL_HCD_GetCurrentSpeed Get device speed */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +ULONG _ux_hcd_stm32_port_status_get(UX_HCD_STM32 *hcd_stm32, ULONG port_index) +{ + +ULONG port_status; + + + /* Check to see if this port is valid on this controller. */ + if (UX_HCD_STM32_NB_ROOT_PORTS < port_index) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_PORT_INDEX_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_PORT_INDEX_UNKNOWN, port_index, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_PORT_INDEX_UNKNOWN); + } + + /* The port is valid, build the status mask for this port. This function + returns a controller agnostic bit field. */ + port_status = 0; + + /* Device Connection Status. */ + if (hcd_stm32 -> ux_hcd_stm32_controller_flag & UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_ATTACHED) + port_status |= UX_PS_CCS; + + switch (HAL_HCD_GetCurrentSpeed(hcd_stm32 -> hcd_handle)) + { + case 0: + /* High Speed. */ + port_status |= UX_PS_DS_HS; + break; + + case 1: + /* Full Speed. */ + port_status |= UX_PS_DS_FS; + break; + + case 2: + /* Low Speed. */ + port_status |= UX_PS_DS_LS; + break; + + default: + /* Full Speed. */ + port_status |= UX_PS_DS_FS; + break; + } + + /* Return port status. */ + return(port_status); +} + diff --git a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_suspend.c similarity index 74% rename from src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S rename to src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_suspend.c index 91b3e4f3..6033c9d1 100644 --- a/src/Middlewares/ST/threadx/ports/cortex_m7/gnu/src/tx_thread_interrupt_disable.S +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_port_suspend.c @@ -13,38 +13,47 @@ /**************************************************************************/ /**************************************************************************/ /** */ -/** ThreadX Component */ +/** USBX Component */ /** */ -/** Thread */ +/** STM32 Controller Driver */ /** */ /**************************************************************************/ /**************************************************************************/ - .text 32 - .align 4 - .syntax unified + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + /**************************************************************************/ /* */ /* FUNCTION RELEASE */ /* */ -/* _tx_thread_interrupt_disable Cortex-M7/GNU */ -/* 6.1.7 */ +/* _ux_hcd_stm32_port_suspend PORTABLE C */ +/* 6.0 */ /* AUTHOR */ /* */ -/* Scott Larson, Microsoft Corporation */ +/* Chaoqiong Xiao, Microsoft Corporation */ /* */ /* DESCRIPTION */ /* */ -/* This function is responsible for disabling interrupts and returning */ -/* the previous interrupt lockout posture. */ +/* This function will suspend a specific port attached to the root */ +/* HUB. */ /* */ /* INPUT */ /* */ -/* None */ +/* hcd_stm32 Pointer to STM32 controller */ +/* port_index Port index */ /* */ /* OUTPUT */ /* */ -/* old_posture Old interrupt lockout posture */ +/* Completion Status */ /* */ /* CALLS */ /* */ @@ -52,28 +61,19 @@ /* */ /* CALLED BY */ /* */ -/* Application Code */ +/* STM32 Controller Driver */ /* */ /* RELEASE HISTORY */ /* */ /* DATE NAME DESCRIPTION */ /* */ -/* 06-02-2021 Scott Larson Initial Version 6.1.7 */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ /* */ /**************************************************************************/ -// UINT _tx_thread_interrupt_disable(VOID) -// { - .global _tx_thread_interrupt_disable - .thumb_func -_tx_thread_interrupt_disable: - /* Return current interrupt lockout posture. */ -#ifdef TX_PORT_USE_BASEPRI - MRS r0, BASEPRI - LDR r1, =TX_PORT_BASEPRI - MSR BASEPRI, r1 -#else - MRS r0, PRIMASK - CPSID i -#endif - BX lr -// } +UINT _ux_hcd_stm32_port_suspend(UX_HCD_STM32 *hcd_stm32, ULONG port_index) +{ + + /* Return error status. */ + return(UX_FUNCTION_NOT_SUPPORTED); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_power_down_port.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_power_down_port.c new file mode 100644 index 00000000..37322869 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_power_down_port.c @@ -0,0 +1,79 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_power_down_port PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will power down a specific port attached to the */ +/* root HUB. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* port_index Port index */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_power_down_port(UX_HCD_STM32 *hcd_stm32, ULONG port_index) +{ + + /* Return error status. */ + return(UX_FUNCTION_NOT_SUPPORTED); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_power_on_port.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_power_on_port.c new file mode 100644 index 00000000..dbfccfcf --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_power_on_port.c @@ -0,0 +1,91 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_power_on_port PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will power a specific port attached to the root HUB. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* port_index Port index */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* None */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_power_on_port(UX_HCD_STM32 *hcd_stm32, ULONG port_index) +{ + + /* Check to see if this port is valid on this controller. On STM32, there is only one. */ + if (port_index != 0) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_PORT_INDEX_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_PORT_INDEX_UNKNOWN, port_index, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_PORT_INDEX_UNKNOWN); + } + + /* This function never fails. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_bulk_transfer.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_bulk_transfer.c new file mode 100644 index 00000000..3ea81001 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_bulk_transfer.c @@ -0,0 +1,131 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_request_bulk_transfer PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a bulk transfer request. A bulk transfer */ +/* can be larger than the size of the stm32 buffer so it may be */ +/* required to chain multiple tds to accommodate this transfer */ +/* request. A bulk transfer is non blocking, so we return before the */ +/* transfer request is completed. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_hcd_stm32_regular_td_obtain Obtain regular TD */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_request_bulk_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request) +{ + +UX_ENDPOINT *endpoint; +UX_HCD_STM32_ED *ed; +UINT direction; +UINT length; + + + /* Get the pointer to the Endpoint. */ + endpoint = (UX_ENDPOINT *) transfer_request -> ux_transfer_request_endpoint; + + /* Now get the physical ED attached to this endpoint. */ + ed = endpoint -> ux_endpoint_ed; + + /* Save the pending transfer in the ED. */ + ed -> ux_stm32_ed_transfer_request = transfer_request; + + /* Direction, 0 : Output / 1 : Input */ + direction = (transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN ? 1 : 0; + + /* If the direction is OUT, request size is larger than MPS, and DMA is not used, we need to set transfer length to MPS. */ + if ((direction == 0) && (transfer_request -> ux_transfer_request_requested_length > endpoint -> ux_endpoint_descriptor.wMaxPacketSize) +#ifndef USB_DRD_FS + && (hcd_stm32 -> hcd_handle -> Init.dma_enable == 0) +#endif /* USB_DRD_FS */ + ) + { + + /* Set transfer length to MPS. */ + length = endpoint -> ux_endpoint_descriptor.wMaxPacketSize; + } + else + { + + /* Keep the original transfer length. */ + length = transfer_request -> ux_transfer_request_requested_length; + } + + /* Save the transfer status in the ED. */ + ed -> ux_stm32_ed_status = direction == 0 ? UX_HCD_STM32_ED_STATUS_BULK_OUT : UX_HCD_STM32_ED_STATUS_BULK_IN; + + /* Save the transfer length. */ + transfer_request -> ux_transfer_request_packet_length = length; + + /* Submit the transfer request. */ + HAL_HCD_HC_SubmitRequest(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel, + direction, + EP_TYPE_BULK, USBH_PID_DATA, + transfer_request->ux_transfer_request_data_pointer, + length, 0); + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_control_transfer.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_control_transfer.c new file mode 100644 index 00000000..a93fac55 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_control_transfer.c @@ -0,0 +1,356 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_request_control_transfer PORTABLE C */ +/* 6.x */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs a control transfer from a transfer request. */ +/* The USB control transfer is in 3 phases (setup, data, status). */ +/* This function will chain all phases of the control sequence before */ +/* setting the stm32 endpoint as a candidate for transfer. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_hcd_stm32_regular_td_obtain Obtain regular TD */ +/* _ux_host_stack_transfer_request_abort Abort transfer request */ +/* _ux_utility_memory_allocate Allocate memory block */ +/* _ux_utility_memory_free Release memory block */ +/* _ux_utility_semaphore_get Get semaphore */ +/* _ux_utility_short_put Write 16-bit value */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* xx-xx-xxxx Chaoqiong Xiao Modified comment(s), */ +/* prefixed UX to MS_TO_TICK, */ +/* resulting in version 6.x */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_request_control_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request) +{ + +UX_ENDPOINT *endpoint; +UCHAR *setup_request; +UX_HCD_STM32_ED *ed; +UINT status; +UINT device_speed; +UINT saved_requested_length; +UINT saved_actual_length; +UINT saved_request_type; +UCHAR * saved_request_data_pointer; + + /* Get the pointer to the Endpoint. */ + endpoint = (UX_ENDPOINT *) transfer_request -> ux_transfer_request_endpoint; + + /* Set device speed. */ + switch (endpoint -> ux_endpoint_device -> ux_device_speed) + { + case UX_HIGH_SPEED_DEVICE: + device_speed = HCD_DEVICE_SPEED_HIGH; + break; + case UX_FULL_SPEED_DEVICE: + device_speed = HCD_DEVICE_SPEED_FULL; + break; + case UX_LOW_SPEED_DEVICE: + device_speed = HCD_DEVICE_SPEED_LOW; + break; + default: + return(UX_ERROR); + } + + /* Now get the physical ED attached to this endpoint. */ + ed = endpoint -> ux_endpoint_ed; + + /* Save the pending transfer in the ED. */ + ed -> ux_stm32_ed_transfer_request = transfer_request; + + /* Build the SETUP packet (phase 1 of the control transfer). */ + setup_request = _ux_utility_memory_allocate(UX_NO_ALIGN, UX_REGULAR_MEMORY, UX_SETUP_SIZE); + if (setup_request == UX_NULL) + return(UX_MEMORY_INSUFFICIENT); + + /* Build the SETUP request. */ + *setup_request = transfer_request -> ux_transfer_request_function; + *(setup_request + UX_SETUP_REQUEST_TYPE) = transfer_request -> ux_transfer_request_type; + *(setup_request + UX_SETUP_REQUEST) = transfer_request -> ux_transfer_request_function; + _ux_utility_short_put(setup_request + UX_SETUP_VALUE, transfer_request -> ux_transfer_request_value); + _ux_utility_short_put(setup_request + UX_SETUP_INDEX, transfer_request -> ux_transfer_request_index); + _ux_utility_short_put(setup_request + UX_SETUP_LENGTH, (USHORT) transfer_request -> ux_transfer_request_requested_length); + + /* Save the original transfer parameter. */ + saved_requested_length = transfer_request -> ux_transfer_request_requested_length; + saved_request_data_pointer = transfer_request -> ux_transfer_request_data_pointer; + + /* Reset requested length for SETUP packet. */ + transfer_request -> ux_transfer_request_requested_length = 0; + + /* Set the packet length for SETUP packet. */ + transfer_request -> ux_transfer_request_packet_length = 8; + + /* Change data pointer to setup data buffer. */ + transfer_request -> ux_transfer_request_data_pointer = setup_request; + + /* Set the current status. */ + ed -> ux_stm32_ed_status = UX_HCD_STM32_ED_STATUS_CONTROL_SETUP; + + /* Initialize the host channel for SETUP phase. */ + HAL_HCD_HC_Init(hcd_stm32 -> hcd_handle, + ed -> ux_stm32_ed_channel, + 0, + endpoint -> ux_endpoint_device -> ux_device_address, + device_speed, + EP_TYPE_CTRL, + endpoint -> ux_endpoint_descriptor.wMaxPacketSize); + + /* Send the SETUP packet. */ + HAL_HCD_HC_SubmitRequest(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel, 0, EP_TYPE_CTRL, USBH_PID_SETUP, setup_request, 8, 0); + + /* Wait for the completion of the transfer request. */ + status = _ux_utility_semaphore_get(&transfer_request -> ux_transfer_request_semaphore, MS_TO_TICK(UX_CONTROL_TRANSFER_TIMEOUT)); + + /* Restore original data buffer pointer. */ + transfer_request -> ux_transfer_request_data_pointer = saved_request_data_pointer; + + /* Free the resources. */ + _ux_utility_memory_free(setup_request); + + /* If the semaphore did not succeed we probably have a time out. */ + if (status != UX_SUCCESS) + { + + /* All transfers pending need to abort. There may have been a partial transfer. */ + _ux_host_stack_transfer_request_abort(transfer_request); + + /* There was an error, return to the caller. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_TIMEOUT; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_TRANSFER_TIMEOUT, transfer_request, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_TRANSFER_TIMEOUT); + } + + /* Check the transfer request completion code. */ + if (transfer_request -> ux_transfer_request_completion_code != UX_SUCCESS) + { + + /* Return completion to caller. */ + return(transfer_request -> ux_transfer_request_completion_code); + } + + /* Check if there is data phase. */ + if (saved_requested_length) + { + + /* Check the direction of the transaction. */ + if ((transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN) + { + + /* Re-initialize the host channel to IN direction. */ + HAL_HCD_HC_Init(hcd_stm32 -> hcd_handle, + ed -> ux_stm32_ed_channel, + 0x80, + endpoint -> ux_endpoint_device -> ux_device_address, + device_speed, + EP_TYPE_CTRL, + endpoint -> ux_endpoint_descriptor.wMaxPacketSize); + + /* Set the current status to data IN. */ + ed -> ux_stm32_ed_status = UX_HCD_STM32_ED_STATUS_CONTROL_DATA_IN; + } + else + { + + /* Set the current status to data OUT. */ + ed -> ux_stm32_ed_status = UX_HCD_STM32_ED_STATUS_CONTROL_DATA_OUT; + } + + /* Save the pending transfer in the ED. */ + ed -> ux_stm32_ed_transfer_request = transfer_request; + + /* Set the transfer to pending. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_STATUS_PENDING; + + /* Restore requested length. */ + transfer_request -> ux_transfer_request_requested_length = saved_requested_length; + + /* If the direction is OUT, request size is larger than MPS, and DMA is not used, we need to set transfer length to MPS. */ + if (((transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_OUT) + && (transfer_request -> ux_transfer_request_requested_length > endpoint -> ux_endpoint_descriptor.wMaxPacketSize) +#ifndef USB_DRD_FS + && (hcd_stm32 -> hcd_handle -> Init.dma_enable == 0) +#endif /* USB_DRD_FS */ + ) + { + /* Set transfer length to MPS. */ + transfer_request -> ux_transfer_request_packet_length = endpoint -> ux_endpoint_descriptor.wMaxPacketSize; + } + else + { + + /* Keep the original transfer length. */ + transfer_request -> ux_transfer_request_packet_length = transfer_request -> ux_transfer_request_requested_length; + } + + /* Reset actual length. */ + transfer_request -> ux_transfer_request_actual_length = 0; + + /* Submit the transfer request. */ + HAL_HCD_HC_SubmitRequest(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel, + (transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN ? 1 : 0, + EP_TYPE_CTRL, USBH_PID_DATA, + transfer_request -> ux_transfer_request_data_pointer, + transfer_request -> ux_transfer_request_packet_length, 0); + + /* Wait for the completion of the transfer request. */ + status = _ux_utility_semaphore_get(&transfer_request -> ux_transfer_request_semaphore, MS_TO_TICK(UX_CONTROL_TRANSFER_TIMEOUT)); + + /* If the semaphore did not succeed we probably have a time out. */ + if (status != UX_SUCCESS) + { + + /* All transfers pending need to abort. There may have been a partial transfer. */ + _ux_host_stack_transfer_request_abort(transfer_request); + + /* There was an error, return to the caller. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_TIMEOUT; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_TRANSFER_TIMEOUT, transfer_request, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_TRANSFER_TIMEOUT); + + } + + /* Check the transfer request completion code. */ + if (transfer_request -> ux_transfer_request_completion_code != UX_SUCCESS) + { + + /* Return completion to caller. */ + return(transfer_request -> ux_transfer_request_completion_code); + } + + if ((transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN) + { + + /* Get the actual transfer length. */ + transfer_request -> ux_transfer_request_actual_length = HAL_HCD_HC_GetXferCount(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel); + } + } + + /* Setup status phase direction. */ + HAL_HCD_HC_Init(hcd_stm32 -> hcd_handle, + ed -> ux_stm32_ed_channel, + (transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN ? 0 : 0x80, + endpoint -> ux_endpoint_device -> ux_device_address, + device_speed, + EP_TYPE_CTRL, + endpoint -> ux_endpoint_descriptor.wMaxPacketSize); + + /* Save the pending transfer in the ED. */ + ed -> ux_stm32_ed_transfer_request = transfer_request; + + /* Set the transfer to pending. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_STATUS_PENDING; + + /* Save the original transfer parameter. */ + saved_requested_length = transfer_request -> ux_transfer_request_requested_length; + transfer_request -> ux_transfer_request_requested_length = 0; + saved_actual_length = transfer_request -> ux_transfer_request_actual_length; + transfer_request -> ux_transfer_request_actual_length = 0; + saved_request_type = transfer_request -> ux_transfer_request_type; + transfer_request -> ux_transfer_request_type = (transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN ? UX_REQUEST_OUT : UX_REQUEST_IN; + + /* Reset the packet length. */ + transfer_request -> ux_transfer_request_packet_length = 0; + + /* Set the current status to data OUT. */ + ed -> ux_stm32_ed_status = ((transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN) ? + UX_HCD_STM32_ED_STATUS_CONTROL_STATUS_IN : UX_HCD_STM32_ED_STATUS_CONTROL_STATUS_OUT; + + /* Submit the request for status phase. */ + HAL_HCD_HC_SubmitRequest(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel, + (transfer_request -> ux_transfer_request_type & UX_REQUEST_DIRECTION) == UX_REQUEST_IN ? 1 : 0, + EP_TYPE_CTRL, USBH_PID_DATA, 0, 0, 0); + + /* Wait for the completion of the transfer request. */ + status = _ux_utility_semaphore_get(&transfer_request -> ux_transfer_request_semaphore, UX_MS_TO_TICK(UX_CONTROL_TRANSFER_TIMEOUT)); + + /* Restore the original transfer parameter. */ + transfer_request -> ux_transfer_request_requested_length = saved_requested_length; + transfer_request -> ux_transfer_request_actual_length = saved_actual_length; + transfer_request -> ux_transfer_request_type = saved_request_type; + + /* If the semaphore did not succeed we probably have a time out. */ + if (status != UX_SUCCESS) + { + + /* All transfers pending need to abort. There may have been a partial transfer. */ + _ux_host_stack_transfer_request_abort(transfer_request); + + /* There was an error, return to the caller. */ + transfer_request -> ux_transfer_request_completion_code = UX_TRANSFER_TIMEOUT; + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_TRANSFER_TIMEOUT, transfer_request, 0, 0, UX_TRACE_ERRORS, 0, 0) + + } + + /* Return completion to caller. */ + return(transfer_request -> ux_transfer_request_completion_code); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_periodic_transfer.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_periodic_transfer.c new file mode 100644 index 00000000..2e6b48d6 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_periodic_transfer.c @@ -0,0 +1,107 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_request_periodic_transfer PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function performs an periodic transfer request. An periodic */ +/* transfer can only be as large as the MaxpacketField in the */ +/* endpoint descriptor. This was verified at the USB layer and does */ +/* not need to be reverified here. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* UX_DISABLE_INTS Disable interrupt */ +/* UX_RESTORE_INTS Restore interrupt */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_request_periodic_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request) +{ + +UX_ENDPOINT *endpoint; +UX_HCD_STM32_ED *ed; +UX_INT_SAVE_AREA + + + /* Get the pointer to the Endpoint. */ + endpoint = (UX_ENDPOINT *) transfer_request -> ux_transfer_request_endpoint; + + /* Now get the physical ED attached to this endpoint. */ + ed = endpoint -> ux_endpoint_ed; + + /* Save the transfer status in the ED. */ + ed -> ux_stm32_ed_status = UX_HCD_STM32_ED_STATUS_PERIODIC_TRANSFER; + + /* Disable interrupt. */ + UX_DISABLE_INTS + + /* Save the pending transfer in the ED. */ + ed -> ux_stm32_ed_transfer_request = transfer_request; + + /* Restore interrupt. */ + UX_RESTORE_INTS + + /* There is no need to wake up the stm32 controller on this transfer + since periodic transactions will be picked up when the interrupt + tree is scanned. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_transfer.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_transfer.c new file mode 100644 index 00000000..54e54c50 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_request_transfer.c @@ -0,0 +1,132 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_request_transfer PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function is the handler for all the transactions on the USB. */ +/* The transfer request passed as parameter contains the endpoint and */ +/* the device descriptors in addition to the type of transaction de */ +/* be executed. This function routes the transfer request to */ +/* according to the type of transfer to be executed. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to STM32 controller */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_hcd_stm32_request_bulk_transfer Request bulk transfer */ +/* _ux_hcd_stm32_request_control_transfer Request control */ +/* transfer */ +/* _ux_hcd_stm32_request_periodic_transfer Request periodic */ +/* transfer */ +/* */ +/* CALLED BY */ +/* */ +/* STM32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_request_transfer(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request) +{ + +UX_ENDPOINT *endpoint; +UINT status; + + /* Device Connection Status. */ + if (hcd_stm32 -> ux_hcd_stm32_controller_flag & UX_HCD_STM32_CONTROLLER_FLAG_DEVICE_ATTACHED) + { + + /* Get the pointer to the Endpoint. */ + endpoint = (UX_ENDPOINT *) transfer_request -> ux_transfer_request_endpoint; + + /* We reset the actual length field of the transfer request as a safety measure. */ + transfer_request -> ux_transfer_request_actual_length = 0; + + /* Isolate the endpoint type and route the transfer request. */ + switch ((endpoint -> ux_endpoint_descriptor.bmAttributes) & UX_MASK_ENDPOINT_TYPE) + { + + case UX_CONTROL_ENDPOINT: + + status = _ux_hcd_stm32_request_control_transfer(hcd_stm32, transfer_request); + break; + + + case UX_BULK_ENDPOINT: + + status = _ux_hcd_stm32_request_bulk_transfer(hcd_stm32, transfer_request); + break; + + case UX_INTERRUPT_ENDPOINT: + case UX_ISOCHRONOUS_ENDPOINT: + + status = _ux_hcd_stm32_request_periodic_transfer(hcd_stm32, transfer_request); + break; + + default: + + status = UX_ERROR; + } + } + else + { + + /* Error, no device attached. */ + status = UX_NO_DEVICE_CONNECTED; + + } + + return(status); +} + diff --git a/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_transfer_abort.c b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_transfer_abort.c new file mode 100644 index 00000000..32b7c521 --- /dev/null +++ b/src/Middlewares/ST/usbx/common/usbx_stm32_host_controllers/ux_hcd_stm32_transfer_abort.c @@ -0,0 +1,115 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** STM32 Controller Driver */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/* Include necessary system files. */ + +#define UX_SOURCE_CODE +#define UX_HCD_STM32_SOURCE_CODE + +#include "ux_api.h" +#include "ux_hcd_stm32.h" +#include "ux_host_stack.h" + + +/**************************************************************************/ +/* */ +/* FUNCTION RELEASE */ +/* */ +/* _ux_hcd_stm32_transfer_abort PORTABLE C */ +/* 6.0 */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This function will abort transactions attached to a transfer */ +/* request. */ +/* */ +/* Note since ThreadX delay is used, the function must not be used in */ +/* interrupts. */ +/* */ +/* INPUT */ +/* */ +/* hcd_stm32 Pointer to stm32 controller */ +/* transfer_request Pointer to transfer request */ +/* */ +/* OUTPUT */ +/* */ +/* Completion Status */ +/* */ +/* CALLS */ +/* */ +/* _ux_utility_delay_ms Delay */ +/* HAL_HCD_HC_Halt Halt host channel */ +/* */ +/* CALLED BY */ +/* */ +/* stm32 Controller Driver */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ +UINT _ux_hcd_stm32_transfer_abort(UX_HCD_STM32 *hcd_stm32, UX_TRANSFER *transfer_request) +{ + +UX_ENDPOINT *endpoint; +UX_HCD_STM32_ED *ed; + + + /* Get the pointer to the endpoint associated with the transfer request. */ + endpoint = (UX_ENDPOINT *) transfer_request -> ux_transfer_request_endpoint; + + /* From the endpoint container, get the address of the physical endpoint. */ + ed = (UX_HCD_STM32_ED *) endpoint -> ux_endpoint_ed; + + /* Check if this physical endpoint has been initialized properly! */ + if (ed == UX_NULL) + { + + /* Error trap. */ + _ux_system_error_handler(UX_SYSTEM_LEVEL_THREAD, UX_SYSTEM_CONTEXT_HCD, UX_ENDPOINT_HANDLE_UNKNOWN); + + /* If trace is enabled, insert this event into the trace buffer. */ + UX_TRACE_IN_LINE_INSERT(UX_TRACE_ERROR, UX_ENDPOINT_HANDLE_UNKNOWN, endpoint, 0, 0, UX_TRACE_ERRORS, 0, 0) + + return(UX_ENDPOINT_HANDLE_UNKNOWN); + } + + /* Save the transfer status in the ED. */ + ed -> ux_stm32_ed_status = UX_HCD_STM32_ED_STATUS_ABORTED; + + /* Halt the host channel. */ + HAL_HCD_HC_Halt(hcd_stm32 -> hcd_handle, ed -> ux_stm32_ed_channel); + + /* Wait for the controller to finish the current frame processing. */ + _ux_utility_delay_ms(1); + + /* Return successful completion. */ + return(UX_SUCCESS); +} + diff --git a/src/Middlewares/ST/usbx/ports/generic/inc/ux_port.h b/src/Middlewares/ST/usbx/ports/generic/inc/ux_port.h new file mode 100644 index 00000000..92ee4513 --- /dev/null +++ b/src/Middlewares/ST/usbx/ports/generic/inc/ux_port.h @@ -0,0 +1,251 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** Port Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* ux_port.h Generic */ +/* 6.1.10 */ +/* */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains data type definitions that make USBX function */ +/* identically on a variety of different processor architectures. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 12-31-2020 Chaoqiong Xiao Initial Version 6.1.3 */ +/* 01-31-2022 Chaoqiong Xiao Modified comment(s), */ +/* moved tx_api.h include and */ +/* typedefs from ux_api.h, */ +/* resulting in version 6.1.10 */ +/* */ +/**************************************************************************/ + +#ifndef UX_PORT_H +#define UX_PORT_H + + +/* Determine if the optional USBX user define file should be used. */ + +#ifdef UX_INCLUDE_USER_DEFINE_FILE + + +/* Yes, include the user defines in ux_user.h. The defines in this file may + alternately be defined on the command line. */ + +#include "ux_user.h" +#endif + + +/* Include library header files. */ + +#include +#include + + +#if !defined(UX_STANDALONE) +#include "tx_api.h" +#else + +/* VAR types used in UX, + if TX still used, expects tx_api.h included before include this. */ +#if !defined(TX_API_H) && !defined(TX_PORT_H) + +#include +typedef void VOID; +typedef char CHAR; +typedef unsigned char UCHAR; +typedef int INT; +typedef unsigned int UINT; +typedef long LONG; +typedef unsigned long ULONG; +typedef short SHORT; +typedef unsigned short USHORT; +typedef uint64_t ULONG64; + +#ifndef ALIGN_TYPE_DEFINED +#define ALIGN_TYPE ULONG +#endif + +#endif +#endif + + +/* CPU definition for X86 systems without preemptive timer function. + This will make USBX uses the controller for the timer. */ + +#undef THREADX_X86_NO_PTIMER + + +/* For X86 systems, the define #define UX_USE_IO_INSTRUCTIONS should be used. */ + + +/* Define additional generic USBX types. */ + +typedef long SLONG; + + +/* Generic USBX Project constants follow. */ + +#ifndef UX_PERIODIC_RATE +#define UX_PERIODIC_RATE 100 +#endif + +#ifndef UX_MAX_CLASS_DRIVER +#define UX_MAX_CLASS_DRIVER 2 +#endif + +#ifndef UX_MAX_SLAVE_CLASS_DRIVER +#define UX_MAX_SLAVE_CLASS_DRIVER 2 +#endif + +#ifndef UX_MAX_HCD +#define UX_MAX_HCD 1 +#endif + +#ifndef UX_MAX_DEVICES +#define UX_MAX_DEVICES 2 +#endif + +#ifndef UX_MAX_ED +#define UX_MAX_ED 80 +#endif + +#ifndef UX_MAX_TD +#define UX_MAX_TD 32 +#endif + +#ifndef UX_MAX_ISO_TD +#define UX_MAX_ISO_TD 2 +#endif + +#ifndef UX_HOST_ENUM_THREAD_STACK_SIZE +#define UX_HOST_ENUM_THREAD_STACK_SIZE (2*1024) +#endif + +#ifndef UX_THREAD_STACK_SIZE +#define UX_THREAD_STACK_SIZE (1*1024) +#endif + +#ifndef UX_THREAD_PRIORITY_ENUM +#define UX_THREAD_PRIORITY_ENUM 20 +#endif + +#ifndef UX_THREAD_PRIORITY_CLASS +#define UX_THREAD_PRIORITY_CLASS 20 +#endif + +#ifndef UX_THREAD_PRIORITY_KEYBOARD +#define UX_THREAD_PRIORITY_KEYBOARD 20 +#endif + +#ifndef UX_THREAD_PRIORITY_HCD +#define UX_THREAD_PRIORITY_HCD 2 +#endif + +#ifndef UX_THREAD_PRIORITY_DCD +#define UX_THREAD_PRIORITY_DCD 2 +#endif + +#ifndef UX_NO_TIME_SLICE +#define UX_NO_TIME_SLICE 0 +#endif + +#ifndef UX_MAX_SLAVE_LUN +#define UX_MAX_SLAVE_LUN 1 +#endif + +#ifndef UX_MAX_HOST_LUN +#define UX_MAX_HOST_LUN 1 +#endif + +#ifndef UX_HOST_CLASS_STORAGE_MAX_MEDIA +#define UX_HOST_CLASS_STORAGE_MAX_MEDIA 1 +#endif + +#ifndef UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH +#define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 +#endif + + +#ifndef UX_SLAVE_REQUEST_DATA_MAX_LENGTH +#define UX_SLAVE_REQUEST_DATA_MAX_LENGTH 2048 +#endif + +#ifndef UX_USE_IO_INSTRUCTIONS + +/* Don't use IO instructions if this define is not set. Default to memory mapped. */ + +#define inpb(a) *((UCHAR *) (a)) +#define inpw(a) *((USHORT *) (a)) +#define inpl(a) *((ULONG *) (a)) +#define outpb(a, b) *((UCHAR *) (a)) = ((UCHAR) (b)) +#define outpw(a, b) *((USHORT *) (a)) = ((USHORT) (b)) +#define outpl(a, b) *((ULONG *) (a)) = ((ULONG) (b)) +#else + + +/* Define simple prototypes for non-memory mapped hardware access. */ + +UCHAR inpb(ULONG); +USHORT inpw(ULONG); +ULONG inpl(ULONG); + +VOID outpb(ULONG,UCHAR); +VOID outpw(ULONG,USHORT); +VOID outpl(ULONG,ULONG); + +#endif +/* Define local delay function for board specific bsps. */ +#ifdef TI_AM335 + #define UX_BSP_SPECIFIC_DELAY_FUNCTION +#endif + + +/* Define interrupt lockout constructs to protect the memory allocation/release which could happen + under ISR in the device stack. */ + +#define UX_INT_SAVE_AREA unsigned int old_interrupt_posture; +#define UX_DISABLE_INTS old_interrupt_posture = tx_interrupt_control(TX_INT_DISABLE); +#define UX_RESTORE_INTS tx_interrupt_control(old_interrupt_posture); + + +/* Define the version ID of USBX. This may be utilized by the application. */ + +#ifdef UX_SYSTEM_INIT +CHAR _ux_version_id[] = + "Copyright (c) Microsoft Corporation. All rights reserved. * USBX Generic Version 6.1.10 *"; +#else +extern CHAR _ux_version_id[]; +#endif + +#endif + diff --git a/src/Middlewares/SUFST/can-defs b/src/Middlewares/SUFST/can-defs deleted file mode 160000 index 9528a405..00000000 --- a/src/Middlewares/SUFST/can-defs +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 9528a405d4c66ba1ee01a016f98143db85247724 diff --git a/src/Middlewares/SUFST/rtcan b/src/Middlewares/SUFST/rtcan deleted file mode 160000 index a23b10f3..00000000 --- a/src/Middlewares/SUFST/rtcan +++ /dev/null @@ -1 +0,0 @@ -Subproject commit a23b10f3418b170c6bb1e6ce1857af0425ae50bd diff --git a/src/STM32F746XX_FLASH.ld b/src/STM32F746XX_FLASH.ld new file mode 100644 index 00000000..ccf4b9eb --- /dev/null +++ b/src/STM32F746XX_FLASH.ld @@ -0,0 +1,207 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** Author : STM32CubeMX +** +** Abstract : Linker script for STM32F746ZGTx series +** 1024Kbytes FLASH and 320Kbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed “as is,” without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +**

© COPYRIGHT(c) 2025 STMicroelectronics

+** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** 1. Redistributions of source code must retain the above copyright notice, +** this list of conditions and the following disclaimer. +** 2. Redistributions in binary form must reproduce the above copyright notice, +** this list of conditions and the following disclaimer in the documentation +** and/or other materials provided with the distribution. +** 3. Neither the name of STMicroelectronics nor the names of its contributors +** may be used to endorse or promote products derived from this software +** without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +***************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 320K +FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 1024K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + +} + + diff --git a/src/STM32F746ZGTx_FLASH.ld b/src/STM32F746ZGTx_FLASH.ld index ab012ecb..39510152 100644 --- a/src/STM32F746ZGTx_FLASH.ld +++ b/src/STM32F746ZGTx_FLASH.ld @@ -146,9 +146,16 @@ SECTIONS } >RAM AT> FLASH - /* Uninitialized data section */ + /* Uninitialized data section + * + * Explicitly marked NOLOAD so the whole output section (including + * .dma_bss below) is emitted as SHT_NOBITS: GCC only auto-classifies + * known bss-like input section names as NOBITS-eligible, and without + * this, merging the custom-named .dma_bss section in would force the + * *entire* .bss output section to PROGBITS, storing ~270K of real zero + * bytes in the flash image instead of just reserving the space. */ . = ALIGN(4); - .bss : + .bss (NOLOAD) : { /* This is used by the startup in order to initialize the .bss secion */ _sbss = .; /* define a global symbol at bss start */ @@ -157,11 +164,23 @@ SECTIONS *(.bss*) *(COMMON) + . = ALIGN(4); + _sdma_bss = .; /* DMA-target buffers: forced after all other bss so they + always land past the 64K DTCM boundary, which DMA + masters cannot reach (see adc_scan.c) */ + *(.dma_bss) + . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; } >RAM + /* Guard the assumption above: fail the build instead of silently placing + * DMA-target buffers in DTCM (0x20000000-0x2000FFFF), which DMA masters + * cannot access, if .bss usage ever shrinks enough to pull .dma_bss back + * into that range. */ + ASSERT(_sdma_bss >= (ORIGIN(RAM) + 64K), ".dma_bss landed inside the 64K DTCM region, which DMA masters cannot access") + /* User_heap_stack section, used to check that there is enough RAM left */ ._user_heap_stack : { diff --git a/src/SUFST/Inc/Functions/compressor.h b/src/SUFST/Inc/Functions/compressor.h new file mode 100644 index 00000000..62aa2654 --- /dev/null +++ b/src/SUFST/Inc/Functions/compressor.h @@ -0,0 +1,31 @@ +/****************************************************************************** + * @file compressor.h + * @brief Audio-compressor-style soft-knee proportional (+ optional integral) + * de-ramp primitive, shared by torque_limiters.c's sub-limiters. The + * integral term leaks every call - even while gate_active is false - + * and is clamped to a configured ceiling, so it self-bounds and + * unwinds once excess drops rather than winding up indefinitely. + *****************************************************************************/ + +#ifndef COMPRESSOR_H +#define COMPRESSOR_H + +#include +#include + +#include "config.h" + +typedef struct +{ + const config_compressor_t *config_ptr; + float integral; // accumulated error, only advances once enabled +} compressor_context_t; + +void compressor_init(compressor_context_t *ctx, const config_compressor_t *config_ptr); +uint16_t compressor_apply(compressor_context_t *ctx, + uint16_t torque_request, + float measured_value, + bool gate_active); +void compressor_reset(compressor_context_t *ctx); + +#endif diff --git a/src/SUFST/Inc/Functions/mode_switch_values.h b/src/SUFST/Inc/Functions/mode_switch_values.h new file mode 100644 index 00000000..acd36508 --- /dev/null +++ b/src/SUFST/Inc/Functions/mode_switch_values.h @@ -0,0 +1,8 @@ +#include "ctrl.h" + +#ifndef MODE_SWITCH_VALUES_H +#define MODE_SWITCH_VALUES_H + +ctrl_mode_t convert_mode_adc_to_discrete(uint16_t adc_reading_0_330); + +#endif diff --git a/src/SUFST/Inc/Functions/torque_limiters.h b/src/SUFST/Inc/Functions/torque_limiters.h new file mode 100644 index 00000000..a5c85239 --- /dev/null +++ b/src/SUFST/Inc/Functions/torque_limiters.h @@ -0,0 +1,37 @@ +/****************************************************************************** + * @file torque_limiters.h + * @brief Torque de-ramp limiters applied after the torque map: a + * slip-ratio-based traction/launch control limiter, and an + * inverter DC-bus electrical power de-ramp limiter. + *****************************************************************************/ + +#ifndef TORQUE_LIMITERS_H +#define TORQUE_LIMITERS_H + +#include +#include + +#include "compressor.h" +#include "config.h" + +typedef struct +{ + const config_torque_limiters_t *config_ptr; + float min_denominator_rpm; // effective floor, >= min_motor_speed_rpm / gear_ratio + compressor_context_t slip; + compressor_context_t power; +} torque_limiters_context_t; + +void torque_limiters_init(torque_limiters_context_t *ctx, + const config_torque_limiters_t *config_ptr); + +uint16_t torque_limiters_apply(torque_limiters_context_t *ctx, + uint16_t torque_request, + bool slip_enabled, + int16_t motor_rpm, + float front_wheel_rpm, + float electrical_power_w); + +void torque_limiters_reset(torque_limiters_context_t *ctx); + +#endif diff --git a/src/SUFST/Inc/Functions/torque_map.h b/src/SUFST/Inc/Functions/torque_map.h index 0fa69483..408ce235 100644 --- a/src/SUFST/Inc/Functions/torque_map.h +++ b/src/SUFST/Inc/Functions/torque_map.h @@ -20,21 +20,18 @@ */ typedef struct _torque_map_t { - uint16_t (*map_func)(struct _torque_map_t*, uint16_t); // mapping function - uint16_t deadzone_end; // end of deadzone + uint16_t (*map_func)(struct _torque_map_t *, uint16_t); // mapping function + uint16_t deadzone_end; // end of deadzone float deadzone_scale; // scale factor for inputs - const config_torque_map_t* config_ptr; // configuration + const config_torque_map_t *config_ptr; // configuration uint16_t output_max; - uint16_t speed_min; // minimum Torque request at max speed (Nm *10) - uint16_t speed_start; // speed to start limiting torque (rpm) - uint16_t speed_end; // speed for max torque limiting (rpm) } torque_map_t; /* * public functions */ -status_t torque_map_init(torque_map_t* map_ptr, - const config_torque_map_t* config_ptr); -uint16_t torque_map_apply(torque_map_t* map_ptr, uint16_t input, int16_t speed); +status_t torque_map_init(torque_map_t *map_ptr, const config_torque_map_t *config_ptr); +uint16_t torque_map_apply(torque_map_t *map_ptr, uint16_t input); +void torque_map_set_output_max(torque_map_t *map_ptr, uint16_t output_max); #endif \ No newline at end of file diff --git a/src/SUFST/Inc/Functions/torque_map_funcs.h b/src/SUFST/Inc/Functions/torque_map_funcs.h index aa2b6f09..4f9ddbd8 100644 --- a/src/SUFST/Inc/Functions/torque_map_funcs.h +++ b/src/SUFST/Inc/Functions/torque_map_funcs.h @@ -10,6 +10,7 @@ typedef enum { TORQUE_MAP_LINEAR, + TORQUE_MAP_EXPONENTIAL, } torque_map_func_e; #endif \ No newline at end of file diff --git a/src/SUFST/Inc/Interfaces/adc_scan.h b/src/SUFST/Inc/Interfaces/adc_scan.h new file mode 100644 index 00000000..956085b2 --- /dev/null +++ b/src/SUFST/Inc/Interfaces/adc_scan.h @@ -0,0 +1,27 @@ +/*************************************************************************** + * @file adc_scan.h + * @brief Free-running scan+DMA ADC sampling, with rolling-average readout + ***************************************************************************/ + +#ifndef ADC_SCAN_H +#define ADC_SCAN_H + +#include +#include +#include + +#include "status.h" + +/* + * ADC1 and ADC2 are configured (see adc.c) to continuously scan their + * regular channel sequence into a circular DMA buffer. adc_scan_init() + * starts that free-running scan; adc_scan_get_average() reads back a + * rolling average (~1ms window) for a given channel's slot in the scan + * sequence (0-based, i.e. rank - 1). + */ + +status_t adc_scan_init(void); +uint16_t adc_scan_get_average(const ADC_HandleTypeDef *hadc, uint8_t slot); +bool adc_scan_is_ready(const ADC_HandleTypeDef *hadc); + +#endif // ADC_SCAN_H diff --git a/src/SUFST/Inc/Interfaces/apps.h b/src/SUFST/Inc/Interfaces/apps.h index 27914f65..ca93823c 100644 --- a/src/SUFST/Inc/Interfaces/apps.h +++ b/src/SUFST/Inc/Interfaces/apps.h @@ -22,14 +22,14 @@ typedef struct scs_t apps_1_signal; // SCS instance for first APPS signal scs_t apps_2_signal; // SCS instance for second APPS signal uint32_t scs_error; // SCS error code (see scs.h) - const config_apps_t* config_ptr; // configuration + const config_apps_t *config_ptr; // configuration } apps_context_t; /* * public functions */ -status_t apps_init(apps_context_t* apps_ptr, const config_apps_t* config_ptr); -status_t apps_read(apps_context_t* apps_ptr, uint16_t* reading_ptr); -bool apps_check_plausibility(apps_context_t* apps_ptr); +status_t apps_init(apps_context_t *apps_ptr, const config_apps_t *config_ptr); +status_t apps_read(apps_context_t *apps_ptr, uint16_t *reading_ptr); +bool apps_check_plausibility(apps_context_t *apps_ptr); #endif diff --git a/src/SUFST/Inc/Interfaces/bps.h b/src/SUFST/Inc/Interfaces/bps.h index 2f016fa1..53f595d7 100644 --- a/src/SUFST/Inc/Interfaces/bps.h +++ b/src/SUFST/Inc/Interfaces/bps.h @@ -22,15 +22,15 @@ typedef struct { scs_t signal; uint16_t fully_pressed_threshold; - const config_bps_t* config_ptr; + const config_bps_t *config_ptr; } bps_context_t; /* * public functions */ -status_t bps_init(bps_context_t* bps_ptr, const config_bps_t* config_ptr); -status_t bps_read(bps_context_t* bps_ptr, uint16_t* reading_ptr); -bool bps_fully_pressed(bps_context_t* bps_ptr); -bool bps_valid(bps_context_t* bps_ptr); +status_t bps_init(bps_context_t *bps_ptr, const config_bps_t *config_ptr); +status_t bps_read(bps_context_t *bps_ptr, uint16_t *reading_ptr); +bool bps_fully_pressed(bps_context_t *bps_ptr); +bool bps_valid(bps_context_t *bps_ptr); #endif \ No newline at end of file diff --git a/src/SUFST/Inc/Interfaces/io.h b/src/SUFST/Inc/Interfaces/io.h new file mode 100644 index 00000000..2e16a0fb --- /dev/null +++ b/src/SUFST/Inc/Interfaces/io.h @@ -0,0 +1,32 @@ +/*************************************************************************** + * @file io.h + * @author Robert Kirkbride (@r-kirkbride, rgak1g24@soton.ac.uk) + * @author Adam Eastman (@Agwld, ace1g24@soton.ac.uk) + * @brief I/O interface + ***************************************************************************/ + +#ifndef IO_H +#define IO_H + +#include "gpio.h" +#include +#include + +#include "status.h" + +/* Input and output functions + STAG 12 VCU (PCB revision v3.0.0 onwards) uses TXH0137D-Q1 and TPL7407L logic level inverters on + digital I/O lines. Always use the board-abstraction helpers below rather than + calling the HAL functions directly to ensure intended behavior. +*/ + +// e.g. VCU_Output_High() sets the output high, which due to the inverter will result in a low voltage on the pin. + +status_t VCU_Output_High(GPIO_TypeDef *port, uint16_t pin); +status_t VCU_Output_Low(GPIO_TypeDef *port, uint16_t pin); +status_t VCU_Output_Write(GPIO_TypeDef *port, uint16_t pin, GPIO_PinState state); +status_t VCU_Output_Toggle(GPIO_TypeDef *port, uint16_t pin); +bool VCU_Input_Read(GPIO_TypeDef *port, uint16_t pin); + + +#endif // IO_H \ No newline at end of file diff --git a/src/SUFST/Inc/Interfaces/rs232.h b/src/SUFST/Inc/Interfaces/rs232.h new file mode 100644 index 00000000..e53b4afd --- /dev/null +++ b/src/SUFST/Inc/Interfaces/rs232.h @@ -0,0 +1,16 @@ +/*************************************************************************** + * @file rtds.h + * @author Martin Perreau (@maartin0) + * @brief RS232 transciever util for the TRS3221E + ***************************************************************************/ + +#ifndef RS232_H +#define RS232_H + +#include + +void rs232_enable(void); +void rs232_disable(void); +bool rs232_is_valid(void); + +#endif diff --git a/src/SUFST/Inc/Interfaces/rtds.h b/src/SUFST/Inc/Interfaces/rtds.h index 349fb0b2..ab10e2da 100644 --- a/src/SUFST/Inc/Interfaces/rtds.h +++ b/src/SUFST/Inc/Interfaces/rtds.h @@ -7,12 +7,27 @@ #ifndef RTDS_H #define RTDS_H +#include #include #include "config.h" #include "log.h" #include "status.h" -status_t rtds_activate(const config_rtds_t* config_ptr); +status_t rtds_activate(const config_rtds_t *config_ptr); + +/** + * @brief Non-blocking RTDS pulse state + */ +typedef struct +{ + const config_rtds_t *config_ptr; // RTDS configuration + bool active; // whether the pulse is currently running + bool pin_on; // current RTDS GPIO output state + uint32_t phase_start; // tick timestamp the current on/off phase began +} rtds_pulse_context_t; + +void rtds_pulse_init(rtds_pulse_context_t *pulse_ptr, const config_rtds_t *config_ptr); +void rtds_pulse_tick(rtds_pulse_context_t *pulse_ptr, bool enable); #endif \ No newline at end of file diff --git a/src/SUFST/Inc/Interfaces/scs.h b/src/SUFST/Inc/Interfaces/scs.h index e9dba18d..acdca272 100644 --- a/src/SUFST/Inc/Interfaces/scs.h +++ b/src/SUFST/Inc/Interfaces/scs.h @@ -17,25 +17,25 @@ /* * error codes, unique to instances within the VCU */ -#define SCS_ERROR_NONE 0x00 -#define SCS_ERROR_APPS1 0x01 -#define SCS_ERROR_APPS2 0x02 +#define SCS_ERROR_NONE 0x00 +#define SCS_ERROR_APPS1 0x01 +#define SCS_ERROR_APPS2 0x02 #define SCS_ERROR_APPS_DISCREPANCY 0x04 -#define SCS_ERROR_BPS 0x08 +#define SCS_ERROR_BPS 0x08 /** * @brief Analogue system critical signal */ typedef struct { - uint16_t adc_reading; // latest raw ADC reading + uint16_t adc_reading; // latest ADC reading (~1ms rolling average) uint16_t mapped_reading; // latest mapped reading bool is_valid; // true if signal is within bounds uint32_t invalid_start_tick; // tick at which signal became invalid bool scale_up; // flag indicating scaling up float scale_factor; // cached scale factor for mapping uint32_t max_bounds_diff; // cached bounds difference for validation - const config_scs_t* config_ptr; // configuration + const config_scs_t *config_ptr; // configuration status_t status; scs_status_t status_verbose; } scs_t; @@ -43,8 +43,8 @@ typedef struct /* * function prototypes */ -status_t scs_create(scs_t* scs_ptr, const config_scs_t* config_ptr); -status_t scs_read(scs_t* scs_ptr, uint16_t* reading_ptr); -uint16_t get_adc(scs_t* scs_ptr); +status_t scs_create(scs_t *scs_ptr, const config_scs_t *config_ptr); +status_t scs_read(scs_t *scs_ptr, uint16_t *reading_ptr); +uint16_t get_adc(const scs_t *scs_ptr); #endif \ No newline at end of file diff --git a/src/SUFST/Inc/Interfaces/trc.h b/src/SUFST/Inc/Interfaces/trc.h index 86624be2..d2ca2a00 100644 --- a/src/SUFST/Inc/Interfaces/trc.h +++ b/src/SUFST/Inc/Interfaces/trc.h @@ -7,9 +7,9 @@ #ifndef TRC_H #define TRC_H -#include -#include +#include "gpio.h" #include +#include #include "status.h" diff --git a/src/SUFST/Inc/Interfaces/usb_mass_storage_mode.h b/src/SUFST/Inc/Interfaces/usb_mass_storage_mode.h new file mode 100644 index 00000000..80ccd5a5 --- /dev/null +++ b/src/SUFST/Inc/Interfaces/usb_mass_storage_mode.h @@ -0,0 +1,26 @@ +/*************************************************************************** + * @file usb_mass_storage_mode.h + * @author Martin Perreau (@maartin0) + * @brief USB mass storage passthrough mode (exposes SD card to host PC) + ***************************************************************************/ + +#ifndef USB_MASS_STORAGE_MODE_H +#define USB_MASS_STORAGE_MODE_H + +#include + +#include "config.h" +#include "status.h" +#include "tx_api.h" + +typedef struct +{ + TX_THREAD thread; + TX_BYTE_POOL *pool; +} usb_msc_context_t; + +bool usb_mass_storage_mode_button_held(void); +status_t usb_msc_init(usb_msc_context_t *ctx, TX_BYTE_POOL *pool, const config_usb_msc_t *config_ptr); +status_t enter_usb_mass_storage_mode(TX_BYTE_POOL *pool); + +#endif diff --git a/src/SUFST/Inc/Services/canbc.h b/src/SUFST/Inc/Services/canbc.h index 93a1bf3c..ff252dbd 100644 --- a/src/SUFST/Inc/Services/canbc.h +++ b/src/SUFST/Inc/Services/canbc.h @@ -8,9 +8,10 @@ #ifndef CANBC_H #define CANBC_H +#include "log.h" #include -#include #include +#include #include #include #include @@ -29,10 +30,11 @@ typedef struct { struct can_s_vcu_sensors_t sensors; + struct can_s_vcu_sensors_raw_t sensors_raw; struct can_s_vcu_temps_t temps; - struct can_s_vcu_state_t state; - struct can_s_vcu_error_t errors; - struct can_s_vcu_pdm_t pdm; + struct can_t_vcu_state_t state; + struct can_t_vcu_error_t errors; + struct can_t_vcu_pdm_t pdm; } canbc_states_t; /** @@ -42,23 +44,29 @@ typedef struct { TX_THREAD thread; // service thread TX_MUTEX state_mutex; // mutex for locking broadcast states - rtcan_handle_t* rtcan_h; // RTCAN instance to broadcast on + rtcan_handle_t *rtcan_t_h; // RTCAN instance for the tractive bus + rtcan_handle_t *rtcan_s_h; // RTCAN instance for the sensor bus canbc_states_t states; // broadcasting states uint16_t rolling_counter; // counts number of broadcasts - const config_canbc_t* config_ptr; // configuration + const config_canbc_t *config_ptr; // configuration + + uint8_t rtcan1_error; // sticky flag: CAN1 (CAN-S) transmit failure + uint8_t rtcan2_error; // sticky flag: CAN2 (CAN-T) transmit failure + uint8_t canbc_error; // sticky flag: canbc service failure (e.g. lock timeout) } canbc_context_t; /* * public functions */ -status_t canbc_init(canbc_context_t* canbc_h, - rtcan_handle_t* rtcan_h, - TX_BYTE_POOL* stack_pool_ptr, - const config_canbc_t* config_ptr); +status_t canbc_init(canbc_context_t *canbc_h, + rtcan_handle_t *rtcan_t_h, + rtcan_handle_t *rtcan_s_h, + TX_BYTE_POOL *stack_pool_ptr, + const config_canbc_t *config_ptr); -canbc_states_t* canbc_lock_state(canbc_context_t* canbc_h, uint32_t timeout); +canbc_states_t *canbc_lock_state(canbc_context_t *canbc_h, uint32_t timeout); -void canbc_unlock_state(canbc_context_t* canbc_h); +void canbc_unlock_state(canbc_context_t *canbc_h); #endif diff --git a/src/SUFST/Inc/Services/ctrl.h b/src/SUFST/Inc/Services/ctrl.h index b989c3f8..abd39db4 100644 --- a/src/SUFST/Inc/Services/ctrl.h +++ b/src/SUFST/Inc/Services/ctrl.h @@ -17,12 +17,16 @@ #include "canbc.h" #include "config.h" #include "dash.h" +#include "fans.h" #include "log.h" #include "pm100.h" +#include "remote_ctrl.h" +#include "rtds.h" #include "status.h" #include "tick.h" +#include "torque_limiters.h" #include "torque_map.h" -#include "remote_ctrl.h" +#include "wheelspeed.h" /* * error codes @@ -39,58 +43,81 @@ */ typedef enum { - CTRL_STATE_TS_BUTTON_WAIT, - CTRL_STATE_WAIT_NEG_AIR, - CTRL_STATE_PRECHARGE_WAIT, - CTRL_STATE_R2D_WAIT, - CTRL_STATE_TS_ON, - CTRL_STATE_R2D_OFF, - CTRL_STATE_R2D_OFF_WAIT, - CTRL_STATE_TS_ACTIVATION_FAILURE, - CTRL_STATE_TS_RUN_FAULT, - CTRL_STATE_SPIN, - CTRL_STATE_APPS_SCS_FAULT, - CTRL_STATE_APPS_BPS_FAULT, - CTRL_STATE_SIM_WAIT_TS_OFF, - CTRL_STATE_SIM_WAIT_TS_ON, - CTRL_STATE_SIM_WAIT_R2D_OFF, - CTRL_STATE_SIM_WAIT_R2D_ON, + CTRL_STATE_TS_BUTTON_WAIT, + CTRL_STATE_WAIT_NEG_AIR, + CTRL_STATE_PRECHARGE_WAIT, + CTRL_STATE_R2D_WAIT, + CTRL_STATE_TS_ON, + CTRL_STATE_R2D_OFF, + CTRL_STATE_R2D_OFF_WAIT, + CTRL_STATE_TS_ACTIVATION_FAILURE, + CTRL_STATE_TS_RUN_FAULT, + CTRL_STATE_SPIN, + CTRL_STATE_APPS_SCS_FAULT, + CTRL_STATE_APPS_BPS_FAULT, } ctrl_state_t; +// Note if changing these, check the line in ctrl.c starting with +// `if (ctrl_ptr->current_mode == CTRL_MODE_UNKNOWN)` +// to allow R2D in any new modes +typedef enum +{ + CTRL_MODE_UNKNOWN = 0, + CTRL_MODE_ENDURANCE = 1, + CTRL_MODE_MAX = 2, + CTRL_MODE_TORQUE_CTRL = 3, + CTRL_MODE_CRAWL = 4, + CTRL_MODE_REVERSE = 5, + CTRL_MODE_REMOTE_CTRL = 6, + CTRL_MODE_UNKNOWN_7 = 7, + CTRL_MODE_UNKNOWN_8 = 8, + CTRL_MODE_UNKNOWN_9 = 9, + CTRL_MODE_INVERTER_PROG = 10 +} ctrl_mode_t; + /** * @brief Control service context */ typedef struct { - ctrl_state_t state; // state machine state - TX_THREAD thread; // service thread - uint16_t apps_reading; // APPS reading (% * 10) - uint16_t bps_reading; // BPS reading (% * 10) - int16_t sagl_reading; // steering angle reading (deg * 10) - int16_t motor_speed_reading; // motor speed reading (rpm) - uint16_t torque_request; // last torque request - uint8_t shdn_reading; - int16_t motor_temp; - int16_t inv_temp; - int8_t max_temp; + ctrl_state_t state; // state machine state + ctrl_mode_t current_mode; // current ctrl mode + ctrl_mode_t requested_mode; // requested ctrl mode + TX_THREAD thread; // service thread + uint16_t apps_reading; // APPS reading (% * 10) + uint16_t bps_reading; // BPS reading (% * 10) + uint16_t sagl_reading; // steering angle reading (% * 40) + uint16_t current_reading; // current reading (% * 40) + int16_t motor_speed_reading; // motor speed reading (rpm) + float front_wheel_rpm; // max(FL, FR) wheel rpm, ground speed reference + float electrical_power_w; // DC-bus power reading (W) + uint16_t torque_request; // last torque request + uint8_t shdn_reading; + int16_t motor_temp; + int16_t inv_temp; + int16_t max_temp; - bool inverter_pwr; - bool pump_pwr; - bool fan_pwr; + bool inverter_pwr; + bool pump_pwr; - uint32_t neg_air_start; - uint32_t precharge_start; // precharge start time in ticks - uint32_t motor_torque_zero_start; - uint32_t apps_bps_start; - dash_context_t *dash_ptr; // dash service - pm100_context_t *pm100_ptr; // PM100 service - canbc_context_t *canbc_ptr; // CANBC service - tick_context_t *tick_ptr; // tick thread (reads certain sensors) - remote_ctrl_context_t *remote_ctrl_ptr; // tick thread (reads certain sensors) - torque_map_t torque_map; // torque map (APPS -> torque request) + uint32_t neg_air_start; + uint32_t precharge_start; // precharge start time in ticks + uint32_t motor_torque_zero_start; + uint32_t apps_bps_start; + uint32_t apps_bps_fault_start; + dash_context_t *dash_ptr; // dash service + pm100_context_t *pm100_ptr; // PM100 service + canbc_context_t *canbc_ptr; // CANBC service + fans_context_t *fans_ptr; // Fans service (reads sensor hub fan switch) + tick_context_t *tick_ptr; // tick thread (reads certain sensors) + remote_ctrl_context_t *remote_ctrl_ptr; // tick thread (reads certain sensors) + wheelspeed_context_t *wheelspeed_ptr; // wheelspeed service (front speed reference) + torque_map_t torque_map; // torque map (APPS -> torque request) + torque_limiters_context_t torque_limiters; // slip / power de-ramp limiters - const config_ctrl_t *config_ptr; // config - const config_rtds_t *rtds_config_ptr; // RTDS config + const config_ctrl_t *config_ptr; // config + const config_rtds_t *rtds_config_ptr; // RTDS config + rtds_pulse_context_t rtds_pulse_ctx; // non-blocking RTDS reverse-pulse state uint8_t error; // error code @@ -105,9 +132,12 @@ status_t ctrl_init(ctrl_context_t *ctrl_ptr, tick_context_t *tick_ptr, remote_ctrl_context_t *remote_ctrl_ptr, canbc_context_t *canbc_ptr, + fans_context_t *fans_ptr, + wheelspeed_context_t *wheelspeed_ptr, TX_BYTE_POOL *stack_pool_ptr, const config_ctrl_t *config_ptr, const config_rtds_t *rtds_config_ptr, - const config_torque_map_t *torque_map_config_ptr); + const config_torque_map_t *torque_map_config_ptr, + const config_torque_limiters_t *torque_limiters_config_ptr); #endif diff --git a/src/SUFST/Inc/Services/dash.h b/src/SUFST/Inc/Services/dash.h index f0d3d2b1..480b3382 100644 --- a/src/SUFST/Inc/Services/dash.h +++ b/src/SUFST/Inc/Services/dash.h @@ -26,7 +26,7 @@ typedef struct uint32_t active_start; // start tick of being active uint32_t required_ticks; // number of ticks for which must be active uint32_t sample_ticks; // sleep ticks between samples - GPIO_TypeDef* port; // input GPIO port + GPIO_TypeDef *port; // input GPIO port uint16_t pin; // input GPIO pin } input_context_t; @@ -36,27 +36,26 @@ typedef struct */ typedef struct { - TX_THREAD thread; // dash service thread - TX_TIMER ts_on_toggle_timer; // timer for toggling TS on LED - const config_dash_t* config_ptr; // configuration + TX_THREAD thread; // dash service thread + TX_TIMER ts_on_toggle_timer; // timer for toggling TS on LED + const config_dash_t *config_ptr; // configuration - input_context_t r2d, tson; - uint8_t r2d_flag, tson_flag; + input_context_t r2d, tson; + uint8_t r2d_flag, tson_flag; } dash_context_t; /* * public functions */ -status_t dash_init(dash_context_t* dash_ptr, - TX_BYTE_POOL* stack_pool_ptr, - const config_dash_t* config_ptr); +status_t dash_init(dash_context_t *dash_ptr, + TX_BYTE_POOL *stack_pool_ptr, + const config_dash_t *config_ptr); -status_t dash_blink_ts_on_led(dash_context_t* dash_ptr, uint32_t ticks); -status_t dash_set_ts_on_led_state(dash_context_t* dash_ptr, - GPIO_PinState state); -status_t dash_wait_for_ts_on(dash_context_t* dash_ptr); -status_t dash_wait_for_r2d(dash_context_t* dash_ptr); -status_t dash_set_r2d_led_state(dash_context_t* dash_ptr, GPIO_PinState state); +status_t dash_blink_ts_on_led(dash_context_t *dash_ptr, uint32_t ticks); +status_t dash_set_ts_on_led_state(dash_context_t *dash_ptr, GPIO_PinState state); +status_t dash_wait_for_ts_on(const dash_context_t *dash_ptr); +status_t dash_wait_for_r2d(const dash_context_t *dash_ptr); +status_t dash_set_r2d_led_state(dash_context_t *dash_ptr, GPIO_PinState state); void dash_update_buttons(dash_context_t *dash_ptr); void dash_clear_buttons(dash_context_t *dash_ptr); diff --git a/src/SUFST/Inc/Services/fans.h b/src/SUFST/Inc/Services/fans.h new file mode 100644 index 00000000..1182f4e6 --- /dev/null +++ b/src/SUFST/Inc/Services/fans.h @@ -0,0 +1,40 @@ +/*************************************************************************** + * @file fans.h + * @author Martin Perreau (@maartin0) + * @brief Fan control service + ***************************************************************************/ + +#ifndef FANS_H +#define FANS_H + +#include +#include +#include + +#include "config.h" +#include "status.h" + +#define FANS_RX_QUEUE_SIZE 3 + +typedef struct +{ + TX_THREAD thread; + TX_SEMAPHORE sample_semaphore; + TX_TIMER sample_timer; + rtcan_handle_t *rtcan_s_h; + rtcan_queue_t can_rx_queue; + uint32_t can_rx_queue_mem[RTCAN_OS_QUEUE_MEM_SIZE(FANS_RX_QUEUE_SIZE, sizeof(rtcan_msg_t *)) / sizeof(uint32_t)]; + bool fan_switch_status; // driver override switch (from CAN) + bool fan_thermal_pwr; // thermal output (motor/inverter temp) + const config_fans_t *config_ptr; +} fans_context_t; + +status_t fans_init(fans_context_t *fans_h, + rtcan_handle_t *rtcan_s_h, + TX_BYTE_POOL *stack_pool_ptr, + const config_fans_t *config_ptr); + +void fans_update_thermal(fans_context_t *fans_h, int16_t max_temp); +bool fans_output_pwr(const fans_context_t *fans_h); + +#endif diff --git a/src/SUFST/Inc/Services/heartbeat.h b/src/SUFST/Inc/Services/heartbeat.h index de6df1fa..3128fffc 100644 --- a/src/SUFST/Inc/Services/heartbeat.h +++ b/src/SUFST/Inc/Services/heartbeat.h @@ -7,6 +7,7 @@ #ifndef HEARTBEAT_H #define HEARTBEAT_H +#include #include #include "config.h" @@ -15,11 +16,14 @@ typedef struct { TX_THREAD thread; - const config_heartbeat_t* config_ptr; + const config_heartbeat_t *config_ptr; + volatile bool fast_mode; } heartbeat_context_t; -status_t heartbeat_init(heartbeat_context_t* heartbeat_h, - TX_BYTE_POOL* stack_pool_ptr, - const config_heartbeat_t* config_ptr); +status_t heartbeat_init(heartbeat_context_t *heartbeat_h, + TX_BYTE_POOL *stack_pool_ptr, + const config_heartbeat_t *config_ptr); + +void heartbeat_set_fast(void); #endif \ No newline at end of file diff --git a/src/SUFST/Inc/Services/log.h b/src/SUFST/Inc/Services/log.h index 24bed58d..17da8312 100644 --- a/src/SUFST/Inc/Services/log.h +++ b/src/SUFST/Inc/Services/log.h @@ -16,16 +16,17 @@ #include "status.h" // error codes -#define LOG_ERROR_NONE 0x00 // no error -#define LOG_ERROR_INIT 0x01 // initialisation error -#define LOG_ERROR_UART 0x02 // UART transmit error +#define LOG_ERROR_NONE 0x00 // no error +#define LOG_ERROR_INIT 0x01 // initialisation error +#define LOG_ERROR_UART 0x02 // UART transmit error #define LOG_ERROR_MUTEX 0x04 // mutex error +#define LOG_ERROR_USART 0x08 // USART transmit error // the max length for a log message #define LOG_MSG_MAX_LEN 64 // the max length for a single line of log message transmission -#define LOG_MSG_MAX_TRANSMITION_LEN 128 +#define LOG_MSG_MAX_TRANSMITION_LEN 64 typedef struct { @@ -46,20 +47,18 @@ typedef struct TX_MUTEX uart_mutex; TX_QUEUE msg_queue; ULONG msg_queue_mem[LOG_MSG_QUEUE_SIZE]; - const config_log_t* config_ptr; + const config_log_t *config_ptr; uint16_t error; } log_context_t; -status_t log_init(log_context_t* log_ptr, - TX_BYTE_POOL* stack_pool_ptr, - const config_log_t* config_ptr); +status_t log_init(log_context_t *log_ptr, TX_BYTE_POOL *stack_pool_ptr, const config_log_t *config_ptr); -status_t log_printf(const config_log_level_t level, const char* format, ...); +status_t log_printf(const config_log_level_t level, const char *format, ...); // Convenience macros #define LOG_DEBUG(...) log_printf(LOG_LEVEL_DEBUG, ##__VA_ARGS__) -#define LOG_INFO(...) log_printf(LOG_LEVEL_INFO, ##__VA_ARGS__) -#define LOG_WARN(...) log_printf(LOG_LEVEL_WARN, ##__VA_ARGS__) +#define LOG_INFO(...) log_printf(LOG_LEVEL_INFO, ##__VA_ARGS__) +#define LOG_WARN(...) log_printf(LOG_LEVEL_WARN, ##__VA_ARGS__) #define LOG_ERROR(...) log_printf(LOG_LEVEL_ERROR, ##__VA_ARGS__) #define LOG_FATAL(...) log_printf(LOG_LEVEL_FATAL, ##__VA_ARGS__) diff --git a/src/SUFST/Inc/Services/pm100.h b/src/SUFST/Inc/Services/pm100.h index 1249d0a5..99c14daa 100644 --- a/src/SUFST/Inc/Services/pm100.h +++ b/src/SUFST/Inc/Services/pm100.h @@ -12,7 +12,7 @@ #ifndef PM100_H #define PM100_H -#include +#include #include #include #include @@ -24,51 +24,57 @@ /* * error codes */ -#define PM100_ERROR_NONE 0x00 // no errors -#define PM100_ERROR_INIT 0x01 // initialisation error +#define PM100_ERROR_NONE 0x00 // no errors +#define PM100_ERROR_INIT 0x01 // initialisation error #define PM100_ERROR_BROADCAST_TIMEOUT 0x02 // no broadcasts received -#define PM100_ERROR_POST_FAULT 0x04 // power-on self-test fault -#define PM100_ERROR_RUN_FAULT 0x08 // runtime fault +#define PM100_ERROR_POST_FAULT 0x04 // power-on self-test fault +#define PM100_ERROR_RUN_FAULT 0x08 // runtime fault -#define PM100_RX_QUEUE_SIZE 10 // 10 items +#define PM100_RX_QUEUE_SIZE \ + 48 // items of headroom against bursts of the 8 subscribed frame types /** * @brief PM100 context */ typedef struct { - TX_THREAD thread; - rtcan_handle_t* rtcan_c_ptr; - rtcan_handle_t* rtcan_s_ptr; - TX_QUEUE can_rx_queue; - ULONG can_rx_queue_mem[PM100_RX_QUEUE_SIZE]; - TX_MUTEX state_mutex; - bool broadcasts_valid; - struct can_c_pm100_internal_states_t states; - struct can_c_pm100_fault_codes_t faults; - struct can_c_pm100_temperature_set_1_t temp1; - struct can_c_pm100_temperature_set_2_t temp2; - struct can_c_pm100_temperature_set_3_t temp3; - struct can_c_pm100_motor_position_info_t info; - uint16_t error; - const config_pm100_t* config_ptr; + TX_THREAD thread; + rtcan_handle_t *rtcan_t_ptr; + rtcan_handle_t *rtcan_s_ptr; + rtcan_queue_t can_rx_queue; + uint32_t can_rx_queue_mem[RTCAN_OS_QUEUE_MEM_SIZE(PM100_RX_QUEUE_SIZE, sizeof(rtcan_msg_t *)) / sizeof(uint32_t)]; + TX_MUTEX state_mutex; + bool broadcasts_valid; + struct can_t_pm100_internal_states_t states; + struct can_t_pm100_fault_codes_t faults; + struct can_t_pm100_temperature_set_1_t temp1; + struct can_t_pm100_temperature_set_2_t temp2; + struct can_t_pm100_temperature_set_3_t temp3; + struct can_t_pm100_motor_position_info_t info; + struct can_t_pm100_voltage_info_t voltage_info; + struct can_t_pm100_current_info_t current_info; + uint16_t error; + const config_pm100_t *config_ptr; + bool reverse_mode_dangerous; } pm100_context_t; /* * public functions */ -status_t pm100_init(pm100_context_t* pm100_ptr, - TX_BYTE_POOL* stack_pool_ptr, - rtcan_handle_t* rtcan_c_ptr, - rtcan_handle_t* rtcan_s_ptr, - const config_pm100_t* config_ptr); -status_t pm100_lvs_on(pm100_context_t* pm100_ptr); -status_t pm100_lvs_off(pm100_context_t* pm100_ptr); -bool pm100_is_precharged(pm100_context_t* pm100_ptr); +status_t pm100_init(pm100_context_t *pm100_ptr, + TX_BYTE_POOL *stack_pool_ptr, + rtcan_handle_t *rtcan_t_ptr, + rtcan_handle_t *rtcan_s_ptr, + const config_pm100_t *config_ptr); +status_t pm100_lvs_on(pm100_context_t *pm100_ptr); +status_t pm100_lvs_off(pm100_context_t *pm100_ptr); +bool pm100_is_precharged(pm100_context_t *pm100_ptr); int16_t pm100_motor_temp(pm100_context_t *pm100_ptr); int16_t pm100_max_inverter_temp(pm100_context_t *pm100_ptr); int16_t pm100_motor_speed(pm100_context_t *pm100_ptr); -status_t pm100_disable(pm100_context_t* pm100_ptr); -status_t pm100_request_torque(pm100_context_t* pm100_ptr, uint16_t torque); +float pm100_electrical_power_w(pm100_context_t *pm100_ptr); +status_t pm100_disable(pm100_context_t *pm100_ptr); +status_t pm100_request_torque(pm100_context_t *pm100_ptr, uint16_t torque); +void pm100_clear_error(pm100_context_t *pm100_ptr); #endif diff --git a/src/SUFST/Inc/Services/remote_ctrl.h b/src/SUFST/Inc/Services/remote_ctrl.h index 585b566c..9c7fbfe3 100644 --- a/src/SUFST/Inc/Services/remote_ctrl.h +++ b/src/SUFST/Inc/Services/remote_ctrl.h @@ -8,17 +8,16 @@ #ifndef REMOTE_CTRL_H #define REMOTE_CTRL_H -#include -#include #include +#include #include +#include +#include +#include "canbc.h" #include "config.h" #include "log.h" #include "status.h" -#include "canbc.h" -#include "bps.h" -#include "apps.h" #define REMOTE_CTRL_RX_QUEUE_SIZE 2 // 2 items (8 bytes) @@ -29,11 +28,12 @@ typedef struct const config_remote_ctrl_t *config_ptr; canbc_context_t *canbc_ptr; rtcan_handle_t *rtcan_s_ptr; - TX_QUEUE can_rx_queue; - ULONG can_rx_queue_mem[REMOTE_CTRL_RX_QUEUE_SIZE]; + rtcan_queue_t can_rx_queue; + uint32_t can_rx_queue_mem[RTCAN_OS_QUEUE_MEM_SIZE(REMOTE_CTRL_RX_QUEUE_SIZE, sizeof(rtcan_msg_t *)) / sizeof(uint32_t)]; struct can_s_vcu_simulation_t requests; - bool brakelight_pwr; + bool ts_on_prev; + bool r2d_prev; } remote_ctrl_context_t; status_t remote_ctrl_init(remote_ctrl_context_t *remote_ctrl_ptr, @@ -42,13 +42,8 @@ status_t remote_ctrl_init(remote_ctrl_context_t *remote_ctrl_ptr, rtcan_handle_t *rtcan_s_prt, const config_remote_ctrl_t *config_ptr); -status_t remote_get_bps_reading(remote_ctrl_context_t *remote_ctrl_ptr, uint16_t *result); -status_t remote_get_apps_reading(remote_ctrl_context_t *remote_ctrl_ptr, uint16_t *result); -uint8_t remote_get_r2d_reading(remote_ctrl_context_t *remote_ctrl_ptr); -uint8_t remote_get_ts_on_reading(remote_ctrl_context_t *remote_ctrl_ptr); +uint8_t remote_get_r2d_pressed(remote_ctrl_context_t *remote_ctrl_ptr); +uint8_t remote_get_ts_on_pressed(remote_ctrl_context_t *remote_ctrl_ptr); uint16_t remote_get_torque_reading(remote_ctrl_context_t *remote_ctrl_ptr); -uint16_t remote_get_power_reading(remote_ctrl_context_t *remote_ctrl_ptr); - -void remote_ctrl_update_canbc_states(remote_ctrl_context_t *remote_ctrl_ptr); #endif /* REMOTE_CTRL_H */ diff --git a/src/SUFST/Inc/Services/sd_logging.h b/src/SUFST/Inc/Services/sd_logging.h new file mode 100644 index 00000000..32c18b59 --- /dev/null +++ b/src/SUFST/Inc/Services/sd_logging.h @@ -0,0 +1,37 @@ +/*************************************************************************** + * @file sd_logging.h + * @author Martin Perreau (@maartin0) + * @brief SD card helpers + logging service + ***************************************************************************/ + +#ifndef SD_LOGGING_H +#define SD_LOGGING_H + +#include +#include + +#include "app_filex.h" +#include "log.h" + +#define SD_LOG_MSG_SIZE_ULONG \ + (LOG_MSG_MAX_TRANSMITION_LEN / sizeof(ULONG)) // 16 +#define SD_LOG_QUEUE_DEPTH 64 +#define SD_LOG_QUEUE_SIZE (SD_LOG_QUEUE_DEPTH * SD_LOG_MSG_SIZE_ULONG) // 2048 + +typedef struct +{ + TX_THREAD thread; + char log_filename[32]; + TX_QUEUE msg_queue; + ULONG msg_queue_mem[SD_LOG_QUEUE_SIZE]; + FX_MEDIA sd_media; + FX_FILE log_file; + UCHAR media_buffer[512] __attribute__((aligned(32))); + const config_sd_t *config_ptr; +} sd_context_t; + +status_t sd_init(sd_context_t *sd, TX_BYTE_POOL *stack_pool_ptr, const config_sd_t *config_ptr); + +void write_sd_log_line(const char *line); + +#endif diff --git a/src/SUFST/Inc/Services/tick.h b/src/SUFST/Inc/Services/tick.h index d1a77b0e..8436f872 100644 --- a/src/SUFST/Inc/Services/tick.h +++ b/src/SUFST/Inc/Services/tick.h @@ -8,31 +8,44 @@ #include "canbc.h" #include "config.h" #include "log.h" +#include "scs.h" #include "status.h" typedef struct { TX_THREAD thread; TX_MUTEX sensor_mutex; - const config_tick_t* config_ptr; - canbc_context_t* canbc_ptr; + const config_tick_t *config_ptr; + const config_ext_inputs_t *ext_inputs_config_ptr; + canbc_context_t *canbc_ptr; bps_context_t bps; bool brakelight_pwr; + bool bps_prev_above; + uint32_t bps_active_start; bool pump_pwr, fan_pwr; apps_context_t apps; - status_t bps_status, apps_status; - uint16_t bps_reading, apps_reading; + status_t bps_status, apps_status, sagl_status, mode_adc_status, current_status; + uint16_t bps_reading, apps_reading, sagl_reading, mode_adc_reading, current_reading; + + scs_t sagl; + scs_t current; + scs_t mode_adc; } tick_context_t; -status_t tick_init(tick_context_t* tick_ptr, - canbc_context_t* canbc_ptr, - TX_BYTE_POOL* stack_pool_ptr, - const config_tick_t* config_ptr, - const config_apps_t* apps_config_ptr, - const config_bps_t* bps_config_ptr); +status_t tick_init(tick_context_t *tick_ptr, + canbc_context_t *canbc_ptr, + TX_BYTE_POOL *stack_pool_ptr, + const config_tick_t *config_ptr, + const config_apps_t *apps_config_ptr, + const config_bps_t *bps_config_ptr, + const config_ext_inputs_t *ext_inputs_config_ptr); -status_t tick_get_bps_reading(tick_context_t* tick_ptr, uint16_t* result); -status_t tick_get_apps_reading(tick_context_t* tick_ptr, uint16_t* result); +status_t tick_get_bps_reading(tick_context_t *tick_ptr, uint16_t *result); +status_t tick_get_apps_reading(tick_context_t *tick_ptr, uint16_t *result); +status_t tick_get_sagl_reading(tick_context_t *tick_ptr, uint16_t *result); +status_t tick_get_current_reading(tick_context_t *tick_ptr, uint16_t *result); +status_t tick_get_mode_adc_reading(tick_context_t *tick_ptr, uint16_t *result); +status_t tick_clear_apps_scs_error(tick_context_t *tick_ptr); #endif /* TICK_H */ diff --git a/src/SUFST/Inc/Services/wheelspeed.h b/src/SUFST/Inc/Services/wheelspeed.h new file mode 100644 index 00000000..4d85eb30 --- /dev/null +++ b/src/SUFST/Inc/Services/wheelspeed.h @@ -0,0 +1,63 @@ +/****************************************************************************** + * @file wheelspeed.h + * @author Martin Perreau (@maartin0) + * @brief Wheelspeed interrupt reader for 4 wheels + * @details Computes wheelspeeds on the fly for 4 wheelspeed sensors, + needs to handle ~4000 interrupts/second + and broadcasts results in both RPM and m/s over CAN-S + *****************************************************************************/ + +#ifndef WHEELSPEED_H +#define WHEELSPEED_H + +#include +#include +#include + +#include "config.h" +#include "status.h" + +typedef struct +{ + volatile uint32_t isr_count; // live count updated by ISR + uint32_t prev_count; // snapshot from last sample +} wheel_state_t; + +typedef struct +{ + float fl_mps; + float fr_mps; + float rl_mps; + float rr_mps; + float fl_rpm; + float fr_rpm; + float rl_rpm; + float rr_rpm; +} wheelspeed_reading_t; + +typedef struct +{ + TX_THREAD thread; + TX_SEMAPHORE sample_semaphore; + TX_TIMER sample_timer; + TX_MUTEX reading_mutex; + rtcan_handle_t *rtcan_h; + wheel_state_t wheel_fr; + wheel_state_t wheel_fl; + wheel_state_t wheel_rr; + wheel_state_t wheel_rl; + wheelspeed_reading_t last_reading; + const config_wheelspeed_t *config_ptr; +} wheelspeed_context_t; + +status_t wheelspeed_init(wheelspeed_context_t *wheelspeed_h, + rtcan_handle_t *rtcan_h, + TX_BYTE_POOL *stack_pool_ptr, + const config_wheelspeed_t *config_ptr); + +void wheelspeed_handle_exti(wheelspeed_context_t *wheelspeed_h, uint16_t gpio_pin); + +status_t wheelspeed_get_speeds(wheelspeed_context_t *wheelspeed_h, + wheelspeed_reading_t *result); + +#endif diff --git a/src/SUFST/Inc/config.h b/src/SUFST/Inc/config.h index 64362464..715597c2 100644 --- a/src/SUFST/Inc/config.h +++ b/src/SUFST/Inc/config.h @@ -11,154 +11,162 @@ #include #include -#include -#include -#include #include +#include +#include +#include #include "torque_map_funcs.h" -// Should be defined if the VCU is in simulation mode -// When not defined(commented out) - the VCU is in normal mode(using apps and bps sensors) -// #define VCU_SIMULATION_MODE - -// Should be defined if the simulation mode is via power sent by remote control; -// When not defined(commented out) - the simulation mode is via torque sent by remote control -// Doesn't matter if VCU_SIMULATION_MODE is not defined -// #define VCU_SIMULATION_ON_POWER - /** * @brief Threads */ -typedef struct { - uint32_t priority; // thread priority - uint32_t stack_size; // stack size - const char* name; // name +typedef struct +{ + uint32_t priority; // thread priority + uint32_t stack_size; // stack size + const char *name; // name } config_thread_t; /** * @brief System critical signals */ -typedef struct { - ADC_HandleTypeDef* hadc; // ADC handle - uint16_t min_adc; // minimum expected ADC reading - uint16_t max_adc; // maximum expected ADC reading - uint16_t min_mapped; // minimum mapped reading - uint16_t max_mapped; // maximum mapped reading - float outside_bounds_fraction; // fraction of mapped range defining out of bounds signal +typedef struct +{ + ADC_HandleTypeDef *hadc; // ADC handle + uint8_t scan_slot; // 0-based index into hadc's scan sequence (rank - 1) + uint16_t min_adc; // minimum expected ADC reading + uint16_t max_adc; // maximum expected ADC reading + uint16_t min_mapped; // minimum mapped reading + uint16_t max_mapped; // maximum mapped reading + float outside_bounds_fraction; // fraction of mapped range defining out of bounds signal } config_scs_t; /** * @brief Control */ -typedef struct { - config_thread_t thread; // control thread config - uint32_t schedule_ticks; // number of ticks between runs of the control loop thread - bool r2d_requires_brake; // whether or not the brake needs to be pressed for R2D activation - uint32_t ts_ready_timeout_ticks; // ticks after which waiting for TS ready times out - uint32_t ts_ready_poll_ticks; // how often to poll input when waiting for TS ready - uint32_t precharge_timeout_ticks; // ticks after which waiting for precharge times out - uint32_t ready_wait_led_toggle_ticks; // ticks between toggling the TS on LED while waiting for 'TS ready' from relay controller - uint32_t error_led_toggle_ticks; // ticks between toggling TS on LED in activation error - uint16_t apps_bps_high_threshold; // apps reading to fault when brake also pressed - uint16_t apps_bps_low_threshold; // apps reading to recover from fault - uint16_t fan_on_threshold; // temperature at which to turn on the fan - uint16_t fan_off_threshold; // temperature at which to turn off the fan - uint16_t bps_on_threshold; // BPS reading to consider BPS 'on' +typedef struct +{ + config_thread_t thread; // control thread config + uint32_t schedule_ticks; // number of ticks between runs of the control loop thread + bool r2d_requires_brake; // whether or not the brake needs to be pressed for R2D activation + uint32_t ts_ready_timeout_ticks; // ticks after which waiting for TS ready times out + uint32_t ts_ready_poll_ticks; // how often to poll input when waiting for TS ready + uint32_t precharge_timeout_ticks; // ticks after which waiting for precharge times out + uint32_t ready_wait_led_toggle_ticks; // ticks between toggling the TS on LED while waiting for 'TS ready' from relay controller + uint32_t error_led_toggle_ticks; // ticks between toggling TS on LED in activation error + uint16_t apps_bps_high_threshold; // apps reading to fault when brake also pressed + uint16_t apps_bps_low_threshold; // apps reading to recover from fault + uint16_t apps_bps_fault_bps_threshold; // live BPS reading threshold for apps/bps plausibility fault + uint16_t bps_on_threshold; // BPS reading to consider BPS 'on' + uint16_t hard_max_torque; // Hard maximum torque value (e.g. accel) + uint16_t endurance_max_torque; // Max torque in endurance mode + uint16_t crawl_max_torque; // Max torque in crawl/reverse mode } config_ctrl_t; /** * @brief Dash */ -typedef struct { - config_thread_t thread; // dash thread config - uint32_t btn_active_ticks; // ticks for which a button must be pressed for it to be considered 'activated' - uint32_t btn_sample_ticks; // ticks between sampling buttons - bool vc_run_check; // whether or not the visual check should run - uint32_t vc_led_on_ticks; // number of ticks for which the visual check should last - bool vc_all_leds_on; // whether or not the visual check turns on all LEDs, or just the VC LEDs - uint32_t vc_stagger_ticks; // ticks between turning on each visible check LED (set to zero to turn all on at once) +typedef struct +{ + config_thread_t thread; // dash thread config + uint32_t btn_active_ticks; // ticks for which a button must be pressed for it to be considered 'activated' + uint32_t btn_sample_ticks; // ticks between sampling buttons + bool vc_run_check; // whether or not the visual check should run + uint32_t vc_led_on_ticks; // number of ticks for which the visual check should last + bool vc_all_leds_on; // whether or not the visual check turns on all LEDs, or just the VC LEDs + uint32_t vc_stagger_ticks; // ticks between turning on each visible check LED (set to zero to turn all on at once) } config_dash_t; /** * @brief APPS */ -typedef struct { - config_scs_t apps_1_scs; // SCS configuration for first APPS signal - config_scs_t apps_2_scs; // SCS configuration for second APPS signal - uint32_t max_discrepancy; // maximum discrepancy between APPS readings +typedef struct +{ + config_scs_t apps_1_scs; // SCS configuration for first APPS signal + config_scs_t apps_2_scs; // SCS configuration for second APPS signal + uint32_t max_discrepancy; // maximum discrepancy between APPS readings + bool inverted; // APPS% = 100 - calculated value } config_apps_t; /** * @brief BPS */ -typedef struct { - config_scs_t scs; // SCS configuration - float fully_pressed_fraction; // threshold above which considered 'fully pressed' +typedef struct +{ + config_scs_t scs; // SCS configuration + float fully_pressed_fraction; // threshold above which considered 'fully pressed' } config_bps_t; /** * @brief Ready to drive speaker */ -typedef struct { - uint32_t active_ticks; // ticks for which RTDS sounds - GPIO_TypeDef* port; // port for pin driving RTDS - uint16_t pin; // pin driving RTDS +typedef struct +{ + uint32_t active_ticks; // ticks for which RTDS sounds (one-shot R2D activation) + uint32_t pulse_on_ticks; // ticks RTDS is on during each reverse-mode pulse + uint32_t pulse_off_ticks; // ticks RTDS is off between reverse-mode pulses + GPIO_TypeDef *port; // port for pin driving RTDS + uint16_t pin; // pin driving RTDS } config_rtds_t; /** * @brief Torque map - * + * * @note All torque is represented as Nm * 10 */ -typedef struct { - torque_map_func_e function; // mapping function - uint16_t input_max; // maximum input value (range must be zero to max) - uint16_t output_max; // maximum output value (Nm * 10) - float deadzone_fraction; // fraction of input range for deadzone - uint16_t speed_min; // minimum Torque request at max speed (Nm *10) - uint16_t speed_start; // speed to start limiting torque (rpm) - uint16_t speed_end; // speed for max torque limiting (rpm) +typedef struct +{ + torque_map_func_e function; // mapping function + uint16_t input_max; // maximum input value (range must be zero to max) + uint16_t output_max; // maximum output value (Nm * 10) + float deadzone_fraction; // fraction of input range for deadzone + float exponent; // curve exponent for TORQUE_MAP_EXPONENTIAL (input/input_max)^exponent } config_torque_map_t; /** * @brief PM100DZ inverter */ -typedef struct { - config_thread_t thread; // service thread config - uint32_t broadcast_timeout_ticks; // maximum number of ticks to wait for a broadcast - uint32_t torque_request_timeout_ticks; - uint32_t precharge_timeout_ticks; - uint8_t speed_mode; +typedef struct +{ + config_thread_t thread; // service thread config + uint32_t broadcast_timeout_ticks; // maximum number of ticks to wait for a broadcast + uint32_t torque_request_timeout_ticks; + uint32_t precharge_timeout_ticks; + uint8_t speed_mode; } config_pm100_t; /** * @brief CAN broadcasting service */ -typedef struct { - config_thread_t thread; // CANBC thread config - uint32_t broadcast_period_ticks; // ticks between broadcasts +typedef struct +{ + config_thread_t thread; // CANBC thread config + uint32_t broadcast_period_ticks; // ticks between broadcasts } config_canbc_t; typedef struct { - config_thread_t thread; // thread config - uint32_t blink_period_ticks; // period to blink the LED + config_thread_t thread; // thread config + uint32_t blink_period_ticks; // period to blink the LED + uint32_t fast_blink_period_ticks; // period to blink in fast mode } config_heartbeat_t; typedef struct { - config_thread_t thread; - uint16_t period; + config_thread_t thread; + uint16_t period; + uint32_t bps_light_threshold; // BPS (% * 10) threshold + uint32_t bps_active_ticks; // time BPS must stay above threshold before treating as high } config_tick_t; typedef struct { - config_thread_t thread; - uint16_t period; - uint32_t broadcast_timeout_ticks; - uint16_t torque_limit; //Nm, limit torque as a precaution - uint16_t power_limit; //W, limit power as a precaution + config_thread_t thread; + uint16_t period; + uint32_t broadcast_timeout_ticks; + uint16_t torque_limit; // Nm, limit torque as a precaution + uint16_t power_limit; // W, limit power as a precaution } config_remote_ctrl_t; /** @@ -166,12 +174,12 @@ typedef struct */ typedef enum { - LOG_LEVEL_DEBUG, - LOG_LEVEL_INFO, - LOG_LEVEL_WARN, - LOG_LEVEL_ERROR, - LOG_LEVEL_FATAL, - LOG_LEVEL_NONE = 0xFF + LOG_LEVEL_DEBUG, + LOG_LEVEL_INFO, + LOG_LEVEL_WARN, + LOG_LEVEL_ERROR, + LOG_LEVEL_FATAL, + LOG_LEVEL_NONE = 0xFF } config_log_level_t; /** @@ -179,78 +187,147 @@ typedef enum */ typedef struct { - config_thread_t thread; - config_log_level_t min_level; - UART_HandleTypeDef *uart; + config_thread_t thread; + config_log_level_t min_level; + config_log_level_t min_sd_log_level; + UART_HandleTypeDef *uart; + USART_HandleTypeDef *usart; } config_log_t; typedef struct { - uint8_t rtcan_s_priority; - uint8_t rtcan_c_priority; - uint8_t ts_ctrl_thread_priority; - bool tracex_enable; - uint16_t driver_ctrl_tick_rate; + uint8_t rtcan_s_priority; + uint8_t rtcan_t_priority; + uint8_t ts_ctrl_thread_priority; + bool tracex_enable; + uint16_t driver_ctrl_tick_rate; } config_rtos_t; typedef struct { - bool run_apps_testbench; - bool run_fault_state_testbench; - uint8_t apps_testbench_laps; + bool run_apps_testbench; + bool run_fault_state_testbench; + uint8_t apps_testbench_laps; } config_testbenches; +typedef struct +{ + config_thread_t thread; + uint8_t ticks_per_wheel; + float wheel_circumference_meters; + uint32_t sample_period_ticks; +} config_wheelspeed_t; + /** - * @brief VCU configuration - * - * @details The intended usage is that the main VCU module loads an instance of - * this struct and initialises all other modules based on its state. - * Theoretically all the individual modules could load the config, - * but that makes them less portable / decoupled. + * @brief Audio-compressor-style soft-knee PI controller (deramp + gentle integral gain) */ -typedef struct { - config_dash_t dash; - config_apps_t apps; - config_bps_t bps; - config_ctrl_t ctrl; - config_rtds_t rtds; - config_torque_map_t torque_map; - config_pm100_t pm100; - config_tick_t tick; - config_remote_ctrl_t remote_ctrl; - config_canbc_t canbc; - config_heartbeat_t heartbeat; - config_log_t log; - config_rtos_t rtos; - config_testbenches testbenches; -} config_t; +typedef struct +{ + float threshold; // knee - measured value below this is untouched + float p_gain; // proportional de-ramp strength above threshold + float i_gain; // integral gain (unused without integral_enabled) + float integral_decay; // per-tick multiplicative leak, 0..1 (100Hz loop tick, no explicit dt) + float integral_max; // hard ceiling on accumulated integral, Nm*10 units (same as derate/torque_request) + bool integral_enabled; // explicit on/off switch, rather than zeroing i_gain +} config_compressor_t; -/* - * public functions +/** + * @brief Torque limiters applied after the torque map: slip-ratio-based + * traction/launch control, and inverter DC-bus electrical power + * de-ramp */ -const config_t* config_get(); - +typedef struct +{ + float gear_ratio; // motor : wheel reduction ratio (e.g. 120 motor rpm -> 37.7 wheel rpm) + float min_motor_speed_rpm; // motor rpm floor below which slip limiting holds off entirely + float min_denominator_rpm; // baseline min wheel rpm for the slip-ratio denominator / front-speed + // reliability gate; raised at init to >= min_motor_speed_rpm / + // gear_ratio so slip control can never engage before front wheel + // speed is itself reliably measurable (see torque_limiters_init) + config_compressor_t slip; // slip de-ramp tuning (threshold is in slip %, unaffected by units) + config_compressor_t power; // power de-ramp tuning (threshold in Watts, DC-bus) +} config_torque_limiters_t; +typedef struct +{ + config_thread_t thread; + bool enable; + uint32_t flush_period_ticks; +} config_sd_t; +typedef struct +{ + config_thread_t thread; +} config_usb_msc_t; +typedef struct +{ + config_scs_t sagl; // ADC configuration for the steering angle signal + config_scs_t mode_switch; // ADC configuration for the dash mode selector switch + config_scs_t current; // ADC configuration for the current sensor +} config_ext_inputs_t; +typedef struct +{ + config_thread_t thread; + uint32_t broadcast_timeout_ticks; // maximum number of ticks to wait for a broadcast + bool enable; + bool inverted; + uint16_t fan_on_threshold; // temperature at which to turn on the fan + uint16_t fan_off_threshold; // temperature at which to turn off the fan +} config_fans_t; +/** + * @brief VCU configuration + * + * @details The intended usage is that the main VCU module loads an instance of + * this struct and initialises all other modules based on its state. + * Theoretically all the individual modules could load the config, + * but that makes them less portable / decoupled. + */ +typedef struct +{ + config_dash_t dash; + config_apps_t apps; + config_bps_t bps; + config_ctrl_t ctrl; + config_rtds_t rtds; + config_torque_map_t torque_map; + config_pm100_t pm100; + config_tick_t tick; + config_remote_ctrl_t remote_ctrl; + config_canbc_t canbc; + config_heartbeat_t heartbeat; + config_log_t log; + config_rtos_t rtos; + config_testbenches testbenches; + config_wheelspeed_t wheelspeed; + config_torque_limiters_t torque_limiters; + config_sd_t sd; + config_usb_msc_t usb_msc; + config_ext_inputs_t ext_inputs; + config_fans_t fans; +} config_t; +/* + * public functions + */ +const config_t *config_get(); /*************************************************************************** - * + * * NOTE: MIGRATION OF OLD CONFIG SYSTEM BELOW IN PROGRESS! - * + * ***************************************************************************/ /*************************************************************************** * RTOS // ***************************************************************************/ -// #define RTCAN_S_PRIORITY 3 -// #define RTCAN_C_PRIORITY 2 // critical systems more important than sensors -// #define TS_CTRL_THREAD_PRIORITY 2 +// #define RTCAN_S_PRIORITY 3 +// #define RTCAN_T_PRIORITY 2 // critical systems more +// important than sensors #define TS_CTRL_THREAD_PRIORITY 2 // #define TRACEX_ENABLE 0 // // enable TraceX logging @@ -261,7 +338,7 @@ const config_t* config_get(); * CAN / inverter ***************************************************************************/ -#define SELECTED_DRIVER_PROFILE DRIVER_PROFILE_DEFAULT +#define SELECTED_DRIVER_PROFILE DRIVER_PROFILE_DEFAULT // #define INVERTER_SPEED_MODE 0 // replace torque requests with speed requests // #define INVERTER_TORQUE_REQUEST_TIMEOUT 100 // in ms diff --git a/src/SUFST/Inc/tx_user.h b/src/SUFST/Inc/tx_user.h new file mode 100644 index 00000000..387c8f3a --- /dev/null +++ b/src/SUFST/Inc/tx_user.h @@ -0,0 +1,10 @@ +/* Wrapper for Core/Inc/tx_user.h. + * + * FileX defines TX_DISABLE_ERROR_CHECKING internally (in each of its source + * files) which conflicts with TX_SAFETY_CRITICAL. Clearing it here ensures + * tx_api.h's safety-critical check passes. #include resolves to the real + * tx_user.h in Core/Inc without recursion. + */ + +#include "../../Core/Inc/tx_user.h" +#undef TX_DISABLE_ERROR_CHECKING diff --git a/src/SUFST/Inc/vcu.h b/src/SUFST/Inc/vcu.h index 75ada435..ad8654a4 100644 --- a/src/SUFST/Inc/vcu.h +++ b/src/SUFST/Inc/vcu.h @@ -13,16 +13,22 @@ #include #include +#include "apps.h" +#include "bps.h" #include "canbc.h" #include "config.h" #include "ctrl.h" #include "dash.h" +#include "fans.h" #include "heartbeat.h" #include "log.h" #include "pm100.h" -#include "tick.h" -#include "status.h" #include "remote_ctrl.h" +#include "sd_logging.h" +#include "status.h" +#include "tick.h" +#include "usb_mass_storage_mode.h" +#include "wheelspeed.h" /** * @brief VCU context @@ -31,18 +37,22 @@ */ typedef struct { - rtcan_handle_t rtcan_s; // RTCAN service for sensors CAN bus - rtcan_handle_t rtcan_c; // RTCAN service for critical systems CAN bus - canbc_context_t canbc; // CAN broadcasting service instance - dash_context_t dash; // dash service - ctrl_context_t ctrl; // control service - pm100_context_t pm100; // PM100 service - tick_context_t tick; - remote_ctrl_context_t remote_ctrl; - heartbeat_context_t heartbeat; // heartbeat service - log_context_t log; // logging service - uint32_t err; // current error code - const config_t* config_ptr; // pointer to global VCU configuration + rtcan_handle_t rtcan_s; // RTCAN service for sensors CAN bus + rtcan_handle_t rtcan_t; // RTCAN service for critical systems CAN bus + canbc_context_t canbc; // CAN broadcasting service instance + dash_context_t dash; // dash service + ctrl_context_t ctrl; // control service + pm100_context_t pm100; // PM100 service + fans_context_t fans; + tick_context_t tick; + remote_ctrl_context_t remote_ctrl; + heartbeat_context_t heartbeat; // heartbeat service + wheelspeed_context_t wheelspeed; // wheelspeed service + log_context_t log; // logging service + sd_context_t sd; // sd card service + usb_msc_context_t usb_msc; // USB mass storage service + uint32_t err; // current error code + const config_t *config_ptr; // pointer to global VCU configuration } vcu_context_t; @@ -50,19 +60,18 @@ typedef struct * public functions */ -status_t vcu_init(vcu_context_t* vcu_ptr, - CAN_HandleTypeDef* can_c_h, - CAN_HandleTypeDef* can_s_h, - TX_BYTE_POOL* app_mem_pool, - const config_t* config_ptr); +status_t vcu_init(vcu_context_t *vcu_ptr, + CAN_HandleTypeDef *can_t_h, + CAN_HandleTypeDef *can_s_h, + TX_BYTE_POOL *app_mem_pool, + const config_t *config_ptr); + +status_t vcu_handle_can_tx_mailbox_callback(vcu_context_t *vcu_ptr, CAN_HandleTypeDef *can_h); -status_t vcu_handle_can_tx_mailbox_callback(vcu_context_t* vcu_ptr, - CAN_HandleTypeDef* can_h); +status_t vcu_handle_can_rx_it(vcu_context_t *vcu_ptr, CAN_HandleTypeDef *can_h, uint32_t rx_fifo); -status_t vcu_handle_can_rx_it(vcu_context_t* vcu_ptr, - CAN_HandleTypeDef* can_h, - uint32_t rx_fifo); +status_t vcu_handle_can_err(vcu_context_t *vcu_ptr, CAN_HandleTypeDef *can_h); -status_t vcu_handle_can_err(vcu_context_t* vcu_ptr, CAN_HandleTypeDef* can_h); +void vcu_handle_gpio_exti(vcu_context_t *vcu_ptr, uint16_t gpio_pin); #endif diff --git a/src/SUFST/Middlewares/can-defs b/src/SUFST/Middlewares/can-defs new file mode 160000 index 00000000..9994183a --- /dev/null +++ b/src/SUFST/Middlewares/can-defs @@ -0,0 +1 @@ +Subproject commit 9994183a33aa4e6c01b762e7169969c74aa94d83 diff --git a/src/SUFST/Middlewares/rtcan b/src/SUFST/Middlewares/rtcan new file mode 160000 index 00000000..7b987d83 --- /dev/null +++ b/src/SUFST/Middlewares/rtcan @@ -0,0 +1 @@ +Subproject commit 7b987d8344febfdc778d612a19f3d074476e9533 diff --git a/src/SUFST/Src/Functions/compressor.c b/src/SUFST/Src/Functions/compressor.c new file mode 100644 index 00000000..ad765789 --- /dev/null +++ b/src/SUFST/Src/Functions/compressor.c @@ -0,0 +1,49 @@ +#include "compressor.h" + +void compressor_init(compressor_context_t *ctx, const config_compressor_t *config_ptr) +{ + ctx->config_ptr = config_ptr; + ctx->integral = 0.0f; +} + +uint16_t compressor_apply(compressor_context_t *ctx, uint16_t torque_request, float measured_value, bool gate_active) +{ + const config_compressor_t *cfg = ctx->config_ptr; + float excess = gate_active ? (measured_value - cfg->threshold) : 0.0f; + + float derate = (excess > 0.0f) ? excess * cfg->p_gain : 0.0f; + + if (cfg->integral_enabled) + { + ctx->integral *= cfg->integral_decay; + + if (excess > 0.0f) + { + ctx->integral += excess * cfg->i_gain; + } + + if (ctx->integral > cfg->integral_max) + { + ctx->integral = cfg->integral_max; + } + else if (ctx->integral < 0.0f) + { + ctx->integral = 0.0f; + } + + derate += ctx->integral; + } + + if (!gate_active || derate <= 0.0f) + { + return torque_request; + } + + float limited = (float)torque_request - derate; + return (limited > 0.0f) ? (uint16_t)limited : 0; +} + +void compressor_reset(compressor_context_t *ctx) +{ + ctx->integral = 0.0f; +} diff --git a/src/SUFST/Src/Functions/mode_switch_values.c b/src/SUFST/Src/Functions/mode_switch_values.c new file mode 100644 index 00000000..301ae0f8 --- /dev/null +++ b/src/SUFST/Src/Functions/mode_switch_values.c @@ -0,0 +1,25 @@ +#include "mode_switch_values.h" + +ctrl_mode_t convert_mode_adc_to_discrete(uint16_t adc_reading_0_330) +{ + // LOG_INFO("MODE ADC %d\n", adc_reading_0_330); + if (adc_reading_0_330 < 19) + return 1; + if (adc_reading_0_330 < 56) + return 2; + if (adc_reading_0_330 < 93) + return 3; + if (adc_reading_0_330 < 130) + return 4; + if (adc_reading_0_330 < 168) + return 5; + if (adc_reading_0_330 < 206) + return 6; + if (adc_reading_0_330 < 243) + return 7; + if (adc_reading_0_330 < 281) + return 8; + if (adc_reading_0_330 < 315) + return 9; + return 10; +} diff --git a/src/SUFST/Src/Functions/torque_limiters.c b/src/SUFST/Src/Functions/torque_limiters.c new file mode 100644 index 00000000..f0bdc626 --- /dev/null +++ b/src/SUFST/Src/Functions/torque_limiters.c @@ -0,0 +1,45 @@ +#include + +#include "torque_limiters.h" + +void torque_limiters_init(torque_limiters_context_t *ctx, + const config_torque_limiters_t *config_ptr) +{ + ctx->config_ptr = config_ptr; + ctx->min_denominator_rpm = + fmaxf(config_ptr->min_denominator_rpm, + config_ptr->min_motor_speed_rpm / config_ptr->gear_ratio); + compressor_init(&ctx->slip, &config_ptr->slip); + compressor_init(&ctx->power, &config_ptr->power); +} + +uint16_t torque_limiters_apply(torque_limiters_context_t *ctx, + uint16_t torque_request, + bool slip_enabled, + int16_t motor_rpm, + float front_wheel_rpm, + float electrical_power_w) +{ + bool front_reliable = front_wheel_rpm >= ctx->min_denominator_rpm; + bool slip_active = slip_enabled && + motor_rpm >= ctx->config_ptr->min_motor_speed_rpm && front_reliable; + + float rear_wheel_rpm = (float)motor_rpm / ctx->config_ptr->gear_ratio; + + float front_rpm_safe = front_reliable ? front_wheel_rpm : ctx->min_denominator_rpm; + + float slip_percent = (rear_wheel_rpm - front_rpm_safe) / front_rpm_safe * 100.0f; + + torque_request = compressor_apply(&ctx->slip, torque_request, slip_percent, slip_active); + + torque_request = + compressor_apply(&ctx->power, torque_request, electrical_power_w, true); + + return torque_request; +} + +void torque_limiters_reset(torque_limiters_context_t *ctx) +{ + compressor_reset(&ctx->slip); + compressor_reset(&ctx->power); +} diff --git a/src/SUFST/Src/Functions/torque_map.c b/src/SUFST/Src/Functions/torque_map.c index bc9e5e13..ea93b96f 100644 --- a/src/SUFST/Src/Functions/torque_map.c +++ b/src/SUFST/Src/Functions/torque_map.c @@ -1,13 +1,14 @@ #include "torque_map.h" +#include + /* * internal function prototypes */ -static inline uint16_t apply_deadzone(torque_map_t* map_ptr, uint16_t input); -static uint16_t null_torque_map(torque_map_t* map_ptr, uint16_t input); -static uint16_t linear_torque_map(torque_map_t* map_ptr, uint16_t input); -static inline uint16_t -apply_speed_limit(torque_map_t* map_ptr, uint16_t input, int16_t speed); +static inline uint16_t apply_deadzone(const torque_map_t *map_ptr, uint16_t input); +static uint16_t null_torque_map(torque_map_t *map_ptr, uint16_t input); +static uint16_t linear_torque_map(torque_map_t *map_ptr, uint16_t input); +static uint16_t exponential_torque_map(torque_map_t *map_ptr, uint16_t input); /** * @brief Initialises the torque map @@ -18,18 +19,15 @@ apply_speed_limit(torque_map_t* map_ptr, uint16_t input, int16_t speed); * @param[in] map_ptr Torque map * @param[in] config_ptr Configuration */ -status_t torque_map_init(torque_map_t* map_ptr, - const config_torque_map_t* config_ptr) +status_t torque_map_init(torque_map_t *map_ptr, const config_torque_map_t *config_ptr) { map_ptr->config_ptr = config_ptr; // pre-compute deadzone parameters - map_ptr->deadzone_end - = config_ptr->deadzone_fraction * config_ptr->input_max; + map_ptr->deadzone_end = config_ptr->deadzone_fraction * config_ptr->input_max; - map_ptr->deadzone_scale - = ((float) config_ptr->input_max) - / ((float) (config_ptr->input_max - map_ptr->deadzone_end)); + map_ptr->deadzone_scale = ((float)config_ptr->input_max) / + ((float)(config_ptr->input_max - map_ptr->deadzone_end)); // load mapping function status_t status = STATUS_OK; @@ -42,15 +40,19 @@ status_t torque_map_init(torque_map_t* map_ptr, break; } + case TORQUE_MAP_EXPONENTIAL: + { + map_ptr->map_func = exponential_torque_map; + break; + } + default: map_ptr->map_func = null_torque_map; status = STATUS_ERROR; break; }; - map_ptr->speed_min = config_ptr->speed_min; - map_ptr->speed_start = config_ptr->speed_start; - map_ptr->speed_end = config_ptr->speed_end; + map_ptr->output_max = config_ptr->output_max; return status; } @@ -61,12 +63,21 @@ status_t torque_map_init(torque_map_t* map_ptr, * @param[in] map_ptr Torque map * @param[in] input Input value */ -uint16_t torque_map_apply(torque_map_t* map_ptr, uint16_t input, int16_t speed) +uint16_t torque_map_apply(torque_map_t *map_ptr, uint16_t input) { const uint16_t input_deadzone = apply_deadzone(map_ptr, input); - const uint16_t torque = map_ptr->map_func(map_ptr, input_deadzone); - const uint16_t limited_torque = apply_speed_limit(map_ptr, torque, speed); - return limited_torque; + return map_ptr->map_func(map_ptr, input_deadzone); +} + +/** + * @brief Sets the torque ceiling for the active drive mode + * + * @param[in] map_ptr Torque map + * @param[in] output_max Torque ceiling for this mode (Nm * 10) + */ +void torque_map_set_output_max(torque_map_t *map_ptr, uint16_t output_max) +{ + map_ptr->output_max = output_max; } /** @@ -76,7 +87,7 @@ uint16_t torque_map_apply(torque_map_t* map_ptr, uint16_t input, int16_t speed) * @param[in] map_ptr Torque map * @param[in] input Input value */ -uint16_t apply_deadzone(torque_map_t* map_ptr, uint16_t input) +uint16_t apply_deadzone(const torque_map_t *map_ptr, uint16_t input) { uint16_t result = 0; @@ -87,7 +98,7 @@ uint16_t apply_deadzone(torque_map_t* map_ptr, uint16_t input) else { const uint16_t shifted_input = input - map_ptr->deadzone_end; - result = (uint16_t) (shifted_input * map_ptr->deadzone_scale); + result = (uint16_t)(shifted_input * map_ptr->deadzone_scale); } return result; @@ -96,7 +107,7 @@ uint16_t apply_deadzone(torque_map_t* map_ptr, uint16_t input) /** * @brief A torque map that returns zero */ -uint16_t null_torque_map(torque_map_t* map_ptr, uint16_t input) +uint16_t null_torque_map(torque_map_t *map_ptr, uint16_t input) { UNUSED(map_ptr); UNUSED(input); @@ -106,53 +117,27 @@ uint16_t null_torque_map(torque_map_t* map_ptr, uint16_t input) /** * @brief A linear torque map */ -uint16_t linear_torque_map(torque_map_t* map_ptr, uint16_t input) +uint16_t linear_torque_map(torque_map_t *map_ptr, uint16_t input) { - const float scale_factor = map_ptr->config_ptr->output_max - / (float) map_ptr->config_ptr->input_max; + const float scale_factor = map_ptr->output_max / (float)map_ptr->config_ptr->input_max; - const uint16_t torque = (uint16_t) (input * scale_factor); - - // TODO: clip to range + const uint16_t torque = (uint16_t)(input * scale_factor); return torque; } -uint16_t apply_speed_limit(torque_map_t* map_ptr, uint16_t input, int16_t speed) +/** + * @brief (input/input_max)^exponent torque map + */ +uint16_t exponential_torque_map(torque_map_t *map_ptr, uint16_t input) { - uint16_t result = 0; - if (speed < map_ptr->speed_start) - { - result = input; - } - else if (speed > map_ptr->speed_end) + if (input > map_ptr->config_ptr->input_max) { - if (input < map_ptr->speed_min) - { - result = input; - } - else - { - result = map_ptr->speed_min; - } - } - else - { - uint16_t max_torque - = map_ptr->config_ptr->output_max - - (map_ptr->config_ptr->output_max - map_ptr->speed_min) - * (speed - map_ptr->speed_start) - / (map_ptr->speed_end - map_ptr->speed_start); - - if (input < max_torque) - { - result = input; - } - else - { - result = max_torque; - } + input = map_ptr->config_ptr->input_max; } - return result; + const float fraction = (float)input / (float)map_ptr->config_ptr->input_max; + const float shaped = powf(fraction, map_ptr->config_ptr->exponent); + + return (uint16_t)(shaped * map_ptr->output_max); } \ No newline at end of file diff --git a/src/SUFST/Src/Interfaces/adc_scan.c b/src/SUFST/Src/Interfaces/adc_scan.c new file mode 100644 index 00000000..cfca0a35 --- /dev/null +++ b/src/SUFST/Src/Interfaces/adc_scan.c @@ -0,0 +1,135 @@ +/*************************************************************************** + * @file adc_scan.c + * @brief Free-running scan+DMA ADC sampling, with rolling-average readout + ***************************************************************************/ + +#include "adc_scan.h" + +#define ADC1_NUM_CHANNELS 5 +#define ADC1_NUM_SCANS 35 +#define ADC1_BUF_LEN (ADC1_NUM_CHANNELS * ADC1_NUM_SCANS) + +#define ADC2_NUM_CHANNELS 1 +#define ADC2_NUM_SCANS 174 +#define ADC2_BUF_LEN (ADC2_NUM_CHANNELS * ADC2_NUM_SCANS) + +/* + * Written by DMA in circular mode, so always volatile from the CPU's point + * of view. Placed in the .dma_bss linker section (see + * STM32F746ZGTx_FLASH.ld) to guarantee they land in DMA-reachable SRAM + * rather than DTCM, which DMA masters cannot access. + * + * D-cache is not enabled anywhere in this codebase (no SCB_EnableDCache() + * call), so no cache maintenance is needed around these buffers. If that + * ever changes, these buffers will need an MPU no-cache region or manual + * SCB_InvalidateDCache_by_Addr() calls before each read below. + */ +static volatile uint16_t adc1_buf[ADC1_BUF_LEN] + __attribute__((section(".dma_bss"))); +static volatile uint16_t adc2_buf[ADC2_BUF_LEN] + __attribute__((section(".dma_bss"))); + +static volatile bool adc1_primed = false; +static volatile bool adc2_primed = false; +static volatile bool adc1_faulted = false; +static volatile bool adc2_faulted = false; + +/** + * @brief Starts the free-running ADC1/ADC2 scans + * + * @details Must be called once, after MX_ADC1_Init()/MX_ADC2_Init(). Readings + * are not valid until adc_scan_is_ready() returns true, ~1ms later. + */ +status_t adc_scan_init(void) +{ + status_t status = STATUS_OK; + + if (HAL_ADC_Start_DMA(&hadc1, (uint32_t *)adc1_buf, ADC1_BUF_LEN) != HAL_OK) + { + status = STATUS_ERROR; + } + + if (HAL_ADC_Start_DMA(&hadc2, (uint32_t *)adc2_buf, ADC2_BUF_LEN) != HAL_OK) + { + status = STATUS_ERROR; + } + + return status; +} + +/** + * @brief Rolling average of the last ~1ms of samples for one channel + * + * @param[in] hadc ADC instance (&hadc1 or &hadc2) + * @param[in] slot 0-based index into hadc's scan sequence (rank - 1) + */ +uint16_t adc_scan_get_average(const ADC_HandleTypeDef *hadc, uint8_t slot) +{ + const volatile uint16_t *buf; + uint8_t stride; + uint16_t num_scans; + + if (hadc->Instance == ADC2) + { + buf = adc2_buf; + stride = ADC2_NUM_CHANNELS; + num_scans = ADC2_NUM_SCANS; + } + else + { + buf = adc1_buf; + stride = ADC1_NUM_CHANNELS; + num_scans = ADC1_NUM_SCANS; + } + + uint32_t sum = 0; + + for (uint16_t i = 0; i < num_scans; i++) + { + sum += buf[(i * stride) + slot]; + } + + return (uint16_t)(sum / num_scans); +} + +/** + * @brief True once hadc has completed at least one full scan cycle and has + * not since faulted (e.g. DMA overrun) + */ +bool adc_scan_is_ready(const ADC_HandleTypeDef *hadc) +{ + if (hadc->Instance == ADC2) + { + return adc2_primed && !adc2_faulted; + } + + return adc1_primed && !adc1_faulted; +} + +// trunk-ignore(cppcheck/constParameterPointer) +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) +{ + if (hadc->Instance == ADC1) + { + adc1_primed = true; + adc1_faulted = false; + } + else if (hadc->Instance == ADC2) + { + adc2_primed = true; + adc2_faulted = false; + } +} + +// trunk-ignore(cppcheck/constParameterPointer) +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + if (hadc->Instance == ADC1) + { + adc1_faulted = true; + } + else if (hadc->Instance == ADC2) + { + adc2_faulted = true; + } +} diff --git a/src/SUFST/Src/Interfaces/apps.c b/src/SUFST/Src/Interfaces/apps.c index 3e996882..60cf3443 100644 --- a/src/SUFST/Src/Interfaces/apps.c +++ b/src/SUFST/Src/Interfaces/apps.c @@ -1,141 +1,127 @@ -#include "apps.h" - -/** - * @brief Initialises the APPS - * - * @param[in] apps_ptr APPS context - */ - -status_t apps_init(apps_context_t* apps_ptr, const config_apps_t* config_ptr) -{ - apps_ptr->config_ptr = config_ptr; - apps_ptr->scs_error = SCS_ERROR_NONE; - - // initialise both SCS instances - status_t status = scs_create(&apps_ptr->apps_1_signal, &config_ptr->apps_1_scs); - - if (status == STATUS_OK) - { - status = scs_create(&apps_ptr->apps_2_signal, &config_ptr->apps_2_scs); - } - - return status; -} -/** - * @brief Reads the APPS - * - * @details If either of the APPS signals is invalid, or there is a - * discrepancy between them, the output is set to zero - * - * @param[in] apps_ptr APPS instance - * @param[out] reading_ptr Output reading - * - * @retval STATUS_OK Neither SCS has faulted and both APPS signals agree - * @retval STATUS_ERROR SCS fault, or signals disagree - */ -status_t apps_read(apps_context_t *apps_ptr, uint16_t *reading_ptr) -{ - status_t status = STATUS_OK; - uint16_t reading_1 = 0; - uint16_t reading_2 = 0; - - /* static uint64_t count = 0; */ - - /* uint8_t max_torque_percentage = 10; */ - /* uint8_t time_s = 30; */ - - /* *reading_ptr */ - /* = (uint16_t) ((1000 * (max_torque_percentage / 100)) / (time_s * - * 100)) */ - /* * count; // At 100Hz */ - /* // 1000 is the max mapped value for APPS (config.c) */ - - /* count = (count >= (time_s * 100)) ? count : count + 1; */ - - // read both signals - status_t status_1 = scs_read(&apps_ptr->apps_1_signal, &reading_1); - scs_status_t status_1_verbose = apps_ptr->apps_1_signal.status_verbose; - status_t status_2 = scs_read(&apps_ptr->apps_2_signal, &reading_2); - scs_status_t status_2_verbose = apps_ptr->apps_2_signal.status_verbose; - uint16_t adc_reading = get_adc(&apps_ptr->apps_2_signal); - - if (status_1 != STATUS_OK) - { - if (status_1_verbose == STATUS_THRESHOLD_ERROR) - { - LOG_INFO("APPS1 threshold error; "); - } - else - { - LOG_INFO("APPS1 unknown error; "); - } - status = STATUS_ERROR; - apps_ptr->scs_error |= SCS_ERROR_APPS1; - } - else if (status_1_verbose == STATUS_THRESHOLD_WARNING) - { - LOG_INFO("APPS1 threshold warning; "); - } - - LOG_INFO("APPS1 reading: %d; ", reading_1); - - if (status_2 != STATUS_OK) - { - if (status_2_verbose == STATUS_THRESHOLD_ERROR) - { - LOG_INFO("APPS2 threshold error; "); - } - else - { - LOG_INFO("APPS2 unknown error; "); - } - status = STATUS_ERROR; - apps_ptr->scs_error |= SCS_ERROR_APPS2; - } - else if (status_2_verbose == STATUS_THRESHOLD_WARNING) - { - LOG_INFO("APPS2 threshold warning; "); - } - - LOG_INFO("APPS2 reading: %d; ", reading_2); - - // // check for discrepancy - uint16_t diff = (reading_1 > reading_2) ? (reading_1 - reading_2) - : (reading_2 - reading_1); - - if (diff > apps_ptr->config_ptr->max_discrepancy) - { - LOG_INFO("DIFF error; "); - status = STATUS_ERROR; - apps_ptr->scs_error |= SCS_ERROR_APPS_DISCREPANCY; - } - - // return reading - if (status == STATUS_OK) - { - *reading_ptr = reading_2; //(reading_1 + reading_2) / 2; - } - else - { - *reading_ptr = 0; - } - - LOG_INFO("\n"); - - return status; -} - -/** - * @brief Reads the APPS to check if it is plausible - * - * @details This should be used when you don't care what the actual reading - * is, but you want to know if the APPS is plausible - * - * @param[in] apps_ptr APPS context - */ -bool apps_check_plausibility(apps_context_t *apps_ptr) -{ - uint16_t reading = 0; - status_t status = apps_read(apps_ptr, &reading); - return (status == STATUS_OK); -} +#include "apps.h" + +static const char *scs_label(status_t status, scs_status_t verbose) +{ + if (status != STATUS_OK) + return verbose == STATUS_THRESHOLD_ERROR ? "TERR" : "ERR"; + return verbose == STATUS_THRESHOLD_WARNING ? "WARN" : "OK"; +} + +/** + * @brief Initialises the APPS + * + * @param[in] apps_ptr APPS context + */ + +status_t apps_init(apps_context_t *apps_ptr, const config_apps_t *config_ptr) +{ + apps_ptr->config_ptr = config_ptr; + apps_ptr->scs_error = SCS_ERROR_NONE; + + // initialise both SCS instances + status_t status = scs_create(&apps_ptr->apps_1_signal, &config_ptr->apps_1_scs); + + if (status == STATUS_OK) + { + status = scs_create(&apps_ptr->apps_2_signal, &config_ptr->apps_2_scs); + } + + return status; +} +/** + * @brief Reads the APPS + * + * @details If either of the APPS signals is invalid, or there is a + * discrepancy between them, the output is set to zero + * + * @param[in] apps_ptr APPS instance + * @param[out] reading_ptr Output reading + * + * @retval STATUS_OK Neither SCS has faulted and both APPS signals agree + * @retval STATUS_ERROR SCS fault, or signals disagree + */ +status_t apps_read(apps_context_t *apps_ptr, uint16_t *reading_ptr) +{ + status_t status = STATUS_OK; + uint8_t scs_error = SCS_ERROR_NONE; + uint16_t reading_1 = 0; + uint16_t reading_2 = 0; + + /* static uint64_t count = 0; */ + + /* uint8_t max_torque_percentage = 10; */ + /* uint8_t time_s = 30; */ + + /* *reading_ptr */ + /* = (uint16_t) ((1000 * (max_torque_percentage / 100)) / (time_s * + * 100)) */ + /* * count; // At 100Hz */ + /* // 1000 is the max mapped value for APPS (config.c) */ + + /* count = (count >= (time_s * 100)) ? count : count + 1; */ + + // read both signals + status_t status_1 = scs_read(&apps_ptr->apps_1_signal, &reading_1); + scs_status_t status_1_verbose = apps_ptr->apps_1_signal.status_verbose; + status_t status_2 = scs_read(&apps_ptr->apps_2_signal, &reading_2); + scs_status_t status_2_verbose = apps_ptr->apps_2_signal.status_verbose; + + if (apps_ptr->config_ptr->inverted) + { + reading_1 = apps_ptr->config_ptr->apps_1_scs.max_mapped - reading_1; + reading_2 = apps_ptr->config_ptr->apps_2_scs.max_mapped - reading_2; + } + + if (status_1 != STATUS_OK) + { + status = STATUS_ERROR; + scs_error |= SCS_ERROR_APPS1; + } + + if (status_2 != STATUS_OK) + { + status = STATUS_ERROR; + scs_error |= SCS_ERROR_APPS2; + } + + // check for discrepancy + uint16_t diff = (reading_1 > reading_2) ? (reading_1 - reading_2) : + (reading_2 - reading_1); + + if (diff > apps_ptr->config_ptr->max_discrepancy) + { + status = STATUS_ERROR; + scs_error |= SCS_ERROR_APPS_DISCREPANCY; + + LOG_WARN("APPS A1:%d[%s] A2:%d[%s] diff:%d[!]\n", reading_1, + scs_label(status_1, status_1_verbose), reading_2, + scs_label(status_2, status_2_verbose), diff); + } + else + { + LOG_DEBUG("APPS A1:%d[%s] A2:%d[%s] diff:%d\n", reading_1, + scs_label(status_1, status_1_verbose), reading_2, + scs_label(status_2, status_2_verbose), diff); + } + + // return reading + *reading_ptr = (status == STATUS_OK) ? reading_2 : 0; //(reading_1 + reading_2) / 2; + + apps_ptr->scs_error = scs_error; + return status; +} + +/** + * @brief Reads the APPS to check if it is plausible + * + * @details This should be used when you don't care what the actual reading + * is, but you want to know if the APPS is plausible + * + * @param[in] apps_ptr APPS context + */ +bool apps_check_plausibility(apps_context_t *apps_ptr) +{ + uint16_t reading = 0; + status_t status = apps_read(apps_ptr, &reading); + return (status == STATUS_OK); +} diff --git a/src/SUFST/Src/Interfaces/bps.c b/src/SUFST/Src/Interfaces/bps.c index 017e4c2a..89437855 100644 --- a/src/SUFST/Src/Interfaces/bps.c +++ b/src/SUFST/Src/Interfaces/bps.c @@ -6,18 +6,16 @@ * @param[in] bps_ptr BPS context * @param[in] config_ptr Configuration */ -status_t bps_init(bps_context_t* bps_ptr, const config_bps_t* config_ptr) +status_t bps_init(bps_context_t *bps_ptr, const config_bps_t *config_ptr) { bps_ptr->config_ptr = config_ptr; // compute pressure thresholds - const uint16_t range - = config_ptr->scs.max_mapped - config_ptr->scs.min_mapped; + const uint16_t range = config_ptr->scs.max_mapped - config_ptr->scs.min_mapped; const uint16_t offset = config_ptr->scs.min_mapped; - bps_ptr->fully_pressed_threshold - = (config_ptr->fully_pressed_fraction * range) + offset; + bps_ptr->fully_pressed_threshold = (config_ptr->fully_pressed_fraction * range) + offset; // create the SCS instance status_t status = scs_create(&bps_ptr->signal, &config_ptr->scs); @@ -31,7 +29,7 @@ status_t bps_init(bps_context_t* bps_ptr, const config_bps_t* config_ptr) * @param[in] bps_ptr * @param[out] reading_ptr */ -status_t bps_read(bps_context_t* bps_ptr, uint16_t* reading_ptr) +status_t bps_read(bps_context_t *bps_ptr, uint16_t *reading_ptr) { status_t status = scs_read(&bps_ptr->signal, reading_ptr); scs_status_t status_verbose = bps_ptr->signal.status_verbose; @@ -40,20 +38,20 @@ status_t bps_read(bps_context_t* bps_ptr, uint16_t* reading_ptr) { if (status_verbose == STATUS_THRESHOLD_ERROR) { - LOG_INFO("BPS threshold error; "); + LOG_INFO("BPS threshold error;\n"); } else { - LOG_INFO("BPS unknown error; "); + LOG_INFO("BPS unknown error;\n"); } status = STATUS_ERROR; } else if (status_verbose == STATUS_THRESHOLD_WARNING) { - LOG_INFO("BPS threshold warning; "); + LOG_DEBUG("BPS threshold warning;\n"); } - // LOG_INFO("BPS reading: %d; ", *reading_ptr); + LOG_DEBUG("BPS reading: %d;\n", *reading_ptr); return status; } @@ -66,7 +64,7 @@ status_t bps_read(bps_context_t* bps_ptr, uint16_t* reading_ptr) * @retval true BPS is fully pressed * @retval false BPS not fully pressed, or SCS fault */ -bool bps_fully_pressed(bps_context_t* bps_ptr) +bool bps_fully_pressed(bps_context_t *bps_ptr) { uint16_t reading = 0; status_t status = bps_read(bps_ptr, &reading); @@ -84,7 +82,7 @@ bool bps_fully_pressed(bps_context_t* bps_ptr) * @retval true BPS is pressed * @retval false BPS is not pressed, or SCS fault */ -bool bps_valid(bps_context_t* bps_ptr) +bool bps_valid(bps_context_t *bps_ptr) { uint16_t reading = 0; status_t status = bps_read(bps_ptr, &reading); diff --git a/src/SUFST/Src/Interfaces/io.c b/src/SUFST/Src/Interfaces/io.c new file mode 100644 index 00000000..61eea997 --- /dev/null +++ b/src/SUFST/Src/Interfaces/io.c @@ -0,0 +1,86 @@ +#include "io.h" + +/** + * @brief Sets the specified GPIO pin(s) to low, so the output will be + * high, due to the io protection on the STAG 12 VCU + * + * @param[in] port GPIO port definition + * @param[in] pin GPIO pin number(s) + */ +status_t VCU_Output_High(GPIO_TypeDef *port, uint16_t pin) +{ + if (IS_GPIO_ALL_INSTANCE(port) && IS_GPIO_PIN(pin)) + { + HAL_GPIO_WritePin(port, pin, GPIO_PIN_RESET); + return STATUS_OK; + } + return STATUS_ERROR; +} + +/** + * @brief Sets the specified GPIO pin(s) to high, so the output will be + * low, due to the io inversion on the STAG 12 VCU + * + * @param[in] port GPIO port definition + * @param[in] pin GPIO pin number(s) + */ +status_t VCU_Output_Low(GPIO_TypeDef *port, uint16_t pin) +{ + if (IS_GPIO_ALL_INSTANCE(port) && IS_GPIO_PIN(pin)) + { + HAL_GPIO_WritePin(port, pin, GPIO_PIN_SET); + return STATUS_OK; + } + return STATUS_ERROR; +} + +/** + * @brief Sets the specified GPIO pin(s) based on the given state + * + * @param[in] port GPIO port definition + * @param[in] pin GPIO pin number(s) + * @param[in] state Desired state (GPIO_PIN_SET or GPIO_PIN_RESET) + */ +status_t VCU_Output_Write(GPIO_TypeDef *port, uint16_t pin, GPIO_PinState state) +{ + if (state == GPIO_PIN_RESET) + { + return VCU_Output_Low(port, pin); + } + else if (state == GPIO_PIN_SET) + { + return VCU_Output_High(port, pin); + } + return STATUS_ERROR; +} + +/** + * @brief Toggles the specified GPIO pin(s) + * + * @param[in] port GPIO port definition + * @param[in] pin GPIO pin number(s) + */ +status_t VCU_Output_Toggle(GPIO_TypeDef *port, uint16_t pin) +{ + if (IS_GPIO_ALL_INSTANCE(port) && IS_GPIO_PIN(pin)) + { + HAL_GPIO_TogglePin(port, pin); + return STATUS_OK; + } + return STATUS_ERROR; +} + +/** + * @brief Reads the logical state of the specified GPIO pin(s) based on STAG 12 VCU logic level inversion + * @param[in] port GPIO port definition + * @param[in] pin GPIO pin number(s) + */ +bool VCU_Input_Read(GPIO_TypeDef *port, uint16_t pin) +{ + if (!IS_GPIO_ALL_INSTANCE(port) || !IS_GPIO_PIN(pin)) + { + return false; + } + GPIO_PinState pin_state = HAL_GPIO_ReadPin(port, pin); + return !pin_state; +} diff --git a/src/SUFST/Src/Interfaces/rs232.c b/src/SUFST/Src/Interfaces/rs232.c new file mode 100644 index 00000000..7a24269e --- /dev/null +++ b/src/SUFST/Src/Interfaces/rs232.c @@ -0,0 +1,21 @@ +#include "rs232.h" + +#include "main.h" + +void rs232_enable(void) +{ + // pull the TRS3221E FORCEON low and FORCEOFF high: normal operation mode + HAL_GPIO_WritePin(RS232_FORCEON_GPIO_Port, RS232_FORCEON_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(RS232_FORCEOFF_GPIO_Port, RS232_FORCEOFF_Pin, GPIO_PIN_SET); +} + +void rs232_disable(void) +{ + // pull the TRS3221E FORCEOFF low + HAL_GPIO_WritePin(RS232_FORCEOFF_GPIO_Port, RS232_FORCEOFF_Pin, GPIO_PIN_RESET); +} + +bool rs232_is_valid(void) +{ + return HAL_GPIO_ReadPin(RS232_BAD_GPIO_Port, RS232_BAD_Pin) == GPIO_PIN_SET; +} diff --git a/src/SUFST/Src/Interfaces/rtds.c b/src/SUFST/Src/Interfaces/rtds.c index 5212741b..8dced0d3 100644 --- a/src/SUFST/Src/Interfaces/rtds.c +++ b/src/SUFST/Src/Interfaces/rtds.c @@ -1,16 +1,19 @@ #include "rtds.h" -#include #include +#include "io.h" + /** * @brief Activates the RTDS and sleeps the calling thread for the * duration of activation * * @param[in] config_ptr RTDS configuration */ -status_t rtds_activate(const config_rtds_t* config_ptr) +status_t rtds_activate(const config_rtds_t *config_ptr) { + + // unlinke other outouts, the RTDS is active high. HAL_GPIO_WritePin(config_ptr->port, config_ptr->pin, GPIO_PIN_SET); LOG_INFO("Waiting - RTDS\n"); UINT tx_status = tx_thread_sleep(config_ptr->active_ticks); @@ -18,4 +21,64 @@ status_t rtds_activate(const config_rtds_t* config_ptr) HAL_GPIO_WritePin(config_ptr->port, config_ptr->pin, GPIO_PIN_RESET); return (tx_status == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; -} \ No newline at end of file +} + +/** + * @brief Initialises non-blocking RTDS pulse state and ensures the + * RTDS output starts off + * + * @param[in] pulse_ptr RTDS pulse context + * @param[in] config_ptr RTDS configuration + */ +void rtds_pulse_init(rtds_pulse_context_t *pulse_ptr, const config_rtds_t *config_ptr) +{ + pulse_ptr->config_ptr = config_ptr; + pulse_ptr->active = false; + pulse_ptr->pin_on = false; + pulse_ptr->phase_start = 0; + + HAL_GPIO_WritePin(config_ptr->port, config_ptr->pin, GPIO_PIN_RESET); +} + +/** + * @brief Advances the non-blocking RTDS pulse by one control-loop tick + * + * @param[in] pulse_ptr RTDS pulse context + * @param[in] enable Whether the pulse should currently be running + */ +void rtds_pulse_tick(rtds_pulse_context_t *pulse_ptr, bool enable) +{ + const config_rtds_t *config_ptr = pulse_ptr->config_ptr; + + if (!enable) + { + if (pulse_ptr->pin_on) + { + HAL_GPIO_WritePin(config_ptr->port, config_ptr->pin, GPIO_PIN_RESET); + pulse_ptr->pin_on = false; + } + pulse_ptr->active = false; + return; + } + + if (!pulse_ptr->active) + { + // rising edge: start the pulse immediately with the RTDS on + pulse_ptr->active = true; + pulse_ptr->pin_on = true; + pulse_ptr->phase_start = tx_time_get(); + HAL_GPIO_WritePin(config_ptr->port, config_ptr->pin, GPIO_PIN_SET); + return; + } + + uint32_t phase_ticks = pulse_ptr->pin_on ? config_ptr->pulse_on_ticks : + config_ptr->pulse_off_ticks; + + if (tx_time_get() >= pulse_ptr->phase_start + phase_ticks) + { + pulse_ptr->pin_on = !pulse_ptr->pin_on; + HAL_GPIO_WritePin(config_ptr->port, config_ptr->pin, + pulse_ptr->pin_on ? GPIO_PIN_SET : GPIO_PIN_RESET); + pulse_ptr->phase_start = tx_time_get(); + } +} diff --git a/src/SUFST/Src/Interfaces/scs.c b/src/SUFST/Src/Interfaces/scs.c index 35079648..0b843264 100644 --- a/src/SUFST/Src/Interfaces/scs.c +++ b/src/SUFST/Src/Interfaces/scs.c @@ -8,16 +8,15 @@ #include +#include "adc_scan.h" #include "clip_to_range.h" /* * internal function prototypes */ static uint16_t map_adc_reading(scs_t *scs_ptr); -static scs_status_t validate(uint16_t adc_reading, - uint16_t max_adc_reading, - uint16_t min_adc_reading, - uint32_t max_diff); +static scs_status_t +validate(uint16_t adc_reading, uint16_t max_adc_reading, uint16_t min_adc_reading, uint32_t max_diff); /** * @brief Create new safety critical signal @@ -39,9 +38,8 @@ status_t scs_create(scs_t *scs_ptr, const config_scs_t *config_ptr) // pre-compute the scale factors and validation constants scs_ptr->scale_up = (adc_range < mapped_range); - scs_ptr->scale_factor = scs_ptr->scale_up - ? ((float)mapped_range / adc_range) - : ((float)adc_range / mapped_range); + scs_ptr->scale_factor = scs_ptr->scale_up ? ((float)mapped_range / adc_range) : + ((float)adc_range / mapped_range); scs_ptr->max_bounds_diff = adc_range * config_ptr->outside_bounds_fraction; return STATUS_OK; @@ -64,17 +62,15 @@ status_t scs_read(scs_t *scs_ptr, uint16_t *reading_ptr) ADC_HandleTypeDef *hadc = scs_ptr->config_ptr->hadc; - // read from the ADC and validate - if ((HAL_ADC_Start(hadc) == HAL_OK) && (HAL_ADC_PollForConversion(hadc, HAL_MAX_DELAY) == HAL_OK)) + // read the current rolling average from the free-running ADC scan, and validate + if (adc_scan_is_ready(hadc)) { - scs_ptr->adc_reading = HAL_ADC_GetValue(hadc); - scs_ptr->status_verbose = validate(scs_ptr->adc_reading, - scs_ptr->config_ptr->max_adc, - scs_ptr->config_ptr->min_adc, - scs_ptr->max_bounds_diff); - scs_ptr->is_valid - = scs_ptr->status_verbose == STATUS_THRESHOLD_OK - || scs_ptr->status_verbose == STATUS_THRESHOLD_WARNING; + scs_ptr->adc_reading = adc_scan_get_average(hadc, scs_ptr->config_ptr->scan_slot); + scs_ptr->status_verbose = + validate(scs_ptr->adc_reading, scs_ptr->config_ptr->max_adc, + scs_ptr->config_ptr->min_adc, scs_ptr->max_bounds_diff); + scs_ptr->is_valid = scs_ptr->status_verbose == STATUS_THRESHOLD_OK || + scs_ptr->status_verbose == STATUS_THRESHOLD_WARNING; if (scs_ptr->is_valid) { @@ -91,8 +87,8 @@ status_t scs_read(scs_t *scs_ptr, uint16_t *reading_ptr) } else { - // TODO: HAL errors here behave as SCS errors, consider if they should - // be treated differently for diagnostics + // ADC scan not yet primed (just after boot), or has faulted (e.g. DMA + // overrun); behaves as an SCS error until it recovers scs_ptr->status = STATUS_ERROR; } @@ -100,14 +96,13 @@ status_t scs_read(scs_t *scs_ptr, uint16_t *reading_ptr) { scs_ptr->invalid_start_tick = tx_time_get(); scs_ptr->is_valid = false; - scs_ptr->adc_reading = scs_ptr->config_ptr->min_adc; scs_ptr->mapped_reading = scs_ptr->config_ptr->min_mapped; } return scs_ptr->status; } -uint16_t get_adc(scs_t *scs_ptr) +uint16_t get_adc(const scs_t *scs_ptr) { return scs_ptr->adc_reading; } @@ -119,19 +114,17 @@ uint16_t get_adc(scs_t *scs_ptr) */ uint16_t map_adc_reading(scs_t *scs_ptr) { - uint16_t clipped = clip_to_range(scs_ptr->adc_reading, - scs_ptr->config_ptr->min_adc, + uint16_t clipped = clip_to_range(scs_ptr->adc_reading, scs_ptr->config_ptr->min_adc, scs_ptr->config_ptr->max_adc); uint16_t shifted = clipped - scs_ptr->config_ptr->min_adc; - uint16_t scaled = (scs_ptr->scale_up) ? shifted * scs_ptr->scale_factor - : shifted / scs_ptr->scale_factor; + uint16_t scaled = (scs_ptr->scale_up) ? shifted * scs_ptr->scale_factor : + shifted / scs_ptr->scale_factor; uint16_t mapped = scaled + scs_ptr->config_ptr->min_mapped; - return clip_to_range(mapped, - scs_ptr->config_ptr->min_mapped, + return clip_to_range(mapped, scs_ptr->config_ptr->min_mapped, scs_ptr->config_ptr->max_mapped); } @@ -165,10 +158,8 @@ uint16_t map_adc_reading(scs_t *scs_ptr) * @return true The signal is valid * @return false The signal is invalid */ -scs_status_t validate(uint16_t adc_reading, - uint16_t max_adc_reading, - uint16_t min_adc_reading, - uint32_t max_diff) +scs_status_t +validate(uint16_t adc_reading, uint16_t max_adc_reading, uint16_t min_adc_reading, uint32_t max_diff) { scs_status_t status = STATUS_THRESHOLD_ERROR; uint16_t low_diff = 0; diff --git a/src/SUFST/Src/Interfaces/trc.c b/src/SUFST/Src/Interfaces/trc.c index 124293ce..dc2272f5 100644 --- a/src/SUFST/Src/Interfaces/trc.c +++ b/src/SUFST/Src/Interfaces/trc.c @@ -3,6 +3,8 @@ #include #include +#include "io.h" + /** * @brief Sets the state of the TS on connection to the TRC * @@ -14,13 +16,12 @@ */ status_t trc_set_ts_on(GPIO_PinState state) { - HAL_GPIO_WritePin(TS_ON_GPIO_Port, TS_ON_Pin, state); - return STATUS_OK; + return VCU_Output_Write(TS_ON_GPIO_Port, TS_ON_Pin, state); } bool trc_ready(void) { - return HAL_GPIO_ReadPin(TS_READY_GPIO_Port, TS_READY_Pin); + return VCU_Input_Read(TS_READY_GPIO_Port, TS_READY_Pin); } /** @@ -40,10 +41,9 @@ status_t trc_wait_for_ready(uint32_t poll_ticks, uint32_t timeout) while (!done && (status == STATUS_OK)) { - status = (tx_thread_sleep(poll_ticks) == TX_SUCCESS) ? STATUS_OK - : STATUS_ERROR; + status = (tx_thread_sleep(poll_ticks) == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; - bool ready_high = (HAL_GPIO_ReadPin(TS_READY_GPIO_Port, TS_READY_Pin) == GPIO_PIN_SET); + bool ready_high = VCU_Input_Read(TS_READY_GPIO_Port, TS_READY_Pin); if (ready_high) { diff --git a/src/SUFST/Src/Interfaces/usb_mass_storage_mode.c b/src/SUFST/Src/Interfaces/usb_mass_storage_mode.c new file mode 100644 index 00000000..d452d26f --- /dev/null +++ b/src/SUFST/Src/Interfaces/usb_mass_storage_mode.c @@ -0,0 +1,193 @@ +#include "usb_mass_storage_mode.h" + +#include + +#include "heartbeat.h" + +#include "log.h" +#include "main.h" +#include "sdmmc.h" +#include "usb_otg.h" +#include "ux_api.h" +#include "ux_dcd_stm32.h" +#include "ux_device_class_storage.h" +#include "ux_device_descriptors.h" +#include "ux_system.h" + +bool usb_mass_storage_mode_button_held(void) +{ + // USER_BUTTON has an external pullup, so is LOW if held + return !HAL_GPIO_ReadPin(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin); +} + +static UINT msc_media_status(VOID *storage, ULONG lun, ULONG media_id, ULONG *media_status) +{ + (void)storage; + (void)lun; + (void)media_id; + *media_status = 0; + if (HAL_SD_GetState(&hsd1) != HAL_SD_STATE_READY) + return UX_ERROR; + return UX_SUCCESS; +} + +static UINT +msc_media_read(VOID *storage, ULONG lun, UCHAR *data_pointer, ULONG number_blocks, ULONG lba, ULONG *media_status) +{ + (void)storage; + (void)lun; + (void)media_status; + if ((uint32_t)data_pointer % 4 != 0) + { + LOG_ERROR("msc_read: buf %p unaligned\n", data_pointer); + return UX_ERROR; + } + HAL_StatusTypeDef dma_status = + HAL_SD_ReadBlocks_DMA(&hsd1, data_pointer, (uint32_t)lba, (uint32_t)number_blocks); + if (dma_status != HAL_OK) + { + LOG_ERROR("msc_read: DMA failed lba=%lu nblk=%lu halstate=%d " + "err=0x%lx\n", + lba, number_blocks, (int)HAL_SD_GetState(&hsd1), + HAL_SD_GetError(&hsd1)); + return UX_ERROR; + } + while (HAL_SD_GetState(&hsd1) != HAL_SD_STATE_READY) + tx_thread_sleep(1); + return UX_SUCCESS; +} + +static UINT +msc_media_write(VOID *storage, ULONG lun, UCHAR *data_pointer, ULONG number_blocks, ULONG lba, ULONG *media_status) +{ + (void)storage; + (void)lun; + (void)media_status; + if (HAL_SD_WriteBlocks_DMA(&hsd1, data_pointer, (uint32_t)lba, + (uint32_t)number_blocks) != HAL_OK) + return UX_ERROR; + // Wait for DMA completion first (no SDMMC command) before issuing CMD13 + while (HAL_SD_GetState(&hsd1) != HAL_SD_STATE_READY) + tx_thread_sleep(1); + // Now safe to poll card programming state via CMD13 + while (HAL_SD_GetCardState(&hsd1) != HAL_SD_CARD_TRANSFER) + tx_thread_sleep(1); + return UX_SUCCESS; +} + +#define UX_DEVICE_POOL_SIZE (64 * 1024) + +static void usb_msc_thread_entry(ULONG input) +{ + usb_msc_context_t *ctx = (usb_msc_context_t *)input; + LOG_INFO("Entering USB mass storage mode\n"); + enter_usb_mass_storage_mode(ctx->pool); +} + +status_t usb_msc_init(usb_msc_context_t *ctx, TX_BYTE_POOL *pool, const config_usb_msc_t *config_ptr) +{ + ctx->pool = pool; + void *stack_ptr = NULL; + if (tx_byte_allocate(pool, &stack_ptr, config_ptr->thread.stack_size, TX_NO_WAIT) != TX_SUCCESS) + return STATUS_ERROR; + if (tx_thread_create(&ctx->thread, (CHAR *)config_ptr->thread.name, usb_msc_thread_entry, + (ULONG)ctx, stack_ptr, config_ptr->thread.stack_size, + config_ptr->thread.priority, config_ptr->thread.priority, + TX_NO_TIME_SLICE, TX_AUTO_START) != TX_SUCCESS) + return STATUS_ERROR; + return STATUS_OK; +} + +status_t enter_usb_mass_storage_mode(TX_BYTE_POOL *pool) +{ + LOG_INFO("USB: Enter mass storage mode - usb otg init\n"); + MX_USB_OTG_FS_PCD_Init(); + LOG_INFO("USB: SD init\n"); + MX_SDMMC1_SD_Init(); + + LOG_INFO("USB: Get card info\n"); + HAL_SD_CardInfoTypeDef card_info; + if (HAL_SD_GetCardInfo(&hsd1, &card_info) != HAL_OK) + { + LOG_ERROR("USB MSC: HAL_SD_GetCardInfo failed\n"); + return STATUS_ERROR; + } + + LOG_INFO("USB: tx_byte_allocate\n"); + UCHAR *ux_pool = NULL; + if (tx_byte_allocate(pool, (VOID **)&ux_pool, UX_DEVICE_POOL_SIZE, TX_NO_WAIT) != TX_SUCCESS) + { + LOG_ERROR("USB MSC: failed to allocate USBX pool\n"); + return STATUS_ERROR; + } + + LOG_INFO("USB: ux_system_initialize\n"); + if (ux_system_initialize(ux_pool, UX_DEVICE_POOL_SIZE, UX_NULL, 0) != UX_SUCCESS) + { + LOG_ERROR("USB MSC: ux_system_initialize failed\n"); + return STATUS_ERROR; + } + + LOG_INFO("USB: USB framework\n"); + ULONG framework_len, string_len, language_len; + UCHAR *framework = USBD_Get_Device_Framework_Speed(USBD_FULL_SPEED, &framework_len); + UCHAR *strings = USBD_Get_String_Framework(&string_len); + UCHAR *language = USBD_Get_Language_Id_Framework(&language_len); + + LOG_INFO("USB: device stack initalize\n"); + if (ux_device_stack_initialize(UX_NULL, 0, framework, framework_len, strings, string_len, + language, language_len, UX_NULL) != UX_SUCCESS) + { + LOG_ERROR("USB MSC: ux_device_stack_initialize failed\n"); + return STATUS_ERROR; + } + + static UX_SLAVE_CLASS_STORAGE_PARAMETER storage_param; + storage_param.ux_slave_class_storage_parameter_number_lun = 1; + + UX_SLAVE_CLASS_STORAGE_LUN *lun = + &storage_param.ux_slave_class_storage_parameter_lun[0]; + lun->ux_slave_class_storage_media_last_lba = card_info.LogBlockNbr - 1; + lun->ux_slave_class_storage_media_block_length = card_info.LogBlockSize; + lun->ux_slave_class_storage_media_type = 0; // direct-access block device + lun->ux_slave_class_storage_media_removable_flag = 0x80; // removable + lun->ux_slave_class_storage_media_read_only_flag = 0; + lun->ux_slave_class_storage_media_read = msc_media_read; + lun->ux_slave_class_storage_media_write = msc_media_write; + lun->ux_slave_class_storage_media_status = msc_media_status; + lun->ux_slave_class_storage_media_flush = UX_NULL; + + storage_param.ux_slave_class_storage_parameter_vendor_id = + (UCHAR *)"SUFST "; + storage_param.ux_slave_class_storage_parameter_product_id = + (UCHAR *)"VCU SD Card "; + storage_param.ux_slave_class_storage_parameter_product_rev = + (UCHAR *)"1.0 "; + storage_param.ux_slave_class_storage_parameter_product_serial = + (UCHAR *)"00000001"; + + LOG_INFO("USB: device stack class register\n"); + if (ux_device_stack_class_register(_ux_system_slave_class_storage_name, ux_device_class_storage_entry, + 1, 0, &storage_param) != UX_SUCCESS) + { + LOG_ERROR("USB MSC: ux_device_stack_class_register failed\n"); + return STATUS_ERROR; + } + + LOG_INFO("USB: dcd_stm32_initialize\n"); + if (ux_dcd_stm32_initialize(0, (ULONG)&hpcd_USB_OTG_FS) != UX_SUCCESS) + { + LOG_ERROR("USB MSC: ux_dcd_stm32_initialize failed\n"); + return STATUS_ERROR; + } + + HAL_PCD_Start(&hpcd_USB_OTG_FS); + LOG_INFO("USB MSC: active, power cycle to exit\n"); + + heartbeat_set_fast(); + + while (1) + tx_thread_sleep(TX_WAIT_FOREVER); + + return STATUS_OK; +} diff --git a/src/SUFST/Src/Services/canbc.c b/src/SUFST/Src/Services/canbc.c index c4c6d35d..ff382fd0 100644 --- a/src/SUFST/Src/Services/canbc.c +++ b/src/SUFST/Src/Services/canbc.c @@ -1,6 +1,7 @@ #include "canbc.h" -#include +#include +#include /* * internal function prototypes @@ -13,44 +14,43 @@ static void send_bc_messages(canbc_context_t *canbc_h); * @brief Initialise CANBC service * * @param[in] canbc_h CANBC handle - * @param[in] rtcan_h RTCAN handle + * @param[in] rtcan_t_h RTCAN handle for the tractive bus + * @param[in] rtcan_s_h RTCAN handle for the sensor bus * @param[in] stack_pool_ptr Application memory pool * @param[in] config_ptr Configuration */ status_t canbc_init(canbc_context_t *canbc_h, - rtcan_handle_t *rtcan_h, + rtcan_handle_t *rtcan_t_h, + rtcan_handle_t *rtcan_s_h, TX_BYTE_POOL *stack_pool_ptr, const config_canbc_t *config_ptr) { - canbc_h->rtcan_h = rtcan_h; + canbc_h->rtcan_t_h = rtcan_t_h; + canbc_h->rtcan_s_h = rtcan_s_h; canbc_h->config_ptr = config_ptr; canbc_h->rolling_counter = 0; + canbc_h->rtcan1_error = 0; + canbc_h->rtcan2_error = 0; + canbc_h->canbc_error = 0; // create service thread void *stack_ptr = NULL; - UINT tx_status = tx_byte_allocate(stack_pool_ptr, - &stack_ptr, - config_ptr->thread.stack_size, - TX_NO_WAIT); + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); if (tx_status == TX_SUCCESS) { - tx_status = tx_thread_create(&canbc_h->thread, - (CHAR *)config_ptr->thread.name, - canbc_thread_entry, - (ULONG)canbc_h, - stack_ptr, - config_ptr->thread.stack_size, - config_ptr->thread.priority, - config_ptr->thread.priority, - TX_NO_TIME_SLICE, - TX_AUTO_START); + tx_status = + tx_thread_create(&canbc_h->thread, (CHAR *)config_ptr->thread.name, + canbc_thread_entry, (ULONG)canbc_h, stack_ptr, + config_ptr->thread.stack_size, config_ptr->thread.priority, + config_ptr->thread.priority, TX_NO_TIME_SLICE, TX_AUTO_START); } // create state mutex if (tx_status == TX_SUCCESS) { - tx_status = tx_mutex_create(&canbc_h->state_mutex, NULL, 0); + tx_status = tx_mutex_create(&canbc_h->state_mutex, NULL, TX_INHERIT); } return (tx_status == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; @@ -91,67 +91,103 @@ static void send_bc_messages(canbc_context_t *canbc_h) { UINT tx_status = tx_mutex_get(&canbc_h->state_mutex, TX_WAIT_FOREVER); - if (tx_status == TX_SUCCESS) + if (tx_status != TX_SUCCESS) { - // states + canbc_h->canbc_error = 1; + LOG_ERROR("canbc: failed to lock state\n"); + return; + } + + canbc_h->states.state.vcu_rolling_counter++; + canbc_states_t snapshot = canbc_h->states; + tx_mutex_put(&canbc_h->state_mutex); + + // states + { + rtcan_msg_t message = { .identifier = CAN_T_VCU_STATE_FRAME_ID, + .length = CAN_T_VCU_STATE_LENGTH, + .extended = CAN_T_VCU_STATE_IS_EXTENDED }; + + can_t_vcu_state_pack(message.data, &snapshot.state, message.length); + if (rtcan_transmit(canbc_h->rtcan_t_h, &message) != RTCAN_OK) { - rtcan_msg_t message = { .identifier = CAN_S_VCU_STATE_FRAME_ID, - .length = CAN_S_VCU_STATE_LENGTH, - .extended = CAN_S_VCU_STATE_IS_EXTENDED}; - - can_s_vcu_state_pack(message.data, - &canbc_h->states.state, - message.length); - rtcan_transmit(canbc_h->rtcan_h, &message); + canbc_h->rtcan2_error = 1; + LOG_ERROR("canbc: failed to transmit VCU state\n"); } + } + + // sensors + { + rtcan_msg_t message = { .identifier = CAN_S_VCU_SENSORS_FRAME_ID, + .length = CAN_S_VCU_SENSORS_LENGTH, + .extended = CAN_S_VCU_SENSORS_IS_EXTENDED }; - // sensors + can_s_vcu_sensors_pack(message.data, &snapshot.sensors, message.length); + if (rtcan_transmit(canbc_h->rtcan_s_h, &message) != RTCAN_OK) { - rtcan_msg_t message = { .identifier = CAN_S_VCU_SENSORS_FRAME_ID, - .length = CAN_S_VCU_SENSORS_LENGTH, - .extended = CAN_S_VCU_SENSORS_IS_EXTENDED}; - - can_s_vcu_sensors_pack(message.data, - &canbc_h->states.sensors, - message.length); - rtcan_transmit(canbc_h->rtcan_h, &message); + canbc_h->rtcan1_error = 1; + LOG_ERROR("canbc: failed to transmit VCU sensors\n"); } - // temps + } + + // temps + { + rtcan_msg_t message = { .identifier = CAN_S_VCU_TEMPS_FRAME_ID, + .length = CAN_S_VCU_TEMPS_LENGTH, + .extended = CAN_S_VCU_TEMPS_IS_EXTENDED }; + + can_s_vcu_temps_pack(message.data, &snapshot.temps, message.length); + if (rtcan_transmit(canbc_h->rtcan_s_h, &message) != RTCAN_OK) { - rtcan_msg_t message = { .identifier = CAN_S_VCU_TEMPS_FRAME_ID, - .length = CAN_S_VCU_TEMPS_LENGTH, - .extended = CAN_S_VCU_TEMPS_IS_EXTENDED}; - - can_s_vcu_temps_pack(message.data, - &canbc_h->states.temps, - message.length); - rtcan_transmit(canbc_h->rtcan_h, &message); + canbc_h->rtcan1_error = 1; + LOG_ERROR("canbc: failed to transmit VCU temps\n"); } + } + + // errors + { + rtcan_msg_t message = { .identifier = CAN_T_VCU_ERROR_FRAME_ID, + .length = CAN_T_VCU_ERROR_LENGTH, + .extended = CAN_T_VCU_ERROR_IS_EXTENDED }; - // errors + snapshot.errors.vcu_rtcan1_error = canbc_h->rtcan1_error; + snapshot.errors.vcu_rtcan2_error = canbc_h->rtcan2_error; + snapshot.errors.vcu_canbc_error = canbc_h->canbc_error; + + can_t_vcu_error_pack(message.data, &snapshot.errors, message.length); + if (rtcan_transmit(canbc_h->rtcan_t_h, &message) != RTCAN_OK) { - rtcan_msg_t message = { .identifier = CAN_S_VCU_ERROR_FRAME_ID, - .length = CAN_S_VCU_ERROR_LENGTH, - .extended = CAN_S_VCU_ERROR_IS_EXTENDED}; - - can_s_vcu_error_pack(message.data, - &canbc_h->states.errors, - message.length); - rtcan_transmit(canbc_h->rtcan_h, &message); + canbc_h->rtcan2_error = 1; + LOG_ERROR("canbc: failed to transmit VCU errors\n"); } + } + // pdm + { + rtcan_msg_t message = { .identifier = CAN_T_VCU_PDM_FRAME_ID, + .length = CAN_T_VCU_PDM_LENGTH, + .extended = CAN_T_VCU_PDM_IS_EXTENDED }; + + can_t_vcu_pdm_pack(message.data, &snapshot.pdm, message.length); + if (rtcan_transmit(canbc_h->rtcan_t_h, &message) != RTCAN_OK) { - rtcan_msg_t message = { .identifier = CAN_S_VCU_PDM_FRAME_ID, - .length = CAN_S_VCU_PDM_LENGTH, - .extended = CAN_S_VCU_PDM_IS_EXTENDED}; - - can_s_vcu_pdm_pack(message.data, - &canbc_h->states.pdm, - message.length); - rtcan_transmit(canbc_h->rtcan_h, &message); + canbc_h->rtcan2_error = 1; + LOG_ERROR("canbc: failed to transmit VCU PDM\n"); } + } + + // raw sensors debug + { + rtcan_msg_t message = { .identifier = CAN_S_VCU_SENSORS_RAW_FRAME_ID, + .length = CAN_S_VCU_SENSORS_RAW_LENGTH, + .extended = CAN_S_VCU_SENSORS_RAW_IS_EXTENDED }; - tx_mutex_put(&canbc_h->state_mutex); + can_s_vcu_sensors_raw_pack(message.data, &snapshot.sensors_raw, message.length); + if (rtcan_transmit(canbc_h->rtcan_s_h, &message) != RTCAN_OK) + { + canbc_h->rtcan1_error = 1; + LOG_ERROR("canbc: failed to transmit VCU raw sensors\n"); + } } } diff --git a/src/SUFST/Src/Services/ctrl.c b/src/SUFST/Src/Services/ctrl.c index 3eab12e8..285f32b6 100644 --- a/src/SUFST/Src/Services/ctrl.c +++ b/src/SUFST/Src/Services/ctrl.c @@ -1,701 +1,762 @@ -/***************************************************************************** - * @file driver_control.c - * @author Tim Brewis (@t-bre, tab1g19@soton.ac.uk) - * @author Toby Godfrey (@_tg03, tmag1g21@soton.ac.uk) - * @brief Driver control - ****************************************************************************/ - -#include "ctrl.h" - -#include - -#include "rtds.h" -#include "trc.h" - -/* - * internal function prototypes - */ -void ctrl_thread_entry(ULONG input); -void ctrl_state_machine_tick(ctrl_context_t* ctrl_ptr); -void ctrl_update_canbc_states(ctrl_context_t* ctrl_ptr); -void ctrl_handle_ts_fault(ctrl_context_t* ctrl_ptr); -status_t ctrl_get_apps_reading(tick_context_t* tick_ptr, - remote_ctrl_context_t* remote_ctrl_ptr, - uint16_t* result); -status_t ctrl_get_bps_reading(tick_context_t* tick_ptr, - remote_ctrl_context_t* remote_ctrl_ptr, - uint16_t* result); -bool ctrl_fan_passed_on_threshold(ctrl_context_t* ctrl_ptr); -bool ctrl_fan_passed_off_threshold(ctrl_context_t* ctrl_ptr); - -/** - * @brief Initialises control service - * - * @param[in] ctrl_ptr Control context - * @param[in] dash_ptr Dash context - * @param[in] canbc_ptr CANBC context - * @param[in] pm100_ptr PM100 context - * @param[in] stack_pool_ptr Byte pool to allocate thread stack from - * @param[in] config_ptr Configuration - * @param[in] apps_config_ptr APPS configuration - * @param[in] bps_config_ptr BPS configuration - * @param[in] rtds_config_ptr RTDS configuration - * @param[in] torque_map_config_ptr Torque map configuration - */ -status_t ctrl_init(ctrl_context_t* ctrl_ptr, - dash_context_t* dash_ptr, - pm100_context_t* pm100_ptr, - tick_context_t* tick_ptr, - remote_ctrl_context_t* remote_ctrl_ptr, - canbc_context_t* canbc_ptr, - TX_BYTE_POOL* stack_pool_ptr, - const config_ctrl_t* config_ptr, - const config_rtds_t* rtds_config_ptr, - const config_torque_map_t* torque_map_config_ptr) -{ - ctrl_ptr->state = CTRL_STATE_TS_BUTTON_WAIT; - ctrl_ptr->dash_ptr = dash_ptr; - ctrl_ptr->pm100_ptr = pm100_ptr; - ctrl_ptr->tick_ptr = tick_ptr; - ctrl_ptr->canbc_ptr = canbc_ptr; - ctrl_ptr->config_ptr = config_ptr; - ctrl_ptr->rtds_config_ptr = rtds_config_ptr; - ctrl_ptr->error = CTRL_ERROR_NONE; - ctrl_ptr->apps_reading = 0; - ctrl_ptr->bps_reading = 0; - ctrl_ptr->sagl_reading = 0; - ctrl_ptr->torque_request = 0; - ctrl_ptr->shdn_reading = 0; - ctrl_ptr->precharge_start = 0; - ctrl_ptr->inverter_pwr = false; - ctrl_ptr->pump_pwr = false; - ctrl_ptr->fan_pwr = false; - ctrl_ptr->remote_ctrl_ptr = remote_ctrl_ptr; - - // create the thread - void* stack_ptr = NULL; - UINT tx_status = tx_byte_allocate(stack_pool_ptr, - &stack_ptr, - config_ptr->thread.stack_size, - TX_NO_WAIT); - - if (tx_status == TX_SUCCESS) - { - tx_status = tx_thread_create(&ctrl_ptr->thread, - (CHAR*) config_ptr->thread.name, - ctrl_thread_entry, - (ULONG) ctrl_ptr, - stack_ptr, - config_ptr->thread.stack_size, - config_ptr->thread.priority, - config_ptr->thread.priority, - TX_NO_TIME_SLICE, - TX_AUTO_START); - } - - status_t status = (tx_status == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; - - // initialise the torque map - if (status == STATUS_OK) - { - status = torque_map_init(&ctrl_ptr->torque_map, torque_map_config_ptr); - } - - // make sure TS is disabled - trc_set_ts_on(GPIO_PIN_RESET); - - // check all ok before starting - if (status != STATUS_OK) - { - tx_thread_terminate(&ctrl_ptr->thread); - ctrl_ptr->error |= CTRL_ERROR_INIT; - } - - // send initial state update - ctrl_update_canbc_states(ctrl_ptr); - - return status; -} - -/** - * @brief Control thread entry function - * - * @param[in] input Control context - */ -void ctrl_thread_entry(ULONG input) -{ - ctrl_context_t* ctrl_ptr = (ctrl_context_t*) input; - - while (1) - { - uint32_t start_time = tx_time_get(); - dash_update_buttons(ctrl_ptr->dash_ptr); - - ctrl_ptr->shdn_reading = trc_ready(); - - ctrl_ptr->motor_temp = pm100_motor_temp(ctrl_ptr->pm100_ptr); - ctrl_ptr->inv_temp = pm100_max_inverter_temp(ctrl_ptr->pm100_ptr); - ctrl_ptr->max_temp = ctrl_ptr->motor_temp > ctrl_ptr->inv_temp - ? ctrl_ptr->motor_temp - : ctrl_ptr->inv_temp; - /* - LOG_INFO("Motor temp: %d Inverter temp: %d Max temp: %d\n", - - ctrl_ptr->motor_temp, - ctrl_ptr->inv_temp, - ctrl_ptr->max_temp); - */ - if (ctrl_fan_passed_on_threshold(ctrl_ptr)) - { - ctrl_ptr->fan_pwr = 1; - } - else if (ctrl_ptr->fan_pwr) - { - if (ctrl_fan_passed_off_threshold(ctrl_ptr)) - { - ctrl_ptr->fan_pwr = 0; - } - } - else - { - ctrl_ptr->fan_pwr = 0; - } - - ctrl_state_machine_tick(ctrl_ptr); - ctrl_update_canbc_states(ctrl_ptr); - - tx_thread_sleep(ctrl_ptr->config_ptr->schedule_ticks); - } -} - -/** - * @brief Checks the motor and inverter temperatures to determine if the - * fan should be turned on - * - * @param[in] ctrl_ptr Control service pointer - * - * @return True if the fan should be turned on - */ -bool ctrl_fan_passed_on_threshold(ctrl_context_t* ctrl_ptr) -{ - return ctrl_ptr->max_temp > ctrl_ptr->config_ptr->fan_on_threshold; -} - -/** - * @brief Checks the motor and inverter temperatures to determine if the - * fan should be turned off - * - * @param[in] ctrl_ptr Control service pointer - * - * @return True if the fan should be turned off - */ -bool ctrl_fan_passed_off_threshold(ctrl_context_t* ctrl_ptr) -{ - return ctrl_ptr->max_temp < ctrl_ptr->config_ptr->fan_off_threshold; -} - -/** - * @brief Runs one tick of the state machine for the control service - * - * @param[in] ctrl_ptr Control context - */ -void ctrl_state_machine_tick(ctrl_context_t* ctrl_ptr) -{ - // reduce typing... - dash_context_t* dash_ptr = ctrl_ptr->dash_ptr; - remote_ctrl_context_t* remote_ctrl_ptr = ctrl_ptr->remote_ctrl_ptr; - const config_ctrl_t* config_ptr = ctrl_ptr->config_ptr; - const uint16_t BPS_ON_THRESH = config_ptr->bps_on_threshold; - - ctrl_state_t next_state = ctrl_ptr->state; - -// In simulation mode, the TS and R2D buttons are controlled by the remote -// control, but the dash is still in effect -#ifdef VCU_SIMULATION_MODE - dash_ptr->tson_flag - = dash_ptr->tson_flag || remote_get_ts_on_reading(remote_ctrl_ptr); - dash_ptr->r2d_flag - = dash_ptr->r2d_flag || remote_get_r2d_reading(remote_ctrl_ptr); -#endif - - switch (ctrl_ptr->state) - { - - // wait for TS button to be held and released - // then begin activating the TS - case (CTRL_STATE_TS_BUTTON_WAIT): - { - if (dash_ptr->tson_flag) - { - dash_clear_buttons(dash_ptr); - - if (trc_ready()) - { - LOG_INFO("TSON pressed & SHDN closed\n"); - - trc_set_ts_on(GPIO_PIN_SET); - - next_state = CTRL_STATE_WAIT_NEG_AIR; - ctrl_ptr->neg_air_start = tx_time_get(); - } - } - else - { - ctrl_ptr->inverter_pwr - = false; // Turn off inverter if TS button is not pressed - } - - break; - } - - case (CTRL_STATE_WAIT_NEG_AIR): - { - if (tx_time_get() - >= ctrl_ptr->neg_air_start + TX_TIMER_TICKS_PER_SECOND / 4) - { - LOG_INFO("Neg AIR closed, turning on inverter\n"); - - ctrl_ptr->inverter_pwr = true; - - next_state = CTRL_STATE_PRECHARGE_WAIT; - ctrl_ptr->precharge_start = tx_time_get(); - } - - break; - } - - // TS is ready, can initiate pre-charge sequence - // TS on LED turns solid - case (CTRL_STATE_PRECHARGE_WAIT): - { - const uint32_t charge_time = tx_time_get() - ctrl_ptr->precharge_start; - - if (pm100_is_precharged(ctrl_ptr->pm100_ptr)) - { -#ifdef VCU_SIMULATION_MODE - next_state = CTRL_STATE_SIM_WAIT_TS_ON; -#else - next_state = CTRL_STATE_R2D_WAIT; -#endif - dash_clear_buttons(dash_ptr); - LOG_INFO("Precharge complete\n"); - } - else if (charge_time >= config_ptr->precharge_timeout_ticks) - { - ctrl_ptr->error |= CTRL_ERROR_PRECHARGE_TIMEOUT; - next_state = CTRL_STATE_TS_ACTIVATION_FAILURE; - LOG_ERROR("Precharge timeout reached\n"); - } - - break; - } - - // pre-charge is complete, wait for R2D signal - // also wait for brake to be fully pressed (if enabled) - case (CTRL_STATE_R2D_WAIT): - { - if (!trc_ready()) - { - LOG_ERROR("SHDN opened\n"); - next_state = CTRL_STATE_TS_ACTIVATION_FAILURE; - } - else if (dash_ptr->tson_flag) // TSON pressed, disable TS - { - dash_ptr->tson_flag = false; - - ctrl_ptr->inverter_pwr = false; // Turn off inverter - trc_set_ts_on(GPIO_PIN_RESET); // Turn off AIRs - -#ifdef VCU_SIMULATION_MODE - next_state = CTRL_STATE_SIM_WAIT_TS_OFF; -#else - next_state = CTRL_STATE_TS_BUTTON_WAIT; -#endif - } - else if (dash_ptr->r2d_flag) // R2D pressed - { -#ifndef VCU_SIMULATION_MODE - dash_ptr->r2d_flag = false; -#endif - - status_t result = ctrl_get_bps_reading(ctrl_ptr->tick_ptr, - remote_ctrl_ptr, - &ctrl_ptr->bps_reading); - - bool r2d = false; - - if (result == STATUS_OK) - { - r2d = (config_ptr->r2d_requires_brake) - ? (ctrl_ptr->bps_reading > BPS_ON_THRESH) - : 1; - - if (r2d) - { - dash_set_r2d_led_state(dash_ptr, GPIO_PIN_SET); - pm100_disable(ctrl_ptr->pm100_ptr); - rtds_activate(ctrl_ptr->rtds_config_ptr); - ctrl_ptr->pump_pwr = 1; - -#ifdef VCU_SIMULATION_MODE - next_state = CTRL_STATE_SIM_WAIT_R2D_ON; -#else - next_state = CTRL_STATE_TS_ON; -#endif - LOG_INFO("R2D active\n"); - } - } - else - { - LOG_ERROR("BPS reading failed\n"); - next_state = CTRL_STATE_TS_ACTIVATION_FAILURE; - } - } - break; - } - - // the TS is on - case (CTRL_STATE_TS_ON): - { - // read from the APPS - status_t pm100_status; - - status_t apps_status = ctrl_get_apps_reading(ctrl_ptr->tick_ptr, - remote_ctrl_ptr, - &ctrl_ptr->apps_reading); - status_t bps_status = ctrl_get_bps_reading(ctrl_ptr->tick_ptr, - remote_ctrl_ptr, - &ctrl_ptr->bps_reading); - - if (dash_ptr->r2d_flag) - { - dash_clear_buttons(dash_ptr); -#ifdef VCU_SIMULATION_MODE - next_state = CTRL_STATE_SIM_WAIT_R2D_OFF; -#else - next_state = CTRL_STATE_R2D_OFF; -#endif - } - else if (apps_status == STATUS_OK && bps_status == STATUS_OK) - { - // Check for brake + accel pedal pressed - if (ctrl_ptr->apps_reading - >= ctrl_ptr->config_ptr->apps_bps_high_threshold - && ctrl_ptr->bps_reading > BPS_ON_THRESH) - { - LOG_ERROR("BP and AP pressed\n"); - - if (tx_time_get() >= ctrl_ptr->apps_bps_start - + (TX_TIMER_TICKS_PER_SECOND / 3)) - { - LOG_ERROR("BP-AP fault\n"); - next_state = CTRL_STATE_APPS_BPS_FAULT; - } - } - else - { - ctrl_ptr->apps_bps_start = tx_time_get(); - } - - int16_t motor_speed = pm100_motor_speed(ctrl_ptr->pm100_ptr); - -#ifdef VCU_SIMULATION_MODE -#ifndef VCU_SIMULATION_ON_POWER - ctrl_ptr->torque_request - = remote_get_torque_reading(remote_ctrl_ptr); -#else - uint16_t power = remote_get_power_reading(remote_ctrl_ptr); - - uint16_t rad_s = 1; - - // this if to be removed - if (motor_speed < 10) - { - motor_speed = 10; - } - // rpm to rad/s - rad_s = (uint16_t) (motor_speed * 0.10472); - if (rad_s == 0) - rad_s = 1; - ctrl_ptr->torque_request = (uint16_t) (power / rad_s); - if (ctrl_ptr->torque_request > 1500) - ctrl_ptr->torque_request = 1500; -#endif -#else - ctrl_ptr->torque_request = torque_map_apply(&ctrl_ptr->torque_map, - ctrl_ptr->apps_reading, - motor_speed); -#endif - - LOG_INFO("ADC: %d, Torque: %d\n", - ctrl_ptr->apps_reading, - ctrl_ptr->torque_request); - - pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, - ctrl_ptr->torque_request); - - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - } - else - { - LOG_ERROR("APPS / BPS fault\n"); - next_state = CTRL_STATE_TS_RUN_FAULT; - } - - break; - } - - case CTRL_STATE_R2D_OFF: - { - ctrl_ptr->torque_request = 0; - status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); - ctrl_ptr->motor_torque_zero_start = tx_time_get(); - ctrl_ptr->pump_pwr = 0; - - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - else - { - next_state = CTRL_STATE_R2D_OFF_WAIT; - } - break; - } - - case CTRL_STATE_R2D_OFF_WAIT: - { - dash_set_r2d_led_state(dash_ptr, GPIO_PIN_RESET); - ctrl_ptr->torque_request = 0; - status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); - - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - else if (tx_time_get() >= ctrl_ptr->motor_torque_zero_start - + TX_TIMER_TICKS_PER_SECOND / 2) - { -#ifdef VCU_SIMULATION_MODE - next_state = CTRL_STATE_SIM_WAIT_R2D_OFF; -#else - next_state = CTRL_STATE_R2D_WAIT; -#endif - } - break; - } - - // activation or runtime failure - case (CTRL_STATE_TS_ACTIVATION_FAILURE): - case (CTRL_STATE_TS_RUN_FAULT): - { - LOG_ERROR("TS fault during activation or runtime\n"); - ctrl_handle_ts_fault(ctrl_ptr); - next_state = CTRL_STATE_TS_BUTTON_WAIT; - break; - } - - case (CTRL_STATE_SPIN): // Spin forever - { - break; - } - - // SCS fault - // this is recoverable, if the signal becomes plausible again - case (CTRL_STATE_APPS_SCS_FAULT): - { - ctrl_ptr->torque_request = 0; - status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); - - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - - if (ctrl_get_apps_reading(ctrl_ptr->tick_ptr, - remote_ctrl_ptr, - &ctrl_ptr->apps_reading) - == STATUS_OK) - { - next_state = CTRL_STATE_TS_ON; - } - - break; - } - - case (CTRL_STATE_APPS_BPS_FAULT): - { - ctrl_ptr->torque_request = 0; - status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); - - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - - status_t apps_status = ctrl_get_apps_reading(ctrl_ptr->tick_ptr, - remote_ctrl_ptr, - &ctrl_ptr->apps_reading); - status_t bps_status = ctrl_get_bps_reading(ctrl_ptr->tick_ptr, - remote_ctrl_ptr, - &ctrl_ptr->bps_reading); - - if (apps_status == STATUS_OK && bps_status == STATUS_OK) - { - if ((ctrl_ptr->apps_reading - < ctrl_ptr->config_ptr->apps_bps_low_threshold) - && (ctrl_ptr->bps_reading < BPS_ON_THRESH)) - { - next_state = CTRL_STATE_TS_ON; - } - } - else - { - next_state = CTRL_STATE_APPS_SCS_FAULT; - } - - break; - } - - // Needed when in simulation mode to avoid the TS being turned on again - case (CTRL_STATE_SIM_WAIT_TS_OFF): - { - ctrl_ptr->torque_request = 0; - status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - - if (!dash_ptr->tson_flag) - { - next_state = CTRL_STATE_TS_BUTTON_WAIT; - } - break; - } - - // Needed when in simulation mode to avoid the TS being turned off again - case (CTRL_STATE_SIM_WAIT_TS_ON): - { - ctrl_ptr->torque_request = 0; - status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - if (!dash_ptr->tson_flag) - { - next_state = CTRL_STATE_R2D_WAIT; - } - break; - } - - // Needed when in simulation mode to avoid the R2D being turned off again - case (CTRL_STATE_SIM_WAIT_R2D_ON): - { - ctrl_ptr->torque_request = 0; - status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - if (!dash_ptr->r2d_flag) - { - next_state = CTRL_STATE_TS_ON; - } - break; - } - - // Needed when in simulation mode to avoid the R2D being turned on again - case (CTRL_STATE_SIM_WAIT_R2D_OFF): - { - ctrl_ptr->torque_request = 0; - status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); - if (pm100_status != STATUS_OK) - { - next_state = CTRL_STATE_TS_RUN_FAULT; - } - if (!dash_ptr->r2d_flag) - { - dash_set_r2d_led_state(dash_ptr, GPIO_PIN_RESET); - next_state = CTRL_STATE_R2D_WAIT; - } - break; - } - - default: - break; - } - - ctrl_ptr->state = next_state; -} - -/** - * @brief Handles an initialisation or runtime fault of the TS and shuts - * down the service - * - * @param[in] ctrl_ptr Control context - */ -void ctrl_handle_ts_fault(ctrl_context_t* ctrl_ptr) -{ - dash_context_t* dash_ptr = ctrl_ptr->dash_ptr; - const config_ctrl_t* config_ptr = ctrl_ptr->config_ptr; - - // pm100_lvs_off(ctrl_ptr->pm100_ptr); - ctrl_ptr->inverter_pwr = false; - ctrl_ptr->pump_pwr = false; - ctrl_ptr->fan_pwr = false; - - trc_set_ts_on(GPIO_PIN_RESET); - dash_blink_ts_on_led(dash_ptr, config_ptr->error_led_toggle_ticks); - ctrl_update_canbc_states(ctrl_ptr); -} - -/** - * @brief Updates the CAN broadcast states relevant to the control service - * - * @param[in] ctrl_ptr - */ -void ctrl_update_canbc_states(ctrl_context_t* ctrl_ptr) -{ - canbc_states_t* states = canbc_lock_state(ctrl_ptr->canbc_ptr, TX_NO_WAIT); - - if (states != NULL) - { - // TODO: add ready to drive state? - states->sensors.vcu_sagl = ctrl_ptr->sagl_reading; - states->sensors.vcu_torque_request = ctrl_ptr->torque_request; - states->temps.vcu_max_temp = (int8_t) ctrl_ptr->max_temp; - states->state.vcu_ctrl_state = (uint8_t) ctrl_ptr->state; - states->state.vcu_drs_active = ctrl_ptr->shdn_reading; - states->errors.vcu_ctrl_error = ctrl_ptr->error; - states->pdm.inverter = ctrl_ptr->inverter_pwr; - states->pdm.pump = ctrl_ptr->pump_pwr; - states->pdm.fan = ctrl_ptr->fan_pwr; - canbc_unlock_state(ctrl_ptr->canbc_ptr); - } -} - -status_t ctrl_get_apps_reading(tick_context_t* tick_ptr, - remote_ctrl_context_t* remote_ctrl_ptr, - uint16_t* result) -{ -#ifdef VCU_SIMULATION_MODE - return remote_get_apps_reading(remote_ctrl_ptr, result); -#else - return tick_get_apps_reading(tick_ptr, result); -#endif -} -status_t ctrl_get_bps_reading(tick_context_t* tick_ptr, - remote_ctrl_context_t* remote_ctrl_ptr, - uint16_t* result) -{ -#ifdef VCU_SIMULATION_MODE - return remote_get_bps_reading(remote_ctrl_ptr, result); -#else - return tick_get_bps_reading(tick_ptr, result); -#endif -} \ No newline at end of file +/***************************************************************************** + * @file driver_control.c + * @author Tim Brewis (@t-bre, tab1g19@soton.ac.uk) + * @author Toby Godfrey (@_tg03, tmag1g21@soton.ac.uk) + * @brief Driver control + ****************************************************************************/ + +#include "ctrl.h" +#include "clip_to_range.h" + +#include + +#include "mode_switch_values.h" +#include "rtds.h" +#include "trc.h" + +/* + * internal function prototypes + */ +void ctrl_thread_entry(ULONG input); +void ctrl_state_machine_tick(ctrl_context_t *ctrl_ptr); +void ctrl_update_canbc_states(ctrl_context_t *ctrl_ptr); + +/** + * @brief Initialises control service + * + * @param[in] ctrl_ptr Control context + * @param[in] dash_ptr Dash context + * @param[in] canbc_ptr CANBC context + * @param[in] pm100_ptr PM100 context + * @param[in] stack_pool_ptr Byte pool to allocate thread stack from + * @param[in] config_ptr Configuration + * @param[in] apps_config_ptr APPS configuration + * @param[in] bps_config_ptr BPS configuration + * @param[in] rtds_config_ptr RTDS configuration + * @param[in] torque_map_config_ptr Torque map configuration + */ +status_t ctrl_init(ctrl_context_t *ctrl_ptr, + dash_context_t *dash_ptr, + pm100_context_t *pm100_ptr, + tick_context_t *tick_ptr, + remote_ctrl_context_t *remote_ctrl_ptr, + canbc_context_t *canbc_ptr, + fans_context_t *fans_ptr, + wheelspeed_context_t *wheelspeed_ptr, + TX_BYTE_POOL *stack_pool_ptr, + const config_ctrl_t *config_ptr, + const config_rtds_t *rtds_config_ptr, + const config_torque_map_t *torque_map_config_ptr, + const config_torque_limiters_t *torque_limiters_config_ptr) +{ + ctrl_ptr->state = CTRL_STATE_TS_BUTTON_WAIT; + ctrl_ptr->current_mode = CTRL_MODE_ENDURANCE; + ctrl_ptr->requested_mode = CTRL_MODE_ENDURANCE; + ctrl_ptr->dash_ptr = dash_ptr; + ctrl_ptr->pm100_ptr = pm100_ptr; + ctrl_ptr->tick_ptr = tick_ptr; + ctrl_ptr->canbc_ptr = canbc_ptr; + ctrl_ptr->config_ptr = config_ptr; + ctrl_ptr->rtds_config_ptr = rtds_config_ptr; + ctrl_ptr->fans_ptr = fans_ptr; + ctrl_ptr->wheelspeed_ptr = wheelspeed_ptr; + ctrl_ptr->error = CTRL_ERROR_NONE; + ctrl_ptr->apps_reading = 0; + ctrl_ptr->bps_reading = 0; + ctrl_ptr->sagl_reading = 0; + ctrl_ptr->current_reading = 0; + ctrl_ptr->motor_speed_reading = 0; + ctrl_ptr->front_wheel_rpm = 0; + ctrl_ptr->torque_request = 0; + ctrl_ptr->shdn_reading = 0; + ctrl_ptr->precharge_start = 0; + ctrl_ptr->inverter_pwr = false; + ctrl_ptr->pump_pwr = false; + ctrl_ptr->remote_ctrl_ptr = remote_ctrl_ptr; + + // create the thread + void *stack_ptr = NULL; + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); + + if (tx_status == TX_SUCCESS) + { + tx_status = + tx_thread_create(&ctrl_ptr->thread, (CHAR *)config_ptr->thread.name, + ctrl_thread_entry, (ULONG)ctrl_ptr, stack_ptr, + config_ptr->thread.stack_size, config_ptr->thread.priority, + config_ptr->thread.priority, TX_NO_TIME_SLICE, TX_AUTO_START); + } + + status_t status = (tx_status == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; + + // initialise the torque map + if (status == STATUS_OK) + { + status = torque_map_init(&ctrl_ptr->torque_map, torque_map_config_ptr); + } + + // initialise the torque limiters (slip control, etc.) + if (status == STATUS_OK) + { + torque_limiters_init(&ctrl_ptr->torque_limiters, torque_limiters_config_ptr); + } + + // make sure TS is disabled + trc_set_ts_on(GPIO_PIN_RESET); + + // check all ok before starting + if (status != STATUS_OK) + { + tx_thread_terminate(&ctrl_ptr->thread); + ctrl_ptr->error |= CTRL_ERROR_INIT; + } + + // send initial state update + ctrl_update_canbc_states(ctrl_ptr); + + // Set RTDS tick counters to zero + rtds_pulse_init(&ctrl_ptr->rtds_pulse_ctx, rtds_config_ptr); + + return status; +} + +/** + * @brief Control thread entry function + * + * @param[in] input Control context + */ +void ctrl_thread_entry(ULONG input) +{ + ctrl_context_t *ctrl_ptr = (ctrl_context_t *)input; + + while (1) + { + dash_update_buttons(ctrl_ptr->dash_ptr); + + ctrl_ptr->shdn_reading = trc_ready(); + + tick_get_sagl_reading(ctrl_ptr->tick_ptr, &ctrl_ptr->sagl_reading); + tick_get_current_reading(ctrl_ptr->tick_ptr, &ctrl_ptr->current_reading); + + uint16_t mode_adc_reading; + if (tick_get_mode_adc_reading(ctrl_ptr->tick_ptr, &mode_adc_reading) == STATUS_OK) + { + ctrl_ptr->requested_mode = convert_mode_adc_to_discrete(mode_adc_reading); + } + + ctrl_ptr->motor_temp = pm100_motor_temp(ctrl_ptr->pm100_ptr); + ctrl_ptr->inv_temp = pm100_max_inverter_temp(ctrl_ptr->pm100_ptr); + ctrl_ptr->motor_speed_reading = pm100_motor_speed(ctrl_ptr->pm100_ptr); + ctrl_ptr->electrical_power_w = pm100_electrical_power_w(ctrl_ptr->pm100_ptr); + + wheelspeed_reading_t wheelspeed_reading; + if (wheelspeed_get_speeds(ctrl_ptr->wheelspeed_ptr, &wheelspeed_reading) == STATUS_OK) + { + ctrl_ptr->front_wheel_rpm = + (wheelspeed_reading.fl_rpm > wheelspeed_reading.fr_rpm) ? + wheelspeed_reading.fl_rpm : + wheelspeed_reading.fr_rpm; + } + + ctrl_ptr->max_temp = ctrl_ptr->motor_temp > ctrl_ptr->inv_temp ? + ctrl_ptr->motor_temp : + ctrl_ptr->inv_temp; + /* + LOG_INFO("Motor temp: %d Inverter temp: %d Max temp: %d\n", + + ctrl_ptr->motor_temp, + ctrl_ptr->inv_temp, + ctrl_ptr->max_temp); + */ + fans_update_thermal(ctrl_ptr->fans_ptr, ctrl_ptr->max_temp); + + ctrl_state_machine_tick(ctrl_ptr); + + bool rtds_pulse_enable = (ctrl_ptr->state == CTRL_STATE_TS_ON) && + (ctrl_ptr->current_mode == CTRL_MODE_REVERSE); + rtds_pulse_tick(&ctrl_ptr->rtds_pulse_ctx, rtds_pulse_enable); + + ctrl_update_canbc_states(ctrl_ptr); + + tx_thread_sleep(ctrl_ptr->config_ptr->schedule_ticks); + } +} + +/** + * @brief Samples the physical dash buttons and remote control overrides for this tick + * + * @param[in] ctrl_ptr Control context + * @param[out] tson_pressed TS input for this tick (dash button + remote control) + * @param[out] r2d_pressed R2D input for this tick (dash button + remote control) + */ +static void ctrl_sample_driver_inputs(ctrl_context_t *ctrl_ptr, bool *tson_pressed, bool *r2d_pressed) +{ + *tson_pressed = ctrl_ptr->dash_ptr->tson_flag; + *r2d_pressed = ctrl_ptr->dash_ptr->r2d_flag; + + if (ctrl_ptr->current_mode == CTRL_MODE_REMOTE_CTRL) + { + *tson_pressed = *tson_pressed || remote_get_ts_on_pressed(ctrl_ptr->remote_ctrl_ptr); + *r2d_pressed = *r2d_pressed || remote_get_r2d_pressed(ctrl_ptr->remote_ctrl_ptr); + } +} + +/** + * @brief Zeroes the torque request and commands the pm100 to 0 + * + * @param[in] ctrl_ptr Control context + * + * @return False if the pm100 request itself failed (caller should + * escalate to CTRL_STATE_TS_RUN_FAULT) + */ +static bool ctrl_fault_zero_torque_ok(ctrl_context_t *ctrl_ptr) +{ + ctrl_ptr->torque_request = 0; + return pm100_request_torque(ctrl_ptr->pm100_ptr, 0) == STATUS_OK; +} + +/** + * @brief Re-reads APPS and BPS into ctrl_ptr + * + * @param[in] ctrl_ptr Control context + * + * @return True if both readings succeeded + */ +static bool ctrl_refresh_apps_bps_ok(ctrl_context_t *ctrl_ptr) +{ + status_t apps_status = + tick_get_apps_reading(ctrl_ptr->tick_ptr, &ctrl_ptr->apps_reading); + status_t bps_status = tick_get_bps_reading(ctrl_ptr->tick_ptr, &ctrl_ptr->bps_reading); + + return apps_status == STATUS_OK && bps_status == STATUS_OK; +} + +/** + * @brief Clears the fault/error state if the driver has pressed TS + * + * @param[in] ctrl_ptr Control context + * @param[in] tson_pressed TS input for this tick + * + * @return True if the fault was acknowledged and cleared (caller + * should return CTRL_STATE_TS_BUTTON_WAIT) + */ +static bool ctrl_try_driver_fault_ack(ctrl_context_t *ctrl_ptr, bool tson_pressed) +{ + if (!tson_pressed) + { + return false; + } + + ctrl_ptr->error = CTRL_ERROR_NONE; + pm100_clear_error(ctrl_ptr->pm100_ptr); + tick_clear_apps_scs_error(ctrl_ptr->tick_ptr); + + return true; +} + +/** + * @brief wait for TS button to be held and released + * then begin activating the TS + * + * @param ctrl_ptr + * @param tson_pressed TS input for this tick + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_ts_button_wait(ctrl_context_t *ctrl_ptr, bool tson_pressed) +{ + ctrl_ptr->current_mode = ctrl_ptr->requested_mode; + dash_set_r2d_led_state(ctrl_ptr->dash_ptr, GPIO_PIN_SET); + if (tson_pressed) + { + if (trc_ready()) + { + LOG_INFO("TSON pressed & SHDN closed\n"); + + trc_set_ts_on(GPIO_PIN_SET); + + ctrl_ptr->neg_air_start = tx_time_get(); + return CTRL_STATE_WAIT_NEG_AIR; + } + } + else if (ctrl_ptr->current_mode == CTRL_MODE_INVERTER_PROG) + { + ctrl_ptr->inverter_pwr = true; + } + else + { + // Turn off inverter if TS button is not pressed + ctrl_ptr->inverter_pwr = false; + } + return CTRL_STATE_TS_BUTTON_WAIT; +} + +/** + * @brief Wait for AIRs to close + * + * @param ctrl_ptr + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_wait_neg_air(ctrl_context_t *ctrl_ptr) +{ + if (tx_time_get() >= ctrl_ptr->neg_air_start + TX_TIMER_TICKS_PER_SECOND / 4) + { + LOG_INFO("Neg AIR closed, turning on inverter\n"); + ctrl_ptr->inverter_pwr = true; + ctrl_ptr->precharge_start = tx_time_get(); + return CTRL_STATE_PRECHARGE_WAIT; + } + return CTRL_STATE_WAIT_NEG_AIR; +} + +/** + * @brief TS is ready, can initiate pre-charge sequence + * TS on LED turns solid + * + * @param ctrl_ptr + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_precharge_wait(ctrl_context_t *ctrl_ptr) +{ + const uint32_t charge_time = tx_time_get() - ctrl_ptr->precharge_start; + if (pm100_is_precharged(ctrl_ptr->pm100_ptr)) + { + LOG_INFO("Precharge complete\n"); + return CTRL_STATE_R2D_WAIT; + } + else if (charge_time >= ctrl_ptr->config_ptr->precharge_timeout_ticks) + { + ctrl_ptr->error |= CTRL_ERROR_PRECHARGE_TIMEOUT; + LOG_ERROR("Precharge timeout reached\n"); + return CTRL_STATE_TS_ACTIVATION_FAILURE; + } + return CTRL_STATE_PRECHARGE_WAIT; +} + +/** + * @brief pre-charge is complete, wait for R2D signal + * also wait for brake to be fully pressed (if enabled) + * + * @param ctrl_ptr + * @param tson_pressed TS input for this tick + * @param r2d_pressed R2D input for this tick + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_r2d_wait(ctrl_context_t *ctrl_ptr, bool tson_pressed, bool r2d_pressed) +{ + if (!trc_ready()) + { + LOG_ERROR("SHDN opened\n"); + return CTRL_STATE_TS_ACTIVATION_FAILURE; + } + + dash_set_r2d_led_state(ctrl_ptr->dash_ptr, GPIO_PIN_SET); + ctrl_ptr->current_mode = ctrl_ptr->requested_mode; + + // Stay in R2D_Wait on an unknown mode (e.g. undefined mode or inverter programming) + if (ctrl_ptr->current_mode == CTRL_MODE_UNKNOWN || ctrl_ptr->current_mode > CTRL_MODE_REMOTE_CTRL) + { + return CTRL_STATE_R2D_WAIT; + } + + if (tson_pressed) + { + ctrl_ptr->inverter_pwr = false; // Turn off inverter + trc_set_ts_on(GPIO_PIN_RESET); // Turn off AIRs + + return CTRL_STATE_TS_BUTTON_WAIT; + } + + if (r2d_pressed) + { + bool r2d = true; + + if (ctrl_ptr->current_mode != CTRL_MODE_REMOTE_CTRL) + { + status_t result = + tick_get_bps_reading(ctrl_ptr->tick_ptr, &ctrl_ptr->bps_reading); + if (result != STATUS_OK) + { + LOG_ERROR("BPS reading failed\n"); + return CTRL_STATE_TS_ACTIVATION_FAILURE; + } + + r2d = (ctrl_ptr->config_ptr->r2d_requires_brake) ? + (ctrl_ptr->bps_reading > ctrl_ptr->config_ptr->bps_on_threshold) : + 1; + } + + if (r2d) + { + dash_set_r2d_led_state(ctrl_ptr->dash_ptr, GPIO_PIN_RESET); + pm100_disable(ctrl_ptr->pm100_ptr); + rtds_activate(ctrl_ptr->rtds_config_ptr); + ctrl_ptr->pump_pwr = 1; + ctrl_ptr->apps_bps_start = tx_time_get(); + + uint16_t torque_cap = (ctrl_ptr->current_mode == CTRL_MODE_CRAWL || + ctrl_ptr->current_mode == CTRL_MODE_REVERSE) ? + ctrl_ptr->config_ptr->crawl_max_torque : + (ctrl_ptr->current_mode == CTRL_MODE_ENDURANCE) ? + ctrl_ptr->config_ptr->endurance_max_torque : + ctrl_ptr->config_ptr->hard_max_torque; + + torque_cap = clip_to_range(torque_cap, 0, ctrl_ptr->config_ptr->hard_max_torque); + + ctrl_ptr->pm100_ptr->reverse_mode_dangerous = + ctrl_ptr->current_mode == CTRL_MODE_REVERSE; + if (ctrl_ptr->pm100_ptr->reverse_mode_dangerous) + { + LOG_WARN("Reverse active"); + } + + torque_map_set_output_max(&ctrl_ptr->torque_map, torque_cap); + LOG_INFO("Torque cap (nm x10)%d\n", ctrl_ptr->torque_map.output_max); + + LOG_INFO("R2D active\n"); + return CTRL_STATE_TS_ON; + } + } + + return CTRL_STATE_R2D_WAIT; +} + +/** + * @brief the TS is on + * + * @param ctrl_ptr + * @param r2d_pressed R2D input for this tick + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_ts_on(ctrl_context_t *ctrl_ptr, bool r2d_pressed) +{ + status_t pm100_status; + + if (r2d_pressed) + { + return CTRL_STATE_R2D_OFF; + } + + if (ctrl_ptr->current_mode != CTRL_MODE_REMOTE_CTRL) + { + // read from the APPS + if (!ctrl_refresh_apps_bps_ok(ctrl_ptr)) + { + LOG_ERROR("APPS / BPS fault\n"); + return CTRL_STATE_APPS_SCS_FAULT; + } + + // Check for brake + accel pedal pressed + if (ctrl_ptr->apps_reading >= ctrl_ptr->config_ptr->apps_bps_high_threshold && + ctrl_ptr->bps_reading > ctrl_ptr->config_ptr->apps_bps_fault_bps_threshold) + { + LOG_ERROR("BP and AP pressed\n"); + + if (tx_time_get() >= ctrl_ptr->apps_bps_start + (TX_TIMER_TICKS_PER_SECOND / 50)) + { + LOG_ERROR("BP-AP fault\n"); + ctrl_ptr->apps_bps_fault_start = tx_time_get(); + return CTRL_STATE_APPS_BPS_FAULT; + } + } + else + { + ctrl_ptr->apps_bps_start = tx_time_get(); + } + + ctrl_ptr->torque_request = + torque_map_apply(&ctrl_ptr->torque_map, ctrl_ptr->apps_reading); + } + else + { + ctrl_ptr->torque_request = remote_get_torque_reading(ctrl_ptr->remote_ctrl_ptr); + } + + LOG_INFO("ADC: %d, Torque: %d\n", ctrl_ptr->apps_reading, ctrl_ptr->torque_request); + + if (ctrl_ptr->torque_request == 0) + { + // off-throttle - reset integral part + torque_limiters_reset(&ctrl_ptr->torque_limiters); + } + else + { + bool slip_enabled = (ctrl_ptr->current_mode == CTRL_MODE_TORQUE_CTRL); + ctrl_ptr->torque_request = + torque_limiters_apply(&ctrl_ptr->torque_limiters, ctrl_ptr->torque_request, + slip_enabled, ctrl_ptr->motor_speed_reading, + ctrl_ptr->front_wheel_rpm, ctrl_ptr->electrical_power_w); + } + + ctrl_ptr->torque_request = + clip_to_range(ctrl_ptr->torque_request, 0, ctrl_ptr->config_ptr->hard_max_torque); + + pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, ctrl_ptr->torque_request); + + if (pm100_status != STATUS_OK) + { + return CTRL_STATE_TS_RUN_FAULT; + } + + return CTRL_STATE_TS_ON; +} + +/** + * @brief R2D off + * + * @param ctrl_ptr + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_r2d_off(ctrl_context_t *ctrl_ptr) +{ + ctrl_ptr->torque_request = 0; + status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); + ctrl_ptr->motor_torque_zero_start = tx_time_get(); + ctrl_ptr->pump_pwr = 0; + + if (pm100_status != STATUS_OK) + { + return CTRL_STATE_TS_RUN_FAULT; + } + + return CTRL_STATE_R2D_OFF_WAIT; +} + +/** + * @brief Wait for R2D to turn back on + * + * @param ctrl_ptr + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_r2d_off_wait(ctrl_context_t *ctrl_ptr) +{ + dash_set_r2d_led_state(ctrl_ptr->dash_ptr, GPIO_PIN_SET); + ctrl_ptr->torque_request = 0; + status_t pm100_status = pm100_request_torque(ctrl_ptr->pm100_ptr, 0); + + if (pm100_status != STATUS_OK) + { + return CTRL_STATE_TS_RUN_FAULT; + } + + if (tx_time_get() >= ctrl_ptr->motor_torque_zero_start + TX_TIMER_TICKS_PER_SECOND / 2) + { + return CTRL_STATE_R2D_WAIT; + } + + return CTRL_STATE_R2D_OFF_WAIT; +} + +/** + * @brief SCS fault + * this is recoverable, if the signal becomes plausible again + * + * @param ctrl_ptr + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_apps_scs_fault(ctrl_context_t *ctrl_ptr, bool tson_pressed) +{ + if (!ctrl_fault_zero_torque_ok(ctrl_ptr)) + { + return CTRL_STATE_TS_RUN_FAULT; + } + + if (ctrl_refresh_apps_bps_ok(ctrl_ptr)) + { + return CTRL_STATE_TS_ON; + } + + if (ctrl_try_driver_fault_ack(ctrl_ptr, tson_pressed)) + { + return CTRL_STATE_TS_BUTTON_WAIT; + } + + return CTRL_STATE_APPS_SCS_FAULT; +} + +/** + * @brief + * + * @param ctrl_ptr + * @param tson_pressed TS input for this tick + * @return ctrl_state_t next state + */ +static ctrl_state_t ctrl_proc_apps_bps_fault(ctrl_context_t *ctrl_ptr, bool tson_pressed) +{ + if (!ctrl_fault_zero_torque_ok(ctrl_ptr)) + { + return CTRL_STATE_TS_RUN_FAULT; + } + + if (ctrl_refresh_apps_bps_ok(ctrl_ptr)) + { + if ((ctrl_ptr->apps_reading < ctrl_ptr->config_ptr->apps_bps_low_threshold) && + ctrl_ptr->bps_reading <= ctrl_ptr->config_ptr->apps_bps_fault_bps_threshold) + { + if (tx_time_get() > ctrl_ptr->apps_bps_fault_start + TX_TIMER_TICKS_PER_SECOND / 10) + { + return CTRL_STATE_TS_ON; + } + } + else + { + ctrl_ptr->apps_bps_fault_start = tx_time_get(); + } + } + + if (ctrl_try_driver_fault_ack(ctrl_ptr, tson_pressed)) + { + return CTRL_STATE_TS_BUTTON_WAIT; + } + + return CTRL_STATE_APPS_BPS_FAULT; +} + +/** + * @brief Handles an initialisation or runtime fault of the TS and shuts + * down the service + * + * @param[in] ctrl_ptr Control context + * @param[in] tson_pressed TS input for this tick + */ +static ctrl_state_t ctrl_handle_ts_fault(ctrl_context_t *ctrl_ptr, bool tson_pressed) +{ + + dash_context_t *dash_ptr = ctrl_ptr->dash_ptr; + const config_ctrl_t *config_ptr = ctrl_ptr->config_ptr; + + pm100_lvs_off(ctrl_ptr->pm100_ptr); + + // Don't turn off the inverter while the motor could be still spinning (or + // you might blow up a PCB like stag-11) ctrl_ptr->inverter_pwr = false; + + ctrl_ptr->torque_request = 0; + pm100_request_torque(ctrl_ptr->pm100_ptr, 0); + ctrl_ptr->pump_pwr = false; + ctrl_ptr->fans_ptr->fan_thermal_pwr = false; + + trc_set_ts_on(GPIO_PIN_RESET); + dash_blink_ts_on_led(dash_ptr, config_ptr->error_led_toggle_ticks); + dash_set_r2d_led_state(ctrl_ptr->dash_ptr, GPIO_PIN_SET); + + if (ctrl_try_driver_fault_ack(ctrl_ptr, tson_pressed)) + { + return CTRL_STATE_TS_BUTTON_WAIT; + } + return CTRL_STATE_TS_RUN_FAULT; +} + +/** + * @brief Runs one tick of the state machine for the control service + * + * @param[in] ctrl_ptr Control context + */ +void ctrl_state_machine_tick(ctrl_context_t *ctrl_ptr) +{ + ctrl_state_t next_state = ctrl_ptr->state; + bool tson_pressed; + bool r2d_pressed; + ctrl_sample_driver_inputs(ctrl_ptr, &tson_pressed, &r2d_pressed); + + switch (ctrl_ptr->state) + { + case CTRL_STATE_TS_BUTTON_WAIT: + { + next_state = ctrl_proc_ts_button_wait(ctrl_ptr, tson_pressed); + break; + } + case CTRL_STATE_WAIT_NEG_AIR: + { + next_state = ctrl_proc_wait_neg_air(ctrl_ptr); + break; + } + case CTRL_STATE_PRECHARGE_WAIT: + { + next_state = ctrl_proc_precharge_wait(ctrl_ptr); + break; + } + case CTRL_STATE_R2D_WAIT: + { + next_state = ctrl_proc_r2d_wait(ctrl_ptr, tson_pressed, r2d_pressed); + break; + } + case CTRL_STATE_TS_ON: + { + next_state = ctrl_proc_ts_on(ctrl_ptr, r2d_pressed); + break; + } + case CTRL_STATE_R2D_OFF: + { + next_state = ctrl_proc_r2d_off(ctrl_ptr); + break; + } + case CTRL_STATE_R2D_OFF_WAIT: + { + next_state = ctrl_proc_r2d_off_wait(ctrl_ptr); + break; + } + // activation or runtime failure + case CTRL_STATE_TS_ACTIVATION_FAILURE: + case CTRL_STATE_TS_RUN_FAULT: + { + LOG_ERROR("TS fault during activation or runtime\n"); + next_state = ctrl_handle_ts_fault(ctrl_ptr, tson_pressed); + break; + } + case CTRL_STATE_SPIN: + { + // Spin forever + break; + } + case CTRL_STATE_APPS_SCS_FAULT: + { + next_state = ctrl_proc_apps_scs_fault(ctrl_ptr, tson_pressed); + break; + } + case CTRL_STATE_APPS_BPS_FAULT: + { + next_state = ctrl_proc_apps_bps_fault(ctrl_ptr, tson_pressed); + break; + } + default: break; + } + + if (next_state == CTRL_STATE_TS_ON && ctrl_ptr->state != CTRL_STATE_TS_ON) + { + // reset torque limiter integrator state on every entry to driving, + // including fault-recovery paths that skip ctrl_proc_r2d_wait + torque_limiters_reset(&ctrl_ptr->torque_limiters); + } + + dash_clear_buttons(ctrl_ptr->dash_ptr); + + ctrl_ptr->state = next_state; +} + +/** + * @brief Updates the CAN broadcast states relevant to the control service + * + * @param[in] ctrl_ptr + */ +void ctrl_update_canbc_states(ctrl_context_t *ctrl_ptr) +{ + canbc_states_t *states = canbc_lock_state(ctrl_ptr->canbc_ptr, TX_NO_WAIT); + + if (states != NULL) + { + states->state.vcu_r2_d = (ctrl_ptr->state == CTRL_STATE_TS_ON); + states->sensors.vcu_sagl = ctrl_ptr->sagl_reading; + states->sensors.vcu_torque_request = ctrl_ptr->torque_request; + states->temps.vcu_max_temp = ctrl_ptr->max_temp; + states->state.vcu_ctrl_state = (uint8_t)ctrl_ptr->state; + states->state.vcu_requested_mode = (uint8_t)ctrl_ptr->requested_mode; + states->state.vcu_current_mode = (uint8_t)ctrl_ptr->current_mode; + states->state.vcu_drs_active = ctrl_ptr->shdn_reading; + states->errors.vcu_ctrl_error = ctrl_ptr->error; + states->errors.vcu_pm100_error = ctrl_ptr->pm100_ptr->error; + states->pdm.inverter = ctrl_ptr->inverter_pwr; + states->pdm.pump = ctrl_ptr->pump_pwr || ctrl_ptr->fans_ptr->fan_switch_status; + states->pdm.fan = fans_output_pwr(ctrl_ptr->fans_ptr); + canbc_unlock_state(ctrl_ptr->canbc_ptr); + } +} diff --git a/src/SUFST/Src/Services/dash.c b/src/SUFST/Src/Services/dash.c index e72b4d64..1e779e9d 100644 --- a/src/SUFST/Src/Services/dash.c +++ b/src/SUFST/Src/Services/dash.c @@ -1,5 +1,7 @@ #include "dash.h" +#include "io.h" + /* * internal functions */ @@ -15,9 +17,7 @@ static status_t input_wait(input_context_t *input_ptr); * @param[in] stack_pool_ptr Byte pool to allocate thread stack from * @param[in] config_ptr Dash configuration */ -status_t dash_init(dash_context_t *dash_ptr, - TX_BYTE_POOL *stack_pool_ptr, - const config_dash_t *config_ptr) +status_t dash_init(dash_context_t *dash_ptr, TX_BYTE_POOL *stack_pool_ptr, const config_dash_t *config_ptr) { status_t status = STATUS_OK; @@ -25,45 +25,38 @@ status_t dash_init(dash_context_t *dash_ptr, dash_ptr->r2d_flag = false; dash_ptr->tson_flag = false; - dash_ptr->r2d = (input_context_t){ - .port = R2D_BTN_GPIO_Port, - .pin = R2D_BTN_Pin, - .active_state = true, - .last_state = false, - .require_release = true, - .active_start = 0, - .required_ticks = dash_ptr->config_ptr->btn_active_ticks, - .sample_ticks = dash_ptr->config_ptr->btn_sample_ticks}; - - dash_ptr->tson = (input_context_t){ - .port = TS_ON_BTN_GPIO_Port, - .pin = TS_ON_BTN_Pin, - .active_state = true, - .last_state = false, - .require_release = true, - .active_start = 0, - .required_ticks = dash_ptr->config_ptr->btn_active_ticks, - .sample_ticks = dash_ptr->config_ptr->btn_sample_ticks}; + dash_ptr->r2d = + (input_context_t){ .port = R2D_BTN_GPIO_Port, + .pin = R2D_BTN_Pin, + .active_state = true, + .last_state = false, + .require_release = true, + .active_start = 0, + .required_ticks = dash_ptr->config_ptr->btn_active_ticks, + .sample_ticks = dash_ptr->config_ptr->btn_sample_ticks }; + + dash_ptr->tson = + (input_context_t){ .port = TS_ON_BTN_GPIO_Port, + .pin = TS_ON_BTN_Pin, + .active_state = true, + .last_state = false, + .require_release = true, + .active_start = 0, + .required_ticks = dash_ptr->config_ptr->btn_active_ticks, + .sample_ticks = dash_ptr->config_ptr->btn_sample_ticks }; // create the thread void *stack_ptr = NULL; - UINT tx_status = tx_byte_allocate(stack_pool_ptr, - &stack_ptr, - config_ptr->thread.stack_size, - TX_NO_WAIT); + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); if (tx_status == TX_SUCCESS) { - tx_status = tx_thread_create(&dash_ptr->thread, - (CHAR *)config_ptr->thread.name, - dash_thread_entry, - (ULONG)dash_ptr, - stack_ptr, - config_ptr->thread.stack_size, - config_ptr->thread.priority, - config_ptr->thread.priority, - TX_NO_TIME_SLICE, - TX_AUTO_START); + tx_status = + tx_thread_create(&dash_ptr->thread, (CHAR *)config_ptr->thread.name, + dash_thread_entry, (ULONG)dash_ptr, stack_ptr, + config_ptr->thread.stack_size, config_ptr->thread.priority, + config_ptr->thread.priority, TX_NO_TIME_SLICE, TX_AUTO_START); } if (tx_status != TX_SUCCESS) @@ -72,13 +65,9 @@ status_t dash_init(dash_context_t *dash_ptr, } // create timer for toggling TS on LED - tx_status = tx_timer_create(&dash_ptr->ts_on_toggle_timer, - NULL, - toggle_ts_on_callback, - (ULONG)dash_ptr, - TX_WAIT_FOREVER, - TX_WAIT_FOREVER, - TX_NO_ACTIVATE); + tx_status = tx_timer_create(&dash_ptr->ts_on_toggle_timer, NULL, + toggle_ts_on_callback, (ULONG)dash_ptr, + TX_WAIT_FOREVER, TX_WAIT_FOREVER, TX_NO_ACTIVATE); if (tx_status != TX_SUCCESS) { @@ -87,10 +76,13 @@ status_t dash_init(dash_context_t *dash_ptr, // CubeMX will auto-generate code which sets initial pin states // however for ease of editing / readability it's done again here - HAL_GPIO_WritePin(R2D_LED_GPIO_Port, R2D_LED_Pin, GPIO_PIN_RESET); - HAL_GPIO_WritePin(TS_ON_LED_GPIO_Port, TS_ON_LED_Pin, GPIO_PIN_RESET); - HAL_GPIO_WritePin(DRS_LED_GPIO_Port, DRS_LED_Pin, GPIO_PIN_RESET); - HAL_GPIO_WritePin(VC_LEDS_GPIO_Port, VC_LEDS_Pin, GPIO_PIN_RESET); + + /* LEDs are active-low; set outputs to 'high' (external off) + to ensure LEDs are off at init. */ + VCU_Output_High(R2D_LED_GPIO_Port, R2D_LED_Pin); + VCU_Output_High(TS_ON_LED_GPIO_Port, TS_ON_LED_Pin); + // VCU_Output_High(DRS_LED_GPIO_Port, DRS_LED_Pin); + VCU_Output_High(VC_LEDS_GPIO_Port, VC_LEDS_Pin); return status; } @@ -102,7 +94,7 @@ status_t dash_init(dash_context_t *dash_ptr, */ void dash_thread_entry(ULONG input) { - dash_context_t *dash_ptr = (dash_context_t *)input; + const dash_context_t *dash_ptr = (dash_context_t *)input; // see 'visible check' rule if (dash_ptr->config_ptr->vc_run_check) @@ -122,11 +114,11 @@ void dash_thread_entry(ULONG input) */ void run_visual_check(uint32_t ticks) { - HAL_GPIO_WritePin(VC_LEDS_GPIO_Port, VC_LEDS_Pin, GPIO_PIN_SET); + VCU_Output_Low(VC_LEDS_GPIO_Port, VC_LEDS_Pin); tx_thread_sleep(ticks); - HAL_GPIO_WritePin(VC_LEDS_GPIO_Port, VC_LEDS_Pin, GPIO_PIN_RESET); + VCU_Output_High(VC_LEDS_GPIO_Port, VC_LEDS_Pin); } /** @@ -162,7 +154,7 @@ static void toggle_ts_on_callback(ULONG input) dash_context_t *dash_ptr = (dash_context_t *)input; UNUSED(dash_ptr); - HAL_GPIO_TogglePin(TS_ON_LED_GPIO_Port, TS_ON_LED_Pin); + VCU_Output_Toggle(TS_ON_LED_GPIO_Port, TS_ON_LED_Pin); } /** @@ -177,21 +169,20 @@ status_t dash_set_ts_on_led_state(dash_context_t *dash_ptr, GPIO_PinState state) { UINT is_toggling = 0; - UINT tx_status = tx_timer_info_get(&dash_ptr->ts_on_toggle_timer, - NULL, - &is_toggling, - NULL, - NULL, - NULL); + UINT tx_status = tx_timer_info_get(&dash_ptr->ts_on_toggle_timer, NULL, + &is_toggling, NULL, NULL, NULL); if (is_toggling && (tx_status == TX_SUCCESS)) { tx_status = tx_timer_deactivate(&dash_ptr->ts_on_toggle_timer); } - HAL_GPIO_WritePin(TS_ON_LED_GPIO_Port, TS_ON_LED_Pin, state); + if (tx_status == TX_SUCCESS) + { + return VCU_Output_Write(TS_ON_LED_GPIO_Port, TS_ON_LED_Pin, state); + } - return (tx_status == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; + return STATUS_ERROR; } /** @@ -199,16 +190,16 @@ status_t dash_set_ts_on_led_state(dash_context_t *dash_ptr, GPIO_PinState state) * * @details The calling thread is suspended until this occurs */ -status_t dash_wait_for_ts_on(dash_context_t *dash_ptr) +status_t dash_wait_for_ts_on(const dash_context_t *dash_ptr) { - input_context_t ts_on_input = {.port = TS_ON_BTN_GPIO_Port, - .pin = TS_ON_BTN_Pin, - .active_state = true, - .last_state = false, - .require_release = true, - .active_start = 0, - .required_ticks = dash_ptr->config_ptr->btn_active_ticks, - .sample_ticks = dash_ptr->config_ptr->btn_sample_ticks}; + input_context_t ts_on_input = { .port = TS_ON_BTN_GPIO_Port, + .pin = TS_ON_BTN_Pin, + .active_state = true, + .last_state = false, + .require_release = true, + .active_start = 0, + .required_ticks = dash_ptr->config_ptr->btn_active_ticks, + .sample_ticks = dash_ptr->config_ptr->btn_sample_ticks }; return input_wait(&ts_on_input); } @@ -218,16 +209,16 @@ status_t dash_wait_for_ts_on(dash_context_t *dash_ptr) * * @details The calling thread is suspended until this occurs */ -status_t dash_wait_for_r2d(dash_context_t *dash_ptr) +status_t dash_wait_for_r2d(const dash_context_t *dash_ptr) { - input_context_t r2d_input = {.port = R2D_BTN_GPIO_Port, - .pin = R2D_BTN_Pin, - .active_state = true, - .last_state = false, - .require_release = true, - .active_start = 0, - .required_ticks = dash_ptr->config_ptr->btn_active_ticks, - .sample_ticks = dash_ptr->config_ptr->btn_sample_ticks}; + input_context_t r2d_input = { .port = R2D_BTN_GPIO_Port, + .pin = R2D_BTN_Pin, + .active_state = true, + .last_state = false, + .require_release = true, + .active_start = 0, + .required_ticks = dash_ptr->config_ptr->btn_active_ticks, + .sample_ticks = dash_ptr->config_ptr->btn_sample_ticks }; return input_wait(&r2d_input); } @@ -245,18 +236,21 @@ status_t input_wait(input_context_t *input_ptr) while (!done && (status == STATUS_OK)) { - bool state = (HAL_GPIO_ReadPin(input_ptr->port, input_ptr->pin) == GPIO_PIN_SET); + bool state = VCU_Input_Read(input_ptr->port, input_ptr->pin); // rising edge (active, previously inactive) - if (state == input_ptr->active_state && (input_ptr->last_state != input_ptr->active_state)) + if (state == input_ptr->active_state && + (input_ptr->last_state != input_ptr->active_state)) { input_ptr->active_start = tx_time_get(); } // held - bool active_no_release_check = !input_ptr->require_release && (state == input_ptr->active_state); + bool active_no_release_check = + !input_ptr->require_release && (state == input_ptr->active_state); - bool held_and_released = (state != input_ptr->active_state) && (input_ptr->last_state == input_ptr->active_state); + bool held_and_released = (state != input_ptr->active_state) && + (input_ptr->last_state == input_ptr->active_state); if (active_no_release_check || held_and_released) { @@ -271,9 +265,7 @@ status_t input_wait(input_context_t *input_ptr) // update state and sleep input_ptr->last_state = state; - status = (tx_thread_sleep(input_ptr->sample_ticks) == TX_SUCCESS) - ? STATUS_OK - : STATUS_ERROR; + status = (tx_thread_sleep(input_ptr->sample_ticks) == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; } return status; @@ -285,7 +277,7 @@ status_t input_wait(input_context_t *input_ptr) bool input_update(input_context_t *input_ptr) { bool pressed = false; - bool state = (HAL_GPIO_ReadPin(input_ptr->port, input_ptr->pin) == GPIO_PIN_SET); + bool state = VCU_Input_Read(input_ptr->port, input_ptr->pin); // rising edge (active, previously inactive) if (state == input_ptr->active_state && (input_ptr->last_state != input_ptr->active_state)) @@ -294,9 +286,11 @@ bool input_update(input_context_t *input_ptr) } // held - bool active_no_release_check = !input_ptr->require_release && (state == input_ptr->active_state); + bool active_no_release_check = + !input_ptr->require_release && (state == input_ptr->active_state); - bool held_and_released = (state != input_ptr->active_state) && (input_ptr->last_state == input_ptr->active_state); + bool held_and_released = (state != input_ptr->active_state) && + (input_ptr->last_state == input_ptr->active_state); if (active_no_release_check || held_and_released) { @@ -335,6 +329,5 @@ void dash_clear_buttons(dash_context_t *dash_ptr) status_t dash_set_r2d_led_state(dash_context_t *dash_ptr, GPIO_PinState state) { UNUSED(dash_ptr); - HAL_GPIO_WritePin(R2D_LED_GPIO_Port, R2D_LED_Pin, state); - return STATUS_OK; + return VCU_Output_Write(R2D_LED_GPIO_Port, R2D_LED_Pin, state); } diff --git a/src/SUFST/Src/Services/fans.c b/src/SUFST/Src/Services/fans.c new file mode 100644 index 00000000..25634753 --- /dev/null +++ b/src/SUFST/Src/Services/fans.c @@ -0,0 +1,117 @@ +#include "fans.h" + +#include "log.h" +#include "main.h" +#include + +static void fans_thread_entry(ULONG input); + +status_t fans_init(fans_context_t *fh, + rtcan_handle_t *rtcan_s_h, + TX_BYTE_POOL *stack_pool_ptr, + const config_fans_t *config_ptr) +{ + if (!config_ptr->enable) + return STATUS_OK; + + fh->config_ptr = config_ptr; + fh->rtcan_s_h = rtcan_s_h; + fh->fan_switch_status = false; + fh->fan_thermal_pwr = false; + + void *stack_ptr = NULL; + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); + + // create CAN receive queue + if (tx_status == TX_SUCCESS) + { + if (rtcan_os_queue_create(&fh->can_rx_queue, NULL, sizeof(rtcan_msg_t *), + FANS_RX_QUEUE_SIZE, fh->can_rx_queue_mem, + sizeof(fh->can_rx_queue_mem)) != RTCAN_OS_OK) + { + tx_status = TX_START_ERROR; + } + } + + // create thread + if (tx_status == TX_SUCCESS) + { + tx_status = + tx_thread_create(&fh->thread, (CHAR *)config_ptr->thread.name, fans_thread_entry, + (ULONG)fh, stack_ptr, config_ptr->thread.stack_size, + config_ptr->thread.priority, config_ptr->thread.priority, + TX_NO_TIME_SLICE, TX_AUTO_START); + } + + return (tx_status == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; +} + +static void process_broadcast(fans_context_t *fh, const rtcan_msg_t *msg_ptr) +{ + if (msg_ptr->identifier != CAN_S_DASH_SENSORS_DIGITAL_FRAME_ID) + return; + struct can_s_dash_sensors_digital_t data; + can_s_dash_sensors_digital_unpack(&data, msg_ptr->data, msg_ptr->length); + fh->fan_switch_status = fh->config_ptr->inverted ? !data.fan_switch : data.fan_switch; +} + +static void fans_thread_entry(ULONG input) +{ + fans_context_t *fh = (fans_context_t *)input; + + rtcan_status_t status = + rtcan_subscribe(fh->rtcan_s_h, CAN_S_DASH_SENSORS_DIGITAL_FRAME_ID, fh->can_rx_queue); + + if (status != RTCAN_OK) + { + LOG_ERROR("Could not subscribe on message. Terminating thread\n"); + tx_thread_terminate(&fh->thread); + } + + while (1) + { + rtcan_msg_t *msg_ptr = NULL; + rtcan_osal_status_t rec_status = + rtcan_os_queue_receive(fh->can_rx_queue, &msg_ptr, + fh->config_ptr->broadcast_timeout_ticks); + + if (rec_status == RTCAN_OS_OK && msg_ptr != NULL) + { + process_broadcast(fh, msg_ptr); + rtcan_msg_consumed(fh->rtcan_s_h, msg_ptr); + continue; + } + + LOG_INFO("FAN switch broadcast timeout\n"); + } +} + +/** + * @brief Updates the thermal hysteresis state from a temperature reading + * + * @param[in] fh Fans context + * @param[in] max_temp Highest of the motor / inverter temperatures + */ +void fans_update_thermal(fans_context_t *fh, int16_t max_temp) +{ + if (max_temp > fh->config_ptr->fan_on_threshold) + { + fh->fan_thermal_pwr = true; + } + else if (fh->fan_thermal_pwr && max_temp < fh->config_ptr->fan_off_threshold) + { + fh->fan_thermal_pwr = false; + } +} + +/** + * @brief Whether the fan should be powered, combining the thermal + * hysteresis output with the driver's manual override switch + * + * @param[in] fh Fans context + */ +bool fans_output_pwr(const fans_context_t *fh) +{ + return fh->fan_thermal_pwr || fh->fan_switch_status; +} diff --git a/src/SUFST/Src/Services/heartbeat.c b/src/SUFST/Src/Services/heartbeat.c index 112c6dce..87c18105 100644 --- a/src/SUFST/Src/Services/heartbeat.c +++ b/src/SUFST/Src/Services/heartbeat.c @@ -6,9 +6,10 @@ #include "heartbeat.h" -/* - * internal function prototypes - */ +#include "io.h" + +static heartbeat_context_t *global_heartbeat_context; + static void heartbeat_thread_entry(ULONG input); /** @@ -26,26 +27,29 @@ status_t heartbeat_init(heartbeat_context_t *heartbeat_h, // create service thread void *stack_ptr = NULL; - UINT tx_status = tx_byte_allocate(stack_pool_ptr, - &stack_ptr, - config_ptr->thread.stack_size, - TX_NO_WAIT); + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); if (tx_status == TX_SUCCESS) { - tx_status = tx_thread_create(&heartbeat_h->thread, - (CHAR *)config_ptr->thread.name, - heartbeat_thread_entry, - (ULONG)heartbeat_h, - stack_ptr, - config_ptr->thread.stack_size, - config_ptr->thread.priority, - config_ptr->thread.priority, - TX_NO_TIME_SLICE, - TX_AUTO_START); + tx_status = + tx_thread_create(&heartbeat_h->thread, (CHAR *)config_ptr->thread.name, + heartbeat_thread_entry, (ULONG)heartbeat_h, stack_ptr, + config_ptr->thread.stack_size, config_ptr->thread.priority, + config_ptr->thread.priority, TX_NO_TIME_SLICE, TX_AUTO_START); } - return (tx_status == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; + if (tx_status != TX_SUCCESS) + return STATUS_ERROR; + + global_heartbeat_context = heartbeat_h; + return STATUS_OK; +} + +void heartbeat_set_fast(void) +{ + if (global_heartbeat_context != NULL) + global_heartbeat_context->fast_mode = true; } /** @@ -59,15 +63,16 @@ static void heartbeat_thread_entry(ULONG input) heartbeat_context_t *heartbeat_h = (heartbeat_context_t *)input; // initialise LED - HAL_GPIO_WritePin(GREEN_LED_GPIO_Port, GREEN_LED_Pin, GPIO_PIN_RESET); + VCU_Output_Low(ROB_LED_GPIO_Port, ROB_LED_Pin); // main loop while (1) { - // toggle LED - HAL_GPIO_TogglePin(GREEN_LED_GPIO_Port, GREEN_LED_Pin); + VCU_Output_Toggle(ROB_LED_GPIO_Port, ROB_LED_Pin); - // wait - tx_thread_sleep(heartbeat_h->config_ptr->blink_period_ticks); + ULONG period = heartbeat_h->fast_mode ? + heartbeat_h->config_ptr->fast_blink_period_ticks : + heartbeat_h->config_ptr->blink_period_ticks; + tx_thread_sleep(period); } } \ No newline at end of file diff --git a/src/SUFST/Src/Services/log.c b/src/SUFST/Src/Services/log.c index 2df47524..28da8d42 100644 --- a/src/SUFST/Src/Services/log.c +++ b/src/SUFST/Src/Services/log.c @@ -16,17 +16,18 @@ #include #include "config.h" +#include "rs232.h" +#include "sd_logging.h" #include "status.h" // internal function prototype static void log_thread_entry(ULONG thread_input); // log level names -static const char* log_level_names[] - = {"DEBUG", "INFO", "WARN", "ERROR", "FATAL"}; +static const char *log_level_names[] = { "DEBUG", "INFO", "WARN", "ERROR", "FATAL" }; // Global log Context -static log_context_t* global_log_context; +static log_context_t *global_log_context; /** * @brief initialises the logging service @@ -36,31 +37,26 @@ static log_context_t* global_log_context; * @param config_ptr logging service configuration * @return status_t outcome of initialisation */ -status_t log_init(log_context_t *log_ptr, - TX_BYTE_POOL *stack_pool_ptr, - const config_log_t *config_ptr) +status_t log_init(log_context_t *log_ptr, TX_BYTE_POOL *stack_pool_ptr, const config_log_t *config_ptr) { log_ptr->config_ptr = config_ptr; log_ptr->error = LOG_ERROR_NONE; global_log_context = log_ptr; + rs232_enable(); + status_t status = STATUS_OK; // allocate stack space void *stack_ptr = NULL; - UINT tx_status = tx_byte_allocate(stack_pool_ptr, - &stack_ptr, - config_ptr->thread.stack_size, - TX_NO_WAIT); + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); // create log message queue if (tx_status == TX_SUCCESS) { - tx_status = tx_queue_create(&log_ptr->msg_queue, - NULL, - TX_16_ULONG, - log_ptr->msg_queue_mem, - LOG_MSG_QUEUE_SIZE); + tx_status = tx_queue_create(&log_ptr->msg_queue, NULL, TX_16_ULONG, + log_ptr->msg_queue_mem, LOG_MSG_QUEUE_SIZE); } // create UART mutex @@ -72,16 +68,12 @@ status_t log_init(log_context_t *log_ptr, // create TX thread if (tx_status == TX_SUCCESS) { - tx_status = tx_thread_create(&log_ptr->thread, - (CHAR *)log_ptr->config_ptr->thread.name, - log_thread_entry, - (ULONG)log_ptr, - stack_ptr, - config_ptr->thread.stack_size, - config_ptr->thread.priority, - config_ptr->thread.priority, - TX_NO_TIME_SLICE, - TX_AUTO_START); + tx_status = + tx_thread_create(&log_ptr->thread, + (CHAR *)log_ptr->config_ptr->thread.name, log_thread_entry, + (ULONG)log_ptr, stack_ptr, config_ptr->thread.stack_size, + config_ptr->thread.priority, config_ptr->thread.priority, + TX_NO_TIME_SLICE, TX_AUTO_START); } // check for errors @@ -101,7 +93,7 @@ status_t log_init(log_context_t *log_ptr, return status; } -status_t log_printf(const config_log_level_t level, const char* format, ...) +status_t log_printf(const config_log_level_t level, const char *format, ...) { // check if the message should be logged if (level < global_log_context->config_ptr->min_level) @@ -123,9 +115,7 @@ status_t log_printf(const config_log_level_t level, const char* format, ...) tx_interrupt_control(last_interrupt_state); // queue the message - UINT tx_status = tx_queue_send(&global_log_context->msg_queue, - (void*) &msg, - TX_NO_WAIT); + UINT tx_status = tx_queue_send(&global_log_context->msg_queue, (void *)&msg, TX_NO_WAIT); // check for errors if (tx_status != TX_SUCCESS) @@ -148,9 +138,7 @@ void log_thread_entry(ULONG thread_input) while (true) { // wait for a message to be queued - tx_status = tx_queue_receive(&log_ptr->msg_queue, - (void *)&msg, - TX_WAIT_FOREVER); + tx_status = tx_queue_receive(&log_ptr->msg_queue, (void *)&msg, TX_WAIT_FOREVER); // if no message was recieved, try again // TODO: Error Handling @@ -162,12 +150,8 @@ void log_thread_entry(ULONG thread_input) // format the log message UINT last_interrupt_state = tx_interrupt_control(TX_INT_DISABLE); - snprintf(log_msg_to_send, - LOG_MSG_MAX_TRANSMITION_LEN, - "%ld [%s]: %s", - msg.timestamp, - log_level_names[msg.level], - msg.msg); + snprintf(log_msg_to_send, LOG_MSG_MAX_TRANSMITION_LEN, "%ld [%s]: %s", + msg.timestamp, log_level_names[msg.level], msg.msg); tx_interrupt_control(last_interrupt_state); // lock the UART mutex @@ -183,12 +167,27 @@ void log_thread_entry(ULONG thread_input) log_ptr->error &= ~LOG_ERROR_MUTEX; } - // print the message - HAL_StatusTypeDef status - = HAL_UART_Transmit(log_ptr->config_ptr->uart, - (const uint8_t*) log_msg_to_send, - strlen(log_msg_to_send), - HAL_MAX_DELAY); + // print the message over UART (-> rs232) + HAL_StatusTypeDef uart_status = HAL_OK; + if (log_ptr->config_ptr->uart != NULL) + { + uart_status = HAL_UART_Transmit(log_ptr->config_ptr->uart, + (const uint8_t *)log_msg_to_send, + strlen(log_msg_to_send), HAL_MAX_DELAY); + } + + // print the message over USART (-> debug header) + HAL_StatusTypeDef usart_status = HAL_OK; + if (log_ptr->config_ptr->usart != NULL) + { + usart_status = HAL_USART_Transmit(log_ptr->config_ptr->usart, + (const uint8_t *)log_msg_to_send, + strlen(log_msg_to_send), HAL_MAX_DELAY); + } + + // if level >= sd_min_level write to SD card + if (msg.level >= log_ptr->config_ptr->min_sd_log_level) + write_sd_log_line(log_msg_to_send); // unlock the UART mutex tx_status = tx_mutex_put(&log_ptr->uart_mutex); @@ -201,7 +200,7 @@ void log_thread_entry(ULONG thread_input) log_ptr->error &= ~LOG_ERROR_MUTEX; } - if (status != HAL_OK) + if (uart_status != HAL_OK) { log_ptr->error |= LOG_ERROR_UART; } @@ -209,5 +208,14 @@ void log_thread_entry(ULONG thread_input) { log_ptr->error &= ~LOG_ERROR_UART; } + + if (usart_status != HAL_OK) + { + log_ptr->error |= LOG_ERROR_USART; + } + else + { + log_ptr->error &= ~LOG_ERROR_USART; + } } } diff --git a/src/SUFST/Src/Services/pm100.c b/src/SUFST/Src/Services/pm100.c index 3c468aee..e9fc27a4 100644 --- a/src/SUFST/Src/Services/pm100.c +++ b/src/SUFST/Src/Services/pm100.c @@ -1,59 +1,62 @@ #include "pm100.h" -#include +#include + #include +#include + +#include "io.h" -#define PM100_NO_FAULTS 0x00 +#define PM100_NO_FAULTS 0x00 -#define PM100_VSM_STATE_START 0x00 -#define PM100_VSM_STATE_PRECHARGE_INIT 0x01 -#define PM100_VSM_STATE_PRECHARGE_ACTIVE 0x02 +#define PM100_VSM_STATE_START 0x00 +#define PM100_VSM_STATE_PRECHARGE_INIT 0x01 +#define PM100_VSM_STATE_PRECHARGE_ACTIVE 0x02 #define PM100_VSM_STATE_PRECHARGE_COMPLETE 0x03 -#define PM100_VSM_STATE_WAIT 0x04 -#define PM100_VSM_STATE_READY 0x05 -#define PM100_VSM_STATE_RUNNING 0x06 -#define PM100_VSM_STATE_FAULT 0x07 - -#define PM100_LOCKOUT_DISABLED 0x0 -#define PM100_LOCKOUT_ENABLED 0x1 -#define PM100_CAN_MODE 0x0 -#define PM100_VSM_MODE 0x1 -#define PM100_DIRECTION_REVERSE 0x0 -#define PM100_DIRECTION_FORWARD 0x1 -#define PM100_INVERTER_OFF 0x0 -#define PM100_INVERTER_ON 0x1 -#define PM100_TORQUE_MODE 0x0 -#define PM100_SPEED_MODE 0x1 -#define PM100_SPEED_MODE_DISABLE 0x0 -#define PM100_SPEED_MODE_ENABLE 0x1 - -#define PM100_DIRECTION_FORWARD 0x1 -#define PM100_DIRECTION_REVERSE 0x0 +#define PM100_VSM_STATE_WAIT 0x04 +#define PM100_VSM_STATE_READY 0x05 +#define PM100_VSM_STATE_RUNNING 0x06 +#define PM100_VSM_STATE_FAULT 0x07 + +#define PM100_LOCKOUT_DISABLED 0x0 +#define PM100_LOCKOUT_ENABLED 0x1 +#define PM100_CAN_MODE 0x0 +#define PM100_VSM_MODE 0x1 +#define PM100_DIRECTION_REVERSE 0x0 +#define PM100_DIRECTION_FORWARD 0x1 +#define PM100_INVERTER_OFF 0x0 +#define PM100_INVERTER_ON 0x1 +#define PM100_TORQUE_MODE 0x0 +#define PM100_SPEED_MODE 0x1 +#define PM100_SPEED_MODE_DISABLE 0x0 +#define PM100_SPEED_MODE_ENABLE 0x1 + +#define PM100_DIRECTION_FORWARD 0x1 +#define PM100_DIRECTION_REVERSE 0x0 /* * internal function prototypes */ static void pm100_thread_entry(ULONG input); -static void process_broadcast(pm100_context_t* pm100_ptr, - const rtcan_msg_t* msg_ptr); +static void process_broadcast(pm100_context_t *pm100_ptr, const rtcan_msg_t *msg_ptr); /** * @brief Initialises the PM100 service * * @param[in] pm100_ptr PM100 context * @param[in] stack_pool_ptr Memory pool for service thread stack - * @param[in] rtcan_c_ptr RTCAN C instance for receiving broadcasts + * @param[in] rtcan_t_ptr RTCAN T instance for receiving broadcasts * @param[in] rtcan_s_ptr RTCAN S instance for sending precharge cmd * @param[in] config_ptr Configuration */ -status_t pm100_init(pm100_context_t* pm100_ptr, - TX_BYTE_POOL* stack_pool_ptr, - rtcan_handle_t* rtcan_c_ptr, - rtcan_handle_t* rtcan_s_ptr, - const config_pm100_t* config_ptr) +status_t pm100_init(pm100_context_t *pm100_ptr, + TX_BYTE_POOL *stack_pool_ptr, + rtcan_handle_t *rtcan_t_ptr, + rtcan_handle_t *rtcan_s_ptr, + const config_pm100_t *config_ptr) { pm100_ptr->config_ptr = config_ptr; - pm100_ptr->rtcan_c_ptr = rtcan_c_ptr; + pm100_ptr->rtcan_t_ptr = rtcan_t_ptr; pm100_ptr->rtcan_s_ptr = rtcan_s_ptr; pm100_ptr->error = PM100_ERROR_NONE; pm100_ptr->broadcasts_valid = false; @@ -61,34 +64,28 @@ status_t pm100_init(pm100_context_t* pm100_ptr, status_t status = STATUS_OK; // create service thread - void* stack_ptr = NULL; - UINT tx_status = tx_byte_allocate(stack_pool_ptr, - &stack_ptr, - config_ptr->thread.stack_size, - TX_NO_WAIT); + void *stack_ptr = NULL; + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); if (tx_status == TX_SUCCESS) { - tx_status = tx_thread_create(&pm100_ptr->thread, - (CHAR*) config_ptr->thread.name, - pm100_thread_entry, - (ULONG) pm100_ptr, - stack_ptr, - config_ptr->thread.stack_size, - config_ptr->thread.priority, - config_ptr->thread.priority, - TX_NO_TIME_SLICE, - TX_AUTO_START); + tx_status = + tx_thread_create(&pm100_ptr->thread, (CHAR *)config_ptr->thread.name, + pm100_thread_entry, (ULONG)pm100_ptr, stack_ptr, + config_ptr->thread.stack_size, config_ptr->thread.priority, + config_ptr->thread.priority, TX_NO_TIME_SLICE, TX_AUTO_START); } // create CAN receive queue if (tx_status == TX_SUCCESS) { - tx_status = tx_queue_create(&pm100_ptr->can_rx_queue, - NULL, - TX_1_ULONG, - pm100_ptr->can_rx_queue_mem, - sizeof(pm100_ptr->can_rx_queue_mem)); + if (rtcan_os_queue_create(&pm100_ptr->can_rx_queue, NULL, sizeof(rtcan_msg_t *), + PM100_RX_QUEUE_SIZE, pm100_ptr->can_rx_queue_mem, + sizeof(pm100_ptr->can_rx_queue_mem)) != RTCAN_OS_OK) + { + tx_status = TX_START_ERROR; + } } // create state mutex @@ -109,9 +106,8 @@ status_t pm100_init(pm100_context_t* pm100_ptr, } // turn off power - HAL_GPIO_WritePin(STATUS_GPIO_Port, // This pin used to be called STATUS - STATUS_Pin, - GPIO_PIN_RESET); + VCU_Output_Low(STATUS_GPIO_Port, // This pin used to be called STATUS + STATUS_Pin); return status; } @@ -124,29 +120,27 @@ status_t pm100_init(pm100_context_t* pm100_ptr, */ void pm100_thread_entry(ULONG input) { - pm100_context_t* pm100_ptr = (pm100_context_t*) input; - const config_pm100_t* config_ptr = pm100_ptr->config_ptr; + pm100_context_t *pm100_ptr = (pm100_context_t *)input; + const config_pm100_t *config_ptr = pm100_ptr->config_ptr; // set up RTCAN subscriptions - uint32_t subscriptions[] = {CAN_C_PM100_INTERNAL_STATES_FRAME_ID, - CAN_C_PM100_FAULT_CODES_FRAME_ID, - CAN_C_PM100_TEMPERATURE_SET_1_FRAME_ID, - CAN_C_PM100_TEMPERATURE_SET_2_FRAME_ID, - CAN_C_PM100_TEMPERATURE_SET_3_FRAME_ID, - CAN_C_PM100_MOTOR_POSITION_INFO_FRAME_ID}; - - for (uint32_t i = 0; i < sizeof(subscriptions) / sizeof(subscriptions[0]); - i++) + uint32_t subscriptions[] = { CAN_T_PM100_INTERNAL_STATES_FRAME_ID, + CAN_T_PM100_FAULT_CODES_FRAME_ID, + CAN_T_PM100_TEMPERATURE_SET_1_FRAME_ID, + CAN_T_PM100_TEMPERATURE_SET_2_FRAME_ID, + CAN_T_PM100_TEMPERATURE_SET_3_FRAME_ID, + CAN_T_PM100_MOTOR_POSITION_INFO_FRAME_ID, + CAN_T_PM100_VOLTAGE_INFO_FRAME_ID, + CAN_T_PM100_CURRENT_INFO_FRAME_ID }; + + for (uint32_t i = 0; i < sizeof(subscriptions) / sizeof(subscriptions[0]); i++) { - rtcan_status_t status = rtcan_subscribe(pm100_ptr->rtcan_c_ptr, - subscriptions[i], - &pm100_ptr->can_rx_queue); + rtcan_status_t status = + rtcan_subscribe(pm100_ptr->rtcan_t_ptr, subscriptions[i], pm100_ptr->can_rx_queue); if (status != RTCAN_OK) { - // TODO: update broadcast states with error - LOG_ERROR( - "Could not subscribe on %d message. Terminating thread\n"); + LOG_ERROR("Could not subscribe on %d message. Terminating thread\n", i); tx_thread_terminate(&pm100_ptr->thread); } } @@ -154,23 +148,23 @@ void pm100_thread_entry(ULONG input) // process incoming messages, or timeout while (1) { - rtcan_msg_t* msg_ptr = NULL; - UINT status = tx_queue_receive(&pm100_ptr->can_rx_queue, - &msg_ptr, - config_ptr->broadcast_timeout_ticks); + rtcan_msg_t *msg_ptr = NULL; + rtcan_osal_status_t status = + rtcan_os_queue_receive(pm100_ptr->can_rx_queue, &msg_ptr, + config_ptr->broadcast_timeout_ticks); - if (status == TX_QUEUE_EMPTY) + if (status == RTCAN_OS_TIMEOUT) { // timed out // TODO: error pm100_ptr->broadcasts_valid = false; LOG_INFO("PM100 broadcast timeout\n"); } - else if (status == TX_SUCCESS && msg_ptr != NULL) + else if (status == RTCAN_OS_OK && msg_ptr != NULL) { pm100_ptr->broadcasts_valid = true; process_broadcast(pm100_ptr, msg_ptr); - rtcan_msg_consumed(pm100_ptr->rtcan_c_ptr, msg_ptr); + rtcan_msg_consumed(pm100_ptr->rtcan_t_ptr, msg_ptr); } else { @@ -185,84 +179,86 @@ void pm100_thread_entry(ULONG input) * @param[in] pm100_ptr PM100 context * @param[in] msg_ptr Incoming message */ -void process_broadcast(pm100_context_t* pm100_ptr, const rtcan_msg_t* msg_ptr) +void process_broadcast(pm100_context_t *pm100_ptr, const rtcan_msg_t *msg_ptr) { switch (msg_ptr->identifier) { - case CAN_C_PM100_INTERNAL_STATES_FRAME_ID: + case CAN_T_PM100_INTERNAL_STATES_FRAME_ID: { - can_c_pm100_internal_states_unpack(&pm100_ptr->states, - msg_ptr->data, + can_t_pm100_internal_states_unpack(&pm100_ptr->states, msg_ptr->data, msg_ptr->length); break; } - case CAN_C_PM100_FAULT_CODES_FRAME_ID: + case CAN_T_PM100_FAULT_CODES_FRAME_ID: { - can_c_pm100_fault_codes_unpack(&pm100_ptr->faults, - msg_ptr->data, + can_t_pm100_fault_codes_unpack(&pm100_ptr->faults, msg_ptr->data, msg_ptr->length); - if (pm100_ptr->faults.pm100_run_fault_hi != PM100_NO_FAULTS - || pm100_ptr->faults.pm100_post_fault_lo != PM100_NO_FAULTS) + if (pm100_ptr->faults.pm100_run_fault_hi != PM100_NO_FAULTS || + pm100_ptr->faults.pm100_post_fault_lo != PM100_NO_FAULTS) { pm100_ptr->error |= PM100_ERROR_RUN_FAULT; - (void) pm100_disable(pm100_ptr); + (void)pm100_disable(pm100_ptr); } - else if (pm100_ptr->faults.pm100_post_fault_hi != PM100_NO_FAULTS - || pm100_ptr->faults.pm100_post_fault_lo != PM100_NO_FAULTS) + else if (pm100_ptr->faults.pm100_post_fault_hi != PM100_NO_FAULTS || + pm100_ptr->faults.pm100_post_fault_lo != PM100_NO_FAULTS) { pm100_ptr->error |= PM100_ERROR_POST_FAULT; - (void) pm100_disable(pm100_ptr); + (void)pm100_disable(pm100_ptr); } break; } - case CAN_C_PM100_TEMPERATURE_SET_1_FRAME_ID: + case CAN_T_PM100_TEMPERATURE_SET_1_FRAME_ID: { - can_c_pm100_temperature_set_1_unpack(&pm100_ptr->temp1, - msg_ptr->data, + can_t_pm100_temperature_set_1_unpack(&pm100_ptr->temp1, msg_ptr->data, msg_ptr->length); break; } - case CAN_C_PM100_TEMPERATURE_SET_2_FRAME_ID: + case CAN_T_PM100_TEMPERATURE_SET_2_FRAME_ID: { - can_c_pm100_temperature_set_2_unpack(&pm100_ptr->temp2, - msg_ptr->data, - msg_ptr->length); - - break; - can_c_pm100_temperature_set_2_unpack(&pm100_ptr->temp2, - msg_ptr->data, + can_t_pm100_temperature_set_2_unpack(&pm100_ptr->temp2, msg_ptr->data, msg_ptr->length); break; } - case CAN_C_PM100_TEMPERATURE_SET_3_FRAME_ID: + case CAN_T_PM100_TEMPERATURE_SET_3_FRAME_ID: { - can_c_pm100_temperature_set_3_unpack(&pm100_ptr->temp3, - msg_ptr->data, + can_t_pm100_temperature_set_3_unpack(&pm100_ptr->temp3, msg_ptr->data, msg_ptr->length); break; } - case CAN_C_PM100_MOTOR_POSITION_INFO_FRAME_ID: + case CAN_T_PM100_MOTOR_POSITION_INFO_FRAME_ID: { - can_c_pm100_motor_position_info_unpack(&pm100_ptr->info, - msg_ptr->data, + can_t_pm100_motor_position_info_unpack(&pm100_ptr->info, msg_ptr->data, msg_ptr->length); break; } - default: + case CAN_T_PM100_VOLTAGE_INFO_FRAME_ID: + { + can_t_pm100_voltage_info_unpack(&pm100_ptr->voltage_info, msg_ptr->data, + msg_ptr->length); break; } + + case CAN_T_PM100_CURRENT_INFO_FRAME_ID: + { + can_t_pm100_current_info_unpack(&pm100_ptr->current_info, msg_ptr->data, + msg_ptr->length); + break; + } + + default: break; + } } /** @@ -280,7 +276,7 @@ void process_broadcast(pm100_context_t* pm100_ptr, const rtcan_msg_t* msg_ptr) * * @param[in] pm100_ptr PM100 context */ -status_t pm100_lvs_on(pm100_context_t* pm100_ptr) +status_t pm100_lvs_on(pm100_context_t *pm100_ptr) { // UINT tx_status = tx_thread_resume(&pm100_ptr->thread); @@ -292,11 +288,10 @@ status_t pm100_lvs_on(pm100_context_t* pm100_ptr) * * @param[in] pm100_ptr PM100 context */ -bool pm100_is_precharged(pm100_context_t* pm100_ptr) +bool pm100_is_precharged(pm100_context_t *pm100_ptr) { - UINT tx_status - = tx_mutex_get(&pm100_ptr->state_mutex, - pm100_ptr->config_ptr->precharge_timeout_ticks); + UINT tx_status = tx_mutex_get(&pm100_ptr->state_mutex, + pm100_ptr->config_ptr->precharge_timeout_ticks); bool broadcasts_valid = false; uint8_t vsm_state = PM100_VSM_STATE_FAULT; // assume something safe @@ -305,17 +300,15 @@ bool pm100_is_precharged(pm100_context_t* pm100_ptr) { vsm_state = pm100_ptr->states.pm100_vsm_state; broadcasts_valid = pm100_ptr->broadcasts_valid; - (void) tx_mutex_put(&pm100_ptr->state_mutex); + (void)tx_mutex_put(&pm100_ptr->state_mutex); } - return broadcasts_valid - && (vsm_state == PM100_VSM_STATE_PRECHARGE_COMPLETE - || vsm_state == PM100_VSM_STATE_WAIT - || vsm_state == PM100_VSM_STATE_READY - || vsm_state == PM100_VSM_STATE_RUNNING); + return broadcasts_valid && + (vsm_state == PM100_VSM_STATE_PRECHARGE_COMPLETE || vsm_state == PM100_VSM_STATE_WAIT || + vsm_state == PM100_VSM_STATE_READY || vsm_state == PM100_VSM_STATE_RUNNING); } -int16_t pm100_max_inverter_temp(pm100_context_t* pm100_ptr) +int16_t pm100_max_inverter_temp(pm100_context_t *pm100_ptr) { int16_t max_temp = 0; @@ -323,16 +316,29 @@ int16_t pm100_max_inverter_temp(pm100_context_t* pm100_ptr) if (tx_status == TX_SUCCESS) { - if (pm100_ptr->temp1.pm100_module_a > max_temp) - max_temp = pm100_ptr->temp1.pm100_module_a; - if (pm100_ptr->temp1.pm100_module_b > max_temp) - max_temp = pm100_ptr->temp1.pm100_module_b; - if (pm100_ptr->temp1.pm100_module_c > max_temp) - max_temp = pm100_ptr->temp1.pm100_module_c; - if (pm100_ptr->temp1.pm100_gate_driver_board > max_temp) - max_temp = pm100_ptr->temp1.pm100_gate_driver_board; - if (pm100_ptr->temp2.pm100_control_board_temperature > max_temp) - max_temp = pm100_ptr->temp2.pm100_control_board_temperature; + int16_t module_a = (int16_t)can_t_pm100_temperature_set_1_pm100_module_a_decode( + pm100_ptr->temp1.pm100_module_a); + int16_t module_b = (int16_t)can_t_pm100_temperature_set_1_pm100_module_b_decode( + pm100_ptr->temp1.pm100_module_b); + int16_t module_c = (int16_t)can_t_pm100_temperature_set_1_pm100_module_c_decode( + pm100_ptr->temp1.pm100_module_c); + int16_t gate_driver_board = + (int16_t)can_t_pm100_temperature_set_1_pm100_gate_driver_board_decode( + pm100_ptr->temp1.pm100_gate_driver_board); + int16_t control_board = + (int16_t)can_t_pm100_temperature_set_2_pm100_control_board_temperature_decode( + pm100_ptr->temp2.pm100_control_board_temperature); + + if (module_a > max_temp) + max_temp = module_a; + if (module_b > max_temp) + max_temp = module_b; + if (module_c > max_temp) + max_temp = module_c; + if (gate_driver_board > max_temp) + max_temp = gate_driver_board; + if (control_board > max_temp) + max_temp = control_board; tx_mutex_put(&pm100_ptr->state_mutex); } @@ -344,7 +350,7 @@ int16_t pm100_max_inverter_temp(pm100_context_t* pm100_ptr) return max_temp; } -int16_t pm100_motor_temp(pm100_context_t* pm100_ptr) +int16_t pm100_motor_temp(pm100_context_t *pm100_ptr) { int16_t motor_temp = 0; @@ -352,7 +358,8 @@ int16_t pm100_motor_temp(pm100_context_t* pm100_ptr) if (tx_status == TX_SUCCESS) { - motor_temp = pm100_ptr->temp3.pm100_motor_temperature; + motor_temp = (int16_t)can_t_pm100_temperature_set_3_pm100_motor_temperature_decode( + pm100_ptr->temp3.pm100_motor_temperature); tx_mutex_put(&pm100_ptr->state_mutex); } @@ -364,7 +371,7 @@ int16_t pm100_motor_temp(pm100_context_t* pm100_ptr) return motor_temp; } -int16_t pm100_motor_speed(pm100_context_t* pm100_ptr) +int16_t pm100_motor_speed(pm100_context_t *pm100_ptr) { int16_t speed = 0; @@ -379,7 +386,47 @@ int16_t pm100_motor_speed(pm100_context_t* pm100_ptr) return speed; } -status_t pm100_lvs_off(pm100_context_t* pm100_ptr) +float pm100_electrical_power_w(pm100_context_t *pm100_ptr) +{ + // return infinity on failure + float power_w = INFINITY; + + UINT tx_status = tx_mutex_get(&pm100_ptr->state_mutex, 100); + + if (tx_status == TX_SUCCESS) + { + float voltage = (float)can_t_pm100_voltage_info_pm100_dc_bus_voltage_decode( + pm100_ptr->voltage_info.pm100_dc_bus_voltage); + float current = (float)can_t_pm100_current_info_pm100_dc_bus_current_decode( + pm100_ptr->current_info.pm100_dc_bus_current); + + power_w = voltage * current; + tx_mutex_put(&pm100_ptr->state_mutex); + } + else + { + LOG_ERROR("Failed to get electrical power\n"); + } + + return power_w; +} + +/** + * @brief Clears the latched PM100 error flags + * @param[in] pm100_ptr PM100 context + */ +void pm100_clear_error(pm100_context_t *pm100_ptr) +{ + UINT tx_status = tx_mutex_get(&pm100_ptr->state_mutex, 100); + + if (tx_status == TX_SUCCESS) + { + pm100_ptr->error = PM100_ERROR_NONE; + tx_mutex_put(&pm100_ptr->state_mutex); + } +} + +status_t pm100_lvs_off(pm100_context_t *pm100_ptr) { return STATUS_OK; } @@ -392,15 +439,15 @@ status_t pm100_lvs_off(pm100_context_t* pm100_ptr) * * @param[in] pm100_ptr */ -status_t pm100_disable(pm100_context_t* pm100_ptr) +status_t pm100_disable(pm100_context_t *pm100_ptr) { LOG_INFO("Sending PM100 Disable command\n"); - rtcan_msg_t msg = {.identifier = CAN_C_PM100_COMMAND_MESSAGE_FRAME_ID, - .length = CAN_C_PM100_COMMAND_MESSAGE_LENGTH, - .extended = CAN_C_PM100_COMMAND_MESSAGE_IS_EXTENDED, - .data = {0, 0, 0, 0, 0, 0, 0, 0}}; + rtcan_msg_t msg = { .identifier = CAN_T_PM100_COMMAND_MESSAGE_FRAME_ID, + .length = CAN_T_PM100_COMMAND_MESSAGE_LENGTH, + .extended = CAN_T_PM100_COMMAND_MESSAGE_IS_EXTENDED, + .data = { 0, 0, 0, 0, 0, 0, 0, 0 } }; - rtcan_status_t status = rtcan_transmit(pm100_ptr->rtcan_c_ptr, &msg); + rtcan_status_t status = rtcan_transmit(pm100_ptr->rtcan_t_ptr, &msg); return (status == RTCAN_OK) ? STATUS_OK : STATUS_ERROR; } @@ -419,32 +466,29 @@ status_t pm100_disable(pm100_context_t* pm100_ptr) * @param[in] pm100_ptr PM100 context * @param[in] torque Desired torque */ -status_t pm100_request_torque(pm100_context_t* pm100_ptr, uint16_t torque) +status_t pm100_request_torque(pm100_context_t *pm100_ptr, uint16_t torque) { status_t status = STATUS_OK; - const bool is_precharged = pm100_is_precharged( - pm100_ptr); // do this before getting mutex to avoid deadlock + const bool is_precharged = + pm100_is_precharged(pm100_ptr); // do this before getting mutex to avoid deadlock const bool no_errors = (pm100_ptr->error == PM100_ERROR_NONE); - UINT tx_status - = tx_mutex_get(&pm100_ptr->state_mutex, - pm100_ptr->config_ptr->torque_request_timeout_ticks); + UINT tx_status = tx_mutex_get(&pm100_ptr->state_mutex, + pm100_ptr->config_ptr->torque_request_timeout_ticks); if (no_errors && is_precharged && tx_status == TX_SUCCESS) { if (pm100_ptr->broadcasts_valid) { - if (pm100_ptr->states.pm100_inverter_enable_lockout - == PM100_LOCKOUT_DISABLED) + if (pm100_ptr->states.pm100_inverter_enable_lockout == PM100_LOCKOUT_DISABLED) { bool inverter_enable = PM100_INVERTER_ON; - rtcan_msg_t msg - = {.identifier = CAN_C_PM100_COMMAND_MESSAGE_FRAME_ID, - .length = CAN_C_PM100_COMMAND_MESSAGE_LENGTH, - .extended = CAN_C_PM100_COMMAND_MESSAGE_IS_EXTENDED, - .data = {0, 0, 0, 0, 0, 0, 0, 0}}; + rtcan_msg_t msg = { .identifier = CAN_T_PM100_COMMAND_MESSAGE_FRAME_ID, + .length = CAN_T_PM100_COMMAND_MESSAGE_LENGTH, + .extended = CAN_T_PM100_COMMAND_MESSAGE_IS_EXTENDED, + .data = { 0, 0, 0, 0, 0, 0, 0, 0 } }; uint16_t speed = pm100_motor_speed(pm100_ptr); if (torque == 0 && speed < 10) @@ -452,17 +496,21 @@ status_t pm100_request_torque(pm100_context_t* pm100_ptr, uint16_t torque) inverter_enable = PM100_INVERTER_OFF; } - struct can_c_pm100_command_message_t cmd - = {.pm100_torque_command = torque, - .pm100_direction_command = PM100_DIRECTION_REVERSE, - .pm100_speed_mode_enable = PM100_SPEED_MODE_DISABLE, - .pm100_inverter_enable = inverter_enable}; + struct can_t_pm100_command_message_t cmd = { + .pm100_torque_command = torque, + // motor is connected backwards so needs to be flipped here + .pm100_direction_command = pm100_ptr->reverse_mode_dangerous ? + PM100_DIRECTION_FORWARD : + PM100_DIRECTION_REVERSE, + .pm100_speed_mode_enable = PM100_SPEED_MODE_DISABLE, + .pm100_inverter_enable = inverter_enable + }; - can_c_pm100_command_message_pack(msg.data, &cmd, msg.length); + can_t_pm100_command_message_pack(msg.data, &cmd, msg.length); LOG_INFO("Sending torque request\n"); - rtcan_status_t rtcan_status - = rtcan_transmit(pm100_ptr->rtcan_c_ptr, &msg); + rtcan_status_t rtcan_status = + rtcan_transmit(pm100_ptr->rtcan_t_ptr, &msg); status = (rtcan_status == RTCAN_OK) ? STATUS_OK : STATUS_ERROR; } else @@ -473,12 +521,12 @@ status_t pm100_request_torque(pm100_context_t* pm100_ptr, uint16_t torque) } } - (void) tx_mutex_put(&pm100_ptr->state_mutex); + (void)tx_mutex_put(&pm100_ptr->state_mutex); } else { LOG_ERROR("Failed to send torque request\n"); - (void) pm100_disable(pm100_ptr); // just in case + (void)pm100_disable(pm100_ptr); // just in case status = STATUS_ERROR; } diff --git a/src/SUFST/Src/Services/remote_ctrl.c b/src/SUFST/Src/Services/remote_ctrl.c index 579ea25a..34e350d4 100644 --- a/src/SUFST/Src/Services/remote_ctrl.c +++ b/src/SUFST/Src/Services/remote_ctrl.c @@ -6,15 +6,14 @@ ****************************************************************************/ #include "remote_ctrl.h" -#include "clip_to_range.h" static void remote_ctrl_thread_entry(ULONG input); static status_t lock_sim_sensors(remote_ctrl_context_t *remote_ctrl_ptr, uint32_t timeout); static void unlock_sim_sensors(remote_ctrl_context_t *remote_ctrl_ptr); -static void process_broadcast(remote_ctrl_context_t *remote_ctrl_ptr, const rtcan_msg_t *msg_ptr); void reset_remote_ctrl_requests(remote_ctrl_context_t *remote_ctrl_ptr); -#define BPS_LIGHT_THRESH 5 +static void process_broadcast(remote_ctrl_context_t *remote_ctrl_ptr, + const rtcan_msg_t *msg_ptr); status_t remote_ctrl_init(remote_ctrl_context_t *remote_ctrl_ptr, canbc_context_t *canbc_ptr, @@ -25,39 +24,36 @@ status_t remote_ctrl_init(remote_ctrl_context_t *remote_ctrl_ptr, remote_ctrl_ptr->config_ptr = config_ptr; remote_ctrl_ptr->rtcan_s_ptr = rtcan_s_prt; remote_ctrl_ptr->canbc_ptr = canbc_ptr; - can_s_vcu_simulate_init(&remote_ctrl_ptr->requests); + remote_ctrl_ptr->requests = (struct can_s_vcu_simulation_t){ 0 }; status_t status = STATUS_OK; // create service thread void *stack_ptr = NULL; - UINT tx_status = tx_byte_allocate(stack_pool_ptr, - &stack_ptr, - config_ptr->thread.stack_size, - TX_NO_WAIT); + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); if (tx_status == TX_SUCCESS) { - tx_status = tx_thread_create(&remote_ctrl_ptr->thread, - (CHAR *)config_ptr->thread.name, - remote_ctrl_thread_entry, - (ULONG)remote_ctrl_ptr, - stack_ptr, - config_ptr->thread.stack_size, - config_ptr->thread.priority, - config_ptr->thread.priority, - TX_NO_TIME_SLICE, - TX_AUTO_START); + tx_status = + tx_thread_create(&remote_ctrl_ptr->thread, + (CHAR *)config_ptr->thread.name, + remote_ctrl_thread_entry, (ULONG)remote_ctrl_ptr, + stack_ptr, config_ptr->thread.stack_size, + config_ptr->thread.priority, config_ptr->thread.priority, + TX_NO_TIME_SLICE, TX_AUTO_START); } // create CAN receive queue if (tx_status == TX_SUCCESS) { - tx_status = tx_queue_create(&remote_ctrl_ptr->can_rx_queue, - NULL, - TX_1_ULONG, - remote_ctrl_ptr->can_rx_queue_mem, - sizeof(remote_ctrl_ptr->can_rx_queue_mem)); + if (rtcan_os_queue_create(&remote_ctrl_ptr->can_rx_queue, NULL, + sizeof(rtcan_msg_t *), REMOTE_CTRL_RX_QUEUE_SIZE, + remote_ctrl_ptr->can_rx_queue_mem, + sizeof(remote_ctrl_ptr->can_rx_queue_mem)) != RTCAN_OS_OK) + { + tx_status = TX_START_ERROR; + } } // create state mutex @@ -82,71 +78,52 @@ status_t remote_ctrl_init(remote_ctrl_context_t *remote_ctrl_ptr, static void remote_ctrl_thread_entry(ULONG input) { + remote_ctrl_context_t *remote_ctrl_ptr = (remote_ctrl_context_t *)input; + const config_remote_ctrl_t *config_ptr = remote_ctrl_ptr->config_ptr; - #ifndef VCU_SIMULATION_MODE - #else - remote_ctrl_context_t *remote_ctrl_ptr = (remote_ctrl_context_t *)input; - const config_remote_ctrl_t *config_ptr = remote_ctrl_ptr->config_ptr; + uint32_t rtcan_channel = CAN_S_VCU_SIMULATION_FRAME_ID; - uint32_t rtcan_channel = CAN_S_VCU_SIMULATION_FRAME_ID; + rtcan_status_t status = rtcan_subscribe(remote_ctrl_ptr->rtcan_s_ptr, rtcan_channel, + remote_ctrl_ptr->can_rx_queue); + + if (status != RTCAN_OK) + { + LOG_ERROR("Failed to subscribe to the CAN_S_VCU_SIMULATION message"); + tx_thread_terminate(&remote_ctrl_ptr->thread); + } - rtcan_status_t status = rtcan_subscribe(remote_ctrl_ptr->rtcan_s_ptr, - rtcan_channel, - &remote_ctrl_ptr->can_rx_queue); + while (1) + { + rtcan_msg_t *msg_ptr = NULL; + rtcan_osal_status_t rec_status = + rtcan_os_queue_receive(remote_ctrl_ptr->can_rx_queue, &msg_ptr, + config_ptr->broadcast_timeout_ticks); - if (status != RTCAN_OK) + if (rec_status == RTCAN_OS_OK && msg_ptr != NULL) + { + if (lock_sim_sensors(remote_ctrl_ptr, 100) == STATUS_OK) { - LOG_ERROR( "Failed to subscribe to the CAN_S_VCU_SIMULATION message"); - tx_thread_terminate(&remote_ctrl_ptr->thread); + process_broadcast(remote_ctrl_ptr, msg_ptr); + rtcan_msg_consumed(remote_ctrl_ptr->rtcan_s_ptr, msg_ptr); + unlock_sim_sensors(remote_ctrl_ptr); } - - while (1) + else { - rtcan_msg_t *msg_ptr = NULL; - UINT status = tx_queue_receive(&remote_ctrl_ptr->can_rx_queue, - &msg_ptr, - config_ptr->broadcast_timeout_ticks); - - if (status == TX_SUCCESS && msg_ptr != NULL) - { - if (lock_sim_sensors(remote_ctrl_ptr, 100) == STATUS_OK) - { - process_broadcast(remote_ctrl_ptr, msg_ptr); - rtcan_msg_consumed(remote_ctrl_ptr->rtcan_s_ptr, msg_ptr); - remote_ctrl_ptr->brakelight_pwr = (remote_ctrl_ptr->requests.sim_bps > BPS_LIGHT_THRESH); - unlock_sim_sensors(remote_ctrl_ptr); - } - else - { - LOG_ERROR( "Error locking sensors\n"); - } - } - else if (status != TX_SUCCESS && msg_ptr == NULL) - { - if (status == TX_QUEUE_EMPTY) - { - LOG_ERROR("TX Broadcast Error & Msg_ptr is null\n"); - } - else - { - LOG_ERROR("TX Error & Msg_ptr is null\n"); - } - reset_remote_ctrl_requests(remote_ctrl_ptr); - } - else if (status == TX_QUEUE_EMPTY) - { - LOG_ERROR("Broadcast timeout\n"); - reset_remote_ctrl_requests(remote_ctrl_ptr); - } - else - { - LOG_ERROR("Broadcast Error\n"); - reset_remote_ctrl_requests(remote_ctrl_ptr); - } - remote_ctrl_update_canbc_states(remote_ctrl_ptr); - tx_thread_sleep(config_ptr->period); + LOG_ERROR("Error locking sensors\n"); } - #endif + } + else if (rec_status == RTCAN_OS_TIMEOUT) + { + LOG_ERROR("Broadcast timeout\n"); + reset_remote_ctrl_requests(remote_ctrl_ptr); + } + else + { + LOG_ERROR("Broadcast Error: %d\n", rec_status); + reset_remote_ctrl_requests(remote_ctrl_ptr); + } + tx_thread_sleep(config_ptr->period); + } } static status_t lock_sim_sensors(remote_ctrl_context_t *remote_ctrl_ptr, uint32_t timeout) @@ -187,49 +164,15 @@ uint16_t remote_get_torque_reading(remote_ctrl_context_t *remote_ctrl_ptr) return result; } -status_t remote_get_bps_reading(remote_ctrl_context_t *remote_ctrl_ptr, uint16_t *result) -{ - status_t status = STATUS_ERROR; - - if (lock_sim_sensors(remote_ctrl_ptr, 100) == STATUS_OK) - { - *result = remote_ctrl_ptr->requests.sim_bps; - status = STATUS_OK; - unlock_sim_sensors(remote_ctrl_ptr); - } - else - { - LOG_ERROR("BPS locking error\n"); - } - - return status; -} - -status_t remote_get_apps_reading(remote_ctrl_context_t *remote_ctrl_ptr, uint16_t *result) -{ - status_t status = STATUS_ERROR; - - if (lock_sim_sensors(remote_ctrl_ptr, 100) == STATUS_OK) - { - *result = remote_ctrl_ptr->requests.sim_apps; - status = STATUS_OK; - unlock_sim_sensors(remote_ctrl_ptr); - } - else - { - LOG_ERROR("APPS locking error\n"); - } - - return status; -} - -uint8_t remote_get_ts_on_reading(remote_ctrl_context_t *remote_ctrl_ptr) +uint8_t remote_get_ts_on_pressed(remote_ctrl_context_t *remote_ctrl_ptr) { uint8_t result = 0u; if (lock_sim_sensors(remote_ctrl_ptr, 100) == STATUS_OK) { - result = remote_ctrl_ptr->requests.sim_ts_on; + bool state = remote_ctrl_ptr->requests.sim_ts_on; + result = state && !remote_ctrl_ptr->ts_on_prev; + remote_ctrl_ptr->ts_on_prev = state; unlock_sim_sensors(remote_ctrl_ptr); } else @@ -240,18 +183,20 @@ uint8_t remote_get_ts_on_reading(remote_ctrl_context_t *remote_ctrl_ptr) return result; } -uint8_t remote_get_r2d_reading(remote_ctrl_context_t *remote_ctrl_ptr) +uint8_t remote_get_r2d_pressed(remote_ctrl_context_t *remote_ctrl_ptr) { uint8_t result = 0u; if (lock_sim_sensors(remote_ctrl_ptr, 100) == STATUS_OK) { - result = remote_ctrl_ptr->requests.sim_r2_d; - if (!can_s_vcu_state_vcu_r2_d_is_in_range(result)) + bool state = remote_ctrl_ptr->requests.sim_r2_d; + if (!can_t_vcu_state_vcu_r2_d_is_in_range(state)) { LOG_WARN("R2D requested is over the limit, setting it to 0\n"); - result = 0u; + state = false; } + result = state && !remote_ctrl_ptr->r2d_prev; + remote_ctrl_ptr->r2d_prev = state; unlock_sim_sensors(remote_ctrl_ptr); } else @@ -262,36 +207,17 @@ uint8_t remote_get_r2d_reading(remote_ctrl_context_t *remote_ctrl_ptr) return result; } -void remote_ctrl_update_canbc_states(remote_ctrl_context_t *remote_ctrl_ptr) -{ - canbc_states_t *states = canbc_lock_state(remote_ctrl_ptr->canbc_ptr, TX_NO_WAIT); - - if (states != NULL) - { - states->pdm.brakelight = remote_ctrl_ptr->brakelight_pwr; - states->sensors.vcu_apps = remote_ctrl_ptr->requests.sim_apps; - states->sensors.vcu_bps = remote_ctrl_ptr->requests.sim_bps; - canbc_unlock_state(remote_ctrl_ptr->canbc_ptr); - } - else - { - LOG_ERROR("CANBC locking failure\n"); - } -} - void process_broadcast(remote_ctrl_context_t *remote_ctrl_ptr, const rtcan_msg_t *msg_ptr) { switch (msg_ptr->identifier) { case CAN_S_VCU_SIMULATION_FRAME_ID: { - can_s_vcu_simulation_unpack(&remote_ctrl_ptr->requests, - msg_ptr->data, + can_s_vcu_simulation_unpack(&remote_ctrl_ptr->requests, msg_ptr->data, msg_ptr->length); break; } - default: - break; + default: break; } } @@ -299,28 +225,13 @@ void reset_remote_ctrl_requests(remote_ctrl_context_t *remote_ctrl_ptr) { if (lock_sim_sensors(remote_ctrl_ptr, 100) == STATUS_OK) { - can_s_vcu_simulate_init(&remote_ctrl_ptr->requests); + remote_ctrl_ptr->requests = (struct can_s_vcu_simulation_t){ 0 }; + remote_ctrl_ptr->ts_on_prev = false; + remote_ctrl_ptr->r2d_prev = false; unlock_sim_sensors(remote_ctrl_ptr); } else { LOG_ERROR("Error locking sensors\n"); } -} - -uint16_t remote_get_power_reading(remote_ctrl_context_t *remote_ctrl_ptr) -{ - uint16_t result = 0; // Set initial power to 0 - - if (lock_sim_sensors(remote_ctrl_ptr, 100) == STATUS_OK) - { - result = remote_ctrl_ptr->requests.sim_power; - unlock_sim_sensors(remote_ctrl_ptr); - } - else - { - LOG_ERROR("Power locking error\n"); - } - - return result; } \ No newline at end of file diff --git a/src/SUFST/Src/Services/sd_logging.c b/src/SUFST/Src/Services/sd_logging.c new file mode 100644 index 00000000..d0e6a035 --- /dev/null +++ b/src/SUFST/Src/Services/sd_logging.c @@ -0,0 +1,162 @@ +#include "sd_logging.h" + +#include +#include + +#include "log.h" +#include "main.h" + +static sd_context_t *global_sd_context; + +static void sd_thread_entry(ULONG input); + +static bool sd_is_connected() +{ + // SD_CARD_DETECT has an external pullup, so is LOW if the SD card is inserted + return !HAL_GPIO_ReadPin(SD_CARD_DETECT_GPIO_Port, SD_CARD_DETECT_Pin); +} + +static UINT create_log_file(sd_context_t *sd) +{ + char fname[16]; + sd->log_filename[0] = '\0'; + + for (UINT n = 1; n <= 999; n++) + { + snprintf(fname, sizeof(fname), "log_%u.txt", n); + FX_FILE test; + UINT s = fx_file_open(&sd->sd_media, &test, fname, FX_OPEN_FOR_READ); + if (s == FX_NOT_FOUND) + { + strncpy(sd->log_filename, fname, sizeof(sd->log_filename) - 1); + break; + } + if (s == FX_SUCCESS) + { + fx_file_close(&test); + continue; + } + return s; + } + + if (sd->log_filename[0] == '\0') + return FX_NO_MORE_SPACE; + + UINT s = fx_file_create(&sd->sd_media, sd->log_filename); + if (s != FX_SUCCESS && s != FX_ALREADY_CREATED) + return s; + + return fx_file_open(&sd->sd_media, &sd->log_file, sd->log_filename, FX_OPEN_FOR_WRITE); +} + +status_t sd_init(sd_context_t *sd, TX_BYTE_POOL *stack_pool_ptr, const config_sd_t *config_ptr) +{ + sd->config_ptr = config_ptr; + + if (!config_ptr->enable) + { + LOG_INFO("SD card disabled in config\n"); + return STATUS_OK; + } + + if (!sd_is_connected()) + { + LOG_ERROR("SD card not detected!\n"); + return STATUS_OK; + } + + LOG_INFO("Enabling SD card\n"); + + void *stack_ptr = NULL; + LOG_INFO("SD: allocate stack\n"); + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); + + if (tx_status == TX_SUCCESS) + { + LOG_INFO("SD: allocate queue\n"); + tx_status = tx_queue_create(&sd->msg_queue, NULL, SD_LOG_MSG_SIZE_ULONG, + sd->msg_queue_mem, sizeof(sd->msg_queue_mem)); + } + + if (tx_status == TX_SUCCESS) + { + LOG_INFO("SD: allocate thread\n"); + tx_status = + tx_thread_create(&sd->thread, (CHAR *)config_ptr->thread.name, sd_thread_entry, + (ULONG)sd, stack_ptr, config_ptr->thread.stack_size, + config_ptr->thread.priority, config_ptr->thread.priority, + TX_NO_TIME_SLICE, TX_AUTO_START); + } + + if (tx_status != TX_SUCCESS) + { + LOG_ERROR("SD init failure\n"); + return STATUS_ERROR; + } + + // Set global context only after queue is initialised + global_sd_context = sd; + + LOG_INFO("SD card init success\n"); + + return STATUS_OK; +} + +void write_sd_log_line(const char *line) +{ + if (global_sd_context == NULL) + return; + + char buf[LOG_MSG_MAX_TRANSMITION_LEN]; + strncpy(buf, line, sizeof(buf) - 1); + buf[sizeof(buf) - 1] = '\0'; + + tx_queue_send(&global_sd_context->msg_queue, buf, TX_NO_WAIT); +} + +static void sd_thread_entry(ULONG input) +{ + sd_context_t *sd = (sd_context_t *)input; + + UINT s = fx_media_open(&sd->sd_media, "SD", fx_stm32_sd_driver, NULL, + sd->media_buffer, sizeof(sd->media_buffer)); + + if (s != FX_SUCCESS) + { + LOG_ERROR("SD: fx_media_open failed (%u)\n", s); + return; + } + + s = create_log_file(sd); + if (s != FX_SUCCESS) + { + LOG_ERROR("SD: failed to create log file (%u)\n", s); + fx_media_close(&sd->sd_media); + return; + } + + LOG_INFO("SD: logging to %s\n", sd->log_filename); + + char line[LOG_MSG_MAX_TRANSMITION_LEN]; + UINT write_status; + + while (1) + { + while (tx_queue_receive(&sd->msg_queue, line, TX_NO_WAIT) == TX_SUCCESS) + { + write_status = fx_file_write(&sd->log_file, line, strlen(line)); + if (write_status != FX_SUCCESS) + { + global_sd_context = NULL; + LOG_ERROR("SD: fx_file_write failed (%u)\n", write_status); + fx_file_close(&sd->log_file); + fx_media_close(&sd->sd_media); + return; + } + } + + fx_media_flush(&sd->sd_media); + tx_thread_sleep(sd->config_ptr->flush_period_ticks); + } +} diff --git a/src/SUFST/Src/Services/tick.c b/src/SUFST/Src/Services/tick.c index 71fda994..e2ca3501 100644 --- a/src/SUFST/Src/Services/tick.c +++ b/src/SUFST/Src/Services/tick.c @@ -1,59 +1,83 @@ #include "tick.h" -#define BPS_LIGHT_THRESH 40 - -static status_t lock_tick_sensors(tick_context_t* tick_ptr, uint32_t timeout); -static void unlock_tick_sensors(tick_context_t* tick_ptr); -void tick_update_canbc_states(tick_context_t* tick_ptr); +static status_t lock_tick_sensors(tick_context_t *tick_ptr, uint32_t timeout); +static void unlock_tick_sensors(tick_context_t *tick_ptr); +void tick_update_canbc_states(tick_context_t *tick_ptr); static void tick_thread_entry(ULONG input) { - tick_context_t* tick_ptr = (tick_context_t*) input; - const config_tick_t* config_ptr = tick_ptr->config_ptr; + tick_context_t *tick_ptr = (tick_context_t *)input; + const config_tick_t *config_ptr = tick_ptr->config_ptr; while (1) { lock_tick_sensors(tick_ptr, 100); tick_ptr->bps_status = bps_read(&tick_ptr->bps, &tick_ptr->bps_reading); - tick_ptr->brakelight_pwr = (tick_ptr->bps_reading > BPS_LIGHT_THRESH); - tick_ptr->apps_status - = apps_read(&tick_ptr->apps, &tick_ptr->apps_reading); + bool bps_above_threshold = (tick_ptr->bps_reading > config_ptr->bps_light_threshold); + + if (bps_above_threshold && !tick_ptr->bps_prev_above) + { + tick_ptr->bps_active_start = tx_time_get(); + } + else if (bps_above_threshold) + { + uint32_t active_ticks = tx_time_get() - tick_ptr->bps_active_start; + tick_ptr->brakelight_pwr = (active_ticks >= config_ptr->bps_active_ticks); + } + else + { + tick_ptr->brakelight_pwr = false; + } + + tick_ptr->bps_prev_above = bps_above_threshold; + + tick_ptr->apps_status = apps_read(&tick_ptr->apps, &tick_ptr->apps_reading); + + tick_ptr->sagl_status = scs_read(&tick_ptr->sagl, &tick_ptr->sagl_reading); + tick_ptr->current_status = scs_read(&tick_ptr->current, &tick_ptr->current_reading); + tick_ptr->mode_adc_status = + scs_read(&tick_ptr->mode_adc, &tick_ptr->mode_adc_reading); -/*LOG_INFO(tick_ptr->log_ptr, "Brake pressure: %d status: %d\n", - tick_ptr->bps_reading, tick_ptr->bps_status);*/ -/*LOG_INFO(tick_ptr->log_ptr, "APPS: %d status: %d\n", - tick_ptr->apps_reading, tick_ptr->apps_status);*/ -#ifndef VCU_SIMULATION_MODE + /*LOG_INFO(tick_ptr->log_ptr, "Brake pressure: %d status: %d\n", + tick_ptr->bps_reading, tick_ptr->bps_status);*/ + /*LOG_INFO(tick_ptr->log_ptr, "APPS: %d status: %d\n", + tick_ptr->apps_reading, tick_ptr->apps_status);*/ tick_update_canbc_states(tick_ptr); -#endif unlock_tick_sensors(tick_ptr); tx_thread_sleep(config_ptr->period); } } -status_t tick_init(tick_context_t* tick_ptr, - canbc_context_t* canbc_ptr, - TX_BYTE_POOL* stack_pool_ptr, - const config_tick_t* config_ptr, - const config_apps_t* apps_config_ptr, - const config_bps_t* bps_config_ptr) +status_t tick_init(tick_context_t *tick_ptr, + canbc_context_t *canbc_ptr, + TX_BYTE_POOL *stack_pool_ptr, + const config_tick_t *config_ptr, + const config_apps_t *apps_config_ptr, + const config_bps_t *bps_config_ptr, + const config_ext_inputs_t *ext_inputs_config_ptr) { tick_ptr->config_ptr = config_ptr; + tick_ptr->ext_inputs_config_ptr = ext_inputs_config_ptr; tick_ptr->canbc_ptr = canbc_ptr; // Assume error so that it won't proceed without at least 1 reading tick_ptr->bps_status = STATUS_ERROR; tick_ptr->apps_status = STATUS_ERROR; + tick_ptr->sagl_status = STATUS_ERROR; + tick_ptr->current_status = STATUS_ERROR; + tick_ptr->mode_adc_status = STATUS_ERROR; + + tick_ptr->brakelight_pwr = false; + tick_ptr->bps_prev_above = false; + tick_ptr->bps_active_start = 0; status_t status = STATUS_OK; - void* stack_ptr = NULL; - UINT tx_status = tx_byte_allocate(stack_pool_ptr, - &stack_ptr, - config_ptr->thread.stack_size, - TX_NO_WAIT); + void *stack_ptr = NULL; + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); // create state mutex if (tx_status == TX_SUCCESS) { @@ -70,18 +94,28 @@ status_t tick_init(tick_context_t* tick_ptr, status = bps_init(&tick_ptr->bps, bps_config_ptr); } + if (status == STATUS_OK) + { + status = scs_create(&tick_ptr->sagl, &ext_inputs_config_ptr->sagl); + } + + if (status == STATUS_OK) + { + status = scs_create(&tick_ptr->current, &ext_inputs_config_ptr->current); + } + + if (status == STATUS_OK) + { + status = scs_create(&tick_ptr->mode_adc, &ext_inputs_config_ptr->mode_switch); + } + if (tx_status == TX_SUCCESS) { - tx_status = tx_thread_create(&tick_ptr->thread, - (CHAR*) config_ptr->thread.name, - tick_thread_entry, - (ULONG) tick_ptr, - stack_ptr, - config_ptr->thread.stack_size, - config_ptr->thread.priority, - config_ptr->thread.priority, - TX_NO_TIME_SLICE, - TX_AUTO_START); + tx_status = + tx_thread_create(&tick_ptr->thread, (CHAR *)config_ptr->thread.name, + tick_thread_entry, (ULONG)tick_ptr, stack_ptr, + config_ptr->thread.stack_size, config_ptr->thread.priority, + config_ptr->thread.priority, TX_NO_TIME_SLICE, TX_AUTO_START); } if (tx_status != TX_SUCCESS) { @@ -97,20 +131,25 @@ status_t tick_init(tick_context_t* tick_ptr, return status; } -void tick_update_canbc_states(tick_context_t* tick_ptr) +void tick_update_canbc_states(tick_context_t *tick_ptr) { - canbc_states_t* states = canbc_lock_state(tick_ptr->canbc_ptr, TX_NO_WAIT); + canbc_states_t *states = canbc_lock_state(tick_ptr->canbc_ptr, TX_NO_WAIT); if (states != NULL) { states->pdm.brakelight = tick_ptr->brakelight_pwr; + states->errors.vcu_scs_error = (uint8_t)tick_ptr->apps.scs_error; states->sensors.vcu_apps = tick_ptr->apps_reading; states->sensors.vcu_bps = tick_ptr->bps_reading; + states->sensors_raw.vcu_apps1_raw = tick_ptr->apps.apps_1_signal.adc_reading; + states->sensors_raw.vcu_apps2_raw = tick_ptr->apps.apps_2_signal.adc_reading; + states->sensors_raw.vcu_bps_raw = tick_ptr->bps.signal.adc_reading; + states->sensors_raw.vcu_current_raw = tick_ptr->current.adc_reading; canbc_unlock_state(tick_ptr->canbc_ptr); } } -static status_t lock_tick_sensors(tick_context_t* tick_ptr, uint32_t timeout) +static status_t lock_tick_sensors(tick_context_t *tick_ptr, uint32_t timeout) { UINT tx_status = tx_mutex_get(&tick_ptr->sensor_mutex, timeout); @@ -124,12 +163,12 @@ static status_t lock_tick_sensors(tick_context_t* tick_ptr, uint32_t timeout) } } -static void unlock_tick_sensors(tick_context_t* tick_ptr) +static void unlock_tick_sensors(tick_context_t *tick_ptr) { tx_mutex_put(&tick_ptr->sensor_mutex); } -status_t tick_get_bps_reading(tick_context_t* tick_ptr, uint16_t* result) +status_t tick_get_bps_reading(tick_context_t *tick_ptr, uint16_t *result) { status_t status = STATUS_ERROR; @@ -147,7 +186,7 @@ status_t tick_get_bps_reading(tick_context_t* tick_ptr, uint16_t* result) return status; } -status_t tick_get_apps_reading(tick_context_t* tick_ptr, uint16_t* result) +status_t tick_get_apps_reading(tick_context_t *tick_ptr, uint16_t *result) { status_t status = STATUS_ERROR; @@ -164,3 +203,74 @@ status_t tick_get_apps_reading(tick_context_t* tick_ptr, uint16_t* result) return status; } + +status_t tick_clear_apps_scs_error(tick_context_t *tick_ptr) +{ + status_t status = lock_tick_sensors(tick_ptr, 100); + + if (status == STATUS_OK) + { + tick_ptr->apps.scs_error = SCS_ERROR_NONE; + unlock_tick_sensors(tick_ptr); + } + else + { + LOG_ERROR("APPS locking error\n"); + } + + return status; +} + +status_t tick_get_sagl_reading(tick_context_t *tick_ptr, uint16_t *result) +{ + status_t status = STATUS_ERROR; + + if (lock_tick_sensors(tick_ptr, 100) == STATUS_OK) + { + *result = tick_ptr->sagl_reading; + status = tick_ptr->sagl_status; + unlock_tick_sensors(tick_ptr); + } + else + { + LOG_ERROR("SAGL locking error\n"); + } + + return status; +} + +status_t tick_get_current_reading(tick_context_t *tick_ptr, uint16_t *result) +{ + status_t status = STATUS_ERROR; + + if (lock_tick_sensors(tick_ptr, 100) == STATUS_OK) + { + *result = tick_ptr->current_reading; + status = tick_ptr->current_status; + unlock_tick_sensors(tick_ptr); + } + else + { + LOG_ERROR("Current locking error\n"); + } + + return status; +} + +status_t tick_get_mode_adc_reading(tick_context_t *tick_ptr, uint16_t *result) +{ + status_t status = STATUS_ERROR; + + if (lock_tick_sensors(tick_ptr, 100) == STATUS_OK) + { + *result = tick_ptr->mode_adc_reading; + status = tick_ptr->mode_adc_status; + unlock_tick_sensors(tick_ptr); + } + else + { + LOG_ERROR("Mode switch locking error\n"); + } + + return status; +} diff --git a/src/SUFST/Src/Services/wheelspeed.c b/src/SUFST/Src/Services/wheelspeed.c new file mode 100644 index 00000000..9c5e92f7 --- /dev/null +++ b/src/SUFST/Src/Services/wheelspeed.c @@ -0,0 +1,177 @@ +#include "wheelspeed.h" + +#include "log.h" +#include "main.h" +#include + +static void wheelspeed_thread_entry(ULONG input); +static void wheelspeed_timer_callback(ULONG input); +static void compute_and_broadcast(wheelspeed_context_t *wh); +static float compute_wheel_rpm(wheel_state_t *wheel, const config_wheelspeed_t *config); + +status_t wheelspeed_init(wheelspeed_context_t *wh, + rtcan_handle_t *rtcan_h, + TX_BYTE_POOL *stack_pool_ptr, + const config_wheelspeed_t *config_ptr) +{ + wh->config_ptr = config_ptr; + wh->rtcan_h = rtcan_h; + + void *stack_ptr = NULL; + UINT tx_status = tx_byte_allocate(stack_pool_ptr, &stack_ptr, + config_ptr->thread.stack_size, TX_NO_WAIT); + + if (tx_status == TX_SUCCESS) + { + tx_status = tx_mutex_create(&wh->reading_mutex, NULL, TX_INHERIT); + } + + if (tx_status == TX_SUCCESS) + { + tx_status = + tx_semaphore_create(&wh->sample_semaphore, (CHAR *)"wheelspeed_sem", 0); + } + + if (tx_status == TX_SUCCESS) + { + tx_status = tx_timer_create(&wh->sample_timer, (CHAR *)"wheelspeed_timer", + wheelspeed_timer_callback, (ULONG)wh, + config_ptr->sample_period_ticks, + config_ptr->sample_period_ticks, TX_AUTO_ACTIVATE); + } + + if (tx_status == TX_SUCCESS) + { + tx_status = + tx_thread_create(&wh->thread, (CHAR *)config_ptr->thread.name, + wheelspeed_thread_entry, (ULONG)wh, stack_ptr, + config_ptr->thread.stack_size, config_ptr->thread.priority, + config_ptr->thread.priority, TX_NO_TIME_SLICE, TX_AUTO_START); + } + + return (tx_status == TX_SUCCESS) ? STATUS_OK : STATUS_ERROR; +} + +static void wheelspeed_timer_callback(ULONG input) +{ + wheelspeed_context_t *wh = (wheelspeed_context_t *)input; + tx_semaphore_put(&wh->sample_semaphore); +} + +static void wheelspeed_thread_entry(ULONG input) +{ + wheelspeed_context_t *wh = (wheelspeed_context_t *)input; + + while (1) + { + tx_semaphore_get(&wh->sample_semaphore, TX_WAIT_FOREVER); + compute_and_broadcast(wh); + } +} + +static float compute_wheel_rpm(wheel_state_t *wheel, const config_wheelspeed_t *config) +{ + uint32_t current = wheel->isr_count; + uint32_t delta = current - wheel->prev_count; + wheel->prev_count = current; + + float revs_per_second = (float)delta * TX_TIMER_TICKS_PER_SECOND / + ((float)config->ticks_per_wheel * (float)config->sample_period_ticks); + return revs_per_second * 60.0; +} + +static void compute_and_broadcast(wheelspeed_context_t *wh) +{ + const config_wheelspeed_t *cfg = wh->config_ptr; + + float rpm_fr = compute_wheel_rpm(&wh->wheel_fr, cfg); + float rpm_fl = compute_wheel_rpm(&wh->wheel_fl, cfg); + float rpm_rr = compute_wheel_rpm(&wh->wheel_rr, cfg); + float rpm_rl = compute_wheel_rpm(&wh->wheel_rl, cfg); + + float mps_fr = rpm_fr / 60.0 * cfg->wheel_circumference_meters; + float mps_fl = rpm_fl / 60.0 * cfg->wheel_circumference_meters; + float mps_rr = rpm_rr / 60.0 * cfg->wheel_circumference_meters; + float mps_rl = rpm_rl / 60.0 * cfg->wheel_circumference_meters; + + if (tx_mutex_get(&wh->reading_mutex, 100) == TX_SUCCESS) + { + wh->last_reading.fl_mps = mps_fl; + wh->last_reading.fr_mps = mps_fr; + wh->last_reading.rl_mps = mps_rl; + wh->last_reading.rr_mps = mps_rr; + wh->last_reading.fl_rpm = rpm_fl; + wh->last_reading.fr_rpm = rpm_fr; + wh->last_reading.rl_rpm = rpm_rl; + wh->last_reading.rr_rpm = rpm_rr; + tx_mutex_put(&wh->reading_mutex); + } + else + { + LOG_ERROR("wheelspeed: reading locking error\n"); + } + + { + struct can_s_wheel_rpm_t data = { + .wheel_fr_rpm = can_s_wheel_rpm_wheel_fr_rpm_encode(rpm_fr), + .wheel_fl_rpm = can_s_wheel_rpm_wheel_fl_rpm_encode(rpm_fl), + .wheel_rr_rpm = can_s_wheel_rpm_wheel_rr_rpm_encode(rpm_rr), + .wheel_rl_rpm = can_s_wheel_rpm_wheel_rl_rpm_encode(rpm_rl), + }; + rtcan_msg_t msg = { + .identifier = CAN_S_WHEEL_RPM_FRAME_ID, + .length = CAN_S_WHEEL_RPM_LENGTH, + .extended = CAN_S_WHEEL_RPM_IS_EXTENDED, + }; + can_s_wheel_rpm_pack(msg.data, &data, msg.length); + if (rtcan_transmit(wh->rtcan_h, &msg) != RTCAN_OK) + LOG_ERROR("wheelspeed: failed to transmit RPM\n"); + } + + { + struct can_s_wheel_speeds_t data = { + .wheel_fr_speed = can_s_wheel_speeds_wheel_fr_speed_encode(mps_fr), + .wheel_fl_speed = can_s_wheel_speeds_wheel_fl_speed_encode(mps_fl), + .wheel_rr_speed = can_s_wheel_speeds_wheel_rr_speed_encode(mps_rr), + .wheel_rl_speed = can_s_wheel_speeds_wheel_rl_speed_encode(mps_rl), + }; + rtcan_msg_t msg = { + .identifier = CAN_S_WHEEL_SPEEDS_FRAME_ID, + .length = CAN_S_WHEEL_SPEEDS_LENGTH, + .extended = CAN_S_WHEEL_SPEEDS_IS_EXTENDED, + }; + can_s_wheel_speeds_pack(msg.data, &data, msg.length); + if (rtcan_transmit(wh->rtcan_h, &msg) != RTCAN_OK) + LOG_ERROR("wheelspeed: failed to transmit speeds\n"); + } +} + +void wheelspeed_handle_exti(wheelspeed_context_t *wh, uint16_t gpio_pin) +{ + if (gpio_pin == WHEELSPEED_FR_Pin) + wh->wheel_fr.isr_count++; + else if (gpio_pin == WHEELSPEED_FL_Pin) + wh->wheel_fl.isr_count++; + else if (gpio_pin == WHEELSPEED_RR_Pin) + wh->wheel_rr.isr_count++; + else if (gpio_pin == WHEELSPEED_RL_Pin) + wh->wheel_rl.isr_count++; +} + +status_t wheelspeed_get_speeds(wheelspeed_context_t *wh, wheelspeed_reading_t *result) +{ + status_t status = STATUS_ERROR; + + if (tx_mutex_get(&wh->reading_mutex, 100) == TX_SUCCESS) + { + *result = wh->last_reading; + status = STATUS_OK; + tx_mutex_put(&wh->reading_mutex); + } + else + { + LOG_ERROR("wheelspeed: reading locking error\n"); + } + + return status; +} diff --git a/src/SUFST/Src/Test/testbench.c b/src/SUFST/Src/Test/testbench.c index 10eb3534..420a1845 100644 --- a/src/SUFST/Src/Test/testbench.c +++ b/src/SUFST/Src/Test/testbench.c @@ -48,8 +48,8 @@ UINT testbench_apps_input() // work out which lookup table to use // -> standing start data in first lap // -> flying lap data for any further laps - const uint16_t* time_data; - const uint16_t* apps_data; + const uint16_t *time_data; + const uint16_t *apps_data; UINT final_lookup_index; { @@ -59,9 +59,9 @@ UINT testbench_apps_input() time_data = standing_start_time_lookup; apps_data = standing_start_apps_lookup; - final_lookup_index = (sizeof(standing_start_time_lookup) - / sizeof(standing_start_time_lookup[0])) - - 1; + final_lookup_index = (sizeof(standing_start_time_lookup) / + sizeof(standing_start_time_lookup[0])) - + 1; } // flying laps else @@ -69,15 +69,13 @@ UINT testbench_apps_input() time_data = flying_lap_time_lookup; apps_data = flying_lap_apps_lookup; - final_lookup_index = (sizeof(flying_lap_time_lookup) - / sizeof(flying_lap_time_lookup[0])) - - 1; + final_lookup_index = + (sizeof(flying_lap_time_lookup) / sizeof(flying_lap_time_lookup[0])) - 1; } } // timestamps in ms - const UINT current_time - = tx_time_get() * 1000 / TX_TIMER_TICKS_PER_SECOND; + const UINT current_time = tx_time_get() * 1000 / TX_TIMER_TICKS_PER_SECOND; const UINT lap_finish_time = time_data[final_lookup_index]; const UINT current_lap_time = current_time - last_lap_finish_time; @@ -102,7 +100,7 @@ UINT testbench_apps_input() // end of lap handling if (end_of_lap) { - end_of_lap = false; + // end_of_lap = false; lookup_index = 0; lap_count++; last_lap_finish_time = current_time; @@ -130,8 +128,8 @@ UINT testbench_apps_input() */ VOID testbench_fault_state() { - GPIO_PinState user_button_state - = HAL_GPIO_ReadPin(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin); + GPIO_PinState user_button_state = + HAL_GPIO_ReadPin(USER_BUTTON_GPIO_Port, USER_BUTTON_Pin); if (user_button_state == GPIO_PIN_SET) { diff --git a/src/SUFST/Src/config.c b/src/SUFST/Src/config.c index 99472197..fd1a8315 100644 --- a/src/SUFST/Src/config.c +++ b/src/SUFST/Src/config.c @@ -2,16 +2,16 @@ /** * @brief Convert seconds to ticks - * + * * @note The maximum precision is determined by how many ticks there are per * second. E.g. TX_TIMER_TICKS_PER_SECOND = 1000 gives down to 0.001s. * Antyhing less than this rounds down to zero ticks. */ -#define SECONDS_TO_TICKS(x) (TX_TIMER_TICKS_PER_SECOND * x) +#define SECONDS_TO_TICKS(x) (TX_TIMER_TICKS_PER_SECOND * x) /** * @brief VCU configuration instance - * + * * @details See definitions of parameters in config.h * * @note This struct is const, i.e. read only! The config should not change @@ -35,53 +35,58 @@ static const config_t config_instance = { .vc_stagger_ticks = SECONDS_TO_TICKS(0.25) }, .apps = { - /*.apps_1_scs = { - .hadc = &hadc1, - .min_adc = 0, - .max_adc = 0xFFF, - .min_mapped = 0, - .max_mapped = 0xFFF, - .outside_bounds_fraction = 0.02f - }, - .apps_2_scs = { - .hadc = &hadc2, - .min_adc = 0, - .max_adc = 0xFFF, - .min_mapped = 0, - .max_mapped = 0xFFF, - .outside_bounds_fraction = 0.02f - }, - .max_discrepancy = 100000,*/ + // .apps_1_scs = { + // .hadc = &hadc1, + // .adc_channel = ADC_CHANNEL_8, + // .min_adc = 0, + // .max_adc = 0xFFF, + // .min_mapped = 0, + // .max_mapped = 0xFFF, + // .outside_bounds_fraction = 0.02f + // }, + // .apps_2_scs = { + // .hadc = &hadc2, + // .adc_channel = ADC_CHANNEL_15, + // .min_adc = 0, + // .max_adc = 0xFFF, + // .min_mapped = 0, + // .max_mapped = 0xFFF, + // .outside_bounds_fraction = 0.02f + // }, + // .max_discrepancy = 100000, .apps_1_scs = { .hadc = &hadc1, - .min_adc = 6, - .max_adc = 192, + .scan_slot = 0, // ADC1 rank 1 + .min_adc = 98, //79 measured - 77 set - 136 previous + .max_adc = 1635, // 1830 measured - 1850 set - 1405 previous .min_mapped = 0, - .max_mapped = 100, - .outside_bounds_fraction = 0.05f + .max_mapped = 1000, + .outside_bounds_fraction = 0.10f }, .apps_2_scs = { .hadc = &hadc2, - .min_adc = 130, - .max_adc = 255, - .min_mapped = 0, - .max_mapped = 100, - .outside_bounds_fraction = 0.05f - }, - .max_discrepancy = 10, - + .scan_slot = 0, // ADC2 rank 1 + .min_adc = 792, // 750 measured - 740 set - 786 previous + .max_adc = 2416, //2660 measured - 2700 set - 2050 previous + .min_mapped = 0, + .max_mapped = 1000, + .outside_bounds_fraction = 0.10f + }, + .max_discrepancy = 120, // TODO: reduce this (ideally 10, worse case 25-30) by doing a better calibration once this is finalised in the car + .inverted = true }, .bps = { .scs = { - .hadc = &hadc3, - .min_adc = 0, - .max_adc = 350, + .hadc = &hadc1, + .scan_slot = 1, // ADC1 rank 2 + .min_adc = 380, + .max_adc = 800, .min_mapped = 0, - .max_mapped = 200, - .outside_bounds_fraction = 0.05f + .max_mapped = 1000, + .outside_bounds_fraction = 0.5f }, - .fully_pressed_fraction = 0.4f + .fully_pressed_fraction = 0.25f }, .ctrl = { .thread = { @@ -91,30 +96,32 @@ static const config_t config_instance = { }, .schedule_ticks = SECONDS_TO_TICKS(0.01), // 100Hz control loop .r2d_requires_brake = true, - .bps_on_threshold = 40, - .apps_bps_low_threshold = 5, - .apps_bps_high_threshold = 30, - .fan_on_threshold = 60, // to be adjusted to the actual value - .fan_off_threshold = 50, // to be adjusted to the actual value + .bps_on_threshold = 50, // brake threshold (% * 10) for entering R2D when r2d_requires_brake = true + .apps_bps_fault_bps_threshold = 150, // brake threshold (% * 10) to trigger apps bps fault + .apps_bps_low_threshold = 50, // required APPS (% * 10) to go out of a APPS bps fault + .apps_bps_high_threshold = 300, // required APPS (% * 10) to go into a APPS bps fault - set this to a big number (e.g. 2000), instead of default 300 (30%) to temporarily disable for scrut hardware demos .ts_ready_poll_ticks = SECONDS_TO_TICKS(0.1), .ts_ready_timeout_ticks = SECONDS_TO_TICKS(5), .precharge_timeout_ticks = SECONDS_TO_TICKS(3), .ready_wait_led_toggle_ticks = SECONDS_TO_TICKS(0.5), - .error_led_toggle_ticks = SECONDS_TO_TICKS(0.1) + .error_led_toggle_ticks = SECONDS_TO_TICKS(0.1), + .hard_max_torque = 2500, + .endurance_max_torque = 1100, + .crawl_max_torque = 200 }, .rtds = { .active_ticks = SECONDS_TO_TICKS(2), + .pulse_on_ticks = SECONDS_TO_TICKS(0.1), + .pulse_off_ticks = SECONDS_TO_TICKS(0.9), .port = R2D_SIREN_GPIO_Port, .pin = R2D_SIREN_Pin }, .torque_map = { - .function = TORQUE_MAP_LINEAR, - .input_max = 100, - .output_max = 700, - .deadzone_fraction = 0.28f, - .speed_min = 700, - .speed_start = 10000, - .speed_end = 20000 + .function = TORQUE_MAP_EXPONENTIAL, + .input_max = 1000, // percent * 10 so 100% + .output_max = 1000, // initial default before R2D; torque_map_set_output_max() is called with .ctrl.{hard,endurance,crawl}_max_torque when entering R2D depending on the current mode + .deadzone_fraction = 0.05f, + .exponent = 1.7f }, .pm100 = { .thread = { @@ -133,7 +140,10 @@ static const config_t config_instance = { .priority = 3, .stack_size = 1024 }, - .period = SECONDS_TO_TICKS(0.01) + .period = SECONDS_TO_TICKS(0.01), + .bps_light_threshold = 200, // Turn breaklight on at 2% + .bps_active_ticks = SECONDS_TO_TICKS(0.3), // debounce: BPS must be above threshold for 0.3s + }, .remote_ctrl = { .thread = { @@ -142,7 +152,7 @@ static const config_t config_instance = { .stack_size = 1024 }, .period = SECONDS_TO_TICKS(0.01), - .torque_limit = 2000, + .torque_limit = 2300, .power_limit = 10000, .broadcast_timeout_ticks = SECONDS_TO_TICKS(1) }, @@ -157,10 +167,11 @@ static const config_t config_instance = { .heartbeat = { .thread = { .name = "HEARTBEAT", - .priority = 10, + .priority = 16, .stack_size = 512 }, - .blink_period_ticks = SECONDS_TO_TICKS(0.25) + .blink_period_ticks = SECONDS_TO_TICKS(0.25), + .fast_blink_period_ticks = SECONDS_TO_TICKS(0.05) }, .log = { .thread = { @@ -168,12 +179,23 @@ static const config_t config_instance = { .priority = 15, .stack_size = 1024, }, - .min_level = LOG_LEVEL_DEBUG, - .uart = &huart1 + .min_level = LOG_LEVEL_INFO, + .min_sd_log_level = LOG_LEVEL_WARN, + .uart = &huart8, + .usart = &husart1, + }, + .sd = { + .thread = { + .name = "SD", + .priority = 16, + .stack_size = 8192, + }, + .enable = true, + .flush_period_ticks = SECONDS_TO_TICKS(10) }, .rtos = { .rtcan_s_priority = 3, - .rtcan_c_priority = 2, + .rtcan_t_priority = 2, .ts_ctrl_thread_priority = 2, .tracex_enable = false, .driver_ctrl_tick_rate = 100 @@ -182,13 +204,92 @@ static const config_t config_instance = { .run_apps_testbench = false, .run_fault_state_testbench = false, .apps_testbench_laps = 1 + }, + .wheelspeed = { + .thread = { + .name = "WHEELSPEED", + .priority = 4, + .stack_size = 1024, + }, + .ticks_per_wheel = 48, + .wheel_circumference_meters = 1.305, + .sample_period_ticks = SECONDS_TO_TICKS(0.02) // min viable speed approx 100rpm + }, + .torque_limiters = { + .gear_ratio = 3.18, + .min_motor_speed_rpm = 120, + .min_denominator_rpm = 40, // baseline only - auto-raised to ~37.7 (120/3.18) at init + .slip = { + .threshold = 10, // 10% slip -> start of deramp + .p_gain = 62.5, // Nm*10, so 62.5 -> -6.25 Nm per % slip above threshold + .i_gain = 0.5, + .integral_decay = 0.90, // 90% -> 10 * ln(0.5) / ln(0.90) ~= 65.8ms half life + .integral_max = 200, // 200 (Nm*10) -> clamp integral contribution to 20 Nm + .integral_enabled = false // P-only + }, + .power = { + .threshold = 75000.0, // 75 kW -> start of deramp + .p_gain = 0.2, // 0.2 -> -100 Nm at 80 kW applied over 5kW + .i_gain = 0.003, + .integral_decay = 0.90, // 90% -> 10 * ln(0.5) / ln(0.90) ~= 65.8ms half life + .integral_max = 1000, // 1000 (Nm*10) -> clamp integral contribution to 100 Nm + .integral_enabled = false // P-only + } + }, + .usb_msc = { + .thread = { + .name = "USB_MSC", + .priority = 16, + .stack_size = 8192 + } + }, + .ext_inputs = { + .sagl = { + .hadc = &hadc1, + .scan_slot = 3, // ADC1 rank 4 + .min_adc = 0, + .max_adc = 4096, + .min_mapped = 0, + .max_mapped = 4000, + .outside_bounds_fraction = 0.05f + }, + .current = { + .hadc = &hadc1, + .scan_slot = 2, // ADC1 rank 3 + .min_adc = 0, + .max_adc = 4096, + .min_mapped = 0, + .max_mapped = 4000, + .outside_bounds_fraction = 0.05f + }, + .mode_switch = { + .hadc = &hadc1, + .scan_slot = 4, // ADC1 rank 5 + .min_adc = 0, + .max_adc = 3300, + .min_mapped = 0, + .max_mapped = 330, + .outside_bounds_fraction = 0.05f + } + }, + .fans = { + .thread = { + .name = "FANS", + .priority = 12, + .stack_size = 1024, + }, + .broadcast_timeout_ticks = SECONDS_TO_TICKS(10), + .enable = true, + .inverted = true, + .fan_on_threshold = 50, // to be adjusted to the actual value + .fan_off_threshold = 48 // to be adjusted to the actual value } }; /** * @brief Returns the VCU configuration instance */ -const config_t* config_get() +const config_t *config_get() { return &config_instance; } diff --git a/src/SUFST/Src/vcu.c b/src/SUFST/Src/vcu.c index 69bf8c88..05b8fc07 100644 --- a/src/SUFST/Src/vcu.c +++ b/src/SUFST/Src/vcu.c @@ -10,22 +10,17 @@ #include -#include "apps.h" -#include "bps.h" -#include "config.h" -#include "dash.h" - /** * @brief Initialises the VCU and all system services * * @param[in] vcu_ptr VCU instance - * @param[in] can_c_h Critical systems CAN bus handle + * @param[in] can_t_h Critical systems CAN bus handle * @param[in] can_s_h Sensor CAN bus handle * @param[in] app_mem_pool Pointer to RTOS application memory pool * @param[in] config_ptr Pointer to VCU configuration instance */ status_t vcu_init(vcu_context_t *vcu_ptr, - CAN_HandleTypeDef *can_c_h, + CAN_HandleTypeDef *can_t_h, CAN_HandleTypeDef *can_s_h, TX_BYTE_POOL *app_mem_pool, const config_t *config_ptr) @@ -40,20 +35,73 @@ status_t vcu_init(vcu_context_t *vcu_ptr, status = log_init(&vcu_ptr->log, app_mem_pool, &vcu_ptr->config_ptr->log); } + // heartbeat + if (status == STATUS_OK) + { + status = heartbeat_init(&vcu_ptr->heartbeat, app_mem_pool, + &vcu_ptr->config_ptr->heartbeat); + } + + // enter USB mass storage mode if requested + if (status == STATUS_OK && usb_mass_storage_mode_button_held()) + { + return usb_msc_init(&vcu_ptr->usb_msc, app_mem_pool, + &vcu_ptr->config_ptr->usb_msc); + } + // RTCAN services - rtcan_handle_t *rtcan_handles[] = {&vcu_ptr->rtcan_s, &vcu_ptr->rtcan_c}; - CAN_HandleTypeDef *can_handles[] = {can_s_h, can_c_h}; - ULONG rtcan_priorities[] = {vcu_ptr->config_ptr->rtos.rtcan_s_priority, - vcu_ptr->config_ptr->rtos.rtcan_c_priority}; + static const CAN_FilterTypeDef can_s_filters[] = { + { + .FilterIdHigh = 0x0000, + .FilterIdLow = 0x0000, + .FilterMaskIdHigh = 0x0000, + .FilterMaskIdLow = 0x0000, + .FilterFIFOAssignment = CAN_FILTER_FIFO0, + .FilterBank = 0, + .FilterMode = CAN_FILTERMODE_IDMASK, + .FilterScale = CAN_FILTERSCALE_32BIT, + .FilterActivation = CAN_FILTER_ENABLE, + .SlaveStartFilterBank = 14, + }, + }; + static const CAN_FilterTypeDef can_t_filters[] = { + { + .FilterIdHigh = 0x0000, + .FilterIdLow = 0x0000, + .FilterMaskIdHigh = 0x0000, + .FilterMaskIdLow = 0x0000, + .FilterFIFOAssignment = CAN_FILTER_FIFO0, + .FilterBank = 14, + .FilterMode = CAN_FILTERMODE_IDMASK, + .FilterScale = CAN_FILTERSCALE_32BIT, + .FilterActivation = CAN_FILTER_ENABLE, + .SlaveStartFilterBank = 14, + }, + }; + + rtcan_handle_t *rtcan_handles[] = { &vcu_ptr->rtcan_s, &vcu_ptr->rtcan_t }; + CAN_HandleTypeDef *can_handles[] = { can_s_h, can_t_h }; + const uint32_t rtcan_priorities[] = { vcu_ptr->config_ptr->rtos.rtcan_s_priority, + vcu_ptr->config_ptr->rtos.rtcan_t_priority }; + const CAN_FilterTypeDef *rtcan_filters[] = { can_s_filters, can_t_filters }; + const uint32_t rtcan_filter_counts[] = { 1U, 1U }; for (uint32_t i = 0; i < 2; i++) { if (status == STATUS_OK) { - rtcan_status_t rtcan_status = rtcan_init(rtcan_handles[i], - can_handles[i], - rtcan_priorities[i], - app_mem_pool); + const rtcan_config_t rtcan_config = { + .thread_priority = rtcan_priorities[i], + .tx_thread_stack_size = 0U, + .rx_thread_stack_size = 0U, + .tx_thread_stack_mem = NULL, + .rx_thread_stack_mem = NULL, + .filters = rtcan_filters[i], + .filter_count = rtcan_filter_counts[i], + }; + + rtcan_status_t rtcan_status = + rtcan_init(rtcan_handles[i], can_handles[i], &rtcan_config); if (rtcan_status == RTCAN_OK) { @@ -76,73 +124,67 @@ status_t vcu_init(vcu_context_t *vcu_ptr, // CAN broadcast service if (status == STATUS_OK) { - status = canbc_init(&vcu_ptr->canbc, - &vcu_ptr->rtcan_s, - app_mem_pool, - &vcu_ptr->config_ptr->canbc); + status = canbc_init(&vcu_ptr->canbc, &vcu_ptr->rtcan_t, &vcu_ptr->rtcan_s, + app_mem_pool, &vcu_ptr->config_ptr->canbc); } // dash if (status == STATUS_OK) { - status = dash_init(&vcu_ptr->dash, - app_mem_pool, - &vcu_ptr->config_ptr->dash); + status = dash_init(&vcu_ptr->dash, app_mem_pool, &vcu_ptr->config_ptr->dash); } // tick if (status == STATUS_OK) { - status = tick_init(&vcu_ptr->tick, - &vcu_ptr->canbc, - app_mem_pool, - &vcu_ptr->config_ptr->tick, - &vcu_ptr->config_ptr->apps, - &vcu_ptr->config_ptr->bps); + status = tick_init(&vcu_ptr->tick, &vcu_ptr->canbc, app_mem_pool, + &vcu_ptr->config_ptr->tick, &vcu_ptr->config_ptr->apps, + &vcu_ptr->config_ptr->bps, &vcu_ptr->config_ptr->ext_inputs); } // pm100 if (status == STATUS_OK) { - status = pm100_init(&vcu_ptr->pm100, - app_mem_pool, - &vcu_ptr->rtcan_c, - &vcu_ptr->rtcan_s, - &vcu_ptr->config_ptr->pm100); + status = pm100_init(&vcu_ptr->pm100, app_mem_pool, &vcu_ptr->rtcan_t, + &vcu_ptr->rtcan_s, &vcu_ptr->config_ptr->pm100); } // control if (status == STATUS_OK) { - status = ctrl_init(&vcu_ptr->ctrl, - &vcu_ptr->dash, - &vcu_ptr->pm100, - &vcu_ptr->tick, - &vcu_ptr->remote_ctrl, - &vcu_ptr->canbc, - app_mem_pool, - &vcu_ptr->config_ptr->ctrl, - &vcu_ptr->config_ptr->rtds, - &vcu_ptr->config_ptr->torque_map); + status = ctrl_init(&vcu_ptr->ctrl, &vcu_ptr->dash, &vcu_ptr->pm100, + &vcu_ptr->tick, &vcu_ptr->remote_ctrl, &vcu_ptr->canbc, + &vcu_ptr->fans, &vcu_ptr->wheelspeed, app_mem_pool, + &vcu_ptr->config_ptr->ctrl, &vcu_ptr->config_ptr->rtds, + &vcu_ptr->config_ptr->torque_map, + &vcu_ptr->config_ptr->torque_limiters); } // remote control if (status == STATUS_OK) { - status = remote_ctrl_init( - &vcu_ptr->remote_ctrl, - &vcu_ptr->canbc, - app_mem_pool, - &vcu_ptr->rtcan_s, - &vcu_ptr->config_ptr->remote_ctrl); + status = remote_ctrl_init(&vcu_ptr->remote_ctrl, &vcu_ptr->canbc, app_mem_pool, + &vcu_ptr->rtcan_s, &vcu_ptr->config_ptr->remote_ctrl); } - // heartbeat + // wheelspeed if (status == STATUS_OK) { - status = heartbeat_init(&vcu_ptr->heartbeat, - app_mem_pool, - &vcu_ptr->config_ptr->heartbeat); + status = wheelspeed_init(&vcu_ptr->wheelspeed, &vcu_ptr->rtcan_s, + app_mem_pool, &vcu_ptr->config_ptr->wheelspeed); + } + + // fans + if (status == STATUS_OK) + { + status = fans_init(&vcu_ptr->fans, &vcu_ptr->rtcan_s, app_mem_pool, + &vcu_ptr->config_ptr->fans); + } + + // sd card + if (status == STATUS_OK) + { + status = sd_init(&vcu_ptr->sd, app_mem_pool, &vcu_ptr->config_ptr->sd); } if (status != STATUS_OK) @@ -157,17 +199,16 @@ status_t vcu_init(vcu_context_t *vcu_ptr, * @param[in] vcu_ptr VCU instance * @param[in] can_h CAN handle from callback */ -status_t vcu_handle_can_tx_mailbox_callback(vcu_context_t *vcu_ptr, - CAN_HandleTypeDef *can_h) +status_t vcu_handle_can_tx_mailbox_callback(vcu_context_t *vcu_ptr, CAN_HandleTypeDef *can_h) { // TODO: how to handle CAN C vs CAN S - rtcan_status_t status = rtcan_handle_tx_mailbox_callback(&vcu_ptr->rtcan_c, can_h); + rtcan_status_t status = rtcan_handle_tx_mailbox_callback(&vcu_ptr->rtcan_t, can_h); if (status != RTCAN_OK) { // TODO: error // vcu_h->err |= VCU_ERROR_PERIPHERAL; - Error_Handler(); + // Error_Handler(); } status = rtcan_handle_tx_mailbox_callback(&vcu_ptr->rtcan_s, can_h); @@ -176,7 +217,7 @@ status_t vcu_handle_can_tx_mailbox_callback(vcu_context_t *vcu_ptr, { // TODO: error // vcu_h->err |= VCU_ERROR_PERIPHERAL; - Error_Handler(); + // Error_Handler(); } return STATUS_OK; //? Error_Handler() never returns so this can only return @@ -190,15 +231,13 @@ status_t vcu_handle_can_tx_mailbox_callback(vcu_context_t *vcu_ptr, * @param[in] can_h CAN handle * @param[in] rx_fifo Rx FIFO number */ -status_t vcu_handle_can_rx_it(vcu_context_t *vcu_ptr, - CAN_HandleTypeDef *can_h, - uint32_t rx_fifo) +status_t vcu_handle_can_rx_it(vcu_context_t *vcu_ptr, CAN_HandleTypeDef *can_h, uint32_t rx_fifo) { rtcan_status_t status; - if (vcu_ptr->rtcan_c.hcan == can_h) + if (vcu_ptr->rtcan_t.hcan == can_h) { - status = rtcan_handle_rx_it(&vcu_ptr->rtcan_c, can_h, rx_fifo); + status = rtcan_handle_rx_it(&vcu_ptr->rtcan_t, can_h, rx_fifo); } else if (vcu_ptr->rtcan_s.hcan == can_h) { @@ -224,9 +263,12 @@ status_t vcu_handle_can_err(vcu_context_t *vcu_ptr, CAN_HandleTypeDef *can_h) { rtcan_status_t status; - if (vcu_ptr->rtcan_c.hcan == can_h) + LOG_ERROR("CAN error 0x%08lX on %s\n", HAL_CAN_GetError(can_h), + (can_h == vcu_ptr->rtcan_t.hcan) ? "CAN_T" : "CAN_S"); + + if (vcu_ptr->rtcan_t.hcan == can_h) { - status = rtcan_handle_hal_error(&vcu_ptr->rtcan_c, can_h); + status = rtcan_handle_hal_error(&vcu_ptr->rtcan_t, can_h); } else if (vcu_ptr->rtcan_s.hcan == can_h) { @@ -235,10 +277,22 @@ status_t vcu_handle_can_err(vcu_context_t *vcu_ptr, CAN_HandleTypeDef *can_h) if (status != RTCAN_OK) { - // TODO: error - // vcu_h->err |= VCU_ERROR_PERIPHERAL; - Error_Handler(); + // vcu_ptr->err |= VCU_OS_ERROR_PERIPHERAL; + + // Note: Do not call Error_Handler() here as the + // Entire VCU will crash whenever there is a CAN bus error. } return STATUS_OK; } + +/** + * @brief Handles GPIO EXTI callbacks (e.g. wheelspeed sensors) + * + * @param[in] vcu_ptr VCU instance + * @param[in] gpio_pin GPIO pin that triggered the interrupt + */ +void vcu_handle_gpio_exti(vcu_context_t *vcu_ptr, uint16_t gpio_pin) +{ + wheelspeed_handle_exti(&vcu_ptr->wheelspeed, gpio_pin); +} diff --git a/src/USBX/App/app_usbx_device.c b/src/USBX/App/app_usbx_device.c new file mode 100644 index 00000000..ae22eff6 --- /dev/null +++ b/src/USBX/App/app_usbx_device.c @@ -0,0 +1,76 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_usbx_device.c + * @author MCD Application Team + * @brief USBX Device applicative file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "app_usbx_device.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ +/** + * @brief Application USBX Device Initialization. + * @param memory_ptr: memory pointer + * @retval int + */ +UINT MX_USBX_Device_Init(VOID *memory_ptr) +{ + UINT ret = UX_SUCCESS; + TX_BYTE_POOL *byte_pool = (TX_BYTE_POOL*)memory_ptr; + + /* USER CODE BEGIN MX_USBX_Device_MEM_POOL */ + (void)byte_pool; + /* USER CODE END MX_USBX_Device_MEM_POOL */ + + /* USER CODE BEGIN MX_USBX_Device_Init */ + + /* USER CODE END MX_USBX_Device_Init */ + + return ret; +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/USBX/App/app_usbx_device.h b/src/USBX/App/app_usbx_device.h new file mode 100644 index 00000000..5f78eeff --- /dev/null +++ b/src/USBX/App/app_usbx_device.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_usbx_device.h + * @author MCD Application Team + * @brief USBX Device applicative header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __APP_USBX_DEVICE_H__ +#define __APP_USBX_DEVICE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ux_api.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +UINT MX_USBX_Device_Init(VOID *memory_ptr); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +#ifdef __cplusplus +} +#endif +#endif /* __APP_USBX_DEVICE_H__ */ diff --git a/src/USBX/App/app_usbx_host.c b/src/USBX/App/app_usbx_host.c new file mode 100644 index 00000000..bc505c78 --- /dev/null +++ b/src/USBX/App/app_usbx_host.c @@ -0,0 +1,76 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_usbx_host.c + * @author MCD Application Team + * @brief USBX host applicative file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "app_usbx_host.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ +/** + * @brief Application USBX Host Initialization. + * @param memory_ptr: memory pointer + * @retval int + */ +UINT MX_USBX_Host_Init(VOID *memory_ptr) +{ + UINT ret = UX_SUCCESS; + TX_BYTE_POOL *byte_pool = (TX_BYTE_POOL*)memory_ptr; + + /* USER CODE BEGIN MX_USBX_Host_MEM_POOL */ + (void)byte_pool; + /* USER CODE END MX_USBX_Host_MEM_POOL */ + + /* USER CODE BEGIN MX_USBX_Host_Init */ + + /* USER CODE END MX_USBX_Host_Init */ + + return ret; +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/USBX/App/app_usbx_host.h b/src/USBX/App/app_usbx_host.h new file mode 100644 index 00000000..2c35d781 --- /dev/null +++ b/src/USBX/App/app_usbx_host.h @@ -0,0 +1,70 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file app_usbx_host.h + * @author MCD Application Team + * @brief USBX Host applicative header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __APP_USBX_HOST_H__ +#define __APP_USBX_HOST_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ux_api.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ +UINT MX_USBX_Host_Init(VOID *memory_ptr); + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +#ifdef __cplusplus +} +#endif +#endif /* __APP_USBX_HOST_H__ */ diff --git a/src/USBX/App/ux_device_descriptors.c b/src/USBX/App/ux_device_descriptors.c new file mode 100644 index 00000000..6256ef31 --- /dev/null +++ b/src/USBX/App/ux_device_descriptors.c @@ -0,0 +1,630 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ux_device_descriptors.c + * @author MCD Application Team + * @brief USBX Device descriptor header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "ux_device_descriptors.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +USBD_DevClassHandleTypeDef USBD_Device_FS, USBD_Device_HS; + +uint8_t UserClassInstance[USBD_MAX_CLASS_INTERFACES] = { + CLASS_TYPE_MSC, +}; + +/* The generic device descriptor buffer that will be filled by builder + Size of the buffer is the maximum possible device FS descriptor size. */ +#if defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +__ALIGN_BEGIN static uint8_t DevFrameWorkDesc_FS[USBD_FRAMEWORK_MAX_DESC_SZ] __ALIGN_END = {0}; + +/* The generic device descriptor buffer that will be filled by builder + Size of the buffer is the maximum possible device HS descriptor size. */ +#if defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +__ALIGN_BEGIN static uint8_t DevFrameWorkDesc_HS[USBD_FRAMEWORK_MAX_DESC_SZ] __ALIGN_END = {0}; + +static uint8_t *pDevFrameWorkDesc_FS = DevFrameWorkDesc_FS; + +static uint8_t *pDevFrameWorkDesc_HS = DevFrameWorkDesc_HS; +/* USER CODE BEGIN PV0 */ + +/* USER CODE END PV0 */ + +/* String Device Framework : + Byte 0 and 1 : Word containing the language ID : 0x0904 for US + Byte 2 : Byte containing the index of the descriptor + Byte 3 : Byte containing the length of the descriptor string +*/ +#if defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +__ALIGN_BEGIN UCHAR USBD_string_framework[USBD_STRING_FRAMEWORK_MAX_LENGTH] +__ALIGN_END = {0}; + +/* Multiple languages are supported on the device, to add + a language besides English, the Unicode language code must + be appended to the language_id_framework array and the length + adjusted accordingly. */ + +#if defined ( __ICCARM__ ) /* IAR Compiler */ +#pragma data_alignment=4 +#endif /* defined ( __ICCARM__ ) */ +UCHAR USBD_language_id_framework[LANGUAGE_ID_MAX_LENGTH] = {0}; + +/* USER CODE BEGIN PV2 */ + +/* USER CODE END PV2 */ + +/* Private function prototypes -----------------------------------------------*/ +static void USBD_Desc_GetString(uint8_t *desc, uint8_t *Buffer, uint16_t *len); +static uint8_t USBD_Desc_GetLen(uint8_t *buf); + +static uint8_t *USBD_Device_Framework_Builder(USBD_DevClassHandleTypeDef *pdev, + uint8_t *pDevFrameWorkDesc, + uint8_t *UserClassInstance, + uint8_t Speed); + +static uint8_t USBD_FrameWork_AddToConfDesc(USBD_DevClassHandleTypeDef *pdev, + uint8_t Speed, + uint8_t *pCmpstConfDesc); + +static uint8_t USBD_FrameWork_AddClass(USBD_DevClassHandleTypeDef *pdev, + USBD_CompositeClassTypeDef class, + uint8_t cfgidx, uint8_t Speed, + uint8_t *pCmpstConfDesc); + +static uint8_t USBD_FrameWork_FindFreeIFNbr(USBD_DevClassHandleTypeDef *pdev); + +static void USBD_FrameWork_AddConfDesc(uint32_t Conf, uint32_t *pSze); + +static void USBD_FrameWork_AssignEp(USBD_DevClassHandleTypeDef *pdev, uint8_t Add, + uint8_t Type, uint32_t Sze); + +#if USBD_MSC_CLASS_ACTIVATED == 1U +static void USBD_FrameWork_MSCDesc(USBD_DevClassHandleTypeDef *pdev, + uint32_t pConf, uint32_t *Sze); +#endif /* USBD_MSC_CLASS_ACTIVATED == 1U */ + +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/** + * @brief USBD_Get_Device_Framework_Speed + * Return the device speed descriptor + * @param Speed : HIGH or FULL SPEED flag + * @param length : length of HIGH or FULL SPEED array + * @retval Pointer to descriptor buffer + */ +uint8_t *USBD_Get_Device_Framework_Speed(uint8_t Speed, ULONG *Length) +{ + uint8_t *pFrameWork = NULL; + /* USER CODE BEGIN Device_Framework0 */ + + /* USER TAG BEGIN Device_Framework0 */ + + if (USBD_FULL_SPEED == Speed) + { + USBD_Device_Framework_Builder(&USBD_Device_FS, pDevFrameWorkDesc_FS, + UserClassInstance, Speed); + + /* Get the length of USBD_device_framework_full_speed */ + *Length = (ULONG)(USBD_Device_FS.CurrDevDescSz + USBD_Device_FS.CurrConfDescSz); + + pFrameWork = pDevFrameWorkDesc_FS; + } + else + { + USBD_Device_Framework_Builder(&USBD_Device_HS, pDevFrameWorkDesc_HS, + UserClassInstance, Speed); + + /* Get the length of USBD_device_framework_high_speed */ + *Length = (ULONG)(USBD_Device_HS.CurrDevDescSz + USBD_Device_HS.CurrConfDescSz); + + pFrameWork = pDevFrameWorkDesc_HS; + } + /* USER CODE Device_Framework1 */ + + /* USER CODE Device_Framework1 */ + return pFrameWork; +} + +/** + * @brief USBD_Get_String_Framework + * Return the language_id_framework + * @param Length : Length of String_Framework + * @retval Pointer to language_id_framework buffer + */ +uint8_t *USBD_Get_String_Framework(ULONG *Length) +{ + uint16_t len = 0U; + uint8_t count = 0U; + + /* USER CODE String_Framework0 */ + + /* USER CODE String_Framework0 */ + + /* Set the Manufacturer language Id and index in USBD_string_framework */ + USBD_string_framework[count++] = USBD_LANGID_STRING & 0xFF; + USBD_string_framework[count++] = USBD_LANGID_STRING >> 8; + USBD_string_framework[count++] = USBD_IDX_MFC_STR; + + /* Set the Manufacturer string in string_framework */ + USBD_Desc_GetString((uint8_t *)USBD_MANUFACTURER_STRING, USBD_string_framework + count, &len); + + /* Set the Product language Id and index in USBD_string_framework */ + count += len + 1; + USBD_string_framework[count++] = USBD_LANGID_STRING & 0xFF; + USBD_string_framework[count++] = USBD_LANGID_STRING >> 8; + USBD_string_framework[count++] = USBD_IDX_PRODUCT_STR; + + /* Set the Product string in USBD_string_framework */ + USBD_Desc_GetString((uint8_t *)USBD_PRODUCT_STRING, USBD_string_framework + count, &len); + + /* Set Serial language Id and index in string_framework */ + count += len + 1; + USBD_string_framework[count++] = USBD_LANGID_STRING & 0xFF; + USBD_string_framework[count++] = USBD_LANGID_STRING >> 8; + USBD_string_framework[count++] = USBD_IDX_SERIAL_STR; + + /* Set the Serial number in USBD_string_framework */ + USBD_Desc_GetString((uint8_t *)USBD_SERIAL_NUMBER, USBD_string_framework + count, &len); + + /* USER CODE String_Framework1 */ + + /* USER CODE String_Framework1 */ + + /* Get the length of USBD_string_framework */ + *Length = strlen((const char *)USBD_string_framework); + + return USBD_string_framework; +} + +/** + * @brief USBD_Get_Language_Id_Framework + * Return the language_id_framework + * @param Length : Length of Language_Id_Framework + * @retval Pointer to language_id_framework buffer + */ +uint8_t *USBD_Get_Language_Id_Framework(ULONG *Length) +{ + uint8_t count = 0U; + + /* Set the language Id in USBD_language_id_framework */ + USBD_language_id_framework[count++] = USBD_LANGID_STRING & 0xFF; + USBD_language_id_framework[count++] = USBD_LANGID_STRING >> 8; + + /* Get the length of USBD_language_id_framework */ + *Length = strlen((const char *)USBD_language_id_framework); + + return USBD_language_id_framework; +} + +/** + * @brief USBD_Desc_GetString + * Convert ASCII string into Unicode one + * @param desc : descriptor buffer + * @param Unicode : Formatted string buffer (Unicode) + * @param len : descriptor length + * @retval None + */ +static void USBD_Desc_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len) +{ + uint8_t idx = 0U; + uint8_t *pdesc; + + if (desc == NULL) + { + return; + } + + pdesc = desc; + *len = (uint16_t)USBD_Desc_GetLen(pdesc); + + unicode[idx++] = *(uint8_t *)len; + + while (*pdesc != (uint8_t)'\0') + { + unicode[idx++] = *pdesc; + pdesc++; + } +} + +/** + * @brief USBD_Desc_GetLen + * return the string length + * @param buf : pointer to the ASCII string buffer + * @retval string length + */ +static uint8_t USBD_Desc_GetLen(uint8_t *buf) +{ + uint8_t len = 0U; + uint8_t *pbuff = buf; + + while (*pbuff != (uint8_t)'\0') + { + len++; + pbuff++; + } + + return len; +} + +/** + * @brief USBD_Device_Framework_Builder + * Device Framework builder + * @param pdev: device instance + * @param pDevFrameWorkDesc: Pointer to the device framework descriptor + * @param UserClassInstance: type of the class to be added + * @param Speed: Speed parameter HS or FS + * @retval status + */ +static uint8_t *USBD_Device_Framework_Builder(USBD_DevClassHandleTypeDef *pdev, + uint8_t *pDevFrameWorkDesc, + uint8_t *UserClassInstance, + uint8_t Speed) +{ + static USBD_DeviceDescTypedef *pDevDesc; + static USBD_DevQualiDescTypedef *pDevQualDesc; + uint8_t Idx_Instance = 0U; + uint8_t NumberClass = 1U; + + /* Set Dev and conf descriptors size to 0 */ + pdev->CurrConfDescSz = 0U; + pdev->CurrDevDescSz = 0U; + + /* Set the pointer to the device descriptor area*/ + pDevDesc = (USBD_DeviceDescTypedef *)pDevFrameWorkDesc; + + /* Start building the generic device descriptor common part */ + pDevDesc->bLength = (uint8_t)sizeof(USBD_DeviceDescTypedef); + pDevDesc->bDescriptorType = UX_DEVICE_DESCRIPTOR_ITEM; + pDevDesc->bcdUSB = USB_BCDUSB; + pDevDesc->bDeviceClass = 0x00; + pDevDesc->bDeviceSubClass = 0x00; + pDevDesc->bDeviceProtocol = 0x00; + pDevDesc->bMaxPacketSize = USBD_MAX_EP0_SIZE; + pDevDesc->idVendor = USBD_VID; + pDevDesc->idProduct = USBD_PID; + pDevDesc->bcdDevice = 0x0200; + pDevDesc->iManufacturer = USBD_IDX_MFC_STR; + pDevDesc->iProduct = USBD_IDX_PRODUCT_STR; + pDevDesc->iSerialNumber = USBD_IDX_SERIAL_STR; + pDevDesc->bNumConfigurations = USBD_MAX_NUM_CONFIGURATION; + pdev->CurrDevDescSz += (uint32_t)sizeof(USBD_DeviceDescTypedef); + + /* Check if USBx is in high speed mode to add qualifier descriptor */ + if (Speed == USBD_HIGH_SPEED) + { + pDevQualDesc = (USBD_DevQualiDescTypedef *)(pDevFrameWorkDesc + pdev->CurrDevDescSz); + pDevQualDesc->bLength = (uint8_t)sizeof(USBD_DevQualiDescTypedef); + pDevQualDesc->bDescriptorType = UX_DEVICE_QUALIFIER_DESCRIPTOR_ITEM; + pDevQualDesc->bcdDevice = 0x0200; + pDevQualDesc->Class = 0x00; + pDevQualDesc->SubClass = 0x00; + pDevQualDesc->Protocol = 0x00; + pDevQualDesc->bMaxPacketSize = 0x40; + pDevQualDesc->bNumConfigurations = 0x01; + pDevQualDesc->bReserved = 0x00; + pdev->CurrDevDescSz += (uint32_t)sizeof(USBD_DevQualiDescTypedef); + } + + /* Build the device framework */ + while (Idx_Instance < USBD_MAX_SUPPORTED_CLASS) + { + if ((pdev->classId < USBD_MAX_SUPPORTED_CLASS) && + (pdev->NumClasses < USBD_MAX_SUPPORTED_CLASS)) + { + /* Call the composite class builder */ + (void)USBD_FrameWork_AddClass(pdev, + (USBD_CompositeClassTypeDef)UserClassInstance[Idx_Instance], + 0, Speed, (pDevFrameWorkDesc + pdev->CurrDevDescSz)); + + /* Increment the ClassId for the next occurrence */ + pdev->classId ++; + pdev->NumClasses ++; + } + Idx_Instance++; + + /* Count the number of Classes different of CLASS_TYPE_NONE */ + if (UserClassInstance[Idx_Instance] != CLASS_TYPE_NONE) + { + NumberClass++; + } + } + /* Check if there is a composite class and update device class */ + if (NumberClass > 1) + { + pDevDesc->bDeviceClass = 0xEF; + pDevDesc->bDeviceSubClass = 0x02; + pDevDesc->bDeviceProtocol = 0x01; + } + else + { + /* Check if the CDC ACM class is set and update device class */ + if (UserClassInstance[0] == CLASS_TYPE_CDC_ACM) + { + pDevDesc->bDeviceClass = 0x02; + pDevDesc->bDeviceSubClass = 0x02; + pDevDesc->bDeviceProtocol = 0x00; + } + } + + return pDevFrameWorkDesc; +} + +/** + * @brief USBD_FrameWork_AddClass + * Register a class in the class builder + * @param pdev: device instance + * @param pclass: pointer to the class structure to be added + * @param class: type of the class to be added (from USBD_CompositeClassTypeDef) + * @param cfgidx: configuration index + * @retval status + */ +uint8_t USBD_FrameWork_AddClass(USBD_DevClassHandleTypeDef *pdev, + USBD_CompositeClassTypeDef class, + uint8_t cfgidx, uint8_t Speed, + uint8_t *pCmpstConfDesc) +{ + if ((pdev->classId < USBD_MAX_SUPPORTED_CLASS) && + (pdev->tclasslist[pdev->classId].Active == 0U)) + { + /* Store the class parameters in the global tab */ + pdev->tclasslist[pdev->classId].ClassId = pdev->classId; + pdev->tclasslist[pdev->classId].Active = 1U; + pdev->tclasslist[pdev->classId].ClassType = class; + + /* Call configuration descriptor builder and endpoint configuration builder */ + if (USBD_FrameWork_AddToConfDesc(pdev, Speed, pCmpstConfDesc) != UX_SUCCESS) + { + return UX_ERROR; + } + } + + UNUSED(cfgidx); + + return UX_SUCCESS; +} + +/** + * @brief USBD_FrameWork_AddToConfDesc + * Add a new class to the configuration descriptor + * @param pdev: device instance + * @retval status + */ +uint8_t USBD_FrameWork_AddToConfDesc(USBD_DevClassHandleTypeDef *pdev, uint8_t Speed, + uint8_t *pCmpstConfDesc) +{ + uint8_t interface = 0U; + + /* USER CODE FrameWork_AddToConfDesc_0 */ + + /* USER CODE FrameWork_AddToConfDesc_0 */ + + /* The USB drivers do not set the speed value, so set it here before starting */ + pdev->Speed = Speed; + + /* start building the config descriptor common part */ + if (pdev->classId == 0U) + { + /* Add configuration and IAD descriptors */ + USBD_FrameWork_AddConfDesc((uint32_t)pCmpstConfDesc, &pdev->CurrConfDescSz); + } + + switch (pdev->tclasslist[pdev->classId].ClassType) + { + +#if USBD_MSC_CLASS_ACTIVATED == 1U + case CLASS_TYPE_MSC: + /* Find the first available interface slot and Assign number of interfaces */ + interface = USBD_FrameWork_FindFreeIFNbr(pdev); + pdev->tclasslist[pdev->classId].NumIf = 1; + pdev->tclasslist[pdev->classId].Ifs[0] = interface; + + /* Assign endpoint numbers */ + pdev->tclasslist[pdev->classId].NumEps = 2; /* EP1_IN, EP1_OUT */ + + /* Check the current speed to assign endpoints */ + if (pdev->Speed == USBD_HIGH_SPEED) + { + /* Assign IN Endpoint */ + USBD_FrameWork_AssignEp(pdev, USBD_MSC_EPIN_ADDR, + USBD_EP_TYPE_BULK, USBD_MSC_EPIN_HS_MPS); + + /* Assign OUT Endpoint */ + USBD_FrameWork_AssignEp(pdev, USBD_MSC_EPOUT_ADDR, + USBD_EP_TYPE_BULK, USBD_MSC_EPOUT_HS_MPS); + } + else + { + /* Assign IN Endpoint */ + USBD_FrameWork_AssignEp(pdev, USBD_MSC_EPIN_ADDR, + USBD_EP_TYPE_BULK, USBD_MSC_EPIN_FS_MPS); + + /* Assign OUT Endpoint */ + USBD_FrameWork_AssignEp(pdev, USBD_MSC_EPOUT_ADDR, + USBD_EP_TYPE_BULK, USBD_MSC_EPOUT_FS_MPS); + } + + /* Configure and Append the Descriptor */ + USBD_FrameWork_MSCDesc(pdev, (uint32_t)pCmpstConfDesc, &pdev->CurrConfDescSz); + + break; +#endif /* USBD_MSC_CLASS_ACTIVATED */ + + /* USER CODE FrameWork_AddToConfDesc_1 */ + + /* USER CODE FrameWork_AddToConfDesc_1 */ + + default: + /* USER CODE FrameWork_AddToConfDesc_2 */ + + /* USER CODE FrameWork_AddToConfDesc_2 */ + break; + } + + return UX_SUCCESS; +} + +/** + * @brief USBD_FrameWork_FindFreeIFNbr + * Find the first interface available slot + * @param pdev: device instance + * @retval The interface number to be used + */ +static uint8_t USBD_FrameWork_FindFreeIFNbr(USBD_DevClassHandleTypeDef *pdev) +{ + uint32_t idx = 0U; + + /* Unroll all already activated classes */ + for (uint32_t i = 0U; i < pdev->NumClasses; i++) + { + /* Unroll each class interfaces */ + for (uint32_t j = 0U; j < pdev->tclasslist[i].NumIf; j++) + { + /* Increment the interface counter index */ + idx++; + } + } + + /* Return the first available interface slot */ + return (uint8_t)idx; +} + +/** + * @brief USBD_FrameWork_AddToConfDesc + * Add a new class to the configuration descriptor + * @param pdev: device instance + * @retval none + */ +static void USBD_FrameWork_AddConfDesc(uint32_t Conf, uint32_t *pSze) +{ + /* Intermediate variable to comply with MISRA-C Rule 11.3 */ + USBD_ConfigDescTypedef *ptr = (USBD_ConfigDescTypedef *)Conf; + + ptr->bLength = (uint8_t)sizeof(USBD_ConfigDescTypedef); + ptr->bDescriptorType = USB_DESC_TYPE_CONFIGURATION; + ptr->wDescriptorLength = 0U; + ptr->bNumInterfaces = 0U; + ptr->bConfigurationValue = 1U; + ptr->iConfiguration = USBD_CONFIG_STR_DESC_IDX; + ptr->bmAttributes = USBD_CONFIG_BMATTRIBUTES; + ptr->bMaxPower = USBD_CONFIG_MAXPOWER; + *pSze += sizeof(USBD_ConfigDescTypedef); +} + +/** + * @brief USBD_FrameWork_AssignEp + * Assign and endpoint + * @param pdev: device instance + * @param Add: Endpoint address + * @param Type: Endpoint type + * @param Sze: Endpoint max packet size + * @retval none + */ +static void USBD_FrameWork_AssignEp(USBD_DevClassHandleTypeDef *pdev, + uint8_t Add, uint8_t Type, uint32_t Sze) +{ + uint32_t idx = 0U; + + /* Find the first available endpoint slot */ + while (((idx < (pdev->tclasslist[pdev->classId]).NumEps) && \ + ((pdev->tclasslist[pdev->classId].Eps[idx].is_used) != 0U))) + { + /* Increment the index */ + idx++; + } + + /* Configure the endpoint */ + pdev->tclasslist[pdev->classId].Eps[idx].add = Add; + pdev->tclasslist[pdev->classId].Eps[idx].type = Type; + pdev->tclasslist[pdev->classId].Eps[idx].size = (uint16_t) Sze; + pdev->tclasslist[pdev->classId].Eps[idx].is_used = 1U; +} + +#if USBD_MSC_CLASS_ACTIVATED == 1 +/** + * @brief USBD_FrameWork_MSCDesc + * Configure and Append the MSC Descriptor + * @param pdev: device instance + * @param pConf: Configuration descriptor pointer + * @param Sze: pointer to the current configuration descriptor size + * @retval None + */ +static void USBD_FrameWork_MSCDesc(USBD_DevClassHandleTypeDef *pdev, + uint32_t pConf, uint32_t *Sze) +{ + USBD_IfDescTypedef *pIfDesc; + USBD_EpDescTypedef *pEpDesc; + + /* Append MSC Interface descriptor */ + __USBD_FRAMEWORK_SET_IF((pdev->tclasslist[pdev->classId].Ifs[0]), (0U), \ + (uint8_t)(pdev->tclasslist[pdev->classId].NumEps), + (0x08U), (0x06U), (0x50U), (0U)); + + /* Append Endpoint descriptor to Configuration descriptor */ + __USBD_FRAMEWORK_SET_EP((pdev->tclasslist[pdev->classId].Eps[0].add), + (USBD_EP_TYPE_BULK), + (uint16_t)(pdev->tclasslist[pdev->classId].Eps[0].size), + (0U), (0U)); + + /* Append Endpoint descriptor to Configuration descriptor */ + __USBD_FRAMEWORK_SET_EP((pdev->tclasslist[pdev->classId].Eps[1].add), + (USBD_EP_TYPE_BULK), + (uint16_t)(pdev->tclasslist[pdev->classId].Eps[1].size), + (0U), (0U)); + + /* Update Config Descriptor and IAD descriptor */ + ((USBD_ConfigDescTypedef *)pConf)->bNumInterfaces += 1U; + ((USBD_ConfigDescTypedef *)pConf)->wDescriptorLength = *Sze; +} +#endif /* USBD_MSC_CLASS_ACTIVATED == 1 */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/USBX/App/ux_device_descriptors.h b/src/USBX/App/ux_device_descriptors.h new file mode 100644 index 00000000..283602f8 --- /dev/null +++ b/src/USBX/App/ux_device_descriptors.h @@ -0,0 +1,312 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ux_device_descriptors.h + * @author MCD Application Team + * @brief USBX Device descriptor header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __UX_DEVICE_DESCRIPTORS_H__ +#define __UX_DEVICE_DESCRIPTORS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ux_api.h" +#include "ux_stm32_config.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private defines -----------------------------------------------------------*/ +#define USBD_MAX_NUM_CONFIGURATION 1U +#define USBD_MAX_SUPPORTED_CLASS 3U +#define USBD_MAX_CLASS_ENDPOINTS 9U +#define USBD_MAX_CLASS_INTERFACES 9U + +#define USBD_MSC_CLASS_ACTIVATED 1U + +#define USBD_CONFIG_MAXPOWER 25U +#define USBD_COMPOSITE_USE_IAD 1U +#define USBD_DEVICE_FRAMEWORK_BUILDER_ENABLED 1U +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Enum Class Type */ +typedef enum +{ + CLASS_TYPE_NONE = 0, + CLASS_TYPE_HID = 1, + CLASS_TYPE_CDC_ACM = 2, + CLASS_TYPE_MSC = 3, + CLASS_TYPE_CDC_ECM = 4, + CLASS_TYPE_DFU = 5, +} USBD_CompositeClassTypeDef; + +/* USB Endpoint handle structure */ +typedef struct +{ + uint32_t status; + uint32_t total_length; + uint32_t rem_length; + uint32_t maxpacket; + uint16_t is_used; + uint16_t bInterval; +} USBD_EndpointTypeDef; + +/* USB endpoint handle structure */ +typedef struct +{ + uint8_t add; + uint8_t type; + uint16_t size; + uint8_t is_used; +} USBD_EPTypeDef; + +/* USB Composite handle structure */ +typedef struct +{ + USBD_CompositeClassTypeDef ClassType; + uint32_t ClassId; + uint32_t Active; + uint32_t NumEps; + USBD_EPTypeDef Eps[USBD_MAX_CLASS_ENDPOINTS]; + uint32_t NumIf; + uint8_t Ifs[USBD_MAX_CLASS_INTERFACES]; +} USBD_CompositeElementTypeDef; + +/* USB Device handle structure */ +typedef struct _USBD_DevClassHandleTypeDef +{ + uint8_t Speed; + uint32_t classId; + uint32_t NumClasses; + USBD_CompositeElementTypeDef tclasslist[USBD_MAX_SUPPORTED_CLASS]; + uint32_t CurrDevDescSz; + uint32_t CurrConfDescSz; +} USBD_DevClassHandleTypeDef; + +/* USB Device endpoint direction */ +typedef enum +{ + OUT = 0x00, + IN = 0x80, +} USBD_EPDirectionTypeDef; + +/* USB Device descriptors structure */ +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} __PACKED USBD_DeviceDescTypedef; + +/* USB Iad descriptors structure */ +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __PACKED USBD_IadDescTypedef; + +/* USB interface descriptors structure */ +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} __PACKED USBD_IfDescTypedef; + +/* USB endpoint descriptors structure */ +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} __PACKED USBD_EpDescTypedef; + +/* USB Config descriptors structure */ +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wDescriptorLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} __PACKED USBD_ConfigDescTypedef; + +/* USB Qualifier descriptors structure */ +typedef struct +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdDevice; + uint8_t Class; + uint8_t SubClass; + uint8_t Protocol; + uint8_t bMaxPacketSize; + uint8_t bNumConfigurations; + uint8_t bReserved; +} __PACKED USBD_DevQualiDescTypedef; + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private_defines */ + +/* USER CODE END Private_defines */ + +/* Exported functions prototypes ---------------------------------------------*/ +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +uint8_t *USBD_Get_Device_Framework_Speed(uint8_t Speed, ULONG *Length); +uint8_t *USBD_Get_String_Framework(ULONG *Length); +uint8_t *USBD_Get_Language_Id_Framework(ULONG *Length); + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN Private_defines */ + +/* USER CODE END Private_defines */ + +#define USBD_VID 1155 +#define USBD_PID 22288 +#define USBD_LANGID_STRING 1033 +#define USBD_MANUFACTURER_STRING "STMicroelectronics" +#define USBD_PRODUCT_STRING "STM32 USB Device" +#define USBD_SERIAL_NUMBER "000000000001" + +#define USB_DESC_TYPE_INTERFACE 0x04U +#define USB_DESC_TYPE_ENDPOINT 0x05U +#define USB_DESC_TYPE_CONFIGURATION 0x02U +#define USB_DESC_TYPE_IAD 0x0BU + +#define USBD_EP_TYPE_CTRL 0x00U +#define USBD_EP_TYPE_ISOC 0x01U +#define USBD_EP_TYPE_BULK 0x02U +#define USBD_EP_TYPE_INTR 0x03U + +#define USBD_FULL_SPEED 0x00U +#define USBD_HIGH_SPEED 0x01U + +#define USB_BCDUSB 0x0200U +#define LANGUAGE_ID_MAX_LENGTH 2U + +#define USBD_IDX_MFC_STR 0x01U +#define USBD_IDX_PRODUCT_STR 0x02U +#define USBD_IDX_SERIAL_STR 0x03U + +#define USBD_MAX_EP0_SIZE 64U +#define USBD_DEVICE_QUALIFIER_DESC_SIZE 0x0AU + +#define USBD_STRING_FRAMEWORK_MAX_LENGTH 256U + +/* Device Storage Class */ +#define USBD_MSC_EPOUT_ADDR 0x01U +#define USBD_MSC_EPIN_ADDR 0x81U + +#define USBD_MSC_EPOUT_FS_MPS 64U +#define USBD_MSC_EPOUT_HS_MPS 512U +#define USBD_MSC_EPIN_FS_MPS 64U +#define USBD_MSC_EPIN_HS_MPS 512U + +/* This is the maximum supported configuration descriptor size + User may redefine this value in order to optima */ +#ifndef USBD_FRAMEWORK_MAX_DESC_SZ +#define USBD_FRAMEWORK_MAX_DESC_SZ 200U +#endif /* USBD_FRAMEWORK_MAX_DESC_SZ */ + +#ifndef USBD_CONFIG_STR_DESC_IDX +#define USBD_CONFIG_STR_DESC_IDX 0U +#endif /* USBD_CONFIG_STR_DESC_IDX */ + +#ifndef USBD_CONFIG_BMATTRIBUTES +#define USBD_CONFIG_BMATTRIBUTES 0xC0U +#endif /* USBD_CONFIG_BMATTRIBUTES */ + +/* Private macro -----------------------------------------------------------*/ +/* USER CODE BEGIN Private_macro */ + +/* USER CODE END Private_macro */ +#define __USBD_FRAMEWORK_SET_EP(epadd, eptype, epsize, HSinterval, FSinterval) do { \ + /* Append Endpoint descriptor to Configuration descriptor */ \ + pEpDesc = ((USBD_EpDescTypedef*)((uint32_t)pConf + *Sze)); \ + pEpDesc->bLength = (uint8_t)sizeof(USBD_EpDescTypedef); \ + pEpDesc->bDescriptorType = USB_DESC_TYPE_ENDPOINT; \ + pEpDesc->bEndpointAddress = (epadd); \ + pEpDesc->bmAttributes = (eptype); \ + pEpDesc->wMaxPacketSize = (epsize); \ + if(pdev->Speed == USBD_HIGH_SPEED) \ + { \ + pEpDesc->bInterval = (HSinterval); \ + } \ + else \ + { \ + pEpDesc->bInterval = (FSinterval); \ + } \ + *Sze += (uint32_t)sizeof(USBD_EpDescTypedef); \ + } while(0) + +#define __USBD_FRAMEWORK_SET_IF(ifnum, alt, eps, class, subclass, protocol, istring) do {\ + /* Interface Descriptor */ \ + pIfDesc = ((USBD_IfDescTypedef*)((uint32_t)pConf + *Sze)); \ + pIfDesc->bLength = (uint8_t)sizeof(USBD_IfDescTypedef); \ + pIfDesc->bDescriptorType = USB_DESC_TYPE_INTERFACE; \ + pIfDesc->bInterfaceNumber = (ifnum); \ + pIfDesc->bAlternateSetting = (alt); \ + pIfDesc->bNumEndpoints = (eps); \ + pIfDesc->bInterfaceClass = (class); \ + pIfDesc->bInterfaceSubClass = (subclass); \ + pIfDesc->bInterfaceProtocol = (protocol); \ + pIfDesc->iInterface = (istring); \ + *Sze += (uint32_t)sizeof(USBD_IfDescTypedef); \ + } while(0) +#ifdef __cplusplus +} +#endif +#endif /* __UX_DEVICE_DESCRIPTORS_H__ */ diff --git a/src/USBX/App/ux_device_msc.c b/src/USBX/App/ux_device_msc.c new file mode 100644 index 00000000..c6154c46 --- /dev/null +++ b/src/USBX/App/ux_device_msc.c @@ -0,0 +1,61 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ux_device_msc.c + * @author MCD Application Team + * @brief USBX Device applicative file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ + +/* Includes ------------------------------------------------------------------*/ +#include "ux_device_msc.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +/* USER CODE BEGIN PFP */ + +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/src/USBX/App/ux_device_msc.h b/src/USBX/App/ux_device_msc.h new file mode 100644 index 00000000..a435f665 --- /dev/null +++ b/src/USBX/App/ux_device_msc.h @@ -0,0 +1,69 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ux_device_msc.h + * @author MCD Application Team + * @brief USBX Device MSC header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __UX_DEVICE_MSC_H__ +#define __UX_DEVICE_MSC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ux_api.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ + +/* USER CODE END Includes */ + +/* Exported types ------------------------------------------------------------*/ +/* USER CODE BEGIN ET */ + +/* USER CODE END ET */ + +/* Exported constants --------------------------------------------------------*/ +/* USER CODE BEGIN EC */ + +/* USER CODE END EC */ + +/* Exported macro ------------------------------------------------------------*/ +/* USER CODE BEGIN EM */ + +/* USER CODE END EM */ + +/* Exported functions prototypes ---------------------------------------------*/ + +/* USER CODE BEGIN EFP */ + +/* USER CODE END EFP */ + +/* Private defines -----------------------------------------------------------*/ +/* USER CODE BEGIN PD */ + +/* USER CODE END PD */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +#ifdef __cplusplus +} +#endif +#endif /* __UX_DEVICE_MSC_H__ */ diff --git a/src/USBX/App/ux_user.h b/src/USBX/App/ux_user.h new file mode 100644 index 00000000..d0ab4e56 --- /dev/null +++ b/src/USBX/App/ux_user.h @@ -0,0 +1,353 @@ +/**************************************************************************/ +/* */ +/* Copyright (c) Microsoft Corporation. All rights reserved. */ +/* */ +/* This software is licensed under the Microsoft Software License */ +/* Terms for Microsoft Azure RTOS. Full text of the license can be */ +/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ +/* and in the root directory of this software. */ +/* */ +/**************************************************************************/ + +/**************************************************************************/ +/**************************************************************************/ +/** */ +/** USBX Component */ +/** */ +/** User Specific */ +/** */ +/**************************************************************************/ +/**************************************************************************/ + +/**************************************************************************/ +/* */ +/* PORT SPECIFIC C INFORMATION RELEASE */ +/* */ +/* ux_user.h PORTABLE C */ +/* 6.0 */ +/* */ +/* AUTHOR */ +/* */ +/* Chaoqiong Xiao, Microsoft Corporation */ +/* */ +/* DESCRIPTION */ +/* */ +/* This file contains user defines for configuring USBX in specific */ +/* ways. This file will have an effect only if the application and */ +/* USBX library are built with UX_INCLUDE_USER_DEFINE_FILE defined. */ +/* Note that all the defines in this file may also be made on the */ +/* command line when building USBX library and application objects. */ +/* */ +/* RELEASE HISTORY */ +/* */ +/* DATE NAME DESCRIPTION */ +/* */ +/* 05-19-2020 Chaoqiong Xiao Initial Version 6.0 */ +/* */ +/**************************************************************************/ + +#ifndef UX_USER_H +#define UX_USER_H + +/* Define various build options for the USBX port. The application should either make changes + here by commenting or un-commenting the conditional compilation defined OR supply the defines + through the compiler's equivalent of the -D option. Override various options with default values + already assigned in ux_api.h or ux_port.h. Please also refer to ux_port.h for descriptions on + each of these options. */ + +/* This value is the size of the stack in bytes for the USBX threads. It can be typically 1024 bytes + or 2048 bytes depending on the processor used and the host controller. */ + +#define UX_THREAD_STACK_SIZE 4096 + +/* Define USBX Host Enum Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_ENUM_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HCD_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE +*/ + +/* Define USBX Host HNP Polling Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE */ +/* +#define UX_HOST_HNP_POLLING_THREAD_STACK UX_THREAD_STACK_SIZE +*/ + +/* Defined, this value represents how many ticks per seconds for a specific hardware platform. + The default is 1000 indicating 1 tick per millisecond. */ + +/* #define UX_PERIODIC_RATE (TX_TIMER_TICKS_PER_SECOND)*/ + +/* Defined, this value is the maximum number of classes that can be loaded by USBX. This value + represents the class container and not the number of instances of a class. For instance, if a + particular implementation of USBX needs the hub class, the printer class, and the storage + class, then the UX_MAX_CLASSES value can be set to 3 regardless of the number of devices + that belong to these classes. */ + +/* #define UX_MAX_CLASS_DRIVER 3 */ + +/* Defined, this value is the maximum number of classes in the device stack that can be loaded by + USBX. */ +#define UX_MAX_SLAVE_CLASS_DRIVER 1 + +/* Defined, this value is the maximum number of interfaces in the device framework. */ + +/* #define UX_MAX_SLAVE_INTERFACES 16 */ + +/* Defined, this value represents the number of different host controllers available in the system. + For USB 1.1 support, this value will usually be 1. For USB 2.0 support, this value can be more + than 1. This value represents the number of concurrent host controllers running at the same time. + If for instance there are two instances of OHCI running, or one EHCI and one OHCI controller + running, the UX_MAX_HCD should be set to 2. */ + +#define UX_MAX_HCD 2 + +/* Defined, this value represents the maximum number of devices that can be attached to the USB. + Normally, the theoretical maximum number on a single USB is 127 devices. This value can be + scaled down to conserve memory. Note that this value represents the total number of devices + regardless of the number of USB buses in the system. */ + +/* #define UX_MAX_DEVICES 127 */ + +/* Defined, this value represents the current number of SCSI logical units represented in the device + storage class driver. */ + +/* #define UX_MAX_SLAVE_LUN 1 */ + +/* Defined, this value represents the maximum number of SCSI logical units represented in the + host storage class driver. */ + +/* #define UX_MAX_HOST_LUN 1 */ + +/* Defined, this value represents the maximum number of bytes received on a control endpoint in + the device stack. The default is 256 bytes but can be reduced in memory constraint environments. */ + +/* #define UX_SLAVE_REQUEST_CONTROL_MAX_LENGTH 256 */ + +/* Defined, this value represents the maximum number of bytes that can be received or transmitted + on any endpoint. This value cannot be less than the maximum packet size of any endpoint. The default + is 4096 bytes but can be reduced in memory constraint environments. For cd-rom support in the storage + class, this value cannot be less than 2048. */ + +/* #define UX_SLAVE_REQUEST_DATA_MAX_LENGTH 4096 */ + +/* Defined, this value includes code to handle storage Multi-Media Commands (MMC). E.g., DVD-ROM. */ + +/* #define UX_SLAVE_CLASS_STORAGE_INCLUDE_MMC */ + +/* Defined, this value represents the maximum number of bytes that a storage payload can send/receive. + The default is 8K bytes but can be reduced in memory constraint environments. */ + +/* #define UX_HOST_CLASS_STORAGE_MEMORY_BUFFER_SIZE 8192 */ + +/* Define USBX Mass Storage Thread Stack Size. The default is to use UX_THREAD_STACK_SIZE. */ + +/* #define UX_HOST_CLASS_STORAGE_THREAD_STACK_SIZE UX_THREAD_STACK_SIZE */ + +/* Defined, this value represents the maximum number of Ed, regular TDs and Isochronous TDs. These values + depend on the type of host controller and can be reduced in memory constraint environments. */ + +/* #define UX_MAX_ED 80 */ + +/* #define UX_MAX_TD 128 */ + +/* #define UX_MAX_ISO_TD 1 */ + +/* Defined, this value represents the maximum size of the HID decompressed buffer. This cannot be determined + in advance so we allocate a big block, usually 4K but for simple HID devices like keyboard and mouse + it can be reduced a lot. */ + +/* #define UX_HOST_CLASS_HID_DECOMPRESSION_BUFFER 4096 */ + +/* Defined, this value represents the maximum number of HID usages for a HID device. + Default is 2048 but for simple HID devices like keyboard and mouse it can be reduced a lot. */ + +/* #define UX_HOST_CLASS_HID_USAGES 2048 */ + +/* By default, each key in each HID report from the device is reported by ux_host_class_hid_keyboard_key_get + (a HID report from the device is received whenever there is a change in a key state i.e. when a key is pressed + or released. The report contains every key that is down). There are limitations to this method such as not being + able to determine when a key has been released. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key changes i.e. key presses + and key releases. */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to only report key pressed/down changes; + key released/up changes are not reported. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_KEY_DOWN_ONLY */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report lock key (CapsLock/NumLock/ScrollLock) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_LOCK_KEYS */ + +/* Works when UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE is defined. + + Defined, this value causes ux_host_class_hid_keyboard_key_get to report modifier key (Ctrl/Alt/Shift/GUI) changes. + */ + +/* #define UX_HOST_CLASS_HID_KEYBOARD_EVENTS_KEY_CHANGES_MODE_REPORT_MODIFIER_KEYS */ + +/* Defined, this value represents the maximum number of media for the host storage class. + Default is 8 but for memory constrained resource systems this can ne reduced to 1. */ + +/* #define UX_HOST_CLASS_STORAGE_MAX_MEDIA 2 */ + +/* Defined, this value includes code to handle storage devices that use the CB + or CBI protocol (such as floppy disks). It is off by default because these + protocols are obsolete, being superseded by the Bulk Only Transport (BOT) protocol + which virtually all modern storage devices use. +*/ + +/* #define UX_HOST_CLASS_STORAGE_INCLUDE_LEGACY_PROTOCOL_SUPPORT */ + +/* Defined, this value forces the memory allocation scheme to enforce alignment + of memory with the UX_SAFE_ALIGN field. +*/ + +/* #define UX_ENFORCE_SAFE_ALIGNMENT */ + +/* Defined, this value represents the number of packets in the CDC_ECM device class. + The default is 16. +*/ + +/* #define UX_DEVICE_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 4 */ + +/* Defined, this value represents the number of packets in the CDC_ECM host class. + The default is 16. +*/ +/* #define UX_HOST_CLASS_CDC_ECM_NX_PKPOOL_ENTRIES 16 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. + The default is 1000 milliseconds. +*/ +/* #define UX_HOST_CLASS_CDC_ECM_PACKET_POOL_WAIT 10 */ + +/* Defined, this value represents the number of milliseconds to wait for packet + allocation until invoking the application's error callback and retrying. +*/ +/* #define UX_DEVICE_CLASS_CDC_ECM_PACKET_POOL_WAIT 1000 */ + +/* Defined, this value represents the the maximum length of HID reports on the + device. + */ + +/* #define UX_DEVICE_CLASS_HID_EVENT_BUFFER_LENGTH 64 */ + +/* Defined, this value represents the the maximum number of HID events/reports + that can be queued at once. + */ + +/* #define UX_DEVICE_CLASS_HID_MAX_EVENTS_QUEUE 8 */ + +/* Defined, this macro will disable DFU_UPLOAD support. */ + +/* #define UX_DEVICE_CLASS_DFU_UPLOAD_DISABLE */ + +/* Defined, this macro will enable DFU_GETSTATUS and DFU_GETSTATE in dfuERROR. */ + +/* #define UX_DEVICE_CLASS_DFU_ERROR_GET_ENABLE */ + +/* Defined, this macro will change status mode. + 0 - simple mode, + status is queried from application in dfuDNLOAD-SYNC and dfuMANIFEST-SYNC state, + no bwPollTimeout. + 1 - status is queried from application once requested, + b0-3 : media status + b4-7 : bStatus + b8-31: bwPollTimeout + bwPollTimeout supported. +*/ + +#define UX_DEVICE_CLASS_DFU_STATUS_MODE 1 + +/* Defined, this value represents the default DFU status bwPollTimeout. + The value is 3 bytes long (max 0xFFFFFFu). + By default the bwPollTimeout is 1 (means 1ms). + */ + +#define UX_DEVICE_CLASS_DFU_STATUS_POLLTIMEOUT 0 + +/* Defined, this macro will enable custom request process callback. */ + +/* #define UX_DEVICE_CLASS_DFU_CUSTOM_REQUEST_ENABLE */ + +/* Defined, this value will only enable the host side of usbx. */ + +/* #define UX_HOST_SIDE_ONLY */ + +#define UX_DEVICE_SIDE_ONLY + +/* Defined, this value will include the OTG polling thread. OTG can only be active if both host/device are present. +*/ + +#ifndef UX_HOST_SIDE_ONLY +#ifndef UX_DEVICE_SIDE_ONLY + +#define UX_OTG_SUPPORT + +#endif +#endif + +/* Defined, this value represents the maximum size of single tansfers for the SCSI data phase. +*/ + +/* #define UX_HOST_CLASS_STORAGE_MAX_TRANSFER_SIZE (1024 * 1) */ + +/* Defined, this value represents the size of the log pool. +*/ +/* #define UX_DEBUG_LOG_SIZE (1024 * 16) */ + +/* This is the ThreadX priority value for the USBX enumeration threads that monitors the bus topology */ + +/* #define UX_THREAD_PRIORITY_ENUM 20 */ + +/* This is the ThreadX priority value for the standard USBX threads */ + +/* #define UX_THREAD_PRIORITY_CLASS 20 */ + +/* This is the ThreadX priority value for the USBX HID keyboard class. */ + +/* #define UX_THREAD_PRIORITY_KEYBOARD 20 */ + +/* This is the ThreadX priority value for the host controller thread. */ + +/* #define UX_THREAD_PRIORITY_HCD 2 */ + +/* This value actually defines the time slice that will be used for threads. For example, if defined to 0, the ThreadX target port does not use time slices. */ + +/* #define UX_NO_TIME_SLICE 0 */ + +/* it define USBX device max number of endpoints (1~n). */ + +/* #define UX_MAX_DEVICE_ENDPOINTS 6 */ + +/* it define USBX device max number of interfacess (1~n). */ + +/* #define UX_MAX_DEVICE_INTERFACES 6 */ + +/* Define USBX max TT. */ + +/* #define UX_MAX_TT 8 */ + +/* Determine if tracing is enabled. */ + +/*#define UX_TRACE_INSERT_MACROS*/ + +/* Defined, this macro enables device bi-directional endpoint support. */ + +#define UX_DEVICE_BIDIRECTIONAL_ENDPOINT_SUPPORT + +#endif + diff --git a/src/USBX/Target/ux_stm32_config.h b/src/USBX/Target/ux_stm32_config.h new file mode 100644 index 00000000..fc027260 --- /dev/null +++ b/src/USBX/Target/ux_stm32_config.h @@ -0,0 +1,50 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file ux_stm32_config.h + * @author MCD Application Team + * @brief USBX STM32 config header file + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __UX_STM32_CONFIG_H__ +#define __UX_STM32_CONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f7xx_hal.h" + +/* USER CODE BEGIN Private Includes */ + +/* USER CODE BEGIN Private Includes */ + +/* Private defines -----------------------------------------------------------*/ + +#define UX_DCD_STM32_MAX_ED 9 + +/* USER CODE BEGIN Private defines */ + +/* USER CODE END Private defines */ + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ + +#ifdef __cplusplus +} +#endif +#endif /* __UX_STM32_CONFIG_H__ */ diff --git a/src/VCU.ioc b/src/VCU.ioc index 8c78e09b..c6b9947c 100644 --- a/src/VCU.ioc +++ b/src/VCU.ioc @@ -1,454 +1,826 @@ -#MicroXplorer Configuration settings - do not modify -ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3 -ADC1.Channel-IN3=ADC_CHANNEL_3 -ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2 -ADC1.ContinuousConvMode=DISABLE -ADC1.DMAContinuousRequests=DISABLE -ADC1.DataAlign=ADC_DATAALIGN_RIGHT -ADC1.DiscontinuousConvMode=DISABLE -ADC1.EOCSelection=ADC_EOC_SINGLE_CONV -ADC1.EnableAnalogWatchDog=false -ADC1.ExternalTrigConv=ADC_SOFTWARE_START -ADC1.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE -ADC1.IPParameters=Channel-IN3,Mode,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,master -ADC1.InjNumberOfConversion=0 -ADC1.Mode=__NULL -ADC1.NbrOfConversion=1 -ADC1.Rank-0\#ChannelRegularConversion=1 -ADC1.Resolution=ADC_RESOLUTION_12B -ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES -ADC1.ScanConvMode=ADC_SCAN_DISABLE -ADC1.master=1 -ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_13 -ADC2.Channel-IN13=ADC_CHANNEL_13 -ADC2.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2 -ADC2.ContinuousConvMode=DISABLE -ADC2.DMAContinuousRequests=DISABLE -ADC2.DataAlign=ADC_DATAALIGN_RIGHT -ADC2.DiscontinuousConvMode=DISABLE -ADC2.EOCSelection=ADC_EOC_SINGLE_CONV -ADC2.EnableAnalogWatchDog=false -ADC2.ExternalTrigConv=ADC_SOFTWARE_START -ADC2.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE -ADC2.IPParameters=Channel-IN13,Mode,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion -ADC2.InjNumberOfConversion=0 -ADC2.Mode=__NULL -ADC2.NbrOfConversion=1 -ADC2.Rank-0\#ChannelRegularConversion=1 -ADC2.Resolution=ADC_RESOLUTION_12B -ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES -ADC2.ScanConvMode=ADC_SCAN_DISABLE -ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_10 -ADC3.Channel-IN10=ADC_CHANNEL_10 -ADC3.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2 -ADC3.ContinuousConvMode=DISABLE -ADC3.DMAContinuousRequests=DISABLE -ADC3.DataAlign=ADC_DATAALIGN_RIGHT -ADC3.DiscontinuousConvMode=DISABLE -ADC3.EOCSelection=ADC_EOC_SINGLE_CONV -ADC3.EnableAnalogWatchDog=false -ADC3.ExternalTrigConv=ADC_SOFTWARE_START -ADC3.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE -ADC3.IPParameters=Channel-IN10,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion -ADC3.InjNumberOfConversion=0 -ADC3.NbrOfConversion=1 -ADC3.Rank-0\#ChannelRegularConversion=1 -ADC3.Resolution=ADC_RESOLUTION_12B -ADC3.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES -ADC3.ScanConvMode=ADC_SCAN_DISABLE -CAD.formats=[] -CAD.pinconfig=Dual -CAD.provider= -CAN1.ABOM=ENABLE -CAN1.AWUM=DISABLE -CAN1.BS1=CAN_BS1_2TQ -CAN1.BS2=CAN_BS2_1TQ -CAN1.CalculateBaudRate=500000 -CAN1.CalculateTimeBit=2000 -CAN1.CalculateTimeQuantum=500.0 -CAN1.IPParameters=Prescaler,BS1,BS2,SJW,TTCM,ABOM,AWUM,NART,RFLM,TXFP,Mode,CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate -CAN1.Mode=CAN_MODE_NORMAL -CAN1.NART=DISABLE -CAN1.Prescaler=18 -CAN1.RFLM=DISABLE -CAN1.SJW=CAN_SJW_1TQ -CAN1.TTCM=DISABLE -CAN1.TXFP=DISABLE -CAN2.ABOM=ENABLE -CAN2.AWUM=DISABLE -CAN2.BS1=CAN_BS1_2TQ -CAN2.BS2=CAN_BS2_1TQ -CAN2.CalculateBaudRate=500000 -CAN2.CalculateTimeBit=2000 -CAN2.CalculateTimeQuantum=500.0 -CAN2.IPParameters=Prescaler,BS1,BS2,SJW,TTCM,ABOM,AWUM,NART,RFLM,TXFP,Mode,CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate -CAN2.Mode=CAN_MODE_NORMAL -CAN2.NART=DISABLE -CAN2.Prescaler=18 -CAN2.RFLM=DISABLE -CAN2.SJW=CAN_SJW_1TQ -CAN2.TTCM=DISABLE -CAN2.TXFP=DISABLE -CORTEX_M7.ART_ACCELERATOR_ENABLE=0 -CORTEX_M7.CPU_DCache=Disabled -CORTEX_M7.CPU_ICache=Disabled -CORTEX_M7.FlashInterface=AXI_Enabled -CORTEX_M7.IPParameters=default_mode_Activation,FlashInterface,ART_ACCELERATOR_ENABLE,PREFETCH_ENABLE,CPU_ICache,CPU_DCache,MPU_Control -CORTEX_M7.MPU_Control=__NULL -CORTEX_M7.PREFETCH_ENABLE=0 -CORTEX_M7.default_mode_Activation=0 -File.Version=6 -GPIO.groupedBy=Group By Peripherals -KeepUserPlacement=false -Mcu.CPN=STM32F746ZGT6 -Mcu.Family=STM32F7 -Mcu.IP0=ADC1 -Mcu.IP1=ADC2 -Mcu.IP2=ADC3 -Mcu.IP3=CAN1 -Mcu.IP4=CAN2 -Mcu.IP5=CORTEX_M7 -Mcu.IP6=NVIC -Mcu.IP7=RCC -Mcu.IP8=SYS -Mcu.IP9=USART1 -Mcu.IPNb=10 -Mcu.Name=STM32F746ZGTx -Mcu.Package=LQFP144 -Mcu.Pin0=PE3 -Mcu.Pin1=PE4 -Mcu.Pin10=PF5 -Mcu.Pin11=PF10 -Mcu.Pin12=PH0/OSC_IN -Mcu.Pin13=PH1/OSC_OUT -Mcu.Pin14=PC0 -Mcu.Pin15=PC3 -Mcu.Pin16=PA0/WKUP -Mcu.Pin17=PA3 -Mcu.Pin18=PB0 -Mcu.Pin19=PF14 -Mcu.Pin2=PE5 -Mcu.Pin20=PF15 -Mcu.Pin21=PE9 -Mcu.Pin22=PE11 -Mcu.Pin23=PB12 -Mcu.Pin24=PB14 -Mcu.Pin25=PA9 -Mcu.Pin26=PA10 -Mcu.Pin27=PA13 -Mcu.Pin28=PA14 -Mcu.Pin29=PA15 -Mcu.Pin3=PE6 -Mcu.Pin30=PD0 -Mcu.Pin31=PD1 -Mcu.Pin32=PB3 -Mcu.Pin33=PB4 -Mcu.Pin34=PB6 -Mcu.Pin35=PB7 -Mcu.Pin36=PB8 -Mcu.Pin37=PB9 -Mcu.Pin38=VP_SYS_VS_tim3 -Mcu.Pin39=VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0 -Mcu.Pin4=PC13 -Mcu.Pin5=PC14/OSC32_IN -Mcu.Pin6=PC15/OSC32_OUT -Mcu.Pin7=PF1 -Mcu.Pin8=PF2 -Mcu.Pin9=PF3 -Mcu.PinsNb=40 -Mcu.ThirdParty0=STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0 -Mcu.ThirdPartyNb=1 -Mcu.UserConstants= -Mcu.UserName=STM32F746ZGTx -MxCube.Version=6.9.2 -MxDb.Version=DB.6.0.92 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false -NVIC.CAN1_RX0_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true -NVIC.CAN1_RX1_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true -NVIC.CAN1_TX_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true -NVIC.CAN2_RX0_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true -NVIC.CAN2_RX1_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true -NVIC.CAN2_TX_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false -NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true -NVIC.ForceEnableDMAVector=true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false -NVIC.SavedPendsvIrqHandlerGenerated=false -NVIC.SavedSvcallIrqHandlerGenerated=false -NVIC.SavedSystickIrqHandlerGenerated=false -NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:true\:false -NVIC.TIM3_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true -NVIC.TimeBase=TIM3_IRQn -NVIC.TimeBaseIP=TIM3 -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false -PA0/WKUP.GPIOParameters=GPIO_Label -PA0/WKUP.GPIO_Label=DRS -PA0/WKUP.Locked=true -PA0/WKUP.Signal=GPIO_Output -PA10.Locked=true -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA13.GPIOParameters=GPIO_Label -PA13.GPIO_Label=TMS -PA13.Locked=true -PA13.Mode=JTAG_5_pins -PA13.Signal=SYS_JTMS-SWDIO -PA14.GPIOParameters=GPIO_Label -PA14.GPIO_Label=TCK -PA14.Locked=true -PA14.Mode=JTAG_5_pins -PA14.Signal=SYS_JTCK-SWCLK -PA15.Locked=true -PA15.Mode=JTAG_5_pins -PA15.Signal=SYS_JTDI -PA3.GPIOParameters=GPIO_Label -PA3.GPIO_Label=APPS_1_ADC -PA3.Locked=true -PA3.Signal=ADCx_IN3 -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX -PB0.GPIOParameters=GPIO_Label -PB0.GPIO_Label=GREEN_LED -PB0.Locked=true -PB0.Signal=GPIO_Output -PB12.GPIOParameters=GPIO_PuPd -PB12.GPIO_PuPd=GPIO_PULLUP -PB12.Mode=CAN_Activate -PB12.Signal=CAN2_RX -PB14.GPIOParameters=GPIO_Label -PB14.GPIO_Label=RED_LED -PB14.Locked=true -PB14.Signal=GPIO_Output -PB3.Locked=true -PB3.Mode=JTAG_5_pins -PB3.Signal=SYS_JTDO-SWO -PB4.Locked=true -PB4.Mode=JTAG_5_pins -PB4.Signal=SYS_JTRST -PB6.GPIOParameters=GPIO_PuPd -PB6.GPIO_PuPd=GPIO_PULLUP -PB6.Mode=CAN_Activate -PB6.Signal=CAN2_TX -PB7.GPIOParameters=GPIO_Label -PB7.GPIO_Label=BLUE_LED -PB7.Locked=true -PB7.Signal=GPIO_Output -PB8.Locked=true -PB8.Signal=I2C1_SCL -PB9.Locked=true -PB9.Signal=I2C1_SDA -PC0.GPIOParameters=GPIO_Label -PC0.GPIO_Label=BPS_ADC -PC0.Locked=true -PC0.Signal=ADCx_IN10 -PC13.GPIOParameters=GPIO_Label -PC13.GPIO_Label=USER_BUTTON -PC13.Locked=true -PC13.Signal=GPXTI13 -PC14/OSC32_IN.Locked=true -PC14/OSC32_IN.Signal=RCC_OSC32_IN -PC15/OSC32_OUT.Locked=true -PC15/OSC32_OUT.Signal=RCC_OSC32_OUT -PC3.GPIOParameters=GPIO_Label -PC3.GPIO_Label=APPS_2_ADC -PC3.Locked=true -PC3.Signal=ADCx_IN13 -PD0.GPIOParameters=GPIO_PuPd -PD0.GPIO_PuPd=GPIO_PULLUP -PD0.Mode=CAN_Activate -PD0.Signal=CAN1_RX -PD1.GPIOParameters=GPIO_PuPd -PD1.GPIO_PuPd=GPIO_PULLUP -PD1.Mode=CAN_Activate -PD1.Signal=CAN1_TX -PE11.GPIOParameters=GPIO_Label -PE11.GPIO_Label=BRAKE_PRESSED -PE11.Locked=true -PE11.Signal=GPIO_Output -PE3.GPIOParameters=GPIO_Label -PE3.GPIO_Label=VC_LEDS -PE3.Locked=true -PE3.Signal=GPIO_Output -PE4.GPIOParameters=GPIO_Label -PE4.GPIO_Label=DRS_LED -PE4.Locked=true -PE4.Signal=GPIO_Output -PE5.GPIOParameters=GPIO_Label -PE5.GPIO_Label=TS_ON_LED -PE5.Locked=true -PE5.Signal=GPIO_Output -PE6.GPIOParameters=GPIO_Label -PE6.GPIO_Label=R2D_LED -PE6.Locked=true -PE6.Signal=GPIO_Output -PE9.GPIOParameters=GPIO_Label -PE9.GPIO_Label=STATUS -PE9.Locked=true -PE9.Signal=GPIO_Output -PF1.GPIOParameters=GPIO_PuPd,GPIO_Label -PF1.GPIO_Label=TS_READY -PF1.GPIO_PuPd=GPIO_PULLDOWN -PF1.Locked=true -PF1.Signal=GPIO_Input -PF10.GPIOParameters=GPIO_PuPd,GPIO_Label -PF10.GPIO_Label=DRS_BTN -PF10.GPIO_PuPd=GPIO_PULLDOWN -PF10.Locked=true -PF10.Signal=GPIO_Input -PF14.GPIOParameters=GPIO_Label -PF14.GPIO_Label=TS_ON -PF14.Locked=true -PF14.Signal=GPIO_Output -PF15.GPIOParameters=GPIO_Label -PF15.GPIO_Label=R2D_SIREN -PF15.Locked=true -PF15.Signal=GPIO_Output -PF2.GPIOParameters=GPIO_PuPd,GPIO_Label -PF2.GPIO_Label=R2D_BTN -PF2.GPIO_PuPd=GPIO_PULLDOWN -PF2.Locked=true -PF2.Signal=GPIO_Input -PF3.GPIOParameters=GPIO_Label -PF3.GPIO_Label=SAGL -PF3.Locked=true -PF3.Signal=GPIO_Input -PF5.GPIOParameters=GPIO_PuPd,GPIO_Label -PF5.GPIO_Label=TS_ON_BTN -PF5.GPIO_PuPd=GPIO_PULLDOWN -PF5.Locked=true -PF5.Signal=GPIO_Input -PH0/OSC_IN.GPIOParameters=GPIO_Label -PH0/OSC_IN.GPIO_Label=MCO [STM32F103CBT6_PA8] -PH0/OSC_IN.Locked=true -PH0/OSC_IN.Mode=HSE-External-Oscillator -PH0/OSC_IN.Signal=RCC_OSC_IN -PH1/OSC_OUT.Locked=true -PH1/OSC_OUT.Mode=HSE-External-Oscillator -PH1/OSC_OUT.Signal=RCC_OSC_OUT -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=true -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32F746ZGTx -ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.2 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=0 -ProjectManager.MainLocation=Core/Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=VCU.ioc -ProjectManager.ProjectName=VCU -ProjectManager.ProjectStructure= -ProjectManager.RegisterCallBack= -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=Makefile -ProjectManager.ToolChainLocation= -ProjectManager.UAScriptAfterPath= -ProjectManager.UAScriptBeforePath= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC3_Init-ADC3-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_ADC2_Init-ADC2-false-HAL-true,6-MX_CAN1_Init-CAN1-false-HAL-true,7-MX_CAN2_Init-CAN2-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true -RCC.AHBFreq_Value=72000000 -RCC.APB1CLKDivider=RCC_HCLK_DIV2 -RCC.APB1Freq_Value=36000000 -RCC.APB1TimFreq_Value=72000000 -RCC.APB2Freq_Value=72000000 -RCC.APB2TimFreq_Value=72000000 -RCC.CECFreq_Value=32786.88524590164 -RCC.CortexFreq_Value=72000000 -RCC.EthernetFreq_Value=72000000 -RCC.FCLKCortexFreq_Value=72000000 -RCC.FLatency=FLASH_LATENCY_2 -RCC.FamilyName=M -RCC.HCLKFreq_Value=72000000 -RCC.HSE_VALUE=8000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=36000000 -RCC.I2C2Freq_Value=36000000 -RCC.I2C3Freq_Value=36000000 -RCC.I2C4Freq_Value=36000000 -RCC.I2SFreq_Value=192000000 -RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FLatency,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value -RCC.LCDTFToutputFreq_Value=96000000 -RCC.LPTIM1Freq_Value=36000000 -RCC.LSE_VALUE=32768 -RCC.LSI_VALUE=32000 -RCC.MCO2PinFreq_Value=72000000 -RCC.PLLCLKFreq_Value=72000000 -RCC.PLLI2SPCLKFreq_Value=192000000 -RCC.PLLI2SQCLKFreq_Value=192000000 -RCC.PLLI2SRCLKFreq_Value=192000000 -RCC.PLLI2SRoutputFreq_Value=192000000 -RCC.PLLM=4 -RCC.PLLN=72 -RCC.PLLQ=3 -RCC.PLLQCLKFreq_Value=48000000 -RCC.PLLQoutputFreq_Value=48000000 -RCC.PLLSAIPCLKFreq_Value=192000000 -RCC.PLLSAIQCLKFreq_Value=192000000 -RCC.PLLSAIRCLKFreq_Value=192000000 -RCC.PLLSAIoutputFreq_Value=192000000 -RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE -RCC.RNGFreq_Value=48000000 -RCC.SAI1Freq_Value=192000000 -RCC.SAI2Freq_Value=192000000 -RCC.SDMMCFreq_Value=72000000 -RCC.SPDIFRXFreq_Value=192000000 -RCC.SYSCLKFreq_VALUE=72000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.UART4Freq_Value=36000000 -RCC.UART5Freq_Value=36000000 -RCC.UART7Freq_Value=36000000 -RCC.UART8Freq_Value=36000000 -RCC.USART1Freq_Value=72000000 -RCC.USART2Freq_Value=36000000 -RCC.USART3Freq_Value=36000000 -RCC.USART6Freq_Value=72000000 -RCC.USBFreq_Value=48000000 -RCC.VCOI2SOutputFreq_Value=384000000 -RCC.VCOInputFreq_Value=2000000 -RCC.VCOOutputFreq_Value=144000000 -RCC.VCOSAIOutputFreq_Value=384000000 -SH.ADCx_IN10.0=ADC3_IN10,IN10 -SH.ADCx_IN10.ConfNb=1 -SH.ADCx_IN13.0=ADC2_IN13,IN13 -SH.ADCx_IN13.ConfNb=1 -SH.ADCx_IN3.0=ADC1_IN3,IN3 -SH.ADCx_IN3.ConfNb=1 -SH.GPXTI13.0=GPIO_EXTI13 -SH.GPXTI13.ConfNb=1 -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.IPParameters=TX_APP_MEM_POOL_SIZE,TX_DISABLE_PREEMPTION_THRESHOLD,TX_DISABLE_NOTIFY_CALLBACKS,TX_TIMER_TICKS_PER_SECOND,TX_SAFETY_CRITICAL,ThreadXCcRTOSJjThreadXJjCore,ThreadXCcRTOSJjThreadXJjPerformanceInfo,ThreadXCcRTOSJjThreadXJjTraceXOosupport,ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.RTOSJjThreadX_Checked=true -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_APP_MEM_POOL_SIZE=16384 -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_DISABLE_NOTIFY_CALLBACKS=0 -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_DISABLE_PREEMPTION_THRESHOLD=0 -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_SAFETY_CRITICAL=1 -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_TIMER_TICKS_PER_SECOND=1000 -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjCore=true -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport=true -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjPerformanceInfo=true -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjTraceXOosupport=true -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0_IsAnAzureRtosMw=true -STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0_SwParameter=ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport\:true;ThreadXCcRTOSJjThreadXJjPerformanceInfo\:true;ThreadXCcRTOSJjThreadXJjTraceXOosupport\:true;ThreadXCcRTOSJjThreadXJjCore\:true; -USART1.IPParameters=VirtualMode-Asynchronous -USART1.VirtualMode-Asynchronous=VM_ASYNC -VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0.Mode=RTOSJjThreadX -VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0 -VP_SYS_VS_tim3.Mode=TIM3 -VP_SYS_VS_tim3.Signal=SYS_VS_tim3 -board=NUCLEO-F746ZG +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_8 +ADC1.Channel-14\#ChannelRegularConversion=ADC_CHANNEL_7 +ADC1.Channel-15\#ChannelRegularConversion=ADC_CHANNEL_5 +ADC1.Channel-16\#ChannelRegularConversion=ADC_CHANNEL_6 +ADC1.Channel-17\#ChannelRegularConversion=ADC_CHANNEL_4 +ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4 +ADC1.ContinuousConvMode=ENABLE +ADC1.DMAContinuousRequests=ENABLE +ADC1.IPParameters=Rank-0\#ChannelRegularConversion,master,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,ScanConvMode,ContinuousConvMode,Mode,Resolution,NbrOfConversion,DMAContinuousRequests,Rank-14\#ChannelRegularConversion,Channel-14\#ChannelRegularConversion,SamplingTime-14\#ChannelRegularConversion,Rank-15\#ChannelRegularConversion,Channel-15\#ChannelRegularConversion,SamplingTime-15\#ChannelRegularConversion,Rank-16\#ChannelRegularConversion,Channel-16\#ChannelRegularConversion,SamplingTime-16\#ChannelRegularConversion,Rank-17\#ChannelRegularConversion,Channel-17\#ChannelRegularConversion,SamplingTime-17\#ChannelRegularConversion +ADC1.Mode=__NULL +ADC1.NbrOfConversion=5 +ADC1.NbrOfConversionFlag=1 +ADC1.Rank-0\#ChannelRegularConversion=1 +ADC1.Rank-14\#ChannelRegularConversion=2 +ADC1.Rank-15\#ChannelRegularConversion=3 +ADC1.Rank-16\#ChannelRegularConversion=4 +ADC1.Rank-17\#ChannelRegularConversion=5 +ADC1.Resolution=ADC_RESOLUTION_12B +ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_144CYCLES +ADC1.SamplingTime-14\#ChannelRegularConversion=ADC_SAMPLETIME_144CYCLES +ADC1.SamplingTime-15\#ChannelRegularConversion=ADC_SAMPLETIME_144CYCLES +ADC1.SamplingTime-16\#ChannelRegularConversion=ADC_SAMPLETIME_144CYCLES +ADC1.SamplingTime-17\#ChannelRegularConversion=ADC_SAMPLETIME_144CYCLES +ADC1.ScanConvMode=ADC_SCAN_ENABLE +ADC1.master=1 +ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_15 +ADC2.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV4 +ADC2.ContinuousConvMode=ENABLE +ADC2.DMAContinuousRequests=ENABLE +ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,ScanConvMode,ContinuousConvMode,DMAContinuousRequests +ADC2.NbrOfConversionFlag=1 +ADC2.Rank-0\#ChannelRegularConversion=1 +ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_144CYCLES +ADC2.ScanConvMode=ADC_SCAN_ENABLE +CAD.formats= +CAD.pinconfig= +CAD.provider= +CAN1.ABOM=ENABLE +CAN1.BS1=CAN_BS1_14TQ +CAN1.BS2=CAN_BS2_3TQ +CAN1.CalculateBaudRate=1000000 +CAN1.CalculateTimeBit=1000 +CAN1.CalculateTimeQuantum=55.55555555555556 +CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS1,Prescaler,BS2,ABOM,NART,SJW +CAN1.NART=ENABLE +CAN1.Prescaler=3 +CAN1.SJW=CAN_SJW_2TQ +CAN2.ABOM=ENABLE +CAN2.BS1=CAN_BS1_14TQ +CAN2.BS2=CAN_BS2_3TQ +CAN2.CalculateBaudRate=500000 +CAN2.CalculateTimeBit=2000 +CAN2.CalculateTimeQuantum=111.11111111111111 +CAN2.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,BS2,BS1,Prescaler,ABOM,NART,SJW +CAN2.NART=ENABLE +CAN2.Prescaler=6 +CAN2.SJW=CAN_SJW_2TQ +CORTEX_M7.IPParameters=default_mode_Activation +CORTEX_M7.default_mode_Activation=1 +Dma.ADC1.2.Direction=DMA_PERIPH_TO_MEMORY +Dma.ADC1.2.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.ADC1.2.Instance=DMA2_Stream0 +Dma.ADC1.2.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.ADC1.2.MemInc=DMA_MINC_ENABLE +Dma.ADC1.2.Mode=DMA_CIRCULAR +Dma.ADC1.2.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.ADC1.2.PeriphInc=DMA_PINC_DISABLE +Dma.ADC1.2.Priority=DMA_PRIORITY_LOW +Dma.ADC1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.ADC2.3.Direction=DMA_PERIPH_TO_MEMORY +Dma.ADC2.3.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.ADC2.3.Instance=DMA2_Stream2 +Dma.ADC2.3.MemDataAlignment=DMA_MDATAALIGN_HALFWORD +Dma.ADC2.3.MemInc=DMA_MINC_ENABLE +Dma.ADC2.3.Mode=DMA_CIRCULAR +Dma.ADC2.3.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD +Dma.ADC2.3.PeriphInc=DMA_PINC_DISABLE +Dma.ADC2.3.Priority=DMA_PRIORITY_LOW +Dma.ADC2.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +Dma.Request0=SDMMC1_RX +Dma.Request1=SDMMC1_TX +Dma.Request2=ADC1 +Dma.Request3=ADC2 +Dma.RequestsNb=4 +Dma.SDMMC1_RX.0.Direction=DMA_PERIPH_TO_MEMORY +Dma.SDMMC1_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.SDMMC1_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.SDMMC1_RX.0.Instance=DMA2_Stream3 +Dma.SDMMC1_RX.0.MemBurst=DMA_MBURST_INC4 +Dma.SDMMC1_RX.0.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.SDMMC1_RX.0.MemInc=DMA_MINC_ENABLE +Dma.SDMMC1_RX.0.Mode=DMA_PFCTRL +Dma.SDMMC1_RX.0.PeriphBurst=DMA_PBURST_INC4 +Dma.SDMMC1_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.SDMMC1_RX.0.PeriphInc=DMA_PINC_DISABLE +Dma.SDMMC1_RX.0.Priority=DMA_PRIORITY_LOW +Dma.SDMMC1_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst +Dma.SDMMC1_TX.1.Direction=DMA_MEMORY_TO_PERIPH +Dma.SDMMC1_TX.1.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.SDMMC1_TX.1.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.SDMMC1_TX.1.Instance=DMA2_Stream6 +Dma.SDMMC1_TX.1.MemBurst=DMA_MBURST_INC4 +Dma.SDMMC1_TX.1.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.SDMMC1_TX.1.MemInc=DMA_MINC_ENABLE +Dma.SDMMC1_TX.1.Mode=DMA_PFCTRL +Dma.SDMMC1_TX.1.PeriphBurst=DMA_PBURST_INC4 +Dma.SDMMC1_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.SDMMC1_TX.1.PeriphInc=DMA_PINC_DISABLE +Dma.SDMMC1_TX.1.Priority=DMA_PRIORITY_LOW +Dma.SDMMC1_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst +File.Version=6 +GPIO.groupedBy=Group By Peripherals +I2C2.IPParameters=Timing +I2C2.Timing=0x20404768 +I2C4.IPParameters=Timing +I2C4.Timing=0x20404768 +KeepUserPlacement=false +Mcu.CPN=STM32F746ZGT6 +Mcu.Family=STM32F7 +Mcu.IP0=ADC1 +Mcu.IP1=ADC2 +Mcu.IP10=SDMMC1 +Mcu.IP11=SPI6 +Mcu.IP12=SYS +Mcu.IP13=TIM2 +Mcu.IP14=TIM3 +Mcu.IP15=TIM10 +Mcu.IP16=TIM11 +Mcu.IP17=TIM12 +Mcu.IP18=UART8 +Mcu.IP19=USART1 +Mcu.IP2=CAN1 +Mcu.IP20=USB_OTG_FS +Mcu.IP3=CAN2 +Mcu.IP4=CORTEX_M7 +Mcu.IP5=DMA +Mcu.IP6=I2C2 +Mcu.IP7=I2C4 +Mcu.IP8=NVIC +Mcu.IP9=RCC +Mcu.IPNb=21 +Mcu.Name=STM32F746ZGTx +Mcu.Package=LQFP144 +Mcu.Pin0=PE2 +Mcu.Pin1=PE3 +Mcu.Pin10=PF10 +Mcu.Pin100=VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_FileOoSystemJjInterfaces_2.1.0_1.1.0 +Mcu.Pin101=VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_USBJjUSBX_6.1.10_1.1.0 +Mcu.Pin11=PH0/OSC_IN +Mcu.Pin12=PH1/OSC_OUT +Mcu.Pin13=PC0 +Mcu.Pin14=PC1 +Mcu.Pin15=PA3 +Mcu.Pin16=PA4 +Mcu.Pin17=PA5 +Mcu.Pin18=PA6 +Mcu.Pin19=PA7 +Mcu.Pin2=PE6 +Mcu.Pin20=PC4 +Mcu.Pin21=PC5 +Mcu.Pin22=PB0 +Mcu.Pin23=PB1 +Mcu.Pin24=PF13 +Mcu.Pin25=PF14 +Mcu.Pin26=PF15 +Mcu.Pin27=PE7 +Mcu.Pin28=PE8 +Mcu.Pin29=PE9 +Mcu.Pin3=PC13 +Mcu.Pin30=PE10 +Mcu.Pin31=PE11 +Mcu.Pin32=PE13 +Mcu.Pin33=PE14 +Mcu.Pin34=PE15 +Mcu.Pin35=PB10 +Mcu.Pin36=PB11 +Mcu.Pin37=PB12 +Mcu.Pin38=PB13 +Mcu.Pin39=PB14 +Mcu.Pin4=PC14/OSC32_IN +Mcu.Pin40=PB15 +Mcu.Pin41=PD8 +Mcu.Pin42=PD9 +Mcu.Pin43=PD10 +Mcu.Pin44=PD11 +Mcu.Pin45=PD12 +Mcu.Pin46=PD13 +Mcu.Pin47=PD14 +Mcu.Pin48=PD15 +Mcu.Pin49=PG2 +Mcu.Pin5=PF0 +Mcu.Pin50=PG3 +Mcu.Pin51=PG4 +Mcu.Pin52=PG5 +Mcu.Pin53=PG6 +Mcu.Pin54=PG7 +Mcu.Pin55=PG8 +Mcu.Pin56=PC6 +Mcu.Pin57=PC7 +Mcu.Pin58=PC8 +Mcu.Pin59=PC9 +Mcu.Pin6=PF1 +Mcu.Pin60=PA8 +Mcu.Pin61=PA9 +Mcu.Pin62=PA10 +Mcu.Pin63=PA11 +Mcu.Pin64=PA12 +Mcu.Pin65=PA13 +Mcu.Pin66=PA14 +Mcu.Pin67=PA15 +Mcu.Pin68=PC10 +Mcu.Pin69=PC11 +Mcu.Pin7=PF2 +Mcu.Pin70=PC12 +Mcu.Pin71=PD0 +Mcu.Pin72=PD1 +Mcu.Pin73=PD2 +Mcu.Pin74=PD3 +Mcu.Pin75=PD4 +Mcu.Pin76=PD5 +Mcu.Pin77=PD6 +Mcu.Pin78=PD7 +Mcu.Pin79=PG9 +Mcu.Pin8=PF6 +Mcu.Pin80=PG10 +Mcu.Pin81=PG11 +Mcu.Pin82=PG12 +Mcu.Pin83=PG13 +Mcu.Pin84=PG14 +Mcu.Pin85=PB3 +Mcu.Pin86=PB4 +Mcu.Pin87=PB5 +Mcu.Pin88=PB6 +Mcu.Pin89=PB7 +Mcu.Pin9=PF7 +Mcu.Pin90=PB8 +Mcu.Pin91=PB9 +Mcu.Pin92=PE0 +Mcu.Pin93=PE1 +Mcu.Pin94=VP_ADC1_Vref_Input +Mcu.Pin95=VP_SYS_VS_tim6 +Mcu.Pin96=VP_TIM10_VS_ClockSourceINT +Mcu.Pin97=VP_TIM11_VS_ClockSourceINT +Mcu.Pin98=VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0 +Mcu.Pin99=VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_FileOoSystemJjFileX_6.1.10_1.1.0 +Mcu.PinsNb=102 +Mcu.ThirdParty0=STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0 +Mcu.ThirdPartyNb=1 +Mcu.UserConstants= +Mcu.UserName=STM32F746ZGTx +MxCube.Version=6.16.1 +MxDb.Version=DB.6.0.161 +NVIC.ADC_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.CAN1_RX0_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.CAN1_RX1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.CAN1_SCE_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.CAN1_TX_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.CAN2_RX0_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.CAN2_RX1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.CAN2_SCE_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.CAN2_TX_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.DMA2_Stream0_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA2_Stream2_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:true\:true +NVIC.DMA2_Stream3_IRQn=true\:7\:0\:true\:false\:true\:true\:false\:true\:true +NVIC.DMA2_Stream6_IRQn=true\:7\:0\:true\:false\:true\:true\:false\:true\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.EXTI15_10_IRQn=true\:6\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.EXTI9_5_IRQn=true\:6\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.OTG_FS_IRQn=true\:15\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SDMMC1_IRQn=true\:7\:0\:true\:false\:true\:false\:true\:true\:true +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false +NVIC.SavedPendsvIrqHandlerGenerated=true +NVIC.SavedSvcallIrqHandlerGenerated=true +NVIC.SavedSystickIrqHandlerGenerated=true +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:true\:false +NVIC.TIM6_DAC_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.TimeBase=TIM6_DAC_IRQn +NVIC.TimeBaseIP=TIM6 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +PA10.Mode=Synchronous +PA10.Signal=USART1_RX +PA11.Mode=Device_Only +PA11.Signal=USB_OTG_FS_DM +PA12.Mode=Device_Only +PA12.Signal=USB_OTG_FS_DP +PA13.Mode=JTAG_5_pins +PA13.Signal=SYS_JTMS-SWDIO +PA14.Mode=JTAG_5_pins +PA14.Signal=SYS_JTCK-SWCLK +PA15.Mode=JTAG_5_pins +PA15.Signal=SYS_JTDI +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=SPARE_ADC +PA3.Signal=ADCx_IN3 +PA4.GPIOParameters=GPIO_Label +PA4.GPIO_Label=DASH_ROTARY_ADC +PA4.Signal=ADCx_IN4 +PA5.GPIOParameters=GPIO_Label +PA5.GPIO_Label=CT_ADC +PA5.Signal=ADCx_IN5 +PA6.GPIOParameters=GPIO_Label +PA6.GPIO_Label=SAGL_ADC +PA6.Signal=ADCx_IN6 +PA7.GPIOParameters=GPIO_Label +PA7.GPIO_Label=BPS_R_ADC +PA7.Signal=ADCx_IN7 +PA8.Mode=Synchronous +PA8.Signal=USART1_CK +PA9.Mode=Synchronous +PA9.Signal=USART1_TX +PB0.GPIOParameters=GPIO_Label +PB0.GPIO_Label=APPS_1_ADC +PB0.Locked=true +PB0.Signal=ADCx_IN8 +PB1.GPIOParameters=GPIO_Label +PB1.GPIO_Label=PWM_SPARE_1 +PB1.Locked=true +PB1.Signal=S_TIM3_CH4 +PB10.GPIOParameters=GPIO_Label +PB10.GPIO_Label=SPARE_OUT_7 +PB10.Locked=true +PB10.Signal=GPIO_Output +PB11.GPIOParameters=GPIO_Label +PB11.GPIO_Label=FAN_PWM_R +PB11.Locked=true +PB11.Signal=S_TIM2_CH4 +PB12.GPIOParameters=GPIO_Label +PB12.GPIO_Label=SPARE_OUT_6 +PB12.Locked=true +PB12.Signal=GPIO_Output +PB13.GPIOParameters=GPIO_Label +PB13.GPIO_Label=SPARE_OUT_5 +PB13.Locked=true +PB13.Signal=GPIO_Output +PB14.GPIOParameters=GPIO_Label +PB14.GPIO_Label=SPARE_OUT_4 +PB14.Locked=true +PB14.Signal=GPIO_Output +PB15.GPIOParameters=GPIO_Label +PB15.GPIO_Label=FAN_PWM_L +PB15.Locked=true +PB15.Signal=S_TIM12_CH2 +PB3.Mode=JTAG_5_pins +PB3.Signal=SYS_JTDO-SWO +PB4.Mode=JTAG_5_pins +PB4.Signal=SYS_JTRST +PB5.GPIOParameters=GPIO_Label +PB5.GPIO_Label=CAN_T_RX +PB5.Locked=true +PB5.Mode=CAN_Activate +PB5.Signal=CAN2_RX +PB6.GPIOParameters=GPIO_Label +PB6.GPIO_Label=CAN_T_TX +PB6.Locked=true +PB6.Mode=CAN_Activate +PB6.Signal=CAN2_TX +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=USER_BUTTON +PB7.Locked=true +PB7.Signal=GPIO_Input +PB8.GPIOParameters=GPIO_Label +PB8.GPIO_Label=CAN_S_RX +PB8.Locked=true +PB8.Mode=CAN_Activate +PB8.Signal=CAN1_RX +PB9.GPIOParameters=GPIO_Label +PB9.GPIO_Label=CAN_S_TX +PB9.Locked=true +PB9.Mode=CAN_Activate +PB9.Signal=CAN1_TX +PC0.GPIOParameters=GPIO_Label +PC0.GPIO_Label=IMU_MODE +PC0.Locked=true +PC0.Signal=GPIO_Output +PC1.GPIOParameters=GPIO_Label +PC1.GPIO_Label=EEPROM_WC +PC1.Locked=true +PC1.Signal=GPIO_Output +PC10.GPIOParameters=GPIO_PuPd +PC10.GPIO_PuPd=GPIO_PULLUP +PC10.Mode=SD_4_bits_Wide_bus +PC10.Signal=SDMMC1_D2 +PC11.GPIOParameters=GPIO_PuPd +PC11.GPIO_PuPd=GPIO_PULLUP +PC11.Mode=SD_4_bits_Wide_bus +PC11.Signal=SDMMC1_D3 +PC12.Mode=SD_4_bits_Wide_bus +PC12.Signal=SDMMC1_CK +PC13.GPIOParameters=GPIO_Label +PC13.GPIO_Label=RS232_FORCEOFF +PC13.Locked=true +PC13.Signal=GPIO_Output +PC14/OSC32_IN.GPIOParameters=GPIO_Label +PC14/OSC32_IN.GPIO_Label=RS232_FORCEON +PC14/OSC32_IN.Locked=true +PC14/OSC32_IN.Signal=GPIO_Output +PC4.GPIOParameters=GPIO_Label +PC4.GPIO_Label=BPS_F_ADC +PC4.Locked=true +PC4.Signal=ADCx_IN14 +PC5.GPIOParameters=GPIO_Label +PC5.GPIO_Label=APPS_2_ADC +PC5.Locked=true +PC5.Signal=ADCx_IN15 +PC6.GPIOParameters=GPIO_Label +PC6.GPIO_Label=TS_ON_BTN +PC6.Locked=true +PC6.Signal=GPIO_Input +PC7.GPIOParameters=GPIO_Label +PC7.GPIO_Label=TS_READY +PC7.Locked=true +PC7.Signal=GPIO_Input +PC8.GPIOParameters=GPIO_PuPd +PC8.GPIO_PuPd=GPIO_PULLUP +PC8.Mode=SD_4_bits_Wide_bus +PC8.Signal=SDMMC1_D0 +PC9.GPIOParameters=GPIO_PuPd +PC9.GPIO_PuPd=GPIO_PULLUP +PC9.Mode=SD_4_bits_Wide_bus +PC9.Signal=SDMMC1_D1 +PCC.Checker=false +PCC.Line=STM32F7x6 +PCC.MCU=STM32F746ZGTx +PCC.PartNumber=STM32F746ZGTx +PCC.Series=STM32F7 +PCC.Temperature=25 +PCC.Vdd=3.3 +PD0.GPIOParameters=GPIO_Label +PD0.GPIO_Label=DEBUG_GPIO_1 +PD0.Locked=true +PD0.Signal=GPIO_Output +PD1.GPIOParameters=GPIO_Label +PD1.GPIO_Label=DEBUG_GPIO_2 +PD1.Locked=true +PD1.Signal=GPIO_Output +PD10.GPIOParameters=GPIO_PuPd,GPIO_Label +PD10.GPIO_Label=WHEELSPEED_FR +PD10.GPIO_PuPd=GPIO_PULLDOWN +PD10.Locked=true +PD10.Signal=GPXTI10 +PD11.GPIOParameters=GPIO_PuPd,GPIO_Label +PD11.GPIO_Label=WHEELSPEED_FL +PD11.GPIO_PuPd=GPIO_PULLDOWN +PD11.Locked=true +PD11.Signal=GPXTI11 +PD12.GPIOParameters=GPIO_Label +PD12.GPIO_Label=SPARE_IN_3 +PD12.Locked=true +PD12.Signal=GPIO_Input +PD13.GPIOParameters=GPIO_Label +PD13.GPIO_Label=GPS_PPS +PD13.Locked=true +PD13.Signal=GPIO_Input +PD14.GPIOParameters=GPIO_Label +PD14.GPIO_Label=SPARE_IN_2 +PD14.Locked=true +PD14.Signal=GPIO_Input +PD15.GPIOParameters=GPIO_Label +PD15.GPIO_Label=SPARE_OUT_3 +PD15.Locked=true +PD15.Signal=GPIO_Output +PD2.Mode=SD_4_bits_Wide_bus +PD2.Signal=SDMMC1_CMD +PD3.GPIOParameters=GPIO_Label +PD3.GPIO_Label=DEBUG_GPIO_3 +PD3.Locked=true +PD3.Signal=GPIO_Output +PD4.GPIOParameters=GPIO_Label +PD4.GPIO_Label=DEBUG_GPIO_4 +PD4.Locked=true +PD4.Signal=GPIO_Output +PD5.GPIOParameters=GPIO_Label +PD5.GPIO_Label=DEBUG_GPIO_5 +PD5.Locked=true +PD5.Signal=GPIO_Output +PD6.GPIOParameters=GPIO_Label +PD6.GPIO_Label=DEBUG_GPIO_6 +PD6.Locked=true +PD6.Signal=GPIO_Output +PD7.GPIOParameters=GPIO_Label +PD7.GPIO_Label=DEBUG_GPIO_7 +PD7.Locked=true +PD7.Signal=GPIO_Output +PD8.GPIOParameters=GPIO_PuPd,GPIO_Label +PD8.GPIO_Label=WHEELSPEED_RR +PD8.GPIO_PuPd=GPIO_PULLDOWN +PD8.Locked=true +PD8.Signal=GPXTI8 +PD9.GPIOParameters=GPIO_PuPd,GPIO_Label +PD9.GPIO_Label=WHEELSPEED_RL +PD9.GPIO_PuPd=GPIO_PULLDOWN +PD9.Locked=true +PD9.Signal=GPXTI9 +PE0.Mode=Asynchronous +PE0.Signal=UART8_RX +PE1.Mode=Asynchronous +PE1.Signal=UART8_TX +PE10.GPIOParameters=GPIO_Label +PE10.GPIO_Label=LED_2 +PE10.Locked=true +PE10.Signal=GPIO_Output +PE11.GPIOParameters=GPIO_Label +PE11.GPIO_Label=TS_ON_LED +PE11.Locked=true +PE11.Signal=GPIO_Output +PE13.GPIOParameters=GPIO_Label +PE13.GPIO_Label=TS_ON +PE13.Locked=true +PE13.Signal=GPIO_Output +PE14.GPIOParameters=GPIO_Label +PE14.GPIO_Label=BRAKELIGHT_EN +PE14.Locked=true +PE14.Signal=GPIO_Output +PE15.GPIOParameters=GPIO_Label +PE15.GPIO_Label=STATUS +PE15.Locked=true +PE15.Signal=GPIO_Output +PE2.GPIOParameters=GPIO_Label +PE2.GPIO_Label=ROB_LED +PE2.Locked=true +PE2.Signal=GPIO_Output +PE3.GPIOParameters=GPIO_PuPd,GPIO_Label +PE3.GPIO_Label=SD_CARD_DETECT +PE3.GPIO_PuPd=GPIO_PULLUP +PE3.Locked=true +PE3.Signal=GPIO_Input +PE6.GPIOParameters=GPIO_Label +PE6.GPIO_Label=RS232_BAD +PE6.Locked=true +PE6.Signal=GPIO_Input +PE7.GPIOParameters=GPIO_Label +PE7.GPIO_Label=VC_LEDS +PE7.Locked=true +PE7.Signal=GPIO_Output +PE8.GPIOParameters=GPIO_Label +PE8.GPIO_Label=LED_4 +PE8.Locked=true +PE8.Signal=GPIO_Output +PE9.GPIOParameters=GPIO_Label +PE9.GPIO_Label=R2D_LED +PE9.Locked=true +PE9.Signal=GPIO_Output +PF0.Mode=I2C +PF0.Signal=I2C2_SDA +PF1.Mode=I2C +PF1.Signal=I2C2_SCL +PF10.GPIOParameters=GPIO_Label +PF10.GPIO_Label=IMU_ADDR +PF10.Locked=true +PF10.Signal=GPIO_Output +PF13.GPIOParameters=GPIO_Label +PF13.GPIO_Label=LS_LED_6 +PF13.Locked=true +PF13.Signal=GPIO_Output +PF14.Mode=I2C +PF14.Signal=I2C4_SCL +PF15.Mode=I2C +PF15.Signal=I2C4_SDA +PF2.GPIOParameters=GPIO_Label +PF2.GPIO_Label=TOO_HOT +PF2.Locked=true +PF2.Signal=GPIO_Input +PF6.GPIOParameters=GPIO_Label +PF6.GPIO_Label=R2D_SIREN +PF6.Locked=true +PF6.Signal=GPIO_Output +PF7.GPIOParameters=GPIO_Label +PF7.GPIO_Label=PWM_SPARE_2 +PF7.Locked=true +PF7.Signal=S_TIM11_CH1 +PG10.GPIOParameters=GPIO_Label +PG10.GPIO_Label=DEBUG_GPIO_9 +PG10.Locked=true +PG10.Signal=GPIO_Output +PG11.GPIOParameters=GPIO_Label +PG11.GPIO_Label=DEBUG_GPIO_10 +PG11.Locked=true +PG11.Signal=GPIO_Output +PG12.Mode=Full_Duplex_Master +PG12.Signal=SPI6_MISO +PG13.Mode=Full_Duplex_Master +PG13.Signal=SPI6_SCK +PG14.Mode=Full_Duplex_Master +PG14.Signal=SPI6_MOSI +PG2.GPIOParameters=GPIO_Label +PG2.GPIO_Label=SPARE_OUT_2 +PG2.Locked=true +PG2.Signal=GPIO_Input +PG3.GPIOParameters=GPIO_Label +PG3.GPIO_Label=SPARE_OUT_1 +PG3.Locked=true +PG3.Signal=GPIO_Input +PG4.GPIOParameters=GPIO_Label +PG4.GPIO_Label=APPS_PWR_GOOD +PG4.Locked=true +PG4.Signal=GPIO_Input +PG5.GPIOParameters=GPIO_Label +PG5.GPIO_Label=SPARE_IN_1 +PG5.Locked=true +PG5.Signal=GPIO_Input +PG6.GPIOParameters=GPIO_Label +PG6.GPIO_Label=SW_BTN_2 +PG6.Locked=true +PG6.Signal=GPIO_Input +PG7.GPIOParameters=GPIO_Label +PG7.GPIO_Label=SW_BTN_1 +PG7.Locked=true +PG7.Signal=GPIO_Input +PG8.GPIOParameters=GPIO_Label +PG8.GPIO_Label=R2D_BTN +PG8.Locked=true +PG8.Signal=GPIO_Input +PG9.GPIOParameters=GPIO_Label +PG9.GPIO_Label=DEBUG_GPIO_8 +PG9.Locked=true +PG9.Signal=GPIO_Output +PH0/OSC_IN.Mode=HSE-External-Oscillator +PH0/OSC_IN.Signal=RCC_OSC_IN +PH1/OSC_OUT.Mode=HSE-External-Oscillator +PH1/OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerLinker=GCC +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F746ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.4 +ProjectManager.FreePins=false +ProjectManager.FreePinsContext= +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=1 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=VCU.ioc +ProjectManager.ProjectName=VCU +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_DMA_Init-DMA-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_CAN2_Init-CAN2-false-HAL-true,7-MX_I2C2_Init-I2C2-false-HAL-true,8-MX_I2C4_Init-I2C4-false-HAL-true,9-MX_SPI6_Init-SPI6-false-HAL-true,10-MX_TIM2_Init-TIM2-false-HAL-true,11-MX_TIM12_Init-TIM12-false-HAL-true,12-MX_UART8_Init-UART8-false-HAL-true,13-MX_USART1_Init-USART1-false-HAL-true,14-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-true-HAL-true,15-MX_TIM10_Init-TIM10-false-HAL-true,16-MX_TIM11_Init-TIM11-false-HAL-true,17-MX_ADC2_Init-ADC2-false-HAL-true,18-MX_TIM3_Init-TIM3-false-HAL-true,19-MX_SDMMC1_SD_Init-SDMMC1-true-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.AHBFreq_Value=216000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV4 +RCC.APB1Freq_Value=54000000 +RCC.APB1TimFreq_Value=108000000 +RCC.APB2CLKDivider=RCC_HCLK_DIV2 +RCC.APB2Freq_Value=108000000 +RCC.APB2TimFreq_Value=216000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=216000000 +RCC.EthernetFreq_Value=216000000 +RCC.FCLKCortexFreq_Value=216000000 +RCC.FamilyName=M +RCC.HCLKFreq_Value=216000000 +RCC.HSE_VALUE=25000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=54000000 +RCC.I2C2Freq_Value=54000000 +RCC.I2C3Freq_Value=54000000 +RCC.I2C4Freq_Value=54000000 +RCC.I2SFreq_Value=96000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2CLKDivider,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCClockSelection,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFToutputFreq_Value=48000000 +RCC.LPTIM1Freq_Value=54000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=216000000 +RCC.PLLCLKFreq_Value=216000000 +RCC.PLLI2SPCLKFreq_Value=96000000 +RCC.PLLI2SQCLKFreq_Value=96000000 +RCC.PLLI2SRCLKFreq_Value=96000000 +RCC.PLLI2SRoutputFreq_Value=96000000 +RCC.PLLM=25 +RCC.PLLN=432 +RCC.PLLQ=9 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLQoutputFreq_Value=48000000 +RCC.PLLSAIPCLKFreq_Value=96000000 +RCC.PLLSAIQCLKFreq_Value=96000000 +RCC.PLLSAIRCLKFreq_Value=96000000 +RCC.PLLSAIoutputFreq_Value=96000000 +RCC.RNGFreq_Value=48000000 +RCC.SAI1Freq_Value=96000000 +RCC.SAI2Freq_Value=96000000 +RCC.SDMMCClockSelection=RCC_SDMMC1CLKSOURCE_CLK48 +RCC.SDMMCFreq_Value=48000000 +RCC.SPDIFRXFreq_Value=96000000 +RCC.SYSCLKFreq_VALUE=216000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=54000000 +RCC.UART5Freq_Value=54000000 +RCC.UART7Freq_Value=54000000 +RCC.UART8Freq_Value=54000000 +RCC.USART1Freq_Value=108000000 +RCC.USART2Freq_Value=54000000 +RCC.USART3Freq_Value=54000000 +RCC.USART6Freq_Value=108000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SOutputFreq_Value=192000000 +RCC.VCOInputFreq_Value=1000000 +RCC.VCOOutputFreq_Value=432000000 +RCC.VCOSAIOutputFreq_Value=192000000 +SDMMC1.ClockPowerSave=SDMMC_CLOCK_POWER_SAVE_ENABLE +SDMMC1.IPParameters=ClockPowerSave +SH.ADCx_IN14.0=ADC1_IN14,IN14 +SH.ADCx_IN14.ConfNb=1 +SH.ADCx_IN15.0=ADC2_IN15,IN15 +SH.ADCx_IN15.ConfNb=1 +SH.ADCx_IN3.0=ADC2_IN3,IN3 +SH.ADCx_IN3.ConfNb=1 +SH.ADCx_IN4.0=ADC1_IN4,IN4 +SH.ADCx_IN4.ConfNb=1 +SH.ADCx_IN5.0=ADC1_IN5,IN5 +SH.ADCx_IN5.ConfNb=1 +SH.ADCx_IN6.0=ADC1_IN6,IN6 +SH.ADCx_IN6.ConfNb=1 +SH.ADCx_IN7.0=ADC1_IN7,IN7 +SH.ADCx_IN7.ConfNb=1 +SH.ADCx_IN8.0=ADC1_IN8,IN8 +SH.ADCx_IN8.ConfNb=1 +SH.GPXTI10.0=GPIO_EXTI10 +SH.GPXTI10.ConfNb=1 +SH.GPXTI11.0=GPIO_EXTI11 +SH.GPXTI11.ConfNb=1 +SH.GPXTI8.0=GPIO_EXTI8 +SH.GPXTI8.ConfNb=1 +SH.GPXTI9.0=GPIO_EXTI9 +SH.GPXTI9.ConfNb=1 +SH.S_TIM11_CH1.0=TIM11_CH1,PWM Generation1 CH1 +SH.S_TIM11_CH1.ConfNb=1 +SH.S_TIM12_CH2.0=TIM12_CH2,Output Compare2 CH2 +SH.S_TIM12_CH2.ConfNb=1 +SH.S_TIM2_CH4.0=TIM2_CH4,PWM Generation4 CH4 +SH.S_TIM2_CH4.ConfNb=1 +SH.S_TIM3_CH4.0=TIM3_CH4,PWM Generation4 CH4 +SH.S_TIM3_CH4.ConfNb=1 +SPI6.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_2 +SPI6.CalculateBaudRate=54.0 MBits/s +SPI6.Direction=SPI_DIRECTION_2LINES +SPI6.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler +SPI6.Mode=SPI_MODE_MASTER +SPI6.VirtualType=VM_MASTER +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ENABLE_CACHE_MAINTENANCE=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.FX_APP_MEM_POOL_SIZE=2048 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.FX_DISABLE_CACHE=1 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.FileOoSystemJjFileX_Checked=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.FileOoSystemJjInterfaces_Checked=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.FileXCcFileOoSystemJjFileXJjCore=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.IPParameters=TX_SAFETY_CRITICAL,TX_TIMER_TICKS_PER_SECOND,TX_DISABLE_PREEMPTION_THRESHOLD,TX_DISABLE_NOTIFY_CALLBACKS,TX_APP_MEM_POOL_SIZE,FX_APP_MEM_POOL_SIZE,UX_DEVICE_APP_MEM_POOL_SIZE,UX_OTG_SUPPORT,UX_HOST_SIDE_ONLY,UX_THREAD_STACK_SIZE,FX_DISABLE_CACHE,ENABLE_CACHE_MAINTENANCE,UX_MAX_HCD,ThreadXCcRTOSJjThreadXJjCore,ThreadXCcRTOSJjThreadXJjPerformanceInfo,ThreadXCcRTOSJjThreadXJjTraceXOosupport,ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport,FileXCcFileOoSystemJjFileXJjCore,InterfacesCcFileOoSystemJjFileXOoSDOointerface,USBXCcUSBJjUSBXJjCoreSystem,USBXCcUSBJjUSBXJjUXOoHostOoCoreStack,USBXCcUSBJjUSBXJjUXOoHostOoControllers,USBXCcUSBJjUSBXJjUXOoDeviceOoCoreStack,USBXCcUSBJjUSBXJjUXOoDeviceOoControllers,USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoSTORAGE +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.InterfacesCcFileOoSystemJjFileXOoSDOointerface=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.RTOSJjThreadX_Checked=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_APP_MEM_POOL_SIZE=131072 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_DISABLE_NOTIFY_CALLBACKS=0 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_DISABLE_PREEMPTION_THRESHOLD=0 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_SAFETY_CRITICAL=1 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_TIMER_TICKS_PER_SECOND=1000 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjCore=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjPerformanceInfo=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjTraceXOosupport=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.USBJjUSBX_Checked=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.USBXCcUSBJjUSBXJjCoreSystem=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoSTORAGE=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.USBXCcUSBJjUSBXJjUXOoDeviceOoControllers=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.USBXCcUSBJjUSBXJjUXOoDeviceOoCoreStack=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.USBXCcUSBJjUSBXJjUXOoHostOoControllers=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.USBXCcUSBJjUSBXJjUXOoHostOoCoreStack=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.UX_DEVICE_APP_MEM_POOL_SIZE=8192 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.UX_HOST_SIDE_ONLY=0 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.UX_MAX_HCD=2 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.UX_OTG_SUPPORT=1 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.UX_THREAD_STACK_SIZE=4096 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0_IsAnAzureRtosMw=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0_SwParameter=InterfacesCcFileOoSystemJjFileXOoSDOointerface\:true;ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport\:true;USBXCcUSBJjUSBXJjUXOoDeviceOoControllers\:true;USBXCcUSBJjUSBXJjCoreSystem\:true;ThreadXCcRTOSJjThreadXJjPerformanceInfo\:true;ThreadXCcRTOSJjThreadXJjTraceXOosupport\:true;FileXCcFileOoSystemJjFileXJjCore\:true;ThreadXCcRTOSJjThreadXJjCore\:true;USBXCcUSBJjUSBXJjUXOoDeviceOoCoreStack\:true;USBXCcUSBJjUSBXJjUXOoHostOoControllers\:true;USBXCcUSBJjUSBXJjUXOoHostOoCoreStack\:true;USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoSTORAGE\:true; +TIM11.Channel=TIM_CHANNEL_1 +TIM11.IPParameters=Channel +TIM12.Channel-Output\ Compare2\ CH2=TIM_CHANNEL_2 +TIM12.IPParameters=Channel-Output Compare2 CH2 +TIM2.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM2.IPParameters=Channel-PWM Generation4 CH4 +TIM3.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4 +TIM3.IPParameters=Channel-PWM Generation4 CH4 +UART8.IPParameters=SwapParam +UART8.SwapParam=UART_ADVFEATURE_SWAP_ENABLE +USART1.IPParameters=VirtualMode-Synchronous +USART1.VirtualMode-Synchronous=VM_SYNC +USB_OTG_FS.IPParameters=VirtualMode +USB_OTG_FS.VirtualMode=Device_Only +VP_ADC1_Vref_Input.Mode=IN-Vrefint +VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_FileOoSystemJjFileX_6.1.10_1.1.0.Mode=FileOoSystemJjFileX +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_FileOoSystemJjFileX_6.1.10_1.1.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-F7_VS_FileOoSystemJjFileX_6.1.10_1.1.0 +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_FileOoSystemJjInterfaces_2.1.0_1.1.0.Mode=FileOoSystemJjInterfaces +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_FileOoSystemJjInterfaces_2.1.0_1.1.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-F7_VS_FileOoSystemJjInterfaces_2.1.0_1.1.0 +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0.Mode=RTOSJjThreadX +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0 +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_USBJjUSBX_6.1.10_1.1.0.Mode=USBJjUSBX +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_USBJjUSBX_6.1.10_1.1.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-F7_VS_USBJjUSBX_6.1.10_1.1.0 +VP_SYS_VS_tim6.Mode=TIM6 +VP_SYS_VS_tim6.Signal=SYS_VS_tim6 +VP_TIM10_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM10_VS_ClockSourceINT.Signal=TIM10_VS_ClockSourceINT +VP_TIM11_VS_ClockSourceINT.Mode=Enable_Timer +VP_TIM11_VS_ClockSourceINT.Signal=TIM11_VS_ClockSourceINT +board=custom diff --git a/src/VCU_Old.ioc b/src/VCU_Old.ioc new file mode 100644 index 00000000..8c78e09b --- /dev/null +++ b/src/VCU_Old.ioc @@ -0,0 +1,454 @@ +#MicroXplorer Configuration settings - do not modify +ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3 +ADC1.Channel-IN3=ADC_CHANNEL_3 +ADC1.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2 +ADC1.ContinuousConvMode=DISABLE +ADC1.DMAContinuousRequests=DISABLE +ADC1.DataAlign=ADC_DATAALIGN_RIGHT +ADC1.DiscontinuousConvMode=DISABLE +ADC1.EOCSelection=ADC_EOC_SINGLE_CONV +ADC1.EnableAnalogWatchDog=false +ADC1.ExternalTrigConv=ADC_SOFTWARE_START +ADC1.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE +ADC1.IPParameters=Channel-IN3,Mode,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,master +ADC1.InjNumberOfConversion=0 +ADC1.Mode=__NULL +ADC1.NbrOfConversion=1 +ADC1.Rank-0\#ChannelRegularConversion=1 +ADC1.Resolution=ADC_RESOLUTION_12B +ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC1.ScanConvMode=ADC_SCAN_DISABLE +ADC1.master=1 +ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_13 +ADC2.Channel-IN13=ADC_CHANNEL_13 +ADC2.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2 +ADC2.ContinuousConvMode=DISABLE +ADC2.DMAContinuousRequests=DISABLE +ADC2.DataAlign=ADC_DATAALIGN_RIGHT +ADC2.DiscontinuousConvMode=DISABLE +ADC2.EOCSelection=ADC_EOC_SINGLE_CONV +ADC2.EnableAnalogWatchDog=false +ADC2.ExternalTrigConv=ADC_SOFTWARE_START +ADC2.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE +ADC2.IPParameters=Channel-IN13,Mode,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion +ADC2.InjNumberOfConversion=0 +ADC2.Mode=__NULL +ADC2.NbrOfConversion=1 +ADC2.Rank-0\#ChannelRegularConversion=1 +ADC2.Resolution=ADC_RESOLUTION_12B +ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC2.ScanConvMode=ADC_SCAN_DISABLE +ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_10 +ADC3.Channel-IN10=ADC_CHANNEL_10 +ADC3.ClockPrescaler=ADC_CLOCK_SYNC_PCLK_DIV2 +ADC3.ContinuousConvMode=DISABLE +ADC3.DMAContinuousRequests=DISABLE +ADC3.DataAlign=ADC_DATAALIGN_RIGHT +ADC3.DiscontinuousConvMode=DISABLE +ADC3.EOCSelection=ADC_EOC_SINGLE_CONV +ADC3.EnableAnalogWatchDog=false +ADC3.ExternalTrigConv=ADC_SOFTWARE_START +ADC3.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_NONE +ADC3.IPParameters=Channel-IN10,ClockPrescaler,Resolution,DataAlign,ScanConvMode,ContinuousConvMode,DiscontinuousConvMode,DMAContinuousRequests,EOCSelection,NbrOfConversion,ExternalTrigConv,ExternalTrigConvEdge,InjNumberOfConversion,EnableAnalogWatchDog,Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion +ADC3.InjNumberOfConversion=0 +ADC3.NbrOfConversion=1 +ADC3.Rank-0\#ChannelRegularConversion=1 +ADC3.Resolution=ADC_RESOLUTION_12B +ADC3.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC3.ScanConvMode=ADC_SCAN_DISABLE +CAD.formats=[] +CAD.pinconfig=Dual +CAD.provider= +CAN1.ABOM=ENABLE +CAN1.AWUM=DISABLE +CAN1.BS1=CAN_BS1_2TQ +CAN1.BS2=CAN_BS2_1TQ +CAN1.CalculateBaudRate=500000 +CAN1.CalculateTimeBit=2000 +CAN1.CalculateTimeQuantum=500.0 +CAN1.IPParameters=Prescaler,BS1,BS2,SJW,TTCM,ABOM,AWUM,NART,RFLM,TXFP,Mode,CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate +CAN1.Mode=CAN_MODE_NORMAL +CAN1.NART=DISABLE +CAN1.Prescaler=18 +CAN1.RFLM=DISABLE +CAN1.SJW=CAN_SJW_1TQ +CAN1.TTCM=DISABLE +CAN1.TXFP=DISABLE +CAN2.ABOM=ENABLE +CAN2.AWUM=DISABLE +CAN2.BS1=CAN_BS1_2TQ +CAN2.BS2=CAN_BS2_1TQ +CAN2.CalculateBaudRate=500000 +CAN2.CalculateTimeBit=2000 +CAN2.CalculateTimeQuantum=500.0 +CAN2.IPParameters=Prescaler,BS1,BS2,SJW,TTCM,ABOM,AWUM,NART,RFLM,TXFP,Mode,CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate +CAN2.Mode=CAN_MODE_NORMAL +CAN2.NART=DISABLE +CAN2.Prescaler=18 +CAN2.RFLM=DISABLE +CAN2.SJW=CAN_SJW_1TQ +CAN2.TTCM=DISABLE +CAN2.TXFP=DISABLE +CORTEX_M7.ART_ACCELERATOR_ENABLE=0 +CORTEX_M7.CPU_DCache=Disabled +CORTEX_M7.CPU_ICache=Disabled +CORTEX_M7.FlashInterface=AXI_Enabled +CORTEX_M7.IPParameters=default_mode_Activation,FlashInterface,ART_ACCELERATOR_ENABLE,PREFETCH_ENABLE,CPU_ICache,CPU_DCache,MPU_Control +CORTEX_M7.MPU_Control=__NULL +CORTEX_M7.PREFETCH_ENABLE=0 +CORTEX_M7.default_mode_Activation=0 +File.Version=6 +GPIO.groupedBy=Group By Peripherals +KeepUserPlacement=false +Mcu.CPN=STM32F746ZGT6 +Mcu.Family=STM32F7 +Mcu.IP0=ADC1 +Mcu.IP1=ADC2 +Mcu.IP2=ADC3 +Mcu.IP3=CAN1 +Mcu.IP4=CAN2 +Mcu.IP5=CORTEX_M7 +Mcu.IP6=NVIC +Mcu.IP7=RCC +Mcu.IP8=SYS +Mcu.IP9=USART1 +Mcu.IPNb=10 +Mcu.Name=STM32F746ZGTx +Mcu.Package=LQFP144 +Mcu.Pin0=PE3 +Mcu.Pin1=PE4 +Mcu.Pin10=PF5 +Mcu.Pin11=PF10 +Mcu.Pin12=PH0/OSC_IN +Mcu.Pin13=PH1/OSC_OUT +Mcu.Pin14=PC0 +Mcu.Pin15=PC3 +Mcu.Pin16=PA0/WKUP +Mcu.Pin17=PA3 +Mcu.Pin18=PB0 +Mcu.Pin19=PF14 +Mcu.Pin2=PE5 +Mcu.Pin20=PF15 +Mcu.Pin21=PE9 +Mcu.Pin22=PE11 +Mcu.Pin23=PB12 +Mcu.Pin24=PB14 +Mcu.Pin25=PA9 +Mcu.Pin26=PA10 +Mcu.Pin27=PA13 +Mcu.Pin28=PA14 +Mcu.Pin29=PA15 +Mcu.Pin3=PE6 +Mcu.Pin30=PD0 +Mcu.Pin31=PD1 +Mcu.Pin32=PB3 +Mcu.Pin33=PB4 +Mcu.Pin34=PB6 +Mcu.Pin35=PB7 +Mcu.Pin36=PB8 +Mcu.Pin37=PB9 +Mcu.Pin38=VP_SYS_VS_tim3 +Mcu.Pin39=VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0 +Mcu.Pin4=PC13 +Mcu.Pin5=PC14/OSC32_IN +Mcu.Pin6=PC15/OSC32_OUT +Mcu.Pin7=PF1 +Mcu.Pin8=PF2 +Mcu.Pin9=PF3 +Mcu.PinsNb=40 +Mcu.ThirdParty0=STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0 +Mcu.ThirdPartyNb=1 +Mcu.UserConstants= +Mcu.UserName=STM32F746ZGTx +MxCube.Version=6.9.2 +MxDb.Version=DB.6.0.92 +NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.CAN1_RX0_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.CAN1_RX1_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.CAN1_TX_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.CAN2_RX0_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.CAN2_RX1_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.CAN2_TX_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.EXTI15_10_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.ForceEnableDMAVector=true +NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false +NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 +NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false +NVIC.SavedPendsvIrqHandlerGenerated=false +NVIC.SavedSvcallIrqHandlerGenerated=false +NVIC.SavedSystickIrqHandlerGenerated=false +NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:true\:false +NVIC.TIM3_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true +NVIC.TimeBase=TIM3_IRQn +NVIC.TimeBaseIP=TIM3 +NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false +PA0/WKUP.GPIOParameters=GPIO_Label +PA0/WKUP.GPIO_Label=DRS +PA0/WKUP.Locked=true +PA0/WKUP.Signal=GPIO_Output +PA10.Locked=true +PA10.Mode=Asynchronous +PA10.Signal=USART1_RX +PA13.GPIOParameters=GPIO_Label +PA13.GPIO_Label=TMS +PA13.Locked=true +PA13.Mode=JTAG_5_pins +PA13.Signal=SYS_JTMS-SWDIO +PA14.GPIOParameters=GPIO_Label +PA14.GPIO_Label=TCK +PA14.Locked=true +PA14.Mode=JTAG_5_pins +PA14.Signal=SYS_JTCK-SWCLK +PA15.Locked=true +PA15.Mode=JTAG_5_pins +PA15.Signal=SYS_JTDI +PA3.GPIOParameters=GPIO_Label +PA3.GPIO_Label=APPS_1_ADC +PA3.Locked=true +PA3.Signal=ADCx_IN3 +PA9.Locked=true +PA9.Mode=Asynchronous +PA9.Signal=USART1_TX +PB0.GPIOParameters=GPIO_Label +PB0.GPIO_Label=GREEN_LED +PB0.Locked=true +PB0.Signal=GPIO_Output +PB12.GPIOParameters=GPIO_PuPd +PB12.GPIO_PuPd=GPIO_PULLUP +PB12.Mode=CAN_Activate +PB12.Signal=CAN2_RX +PB14.GPIOParameters=GPIO_Label +PB14.GPIO_Label=RED_LED +PB14.Locked=true +PB14.Signal=GPIO_Output +PB3.Locked=true +PB3.Mode=JTAG_5_pins +PB3.Signal=SYS_JTDO-SWO +PB4.Locked=true +PB4.Mode=JTAG_5_pins +PB4.Signal=SYS_JTRST +PB6.GPIOParameters=GPIO_PuPd +PB6.GPIO_PuPd=GPIO_PULLUP +PB6.Mode=CAN_Activate +PB6.Signal=CAN2_TX +PB7.GPIOParameters=GPIO_Label +PB7.GPIO_Label=BLUE_LED +PB7.Locked=true +PB7.Signal=GPIO_Output +PB8.Locked=true +PB8.Signal=I2C1_SCL +PB9.Locked=true +PB9.Signal=I2C1_SDA +PC0.GPIOParameters=GPIO_Label +PC0.GPIO_Label=BPS_ADC +PC0.Locked=true +PC0.Signal=ADCx_IN10 +PC13.GPIOParameters=GPIO_Label +PC13.GPIO_Label=USER_BUTTON +PC13.Locked=true +PC13.Signal=GPXTI13 +PC14/OSC32_IN.Locked=true +PC14/OSC32_IN.Signal=RCC_OSC32_IN +PC15/OSC32_OUT.Locked=true +PC15/OSC32_OUT.Signal=RCC_OSC32_OUT +PC3.GPIOParameters=GPIO_Label +PC3.GPIO_Label=APPS_2_ADC +PC3.Locked=true +PC3.Signal=ADCx_IN13 +PD0.GPIOParameters=GPIO_PuPd +PD0.GPIO_PuPd=GPIO_PULLUP +PD0.Mode=CAN_Activate +PD0.Signal=CAN1_RX +PD1.GPIOParameters=GPIO_PuPd +PD1.GPIO_PuPd=GPIO_PULLUP +PD1.Mode=CAN_Activate +PD1.Signal=CAN1_TX +PE11.GPIOParameters=GPIO_Label +PE11.GPIO_Label=BRAKE_PRESSED +PE11.Locked=true +PE11.Signal=GPIO_Output +PE3.GPIOParameters=GPIO_Label +PE3.GPIO_Label=VC_LEDS +PE3.Locked=true +PE3.Signal=GPIO_Output +PE4.GPIOParameters=GPIO_Label +PE4.GPIO_Label=DRS_LED +PE4.Locked=true +PE4.Signal=GPIO_Output +PE5.GPIOParameters=GPIO_Label +PE5.GPIO_Label=TS_ON_LED +PE5.Locked=true +PE5.Signal=GPIO_Output +PE6.GPIOParameters=GPIO_Label +PE6.GPIO_Label=R2D_LED +PE6.Locked=true +PE6.Signal=GPIO_Output +PE9.GPIOParameters=GPIO_Label +PE9.GPIO_Label=STATUS +PE9.Locked=true +PE9.Signal=GPIO_Output +PF1.GPIOParameters=GPIO_PuPd,GPIO_Label +PF1.GPIO_Label=TS_READY +PF1.GPIO_PuPd=GPIO_PULLDOWN +PF1.Locked=true +PF1.Signal=GPIO_Input +PF10.GPIOParameters=GPIO_PuPd,GPIO_Label +PF10.GPIO_Label=DRS_BTN +PF10.GPIO_PuPd=GPIO_PULLDOWN +PF10.Locked=true +PF10.Signal=GPIO_Input +PF14.GPIOParameters=GPIO_Label +PF14.GPIO_Label=TS_ON +PF14.Locked=true +PF14.Signal=GPIO_Output +PF15.GPIOParameters=GPIO_Label +PF15.GPIO_Label=R2D_SIREN +PF15.Locked=true +PF15.Signal=GPIO_Output +PF2.GPIOParameters=GPIO_PuPd,GPIO_Label +PF2.GPIO_Label=R2D_BTN +PF2.GPIO_PuPd=GPIO_PULLDOWN +PF2.Locked=true +PF2.Signal=GPIO_Input +PF3.GPIOParameters=GPIO_Label +PF3.GPIO_Label=SAGL +PF3.Locked=true +PF3.Signal=GPIO_Input +PF5.GPIOParameters=GPIO_PuPd,GPIO_Label +PF5.GPIO_Label=TS_ON_BTN +PF5.GPIO_PuPd=GPIO_PULLDOWN +PF5.Locked=true +PF5.Signal=GPIO_Input +PH0/OSC_IN.GPIOParameters=GPIO_Label +PH0/OSC_IN.GPIO_Label=MCO [STM32F103CBT6_PA8] +PH0/OSC_IN.Locked=true +PH0/OSC_IN.Mode=HSE-External-Oscillator +PH0/OSC_IN.Signal=RCC_OSC_IN +PH1/OSC_OUT.Locked=true +PH1/OSC_OUT.Mode=HSE-External-Oscillator +PH1/OSC_OUT.Signal=RCC_OSC_OUT +PinOutPanel.RotationAngle=0 +ProjectManager.AskForMigrate=true +ProjectManager.BackupPrevious=false +ProjectManager.CompilerOptimize=6 +ProjectManager.ComputerToolchain=false +ProjectManager.CoupleFile=true +ProjectManager.CustomerFirmwarePackage= +ProjectManager.DefaultFWLocation=true +ProjectManager.DeletePrevious=true +ProjectManager.DeviceId=STM32F746ZGTx +ProjectManager.FirmwarePackage=STM32Cube FW_F7 V1.17.2 +ProjectManager.FreePins=false +ProjectManager.HalAssertFull=false +ProjectManager.HeapSize=0x200 +ProjectManager.KeepUserCode=true +ProjectManager.LastFirmware=true +ProjectManager.LibraryCopy=0 +ProjectManager.MainLocation=Core/Src +ProjectManager.NoMain=false +ProjectManager.PreviousToolchain= +ProjectManager.ProjectBuild=false +ProjectManager.ProjectFileName=VCU.ioc +ProjectManager.ProjectName=VCU +ProjectManager.ProjectStructure= +ProjectManager.RegisterCallBack= +ProjectManager.StackSize=0x400 +ProjectManager.TargetToolchain=Makefile +ProjectManager.ToolChainLocation= +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= +ProjectManager.UnderRoot=false +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC3_Init-ADC3-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_ADC2_Init-ADC2-false-HAL-true,6-MX_CAN1_Init-CAN1-false-HAL-true,7-MX_CAN2_Init-CAN2-false-HAL-true,8-MX_USART1_UART_Init-USART1-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +RCC.AHBFreq_Value=72000000 +RCC.APB1CLKDivider=RCC_HCLK_DIV2 +RCC.APB1Freq_Value=36000000 +RCC.APB1TimFreq_Value=72000000 +RCC.APB2Freq_Value=72000000 +RCC.APB2TimFreq_Value=72000000 +RCC.CECFreq_Value=32786.88524590164 +RCC.CortexFreq_Value=72000000 +RCC.EthernetFreq_Value=72000000 +RCC.FCLKCortexFreq_Value=72000000 +RCC.FLatency=FLASH_LATENCY_2 +RCC.FamilyName=M +RCC.HCLKFreq_Value=72000000 +RCC.HSE_VALUE=8000000 +RCC.HSI_VALUE=16000000 +RCC.I2C1Freq_Value=36000000 +RCC.I2C2Freq_Value=36000000 +RCC.I2C3Freq_Value=36000000 +RCC.I2C4Freq_Value=36000000 +RCC.I2SFreq_Value=192000000 +RCC.IPParameters=AHBFreq_Value,APB1CLKDivider,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CECFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FLatency,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LCDTFToutputFreq_Value,LPTIM1Freq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLI2SPCLKFreq_Value,PLLI2SQCLKFreq_Value,PLLI2SRCLKFreq_Value,PLLI2SRoutputFreq_Value,PLLM,PLLN,PLLQ,PLLQCLKFreq_Value,PLLQoutputFreq_Value,PLLSAIPCLKFreq_Value,PLLSAIQCLKFreq_Value,PLLSAIRCLKFreq_Value,PLLSAIoutputFreq_Value,PLLSourceVirtual,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOSAIOutputFreq_Value +RCC.LCDTFToutputFreq_Value=96000000 +RCC.LPTIM1Freq_Value=36000000 +RCC.LSE_VALUE=32768 +RCC.LSI_VALUE=32000 +RCC.MCO2PinFreq_Value=72000000 +RCC.PLLCLKFreq_Value=72000000 +RCC.PLLI2SPCLKFreq_Value=192000000 +RCC.PLLI2SQCLKFreq_Value=192000000 +RCC.PLLI2SRCLKFreq_Value=192000000 +RCC.PLLI2SRoutputFreq_Value=192000000 +RCC.PLLM=4 +RCC.PLLN=72 +RCC.PLLQ=3 +RCC.PLLQCLKFreq_Value=48000000 +RCC.PLLQoutputFreq_Value=48000000 +RCC.PLLSAIPCLKFreq_Value=192000000 +RCC.PLLSAIQCLKFreq_Value=192000000 +RCC.PLLSAIRCLKFreq_Value=192000000 +RCC.PLLSAIoutputFreq_Value=192000000 +RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE +RCC.RNGFreq_Value=48000000 +RCC.SAI1Freq_Value=192000000 +RCC.SAI2Freq_Value=192000000 +RCC.SDMMCFreq_Value=72000000 +RCC.SPDIFRXFreq_Value=192000000 +RCC.SYSCLKFreq_VALUE=72000000 +RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK +RCC.UART4Freq_Value=36000000 +RCC.UART5Freq_Value=36000000 +RCC.UART7Freq_Value=36000000 +RCC.UART8Freq_Value=36000000 +RCC.USART1Freq_Value=72000000 +RCC.USART2Freq_Value=36000000 +RCC.USART3Freq_Value=36000000 +RCC.USART6Freq_Value=72000000 +RCC.USBFreq_Value=48000000 +RCC.VCOI2SOutputFreq_Value=384000000 +RCC.VCOInputFreq_Value=2000000 +RCC.VCOOutputFreq_Value=144000000 +RCC.VCOSAIOutputFreq_Value=384000000 +SH.ADCx_IN10.0=ADC3_IN10,IN10 +SH.ADCx_IN10.ConfNb=1 +SH.ADCx_IN13.0=ADC2_IN13,IN13 +SH.ADCx_IN13.ConfNb=1 +SH.ADCx_IN3.0=ADC1_IN3,IN3 +SH.ADCx_IN3.ConfNb=1 +SH.GPXTI13.0=GPIO_EXTI13 +SH.GPXTI13.ConfNb=1 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.IPParameters=TX_APP_MEM_POOL_SIZE,TX_DISABLE_PREEMPTION_THRESHOLD,TX_DISABLE_NOTIFY_CALLBACKS,TX_TIMER_TICKS_PER_SECOND,TX_SAFETY_CRITICAL,ThreadXCcRTOSJjThreadXJjCore,ThreadXCcRTOSJjThreadXJjPerformanceInfo,ThreadXCcRTOSJjThreadXJjTraceXOosupport,ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.RTOSJjThreadX_Checked=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_APP_MEM_POOL_SIZE=16384 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_DISABLE_NOTIFY_CALLBACKS=0 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_DISABLE_PREEMPTION_THRESHOLD=0 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_SAFETY_CRITICAL=1 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.TX_TIMER_TICKS_PER_SECOND=1000 +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjCore=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjPerformanceInfo=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0.ThreadXCcRTOSJjThreadXJjTraceXOosupport=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0_IsAnAzureRtosMw=true +STMicroelectronics.X-CUBE-AZRTOS-F7.1.1.0_SwParameter=ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport\:true;ThreadXCcRTOSJjThreadXJjPerformanceInfo\:true;ThreadXCcRTOSJjThreadXJjTraceXOosupport\:true;ThreadXCcRTOSJjThreadXJjCore\:true; +USART1.IPParameters=VirtualMode-Asynchronous +USART1.VirtualMode-Asynchronous=VM_ASYNC +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0.Mode=RTOSJjThreadX +VP_STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-F7_VS_RTOSJjThreadX_6.1.10_1.1.0 +VP_SYS_VS_tim3.Mode=TIM3 +VP_SYS_VS_tim3.Signal=SYS_VS_tim3 +board=NUCLEO-F746ZG diff --git a/src/startup_stm32f746xx.s b/src/startup_stm32f746xx.s index 253f8e54..a94085c7 100644 --- a/src/startup_stm32f746xx.s +++ b/src/startup_stm32f746xx.s @@ -1,571 +1,572 @@ -/** - ****************************************************************************** - * @file startup_stm32f746xx.s - * @author MCD Application Team - * @brief STM32F746xx Devices vector table for GCC based toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M7 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m7 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - bl __libc_init_array -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M7. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDMMC1_IRQHandler /* SDMMC1 */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* Rng */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ - .word SAI2_IRQHandler /* SAI2 */ - .word QUADSPI_IRQHandler /* QUADSPI */ - .word LPTIM1_IRQHandler /* LPTIM1 */ - .word CEC_IRQHandler /* HDMI_CEC */ - .word I2C4_EV_IRQHandler /* I2C4 Event */ - .word I2C4_ER_IRQHandler /* I2C4 Error */ - .word SPDIF_RX_IRQHandler /* SPDIF_RX */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDMMC1_IRQHandler - .thumb_set SDMMC1_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak LTDC_IRQHandler - .thumb_set LTDC_IRQHandler,Default_Handler - - .weak LTDC_ER_IRQHandler - .thumb_set LTDC_ER_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - - .weak SAI2_IRQHandler - .thumb_set SAI2_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler - - .weak CEC_IRQHandler - .thumb_set CEC_IRQHandler,Default_Handler - - .weak I2C4_EV_IRQHandler - .thumb_set I2C4_EV_IRQHandler,Default_Handler - - .weak I2C4_ER_IRQHandler - .thumb_set I2C4_ER_IRQHandler,Default_Handler - - .weak SPDIF_RX_IRQHandler - .thumb_set SPDIF_RX_IRQHandler,Default_Handler - - +/** + ****************************************************************************** + * @file startup_stm32f746xx.s + * @author MCD Application Team + * @brief STM32F746xx Devices vector table for GCC based toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M7 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m7 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Call the clock system initialization function.*/ + bl SystemInit + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M7. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDMMC1_IRQHandler /* SDMMC1 */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word SAI2_IRQHandler /* SAI2 */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word LPTIM1_IRQHandler /* LPTIM1 */ + .word CEC_IRQHandler /* HDMI_CEC */ + .word I2C4_EV_IRQHandler /* I2C4 Event */ + .word I2C4_ER_IRQHandler /* I2C4 Error */ + .word SPDIF_RX_IRQHandler /* SPDIF_RX */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDMMC1_IRQHandler + .thumb_set SDMMC1_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak SAI2_IRQHandler + .thumb_set SAI2_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler + + .weak CEC_IRQHandler + .thumb_set CEC_IRQHandler,Default_Handler + + .weak I2C4_EV_IRQHandler + .thumb_set I2C4_EV_IRQHandler,Default_Handler + + .weak I2C4_ER_IRQHandler + .thumb_set I2C4_ER_IRQHandler,Default_Handler + + .weak SPDIF_RX_IRQHandler + .thumb_set SPDIF_RX_IRQHandler,Default_Handler + + diff --git a/vcu-setup-script.sh b/vcu-setup-script.sh old mode 100644 new mode 100755 index 7d9de35e..ff03034f --- a/vcu-setup-script.sh +++ b/vcu-setup-script.sh @@ -1,22 +1,36 @@ #!/bin/bash -sudo apt update && sudo apt upgrade -mkdir sufst -cd sufst -git clone https://github.com/sufst/vcu -sudo apt install gcc-arm-none-eabi -sudo apt install stlink-tools +set -ex -cd vcu +echo "Installing dependencies" +sudo apt-get update +sudo apt-get install -y gcc-arm-none-eabi stlink-tools python3-pip clang-format + +# If repo already got cloned then skip +if ! [ -f vcu-setup-script.sh ]; then + git clone https://github.com/sufst/vcu sufst-vcu + cd sufst-vcu +else + git pull +fi + +echo "Initialising submodules" git submodule init git submodule update -sudo apt install python3-pip +echo "Setting up venv" python3 -m venv .venv source .venv/bin/activate python3 -m pip install ccdgen make -s ccd +echo "Setting up Trunk" +curl https://get.trunk.io -fsSL | bash +trunk init || echo "trunk already initialised, skipping" +trunk check + +echo + echo "Ensure that Visual Studio Code is installed on Windows!" echo "Then install the WSL extension" -echo "once complete run 'code .' in wsl \ No newline at end of file +echo "once complete run 'code .' in wsl